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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_ll_rcc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l4xx_ll_rcc.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of RCC LL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L4xx_LL_RCC_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L4xx_LL_RCC_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	45	#include "stm32l4xx.h"
AnnaBridge	189:f392fc9709a3	46
AnnaBridge	189:f392fc9709a3	47	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	189:f392fc9709a3	48	* @{
AnnaBridge	189:f392fc9709a3	49	*/
AnnaBridge	189:f392fc9709a3	50
AnnaBridge	189:f392fc9709a3	51	#if defined(RCC)
AnnaBridge	189:f392fc9709a3	52
AnnaBridge	189:f392fc9709a3	53	/** @defgroup RCC_LL RCC
AnnaBridge	189:f392fc9709a3	54	* @{
AnnaBridge	189:f392fc9709a3	55	*/
AnnaBridge	189:f392fc9709a3	56
AnnaBridge	189:f392fc9709a3	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	59	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
AnnaBridge	189:f392fc9709a3	60	* @{
AnnaBridge	189:f392fc9709a3	61	*/
AnnaBridge	189:f392fc9709a3	62
AnnaBridge	189:f392fc9709a3	63	#if defined(RCC_CCIPR2_PLLSAI2DIVR)
AnnaBridge	189:f392fc9709a3	64	static const uint8_t aRCC_PLLSAI2DIVRPrescTable[4] = {2, 4, 8, 16};
AnnaBridge	189:f392fc9709a3	65	#endif /* RCC_CCIPR2_PLLSAI2DIVR */
AnnaBridge	189:f392fc9709a3	66
AnnaBridge	189:f392fc9709a3	67	/**
AnnaBridge	189:f392fc9709a3	68	* @}
AnnaBridge	189:f392fc9709a3	69	*/
AnnaBridge	189:f392fc9709a3	70
AnnaBridge	189:f392fc9709a3	71	/* Private constants ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	72	/** @defgroup RCC_LL_Private_Constants RCC Private Constants
AnnaBridge	189:f392fc9709a3	73	* @{
AnnaBridge	189:f392fc9709a3	74	*/
AnnaBridge	189:f392fc9709a3	75	/* Defines used to perform offsets*/
AnnaBridge	189:f392fc9709a3	76	/* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
AnnaBridge	189:f392fc9709a3	77	#define RCC_OFFSET_CCIPR 0U
AnnaBridge	189:f392fc9709a3	78	#define RCC_OFFSET_CCIPR2 0x14U
AnnaBridge	189:f392fc9709a3	79
AnnaBridge	189:f392fc9709a3	80	/**
AnnaBridge	189:f392fc9709a3	81	* @}
AnnaBridge	189:f392fc9709a3	82	*/
AnnaBridge	189:f392fc9709a3	83
AnnaBridge	189:f392fc9709a3	84	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	85	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	86	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
AnnaBridge	189:f392fc9709a3	87	* @{
AnnaBridge	189:f392fc9709a3	88	*/
AnnaBridge	189:f392fc9709a3	89	/**
AnnaBridge	189:f392fc9709a3	90	* @}
AnnaBridge	189:f392fc9709a3	91	*/
AnnaBridge	189:f392fc9709a3	92	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	189:f392fc9709a3	93
AnnaBridge	189:f392fc9709a3	94	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	95	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	96	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
AnnaBridge	189:f392fc9709a3	97	* @{
AnnaBridge	189:f392fc9709a3	98	*/
AnnaBridge	189:f392fc9709a3	99
AnnaBridge	189:f392fc9709a3	100	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
AnnaBridge	189:f392fc9709a3	101	* @{
AnnaBridge	189:f392fc9709a3	102	*/
AnnaBridge	189:f392fc9709a3	103
AnnaBridge	189:f392fc9709a3	104	/**
AnnaBridge	189:f392fc9709a3	105	* @brief RCC Clocks Frequency Structure
AnnaBridge	189:f392fc9709a3	106	*/
AnnaBridge	189:f392fc9709a3	107	typedef struct
AnnaBridge	189:f392fc9709a3	108	{
AnnaBridge	189:f392fc9709a3	109	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
AnnaBridge	189:f392fc9709a3	110	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
AnnaBridge	189:f392fc9709a3	111	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
AnnaBridge	189:f392fc9709a3	112	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
AnnaBridge	189:f392fc9709a3	113	} LL_RCC_ClocksTypeDef;
AnnaBridge	189:f392fc9709a3	114
AnnaBridge	189:f392fc9709a3	115	/**
AnnaBridge	189:f392fc9709a3	116	* @}
AnnaBridge	189:f392fc9709a3	117	*/
AnnaBridge	189:f392fc9709a3	118
AnnaBridge	189:f392fc9709a3	119	/**
AnnaBridge	189:f392fc9709a3	120	* @}
AnnaBridge	189:f392fc9709a3	121	*/
AnnaBridge	189:f392fc9709a3	122	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	123
AnnaBridge	189:f392fc9709a3	124	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	125	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
AnnaBridge	189:f392fc9709a3	126	* @{
AnnaBridge	189:f392fc9709a3	127	*/
AnnaBridge	189:f392fc9709a3	128
AnnaBridge	189:f392fc9709a3	129	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
AnnaBridge	189:f392fc9709a3	130	* @brief Defines used to adapt values of different oscillators
AnnaBridge	189:f392fc9709a3	131	* @note These values could be modified in the user environment according to
AnnaBridge	189:f392fc9709a3	132	* HW set-up.
AnnaBridge	189:f392fc9709a3	133	* @{
AnnaBridge	189:f392fc9709a3	134	*/
AnnaBridge	189:f392fc9709a3	135	#if !defined (HSE_VALUE)
AnnaBridge	189:f392fc9709a3	136	#define HSE_VALUE 8000000U /!< Value of the HSE oscillator in Hz /
AnnaBridge	189:f392fc9709a3	137	#endif /* HSE_VALUE */
AnnaBridge	189:f392fc9709a3	138
AnnaBridge	189:f392fc9709a3	139	#if !defined (HSI_VALUE)
AnnaBridge	189:f392fc9709a3	140	#define HSI_VALUE 16000000U /!< Value of the HSI oscillator in Hz /
AnnaBridge	189:f392fc9709a3	141	#endif /* HSI_VALUE */
AnnaBridge	189:f392fc9709a3	142
AnnaBridge	189:f392fc9709a3	143	#if !defined (LSE_VALUE)
AnnaBridge	189:f392fc9709a3	144	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
AnnaBridge	189:f392fc9709a3	145	#endif /* LSE_VALUE */
AnnaBridge	189:f392fc9709a3	146
AnnaBridge	189:f392fc9709a3	147	#if !defined (LSI_VALUE)
AnnaBridge	189:f392fc9709a3	148	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
AnnaBridge	189:f392fc9709a3	149	#endif /* LSI_VALUE */
AnnaBridge	189:f392fc9709a3	150	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	151
AnnaBridge	189:f392fc9709a3	152	#if !defined (HSI48_VALUE)
AnnaBridge	189:f392fc9709a3	153	#define HSI48_VALUE 48000000U /!< Value of the HSI48 oscillator in Hz /
AnnaBridge	189:f392fc9709a3	154	#endif /* HSI48_VALUE */
AnnaBridge	189:f392fc9709a3	155	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	156	/**
AnnaBridge	189:f392fc9709a3	157	* @}
AnnaBridge	189:f392fc9709a3	158	*/
AnnaBridge	189:f392fc9709a3	159
AnnaBridge	189:f392fc9709a3	160	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	189:f392fc9709a3	161	* @brief Flags defines which can be used with LL_RCC_WriteReg function
AnnaBridge	189:f392fc9709a3	162	* @{
AnnaBridge	189:f392fc9709a3	163	*/
AnnaBridge	189:f392fc9709a3	164	#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /!< LSI Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	165	#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /!< LSE Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	166	#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /!< MSI Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	167	#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /!< HSI Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	168	#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /!< HSE Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	169	#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /!< PLL Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	170	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	171	#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /!< HSI48 Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	172	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	173	#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /!< PLLSAI1 Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	174	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	189:f392fc9709a3	175	#define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /!< PLLSAI2 Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	176	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	189:f392fc9709a3	177	#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /!< LSE Clock Security System Interrupt Clear /
AnnaBridge	189:f392fc9709a3	178	#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /!< Clock Security System Interrupt Clear /
AnnaBridge	189:f392fc9709a3	179	/**
AnnaBridge	189:f392fc9709a3	180	* @}
AnnaBridge	189:f392fc9709a3	181	*/
AnnaBridge	189:f392fc9709a3	182
AnnaBridge	189:f392fc9709a3	183	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	189:f392fc9709a3	184	* @brief Flags defines which can be used with LL_RCC_ReadReg function
AnnaBridge	189:f392fc9709a3	185	* @{
AnnaBridge	189:f392fc9709a3	186	*/
AnnaBridge	189:f392fc9709a3	187	#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /!< LSI Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	188	#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /!< LSE Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	189	#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /!< MSI Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	190	#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /!< HSI Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	191	#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /!< HSE Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	192	#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /!< PLL Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	193	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	194	#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	195	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	196	#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /!< PLLSAI1 Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	197	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	189:f392fc9709a3	198	#define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /!< PLLSAI2 Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	199	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	189:f392fc9709a3	200	#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /!< LSE Clock Security System Interrupt flag /
AnnaBridge	189:f392fc9709a3	201	#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /!< Clock Security System Interrupt flag /
AnnaBridge	189:f392fc9709a3	202	#define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /!< Firewall reset flag /
AnnaBridge	189:f392fc9709a3	203	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
AnnaBridge	189:f392fc9709a3	204	#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /!< OBL reset flag /
AnnaBridge	189:f392fc9709a3	205	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
AnnaBridge	189:f392fc9709a3	206	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
AnnaBridge	189:f392fc9709a3	207	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
AnnaBridge	189:f392fc9709a3	208	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
AnnaBridge	189:f392fc9709a3	209	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /!< BOR reset flag /
AnnaBridge	189:f392fc9709a3	210	/**
AnnaBridge	189:f392fc9709a3	211	* @}
AnnaBridge	189:f392fc9709a3	212	*/
AnnaBridge	189:f392fc9709a3	213
AnnaBridge	189:f392fc9709a3	214	/** @defgroup RCC_LL_EC_IT IT Defines
AnnaBridge	189:f392fc9709a3	215	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
AnnaBridge	189:f392fc9709a3	216	* @{
AnnaBridge	189:f392fc9709a3	217	*/
AnnaBridge	189:f392fc9709a3	218	#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /!< LSI Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	219	#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /!< LSE Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	220	#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /!< MSI Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	221	#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /!< HSI Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	222	#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /!< HSE Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	223	#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /!< PLL Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	224	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	225	#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /!< HSI48 Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	226	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	227	#define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /!< PLLSAI1 Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	228	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	189:f392fc9709a3	229	#define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /!< PLLSAI2 Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	230	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	189:f392fc9709a3	231	#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /!< LSE CSS Interrupt Enable /
AnnaBridge	189:f392fc9709a3	232	/**
AnnaBridge	189:f392fc9709a3	233	* @}
AnnaBridge	189:f392fc9709a3	234	*/
AnnaBridge	189:f392fc9709a3	235
AnnaBridge	189:f392fc9709a3	236	/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
AnnaBridge	189:f392fc9709a3	237	* @{
AnnaBridge	189:f392fc9709a3	238	*/
AnnaBridge	189:f392fc9709a3	239	#define LL_RCC_LSEDRIVE_LOW 0x00000000U /!< Xtal mode lower driving capability /
AnnaBridge	189:f392fc9709a3	240	#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /!< Xtal mode medium low driving capability /
AnnaBridge	189:f392fc9709a3	241	#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /!< Xtal mode medium high driving capability /
AnnaBridge	189:f392fc9709a3	242	#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
AnnaBridge	189:f392fc9709a3	243	/**
AnnaBridge	189:f392fc9709a3	244	* @}
AnnaBridge	189:f392fc9709a3	245	*/
AnnaBridge	189:f392fc9709a3	246
AnnaBridge	189:f392fc9709a3	247	/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
AnnaBridge	189:f392fc9709a3	248	* @{
AnnaBridge	189:f392fc9709a3	249	*/
AnnaBridge	189:f392fc9709a3	250	#define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /!< MSI = 100 KHz /
AnnaBridge	189:f392fc9709a3	251	#define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /!< MSI = 200 KHz /
AnnaBridge	189:f392fc9709a3	252	#define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /!< MSI = 400 KHz /
AnnaBridge	189:f392fc9709a3	253	#define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /!< MSI = 800 KHz /
AnnaBridge	189:f392fc9709a3	254	#define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /!< MSI = 1 MHz /
AnnaBridge	189:f392fc9709a3	255	#define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /!< MSI = 2 MHz /
AnnaBridge	189:f392fc9709a3	256	#define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /!< MSI = 4 MHz /
AnnaBridge	189:f392fc9709a3	257	#define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /!< MSI = 8 MHz /
AnnaBridge	189:f392fc9709a3	258	#define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /!< MSI = 16 MHz /
AnnaBridge	189:f392fc9709a3	259	#define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /!< MSI = 24 MHz /
AnnaBridge	189:f392fc9709a3	260	#define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /!< MSI = 32 MHz /
AnnaBridge	189:f392fc9709a3	261	#define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /!< MSI = 48 MHz /
AnnaBridge	189:f392fc9709a3	262	/**
AnnaBridge	189:f392fc9709a3	263	* @}
AnnaBridge	189:f392fc9709a3	264	*/
AnnaBridge	189:f392fc9709a3	265
AnnaBridge	189:f392fc9709a3	266	/** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
AnnaBridge	189:f392fc9709a3	267	* @{
AnnaBridge	189:f392fc9709a3	268	*/
AnnaBridge	189:f392fc9709a3	269	#define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /!< MSI = 1 MHz /
AnnaBridge	189:f392fc9709a3	270	#define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /!< MSI = 2 MHz /
AnnaBridge	189:f392fc9709a3	271	#define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /!< MSI = 4 MHz /
AnnaBridge	189:f392fc9709a3	272	#define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /!< MSI = 8 MHz /
AnnaBridge	189:f392fc9709a3	273	/**
AnnaBridge	189:f392fc9709a3	274	* @}
AnnaBridge	189:f392fc9709a3	275	*/
AnnaBridge	189:f392fc9709a3	276
AnnaBridge	189:f392fc9709a3	277	/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
AnnaBridge	189:f392fc9709a3	278	* @{
AnnaBridge	189:f392fc9709a3	279	*/
AnnaBridge	189:f392fc9709a3	280	#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /!< LSI selection for low speed clock /
AnnaBridge	189:f392fc9709a3	281	#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /!< LSE selection for low speed clock /
AnnaBridge	189:f392fc9709a3	282	/**
AnnaBridge	189:f392fc9709a3	283	* @}
AnnaBridge	189:f392fc9709a3	284	*/
AnnaBridge	189:f392fc9709a3	285
AnnaBridge	189:f392fc9709a3	286	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
AnnaBridge	189:f392fc9709a3	287	* @{
AnnaBridge	189:f392fc9709a3	288	*/
AnnaBridge	189:f392fc9709a3	289	#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
AnnaBridge	189:f392fc9709a3	290	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
AnnaBridge	189:f392fc9709a3	291	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
AnnaBridge	189:f392fc9709a3	292	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
AnnaBridge	189:f392fc9709a3	293	/**
AnnaBridge	189:f392fc9709a3	294	* @}
AnnaBridge	189:f392fc9709a3	295	*/
AnnaBridge	189:f392fc9709a3	296
AnnaBridge	189:f392fc9709a3	297	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
AnnaBridge	189:f392fc9709a3	298	* @{
AnnaBridge	189:f392fc9709a3	299	*/
AnnaBridge	189:f392fc9709a3	300	#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
AnnaBridge	189:f392fc9709a3	301	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	189:f392fc9709a3	302	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	189:f392fc9709a3	303	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	189:f392fc9709a3	304	/**
AnnaBridge	189:f392fc9709a3	305	* @}
AnnaBridge	189:f392fc9709a3	306	*/
AnnaBridge	189:f392fc9709a3	307
AnnaBridge	189:f392fc9709a3	308	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
AnnaBridge	189:f392fc9709a3	309	* @{
AnnaBridge	189:f392fc9709a3	310	*/
AnnaBridge	189:f392fc9709a3	311	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	189:f392fc9709a3	312	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	189:f392fc9709a3	313	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	189:f392fc9709a3	314	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	189:f392fc9709a3	315	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	189:f392fc9709a3	316	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	189:f392fc9709a3	317	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	189:f392fc9709a3	318	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	189:f392fc9709a3	319	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	189:f392fc9709a3	320	/**
AnnaBridge	189:f392fc9709a3	321	* @}
AnnaBridge	189:f392fc9709a3	322	*/
AnnaBridge	189:f392fc9709a3	323
AnnaBridge	189:f392fc9709a3	324	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
AnnaBridge	189:f392fc9709a3	325	* @{
AnnaBridge	189:f392fc9709a3	326	*/
AnnaBridge	189:f392fc9709a3	327	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	189:f392fc9709a3	328	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	189:f392fc9709a3	329	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	189:f392fc9709a3	330	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	189:f392fc9709a3	331	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	189:f392fc9709a3	332	/**
AnnaBridge	189:f392fc9709a3	333	* @}
AnnaBridge	189:f392fc9709a3	334	*/
AnnaBridge	189:f392fc9709a3	335
AnnaBridge	189:f392fc9709a3	336	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
AnnaBridge	189:f392fc9709a3	337	* @{
AnnaBridge	189:f392fc9709a3	338	*/
AnnaBridge	189:f392fc9709a3	339	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
AnnaBridge	189:f392fc9709a3	340	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
AnnaBridge	189:f392fc9709a3	341	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
AnnaBridge	189:f392fc9709a3	342	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
AnnaBridge	189:f392fc9709a3	343	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
AnnaBridge	189:f392fc9709a3	344	/**
AnnaBridge	189:f392fc9709a3	345	* @}
AnnaBridge	189:f392fc9709a3	346	*/
AnnaBridge	189:f392fc9709a3	347
AnnaBridge	189:f392fc9709a3	348	/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
AnnaBridge	189:f392fc9709a3	349	* @{
AnnaBridge	189:f392fc9709a3	350	*/
AnnaBridge	189:f392fc9709a3	351	#define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /!< MSI selection after wake-up from STOP /
AnnaBridge	189:f392fc9709a3	352	#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
AnnaBridge	189:f392fc9709a3	353	/**
AnnaBridge	189:f392fc9709a3	354	* @}
AnnaBridge	189:f392fc9709a3	355	*/
AnnaBridge	189:f392fc9709a3	356
AnnaBridge	189:f392fc9709a3	357	/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
AnnaBridge	189:f392fc9709a3	358	* @{
AnnaBridge	189:f392fc9709a3	359	*/
AnnaBridge	189:f392fc9709a3	360	#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /!< MCO output disabled, no clock on MCO /
AnnaBridge	189:f392fc9709a3	361	#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /!< SYSCLK selection as MCO1 source /
AnnaBridge	189:f392fc9709a3	362	#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /!< MSI selection as MCO1 source /
AnnaBridge	189:f392fc9709a3	363	#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1) /!< HSI16 selection as MCO1 source /
AnnaBridge	189:f392fc9709a3	364	#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /!< HSE selection as MCO1 source /
AnnaBridge	189:f392fc9709a3	365	#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2) /!< Main PLL selection as MCO1 source /
AnnaBridge	189:f392fc9709a3	366	#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSI selection as MCO1 source /
AnnaBridge	189:f392fc9709a3	367	#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSE selection as MCO1 source /
AnnaBridge	189:f392fc9709a3	368	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	369	#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /!< HSI48 selection as MCO1 source /
AnnaBridge	189:f392fc9709a3	370	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	371	/**
AnnaBridge	189:f392fc9709a3	372	* @}
AnnaBridge	189:f392fc9709a3	373	*/
AnnaBridge	189:f392fc9709a3	374
AnnaBridge	189:f392fc9709a3	375	/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
AnnaBridge	189:f392fc9709a3	376	* @{
AnnaBridge	189:f392fc9709a3	377	*/
AnnaBridge	189:f392fc9709a3	378	#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /!< MCO not divided /
AnnaBridge	189:f392fc9709a3	379	#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO divided by 2 /
AnnaBridge	189:f392fc9709a3	380	#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO divided by 4 /
AnnaBridge	189:f392fc9709a3	381	#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO divided by 8 /
AnnaBridge	189:f392fc9709a3	382	#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO divided by 16 /
AnnaBridge	189:f392fc9709a3	383	/**
AnnaBridge	189:f392fc9709a3	384	* @}
AnnaBridge	189:f392fc9709a3	385	*/
AnnaBridge	189:f392fc9709a3	386
AnnaBridge	189:f392fc9709a3	387	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	388	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
AnnaBridge	189:f392fc9709a3	389	* @{
AnnaBridge	189:f392fc9709a3	390	*/
AnnaBridge	189:f392fc9709a3	391	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
AnnaBridge	189:f392fc9709a3	392	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
AnnaBridge	189:f392fc9709a3	393	/**
AnnaBridge	189:f392fc9709a3	394	* @}
AnnaBridge	189:f392fc9709a3	395	*/
AnnaBridge	189:f392fc9709a3	396	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	397
AnnaBridge	189:f392fc9709a3	398	/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
AnnaBridge	189:f392fc9709a3	399	* @{
AnnaBridge	189:f392fc9709a3	400	*/
AnnaBridge	189:f392fc9709a3	401	#define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /!< PCLK2 clock used as USART1 clock source /
AnnaBridge	189:f392fc9709a3	402	#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL_0) /!< SYSCLK clock used as USART1 clock source /
AnnaBridge	189:f392fc9709a3	403	#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL_1) /!< HSI clock used as USART1 clock source /
AnnaBridge	189:f392fc9709a3	404	#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL) /!< LSE clock used as USART1 clock source /
AnnaBridge	189:f392fc9709a3	405	#define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /!< PCLK1 clock used as USART2 clock source /
AnnaBridge	189:f392fc9709a3	406	#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL_0) /!< SYSCLK clock used as USART2 clock source /
AnnaBridge	189:f392fc9709a3	407	#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL_1) /!< HSI clock used as USART2 clock source /
AnnaBridge	189:f392fc9709a3	408	#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL) /!< LSE clock used as USART2 clock source /
AnnaBridge	189:f392fc9709a3	409	#if defined(RCC_CCIPR_USART3SEL)
AnnaBridge	189:f392fc9709a3	410	#define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /!< PCLK1 clock used as USART3 clock source /
AnnaBridge	189:f392fc9709a3	411	#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL_0) /!< SYSCLK clock used as USART3 clock source /
AnnaBridge	189:f392fc9709a3	412	#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL_1) /!< HSI clock used as USART3 clock source /
AnnaBridge	189:f392fc9709a3	413	#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL) /!< LSE clock used as USART3 clock source /
AnnaBridge	189:f392fc9709a3	414	#endif /* RCC_CCIPR_USART3SEL */
AnnaBridge	189:f392fc9709a3	415	/**
AnnaBridge	189:f392fc9709a3	416	* @}
AnnaBridge	189:f392fc9709a3	417	*/
AnnaBridge	189:f392fc9709a3	418
AnnaBridge	189:f392fc9709a3	419	#if defined(RCC_CCIPR_UART4SEL) \|\| defined(RCC_CCIPR_UART5SEL)
AnnaBridge	189:f392fc9709a3	420	/** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
AnnaBridge	189:f392fc9709a3	421	* @{
AnnaBridge	189:f392fc9709a3	422	*/
AnnaBridge	189:f392fc9709a3	423	#if defined(RCC_CCIPR_UART4SEL)
AnnaBridge	189:f392fc9709a3	424	#define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /!< PCLK1 clock used as UART4 clock source /
AnnaBridge	189:f392fc9709a3	425	#define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) \| RCC_CCIPR_UART4SEL_0) /!< SYSCLK clock used as UART4 clock source /
AnnaBridge	189:f392fc9709a3	426	#define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) \| RCC_CCIPR_UART4SEL_1) /!< HSI clock used as UART4 clock source /
AnnaBridge	189:f392fc9709a3	427	#define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) \| RCC_CCIPR_UART4SEL) /!< LSE clock used as UART4 clock source /
AnnaBridge	189:f392fc9709a3	428	#endif /* RCC_CCIPR_UART4SEL */
AnnaBridge	189:f392fc9709a3	429	#if defined(RCC_CCIPR_UART5SEL)
AnnaBridge	189:f392fc9709a3	430	#define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /!< PCLK1 clock used as UART5 clock source /
AnnaBridge	189:f392fc9709a3	431	#define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) \| RCC_CCIPR_UART5SEL_0) /!< SYSCLK clock used as UART5 clock source /
AnnaBridge	189:f392fc9709a3	432	#define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) \| RCC_CCIPR_UART5SEL_1) /!< HSI clock used as UART5 clock source /
AnnaBridge	189:f392fc9709a3	433	#define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) \| RCC_CCIPR_UART5SEL) /!< LSE clock used as UART5 clock source /
AnnaBridge	189:f392fc9709a3	434	#endif /* RCC_CCIPR_UART5SEL */
AnnaBridge	189:f392fc9709a3	435	/**
AnnaBridge	189:f392fc9709a3	436	* @}
AnnaBridge	189:f392fc9709a3	437	*/
AnnaBridge	189:f392fc9709a3	438	#endif /* RCC_CCIPR_UART4SEL \|\| RCC_CCIPR_UART5SEL */
AnnaBridge	189:f392fc9709a3	439
AnnaBridge	189:f392fc9709a3	440	/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
AnnaBridge	189:f392fc9709a3	441	* @{
AnnaBridge	189:f392fc9709a3	442	*/
AnnaBridge	189:f392fc9709a3	443	#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as LPUART1 clock source /
AnnaBridge	189:f392fc9709a3	444	#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /!< SYSCLK clock used as LPUART1 clock source /
AnnaBridge	189:f392fc9709a3	445	#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /!< HSI clock used as LPUART1 clock source /
AnnaBridge	189:f392fc9709a3	446	#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /!< LSE clock used as LPUART1 clock source /
AnnaBridge	189:f392fc9709a3	447	/**
AnnaBridge	189:f392fc9709a3	448	* @}
AnnaBridge	189:f392fc9709a3	449	*/
AnnaBridge	189:f392fc9709a3	450
AnnaBridge	189:f392fc9709a3	451	/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
AnnaBridge	189:f392fc9709a3	452	* @{
AnnaBridge	189:f392fc9709a3	453	*/
AnnaBridge	189:f392fc9709a3	454	#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U)) /!< PCLK1 clock used as I2C1 clock source /
AnnaBridge	189:f392fc9709a3	455	#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /!< SYSCLK clock used as I2C1 clock source /
AnnaBridge	189:f392fc9709a3	456	#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /!< HSI clock used as I2C1 clock source /
AnnaBridge	189:f392fc9709a3	457	#if defined(RCC_CCIPR_I2C2SEL)
AnnaBridge	189:f392fc9709a3	458	#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U)) /!< PCLK1 clock used as I2C2 clock source /
AnnaBridge	189:f392fc9709a3	459	#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /!< SYSCLK clock used as I2C2 clock source /
AnnaBridge	189:f392fc9709a3	460	#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /!< HSI clock used as I2C2 clock source /
AnnaBridge	189:f392fc9709a3	461	#endif /* RCC_CCIPR_I2C2SEL */
AnnaBridge	189:f392fc9709a3	462	#define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U)) /!< PCLK1 clock used as I2C3 clock source /
AnnaBridge	189:f392fc9709a3	463	#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /!< SYSCLK clock used as I2C3 clock source /
AnnaBridge	189:f392fc9709a3	464	#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /!< HSI clock used as I2C3 clock source /
AnnaBridge	189:f392fc9709a3	465	#if defined(RCC_CCIPR2_I2C4SEL)
AnnaBridge	189:f392fc9709a3	466	#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /!< PCLK1 clock used as I2C4 clock source /
AnnaBridge	189:f392fc9709a3	467	#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U) \| (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /!< SYSCLK clock used as I2C4 clock source /
AnnaBridge	189:f392fc9709a3	468	#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U) \| (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /!< HSI clock used as I2C4 clock source /
AnnaBridge	189:f392fc9709a3	469	#endif /* RCC_CCIPR2_I2C4SEL */
AnnaBridge	189:f392fc9709a3	470	/**
AnnaBridge	189:f392fc9709a3	471	* @}
AnnaBridge	189:f392fc9709a3	472	*/
AnnaBridge	189:f392fc9709a3	473
AnnaBridge	189:f392fc9709a3	474	/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
AnnaBridge	189:f392fc9709a3	475	* @{
AnnaBridge	189:f392fc9709a3	476	*/
AnnaBridge	189:f392fc9709a3	477	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM1SEL /!< PCLK1 clock used as LPTIM1 clock source /
AnnaBridge	189:f392fc9709a3	478	#define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /!< LSI clock used as LPTIM1 clock source /
AnnaBridge	189:f392fc9709a3	479	#define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /!< HSI clock used as LPTIM1 clock source /
AnnaBridge	189:f392fc9709a3	480	#define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL >> 16U)) /!< LSE clock used as LPTIM1 clock source /
AnnaBridge	189:f392fc9709a3	481	#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM2SEL /!< PCLK1 clock used as LPTIM2 clock source /
AnnaBridge	189:f392fc9709a3	482	#define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /!< LSI clock used as LPTIM2 clock source /
AnnaBridge	189:f392fc9709a3	483	#define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /!< HSI clock used as LPTIM2 clock source /
AnnaBridge	189:f392fc9709a3	484	#define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL >> 16U)) /!< LSE clock used as LPTIM2 clock source /
AnnaBridge	189:f392fc9709a3	485	/**
AnnaBridge	189:f392fc9709a3	486	* @}
AnnaBridge	189:f392fc9709a3	487	*/
AnnaBridge	189:f392fc9709a3	488
AnnaBridge	189:f392fc9709a3	489	/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
AnnaBridge	189:f392fc9709a3	490	* @{
AnnaBridge	189:f392fc9709a3	491	*/
AnnaBridge	189:f392fc9709a3	492	#if defined(RCC_CCIPR2_SAI1SEL)
AnnaBridge	189:f392fc9709a3	493	#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR2_SAI1SEL << 16U) /!< PLL clock used as SAI1 clock source /
AnnaBridge	189:f392fc9709a3	494	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI1SEL << 16U) \| RCC_CCIPR2_SAI1SEL_0) /!< PLLSAI1 clock used as SAI1 clock source /
AnnaBridge	189:f392fc9709a3	495	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) \| RCC_CCIPR2_SAI1SEL_1) /!< PLLSAI2 clock used as SAI1 clock source /
AnnaBridge	189:f392fc9709a3	496	#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) \| RCC_CCIPR2_SAI1SEL_2) /!< HSI clock used as SAI1 clock source /
AnnaBridge	189:f392fc9709a3	497	#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) \| (RCC_CCIPR2_SAI1SEL_1 \| RCC_CCIPR2_SAI1SEL_0)) /!< External input clock used as SAI1 clock source /
AnnaBridge	189:f392fc9709a3	498	#else
AnnaBridge	189:f392fc9709a3	499	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /!< PLLSAI1 clock used as SAI1 clock source /
AnnaBridge	189:f392fc9709a3	500	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	189:f392fc9709a3	501	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL_0 >> 16U)) /!< PLLSAI2 clock used as SAI1 clock source /
AnnaBridge	189:f392fc9709a3	502	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	189:f392fc9709a3	503	#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL_1 >> 16U)) /!< PLL clock used as SAI1 clock source /
AnnaBridge	189:f392fc9709a3	504	#define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL >> 16U)) /!< External input clock used as SAI1 clock source /
AnnaBridge	189:f392fc9709a3	505	#endif /* RCC_CCIPR2_SAI1SEL */
AnnaBridge	189:f392fc9709a3	506
AnnaBridge	189:f392fc9709a3	507	#if defined(RCC_CCIPR2_SAI2SEL)
AnnaBridge	189:f392fc9709a3	508	#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR2_SAI2SEL << 16U) /!< PLL clock used as SAI2 clock source /
AnnaBridge	189:f392fc9709a3	509	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI2SEL << 16U) \| RCC_CCIPR2_SAI2SEL_0) /!< PLLSAI1 clock used as SAI2 clock source /
AnnaBridge	189:f392fc9709a3	510	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) \| RCC_CCIPR2_SAI2SEL_1) /!< PLLSAI2 clock used as SAI2 clock source /
AnnaBridge	189:f392fc9709a3	511	#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) \| RCC_CCIPR2_SAI2SEL_2) /!< HSI clock used as SAI2 clock source /
AnnaBridge	189:f392fc9709a3	512	#define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) \| (RCC_CCIPR2_SAI2SEL_1 \| RCC_CCIPR2_SAI2SEL_0)) /!< External input clock used as SAI2 clock source /
AnnaBridge	189:f392fc9709a3	513	#elif defined(RCC_CCIPR_SAI2SEL)
AnnaBridge	189:f392fc9709a3	514	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /!< PLLSAI1 clock used as SAI2 clock source /
AnnaBridge	189:f392fc9709a3	515	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	189:f392fc9709a3	516	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL_0 >> 16U)) /!< PLLSAI2 clock used as SAI2 clock source /
AnnaBridge	189:f392fc9709a3	517	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	189:f392fc9709a3	518	#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL_1 >> 16U)) /!< PLL clock used as SAI2 clock source /
AnnaBridge	189:f392fc9709a3	519	#define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL >> 16U)) /!< External input clock used as SAI2 clock source /
AnnaBridge	189:f392fc9709a3	520	#endif /* RCC_CCIPR2_SAI2SEL */
AnnaBridge	189:f392fc9709a3	521	/**
AnnaBridge	189:f392fc9709a3	522	* @}
AnnaBridge	189:f392fc9709a3	523	*/
AnnaBridge	189:f392fc9709a3	524
AnnaBridge	189:f392fc9709a3	525	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	189:f392fc9709a3	526	/** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection
AnnaBridge	189:f392fc9709a3	527	* @{
AnnaBridge	189:f392fc9709a3	528	*/
AnnaBridge	189:f392fc9709a3	529	#define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /!< 48MHz clock from internal multiplexor used as SDMMC1 clock source /
AnnaBridge	189:f392fc9709a3	530	#define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /!< PLLSAI3CLK clock used as SDMMC1 clock source /
AnnaBridge	189:f392fc9709a3	531	/**
AnnaBridge	189:f392fc9709a3	532	* @}
AnnaBridge	189:f392fc9709a3	533	*/
AnnaBridge	189:f392fc9709a3	534	#endif /* RCC_CCIPR2_SDMMCSEL */
AnnaBridge	189:f392fc9709a3	535
AnnaBridge	189:f392fc9709a3	536	/** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
AnnaBridge	189:f392fc9709a3	537	* @{
AnnaBridge	189:f392fc9709a3	538	*/
AnnaBridge	189:f392fc9709a3	539	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	540	#define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U /!< HSI48 clock used as SDMMC1 clock source /
AnnaBridge	189:f392fc9709a3	541	#else
AnnaBridge	189:f392fc9709a3	542	#define LL_RCC_SDMMC1_CLKSOURCE_NONE 0x00000000U /!< No clock used as SDMMC1 clock source /
AnnaBridge	189:f392fc9709a3	543	#endif
AnnaBridge	189:f392fc9709a3	544	#define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /!< PLLSAI1 clock used as SDMMC1 clock source /
AnnaBridge	189:f392fc9709a3	545	#define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /!< PLL clock used as SDMMC1 clock source /
AnnaBridge	189:f392fc9709a3	546	#define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /!< MSI clock used as SDMMC1 clock source /
AnnaBridge	189:f392fc9709a3	547	/**
AnnaBridge	189:f392fc9709a3	548	* @}
AnnaBridge	189:f392fc9709a3	549	*/
AnnaBridge	189:f392fc9709a3	550
AnnaBridge	189:f392fc9709a3	551	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
AnnaBridge	189:f392fc9709a3	552	* @{
AnnaBridge	189:f392fc9709a3	553	*/
AnnaBridge	189:f392fc9709a3	554	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	555	#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /!< HSI48 clock used as RNG clock source /
AnnaBridge	189:f392fc9709a3	556	#else
AnnaBridge	189:f392fc9709a3	557	#define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /!< No clock used as RNG clock source /
AnnaBridge	189:f392fc9709a3	558	#endif
AnnaBridge	189:f392fc9709a3	559	#define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /!< PLLSAI1 clock used as RNG clock source /
AnnaBridge	189:f392fc9709a3	560	#define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /!< PLL clock used as RNG clock source /
AnnaBridge	189:f392fc9709a3	561	#define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /!< MSI clock used as RNG clock source /
AnnaBridge	189:f392fc9709a3	562	/**
AnnaBridge	189:f392fc9709a3	563	* @}
AnnaBridge	189:f392fc9709a3	564	*/
AnnaBridge	189:f392fc9709a3	565
AnnaBridge	189:f392fc9709a3	566	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	189:f392fc9709a3	567	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
AnnaBridge	189:f392fc9709a3	568	* @{
AnnaBridge	189:f392fc9709a3	569	*/
AnnaBridge	189:f392fc9709a3	570	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	571	#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /!< HSI48 clock used as USB clock source /
AnnaBridge	189:f392fc9709a3	572	#else
AnnaBridge	189:f392fc9709a3	573	#define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /!< No clock used as USB clock source /
AnnaBridge	189:f392fc9709a3	574	#endif
AnnaBridge	189:f392fc9709a3	575	#define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /!< PLLSAI1 clock used as USB clock source /
AnnaBridge	189:f392fc9709a3	576	#define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /!< PLL clock used as USB clock source /
AnnaBridge	189:f392fc9709a3	577	#define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /!< MSI clock used as USB clock source /
AnnaBridge	189:f392fc9709a3	578	/**
AnnaBridge	189:f392fc9709a3	579	* @}
AnnaBridge	189:f392fc9709a3	580	*/
AnnaBridge	189:f392fc9709a3	581
AnnaBridge	189:f392fc9709a3	582	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	189:f392fc9709a3	583
AnnaBridge	189:f392fc9709a3	584	/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
AnnaBridge	189:f392fc9709a3	585	* @{
AnnaBridge	189:f392fc9709a3	586	*/
AnnaBridge	189:f392fc9709a3	587	#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /!< No clock used as ADC clock source /
AnnaBridge	189:f392fc9709a3	588	#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /!< PLLSAI1 clock used as ADC clock source /
AnnaBridge	189:f392fc9709a3	589	#if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC)
AnnaBridge	189:f392fc9709a3	590	#define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /!< PLLSAI2 clock used as ADC clock source /
AnnaBridge	189:f392fc9709a3	591	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	189:f392fc9709a3	592	#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /!< SYSCLK clock used as ADC clock source /
AnnaBridge	189:f392fc9709a3	593	/**
AnnaBridge	189:f392fc9709a3	594	* @}
AnnaBridge	189:f392fc9709a3	595	*/
AnnaBridge	189:f392fc9709a3	596
AnnaBridge	189:f392fc9709a3	597	#if defined(SWPMI1)
AnnaBridge	189:f392fc9709a3	598	/** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI1 clock source selection
AnnaBridge	189:f392fc9709a3	599	* @{
AnnaBridge	189:f392fc9709a3	600	*/
AnnaBridge	189:f392fc9709a3	601	#define LL_RCC_SWPMI1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 used as SWPMI1 clock source /
AnnaBridge	189:f392fc9709a3	602	#define LL_RCC_SWPMI1_CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL /!< HSI used as SWPMI1 clock source /
AnnaBridge	189:f392fc9709a3	603	/**
AnnaBridge	189:f392fc9709a3	604	* @}
AnnaBridge	189:f392fc9709a3	605	*/
AnnaBridge	189:f392fc9709a3	606	#endif /* SWPMI1 */
AnnaBridge	189:f392fc9709a3	607
AnnaBridge	189:f392fc9709a3	608	#if defined(DFSDM1_Channel0)
AnnaBridge	189:f392fc9709a3	609	#if defined(RCC_CCIPR2_ADFSDM1SEL)
AnnaBridge	189:f392fc9709a3	610	/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM1 Audio clock source selection
AnnaBridge	189:f392fc9709a3	611	* @{
AnnaBridge	189:f392fc9709a3	612	*/
AnnaBridge	189:f392fc9709a3	613	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /!< SAI1 clock used as DFSDM1 Audio clock /
AnnaBridge	189:f392fc9709a3	614	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 /!< HSI clock used as DFSDM1 Audio clock /
AnnaBridge	189:f392fc9709a3	615	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /!< MSI clock used as DFSDM1 Audio clock /
AnnaBridge	189:f392fc9709a3	616	/**
AnnaBridge	189:f392fc9709a3	617	* @}
AnnaBridge	189:f392fc9709a3	618	*/
AnnaBridge	189:f392fc9709a3	619	#endif /* RCC_CCIPR2_ADFSDM1SEL */
AnnaBridge	189:f392fc9709a3	620
AnnaBridge	189:f392fc9709a3	621	/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection
AnnaBridge	189:f392fc9709a3	622	* @{
AnnaBridge	189:f392fc9709a3	623	*/
AnnaBridge	189:f392fc9709a3	624	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	189:f392fc9709a3	625	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 used as DFSDM1 clock source /
AnnaBridge	189:f392fc9709a3	626	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL /!< SYSCLK used as DFSDM1 clock source /
AnnaBridge	189:f392fc9709a3	627	#else
AnnaBridge	189:f392fc9709a3	628	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 used as DFSDM1 clock source /
AnnaBridge	189:f392fc9709a3	629	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL /!< SYSCLK used as DFSDM1 clock source /
AnnaBridge	189:f392fc9709a3	630	#endif /* RCC_CCIPR2_DFSDM1SEL */
AnnaBridge	189:f392fc9709a3	631	/**
AnnaBridge	189:f392fc9709a3	632	* @}
AnnaBridge	189:f392fc9709a3	633	*/
AnnaBridge	189:f392fc9709a3	634	#endif /* DFSDM1_Channel0 */
AnnaBridge	189:f392fc9709a3	635
AnnaBridge	189:f392fc9709a3	636	#if defined(DSI)
AnnaBridge	189:f392fc9709a3	637	/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
AnnaBridge	189:f392fc9709a3	638	* @{
AnnaBridge	189:f392fc9709a3	639	*/
AnnaBridge	189:f392fc9709a3	640	#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /!< DSI-PHY clock used as DSI byte lane clock source /
AnnaBridge	189:f392fc9709a3	641	#define LL_RCC_DSI_CLKSOURCE_PLL RCC_CCIPR2_DSISEL /!< PLL clock used as DSI byte lane clock source /
AnnaBridge	189:f392fc9709a3	642	/**
AnnaBridge	189:f392fc9709a3	643	* @}
AnnaBridge	189:f392fc9709a3	644	*/
AnnaBridge	189:f392fc9709a3	645	#endif /* DSI */
AnnaBridge	189:f392fc9709a3	646
AnnaBridge	189:f392fc9709a3	647	#if defined(LTDC)
AnnaBridge	189:f392fc9709a3	648	/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection
AnnaBridge	189:f392fc9709a3	649	* @{
AnnaBridge	189:f392fc9709a3	650	*/
AnnaBridge	189:f392fc9709a3	651	#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 0x00000000U /!< PLLSAI2DIVR divided by 2 used as LTDC clock source /
AnnaBridge	189:f392fc9709a3	652	#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 /!< PLLSAI2DIVR divided by 4 used as LTDC clock source /
AnnaBridge	189:f392fc9709a3	653	#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 /!< PLLSAI2DIVR divided by 8 used as LTDC clock source /
AnnaBridge	189:f392fc9709a3	654	#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR /!< PLLSAI2DIVR divided by 16 used as LTDC clock source /
AnnaBridge	189:f392fc9709a3	655	/**
AnnaBridge	189:f392fc9709a3	656	* @}
AnnaBridge	189:f392fc9709a3	657	*/
AnnaBridge	189:f392fc9709a3	658	#endif /* LTDC */
AnnaBridge	189:f392fc9709a3	659
AnnaBridge	189:f392fc9709a3	660	#if defined(OCTOSPI1)
AnnaBridge	189:f392fc9709a3	661	/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
AnnaBridge	189:f392fc9709a3	662	* @{
AnnaBridge	189:f392fc9709a3	663	*/
AnnaBridge	189:f392fc9709a3	664	#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /!< SYSCLK used as OctoSPI clock source /
AnnaBridge	189:f392fc9709a3	665	#define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /!< MSI used as OctoSPI clock source /
AnnaBridge	189:f392fc9709a3	666	#define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /!< PLL used as OctoSPI clock source /
AnnaBridge	189:f392fc9709a3	667	/**
AnnaBridge	189:f392fc9709a3	668	* @}
AnnaBridge	189:f392fc9709a3	669	*/
AnnaBridge	189:f392fc9709a3	670	#endif /* OCTOSPI1 */
AnnaBridge	189:f392fc9709a3	671
AnnaBridge	189:f392fc9709a3	672	/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
AnnaBridge	189:f392fc9709a3	673	* @{
AnnaBridge	189:f392fc9709a3	674	*/
AnnaBridge	189:f392fc9709a3	675	#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /!< USART1 Clock source selection /
AnnaBridge	189:f392fc9709a3	676	#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /!< USART2 Clock source selection /
AnnaBridge	189:f392fc9709a3	677	#if defined(RCC_CCIPR_USART3SEL)
AnnaBridge	189:f392fc9709a3	678	#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /!< USART3 Clock source selection /
AnnaBridge	189:f392fc9709a3	679	#endif /* RCC_CCIPR_USART3SEL */
AnnaBridge	189:f392fc9709a3	680	/**
AnnaBridge	189:f392fc9709a3	681	* @}
AnnaBridge	189:f392fc9709a3	682	*/
AnnaBridge	189:f392fc9709a3	683
AnnaBridge	189:f392fc9709a3	684	#if defined(RCC_CCIPR_UART4SEL) \|\| defined(RCC_CCIPR_UART5SEL)
AnnaBridge	189:f392fc9709a3	685	/** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source
AnnaBridge	189:f392fc9709a3	686	* @{
AnnaBridge	189:f392fc9709a3	687	*/
AnnaBridge	189:f392fc9709a3	688	#if defined(RCC_CCIPR_UART4SEL)
AnnaBridge	189:f392fc9709a3	689	#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /!< UART4 Clock source selection /
AnnaBridge	189:f392fc9709a3	690	#endif /* RCC_CCIPR_UART4SEL */
AnnaBridge	189:f392fc9709a3	691	#if defined(RCC_CCIPR_UART5SEL)
AnnaBridge	189:f392fc9709a3	692	#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /!< UART5 Clock source selection /
AnnaBridge	189:f392fc9709a3	693	#endif /* RCC_CCIPR_UART5SEL */
AnnaBridge	189:f392fc9709a3	694	/**
AnnaBridge	189:f392fc9709a3	695	* @}
AnnaBridge	189:f392fc9709a3	696	*/
AnnaBridge	189:f392fc9709a3	697	#endif /* RCC_CCIPR_UART4SEL \|\| RCC_CCIPR_UART5SEL */
AnnaBridge	189:f392fc9709a3	698
AnnaBridge	189:f392fc9709a3	699	/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
AnnaBridge	189:f392fc9709a3	700	* @{
AnnaBridge	189:f392fc9709a3	701	*/
AnnaBridge	189:f392fc9709a3	702	#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /!< LPUART1 Clock source selection /
AnnaBridge	189:f392fc9709a3	703	/**
AnnaBridge	189:f392fc9709a3	704	* @}
AnnaBridge	189:f392fc9709a3	705	*/
AnnaBridge	189:f392fc9709a3	706
AnnaBridge	189:f392fc9709a3	707	/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
AnnaBridge	189:f392fc9709a3	708	* @{
AnnaBridge	189:f392fc9709a3	709	*/
AnnaBridge	189:f392fc9709a3	710	#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /!< I2C1 Clock source selection /
AnnaBridge	189:f392fc9709a3	711	#if defined(RCC_CCIPR_I2C2SEL)
AnnaBridge	189:f392fc9709a3	712	#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /!< I2C2 Clock source selection /
AnnaBridge	189:f392fc9709a3	713	#endif /* RCC_CCIPR_I2C2SEL */
AnnaBridge	189:f392fc9709a3	714	#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /!< I2C3 Clock source selection /
AnnaBridge	189:f392fc9709a3	715	#if defined(RCC_CCIPR2_I2C4SEL)
AnnaBridge	189:f392fc9709a3	716	#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U) \| (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /!< I2C4 Clock source selection /
AnnaBridge	189:f392fc9709a3	717	#endif /* RCC_CCIPR2_I2C4SEL */
AnnaBridge	189:f392fc9709a3	718	/**
AnnaBridge	189:f392fc9709a3	719	* @}
AnnaBridge	189:f392fc9709a3	720	*/
AnnaBridge	189:f392fc9709a3	721
AnnaBridge	189:f392fc9709a3	722	/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
AnnaBridge	189:f392fc9709a3	723	* @{
AnnaBridge	189:f392fc9709a3	724	*/
AnnaBridge	189:f392fc9709a3	725	#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /!< LPTIM1 Clock source selection /
AnnaBridge	189:f392fc9709a3	726	#define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /!< LPTIM2 Clock source selection /
AnnaBridge	189:f392fc9709a3	727	/**
AnnaBridge	189:f392fc9709a3	728	* @}
AnnaBridge	189:f392fc9709a3	729	*/
AnnaBridge	189:f392fc9709a3	730
AnnaBridge	189:f392fc9709a3	731	/** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
AnnaBridge	189:f392fc9709a3	732	* @{
AnnaBridge	189:f392fc9709a3	733	*/
AnnaBridge	189:f392fc9709a3	734	#if defined(RCC_CCIPR2_SAI1SEL)
AnnaBridge	189:f392fc9709a3	735	#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /!< SAI1 Clock source selection /
AnnaBridge	189:f392fc9709a3	736	#else
AnnaBridge	189:f392fc9709a3	737	#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /!< SAI1 Clock source selection /
AnnaBridge	189:f392fc9709a3	738	#endif /* RCC_CCIPR2_SAI1SEL */
AnnaBridge	189:f392fc9709a3	739	#if defined(RCC_CCIPR2_SAI2SEL)
AnnaBridge	189:f392fc9709a3	740	#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /!< SAI2 Clock source selection /
AnnaBridge	189:f392fc9709a3	741	#elif defined(RCC_CCIPR_SAI2SEL)
AnnaBridge	189:f392fc9709a3	742	#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /!< SAI2 Clock source selection /
AnnaBridge	189:f392fc9709a3	743	#endif /* RCC_CCIPR2_SAI2SEL */
AnnaBridge	189:f392fc9709a3	744	/**
AnnaBridge	189:f392fc9709a3	745	* @}
AnnaBridge	189:f392fc9709a3	746	*/
AnnaBridge	189:f392fc9709a3	747
AnnaBridge	189:f392fc9709a3	748	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	189:f392fc9709a3	749	/** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source
AnnaBridge	189:f392fc9709a3	750	* @{
AnnaBridge	189:f392fc9709a3	751	*/
AnnaBridge	189:f392fc9709a3	752	#define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /!< SDMMC1 Kernel Clock source selection /
AnnaBridge	189:f392fc9709a3	753	/**
AnnaBridge	189:f392fc9709a3	754	* @}
AnnaBridge	189:f392fc9709a3	755	*/
AnnaBridge	189:f392fc9709a3	756	#endif /* RCC_CCIPR2_SDMMCSEL */
AnnaBridge	189:f392fc9709a3	757
AnnaBridge	189:f392fc9709a3	758	/** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source
AnnaBridge	189:f392fc9709a3	759	* @{
AnnaBridge	189:f392fc9709a3	760	*/
AnnaBridge	189:f392fc9709a3	761	#define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /!< SDMMC1 Clock source selection /
AnnaBridge	189:f392fc9709a3	762	/**
AnnaBridge	189:f392fc9709a3	763	* @}
AnnaBridge	189:f392fc9709a3	764	*/
AnnaBridge	189:f392fc9709a3	765
AnnaBridge	189:f392fc9709a3	766	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
AnnaBridge	189:f392fc9709a3	767	* @{
AnnaBridge	189:f392fc9709a3	768	*/
AnnaBridge	189:f392fc9709a3	769	#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /!< RNG Clock source selection /
AnnaBridge	189:f392fc9709a3	770	/**
AnnaBridge	189:f392fc9709a3	771	* @}
AnnaBridge	189:f392fc9709a3	772	*/
AnnaBridge	189:f392fc9709a3	773
AnnaBridge	189:f392fc9709a3	774	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	189:f392fc9709a3	775	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
AnnaBridge	189:f392fc9709a3	776	* @{
AnnaBridge	189:f392fc9709a3	777	*/
AnnaBridge	189:f392fc9709a3	778	#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /!< USB Clock source selection /
AnnaBridge	189:f392fc9709a3	779	/**
AnnaBridge	189:f392fc9709a3	780	* @}
AnnaBridge	189:f392fc9709a3	781	*/
AnnaBridge	189:f392fc9709a3	782	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	189:f392fc9709a3	783
AnnaBridge	189:f392fc9709a3	784	/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
AnnaBridge	189:f392fc9709a3	785	* @{
AnnaBridge	189:f392fc9709a3	786	*/
AnnaBridge	189:f392fc9709a3	787	#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /!< ADC Clock source selection /
AnnaBridge	189:f392fc9709a3	788	/**
AnnaBridge	189:f392fc9709a3	789	* @}
AnnaBridge	189:f392fc9709a3	790	*/
AnnaBridge	189:f392fc9709a3	791
AnnaBridge	189:f392fc9709a3	792	#if defined(SWPMI1)
AnnaBridge	189:f392fc9709a3	793	/** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI1 get clock source
AnnaBridge	189:f392fc9709a3	794	* @{
AnnaBridge	189:f392fc9709a3	795	*/
AnnaBridge	189:f392fc9709a3	796	#define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL /!< SWPMI1 Clock source selection /
AnnaBridge	189:f392fc9709a3	797	/**
AnnaBridge	189:f392fc9709a3	798	* @}
AnnaBridge	189:f392fc9709a3	799	*/
AnnaBridge	189:f392fc9709a3	800	#endif /* SWPMI1 */
AnnaBridge	189:f392fc9709a3	801
AnnaBridge	189:f392fc9709a3	802	#if defined(DFSDM1_Channel0)
AnnaBridge	189:f392fc9709a3	803	#if defined(RCC_CCIPR2_ADFSDM1SEL)
AnnaBridge	189:f392fc9709a3	804	/** @defgroup RCC_LL_EC_DFSDM1_AUDIO Peripheral DFSDM1 Audio get clock source
AnnaBridge	189:f392fc9709a3	805	* @{
AnnaBridge	189:f392fc9709a3	806	*/
AnnaBridge	189:f392fc9709a3	807	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */
AnnaBridge	189:f392fc9709a3	808	/**
AnnaBridge	189:f392fc9709a3	809	* @}
AnnaBridge	189:f392fc9709a3	810	*/
AnnaBridge	189:f392fc9709a3	811
AnnaBridge	189:f392fc9709a3	812	#endif /* RCC_CCIPR2_ADFSDM1SEL */
AnnaBridge	189:f392fc9709a3	813	/** @defgroup RCC_LL_EC_DFSDM1 Peripheral DFSDM1 get clock source
AnnaBridge	189:f392fc9709a3	814	* @{
AnnaBridge	189:f392fc9709a3	815	*/
AnnaBridge	189:f392fc9709a3	816	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	189:f392fc9709a3	817	#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDM1SEL /!< DFSDM1 Clock source selection /
AnnaBridge	189:f392fc9709a3	818	#else
AnnaBridge	189:f392fc9709a3	819	#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /!< DFSDM1 Clock source selection /
AnnaBridge	189:f392fc9709a3	820	#endif /* RCC_CCIPR2_DFSDM1SEL */
AnnaBridge	189:f392fc9709a3	821	/**
AnnaBridge	189:f392fc9709a3	822	* @}
AnnaBridge	189:f392fc9709a3	823	*/
AnnaBridge	189:f392fc9709a3	824	#endif /* DFSDM1_Channel0 */
AnnaBridge	189:f392fc9709a3	825
AnnaBridge	189:f392fc9709a3	826	#if defined(DSI)
AnnaBridge	189:f392fc9709a3	827	/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
AnnaBridge	189:f392fc9709a3	828	* @{
AnnaBridge	189:f392fc9709a3	829	*/
AnnaBridge	189:f392fc9709a3	830	#define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSISEL /!< DSI Clock source selection /
AnnaBridge	189:f392fc9709a3	831	/**
AnnaBridge	189:f392fc9709a3	832	* @}
AnnaBridge	189:f392fc9709a3	833	*/
AnnaBridge	189:f392fc9709a3	834	#endif /* DSI */
AnnaBridge	189:f392fc9709a3	835
AnnaBridge	189:f392fc9709a3	836	#if defined(LTDC)
AnnaBridge	189:f392fc9709a3	837	/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
AnnaBridge	189:f392fc9709a3	838	* @{
AnnaBridge	189:f392fc9709a3	839	*/
AnnaBridge	189:f392fc9709a3	840	#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_PLLSAI2DIVR /!< LTDC Clock source selection /
AnnaBridge	189:f392fc9709a3	841	/**
AnnaBridge	189:f392fc9709a3	842	* @}
AnnaBridge	189:f392fc9709a3	843	*/
AnnaBridge	189:f392fc9709a3	844	#endif /* LTDC */
AnnaBridge	189:f392fc9709a3	845
AnnaBridge	189:f392fc9709a3	846	#if defined(OCTOSPI1)
AnnaBridge	189:f392fc9709a3	847	/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
AnnaBridge	189:f392fc9709a3	848	* @{
AnnaBridge	189:f392fc9709a3	849	*/
AnnaBridge	189:f392fc9709a3	850	#define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL /!< OctoSPI Clock source selection /
AnnaBridge	189:f392fc9709a3	851	/**
AnnaBridge	189:f392fc9709a3	852	* @}
AnnaBridge	189:f392fc9709a3	853	*/
AnnaBridge	189:f392fc9709a3	854	#endif /* OCTOSPI1 */
AnnaBridge	189:f392fc9709a3	855
AnnaBridge	189:f392fc9709a3	856
AnnaBridge	189:f392fc9709a3	857	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
AnnaBridge	189:f392fc9709a3	858	* @{
AnnaBridge	189:f392fc9709a3	859	*/
AnnaBridge	189:f392fc9709a3	860	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
AnnaBridge	189:f392fc9709a3	861	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
AnnaBridge	189:f392fc9709a3	862	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
AnnaBridge	189:f392fc9709a3	863	#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
AnnaBridge	189:f392fc9709a3	864	/**
AnnaBridge	189:f392fc9709a3	865	* @}
AnnaBridge	189:f392fc9709a3	866	*/
AnnaBridge	189:f392fc9709a3	867
AnnaBridge	189:f392fc9709a3	868
AnnaBridge	189:f392fc9709a3	869	/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source
AnnaBridge	189:f392fc9709a3	870	* @{
AnnaBridge	189:f392fc9709a3	871	*/
AnnaBridge	189:f392fc9709a3	872	#define LL_RCC_PLLSOURCE_NONE 0x00000000U /!< No clock /
AnnaBridge	189:f392fc9709a3	873	#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /!< MSI clock selected as PLL entry clock source /
AnnaBridge	189:f392fc9709a3	874	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI16 clock selected as PLL entry clock source /
AnnaBridge	189:f392fc9709a3	875	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
AnnaBridge	189:f392fc9709a3	876	/**
AnnaBridge	189:f392fc9709a3	877	* @}
AnnaBridge	189:f392fc9709a3	878	*/
AnnaBridge	189:f392fc9709a3	879
AnnaBridge	189:f392fc9709a3	880	/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
AnnaBridge	189:f392fc9709a3	881	* @{
AnnaBridge	189:f392fc9709a3	882	*/
AnnaBridge	189:f392fc9709a3	883	#define LL_RCC_PLLM_DIV_1 0x00000000U /!< Main PLL division factor for PLLM input by 1 /
AnnaBridge	189:f392fc9709a3	884	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 2 /
AnnaBridge	189:f392fc9709a3	885	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /!< Main PLL division factor for PLLM input by 3 /
AnnaBridge	189:f392fc9709a3	886	#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 4 /
AnnaBridge	189:f392fc9709a3	887	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /!< Main PLL division factor for PLLM input by 5 /
AnnaBridge	189:f392fc9709a3	888	#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 6 /
AnnaBridge	189:f392fc9709a3	889	#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< Main PLL division factor for PLLM input by 7 /
AnnaBridge	189:f392fc9709a3	890	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 8 /
AnnaBridge	189:f392fc9709a3	891	#if defined(RCC_PLLM_DIV_1_16_SUPPORT)
AnnaBridge	189:f392fc9709a3	892	#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3) /!< Main PLL division factor for PLLM input by 9 /
AnnaBridge	189:f392fc9709a3	893	#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 10 /
AnnaBridge	189:f392fc9709a3	894	#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< Main PLL division factor for PLLM input by 11 /
AnnaBridge	189:f392fc9709a3	895	#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 12 /
AnnaBridge	189:f392fc9709a3	896	#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< Main PLL division factor for PLLM input by 13 /
AnnaBridge	189:f392fc9709a3	897	#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 14 /
AnnaBridge	189:f392fc9709a3	898	#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< Main PLL division factor for PLLM input by 15 /
AnnaBridge	189:f392fc9709a3	899	#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 16 /
AnnaBridge	189:f392fc9709a3	900	#endif /* RCC_PLLM_DIV_1_16_SUPPORT */
AnnaBridge	189:f392fc9709a3	901	/**
AnnaBridge	189:f392fc9709a3	902	* @}
AnnaBridge	189:f392fc9709a3	903	*/
AnnaBridge	189:f392fc9709a3	904
AnnaBridge	189:f392fc9709a3	905	/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
AnnaBridge	189:f392fc9709a3	906	* @{
AnnaBridge	189:f392fc9709a3	907	*/
AnnaBridge	189:f392fc9709a3	908	#define LL_RCC_PLLR_DIV_2 0x00000000U /!< Main PLL division factor for PLLCLK (system clock) by 2 /
AnnaBridge	189:f392fc9709a3	909	#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 4 /
AnnaBridge	189:f392fc9709a3	910	#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 6 /
AnnaBridge	189:f392fc9709a3	911	#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /!< Main PLL division factor for PLLCLK (system clock) by 8 /
AnnaBridge	189:f392fc9709a3	912	/**
AnnaBridge	189:f392fc9709a3	913	* @}
AnnaBridge	189:f392fc9709a3	914	*/
AnnaBridge	189:f392fc9709a3	915
AnnaBridge	189:f392fc9709a3	916	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
AnnaBridge	189:f392fc9709a3	917	* @{
AnnaBridge	189:f392fc9709a3	918	*/
AnnaBridge	189:f392fc9709a3	919	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	920	#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 2 /
AnnaBridge	189:f392fc9709a3	921	#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 3 /
AnnaBridge	189:f392fc9709a3	922	#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 4 /
AnnaBridge	189:f392fc9709a3	923	#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 5 /
AnnaBridge	189:f392fc9709a3	924	#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 6 /
AnnaBridge	189:f392fc9709a3	925	#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 7 /
AnnaBridge	189:f392fc9709a3	926	#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 8 /
AnnaBridge	189:f392fc9709a3	927	#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 9 /
AnnaBridge	189:f392fc9709a3	928	#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 10 /
AnnaBridge	189:f392fc9709a3	929	#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 11 /
AnnaBridge	189:f392fc9709a3	930	#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 12 /
AnnaBridge	189:f392fc9709a3	931	#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 13 /
AnnaBridge	189:f392fc9709a3	932	#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 14 /
AnnaBridge	189:f392fc9709a3	933	#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 15 /
AnnaBridge	189:f392fc9709a3	934	#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 16 /
AnnaBridge	189:f392fc9709a3	935	#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 17 /
AnnaBridge	189:f392fc9709a3	936	#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 18 /
AnnaBridge	189:f392fc9709a3	937	#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 19 /
AnnaBridge	189:f392fc9709a3	938	#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 20 /
AnnaBridge	189:f392fc9709a3	939	#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 21 /
AnnaBridge	189:f392fc9709a3	940	#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 22 /
AnnaBridge	189:f392fc9709a3	941	#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 23 /
AnnaBridge	189:f392fc9709a3	942	#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 24 /
AnnaBridge	189:f392fc9709a3	943	#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 25 /
AnnaBridge	189:f392fc9709a3	944	#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 26 /
AnnaBridge	189:f392fc9709a3	945	#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 27 /
AnnaBridge	189:f392fc9709a3	946	#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 28 /
AnnaBridge	189:f392fc9709a3	947	#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 29 /
AnnaBridge	189:f392fc9709a3	948	#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 30 /
AnnaBridge	189:f392fc9709a3	949	#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 31 /
AnnaBridge	189:f392fc9709a3	950	#else
AnnaBridge	189:f392fc9709a3	951	#define LL_RCC_PLLP_DIV_7 0x00000000U /!< Main PLL division factor for PLLP output by 7 /
AnnaBridge	189:f392fc9709a3	952	#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /!< Main PLL division factor for PLLP output by 17 /
AnnaBridge	189:f392fc9709a3	953	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	189:f392fc9709a3	954	/**
AnnaBridge	189:f392fc9709a3	955	* @}
AnnaBridge	189:f392fc9709a3	956	*/
AnnaBridge	189:f392fc9709a3	957
AnnaBridge	189:f392fc9709a3	958	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
AnnaBridge	189:f392fc9709a3	959	* @{
AnnaBridge	189:f392fc9709a3	960	*/
AnnaBridge	189:f392fc9709a3	961	#define LL_RCC_PLLQ_DIV_2 0x00000000U /!< Main PLL division factor for PLLQ output by 2 /
AnnaBridge	189:f392fc9709a3	962	#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 4 /
AnnaBridge	189:f392fc9709a3	963	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 6 /
AnnaBridge	189:f392fc9709a3	964	#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /!< Main PLL division factor for PLLQ output by 8 /
AnnaBridge	189:f392fc9709a3	965	/**
AnnaBridge	189:f392fc9709a3	966	* @}
AnnaBridge	189:f392fc9709a3	967	*/
AnnaBridge	189:f392fc9709a3	968
AnnaBridge	189:f392fc9709a3	969	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	189:f392fc9709a3	970	/** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M)
AnnaBridge	189:f392fc9709a3	971	* @{
AnnaBridge	189:f392fc9709a3	972	*/
AnnaBridge	189:f392fc9709a3	973	#define LL_RCC_PLLSAI1M_DIV_1 0x00000000U /!< PLLSAI1 division factor for PLLSAI1M input by 1 /
AnnaBridge	189:f392fc9709a3	974	#define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 2 /
AnnaBridge	189:f392fc9709a3	975	#define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /!< PLLSAI1 division factor for PLLSAI1M input by 3 /
AnnaBridge	189:f392fc9709a3	976	#define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 4 /
AnnaBridge	189:f392fc9709a3	977	#define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2) /!< PLLSAI1 division factor for PLLSAI1M input by 5 /
AnnaBridge	189:f392fc9709a3	978	#define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 6 /
AnnaBridge	189:f392fc9709a3	979	#define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_1) /!< PLLSAI1 division factor for PLLSAI1M input by 7 /
AnnaBridge	189:f392fc9709a3	980	#define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_1\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 8 /
AnnaBridge	189:f392fc9709a3	981	#define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3) /!< PLLSAI1 division factor for PLLSAI1M input by 9 /
AnnaBridge	189:f392fc9709a3	982	#define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 10 /
AnnaBridge	189:f392fc9709a3	983	#define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_1) /!< PLLSAI1 division factor for PLLSAI1M input by 11 /
AnnaBridge	189:f392fc9709a3	984	#define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_1\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 12 /
AnnaBridge	189:f392fc9709a3	985	#define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_2) /!< PLLSAI1 division factor for PLLSAI1M input by 13 /
AnnaBridge	189:f392fc9709a3	986	#define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 14 /
AnnaBridge	189:f392fc9709a3	987	#define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_1) /!< PLLSAI1 division factor for PLLSAI1M input by 15 /
AnnaBridge	189:f392fc9709a3	988	#define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_1\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 16 /
AnnaBridge	189:f392fc9709a3	989	/**
AnnaBridge	189:f392fc9709a3	990	* @}
AnnaBridge	189:f392fc9709a3	991	*/
AnnaBridge	189:f392fc9709a3	992	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	189:f392fc9709a3	993
AnnaBridge	189:f392fc9709a3	994	/** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q)
AnnaBridge	189:f392fc9709a3	995	* @{
AnnaBridge	189:f392fc9709a3	996	*/
AnnaBridge	189:f392fc9709a3	997	#define LL_RCC_PLLSAI1Q_DIV_2 0x00000000U /!< PLLSAI1 division factor for PLLSAI1Q output by 2 /
AnnaBridge	189:f392fc9709a3	998	#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /!< PLLSAI1 division factor for PLLSAI1Q output by 4 /
AnnaBridge	189:f392fc9709a3	999	#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /!< PLLSAI1 division factor for PLLSAI1Q output by 6 /
AnnaBridge	189:f392fc9709a3	1000	#define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /!< PLLSAI1 division factor for PLLSAI1Q output by 8 /
AnnaBridge	189:f392fc9709a3	1001	/**
AnnaBridge	189:f392fc9709a3	1002	* @}
AnnaBridge	189:f392fc9709a3	1003	*/
AnnaBridge	189:f392fc9709a3	1004
AnnaBridge	189:f392fc9709a3	1005	/** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P)
AnnaBridge	189:f392fc9709a3	1006	* @{
AnnaBridge	189:f392fc9709a3	1007	*/
AnnaBridge	189:f392fc9709a3	1008	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	1009	#define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 2 /
AnnaBridge	189:f392fc9709a3	1010	#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 3 /
AnnaBridge	189:f392fc9709a3	1011	#define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 4 /
AnnaBridge	189:f392fc9709a3	1012	#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 5 /
AnnaBridge	189:f392fc9709a3	1013	#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 6 /
AnnaBridge	189:f392fc9709a3	1014	#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 7 /
AnnaBridge	189:f392fc9709a3	1015	#define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 8 /
AnnaBridge	189:f392fc9709a3	1016	#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 9 /
AnnaBridge	189:f392fc9709a3	1017	#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 10 /
AnnaBridge	189:f392fc9709a3	1018	#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 1 /
AnnaBridge	189:f392fc9709a3	1019	#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 12 /
AnnaBridge	189:f392fc9709a3	1020	#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 13 /
AnnaBridge	189:f392fc9709a3	1021	#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 14 /
AnnaBridge	189:f392fc9709a3	1022	#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 15 /
AnnaBridge	189:f392fc9709a3	1023	#define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 16 /
AnnaBridge	189:f392fc9709a3	1024	#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 17 /
AnnaBridge	189:f392fc9709a3	1025	#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 18 /
AnnaBridge	189:f392fc9709a3	1026	#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 19 /
AnnaBridge	189:f392fc9709a3	1027	#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 20 /
AnnaBridge	189:f392fc9709a3	1028	#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division fctor for PLLSAI1P output by 21 /
AnnaBridge	189:f392fc9709a3	1029	#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 22 /
AnnaBridge	189:f392fc9709a3	1030	#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 23 /
AnnaBridge	189:f392fc9709a3	1031	#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 24 /
AnnaBridge	189:f392fc9709a3	1032	#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 25 /
AnnaBridge	189:f392fc9709a3	1033	#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 26 /
AnnaBridge	189:f392fc9709a3	1034	#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 27 /
AnnaBridge	189:f392fc9709a3	1035	#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 28 /
AnnaBridge	189:f392fc9709a3	1036	#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 29 /
AnnaBridge	189:f392fc9709a3	1037	#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 30 /
AnnaBridge	189:f392fc9709a3	1038	#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 31 /
AnnaBridge	189:f392fc9709a3	1039	#else
AnnaBridge	189:f392fc9709a3	1040	#define LL_RCC_PLLSAI1P_DIV_7 0x00000000U /!< PLLSAI1 division factor for PLLSAI1P output by 7 /
AnnaBridge	189:f392fc9709a3	1041	#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /!< PLLSAI1 division factor for PLLSAI1P output by 17 /
AnnaBridge	189:f392fc9709a3	1042	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge	189:f392fc9709a3	1043	/**
AnnaBridge	189:f392fc9709a3	1044	* @}
AnnaBridge	189:f392fc9709a3	1045	*/
AnnaBridge	189:f392fc9709a3	1046
AnnaBridge	189:f392fc9709a3	1047	/** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R)
AnnaBridge	189:f392fc9709a3	1048	* @{
AnnaBridge	189:f392fc9709a3	1049	*/
AnnaBridge	189:f392fc9709a3	1050	#define LL_RCC_PLLSAI1R_DIV_2 0x00000000U /!< PLLSAI1 division factor for PLLSAI1R output by 2 /
AnnaBridge	189:f392fc9709a3	1051	#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /!< PLLSAI1 division factor for PLLSAI1R output by 4 /
AnnaBridge	189:f392fc9709a3	1052	#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /!< PLLSAI1 division factor for PLLSAI1R output by 6 /
AnnaBridge	189:f392fc9709a3	1053	#define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /!< PLLSAI1 division factor for PLLSAI1R output by 8 /
AnnaBridge	189:f392fc9709a3	1054	/**
AnnaBridge	189:f392fc9709a3	1055	* @}
AnnaBridge	189:f392fc9709a3	1056	*/
AnnaBridge	189:f392fc9709a3	1057
AnnaBridge	189:f392fc9709a3	1058	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1059	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
AnnaBridge	189:f392fc9709a3	1060	/** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI1 division factor (PLLSAI2M)
AnnaBridge	189:f392fc9709a3	1061	* @{
AnnaBridge	189:f392fc9709a3	1062	*/
AnnaBridge	189:f392fc9709a3	1063	#define LL_RCC_PLLSAI2M_DIV_1 0x00000000U /!< PLLSAI2 division factor for PLLSAI2M input by 1 /
AnnaBridge	189:f392fc9709a3	1064	#define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 2 /
AnnaBridge	189:f392fc9709a3	1065	#define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /!< PLLSAI2 division factor for PLLSAI2M input by 3 /
AnnaBridge	189:f392fc9709a3	1066	#define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 4 /
AnnaBridge	189:f392fc9709a3	1067	#define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2) /!< PLLSAI2 division factor for PLLSAI2M input by 5 /
AnnaBridge	189:f392fc9709a3	1068	#define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 6 /
AnnaBridge	189:f392fc9709a3	1069	#define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_1) /!< PLLSAI2 division factor for PLLSAI2M input by 7 /
AnnaBridge	189:f392fc9709a3	1070	#define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_1\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 8 /
AnnaBridge	189:f392fc9709a3	1071	#define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3) /!< PLLSAI2 division factor for PLLSAI2M input by 9 /
AnnaBridge	189:f392fc9709a3	1072	#define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 10 /
AnnaBridge	189:f392fc9709a3	1073	#define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_1) /!< PLLSAI2 division factor for PLLSAI2M input by 11 /
AnnaBridge	189:f392fc9709a3	1074	#define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_1\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 12 /
AnnaBridge	189:f392fc9709a3	1075	#define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_2) /!< PLLSAI2 division factor for PLLSAI2M input by 13 /
AnnaBridge	189:f392fc9709a3	1076	#define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 14 /
AnnaBridge	189:f392fc9709a3	1077	#define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_1) /!< PLLSAI2 division factor for PLLSAI2M input by 15 /
AnnaBridge	189:f392fc9709a3	1078	#define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_1\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 16 /
AnnaBridge	189:f392fc9709a3	1079	/**
AnnaBridge	189:f392fc9709a3	1080	* @}
AnnaBridge	189:f392fc9709a3	1081	*/
AnnaBridge	189:f392fc9709a3	1082	#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
AnnaBridge	189:f392fc9709a3	1083
AnnaBridge	189:f392fc9709a3	1084	#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
AnnaBridge	189:f392fc9709a3	1085	/** @defgroup RCC_LL_EC_PLLSAI2Q PLLSAI2 division factor (PLLSAI2Q)
AnnaBridge	189:f392fc9709a3	1086	* @{
AnnaBridge	189:f392fc9709a3	1087	*/
AnnaBridge	189:f392fc9709a3	1088	#define LL_RCC_PLLSAI2Q_DIV_2 0x00000000U /!< PLLSAI2 division factor for PLLSAI2Q output by 2 /
AnnaBridge	189:f392fc9709a3	1089	#define LL_RCC_PLLSAI2Q_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2Q_0) /!< PLLSAI2 division factor for PLLSAI2Q output by 4 /
AnnaBridge	189:f392fc9709a3	1090	#define LL_RCC_PLLSAI2Q_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2Q_1) /!< PLLSAI2 division factor for PLLSAI2Q output by 6 /
AnnaBridge	189:f392fc9709a3	1091	#define LL_RCC_PLLSAI2Q_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2Q) /!< PLLSAI2 division factor for PLLSAI2Q output by 8 /
AnnaBridge	189:f392fc9709a3	1092	/**
AnnaBridge	189:f392fc9709a3	1093	* @}
AnnaBridge	189:f392fc9709a3	1094	*/
AnnaBridge	189:f392fc9709a3	1095	#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
AnnaBridge	189:f392fc9709a3	1096
AnnaBridge	189:f392fc9709a3	1097	/** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P)
AnnaBridge	189:f392fc9709a3	1098	* @{
AnnaBridge	189:f392fc9709a3	1099	*/
AnnaBridge	189:f392fc9709a3	1100	#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	1101	#define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 2 /
AnnaBridge	189:f392fc9709a3	1102	#define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 3 /
AnnaBridge	189:f392fc9709a3	1103	#define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /!< PLLSAI2 division factor for PLLSAI2P output by 4 /
AnnaBridge	189:f392fc9709a3	1104	#define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 5 /
AnnaBridge	189:f392fc9709a3	1105	#define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 6 /
AnnaBridge	189:f392fc9709a3	1106	#define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 7 /
AnnaBridge	189:f392fc9709a3	1107	#define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /!< PLLSAI2 division factor for PLLSAI2P output by 8 /
AnnaBridge	189:f392fc9709a3	1108	#define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 9 /
AnnaBridge	189:f392fc9709a3	1109	#define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 10 /
AnnaBridge	189:f392fc9709a3	1110	#define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 1 /
AnnaBridge	189:f392fc9709a3	1111	#define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /!< PLLSAI2 division factor for PLLSAI2P output by 12 /
AnnaBridge	189:f392fc9709a3	1112	#define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 13 /
AnnaBridge	189:f392fc9709a3	1113	#define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 14 /
AnnaBridge	189:f392fc9709a3	1114	#define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 15 /
AnnaBridge	189:f392fc9709a3	1115	#define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4) /!< PLLSAI2 division factor for PLLSAI2P output by 16 /
AnnaBridge	189:f392fc9709a3	1116	#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 17 /
AnnaBridge	189:f392fc9709a3	1117	#define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 18 /
AnnaBridge	189:f392fc9709a3	1118	#define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 19 /
AnnaBridge	189:f392fc9709a3	1119	#define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /!< PLLSAI2 division factor for PLLSAI2P output by 20 /
AnnaBridge	189:f392fc9709a3	1120	#define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division fctor for PLLSAI2P output by 21 /
AnnaBridge	189:f392fc9709a3	1121	#define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 22 /
AnnaBridge	189:f392fc9709a3	1122	#define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 23 /
AnnaBridge	189:f392fc9709a3	1123	#define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /!< PLLSAI2 division factor for PLLSAI2P output by 24 /
AnnaBridge	189:f392fc9709a3	1124	#define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 25 /
AnnaBridge	189:f392fc9709a3	1125	#define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 26 /
AnnaBridge	189:f392fc9709a3	1126	#define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 27 /
AnnaBridge	189:f392fc9709a3	1127	#define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /!< PLLSAI2 division factor for PLLSAI2P output by 28 /
AnnaBridge	189:f392fc9709a3	1128	#define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 29 /
AnnaBridge	189:f392fc9709a3	1129	#define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 30 /
AnnaBridge	189:f392fc9709a3	1130	#define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 31 /
AnnaBridge	189:f392fc9709a3	1131	#else
AnnaBridge	189:f392fc9709a3	1132	#define LL_RCC_PLLSAI2P_DIV_7 0x00000000U /!< PLLSAI2 division factor for PLLSAI2P output by 7 /
AnnaBridge	189:f392fc9709a3	1133	#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /!< PLLSAI2 division factor for PLLSAI2P output by 17 /
AnnaBridge	189:f392fc9709a3	1134	#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge	189:f392fc9709a3	1135	/**
AnnaBridge	189:f392fc9709a3	1136	* @}
AnnaBridge	189:f392fc9709a3	1137	*/
AnnaBridge	189:f392fc9709a3	1138
AnnaBridge	189:f392fc9709a3	1139	/** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R)
AnnaBridge	189:f392fc9709a3	1140	* @{
AnnaBridge	189:f392fc9709a3	1141	*/
AnnaBridge	189:f392fc9709a3	1142	#define LL_RCC_PLLSAI2R_DIV_2 0x00000000U /!< PLLSAI2 division factor for PLLSAI2R output by 2 /
AnnaBridge	189:f392fc9709a3	1143	#define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0) /!< PLLSAI2 division factor for PLLSAI2R output by 4 /
AnnaBridge	189:f392fc9709a3	1144	#define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1) /!< PLLSAI2 division factor for PLLSAI2R output by 6 /
AnnaBridge	189:f392fc9709a3	1145	#define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R) /!< PLLSAI2 division factor for PLLSAI2R output by 8 /
AnnaBridge	189:f392fc9709a3	1146	/**
AnnaBridge	189:f392fc9709a3	1147	* @}
AnnaBridge	189:f392fc9709a3	1148	*/
AnnaBridge	189:f392fc9709a3	1149
AnnaBridge	189:f392fc9709a3	1150	#if defined(RCC_CCIPR2_PLLSAI2DIVR)
AnnaBridge	189:f392fc9709a3	1151	/** @defgroup RCC_LL_EC_PLLSAI2DIVR PLLSAI2DIVR division factor (PLLSAI2DIVR)
AnnaBridge	189:f392fc9709a3	1152	* @{
AnnaBridge	189:f392fc9709a3	1153	*/
AnnaBridge	189:f392fc9709a3	1154	#define LL_RCC_PLLSAI2DIVR_DIV_2 0x00000000U /!< PLLSAI2 division factor for PLLSAI2DIVR output by 2 /
AnnaBridge	189:f392fc9709a3	1155	#define LL_RCC_PLLSAI2DIVR_DIV_4 RCC_CCIPR2_PLLSAI2DIVR_0 /!< PLLSAI2 division factor for PLLSAI2DIVR output by 4 /
AnnaBridge	189:f392fc9709a3	1156	#define LL_RCC_PLLSAI2DIVR_DIV_8 RCC_CCIPR2_PLLSAI2DIVR_1 /!< PLLSAI2 division factor for PLLSAI2DIVR output by 8 /
AnnaBridge	189:f392fc9709a3	1157	#define LL_RCC_PLLSAI2DIVR_DIV_16 (RCC_CCIPR2_PLLSAI2DIVR_1 \| RCC_CCIPR2_PLLSAI2DIVR_0) /!< PLLSAI2 division factor for PLLSAI2DIVR output by 16 /
AnnaBridge	189:f392fc9709a3	1158	/**
AnnaBridge	189:f392fc9709a3	1159	* @}
AnnaBridge	189:f392fc9709a3	1160	*/
AnnaBridge	189:f392fc9709a3	1161	#endif /* RCC_CCIPR2_PLLSAI2DIVR */
AnnaBridge	189:f392fc9709a3	1162	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1163
AnnaBridge	189:f392fc9709a3	1164	/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
AnnaBridge	189:f392fc9709a3	1165	* @{
AnnaBridge	189:f392fc9709a3	1166	*/
AnnaBridge	189:f392fc9709a3	1167	#define LL_RCC_MSIRANGESEL_STANDBY 0U /!< MSI Range is provided by MSISRANGE /
AnnaBridge	189:f392fc9709a3	1168	#define LL_RCC_MSIRANGESEL_RUN 1U /!< MSI Range is provided by MSIRANGE /
AnnaBridge	189:f392fc9709a3	1169	/**
AnnaBridge	189:f392fc9709a3	1170	* @}
AnnaBridge	189:f392fc9709a3	1171	*/
AnnaBridge	189:f392fc9709a3	1172
AnnaBridge	189:f392fc9709a3	1173	/** Legacy definitions for compatibility purpose
AnnaBridge	189:f392fc9709a3	1174	@cond 0
AnnaBridge	189:f392fc9709a3	1175	*/
AnnaBridge	189:f392fc9709a3	1176	#if defined(DFSDM1_Channel0)
AnnaBridge	189:f392fc9709a3	1177	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	189:f392fc9709a3	1178	#define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	189:f392fc9709a3	1179	#define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	1180	#define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1181	#endif /* DFSDM1_Channel0 */
AnnaBridge	189:f392fc9709a3	1182	#if defined(SWPMI1)
AnnaBridge	189:f392fc9709a3	1183	#define LL_RCC_SWPMI1_CLKSOURCE_PCLK LL_RCC_SWPMI1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	1184	#endif /* SWPMI1 */
AnnaBridge	189:f392fc9709a3	1185	/**
AnnaBridge	189:f392fc9709a3	1186	@endcond
AnnaBridge	189:f392fc9709a3	1187	*/
AnnaBridge	189:f392fc9709a3	1188
AnnaBridge	189:f392fc9709a3	1189	/**
AnnaBridge	189:f392fc9709a3	1190	* @}
AnnaBridge	189:f392fc9709a3	1191	*/
AnnaBridge	189:f392fc9709a3	1192
AnnaBridge	189:f392fc9709a3	1193	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1194	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
AnnaBridge	189:f392fc9709a3	1195	* @{
AnnaBridge	189:f392fc9709a3	1196	*/
AnnaBridge	189:f392fc9709a3	1197
AnnaBridge	189:f392fc9709a3	1198	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	189:f392fc9709a3	1199	* @{
AnnaBridge	189:f392fc9709a3	1200	*/
AnnaBridge	189:f392fc9709a3	1201
AnnaBridge	189:f392fc9709a3	1202	/**
AnnaBridge	189:f392fc9709a3	1203	* @brief Write a value in RCC register
AnnaBridge	189:f392fc9709a3	1204	* @param __REG__ Register to be written
AnnaBridge	189:f392fc9709a3	1205	* @param __VALUE__ Value to be written in the register
AnnaBridge	189:f392fc9709a3	1206	* @retval None
AnnaBridge	189:f392fc9709a3	1207	*/
AnnaBridge	189:f392fc9709a3	1208	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
AnnaBridge	189:f392fc9709a3	1209
AnnaBridge	189:f392fc9709a3	1210	/**
AnnaBridge	189:f392fc9709a3	1211	* @brief Read a value in RCC register
AnnaBridge	189:f392fc9709a3	1212	* @param __REG__ Register to be read
AnnaBridge	189:f392fc9709a3	1213	* @retval Register value
AnnaBridge	189:f392fc9709a3	1214	*/
AnnaBridge	189:f392fc9709a3	1215	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
AnnaBridge	189:f392fc9709a3	1216	/**
AnnaBridge	189:f392fc9709a3	1217	* @}
AnnaBridge	189:f392fc9709a3	1218	*/
AnnaBridge	189:f392fc9709a3	1219
AnnaBridge	189:f392fc9709a3	1220	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
AnnaBridge	189:f392fc9709a3	1221	* @{
AnnaBridge	189:f392fc9709a3	1222	*/
AnnaBridge	189:f392fc9709a3	1223
AnnaBridge	189:f392fc9709a3	1224	/**
AnnaBridge	189:f392fc9709a3	1225	* @brief Helper macro to calculate the PLLCLK frequency on system domain
AnnaBridge	189:f392fc9709a3	1226	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	189:f392fc9709a3	1227	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
AnnaBridge	189:f392fc9709a3	1228	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1229	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1230	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	1231	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	1232	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	1233	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	1234	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	1235	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	1236	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	1237	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	1238	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	189:f392fc9709a3	1239	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	189:f392fc9709a3	1240	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	189:f392fc9709a3	1241	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	189:f392fc9709a3	1242	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	189:f392fc9709a3	1243	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	189:f392fc9709a3	1244	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	189:f392fc9709a3	1245	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	189:f392fc9709a3	1246	*
AnnaBridge	189:f392fc9709a3	1247	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1248	* @param __PLLN__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1249	* @param __PLLR__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1250	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	189:f392fc9709a3	1251	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	189:f392fc9709a3	1252	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	189:f392fc9709a3	1253	* @arg @ref LL_RCC_PLLR_DIV_8
AnnaBridge	189:f392fc9709a3	1254	* @retval PLL clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1255	*/
AnnaBridge	189:f392fc9709a3	1256	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	189:f392fc9709a3	1257	((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
AnnaBridge	189:f392fc9709a3	1258
AnnaBridge	189:f392fc9709a3	1259	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	1260	/**
AnnaBridge	189:f392fc9709a3	1261	* @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
AnnaBridge	189:f392fc9709a3	1262	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	189:f392fc9709a3	1263	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
AnnaBridge	189:f392fc9709a3	1264	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1265	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1266	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	1267	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	1268	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	1269	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	1270	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	1271	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	1272	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	1273	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	1274	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	189:f392fc9709a3	1275	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	189:f392fc9709a3	1276	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	189:f392fc9709a3	1277	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	189:f392fc9709a3	1278	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	189:f392fc9709a3	1279	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	189:f392fc9709a3	1280	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	189:f392fc9709a3	1281	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	189:f392fc9709a3	1282	*
AnnaBridge	189:f392fc9709a3	1283	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1284	* @param __PLLN__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1285	* @param __PLLP__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1286	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	189:f392fc9709a3	1287	* @arg @ref LL_RCC_PLLP_DIV_3
AnnaBridge	189:f392fc9709a3	1288	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	189:f392fc9709a3	1289	* @arg @ref LL_RCC_PLLP_DIV_5
AnnaBridge	189:f392fc9709a3	1290	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	189:f392fc9709a3	1291	* @arg @ref LL_RCC_PLLP_DIV_7
AnnaBridge	189:f392fc9709a3	1292	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	189:f392fc9709a3	1293	* @arg @ref LL_RCC_PLLP_DIV_9
AnnaBridge	189:f392fc9709a3	1294	* @arg @ref LL_RCC_PLLP_DIV_10
AnnaBridge	189:f392fc9709a3	1295	* @arg @ref LL_RCC_PLLP_DIV_11
AnnaBridge	189:f392fc9709a3	1296	* @arg @ref LL_RCC_PLLP_DIV_12
AnnaBridge	189:f392fc9709a3	1297	* @arg @ref LL_RCC_PLLP_DIV_13
AnnaBridge	189:f392fc9709a3	1298	* @arg @ref LL_RCC_PLLP_DIV_14
AnnaBridge	189:f392fc9709a3	1299	* @arg @ref LL_RCC_PLLP_DIV_15
AnnaBridge	189:f392fc9709a3	1300	* @arg @ref LL_RCC_PLLP_DIV_16
AnnaBridge	189:f392fc9709a3	1301	* @arg @ref LL_RCC_PLLP_DIV_17
AnnaBridge	189:f392fc9709a3	1302	* @arg @ref LL_RCC_PLLP_DIV_18
AnnaBridge	189:f392fc9709a3	1303	* @arg @ref LL_RCC_PLLP_DIV_19
AnnaBridge	189:f392fc9709a3	1304	* @arg @ref LL_RCC_PLLP_DIV_20
AnnaBridge	189:f392fc9709a3	1305	* @arg @ref LL_RCC_PLLP_DIV_21
AnnaBridge	189:f392fc9709a3	1306	* @arg @ref LL_RCC_PLLP_DIV_22
AnnaBridge	189:f392fc9709a3	1307	* @arg @ref LL_RCC_PLLP_DIV_23
AnnaBridge	189:f392fc9709a3	1308	* @arg @ref LL_RCC_PLLP_DIV_24
AnnaBridge	189:f392fc9709a3	1309	* @arg @ref LL_RCC_PLLP_DIV_25
AnnaBridge	189:f392fc9709a3	1310	* @arg @ref LL_RCC_PLLP_DIV_26
AnnaBridge	189:f392fc9709a3	1311	* @arg @ref LL_RCC_PLLP_DIV_27
AnnaBridge	189:f392fc9709a3	1312	* @arg @ref LL_RCC_PLLP_DIV_28
AnnaBridge	189:f392fc9709a3	1313	* @arg @ref LL_RCC_PLLP_DIV_29
AnnaBridge	189:f392fc9709a3	1314	* @arg @ref LL_RCC_PLLP_DIV_30
AnnaBridge	189:f392fc9709a3	1315	* @arg @ref LL_RCC_PLLP_DIV_31
AnnaBridge	189:f392fc9709a3	1316	* @retval PLL clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1317	*/
AnnaBridge	189:f392fc9709a3	1318	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	189:f392fc9709a3	1319	((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
AnnaBridge	189:f392fc9709a3	1320
AnnaBridge	189:f392fc9709a3	1321	#else
AnnaBridge	189:f392fc9709a3	1322	/**
AnnaBridge	189:f392fc9709a3	1323	* @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
AnnaBridge	189:f392fc9709a3	1324	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	189:f392fc9709a3	1325	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
AnnaBridge	189:f392fc9709a3	1326	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1327	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1328	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	1329	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	1330	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	1331	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	1332	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	1333	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	1334	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	1335	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	1336	* @param __PLLN__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1337	* @param __PLLP__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1338	* @arg @ref LL_RCC_PLLP_DIV_7
AnnaBridge	189:f392fc9709a3	1339	* @arg @ref LL_RCC_PLLP_DIV_17
AnnaBridge	189:f392fc9709a3	1340	* @retval PLL clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1341	*/
AnnaBridge	189:f392fc9709a3	1342	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	189:f392fc9709a3	1343	(((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U))
AnnaBridge	189:f392fc9709a3	1344
AnnaBridge	189:f392fc9709a3	1345	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	189:f392fc9709a3	1346
AnnaBridge	189:f392fc9709a3	1347	/**
AnnaBridge	189:f392fc9709a3	1348	* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
AnnaBridge	189:f392fc9709a3	1349	* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	189:f392fc9709a3	1350	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
AnnaBridge	189:f392fc9709a3	1351	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1352	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1353	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	1354	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	1355	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	1356	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	1357	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	1358	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	1359	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	1360	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	1361	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	189:f392fc9709a3	1362	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	189:f392fc9709a3	1363	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	189:f392fc9709a3	1364	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	189:f392fc9709a3	1365	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	189:f392fc9709a3	1366	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	189:f392fc9709a3	1367	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	189:f392fc9709a3	1368	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	189:f392fc9709a3	1369	*
AnnaBridge	189:f392fc9709a3	1370	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1371	* @param __PLLN__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1372	* @param __PLLQ__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1373	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	189:f392fc9709a3	1374	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	189:f392fc9709a3	1375	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	189:f392fc9709a3	1376	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	189:f392fc9709a3	1377	* @retval PLL clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1378	*/
AnnaBridge	189:f392fc9709a3	1379	#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	189:f392fc9709a3	1380	((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
AnnaBridge	189:f392fc9709a3	1381
AnnaBridge	189:f392fc9709a3	1382	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	1383	/**
AnnaBridge	189:f392fc9709a3	1384	* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
AnnaBridge	189:f392fc9709a3	1385	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
AnnaBridge	189:f392fc9709a3	1386	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
AnnaBridge	189:f392fc9709a3	1387	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1388	* @param __PLLSAI1M__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1389	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	189:f392fc9709a3	1390	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	189:f392fc9709a3	1391	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	189:f392fc9709a3	1392	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	189:f392fc9709a3	1393	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	189:f392fc9709a3	1394	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	189:f392fc9709a3	1395	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	189:f392fc9709a3	1396	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	189:f392fc9709a3	1397	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	189:f392fc9709a3	1398	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	189:f392fc9709a3	1399	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	189:f392fc9709a3	1400	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	189:f392fc9709a3	1401	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	189:f392fc9709a3	1402	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	189:f392fc9709a3	1403	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	189:f392fc9709a3	1404	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	189:f392fc9709a3	1405	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1406	* @param __PLLSAI1P__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1407	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
AnnaBridge	189:f392fc9709a3	1408	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
AnnaBridge	189:f392fc9709a3	1409	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
AnnaBridge	189:f392fc9709a3	1410	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
AnnaBridge	189:f392fc9709a3	1411	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
AnnaBridge	189:f392fc9709a3	1412	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	189:f392fc9709a3	1413	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
AnnaBridge	189:f392fc9709a3	1414	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
AnnaBridge	189:f392fc9709a3	1415	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
AnnaBridge	189:f392fc9709a3	1416	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
AnnaBridge	189:f392fc9709a3	1417	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
AnnaBridge	189:f392fc9709a3	1418	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
AnnaBridge	189:f392fc9709a3	1419	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
AnnaBridge	189:f392fc9709a3	1420	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
AnnaBridge	189:f392fc9709a3	1421	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
AnnaBridge	189:f392fc9709a3	1422	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	189:f392fc9709a3	1423	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
AnnaBridge	189:f392fc9709a3	1424	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
AnnaBridge	189:f392fc9709a3	1425	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
AnnaBridge	189:f392fc9709a3	1426	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
AnnaBridge	189:f392fc9709a3	1427	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
AnnaBridge	189:f392fc9709a3	1428	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
AnnaBridge	189:f392fc9709a3	1429	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
AnnaBridge	189:f392fc9709a3	1430	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
AnnaBridge	189:f392fc9709a3	1431	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
AnnaBridge	189:f392fc9709a3	1432	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
AnnaBridge	189:f392fc9709a3	1433	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
AnnaBridge	189:f392fc9709a3	1434	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
AnnaBridge	189:f392fc9709a3	1435	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
AnnaBridge	189:f392fc9709a3	1436	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
AnnaBridge	189:f392fc9709a3	1437	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1438	*/
AnnaBridge	189:f392fc9709a3	1439	#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \
AnnaBridge	189:f392fc9709a3	1440	((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	189:f392fc9709a3	1441	((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
AnnaBridge	189:f392fc9709a3	1442
AnnaBridge	189:f392fc9709a3	1443	#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	1444	/**
AnnaBridge	189:f392fc9709a3	1445	* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
AnnaBridge	189:f392fc9709a3	1446	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	189:f392fc9709a3	1447	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
AnnaBridge	189:f392fc9709a3	1448	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1449	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1450	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	1451	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	1452	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	1453	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	1454	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	1455	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	1456	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	1457	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	1458	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1459	* @param __PLLSAI1P__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1460	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
AnnaBridge	189:f392fc9709a3	1461	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
AnnaBridge	189:f392fc9709a3	1462	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
AnnaBridge	189:f392fc9709a3	1463	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
AnnaBridge	189:f392fc9709a3	1464	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
AnnaBridge	189:f392fc9709a3	1465	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	189:f392fc9709a3	1466	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
AnnaBridge	189:f392fc9709a3	1467	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
AnnaBridge	189:f392fc9709a3	1468	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
AnnaBridge	189:f392fc9709a3	1469	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
AnnaBridge	189:f392fc9709a3	1470	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
AnnaBridge	189:f392fc9709a3	1471	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
AnnaBridge	189:f392fc9709a3	1472	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
AnnaBridge	189:f392fc9709a3	1473	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
AnnaBridge	189:f392fc9709a3	1474	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
AnnaBridge	189:f392fc9709a3	1475	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	189:f392fc9709a3	1476	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
AnnaBridge	189:f392fc9709a3	1477	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
AnnaBridge	189:f392fc9709a3	1478	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
AnnaBridge	189:f392fc9709a3	1479	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
AnnaBridge	189:f392fc9709a3	1480	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
AnnaBridge	189:f392fc9709a3	1481	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
AnnaBridge	189:f392fc9709a3	1482	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
AnnaBridge	189:f392fc9709a3	1483	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
AnnaBridge	189:f392fc9709a3	1484	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
AnnaBridge	189:f392fc9709a3	1485	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
AnnaBridge	189:f392fc9709a3	1486	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
AnnaBridge	189:f392fc9709a3	1487	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
AnnaBridge	189:f392fc9709a3	1488	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
AnnaBridge	189:f392fc9709a3	1489	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
AnnaBridge	189:f392fc9709a3	1490	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1491	*/
AnnaBridge	189:f392fc9709a3	1492	#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
AnnaBridge	189:f392fc9709a3	1493	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	189:f392fc9709a3	1494	((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
AnnaBridge	189:f392fc9709a3	1495
AnnaBridge	189:f392fc9709a3	1496	#else
AnnaBridge	189:f392fc9709a3	1497	/**
AnnaBridge	189:f392fc9709a3	1498	* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
AnnaBridge	189:f392fc9709a3	1499	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	189:f392fc9709a3	1500	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
AnnaBridge	189:f392fc9709a3	1501	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1502	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1503	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	1504	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	1505	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	1506	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	1507	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	1508	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	1509	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	1510	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	1511	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1512	* @param __PLLSAI1P__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1513	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	189:f392fc9709a3	1514	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	189:f392fc9709a3	1515	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1516	*/
AnnaBridge	189:f392fc9709a3	1517	#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
AnnaBridge	189:f392fc9709a3	1518	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	189:f392fc9709a3	1519	(((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U))
AnnaBridge	189:f392fc9709a3	1520
AnnaBridge	189:f392fc9709a3	1521	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge	189:f392fc9709a3	1522
AnnaBridge	189:f392fc9709a3	1523	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	189:f392fc9709a3	1524	/**
AnnaBridge	189:f392fc9709a3	1525	* @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
AnnaBridge	189:f392fc9709a3	1526	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
AnnaBridge	189:f392fc9709a3	1527	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
AnnaBridge	189:f392fc9709a3	1528	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1529	* @param __PLLSAI1M__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1530	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	189:f392fc9709a3	1531	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	189:f392fc9709a3	1532	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	189:f392fc9709a3	1533	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	189:f392fc9709a3	1534	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	189:f392fc9709a3	1535	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	189:f392fc9709a3	1536	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	189:f392fc9709a3	1537	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	189:f392fc9709a3	1538	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	189:f392fc9709a3	1539	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	189:f392fc9709a3	1540	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	189:f392fc9709a3	1541	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	189:f392fc9709a3	1542	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	189:f392fc9709a3	1543	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	189:f392fc9709a3	1544	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	189:f392fc9709a3	1545	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	189:f392fc9709a3	1546	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1547	* @param __PLLSAI1Q__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1548	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
AnnaBridge	189:f392fc9709a3	1549	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
AnnaBridge	189:f392fc9709a3	1550	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
AnnaBridge	189:f392fc9709a3	1551	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
AnnaBridge	189:f392fc9709a3	1552	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1553	*/
AnnaBridge	189:f392fc9709a3	1554	#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \
AnnaBridge	189:f392fc9709a3	1555	((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	189:f392fc9709a3	1556	((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
AnnaBridge	189:f392fc9709a3	1557
AnnaBridge	189:f392fc9709a3	1558	#else
AnnaBridge	189:f392fc9709a3	1559	/**
AnnaBridge	189:f392fc9709a3	1560	* @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
AnnaBridge	189:f392fc9709a3	1561	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	189:f392fc9709a3	1562	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
AnnaBridge	189:f392fc9709a3	1563	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1564	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1565	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	1566	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	1567	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	1568	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	1569	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	1570	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	1571	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	1572	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	1573	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1574	* @param __PLLSAI1Q__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1575	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
AnnaBridge	189:f392fc9709a3	1576	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
AnnaBridge	189:f392fc9709a3	1577	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
AnnaBridge	189:f392fc9709a3	1578	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
AnnaBridge	189:f392fc9709a3	1579	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1580	*/
AnnaBridge	189:f392fc9709a3	1581	#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \
AnnaBridge	189:f392fc9709a3	1582	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	189:f392fc9709a3	1583	((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
AnnaBridge	189:f392fc9709a3	1584
AnnaBridge	189:f392fc9709a3	1585	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	189:f392fc9709a3	1586
AnnaBridge	189:f392fc9709a3	1587	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	189:f392fc9709a3	1588	/**
AnnaBridge	189:f392fc9709a3	1589	* @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
AnnaBridge	189:f392fc9709a3	1590	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
AnnaBridge	189:f392fc9709a3	1591	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
AnnaBridge	189:f392fc9709a3	1592	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1593	* @param __PLLSAI1M__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1594	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	189:f392fc9709a3	1595	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	189:f392fc9709a3	1596	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	189:f392fc9709a3	1597	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	189:f392fc9709a3	1598	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	189:f392fc9709a3	1599	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	189:f392fc9709a3	1600	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	189:f392fc9709a3	1601	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	189:f392fc9709a3	1602	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	189:f392fc9709a3	1603	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	189:f392fc9709a3	1604	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	189:f392fc9709a3	1605	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	189:f392fc9709a3	1606	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	189:f392fc9709a3	1607	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	189:f392fc9709a3	1608	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	189:f392fc9709a3	1609	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	189:f392fc9709a3	1610	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1611	* @param __PLLSAI1R__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1612	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
AnnaBridge	189:f392fc9709a3	1613	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
AnnaBridge	189:f392fc9709a3	1614	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
AnnaBridge	189:f392fc9709a3	1615	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
AnnaBridge	189:f392fc9709a3	1616	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1617	*/
AnnaBridge	189:f392fc9709a3	1618	#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \
AnnaBridge	189:f392fc9709a3	1619	((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	189:f392fc9709a3	1620	((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
AnnaBridge	189:f392fc9709a3	1621
AnnaBridge	189:f392fc9709a3	1622	#else
AnnaBridge	189:f392fc9709a3	1623	/**
AnnaBridge	189:f392fc9709a3	1624	* @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
AnnaBridge	189:f392fc9709a3	1625	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	189:f392fc9709a3	1626	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
AnnaBridge	189:f392fc9709a3	1627	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1628	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1629	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	1630	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	1631	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	1632	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	1633	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	1634	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	1635	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	1636	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	1637	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1638	* @param __PLLSAI1R__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1639	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
AnnaBridge	189:f392fc9709a3	1640	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
AnnaBridge	189:f392fc9709a3	1641	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
AnnaBridge	189:f392fc9709a3	1642	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
AnnaBridge	189:f392fc9709a3	1643	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1644	*/
AnnaBridge	189:f392fc9709a3	1645	#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \
AnnaBridge	189:f392fc9709a3	1646	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	189:f392fc9709a3	1647	((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
AnnaBridge	189:f392fc9709a3	1648
AnnaBridge	189:f392fc9709a3	1649	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	189:f392fc9709a3	1650
AnnaBridge	189:f392fc9709a3	1651	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	1652	/**
AnnaBridge	189:f392fc9709a3	1653	* @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
AnnaBridge	189:f392fc9709a3	1654	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
AnnaBridge	189:f392fc9709a3	1655	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
AnnaBridge	189:f392fc9709a3	1656	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1657	* @param __PLLSAI2M__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1658	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	189:f392fc9709a3	1659	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	189:f392fc9709a3	1660	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	189:f392fc9709a3	1661	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	189:f392fc9709a3	1662	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	189:f392fc9709a3	1663	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	189:f392fc9709a3	1664	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	189:f392fc9709a3	1665	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	189:f392fc9709a3	1666	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	189:f392fc9709a3	1667	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	189:f392fc9709a3	1668	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	189:f392fc9709a3	1669	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	189:f392fc9709a3	1670	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	189:f392fc9709a3	1671	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	189:f392fc9709a3	1672	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	189:f392fc9709a3	1673	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	189:f392fc9709a3	1674	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1675	* @param __PLLSAI2P__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1676	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	189:f392fc9709a3	1677	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	189:f392fc9709a3	1678	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	189:f392fc9709a3	1679	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	189:f392fc9709a3	1680	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	189:f392fc9709a3	1681	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	189:f392fc9709a3	1682	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	189:f392fc9709a3	1683	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	189:f392fc9709a3	1684	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	189:f392fc9709a3	1685	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	189:f392fc9709a3	1686	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	189:f392fc9709a3	1687	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	189:f392fc9709a3	1688	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	189:f392fc9709a3	1689	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	189:f392fc9709a3	1690	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	189:f392fc9709a3	1691	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	189:f392fc9709a3	1692	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	189:f392fc9709a3	1693	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	189:f392fc9709a3	1694	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	189:f392fc9709a3	1695	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	189:f392fc9709a3	1696	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	189:f392fc9709a3	1697	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	189:f392fc9709a3	1698	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	189:f392fc9709a3	1699	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	189:f392fc9709a3	1700	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	189:f392fc9709a3	1701	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	189:f392fc9709a3	1702	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	189:f392fc9709a3	1703	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	189:f392fc9709a3	1704	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	189:f392fc9709a3	1705	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	189:f392fc9709a3	1706	* @retval PLLSAI2 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1707	*/
AnnaBridge	189:f392fc9709a3	1708	#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \
AnnaBridge	189:f392fc9709a3	1709	((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	189:f392fc9709a3	1710	((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
AnnaBridge	189:f392fc9709a3	1711
AnnaBridge	189:f392fc9709a3	1712	#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	1713	/**
AnnaBridge	189:f392fc9709a3	1714	* @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
AnnaBridge	189:f392fc9709a3	1715	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	189:f392fc9709a3	1716	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
AnnaBridge	189:f392fc9709a3	1717	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1718	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1719	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	1720	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	1721	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	1722	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	1723	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	1724	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	1725	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	1726	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	1727	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1728	* @param __PLLSAI2P__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1729	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	189:f392fc9709a3	1730	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	189:f392fc9709a3	1731	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	189:f392fc9709a3	1732	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	189:f392fc9709a3	1733	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	189:f392fc9709a3	1734	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	189:f392fc9709a3	1735	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	189:f392fc9709a3	1736	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	189:f392fc9709a3	1737	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	189:f392fc9709a3	1738	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	189:f392fc9709a3	1739	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	189:f392fc9709a3	1740	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	189:f392fc9709a3	1741	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	189:f392fc9709a3	1742	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	189:f392fc9709a3	1743	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	189:f392fc9709a3	1744	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	189:f392fc9709a3	1745	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	189:f392fc9709a3	1746	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	189:f392fc9709a3	1747	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	189:f392fc9709a3	1748	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	189:f392fc9709a3	1749	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	189:f392fc9709a3	1750	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	189:f392fc9709a3	1751	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	189:f392fc9709a3	1752	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	189:f392fc9709a3	1753	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	189:f392fc9709a3	1754	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	189:f392fc9709a3	1755	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	189:f392fc9709a3	1756	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	189:f392fc9709a3	1757	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	189:f392fc9709a3	1758	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	189:f392fc9709a3	1759	* @retval PLLSAI2 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1760	*/
AnnaBridge	189:f392fc9709a3	1761	#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
AnnaBridge	189:f392fc9709a3	1762	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	189:f392fc9709a3	1763	((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
AnnaBridge	189:f392fc9709a3	1764
AnnaBridge	189:f392fc9709a3	1765	#else
AnnaBridge	189:f392fc9709a3	1766	/**
AnnaBridge	189:f392fc9709a3	1767	* @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
AnnaBridge	189:f392fc9709a3	1768	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	189:f392fc9709a3	1769	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
AnnaBridge	189:f392fc9709a3	1770	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1771	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1772	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	1773	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	1774	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	1775	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	1776	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	1777	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	1778	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	1779	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	1780	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1781	* @param __PLLSAI2P__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1782	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	189:f392fc9709a3	1783	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	189:f392fc9709a3	1784	* @retval PLLSAI2 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1785	*/
AnnaBridge	189:f392fc9709a3	1786	#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
AnnaBridge	189:f392fc9709a3	1787	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \
AnnaBridge	189:f392fc9709a3	1788	(((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U))
AnnaBridge	189:f392fc9709a3	1789
AnnaBridge	189:f392fc9709a3	1790	#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge	189:f392fc9709a3	1791
AnnaBridge	189:f392fc9709a3	1792	#if defined(LTDC)
AnnaBridge	189:f392fc9709a3	1793	/**
AnnaBridge	189:f392fc9709a3	1794	* @brief Helper macro to calculate the PLLSAI2 frequency used for LTDC domain
AnnaBridge	189:f392fc9709a3	1795	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
AnnaBridge	189:f392fc9709a3	1796	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR (), @ref LL_RCC_PLLSAI2_GetDIVR ());
AnnaBridge	189:f392fc9709a3	1797	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
AnnaBridge	189:f392fc9709a3	1798	* @param __PLLSAI2M__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1799	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	189:f392fc9709a3	1800	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	189:f392fc9709a3	1801	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	189:f392fc9709a3	1802	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	189:f392fc9709a3	1803	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	189:f392fc9709a3	1804	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	189:f392fc9709a3	1805	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	189:f392fc9709a3	1806	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	189:f392fc9709a3	1807	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	189:f392fc9709a3	1808	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	189:f392fc9709a3	1809	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	189:f392fc9709a3	1810	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	189:f392fc9709a3	1811	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	189:f392fc9709a3	1812	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	189:f392fc9709a3	1813	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	189:f392fc9709a3	1814	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	189:f392fc9709a3	1815	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1816	* @param __PLLSAI2R__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1817	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
AnnaBridge	189:f392fc9709a3	1818	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
AnnaBridge	189:f392fc9709a3	1819	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
AnnaBridge	189:f392fc9709a3	1820	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
AnnaBridge	189:f392fc9709a3	1821	* @param __PLLSAI2DIVR__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1822	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
AnnaBridge	189:f392fc9709a3	1823	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
AnnaBridge	189:f392fc9709a3	1824	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
AnnaBridge	189:f392fc9709a3	1825	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
AnnaBridge	189:f392fc9709a3	1826	* @retval PLLSAI2 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1827	*/
AnnaBridge	189:f392fc9709a3	1828	#define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \
AnnaBridge	189:f392fc9709a3	1829	(((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	189:f392fc9709a3	1830	(((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (aRCC_PLLSAI2DIVRPrescTable[(__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos])))
AnnaBridge	189:f392fc9709a3	1831	#else
AnnaBridge	189:f392fc9709a3	1832	/**
AnnaBridge	189:f392fc9709a3	1833	* @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain
AnnaBridge	189:f392fc9709a3	1834	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	189:f392fc9709a3	1835	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ());
AnnaBridge	189:f392fc9709a3	1836	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	1837	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1838	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	1839	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	1840	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	1841	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	1842	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	1843	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	1844	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	1845	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	1846	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1847	* @param __PLLSAI2R__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1848	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
AnnaBridge	189:f392fc9709a3	1849	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
AnnaBridge	189:f392fc9709a3	1850	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
AnnaBridge	189:f392fc9709a3	1851	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
AnnaBridge	189:f392fc9709a3	1852	* @retval PLLSAI2 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1853	*/
AnnaBridge	189:f392fc9709a3	1854	#define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) \
AnnaBridge	189:f392fc9709a3	1855	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	189:f392fc9709a3	1856	((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U))
AnnaBridge	189:f392fc9709a3	1857
AnnaBridge	189:f392fc9709a3	1858	#endif /* LTDC */
AnnaBridge	189:f392fc9709a3	1859
AnnaBridge	189:f392fc9709a3	1860	#if defined(DSI)
AnnaBridge	189:f392fc9709a3	1861	/**
AnnaBridge	189:f392fc9709a3	1862	* @brief Helper macro to calculate the PLLDSICLK frequency used on DSI
AnnaBridge	189:f392fc9709a3	1863	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_DSI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
AnnaBridge	189:f392fc9709a3	1864	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetQ ());
AnnaBridge	189:f392fc9709a3	1865	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
AnnaBridge	189:f392fc9709a3	1866	* @param __PLLSAI2M__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1867	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	189:f392fc9709a3	1868	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	189:f392fc9709a3	1869	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	189:f392fc9709a3	1870	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	189:f392fc9709a3	1871	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	189:f392fc9709a3	1872	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	189:f392fc9709a3	1873	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	189:f392fc9709a3	1874	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	189:f392fc9709a3	1875	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	189:f392fc9709a3	1876	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	189:f392fc9709a3	1877	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	189:f392fc9709a3	1878	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	189:f392fc9709a3	1879	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	189:f392fc9709a3	1880	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	189:f392fc9709a3	1881	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	189:f392fc9709a3	1882	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	189:f392fc9709a3	1883	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	189:f392fc9709a3	1884	* @param __PLLSAI2Q__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1885	* @arg @ref LL_RCC_PLLSAI2Q_DIV_2
AnnaBridge	189:f392fc9709a3	1886	* @arg @ref LL_RCC_PLLSAI2Q_DIV_4
AnnaBridge	189:f392fc9709a3	1887	* @arg @ref LL_RCC_PLLSAI2Q_DIV_6
AnnaBridge	189:f392fc9709a3	1888	* @arg @ref LL_RCC_PLLSAI2Q_DIV_8
AnnaBridge	189:f392fc9709a3	1889	* @retval PLL clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1890	*/
AnnaBridge	189:f392fc9709a3	1891	#define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \
AnnaBridge	189:f392fc9709a3	1892	((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	189:f392fc9709a3	1893	((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U))
AnnaBridge	189:f392fc9709a3	1894	#endif /* DSI */
AnnaBridge	189:f392fc9709a3	1895
AnnaBridge	189:f392fc9709a3	1896
AnnaBridge	189:f392fc9709a3	1897
AnnaBridge	189:f392fc9709a3	1898	/**
AnnaBridge	189:f392fc9709a3	1899	* @brief Helper macro to calculate the HCLK frequency
AnnaBridge	189:f392fc9709a3	1900	* @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
AnnaBridge	189:f392fc9709a3	1901	* @param __AHBPRESCALER__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1902	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	189:f392fc9709a3	1903	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	189:f392fc9709a3	1904	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	189:f392fc9709a3	1905	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	189:f392fc9709a3	1906	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	189:f392fc9709a3	1907	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	189:f392fc9709a3	1908	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	189:f392fc9709a3	1909	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	189:f392fc9709a3	1910	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	189:f392fc9709a3	1911	* @retval HCLK clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1912	*/
AnnaBridge	189:f392fc9709a3	1913	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
AnnaBridge	189:f392fc9709a3	1914
AnnaBridge	189:f392fc9709a3	1915	/**
AnnaBridge	189:f392fc9709a3	1916	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
AnnaBridge	189:f392fc9709a3	1917	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	189:f392fc9709a3	1918	* @param __APB1PRESCALER__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1919	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	189:f392fc9709a3	1920	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	189:f392fc9709a3	1921	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	189:f392fc9709a3	1922	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	189:f392fc9709a3	1923	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	189:f392fc9709a3	1924	* @retval PCLK1 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1925	*/
AnnaBridge	189:f392fc9709a3	1926	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
AnnaBridge	189:f392fc9709a3	1927
AnnaBridge	189:f392fc9709a3	1928	/**
AnnaBridge	189:f392fc9709a3	1929	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
AnnaBridge	189:f392fc9709a3	1930	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	189:f392fc9709a3	1931	* @param __APB2PRESCALER__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1932	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	189:f392fc9709a3	1933	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	189:f392fc9709a3	1934	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	189:f392fc9709a3	1935	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	189:f392fc9709a3	1936	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	189:f392fc9709a3	1937	* @retval PCLK2 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1938	*/
AnnaBridge	189:f392fc9709a3	1939	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
AnnaBridge	189:f392fc9709a3	1940
AnnaBridge	189:f392fc9709a3	1941	/**
AnnaBridge	189:f392fc9709a3	1942	* @brief Helper macro to calculate the MSI frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1943	* @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
AnnaBridge	189:f392fc9709a3	1944	* @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
AnnaBridge	189:f392fc9709a3	1945	* __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()
AnnaBridge	189:f392fc9709a3	1946	* else by LL_RCC_MSI_GetRange()
AnnaBridge	189:f392fc9709a3	1947	* ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
AnnaBridge	189:f392fc9709a3	1948	* (LL_RCC_MSI_IsEnabledRangeSelect()?
AnnaBridge	189:f392fc9709a3	1949	* LL_RCC_MSI_GetRange():
AnnaBridge	189:f392fc9709a3	1950	* LL_RCC_MSI_GetRangeAfterStandby()))
AnnaBridge	189:f392fc9709a3	1951	* @param __MSISEL__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1952	* @arg @ref LL_RCC_MSIRANGESEL_STANDBY
AnnaBridge	189:f392fc9709a3	1953	* @arg @ref LL_RCC_MSIRANGESEL_RUN
AnnaBridge	189:f392fc9709a3	1954	* @param __MSIRANGE__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1955	* @arg @ref LL_RCC_MSIRANGE_0
AnnaBridge	189:f392fc9709a3	1956	* @arg @ref LL_RCC_MSIRANGE_1
AnnaBridge	189:f392fc9709a3	1957	* @arg @ref LL_RCC_MSIRANGE_2
AnnaBridge	189:f392fc9709a3	1958	* @arg @ref LL_RCC_MSIRANGE_3
AnnaBridge	189:f392fc9709a3	1959	* @arg @ref LL_RCC_MSIRANGE_4
AnnaBridge	189:f392fc9709a3	1960	* @arg @ref LL_RCC_MSIRANGE_5
AnnaBridge	189:f392fc9709a3	1961	* @arg @ref LL_RCC_MSIRANGE_6
AnnaBridge	189:f392fc9709a3	1962	* @arg @ref LL_RCC_MSIRANGE_7
AnnaBridge	189:f392fc9709a3	1963	* @arg @ref LL_RCC_MSIRANGE_8
AnnaBridge	189:f392fc9709a3	1964	* @arg @ref LL_RCC_MSIRANGE_9
AnnaBridge	189:f392fc9709a3	1965	* @arg @ref LL_RCC_MSIRANGE_10
AnnaBridge	189:f392fc9709a3	1966	* @arg @ref LL_RCC_MSIRANGE_11
AnnaBridge	189:f392fc9709a3	1967	* @arg @ref LL_RCC_MSISRANGE_4
AnnaBridge	189:f392fc9709a3	1968	* @arg @ref LL_RCC_MSISRANGE_5
AnnaBridge	189:f392fc9709a3	1969	* @arg @ref LL_RCC_MSISRANGE_6
AnnaBridge	189:f392fc9709a3	1970	* @arg @ref LL_RCC_MSISRANGE_7
AnnaBridge	189:f392fc9709a3	1971	* @retval MSI clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1972	*/
AnnaBridge	189:f392fc9709a3	1973	#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
AnnaBridge	189:f392fc9709a3	1974	(MSIRangeTable[(__MSIRANGE__) >> 8U]) : \
AnnaBridge	189:f392fc9709a3	1975	(MSIRangeTable[(__MSIRANGE__) >> 4U]))
AnnaBridge	189:f392fc9709a3	1976
AnnaBridge	189:f392fc9709a3	1977	/**
AnnaBridge	189:f392fc9709a3	1978	* @}
AnnaBridge	189:f392fc9709a3	1979	*/
AnnaBridge	189:f392fc9709a3	1980
AnnaBridge	189:f392fc9709a3	1981	/**
AnnaBridge	189:f392fc9709a3	1982	* @}
AnnaBridge	189:f392fc9709a3	1983	*/
AnnaBridge	189:f392fc9709a3	1984
AnnaBridge	189:f392fc9709a3	1985	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1986	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
AnnaBridge	189:f392fc9709a3	1987	* @{
AnnaBridge	189:f392fc9709a3	1988	*/
AnnaBridge	189:f392fc9709a3	1989
AnnaBridge	189:f392fc9709a3	1990	/** @defgroup RCC_LL_EF_HSE HSE
AnnaBridge	189:f392fc9709a3	1991	* @{
AnnaBridge	189:f392fc9709a3	1992	*/
AnnaBridge	189:f392fc9709a3	1993
AnnaBridge	189:f392fc9709a3	1994	/**
AnnaBridge	189:f392fc9709a3	1995	* @brief Enable the Clock Security System.
AnnaBridge	189:f392fc9709a3	1996	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
AnnaBridge	189:f392fc9709a3	1997	* @retval None
AnnaBridge	189:f392fc9709a3	1998	*/
AnnaBridge	189:f392fc9709a3	1999	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
AnnaBridge	189:f392fc9709a3	2000	{
AnnaBridge	189:f392fc9709a3	2001	SET_BIT(RCC->CR, RCC_CR_CSSON);
AnnaBridge	189:f392fc9709a3	2002	}
AnnaBridge	189:f392fc9709a3	2003
AnnaBridge	189:f392fc9709a3	2004	/**
AnnaBridge	189:f392fc9709a3	2005	* @brief Enable HSE external oscillator (HSE Bypass)
AnnaBridge	189:f392fc9709a3	2006	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
AnnaBridge	189:f392fc9709a3	2007	* @retval None
AnnaBridge	189:f392fc9709a3	2008	*/
AnnaBridge	189:f392fc9709a3	2009	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
AnnaBridge	189:f392fc9709a3	2010	{
AnnaBridge	189:f392fc9709a3	2011	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	189:f392fc9709a3	2012	}
AnnaBridge	189:f392fc9709a3	2013
AnnaBridge	189:f392fc9709a3	2014	/**
AnnaBridge	189:f392fc9709a3	2015	* @brief Disable HSE external oscillator (HSE Bypass)
AnnaBridge	189:f392fc9709a3	2016	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
AnnaBridge	189:f392fc9709a3	2017	* @retval None
AnnaBridge	189:f392fc9709a3	2018	*/
AnnaBridge	189:f392fc9709a3	2019	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
AnnaBridge	189:f392fc9709a3	2020	{
AnnaBridge	189:f392fc9709a3	2021	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	189:f392fc9709a3	2022	}
AnnaBridge	189:f392fc9709a3	2023
AnnaBridge	189:f392fc9709a3	2024	/**
AnnaBridge	189:f392fc9709a3	2025	* @brief Enable HSE crystal oscillator (HSE ON)
AnnaBridge	189:f392fc9709a3	2026	* @rmtoll CR HSEON LL_RCC_HSE_Enable
AnnaBridge	189:f392fc9709a3	2027	* @retval None
AnnaBridge	189:f392fc9709a3	2028	*/
AnnaBridge	189:f392fc9709a3	2029	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
AnnaBridge	189:f392fc9709a3	2030	{
AnnaBridge	189:f392fc9709a3	2031	SET_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	189:f392fc9709a3	2032	}
AnnaBridge	189:f392fc9709a3	2033
AnnaBridge	189:f392fc9709a3	2034	/**
AnnaBridge	189:f392fc9709a3	2035	* @brief Disable HSE crystal oscillator (HSE ON)
AnnaBridge	189:f392fc9709a3	2036	* @rmtoll CR HSEON LL_RCC_HSE_Disable
AnnaBridge	189:f392fc9709a3	2037	* @retval None
AnnaBridge	189:f392fc9709a3	2038	*/
AnnaBridge	189:f392fc9709a3	2039	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
AnnaBridge	189:f392fc9709a3	2040	{
AnnaBridge	189:f392fc9709a3	2041	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	189:f392fc9709a3	2042	}
AnnaBridge	189:f392fc9709a3	2043
AnnaBridge	189:f392fc9709a3	2044	/**
AnnaBridge	189:f392fc9709a3	2045	* @brief Check if HSE oscillator Ready
AnnaBridge	189:f392fc9709a3	2046	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
AnnaBridge	189:f392fc9709a3	2047	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2048	*/
AnnaBridge	189:f392fc9709a3	2049	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
AnnaBridge	189:f392fc9709a3	2050	{
AnnaBridge	189:f392fc9709a3	2051	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
AnnaBridge	189:f392fc9709a3	2052	}
AnnaBridge	189:f392fc9709a3	2053
AnnaBridge	189:f392fc9709a3	2054	/**
AnnaBridge	189:f392fc9709a3	2055	* @}
AnnaBridge	189:f392fc9709a3	2056	*/
AnnaBridge	189:f392fc9709a3	2057
AnnaBridge	189:f392fc9709a3	2058	/** @defgroup RCC_LL_EF_HSI HSI
AnnaBridge	189:f392fc9709a3	2059	* @{
AnnaBridge	189:f392fc9709a3	2060	*/
AnnaBridge	189:f392fc9709a3	2061
AnnaBridge	189:f392fc9709a3	2062	/**
AnnaBridge	189:f392fc9709a3	2063	* @brief Enable HSI even in stop mode
AnnaBridge	189:f392fc9709a3	2064	* @note HSI oscillator is forced ON even in Stop mode
AnnaBridge	189:f392fc9709a3	2065	* @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
AnnaBridge	189:f392fc9709a3	2066	* @retval None
AnnaBridge	189:f392fc9709a3	2067	*/
AnnaBridge	189:f392fc9709a3	2068	__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
AnnaBridge	189:f392fc9709a3	2069	{
AnnaBridge	189:f392fc9709a3	2070	SET_BIT(RCC->CR, RCC_CR_HSIKERON);
AnnaBridge	189:f392fc9709a3	2071	}
AnnaBridge	189:f392fc9709a3	2072
AnnaBridge	189:f392fc9709a3	2073	/**
AnnaBridge	189:f392fc9709a3	2074	* @brief Disable HSI in stop mode
AnnaBridge	189:f392fc9709a3	2075	* @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
AnnaBridge	189:f392fc9709a3	2076	* @retval None
AnnaBridge	189:f392fc9709a3	2077	*/
AnnaBridge	189:f392fc9709a3	2078	__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
AnnaBridge	189:f392fc9709a3	2079	{
AnnaBridge	189:f392fc9709a3	2080	CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
AnnaBridge	189:f392fc9709a3	2081	}
AnnaBridge	189:f392fc9709a3	2082
AnnaBridge	189:f392fc9709a3	2083	/**
AnnaBridge	189:f392fc9709a3	2084	* @brief Check if HSI is enabled in stop mode
AnnaBridge	189:f392fc9709a3	2085	* @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
AnnaBridge	189:f392fc9709a3	2086	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2087	*/
AnnaBridge	189:f392fc9709a3	2088	__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
AnnaBridge	189:f392fc9709a3	2089	{
AnnaBridge	189:f392fc9709a3	2090	return (READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON));
AnnaBridge	189:f392fc9709a3	2091	}
AnnaBridge	189:f392fc9709a3	2092
AnnaBridge	189:f392fc9709a3	2093	/**
AnnaBridge	189:f392fc9709a3	2094	* @brief Enable HSI oscillator
AnnaBridge	189:f392fc9709a3	2095	* @rmtoll CR HSION LL_RCC_HSI_Enable
AnnaBridge	189:f392fc9709a3	2096	* @retval None
AnnaBridge	189:f392fc9709a3	2097	*/
AnnaBridge	189:f392fc9709a3	2098	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
AnnaBridge	189:f392fc9709a3	2099	{
AnnaBridge	189:f392fc9709a3	2100	SET_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	189:f392fc9709a3	2101	}
AnnaBridge	189:f392fc9709a3	2102
AnnaBridge	189:f392fc9709a3	2103	/**
AnnaBridge	189:f392fc9709a3	2104	* @brief Disable HSI oscillator
AnnaBridge	189:f392fc9709a3	2105	* @rmtoll CR HSION LL_RCC_HSI_Disable
AnnaBridge	189:f392fc9709a3	2106	* @retval None
AnnaBridge	189:f392fc9709a3	2107	*/
AnnaBridge	189:f392fc9709a3	2108	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
AnnaBridge	189:f392fc9709a3	2109	{
AnnaBridge	189:f392fc9709a3	2110	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	189:f392fc9709a3	2111	}
AnnaBridge	189:f392fc9709a3	2112
AnnaBridge	189:f392fc9709a3	2113	/**
AnnaBridge	189:f392fc9709a3	2114	* @brief Check if HSI clock is ready
AnnaBridge	189:f392fc9709a3	2115	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
AnnaBridge	189:f392fc9709a3	2116	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2117	*/
AnnaBridge	189:f392fc9709a3	2118	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
AnnaBridge	189:f392fc9709a3	2119	{
AnnaBridge	189:f392fc9709a3	2120	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
AnnaBridge	189:f392fc9709a3	2121	}
AnnaBridge	189:f392fc9709a3	2122
AnnaBridge	189:f392fc9709a3	2123	/**
AnnaBridge	189:f392fc9709a3	2124	* @brief Enable HSI Automatic from stop mode
AnnaBridge	189:f392fc9709a3	2125	* @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
AnnaBridge	189:f392fc9709a3	2126	* @retval None
AnnaBridge	189:f392fc9709a3	2127	*/
AnnaBridge	189:f392fc9709a3	2128	__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
AnnaBridge	189:f392fc9709a3	2129	{
AnnaBridge	189:f392fc9709a3	2130	SET_BIT(RCC->CR, RCC_CR_HSIASFS);
AnnaBridge	189:f392fc9709a3	2131	}
AnnaBridge	189:f392fc9709a3	2132
AnnaBridge	189:f392fc9709a3	2133	/**
AnnaBridge	189:f392fc9709a3	2134	* @brief Disable HSI Automatic from stop mode
AnnaBridge	189:f392fc9709a3	2135	* @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
AnnaBridge	189:f392fc9709a3	2136	* @retval None
AnnaBridge	189:f392fc9709a3	2137	*/
AnnaBridge	189:f392fc9709a3	2138	__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
AnnaBridge	189:f392fc9709a3	2139	{
AnnaBridge	189:f392fc9709a3	2140	CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
AnnaBridge	189:f392fc9709a3	2141	}
AnnaBridge	189:f392fc9709a3	2142	/**
AnnaBridge	189:f392fc9709a3	2143	* @brief Get HSI Calibration value
AnnaBridge	189:f392fc9709a3	2144	* @note When HSITRIM is written, HSICAL is updated with the sum of
AnnaBridge	189:f392fc9709a3	2145	* HSITRIM and the factory trim value
AnnaBridge	189:f392fc9709a3	2146	* @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
AnnaBridge	189:f392fc9709a3	2147	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	189:f392fc9709a3	2148	*/
AnnaBridge	189:f392fc9709a3	2149	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
AnnaBridge	189:f392fc9709a3	2150	{
AnnaBridge	189:f392fc9709a3	2151	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
AnnaBridge	189:f392fc9709a3	2152	}
AnnaBridge	189:f392fc9709a3	2153
AnnaBridge	189:f392fc9709a3	2154	/**
AnnaBridge	189:f392fc9709a3	2155	* @brief Set HSI Calibration trimming
AnnaBridge	189:f392fc9709a3	2156	* @note user-programmable trimming value that is added to the HSICAL
AnnaBridge	189:f392fc9709a3	2157	* @note Default value is 16, which, when added to the HSICAL value,
AnnaBridge	189:f392fc9709a3	2158	* should trim the HSI to 16 MHz +/- 1 %
AnnaBridge	189:f392fc9709a3	2159	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
AnnaBridge	189:f392fc9709a3	2160	* @param Value Between Min_Data = 0 and Max_Data = 31
AnnaBridge	189:f392fc9709a3	2161	* @retval None
AnnaBridge	189:f392fc9709a3	2162	*/
AnnaBridge	189:f392fc9709a3	2163	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	189:f392fc9709a3	2164	{
AnnaBridge	189:f392fc9709a3	2165	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
AnnaBridge	189:f392fc9709a3	2166	}
AnnaBridge	189:f392fc9709a3	2167
AnnaBridge	189:f392fc9709a3	2168	/**
AnnaBridge	189:f392fc9709a3	2169	* @brief Get HSI Calibration trimming
AnnaBridge	189:f392fc9709a3	2170	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
AnnaBridge	189:f392fc9709a3	2171	* @retval Between Min_Data = 0 and Max_Data = 31
AnnaBridge	189:f392fc9709a3	2172	*/
AnnaBridge	189:f392fc9709a3	2173	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
AnnaBridge	189:f392fc9709a3	2174	{
AnnaBridge	189:f392fc9709a3	2175	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
AnnaBridge	189:f392fc9709a3	2176	}
AnnaBridge	189:f392fc9709a3	2177
AnnaBridge	189:f392fc9709a3	2178	/**
AnnaBridge	189:f392fc9709a3	2179	* @}
AnnaBridge	189:f392fc9709a3	2180	*/
AnnaBridge	189:f392fc9709a3	2181
AnnaBridge	189:f392fc9709a3	2182	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	2183	/** @defgroup RCC_LL_EF_HSI48 HSI48
AnnaBridge	189:f392fc9709a3	2184	* @{
AnnaBridge	189:f392fc9709a3	2185	*/
AnnaBridge	189:f392fc9709a3	2186
AnnaBridge	189:f392fc9709a3	2187	/**
AnnaBridge	189:f392fc9709a3	2188	* @brief Enable HSI48
AnnaBridge	189:f392fc9709a3	2189	* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
AnnaBridge	189:f392fc9709a3	2190	* @retval None
AnnaBridge	189:f392fc9709a3	2191	*/
AnnaBridge	189:f392fc9709a3	2192	__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
AnnaBridge	189:f392fc9709a3	2193	{
AnnaBridge	189:f392fc9709a3	2194	SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
AnnaBridge	189:f392fc9709a3	2195	}
AnnaBridge	189:f392fc9709a3	2196
AnnaBridge	189:f392fc9709a3	2197	/**
AnnaBridge	189:f392fc9709a3	2198	* @brief Disable HSI48
AnnaBridge	189:f392fc9709a3	2199	* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
AnnaBridge	189:f392fc9709a3	2200	* @retval None
AnnaBridge	189:f392fc9709a3	2201	*/
AnnaBridge	189:f392fc9709a3	2202	__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
AnnaBridge	189:f392fc9709a3	2203	{
AnnaBridge	189:f392fc9709a3	2204	CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
AnnaBridge	189:f392fc9709a3	2205	}
AnnaBridge	189:f392fc9709a3	2206
AnnaBridge	189:f392fc9709a3	2207	/**
AnnaBridge	189:f392fc9709a3	2208	* @brief Check if HSI48 oscillator Ready
AnnaBridge	189:f392fc9709a3	2209	* @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
AnnaBridge	189:f392fc9709a3	2210	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2211	*/
AnnaBridge	189:f392fc9709a3	2212	__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
AnnaBridge	189:f392fc9709a3	2213	{
AnnaBridge	189:f392fc9709a3	2214	return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY));
AnnaBridge	189:f392fc9709a3	2215	}
AnnaBridge	189:f392fc9709a3	2216
AnnaBridge	189:f392fc9709a3	2217	/**
AnnaBridge	189:f392fc9709a3	2218	* @brief Get HSI48 Calibration value
AnnaBridge	189:f392fc9709a3	2219	* @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
AnnaBridge	189:f392fc9709a3	2220	* @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
AnnaBridge	189:f392fc9709a3	2221	*/
AnnaBridge	189:f392fc9709a3	2222	__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
AnnaBridge	189:f392fc9709a3	2223	{
AnnaBridge	189:f392fc9709a3	2224	return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
AnnaBridge	189:f392fc9709a3	2225	}
AnnaBridge	189:f392fc9709a3	2226
AnnaBridge	189:f392fc9709a3	2227	/**
AnnaBridge	189:f392fc9709a3	2228	* @}
AnnaBridge	189:f392fc9709a3	2229	*/
AnnaBridge	189:f392fc9709a3	2230	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	2231
AnnaBridge	189:f392fc9709a3	2232	/** @defgroup RCC_LL_EF_LSE LSE
AnnaBridge	189:f392fc9709a3	2233	* @{
AnnaBridge	189:f392fc9709a3	2234	*/
AnnaBridge	189:f392fc9709a3	2235
AnnaBridge	189:f392fc9709a3	2236	/**
AnnaBridge	189:f392fc9709a3	2237	* @brief Enable Low Speed External (LSE) crystal.
AnnaBridge	189:f392fc9709a3	2238	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
AnnaBridge	189:f392fc9709a3	2239	* @retval None
AnnaBridge	189:f392fc9709a3	2240	*/
AnnaBridge	189:f392fc9709a3	2241	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
AnnaBridge	189:f392fc9709a3	2242	{
AnnaBridge	189:f392fc9709a3	2243	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	189:f392fc9709a3	2244	}
AnnaBridge	189:f392fc9709a3	2245
AnnaBridge	189:f392fc9709a3	2246	/**
AnnaBridge	189:f392fc9709a3	2247	* @brief Disable Low Speed External (LSE) crystal.
AnnaBridge	189:f392fc9709a3	2248	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
AnnaBridge	189:f392fc9709a3	2249	* @retval None
AnnaBridge	189:f392fc9709a3	2250	*/
AnnaBridge	189:f392fc9709a3	2251	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
AnnaBridge	189:f392fc9709a3	2252	{
AnnaBridge	189:f392fc9709a3	2253	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	189:f392fc9709a3	2254	}
AnnaBridge	189:f392fc9709a3	2255
AnnaBridge	189:f392fc9709a3	2256	/**
AnnaBridge	189:f392fc9709a3	2257	* @brief Enable external clock source (LSE bypass).
AnnaBridge	189:f392fc9709a3	2258	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
AnnaBridge	189:f392fc9709a3	2259	* @retval None
AnnaBridge	189:f392fc9709a3	2260	*/
AnnaBridge	189:f392fc9709a3	2261	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
AnnaBridge	189:f392fc9709a3	2262	{
AnnaBridge	189:f392fc9709a3	2263	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	189:f392fc9709a3	2264	}
AnnaBridge	189:f392fc9709a3	2265
AnnaBridge	189:f392fc9709a3	2266	/**
AnnaBridge	189:f392fc9709a3	2267	* @brief Disable external clock source (LSE bypass).
AnnaBridge	189:f392fc9709a3	2268	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
AnnaBridge	189:f392fc9709a3	2269	* @retval None
AnnaBridge	189:f392fc9709a3	2270	*/
AnnaBridge	189:f392fc9709a3	2271	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
AnnaBridge	189:f392fc9709a3	2272	{
AnnaBridge	189:f392fc9709a3	2273	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	189:f392fc9709a3	2274	}
AnnaBridge	189:f392fc9709a3	2275
AnnaBridge	189:f392fc9709a3	2276	/**
AnnaBridge	189:f392fc9709a3	2277	* @brief Set LSE oscillator drive capability
AnnaBridge	189:f392fc9709a3	2278	* @note The oscillator is in Xtal mode when it is not in bypass mode.
AnnaBridge	189:f392fc9709a3	2279	* @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
AnnaBridge	189:f392fc9709a3	2280	* @param LSEDrive This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2281	* @arg @ref LL_RCC_LSEDRIVE_LOW
AnnaBridge	189:f392fc9709a3	2282	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
AnnaBridge	189:f392fc9709a3	2283	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
AnnaBridge	189:f392fc9709a3	2284	* @arg @ref LL_RCC_LSEDRIVE_HIGH
AnnaBridge	189:f392fc9709a3	2285	* @retval None
AnnaBridge	189:f392fc9709a3	2286	*/
AnnaBridge	189:f392fc9709a3	2287	__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
AnnaBridge	189:f392fc9709a3	2288	{
AnnaBridge	189:f392fc9709a3	2289	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
AnnaBridge	189:f392fc9709a3	2290	}
AnnaBridge	189:f392fc9709a3	2291
AnnaBridge	189:f392fc9709a3	2292	/**
AnnaBridge	189:f392fc9709a3	2293	* @brief Get LSE oscillator drive capability
AnnaBridge	189:f392fc9709a3	2294	* @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
AnnaBridge	189:f392fc9709a3	2295	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	2296	* @arg @ref LL_RCC_LSEDRIVE_LOW
AnnaBridge	189:f392fc9709a3	2297	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
AnnaBridge	189:f392fc9709a3	2298	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
AnnaBridge	189:f392fc9709a3	2299	* @arg @ref LL_RCC_LSEDRIVE_HIGH
AnnaBridge	189:f392fc9709a3	2300	*/
AnnaBridge	189:f392fc9709a3	2301	__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
AnnaBridge	189:f392fc9709a3	2302	{
AnnaBridge	189:f392fc9709a3	2303	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
AnnaBridge	189:f392fc9709a3	2304	}
AnnaBridge	189:f392fc9709a3	2305
AnnaBridge	189:f392fc9709a3	2306	/**
AnnaBridge	189:f392fc9709a3	2307	* @brief Enable Clock security system on LSE.
AnnaBridge	189:f392fc9709a3	2308	* @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
AnnaBridge	189:f392fc9709a3	2309	* @retval None
AnnaBridge	189:f392fc9709a3	2310	*/
AnnaBridge	189:f392fc9709a3	2311	__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
AnnaBridge	189:f392fc9709a3	2312	{
AnnaBridge	189:f392fc9709a3	2313	SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
AnnaBridge	189:f392fc9709a3	2314	}
AnnaBridge	189:f392fc9709a3	2315
AnnaBridge	189:f392fc9709a3	2316	/**
AnnaBridge	189:f392fc9709a3	2317	* @brief Disable Clock security system on LSE.
AnnaBridge	189:f392fc9709a3	2318	* @note Clock security system can be disabled only after a LSE
AnnaBridge	189:f392fc9709a3	2319	* failure detection. In that case it MUST be disabled by software.
AnnaBridge	189:f392fc9709a3	2320	* @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
AnnaBridge	189:f392fc9709a3	2321	* @retval None
AnnaBridge	189:f392fc9709a3	2322	*/
AnnaBridge	189:f392fc9709a3	2323	__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
AnnaBridge	189:f392fc9709a3	2324	{
AnnaBridge	189:f392fc9709a3	2325	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
AnnaBridge	189:f392fc9709a3	2326	}
AnnaBridge	189:f392fc9709a3	2327
AnnaBridge	189:f392fc9709a3	2328	/**
AnnaBridge	189:f392fc9709a3	2329	* @brief Check if LSE oscillator Ready
AnnaBridge	189:f392fc9709a3	2330	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
AnnaBridge	189:f392fc9709a3	2331	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2332	*/
AnnaBridge	189:f392fc9709a3	2333	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
AnnaBridge	189:f392fc9709a3	2334	{
AnnaBridge	189:f392fc9709a3	2335	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
AnnaBridge	189:f392fc9709a3	2336	}
AnnaBridge	189:f392fc9709a3	2337
AnnaBridge	189:f392fc9709a3	2338	/**
AnnaBridge	189:f392fc9709a3	2339	* @brief Check if CSS on LSE failure Detection
AnnaBridge	189:f392fc9709a3	2340	* @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
AnnaBridge	189:f392fc9709a3	2341	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2342	*/
AnnaBridge	189:f392fc9709a3	2343	__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
AnnaBridge	189:f392fc9709a3	2344	{
AnnaBridge	189:f392fc9709a3	2345	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD));
AnnaBridge	189:f392fc9709a3	2346	}
AnnaBridge	189:f392fc9709a3	2347
AnnaBridge	189:f392fc9709a3	2348	/**
AnnaBridge	189:f392fc9709a3	2349	* @}
AnnaBridge	189:f392fc9709a3	2350	*/
AnnaBridge	189:f392fc9709a3	2351
AnnaBridge	189:f392fc9709a3	2352	/** @defgroup RCC_LL_EF_LSI LSI
AnnaBridge	189:f392fc9709a3	2353	* @{
AnnaBridge	189:f392fc9709a3	2354	*/
AnnaBridge	189:f392fc9709a3	2355
AnnaBridge	189:f392fc9709a3	2356	/**
AnnaBridge	189:f392fc9709a3	2357	* @brief Enable LSI Oscillator
AnnaBridge	189:f392fc9709a3	2358	* @rmtoll CSR LSION LL_RCC_LSI_Enable
AnnaBridge	189:f392fc9709a3	2359	* @retval None
AnnaBridge	189:f392fc9709a3	2360	*/
AnnaBridge	189:f392fc9709a3	2361	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
AnnaBridge	189:f392fc9709a3	2362	{
AnnaBridge	189:f392fc9709a3	2363	SET_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	189:f392fc9709a3	2364	}
AnnaBridge	189:f392fc9709a3	2365
AnnaBridge	189:f392fc9709a3	2366	/**
AnnaBridge	189:f392fc9709a3	2367	* @brief Disable LSI Oscillator
AnnaBridge	189:f392fc9709a3	2368	* @rmtoll CSR LSION LL_RCC_LSI_Disable
AnnaBridge	189:f392fc9709a3	2369	* @retval None
AnnaBridge	189:f392fc9709a3	2370	*/
AnnaBridge	189:f392fc9709a3	2371	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
AnnaBridge	189:f392fc9709a3	2372	{
AnnaBridge	189:f392fc9709a3	2373	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	189:f392fc9709a3	2374	}
AnnaBridge	189:f392fc9709a3	2375
AnnaBridge	189:f392fc9709a3	2376	/**
AnnaBridge	189:f392fc9709a3	2377	* @brief Check if LSI is Ready
AnnaBridge	189:f392fc9709a3	2378	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
AnnaBridge	189:f392fc9709a3	2379	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2380	*/
AnnaBridge	189:f392fc9709a3	2381	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
AnnaBridge	189:f392fc9709a3	2382	{
AnnaBridge	189:f392fc9709a3	2383	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
AnnaBridge	189:f392fc9709a3	2384	}
AnnaBridge	189:f392fc9709a3	2385
AnnaBridge	189:f392fc9709a3	2386	/**
AnnaBridge	189:f392fc9709a3	2387	* @}
AnnaBridge	189:f392fc9709a3	2388	*/
AnnaBridge	189:f392fc9709a3	2389
AnnaBridge	189:f392fc9709a3	2390	/** @defgroup RCC_LL_EF_MSI MSI
AnnaBridge	189:f392fc9709a3	2391	* @{
AnnaBridge	189:f392fc9709a3	2392	*/
AnnaBridge	189:f392fc9709a3	2393
AnnaBridge	189:f392fc9709a3	2394	/**
AnnaBridge	189:f392fc9709a3	2395	* @brief Enable MSI oscillator
AnnaBridge	189:f392fc9709a3	2396	* @rmtoll CR MSION LL_RCC_MSI_Enable
AnnaBridge	189:f392fc9709a3	2397	* @retval None
AnnaBridge	189:f392fc9709a3	2398	*/
AnnaBridge	189:f392fc9709a3	2399	__STATIC_INLINE void LL_RCC_MSI_Enable(void)
AnnaBridge	189:f392fc9709a3	2400	{
AnnaBridge	189:f392fc9709a3	2401	SET_BIT(RCC->CR, RCC_CR_MSION);
AnnaBridge	189:f392fc9709a3	2402	}
AnnaBridge	189:f392fc9709a3	2403
AnnaBridge	189:f392fc9709a3	2404	/**
AnnaBridge	189:f392fc9709a3	2405	* @brief Disable MSI oscillator
AnnaBridge	189:f392fc9709a3	2406	* @rmtoll CR MSION LL_RCC_MSI_Disable
AnnaBridge	189:f392fc9709a3	2407	* @retval None
AnnaBridge	189:f392fc9709a3	2408	*/
AnnaBridge	189:f392fc9709a3	2409	__STATIC_INLINE void LL_RCC_MSI_Disable(void)
AnnaBridge	189:f392fc9709a3	2410	{
AnnaBridge	189:f392fc9709a3	2411	CLEAR_BIT(RCC->CR, RCC_CR_MSION);
AnnaBridge	189:f392fc9709a3	2412	}
AnnaBridge	189:f392fc9709a3	2413
AnnaBridge	189:f392fc9709a3	2414	/**
AnnaBridge	189:f392fc9709a3	2415	* @brief Check if MSI oscillator Ready
AnnaBridge	189:f392fc9709a3	2416	* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
AnnaBridge	189:f392fc9709a3	2417	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2418	*/
AnnaBridge	189:f392fc9709a3	2419	__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
AnnaBridge	189:f392fc9709a3	2420	{
AnnaBridge	189:f392fc9709a3	2421	return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
AnnaBridge	189:f392fc9709a3	2422	}
AnnaBridge	189:f392fc9709a3	2423
AnnaBridge	189:f392fc9709a3	2424	/**
AnnaBridge	189:f392fc9709a3	2425	* @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
AnnaBridge	189:f392fc9709a3	2426	* @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
AnnaBridge	189:f392fc9709a3	2427	* and ready (LSERDY set by hardware)
AnnaBridge	189:f392fc9709a3	2428	* @note hardware protection to avoid enabling MSIPLLEN if LSE is not
AnnaBridge	189:f392fc9709a3	2429	* ready
AnnaBridge	189:f392fc9709a3	2430	* @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
AnnaBridge	189:f392fc9709a3	2431	* @retval None
AnnaBridge	189:f392fc9709a3	2432	*/
AnnaBridge	189:f392fc9709a3	2433	__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
AnnaBridge	189:f392fc9709a3	2434	{
AnnaBridge	189:f392fc9709a3	2435	SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
AnnaBridge	189:f392fc9709a3	2436	}
AnnaBridge	189:f392fc9709a3	2437
AnnaBridge	189:f392fc9709a3	2438	/**
AnnaBridge	189:f392fc9709a3	2439	* @brief Disable MSI-PLL mode
AnnaBridge	189:f392fc9709a3	2440	* @note cleared by hardware when LSE is disabled (LSEON = 0) or when
AnnaBridge	189:f392fc9709a3	2441	* the Clock Security System on LSE detects a LSE failure
AnnaBridge	189:f392fc9709a3	2442	* @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
AnnaBridge	189:f392fc9709a3	2443	* @retval None
AnnaBridge	189:f392fc9709a3	2444	*/
AnnaBridge	189:f392fc9709a3	2445	__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
AnnaBridge	189:f392fc9709a3	2446	{
AnnaBridge	189:f392fc9709a3	2447	CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
AnnaBridge	189:f392fc9709a3	2448	}
AnnaBridge	189:f392fc9709a3	2449
AnnaBridge	189:f392fc9709a3	2450	/**
AnnaBridge	189:f392fc9709a3	2451	* @brief Enable MSI clock range selection with MSIRANGE register
AnnaBridge	189:f392fc9709a3	2452	* @note Write 0 has no effect. After a standby or a reset
AnnaBridge	189:f392fc9709a3	2453	* MSIRGSEL is at 0 and the MSI range value is provided by
AnnaBridge	189:f392fc9709a3	2454	* MSISRANGE
AnnaBridge	189:f392fc9709a3	2455	* @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
AnnaBridge	189:f392fc9709a3	2456	* @retval None
AnnaBridge	189:f392fc9709a3	2457	*/
AnnaBridge	189:f392fc9709a3	2458	__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
AnnaBridge	189:f392fc9709a3	2459	{
AnnaBridge	189:f392fc9709a3	2460	SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
AnnaBridge	189:f392fc9709a3	2461	}
AnnaBridge	189:f392fc9709a3	2462
AnnaBridge	189:f392fc9709a3	2463	/**
AnnaBridge	189:f392fc9709a3	2464	* @brief Check if MSI clock range is selected with MSIRANGE register
AnnaBridge	189:f392fc9709a3	2465	* @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
AnnaBridge	189:f392fc9709a3	2466	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2467	*/
AnnaBridge	189:f392fc9709a3	2468	__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
AnnaBridge	189:f392fc9709a3	2469	{
AnnaBridge	189:f392fc9709a3	2470	return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL));
AnnaBridge	189:f392fc9709a3	2471	}
AnnaBridge	189:f392fc9709a3	2472
AnnaBridge	189:f392fc9709a3	2473	/**
AnnaBridge	189:f392fc9709a3	2474	* @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
AnnaBridge	189:f392fc9709a3	2475	* @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
AnnaBridge	189:f392fc9709a3	2476	* @param Range This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2477	* @arg @ref LL_RCC_MSIRANGE_0
AnnaBridge	189:f392fc9709a3	2478	* @arg @ref LL_RCC_MSIRANGE_1
AnnaBridge	189:f392fc9709a3	2479	* @arg @ref LL_RCC_MSIRANGE_2
AnnaBridge	189:f392fc9709a3	2480	* @arg @ref LL_RCC_MSIRANGE_3
AnnaBridge	189:f392fc9709a3	2481	* @arg @ref LL_RCC_MSIRANGE_4
AnnaBridge	189:f392fc9709a3	2482	* @arg @ref LL_RCC_MSIRANGE_5
AnnaBridge	189:f392fc9709a3	2483	* @arg @ref LL_RCC_MSIRANGE_6
AnnaBridge	189:f392fc9709a3	2484	* @arg @ref LL_RCC_MSIRANGE_7
AnnaBridge	189:f392fc9709a3	2485	* @arg @ref LL_RCC_MSIRANGE_8
AnnaBridge	189:f392fc9709a3	2486	* @arg @ref LL_RCC_MSIRANGE_9
AnnaBridge	189:f392fc9709a3	2487	* @arg @ref LL_RCC_MSIRANGE_10
AnnaBridge	189:f392fc9709a3	2488	* @arg @ref LL_RCC_MSIRANGE_11
AnnaBridge	189:f392fc9709a3	2489	* @retval None
AnnaBridge	189:f392fc9709a3	2490	*/
AnnaBridge	189:f392fc9709a3	2491	__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
AnnaBridge	189:f392fc9709a3	2492	{
AnnaBridge	189:f392fc9709a3	2493	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
AnnaBridge	189:f392fc9709a3	2494	}
AnnaBridge	189:f392fc9709a3	2495
AnnaBridge	189:f392fc9709a3	2496	/**
AnnaBridge	189:f392fc9709a3	2497	* @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
AnnaBridge	189:f392fc9709a3	2498	* @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
AnnaBridge	189:f392fc9709a3	2499	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	2500	* @arg @ref LL_RCC_MSIRANGE_0
AnnaBridge	189:f392fc9709a3	2501	* @arg @ref LL_RCC_MSIRANGE_1
AnnaBridge	189:f392fc9709a3	2502	* @arg @ref LL_RCC_MSIRANGE_2
AnnaBridge	189:f392fc9709a3	2503	* @arg @ref LL_RCC_MSIRANGE_3
AnnaBridge	189:f392fc9709a3	2504	* @arg @ref LL_RCC_MSIRANGE_4
AnnaBridge	189:f392fc9709a3	2505	* @arg @ref LL_RCC_MSIRANGE_5
AnnaBridge	189:f392fc9709a3	2506	* @arg @ref LL_RCC_MSIRANGE_6
AnnaBridge	189:f392fc9709a3	2507	* @arg @ref LL_RCC_MSIRANGE_7
AnnaBridge	189:f392fc9709a3	2508	* @arg @ref LL_RCC_MSIRANGE_8
AnnaBridge	189:f392fc9709a3	2509	* @arg @ref LL_RCC_MSIRANGE_9
AnnaBridge	189:f392fc9709a3	2510	* @arg @ref LL_RCC_MSIRANGE_10
AnnaBridge	189:f392fc9709a3	2511	* @arg @ref LL_RCC_MSIRANGE_11
AnnaBridge	189:f392fc9709a3	2512	*/
AnnaBridge	189:f392fc9709a3	2513	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
AnnaBridge	189:f392fc9709a3	2514	{
AnnaBridge	189:f392fc9709a3	2515	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
AnnaBridge	189:f392fc9709a3	2516	}
AnnaBridge	189:f392fc9709a3	2517
AnnaBridge	189:f392fc9709a3	2518	/**
AnnaBridge	189:f392fc9709a3	2519	* @brief Configure MSI range used after standby
AnnaBridge	189:f392fc9709a3	2520	* @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby
AnnaBridge	189:f392fc9709a3	2521	* @param Range This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2522	* @arg @ref LL_RCC_MSISRANGE_4
AnnaBridge	189:f392fc9709a3	2523	* @arg @ref LL_RCC_MSISRANGE_5
AnnaBridge	189:f392fc9709a3	2524	* @arg @ref LL_RCC_MSISRANGE_6
AnnaBridge	189:f392fc9709a3	2525	* @arg @ref LL_RCC_MSISRANGE_7
AnnaBridge	189:f392fc9709a3	2526	* @retval None
AnnaBridge	189:f392fc9709a3	2527	*/
AnnaBridge	189:f392fc9709a3	2528	__STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
AnnaBridge	189:f392fc9709a3	2529	{
AnnaBridge	189:f392fc9709a3	2530	MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
AnnaBridge	189:f392fc9709a3	2531	}
AnnaBridge	189:f392fc9709a3	2532
AnnaBridge	189:f392fc9709a3	2533	/**
AnnaBridge	189:f392fc9709a3	2534	* @brief Get MSI range used after standby
AnnaBridge	189:f392fc9709a3	2535	* @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby
AnnaBridge	189:f392fc9709a3	2536	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	2537	* @arg @ref LL_RCC_MSISRANGE_4
AnnaBridge	189:f392fc9709a3	2538	* @arg @ref LL_RCC_MSISRANGE_5
AnnaBridge	189:f392fc9709a3	2539	* @arg @ref LL_RCC_MSISRANGE_6
AnnaBridge	189:f392fc9709a3	2540	* @arg @ref LL_RCC_MSISRANGE_7
AnnaBridge	189:f392fc9709a3	2541	*/
AnnaBridge	189:f392fc9709a3	2542	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
AnnaBridge	189:f392fc9709a3	2543	{
AnnaBridge	189:f392fc9709a3	2544	return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
AnnaBridge	189:f392fc9709a3	2545	}
AnnaBridge	189:f392fc9709a3	2546
AnnaBridge	189:f392fc9709a3	2547	/**
AnnaBridge	189:f392fc9709a3	2548	* @brief Get MSI Calibration value
AnnaBridge	189:f392fc9709a3	2549	* @note When MSITRIM is written, MSICAL is updated with the sum of
AnnaBridge	189:f392fc9709a3	2550	* MSITRIM and the factory trim value
AnnaBridge	189:f392fc9709a3	2551	* @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
AnnaBridge	189:f392fc9709a3	2552	* @retval Between Min_Data = 0 and Max_Data = 255
AnnaBridge	189:f392fc9709a3	2553	*/
AnnaBridge	189:f392fc9709a3	2554	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
AnnaBridge	189:f392fc9709a3	2555	{
AnnaBridge	189:f392fc9709a3	2556	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
AnnaBridge	189:f392fc9709a3	2557	}
AnnaBridge	189:f392fc9709a3	2558
AnnaBridge	189:f392fc9709a3	2559	/**
AnnaBridge	189:f392fc9709a3	2560	* @brief Set MSI Calibration trimming
AnnaBridge	189:f392fc9709a3	2561	* @note user-programmable trimming value that is added to the MSICAL
AnnaBridge	189:f392fc9709a3	2562	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
AnnaBridge	189:f392fc9709a3	2563	* @param Value Between Min_Data = 0 and Max_Data = 255
AnnaBridge	189:f392fc9709a3	2564	* @retval None
AnnaBridge	189:f392fc9709a3	2565	*/
AnnaBridge	189:f392fc9709a3	2566	__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	189:f392fc9709a3	2567	{
AnnaBridge	189:f392fc9709a3	2568	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
AnnaBridge	189:f392fc9709a3	2569	}
AnnaBridge	189:f392fc9709a3	2570
AnnaBridge	189:f392fc9709a3	2571	/**
AnnaBridge	189:f392fc9709a3	2572	* @brief Get MSI Calibration trimming
AnnaBridge	189:f392fc9709a3	2573	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
AnnaBridge	189:f392fc9709a3	2574	* @retval Between 0 and 255
AnnaBridge	189:f392fc9709a3	2575	*/
AnnaBridge	189:f392fc9709a3	2576	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
AnnaBridge	189:f392fc9709a3	2577	{
AnnaBridge	189:f392fc9709a3	2578	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
AnnaBridge	189:f392fc9709a3	2579	}
AnnaBridge	189:f392fc9709a3	2580
AnnaBridge	189:f392fc9709a3	2581	/**
AnnaBridge	189:f392fc9709a3	2582	* @}
AnnaBridge	189:f392fc9709a3	2583	*/
AnnaBridge	189:f392fc9709a3	2584
AnnaBridge	189:f392fc9709a3	2585	/** @defgroup RCC_LL_EF_LSCO LSCO
AnnaBridge	189:f392fc9709a3	2586	* @{
AnnaBridge	189:f392fc9709a3	2587	*/
AnnaBridge	189:f392fc9709a3	2588
AnnaBridge	189:f392fc9709a3	2589	/**
AnnaBridge	189:f392fc9709a3	2590	* @brief Enable Low speed clock
AnnaBridge	189:f392fc9709a3	2591	* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
AnnaBridge	189:f392fc9709a3	2592	* @retval None
AnnaBridge	189:f392fc9709a3	2593	*/
AnnaBridge	189:f392fc9709a3	2594	__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
AnnaBridge	189:f392fc9709a3	2595	{
AnnaBridge	189:f392fc9709a3	2596	SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
AnnaBridge	189:f392fc9709a3	2597	}
AnnaBridge	189:f392fc9709a3	2598
AnnaBridge	189:f392fc9709a3	2599	/**
AnnaBridge	189:f392fc9709a3	2600	* @brief Disable Low speed clock
AnnaBridge	189:f392fc9709a3	2601	* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
AnnaBridge	189:f392fc9709a3	2602	* @retval None
AnnaBridge	189:f392fc9709a3	2603	*/
AnnaBridge	189:f392fc9709a3	2604	__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
AnnaBridge	189:f392fc9709a3	2605	{
AnnaBridge	189:f392fc9709a3	2606	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
AnnaBridge	189:f392fc9709a3	2607	}
AnnaBridge	189:f392fc9709a3	2608
AnnaBridge	189:f392fc9709a3	2609	/**
AnnaBridge	189:f392fc9709a3	2610	* @brief Configure Low speed clock selection
AnnaBridge	189:f392fc9709a3	2611	* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
AnnaBridge	189:f392fc9709a3	2612	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2613	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	2614	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	2615	* @retval None
AnnaBridge	189:f392fc9709a3	2616	*/
AnnaBridge	189:f392fc9709a3	2617	__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
AnnaBridge	189:f392fc9709a3	2618	{
AnnaBridge	189:f392fc9709a3	2619	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
AnnaBridge	189:f392fc9709a3	2620	}
AnnaBridge	189:f392fc9709a3	2621
AnnaBridge	189:f392fc9709a3	2622	/**
AnnaBridge	189:f392fc9709a3	2623	* @brief Get Low speed clock selection
AnnaBridge	189:f392fc9709a3	2624	* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
AnnaBridge	189:f392fc9709a3	2625	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	2626	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	2627	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	2628	*/
AnnaBridge	189:f392fc9709a3	2629	__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
AnnaBridge	189:f392fc9709a3	2630	{
AnnaBridge	189:f392fc9709a3	2631	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
AnnaBridge	189:f392fc9709a3	2632	}
AnnaBridge	189:f392fc9709a3	2633
AnnaBridge	189:f392fc9709a3	2634	/**
AnnaBridge	189:f392fc9709a3	2635	* @}
AnnaBridge	189:f392fc9709a3	2636	*/
AnnaBridge	189:f392fc9709a3	2637
AnnaBridge	189:f392fc9709a3	2638	/** @defgroup RCC_LL_EF_System System
AnnaBridge	189:f392fc9709a3	2639	* @{
AnnaBridge	189:f392fc9709a3	2640	*/
AnnaBridge	189:f392fc9709a3	2641
AnnaBridge	189:f392fc9709a3	2642	/**
AnnaBridge	189:f392fc9709a3	2643	* @brief Configure the system clock source
AnnaBridge	189:f392fc9709a3	2644	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
AnnaBridge	189:f392fc9709a3	2645	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2646	* @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
AnnaBridge	189:f392fc9709a3	2647	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	2648	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
AnnaBridge	189:f392fc9709a3	2649	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	2650	* @retval None
AnnaBridge	189:f392fc9709a3	2651	*/
AnnaBridge	189:f392fc9709a3	2652	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
AnnaBridge	189:f392fc9709a3	2653	{
AnnaBridge	189:f392fc9709a3	2654	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
AnnaBridge	189:f392fc9709a3	2655	}
AnnaBridge	189:f392fc9709a3	2656
AnnaBridge	189:f392fc9709a3	2657	/**
AnnaBridge	189:f392fc9709a3	2658	* @brief Get the system clock source
AnnaBridge	189:f392fc9709a3	2659	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
AnnaBridge	189:f392fc9709a3	2660	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	2661	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
AnnaBridge	189:f392fc9709a3	2662	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
AnnaBridge	189:f392fc9709a3	2663	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
AnnaBridge	189:f392fc9709a3	2664	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
AnnaBridge	189:f392fc9709a3	2665	*/
AnnaBridge	189:f392fc9709a3	2666	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
AnnaBridge	189:f392fc9709a3	2667	{
AnnaBridge	189:f392fc9709a3	2668	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
AnnaBridge	189:f392fc9709a3	2669	}
AnnaBridge	189:f392fc9709a3	2670
AnnaBridge	189:f392fc9709a3	2671	/**
AnnaBridge	189:f392fc9709a3	2672	* @brief Set AHB prescaler
AnnaBridge	189:f392fc9709a3	2673	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
AnnaBridge	189:f392fc9709a3	2674	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2675	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	189:f392fc9709a3	2676	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	189:f392fc9709a3	2677	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	189:f392fc9709a3	2678	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	189:f392fc9709a3	2679	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	189:f392fc9709a3	2680	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	189:f392fc9709a3	2681	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	189:f392fc9709a3	2682	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	189:f392fc9709a3	2683	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	189:f392fc9709a3	2684	* @retval None
AnnaBridge	189:f392fc9709a3	2685	*/
AnnaBridge	189:f392fc9709a3	2686	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
AnnaBridge	189:f392fc9709a3	2687	{
AnnaBridge	189:f392fc9709a3	2688	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
AnnaBridge	189:f392fc9709a3	2689	}
AnnaBridge	189:f392fc9709a3	2690
AnnaBridge	189:f392fc9709a3	2691	/**
AnnaBridge	189:f392fc9709a3	2692	* @brief Set APB1 prescaler
AnnaBridge	189:f392fc9709a3	2693	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
AnnaBridge	189:f392fc9709a3	2694	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2695	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	189:f392fc9709a3	2696	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	189:f392fc9709a3	2697	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	189:f392fc9709a3	2698	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	189:f392fc9709a3	2699	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	189:f392fc9709a3	2700	* @retval None
AnnaBridge	189:f392fc9709a3	2701	*/
AnnaBridge	189:f392fc9709a3	2702	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
AnnaBridge	189:f392fc9709a3	2703	{
AnnaBridge	189:f392fc9709a3	2704	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
AnnaBridge	189:f392fc9709a3	2705	}
AnnaBridge	189:f392fc9709a3	2706
AnnaBridge	189:f392fc9709a3	2707	/**
AnnaBridge	189:f392fc9709a3	2708	* @brief Set APB2 prescaler
AnnaBridge	189:f392fc9709a3	2709	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
AnnaBridge	189:f392fc9709a3	2710	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2711	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	189:f392fc9709a3	2712	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	189:f392fc9709a3	2713	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	189:f392fc9709a3	2714	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	189:f392fc9709a3	2715	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	189:f392fc9709a3	2716	* @retval None
AnnaBridge	189:f392fc9709a3	2717	*/
AnnaBridge	189:f392fc9709a3	2718	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
AnnaBridge	189:f392fc9709a3	2719	{
AnnaBridge	189:f392fc9709a3	2720	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
AnnaBridge	189:f392fc9709a3	2721	}
AnnaBridge	189:f392fc9709a3	2722
AnnaBridge	189:f392fc9709a3	2723	/**
AnnaBridge	189:f392fc9709a3	2724	* @brief Get AHB prescaler
AnnaBridge	189:f392fc9709a3	2725	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
AnnaBridge	189:f392fc9709a3	2726	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	2727	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	189:f392fc9709a3	2728	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	189:f392fc9709a3	2729	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	189:f392fc9709a3	2730	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	189:f392fc9709a3	2731	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	189:f392fc9709a3	2732	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	189:f392fc9709a3	2733	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	189:f392fc9709a3	2734	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	189:f392fc9709a3	2735	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	189:f392fc9709a3	2736	*/
AnnaBridge	189:f392fc9709a3	2737	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
AnnaBridge	189:f392fc9709a3	2738	{
AnnaBridge	189:f392fc9709a3	2739	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
AnnaBridge	189:f392fc9709a3	2740	}
AnnaBridge	189:f392fc9709a3	2741
AnnaBridge	189:f392fc9709a3	2742	/**
AnnaBridge	189:f392fc9709a3	2743	* @brief Get APB1 prescaler
AnnaBridge	189:f392fc9709a3	2744	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
AnnaBridge	189:f392fc9709a3	2745	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	2746	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	189:f392fc9709a3	2747	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	189:f392fc9709a3	2748	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	189:f392fc9709a3	2749	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	189:f392fc9709a3	2750	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	189:f392fc9709a3	2751	*/
AnnaBridge	189:f392fc9709a3	2752	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
AnnaBridge	189:f392fc9709a3	2753	{
AnnaBridge	189:f392fc9709a3	2754	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
AnnaBridge	189:f392fc9709a3	2755	}
AnnaBridge	189:f392fc9709a3	2756
AnnaBridge	189:f392fc9709a3	2757	/**
AnnaBridge	189:f392fc9709a3	2758	* @brief Get APB2 prescaler
AnnaBridge	189:f392fc9709a3	2759	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
AnnaBridge	189:f392fc9709a3	2760	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	2761	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	189:f392fc9709a3	2762	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	189:f392fc9709a3	2763	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	189:f392fc9709a3	2764	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	189:f392fc9709a3	2765	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	189:f392fc9709a3	2766	*/
AnnaBridge	189:f392fc9709a3	2767	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
AnnaBridge	189:f392fc9709a3	2768	{
AnnaBridge	189:f392fc9709a3	2769	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
AnnaBridge	189:f392fc9709a3	2770	}
AnnaBridge	189:f392fc9709a3	2771
AnnaBridge	189:f392fc9709a3	2772	/**
AnnaBridge	189:f392fc9709a3	2773	* @brief Set Clock After Wake-Up From Stop mode
AnnaBridge	189:f392fc9709a3	2774	* @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
AnnaBridge	189:f392fc9709a3	2775	* @param Clock This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2776	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
AnnaBridge	189:f392fc9709a3	2777	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
AnnaBridge	189:f392fc9709a3	2778	* @retval None
AnnaBridge	189:f392fc9709a3	2779	*/
AnnaBridge	189:f392fc9709a3	2780	__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
AnnaBridge	189:f392fc9709a3	2781	{
AnnaBridge	189:f392fc9709a3	2782	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
AnnaBridge	189:f392fc9709a3	2783	}
AnnaBridge	189:f392fc9709a3	2784
AnnaBridge	189:f392fc9709a3	2785	/**
AnnaBridge	189:f392fc9709a3	2786	* @brief Get Clock After Wake-Up From Stop mode
AnnaBridge	189:f392fc9709a3	2787	* @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
AnnaBridge	189:f392fc9709a3	2788	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	2789	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
AnnaBridge	189:f392fc9709a3	2790	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
AnnaBridge	189:f392fc9709a3	2791	*/
AnnaBridge	189:f392fc9709a3	2792	__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
AnnaBridge	189:f392fc9709a3	2793	{
AnnaBridge	189:f392fc9709a3	2794	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
AnnaBridge	189:f392fc9709a3	2795	}
AnnaBridge	189:f392fc9709a3	2796
AnnaBridge	189:f392fc9709a3	2797	/**
AnnaBridge	189:f392fc9709a3	2798	* @}
AnnaBridge	189:f392fc9709a3	2799	*/
AnnaBridge	189:f392fc9709a3	2800
AnnaBridge	189:f392fc9709a3	2801	/** @defgroup RCC_LL_EF_MCO MCO
AnnaBridge	189:f392fc9709a3	2802	* @{
AnnaBridge	189:f392fc9709a3	2803	*/
AnnaBridge	189:f392fc9709a3	2804
AnnaBridge	189:f392fc9709a3	2805	/**
AnnaBridge	189:f392fc9709a3	2806	* @brief Configure MCOx
AnnaBridge	189:f392fc9709a3	2807	* @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
AnnaBridge	189:f392fc9709a3	2808	* CFGR MCOPRE LL_RCC_ConfigMCO
AnnaBridge	189:f392fc9709a3	2809	* @param MCOxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2810	* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
AnnaBridge	189:f392fc9709a3	2811	* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	2812	* @arg @ref LL_RCC_MCO1SOURCE_MSI
AnnaBridge	189:f392fc9709a3	2813	* @arg @ref LL_RCC_MCO1SOURCE_HSI
AnnaBridge	189:f392fc9709a3	2814	* @arg @ref LL_RCC_MCO1SOURCE_HSE
AnnaBridge	189:f392fc9709a3	2815	* @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
AnnaBridge	189:f392fc9709a3	2816	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
AnnaBridge	189:f392fc9709a3	2817	* @arg @ref LL_RCC_MCO1SOURCE_LSI
AnnaBridge	189:f392fc9709a3	2818	* @arg @ref LL_RCC_MCO1SOURCE_LSE
AnnaBridge	189:f392fc9709a3	2819	*
AnnaBridge	189:f392fc9709a3	2820	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	2821	* @param MCOxPrescaler This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2822	* @arg @ref LL_RCC_MCO1_DIV_1
AnnaBridge	189:f392fc9709a3	2823	* @arg @ref LL_RCC_MCO1_DIV_2
AnnaBridge	189:f392fc9709a3	2824	* @arg @ref LL_RCC_MCO1_DIV_4
AnnaBridge	189:f392fc9709a3	2825	* @arg @ref LL_RCC_MCO1_DIV_8
AnnaBridge	189:f392fc9709a3	2826	* @arg @ref LL_RCC_MCO1_DIV_16
AnnaBridge	189:f392fc9709a3	2827	* @retval None
AnnaBridge	189:f392fc9709a3	2828	*/
AnnaBridge	189:f392fc9709a3	2829	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
AnnaBridge	189:f392fc9709a3	2830	{
AnnaBridge	189:f392fc9709a3	2831	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE, MCOxSource \| MCOxPrescaler);
AnnaBridge	189:f392fc9709a3	2832	}
AnnaBridge	189:f392fc9709a3	2833
AnnaBridge	189:f392fc9709a3	2834	/**
AnnaBridge	189:f392fc9709a3	2835	* @}
AnnaBridge	189:f392fc9709a3	2836	*/
AnnaBridge	189:f392fc9709a3	2837
AnnaBridge	189:f392fc9709a3	2838	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
AnnaBridge	189:f392fc9709a3	2839	* @{
AnnaBridge	189:f392fc9709a3	2840	*/
AnnaBridge	189:f392fc9709a3	2841
AnnaBridge	189:f392fc9709a3	2842	/**
AnnaBridge	189:f392fc9709a3	2843	* @brief Configure USARTx clock source
AnnaBridge	189:f392fc9709a3	2844	* @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
AnnaBridge	189:f392fc9709a3	2845	* @param USARTxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2846	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
AnnaBridge	189:f392fc9709a3	2847	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	2848	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	2849	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	2850	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	2851	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	2852	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	2853	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	2854	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
AnnaBridge	189:f392fc9709a3	2855	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
AnnaBridge	189:f392fc9709a3	2856	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
AnnaBridge	189:f392fc9709a3	2857	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
AnnaBridge	189:f392fc9709a3	2858	*
AnnaBridge	189:f392fc9709a3	2859	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	2860	* @retval None
AnnaBridge	189:f392fc9709a3	2861	*/
AnnaBridge	189:f392fc9709a3	2862	__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
AnnaBridge	189:f392fc9709a3	2863	{
AnnaBridge	189:f392fc9709a3	2864	MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF));
AnnaBridge	189:f392fc9709a3	2865	}
AnnaBridge	189:f392fc9709a3	2866
AnnaBridge	189:f392fc9709a3	2867	#if defined(UART4) \|\| defined(UART5)
AnnaBridge	189:f392fc9709a3	2868	/**
AnnaBridge	189:f392fc9709a3	2869	* @brief Configure UARTx clock source
AnnaBridge	189:f392fc9709a3	2870	* @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
AnnaBridge	189:f392fc9709a3	2871	* @param UARTxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2872	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	2873	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	2874	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	2875	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	2876	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	2877	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	2878	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	2879	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	2880	* @retval None
AnnaBridge	189:f392fc9709a3	2881	*/
AnnaBridge	189:f392fc9709a3	2882	__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
AnnaBridge	189:f392fc9709a3	2883	{
AnnaBridge	189:f392fc9709a3	2884	MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF));
AnnaBridge	189:f392fc9709a3	2885	}
AnnaBridge	189:f392fc9709a3	2886	#endif /* UART4 \|\| UART5 */
AnnaBridge	189:f392fc9709a3	2887
AnnaBridge	189:f392fc9709a3	2888	/**
AnnaBridge	189:f392fc9709a3	2889	* @brief Configure LPUART1x clock source
AnnaBridge	189:f392fc9709a3	2890	* @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
AnnaBridge	189:f392fc9709a3	2891	* @param LPUARTxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2892	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	2893	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	2894	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	2895	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	2896	* @retval None
AnnaBridge	189:f392fc9709a3	2897	*/
AnnaBridge	189:f392fc9709a3	2898	__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
AnnaBridge	189:f392fc9709a3	2899	{
AnnaBridge	189:f392fc9709a3	2900	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
AnnaBridge	189:f392fc9709a3	2901	}
AnnaBridge	189:f392fc9709a3	2902
AnnaBridge	189:f392fc9709a3	2903	/**
AnnaBridge	189:f392fc9709a3	2904	* @brief Configure I2Cx clock source
AnnaBridge	189:f392fc9709a3	2905	* @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
AnnaBridge	189:f392fc9709a3	2906	* @param I2CxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2907	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	2908	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	2909	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	2910	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
AnnaBridge	189:f392fc9709a3	2911	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
AnnaBridge	189:f392fc9709a3	2912	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
AnnaBridge	189:f392fc9709a3	2913	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	2914	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	2915	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	2916	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
AnnaBridge	189:f392fc9709a3	2917	* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
AnnaBridge	189:f392fc9709a3	2918	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
AnnaBridge	189:f392fc9709a3	2919	*
AnnaBridge	189:f392fc9709a3	2920	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	2921	* @retval None
AnnaBridge	189:f392fc9709a3	2922	*/
AnnaBridge	189:f392fc9709a3	2923	__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
AnnaBridge	189:f392fc9709a3	2924	{
AnnaBridge	189:f392fc9709a3	2925	__IO uint32_t reg = (__IO uint32_t )(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
AnnaBridge	189:f392fc9709a3	2926	MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U)));
AnnaBridge	189:f392fc9709a3	2927	}
AnnaBridge	189:f392fc9709a3	2928
AnnaBridge	189:f392fc9709a3	2929	/**
AnnaBridge	189:f392fc9709a3	2930	* @brief Configure LPTIMx clock source
AnnaBridge	189:f392fc9709a3	2931	* @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
AnnaBridge	189:f392fc9709a3	2932	* @param LPTIMxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2933	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	2934	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	2935	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	2936	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	2937	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	2938	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	2939	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	2940	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	2941	* @retval None
AnnaBridge	189:f392fc9709a3	2942	*/
AnnaBridge	189:f392fc9709a3	2943	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
AnnaBridge	189:f392fc9709a3	2944	{
AnnaBridge	189:f392fc9709a3	2945	MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
AnnaBridge	189:f392fc9709a3	2946	}
AnnaBridge	189:f392fc9709a3	2947
AnnaBridge	189:f392fc9709a3	2948	/**
AnnaBridge	189:f392fc9709a3	2949	* @brief Configure SAIx clock source
AnnaBridge	189:f392fc9709a3	2950	@if STM32L4S9xx
AnnaBridge	189:f392fc9709a3	2951	* @rmtoll CCIPR2 SAIxSEL LL_RCC_SetSAIClockSource
AnnaBridge	189:f392fc9709a3	2952	@else
AnnaBridge	189:f392fc9709a3	2953	* @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource
AnnaBridge	189:f392fc9709a3	2954	@endif
AnnaBridge	189:f392fc9709a3	2955	* @param SAIxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2956	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
AnnaBridge	189:f392fc9709a3	2957	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
AnnaBridge	189:f392fc9709a3	2958	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	2959	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
AnnaBridge	189:f392fc9709a3	2960	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
AnnaBridge	189:f392fc9709a3	2961	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
AnnaBridge	189:f392fc9709a3	2962	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
AnnaBridge	189:f392fc9709a3	2963	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
AnnaBridge	189:f392fc9709a3	2964	*
AnnaBridge	189:f392fc9709a3	2965	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	2966	* @retval None
AnnaBridge	189:f392fc9709a3	2967	*/
AnnaBridge	189:f392fc9709a3	2968	__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
AnnaBridge	189:f392fc9709a3	2969	{
AnnaBridge	189:f392fc9709a3	2970	#if defined(RCC_CCIPR2_SAI1SEL)
AnnaBridge	189:f392fc9709a3	2971	MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
AnnaBridge	189:f392fc9709a3	2972	#else
AnnaBridge	189:f392fc9709a3	2973	MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
AnnaBridge	189:f392fc9709a3	2974	#endif /* RCC_CCIPR2_SAI1SEL */
AnnaBridge	189:f392fc9709a3	2975	}
AnnaBridge	189:f392fc9709a3	2976
AnnaBridge	189:f392fc9709a3	2977	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	189:f392fc9709a3	2978	/**
AnnaBridge	189:f392fc9709a3	2979	* @brief Configure SDMMC1 kernel clock source
AnnaBridge	189:f392fc9709a3	2980	* @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource
AnnaBridge	189:f392fc9709a3	2981	* @param SDMMCxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2982	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
AnnaBridge	189:f392fc9709a3	2983	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP (*)
AnnaBridge	189:f392fc9709a3	2984	*
AnnaBridge	189:f392fc9709a3	2985	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	2986	* @retval None
AnnaBridge	189:f392fc9709a3	2987	*/
AnnaBridge	189:f392fc9709a3	2988	__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)
AnnaBridge	189:f392fc9709a3	2989	{
AnnaBridge	189:f392fc9709a3	2990	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);
AnnaBridge	189:f392fc9709a3	2991	}
AnnaBridge	189:f392fc9709a3	2992	#endif /* RCC_CCIPR2_SDMMCSEL */
AnnaBridge	189:f392fc9709a3	2993
AnnaBridge	189:f392fc9709a3	2994	/**
AnnaBridge	189:f392fc9709a3	2995	* @brief Configure SDMMC1 clock source
AnnaBridge	189:f392fc9709a3	2996	* @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource
AnnaBridge	189:f392fc9709a3	2997	* @param SDMMCxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2998	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
AnnaBridge	189:f392fc9709a3	2999	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
AnnaBridge	189:f392fc9709a3	3000	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
AnnaBridge	189:f392fc9709a3	3001	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	3002	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
AnnaBridge	189:f392fc9709a3	3003	*
AnnaBridge	189:f392fc9709a3	3004	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3005	* @retval None
AnnaBridge	189:f392fc9709a3	3006	*/
AnnaBridge	189:f392fc9709a3	3007	__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
AnnaBridge	189:f392fc9709a3	3008	{
AnnaBridge	189:f392fc9709a3	3009	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
AnnaBridge	189:f392fc9709a3	3010	}
AnnaBridge	189:f392fc9709a3	3011
AnnaBridge	189:f392fc9709a3	3012	/**
AnnaBridge	189:f392fc9709a3	3013	* @brief Configure RNG clock source
AnnaBridge	189:f392fc9709a3	3014	* @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
AnnaBridge	189:f392fc9709a3	3015	* @param RNGxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3016	* @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
AnnaBridge	189:f392fc9709a3	3017	* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
AnnaBridge	189:f392fc9709a3	3018	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
AnnaBridge	189:f392fc9709a3	3019	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	3020	* @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3021	*
AnnaBridge	189:f392fc9709a3	3022	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3023	* @retval None
AnnaBridge	189:f392fc9709a3	3024	*/
AnnaBridge	189:f392fc9709a3	3025	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
AnnaBridge	189:f392fc9709a3	3026	{
AnnaBridge	189:f392fc9709a3	3027	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
AnnaBridge	189:f392fc9709a3	3028	}
AnnaBridge	189:f392fc9709a3	3029
AnnaBridge	189:f392fc9709a3	3030	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	189:f392fc9709a3	3031	/**
AnnaBridge	189:f392fc9709a3	3032	* @brief Configure USB clock source
AnnaBridge	189:f392fc9709a3	3033	* @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
AnnaBridge	189:f392fc9709a3	3034	* @param USBxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3035	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
AnnaBridge	189:f392fc9709a3	3036	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
AnnaBridge	189:f392fc9709a3	3037	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
AnnaBridge	189:f392fc9709a3	3038	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	3039	* @arg @ref LL_RCC_USB_CLKSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3040	*
AnnaBridge	189:f392fc9709a3	3041	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3042	* @retval None
AnnaBridge	189:f392fc9709a3	3043	*/
AnnaBridge	189:f392fc9709a3	3044	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
AnnaBridge	189:f392fc9709a3	3045	{
AnnaBridge	189:f392fc9709a3	3046	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
AnnaBridge	189:f392fc9709a3	3047	}
AnnaBridge	189:f392fc9709a3	3048	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	189:f392fc9709a3	3049
AnnaBridge	189:f392fc9709a3	3050	/**
AnnaBridge	189:f392fc9709a3	3051	* @brief Configure ADC clock source
AnnaBridge	189:f392fc9709a3	3052	* @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
AnnaBridge	189:f392fc9709a3	3053	* @param ADCxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3054	* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
AnnaBridge	189:f392fc9709a3	3055	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
AnnaBridge	189:f392fc9709a3	3056	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
AnnaBridge	189:f392fc9709a3	3057	* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	3058	*
AnnaBridge	189:f392fc9709a3	3059	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3060	* @retval None
AnnaBridge	189:f392fc9709a3	3061	*/
AnnaBridge	189:f392fc9709a3	3062	__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
AnnaBridge	189:f392fc9709a3	3063	{
AnnaBridge	189:f392fc9709a3	3064	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
AnnaBridge	189:f392fc9709a3	3065	}
AnnaBridge	189:f392fc9709a3	3066
AnnaBridge	189:f392fc9709a3	3067	#if defined(SWPMI1)
AnnaBridge	189:f392fc9709a3	3068	/**
AnnaBridge	189:f392fc9709a3	3069	* @brief Configure SWPMI clock source
AnnaBridge	189:f392fc9709a3	3070	* @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource
AnnaBridge	189:f392fc9709a3	3071	* @param SWPMIxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3072	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	3073	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3074	* @retval None
AnnaBridge	189:f392fc9709a3	3075	*/
AnnaBridge	189:f392fc9709a3	3076	__STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
AnnaBridge	189:f392fc9709a3	3077	{
AnnaBridge	189:f392fc9709a3	3078	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
AnnaBridge	189:f392fc9709a3	3079	}
AnnaBridge	189:f392fc9709a3	3080	#endif /* SWPMI1 */
AnnaBridge	189:f392fc9709a3	3081
AnnaBridge	189:f392fc9709a3	3082	#if defined(DFSDM1_Channel0)
AnnaBridge	189:f392fc9709a3	3083	#if defined(RCC_CCIPR2_ADFSDM1SEL)
AnnaBridge	189:f392fc9709a3	3084	/**
AnnaBridge	189:f392fc9709a3	3085	* @brief Configure DFSDM Audio clock source
AnnaBridge	189:f392fc9709a3	3086	* @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource
AnnaBridge	189:f392fc9709a3	3087	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3088	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
AnnaBridge	189:f392fc9709a3	3089	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3090	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3091	* @retval None
AnnaBridge	189:f392fc9709a3	3092	*/
AnnaBridge	189:f392fc9709a3	3093	__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
AnnaBridge	189:f392fc9709a3	3094	{
AnnaBridge	189:f392fc9709a3	3095	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source);
AnnaBridge	189:f392fc9709a3	3096	}
AnnaBridge	189:f392fc9709a3	3097	#endif /* RCC_CCIPR2_ADFSDM1SEL */
AnnaBridge	189:f392fc9709a3	3098
AnnaBridge	189:f392fc9709a3	3099	/**
AnnaBridge	189:f392fc9709a3	3100	* @brief Configure DFSDM Kernel clock source
AnnaBridge	189:f392fc9709a3	3101	@if STM32L4S9xx
AnnaBridge	189:f392fc9709a3	3102	* @rmtoll CCIPR2 DFSDM1SEL LL_RCC_SetDFSDMClockSource
AnnaBridge	189:f392fc9709a3	3103	@else
AnnaBridge	189:f392fc9709a3	3104	* @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource
AnnaBridge	189:f392fc9709a3	3105	@endif
AnnaBridge	189:f392fc9709a3	3106	* @param DFSDMxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3107	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	189:f392fc9709a3	3108	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	3109	* @retval None
AnnaBridge	189:f392fc9709a3	3110	*/
AnnaBridge	189:f392fc9709a3	3111	__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
AnnaBridge	189:f392fc9709a3	3112	{
AnnaBridge	189:f392fc9709a3	3113	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	189:f392fc9709a3	3114	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource);
AnnaBridge	189:f392fc9709a3	3115	#else
AnnaBridge	189:f392fc9709a3	3116	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);
AnnaBridge	189:f392fc9709a3	3117	#endif /* RCC_CCIPR2_DFSDM1SEL */
AnnaBridge	189:f392fc9709a3	3118	}
AnnaBridge	189:f392fc9709a3	3119	#endif /* DFSDM1_Channel0 */
AnnaBridge	189:f392fc9709a3	3120
AnnaBridge	189:f392fc9709a3	3121	#if defined(DSI)
AnnaBridge	189:f392fc9709a3	3122	/**
AnnaBridge	189:f392fc9709a3	3123	* @brief Configure DSI clock source
AnnaBridge	189:f392fc9709a3	3124	* @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource
AnnaBridge	189:f392fc9709a3	3125	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3126	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
AnnaBridge	189:f392fc9709a3	3127	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	3128	* @retval None
AnnaBridge	189:f392fc9709a3	3129	*/
AnnaBridge	189:f392fc9709a3	3130	__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
AnnaBridge	189:f392fc9709a3	3131	{
AnnaBridge	189:f392fc9709a3	3132	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source);
AnnaBridge	189:f392fc9709a3	3133	}
AnnaBridge	189:f392fc9709a3	3134	#endif /* DSI */
AnnaBridge	189:f392fc9709a3	3135
AnnaBridge	189:f392fc9709a3	3136	#if defined(LTDC)
AnnaBridge	189:f392fc9709a3	3137	/**
AnnaBridge	189:f392fc9709a3	3138	* @brief Configure LTDC Clock Source
AnnaBridge	189:f392fc9709a3	3139	* @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_SetLTDCClockSource
AnnaBridge	189:f392fc9709a3	3140	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3141	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
AnnaBridge	189:f392fc9709a3	3142	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
AnnaBridge	189:f392fc9709a3	3143	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
AnnaBridge	189:f392fc9709a3	3144	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
AnnaBridge	189:f392fc9709a3	3145	* @retval None
AnnaBridge	189:f392fc9709a3	3146	*/
AnnaBridge	189:f392fc9709a3	3147	__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source)
AnnaBridge	189:f392fc9709a3	3148	{
AnnaBridge	189:f392fc9709a3	3149	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source);
AnnaBridge	189:f392fc9709a3	3150	}
AnnaBridge	189:f392fc9709a3	3151	#endif /* LTDC */
AnnaBridge	189:f392fc9709a3	3152
AnnaBridge	189:f392fc9709a3	3153	#if defined(OCTOSPI1)
AnnaBridge	189:f392fc9709a3	3154	/**
AnnaBridge	189:f392fc9709a3	3155	* @brief Configure OCTOSPI clock source
AnnaBridge	189:f392fc9709a3	3156	* @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource
AnnaBridge	189:f392fc9709a3	3157	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3158	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	3159	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3160	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	3161	* @retval None
AnnaBridge	189:f392fc9709a3	3162	*/
AnnaBridge	189:f392fc9709a3	3163	__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source)
AnnaBridge	189:f392fc9709a3	3164	{
AnnaBridge	189:f392fc9709a3	3165	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source);
AnnaBridge	189:f392fc9709a3	3166	}
AnnaBridge	189:f392fc9709a3	3167	#endif /* OCTOSPI1 */
AnnaBridge	189:f392fc9709a3	3168
AnnaBridge	189:f392fc9709a3	3169	/**
AnnaBridge	189:f392fc9709a3	3170	* @brief Get USARTx clock source
AnnaBridge	189:f392fc9709a3	3171	* @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
AnnaBridge	189:f392fc9709a3	3172	* @param USARTx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3173	* @arg @ref LL_RCC_USART1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3174	* @arg @ref LL_RCC_USART2_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3175	* @arg @ref LL_RCC_USART3_CLKSOURCE (*)
AnnaBridge	189:f392fc9709a3	3176	*
AnnaBridge	189:f392fc9709a3	3177	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3178	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3179	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
AnnaBridge	189:f392fc9709a3	3180	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	3181	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3182	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	3183	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	3184	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	3185	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3186	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	3187	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
AnnaBridge	189:f392fc9709a3	3188	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
AnnaBridge	189:f392fc9709a3	3189	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
AnnaBridge	189:f392fc9709a3	3190	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
AnnaBridge	189:f392fc9709a3	3191	*
AnnaBridge	189:f392fc9709a3	3192	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3193	*/
AnnaBridge	189:f392fc9709a3	3194	__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
AnnaBridge	189:f392fc9709a3	3195	{
AnnaBridge	189:f392fc9709a3	3196	return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) \| (USARTx << 16U));
AnnaBridge	189:f392fc9709a3	3197	}
AnnaBridge	189:f392fc9709a3	3198
AnnaBridge	189:f392fc9709a3	3199	#if defined(UART4) \|\| defined(UART5)
AnnaBridge	189:f392fc9709a3	3200	/**
AnnaBridge	189:f392fc9709a3	3201	* @brief Get UARTx clock source
AnnaBridge	189:f392fc9709a3	3202	* @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
AnnaBridge	189:f392fc9709a3	3203	* @param UARTx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3204	* @arg @ref LL_RCC_UART4_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3205	* @arg @ref LL_RCC_UART5_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3206	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3207	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	3208	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	3209	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3210	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	3211	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	3212	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	3213	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3214	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	3215	*/
AnnaBridge	189:f392fc9709a3	3216	__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
AnnaBridge	189:f392fc9709a3	3217	{
AnnaBridge	189:f392fc9709a3	3218	return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) \| (UARTx << 16U));
AnnaBridge	189:f392fc9709a3	3219	}
AnnaBridge	189:f392fc9709a3	3220	#endif /* UART4 \|\| UART5 */
AnnaBridge	189:f392fc9709a3	3221
AnnaBridge	189:f392fc9709a3	3222	/**
AnnaBridge	189:f392fc9709a3	3223	* @brief Get LPUARTx clock source
AnnaBridge	189:f392fc9709a3	3224	* @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
AnnaBridge	189:f392fc9709a3	3225	* @param LPUARTx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3226	* @arg @ref LL_RCC_LPUART1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3227	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3228	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	3229	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	3230	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3231	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	3232	*/
AnnaBridge	189:f392fc9709a3	3233	__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
AnnaBridge	189:f392fc9709a3	3234	{
AnnaBridge	189:f392fc9709a3	3235	return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
AnnaBridge	189:f392fc9709a3	3236	}
AnnaBridge	189:f392fc9709a3	3237
AnnaBridge	189:f392fc9709a3	3238	/**
AnnaBridge	189:f392fc9709a3	3239	* @brief Get I2Cx clock source
AnnaBridge	189:f392fc9709a3	3240	* @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
AnnaBridge	189:f392fc9709a3	3241	* @param I2Cx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3242	* @arg @ref LL_RCC_I2C1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3243	* @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
AnnaBridge	189:f392fc9709a3	3244	* @arg @ref LL_RCC_I2C3_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3245	* @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
AnnaBridge	189:f392fc9709a3	3246	*
AnnaBridge	189:f392fc9709a3	3247	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3248	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3249	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	3250	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	3251	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3252	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
AnnaBridge	189:f392fc9709a3	3253	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
AnnaBridge	189:f392fc9709a3	3254	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
AnnaBridge	189:f392fc9709a3	3255	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	3256	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	3257	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3258	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
AnnaBridge	189:f392fc9709a3	3259	* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
AnnaBridge	189:f392fc9709a3	3260	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
AnnaBridge	189:f392fc9709a3	3261	*
AnnaBridge	189:f392fc9709a3	3262	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3263	*/
AnnaBridge	189:f392fc9709a3	3264	__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
AnnaBridge	189:f392fc9709a3	3265	{
AnnaBridge	189:f392fc9709a3	3266	__IO uint32_t reg = (__IO uint32_t )(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
AnnaBridge	189:f392fc9709a3	3267	return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x00FF0000U) >> 16U)) >> ((I2Cx & 0x00FF0000U) >> 16U)) \| (I2Cx & 0xFFFF0000U));
AnnaBridge	189:f392fc9709a3	3268	}
AnnaBridge	189:f392fc9709a3	3269
AnnaBridge	189:f392fc9709a3	3270	/**
AnnaBridge	189:f392fc9709a3	3271	* @brief Get LPTIMx clock source
AnnaBridge	189:f392fc9709a3	3272	* @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
AnnaBridge	189:f392fc9709a3	3273	* @param LPTIMx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3274	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3275	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3276	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3277	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	3278	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	3279	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3280	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	3281	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	3282	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	3283	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3284	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	3285	*/
AnnaBridge	189:f392fc9709a3	3286	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
AnnaBridge	189:f392fc9709a3	3287	{
AnnaBridge	189:f392fc9709a3	3288	return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16U \| LPTIMx);
AnnaBridge	189:f392fc9709a3	3289	}
AnnaBridge	189:f392fc9709a3	3290
AnnaBridge	189:f392fc9709a3	3291	/**
AnnaBridge	189:f392fc9709a3	3292	* @brief Get SAIx clock source
AnnaBridge	189:f392fc9709a3	3293	@if STM32L4S9xx
AnnaBridge	189:f392fc9709a3	3294	* @rmtoll CCIPR2 SAIxSEL LL_RCC_GetSAIClockSource
AnnaBridge	189:f392fc9709a3	3295	@else
AnnaBridge	189:f392fc9709a3	3296	* @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource
AnnaBridge	189:f392fc9709a3	3297	@endif
AnnaBridge	189:f392fc9709a3	3298	* @param SAIx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3299	* @arg @ref LL_RCC_SAI1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3300	* @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
AnnaBridge	189:f392fc9709a3	3301	*
AnnaBridge	189:f392fc9709a3	3302	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3303	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3304	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
AnnaBridge	189:f392fc9709a3	3305	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
AnnaBridge	189:f392fc9709a3	3306	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	3307	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
AnnaBridge	189:f392fc9709a3	3308	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
AnnaBridge	189:f392fc9709a3	3309	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
AnnaBridge	189:f392fc9709a3	3310	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
AnnaBridge	189:f392fc9709a3	3311	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
AnnaBridge	189:f392fc9709a3	3312	*
AnnaBridge	189:f392fc9709a3	3313	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3314	*/
AnnaBridge	189:f392fc9709a3	3315	__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
AnnaBridge	189:f392fc9709a3	3316	{
AnnaBridge	189:f392fc9709a3	3317	#if defined(RCC_CCIPR2_SAI1SEL)
AnnaBridge	189:f392fc9709a3	3318	return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) \| (SAIx << 16U));
AnnaBridge	189:f392fc9709a3	3319	#else
AnnaBridge	189:f392fc9709a3	3320	return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U \| SAIx);
AnnaBridge	189:f392fc9709a3	3321	#endif /* RCC_CCIPR2_SAI1SEL */
AnnaBridge	189:f392fc9709a3	3322	}
AnnaBridge	189:f392fc9709a3	3323
AnnaBridge	189:f392fc9709a3	3324	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	189:f392fc9709a3	3325	/**
AnnaBridge	189:f392fc9709a3	3326	* @brief Get SDMMCx kernel clock source
AnnaBridge	189:f392fc9709a3	3327	* @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource
AnnaBridge	189:f392fc9709a3	3328	* @param SDMMCx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3329	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
AnnaBridge	189:f392fc9709a3	3330	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3331	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
AnnaBridge	189:f392fc9709a3	3332	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*)
AnnaBridge	189:f392fc9709a3	3333	*
AnnaBridge	189:f392fc9709a3	3334	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3335	*/
AnnaBridge	189:f392fc9709a3	3336	__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)
AnnaBridge	189:f392fc9709a3	3337	{
AnnaBridge	189:f392fc9709a3	3338	return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));
AnnaBridge	189:f392fc9709a3	3339	}
AnnaBridge	189:f392fc9709a3	3340	#endif /* RCC_CCIPR2_SDMMCSEL */
AnnaBridge	189:f392fc9709a3	3341
AnnaBridge	189:f392fc9709a3	3342	/**
AnnaBridge	189:f392fc9709a3	3343	* @brief Get SDMMCx clock source
AnnaBridge	189:f392fc9709a3	3344	* @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource
AnnaBridge	189:f392fc9709a3	3345	* @param SDMMCx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3346	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3347	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3348	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
AnnaBridge	189:f392fc9709a3	3349	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
AnnaBridge	189:f392fc9709a3	3350	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
AnnaBridge	189:f392fc9709a3	3351	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	3352	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
AnnaBridge	189:f392fc9709a3	3353	*
AnnaBridge	189:f392fc9709a3	3354	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3355	*/
AnnaBridge	189:f392fc9709a3	3356	__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
AnnaBridge	189:f392fc9709a3	3357	{
AnnaBridge	189:f392fc9709a3	3358	return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
AnnaBridge	189:f392fc9709a3	3359	}
AnnaBridge	189:f392fc9709a3	3360
AnnaBridge	189:f392fc9709a3	3361	/**
AnnaBridge	189:f392fc9709a3	3362	* @brief Get RNGx clock source
AnnaBridge	189:f392fc9709a3	3363	* @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
AnnaBridge	189:f392fc9709a3	3364	* @param RNGx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3365	* @arg @ref LL_RCC_RNG_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3366	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3367	* @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
AnnaBridge	189:f392fc9709a3	3368	* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
AnnaBridge	189:f392fc9709a3	3369	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
AnnaBridge	189:f392fc9709a3	3370	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	3371	* @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3372	*
AnnaBridge	189:f392fc9709a3	3373	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3374	*/
AnnaBridge	189:f392fc9709a3	3375	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
AnnaBridge	189:f392fc9709a3	3376	{
AnnaBridge	189:f392fc9709a3	3377	return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
AnnaBridge	189:f392fc9709a3	3378	}
AnnaBridge	189:f392fc9709a3	3379
AnnaBridge	189:f392fc9709a3	3380	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	189:f392fc9709a3	3381	/**
AnnaBridge	189:f392fc9709a3	3382	* @brief Get USBx clock source
AnnaBridge	189:f392fc9709a3	3383	* @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
AnnaBridge	189:f392fc9709a3	3384	* @param USBx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3385	* @arg @ref LL_RCC_USB_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3386	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3387	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
AnnaBridge	189:f392fc9709a3	3388	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
AnnaBridge	189:f392fc9709a3	3389	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
AnnaBridge	189:f392fc9709a3	3390	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	3391	* @arg @ref LL_RCC_USB_CLKSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3392	*
AnnaBridge	189:f392fc9709a3	3393	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3394	*/
AnnaBridge	189:f392fc9709a3	3395	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
AnnaBridge	189:f392fc9709a3	3396	{
AnnaBridge	189:f392fc9709a3	3397	return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
AnnaBridge	189:f392fc9709a3	3398	}
AnnaBridge	189:f392fc9709a3	3399	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	189:f392fc9709a3	3400
AnnaBridge	189:f392fc9709a3	3401	/**
AnnaBridge	189:f392fc9709a3	3402	* @brief Get ADCx clock source
AnnaBridge	189:f392fc9709a3	3403	* @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
AnnaBridge	189:f392fc9709a3	3404	* @param ADCx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3405	* @arg @ref LL_RCC_ADC_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3406	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3407	* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
AnnaBridge	189:f392fc9709a3	3408	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
AnnaBridge	189:f392fc9709a3	3409	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
AnnaBridge	189:f392fc9709a3	3410	* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	3411	*
AnnaBridge	189:f392fc9709a3	3412	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3413	*/
AnnaBridge	189:f392fc9709a3	3414	__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
AnnaBridge	189:f392fc9709a3	3415	{
AnnaBridge	189:f392fc9709a3	3416	return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
AnnaBridge	189:f392fc9709a3	3417	}
AnnaBridge	189:f392fc9709a3	3418
AnnaBridge	189:f392fc9709a3	3419	#if defined(SWPMI1)
AnnaBridge	189:f392fc9709a3	3420	/**
AnnaBridge	189:f392fc9709a3	3421	* @brief Get SWPMIx clock source
AnnaBridge	189:f392fc9709a3	3422	* @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource
AnnaBridge	189:f392fc9709a3	3423	* @param SPWMIx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3424	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3425	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3426	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	3427	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3428	*/
AnnaBridge	189:f392fc9709a3	3429	__STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
AnnaBridge	189:f392fc9709a3	3430	{
AnnaBridge	189:f392fc9709a3	3431	return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
AnnaBridge	189:f392fc9709a3	3432	}
AnnaBridge	189:f392fc9709a3	3433	#endif /* SWPMI1 */
AnnaBridge	189:f392fc9709a3	3434
AnnaBridge	189:f392fc9709a3	3435	#if defined(DFSDM1_Channel0)
AnnaBridge	189:f392fc9709a3	3436	#if defined(RCC_CCIPR2_ADFSDM1SEL)
AnnaBridge	189:f392fc9709a3	3437	/**
AnnaBridge	189:f392fc9709a3	3438	* @brief Get DFSDM Audio Clock Source
AnnaBridge	189:f392fc9709a3	3439	* @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource
AnnaBridge	189:f392fc9709a3	3440	* @param DFSDMx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3441	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3442	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3443	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
AnnaBridge	189:f392fc9709a3	3444	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3445	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3446	*/
AnnaBridge	189:f392fc9709a3	3447	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
AnnaBridge	189:f392fc9709a3	3448	{
AnnaBridge	189:f392fc9709a3	3449	return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
AnnaBridge	189:f392fc9709a3	3450	}
AnnaBridge	189:f392fc9709a3	3451	#endif /* RCC_CCIPR2_ADFSDM1SEL */
AnnaBridge	189:f392fc9709a3	3452
AnnaBridge	189:f392fc9709a3	3453	/**
AnnaBridge	189:f392fc9709a3	3454	* @brief Get DFSDMx Kernel clock source
AnnaBridge	189:f392fc9709a3	3455	@if STM32L4S9xx
AnnaBridge	189:f392fc9709a3	3456	* @rmtoll CCIPR2 DFSDM1SEL LL_RCC_GetDFSDMClockSource
AnnaBridge	189:f392fc9709a3	3457	@else
AnnaBridge	189:f392fc9709a3	3458	* @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource
AnnaBridge	189:f392fc9709a3	3459	@endif
AnnaBridge	189:f392fc9709a3	3460	* @param DFSDMx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3461	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3462	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3463	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	189:f392fc9709a3	3464	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	3465	*/
AnnaBridge	189:f392fc9709a3	3466	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
AnnaBridge	189:f392fc9709a3	3467	{
AnnaBridge	189:f392fc9709a3	3468	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	189:f392fc9709a3	3469	return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
AnnaBridge	189:f392fc9709a3	3470	#else
AnnaBridge	189:f392fc9709a3	3471	return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
AnnaBridge	189:f392fc9709a3	3472	#endif /* RCC_CCIPR2_DFSDM1SEL */
AnnaBridge	189:f392fc9709a3	3473	}
AnnaBridge	189:f392fc9709a3	3474	#endif /* DFSDM1_Channel0 */
AnnaBridge	189:f392fc9709a3	3475
AnnaBridge	189:f392fc9709a3	3476	#if defined(DSI)
AnnaBridge	189:f392fc9709a3	3477	/**
AnnaBridge	189:f392fc9709a3	3478	* @brief Get DSI Clock Source
AnnaBridge	189:f392fc9709a3	3479	* @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource
AnnaBridge	189:f392fc9709a3	3480	* @param DSIx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3481	* @arg @ref LL_RCC_DSI_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3482	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3483	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
AnnaBridge	189:f392fc9709a3	3484	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	3485	*/
AnnaBridge	189:f392fc9709a3	3486	__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
AnnaBridge	189:f392fc9709a3	3487	{
AnnaBridge	189:f392fc9709a3	3488	return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx));
AnnaBridge	189:f392fc9709a3	3489	}
AnnaBridge	189:f392fc9709a3	3490	#endif /* DSI */
AnnaBridge	189:f392fc9709a3	3491
AnnaBridge	189:f392fc9709a3	3492	#if defined(LTDC)
AnnaBridge	189:f392fc9709a3	3493	/**
AnnaBridge	189:f392fc9709a3	3494	* @brief Get LTDC Clock Source
AnnaBridge	189:f392fc9709a3	3495	* @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_GetLTDCClockSource
AnnaBridge	189:f392fc9709a3	3496	* @param LTDCx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3497	* @arg @ref LL_RCC_LTDC_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3498	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3499	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
AnnaBridge	189:f392fc9709a3	3500	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
AnnaBridge	189:f392fc9709a3	3501	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
AnnaBridge	189:f392fc9709a3	3502	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
AnnaBridge	189:f392fc9709a3	3503	*/
AnnaBridge	189:f392fc9709a3	3504	__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx)
AnnaBridge	189:f392fc9709a3	3505	{
AnnaBridge	189:f392fc9709a3	3506	return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx));
AnnaBridge	189:f392fc9709a3	3507	}
AnnaBridge	189:f392fc9709a3	3508	#endif /* LTDC */
AnnaBridge	189:f392fc9709a3	3509
AnnaBridge	189:f392fc9709a3	3510	#if defined(OCTOSPI1)
AnnaBridge	189:f392fc9709a3	3511	/**
AnnaBridge	189:f392fc9709a3	3512	* @brief Get OCTOSPI clock source
AnnaBridge	189:f392fc9709a3	3513	* @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource
AnnaBridge	189:f392fc9709a3	3514	* @param OCTOSPIx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3515	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
AnnaBridge	189:f392fc9709a3	3516	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3517	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	3518	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3519	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	3520	*/
AnnaBridge	189:f392fc9709a3	3521	__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
AnnaBridge	189:f392fc9709a3	3522	{
AnnaBridge	189:f392fc9709a3	3523	return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx));
AnnaBridge	189:f392fc9709a3	3524	}
AnnaBridge	189:f392fc9709a3	3525	#endif /* OCTOSPI1 */
AnnaBridge	189:f392fc9709a3	3526	/**
AnnaBridge	189:f392fc9709a3	3527	* @}
AnnaBridge	189:f392fc9709a3	3528	*/
AnnaBridge	189:f392fc9709a3	3529
AnnaBridge	189:f392fc9709a3	3530	/** @defgroup RCC_LL_EF_RTC RTC
AnnaBridge	189:f392fc9709a3	3531	* @{
AnnaBridge	189:f392fc9709a3	3532	*/
AnnaBridge	189:f392fc9709a3	3533
AnnaBridge	189:f392fc9709a3	3534	/**
AnnaBridge	189:f392fc9709a3	3535	* @brief Set RTC Clock Source
AnnaBridge	189:f392fc9709a3	3536	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
AnnaBridge	189:f392fc9709a3	3537	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
AnnaBridge	189:f392fc9709a3	3538	* set). The BDRST bit can be used to reset them.
AnnaBridge	189:f392fc9709a3	3539	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
AnnaBridge	189:f392fc9709a3	3540	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3541	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	189:f392fc9709a3	3542	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	3543	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	3544	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
AnnaBridge	189:f392fc9709a3	3545	* @retval None
AnnaBridge	189:f392fc9709a3	3546	*/
AnnaBridge	189:f392fc9709a3	3547	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
AnnaBridge	189:f392fc9709a3	3548	{
AnnaBridge	189:f392fc9709a3	3549	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
AnnaBridge	189:f392fc9709a3	3550	}
AnnaBridge	189:f392fc9709a3	3551
AnnaBridge	189:f392fc9709a3	3552	/**
AnnaBridge	189:f392fc9709a3	3553	* @brief Get RTC Clock Source
AnnaBridge	189:f392fc9709a3	3554	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
AnnaBridge	189:f392fc9709a3	3555	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3556	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	189:f392fc9709a3	3557	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	3558	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	3559	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
AnnaBridge	189:f392fc9709a3	3560	*/
AnnaBridge	189:f392fc9709a3	3561	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
AnnaBridge	189:f392fc9709a3	3562	{
AnnaBridge	189:f392fc9709a3	3563	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
AnnaBridge	189:f392fc9709a3	3564	}
AnnaBridge	189:f392fc9709a3	3565
AnnaBridge	189:f392fc9709a3	3566	/**
AnnaBridge	189:f392fc9709a3	3567	* @brief Enable RTC
AnnaBridge	189:f392fc9709a3	3568	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
AnnaBridge	189:f392fc9709a3	3569	* @retval None
AnnaBridge	189:f392fc9709a3	3570	*/
AnnaBridge	189:f392fc9709a3	3571	__STATIC_INLINE void LL_RCC_EnableRTC(void)
AnnaBridge	189:f392fc9709a3	3572	{
AnnaBridge	189:f392fc9709a3	3573	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	189:f392fc9709a3	3574	}
AnnaBridge	189:f392fc9709a3	3575
AnnaBridge	189:f392fc9709a3	3576	/**
AnnaBridge	189:f392fc9709a3	3577	* @brief Disable RTC
AnnaBridge	189:f392fc9709a3	3578	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
AnnaBridge	189:f392fc9709a3	3579	* @retval None
AnnaBridge	189:f392fc9709a3	3580	*/
AnnaBridge	189:f392fc9709a3	3581	__STATIC_INLINE void LL_RCC_DisableRTC(void)
AnnaBridge	189:f392fc9709a3	3582	{
AnnaBridge	189:f392fc9709a3	3583	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	189:f392fc9709a3	3584	}
AnnaBridge	189:f392fc9709a3	3585
AnnaBridge	189:f392fc9709a3	3586	/**
AnnaBridge	189:f392fc9709a3	3587	* @brief Check if RTC has been enabled or not
AnnaBridge	189:f392fc9709a3	3588	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
AnnaBridge	189:f392fc9709a3	3589	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	3590	*/
AnnaBridge	189:f392fc9709a3	3591	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
AnnaBridge	189:f392fc9709a3	3592	{
AnnaBridge	189:f392fc9709a3	3593	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
AnnaBridge	189:f392fc9709a3	3594	}
AnnaBridge	189:f392fc9709a3	3595
AnnaBridge	189:f392fc9709a3	3596	/**
AnnaBridge	189:f392fc9709a3	3597	* @brief Force the Backup domain reset
AnnaBridge	189:f392fc9709a3	3598	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
AnnaBridge	189:f392fc9709a3	3599	* @retval None
AnnaBridge	189:f392fc9709a3	3600	*/
AnnaBridge	189:f392fc9709a3	3601	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
AnnaBridge	189:f392fc9709a3	3602	{
AnnaBridge	189:f392fc9709a3	3603	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	189:f392fc9709a3	3604	}
AnnaBridge	189:f392fc9709a3	3605
AnnaBridge	189:f392fc9709a3	3606	/**
AnnaBridge	189:f392fc9709a3	3607	* @brief Release the Backup domain reset
AnnaBridge	189:f392fc9709a3	3608	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
AnnaBridge	189:f392fc9709a3	3609	* @retval None
AnnaBridge	189:f392fc9709a3	3610	*/
AnnaBridge	189:f392fc9709a3	3611	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
AnnaBridge	189:f392fc9709a3	3612	{
AnnaBridge	189:f392fc9709a3	3613	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	189:f392fc9709a3	3614	}
AnnaBridge	189:f392fc9709a3	3615
AnnaBridge	189:f392fc9709a3	3616	/**
AnnaBridge	189:f392fc9709a3	3617	* @}
AnnaBridge	189:f392fc9709a3	3618	*/
AnnaBridge	189:f392fc9709a3	3619
AnnaBridge	189:f392fc9709a3	3620
AnnaBridge	189:f392fc9709a3	3621	/** @defgroup RCC_LL_EF_PLL PLL
AnnaBridge	189:f392fc9709a3	3622	* @{
AnnaBridge	189:f392fc9709a3	3623	*/
AnnaBridge	189:f392fc9709a3	3624
AnnaBridge	189:f392fc9709a3	3625	/**
AnnaBridge	189:f392fc9709a3	3626	* @brief Enable PLL
AnnaBridge	189:f392fc9709a3	3627	* @rmtoll CR PLLON LL_RCC_PLL_Enable
AnnaBridge	189:f392fc9709a3	3628	* @retval None
AnnaBridge	189:f392fc9709a3	3629	*/
AnnaBridge	189:f392fc9709a3	3630	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
AnnaBridge	189:f392fc9709a3	3631	{
AnnaBridge	189:f392fc9709a3	3632	SET_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	189:f392fc9709a3	3633	}
AnnaBridge	189:f392fc9709a3	3634
AnnaBridge	189:f392fc9709a3	3635	/**
AnnaBridge	189:f392fc9709a3	3636	* @brief Disable PLL
AnnaBridge	189:f392fc9709a3	3637	* @note Cannot be disabled if the PLL clock is used as the system clock
AnnaBridge	189:f392fc9709a3	3638	* @rmtoll CR PLLON LL_RCC_PLL_Disable
AnnaBridge	189:f392fc9709a3	3639	* @retval None
AnnaBridge	189:f392fc9709a3	3640	*/
AnnaBridge	189:f392fc9709a3	3641	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
AnnaBridge	189:f392fc9709a3	3642	{
AnnaBridge	189:f392fc9709a3	3643	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	189:f392fc9709a3	3644	}
AnnaBridge	189:f392fc9709a3	3645
AnnaBridge	189:f392fc9709a3	3646	/**
AnnaBridge	189:f392fc9709a3	3647	* @brief Check if PLL Ready
AnnaBridge	189:f392fc9709a3	3648	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
AnnaBridge	189:f392fc9709a3	3649	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	3650	*/
AnnaBridge	189:f392fc9709a3	3651	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
AnnaBridge	189:f392fc9709a3	3652	{
AnnaBridge	189:f392fc9709a3	3653	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
AnnaBridge	189:f392fc9709a3	3654	}
AnnaBridge	189:f392fc9709a3	3655
AnnaBridge	189:f392fc9709a3	3656	/**
AnnaBridge	189:f392fc9709a3	3657	* @brief Configure PLL used for SYSCLK Domain
AnnaBridge	189:f392fc9709a3	3658	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	189:f392fc9709a3	3659	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	3660	* @note PLLN/PLLR can be written only when PLL is disabled.
AnnaBridge	189:f392fc9709a3	3661	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	189:f392fc9709a3	3662	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	189:f392fc9709a3	3663	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	189:f392fc9709a3	3664	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
AnnaBridge	189:f392fc9709a3	3665	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3666	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	3667	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3668	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3669	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	3670	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3671	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	3672	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	3673	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	3674	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	3675	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	3676	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	3677	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	3678	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	3679	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	189:f392fc9709a3	3680	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	189:f392fc9709a3	3681	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	189:f392fc9709a3	3682	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	189:f392fc9709a3	3683	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	189:f392fc9709a3	3684	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	189:f392fc9709a3	3685	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	189:f392fc9709a3	3686	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	189:f392fc9709a3	3687	*
AnnaBridge	189:f392fc9709a3	3688	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3689	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	3690	* @param PLLR This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3691	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	189:f392fc9709a3	3692	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	189:f392fc9709a3	3693	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	189:f392fc9709a3	3694	* @arg @ref LL_RCC_PLLR_DIV_8
AnnaBridge	189:f392fc9709a3	3695	* @retval None
AnnaBridge	189:f392fc9709a3	3696	*/
AnnaBridge	189:f392fc9709a3	3697	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	189:f392fc9709a3	3698	{
AnnaBridge	189:f392fc9709a3	3699	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
AnnaBridge	189:f392fc9709a3	3700	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
AnnaBridge	189:f392fc9709a3	3701	}
AnnaBridge	189:f392fc9709a3	3702
AnnaBridge	189:f392fc9709a3	3703	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	3704	/**
AnnaBridge	189:f392fc9709a3	3705	* @brief Configure PLL used for SAI domain clock
AnnaBridge	189:f392fc9709a3	3706	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	189:f392fc9709a3	3707	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	3708	* @note PLLN/PLLP can be written only when PLL is disabled.
AnnaBridge	189:f392fc9709a3	3709	* @note This can be selected for SAI1 or SAI2 (*)
AnnaBridge	189:f392fc9709a3	3710	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	3711	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	3712	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	3713	* PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI
AnnaBridge	189:f392fc9709a3	3714	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3715	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	3716	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3717	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3718	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	3719	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3720	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	3721	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	3722	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	3723	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	3724	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	3725	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	3726	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	3727	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	3728	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	189:f392fc9709a3	3729	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	189:f392fc9709a3	3730	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	189:f392fc9709a3	3731	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	189:f392fc9709a3	3732	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	189:f392fc9709a3	3733	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	189:f392fc9709a3	3734	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	189:f392fc9709a3	3735	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	189:f392fc9709a3	3736	*
AnnaBridge	189:f392fc9709a3	3737	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3738	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	3739	* @param PLLP This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3740	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	189:f392fc9709a3	3741	* @arg @ref LL_RCC_PLLP_DIV_3
AnnaBridge	189:f392fc9709a3	3742	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	189:f392fc9709a3	3743	* @arg @ref LL_RCC_PLLP_DIV_5
AnnaBridge	189:f392fc9709a3	3744	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	189:f392fc9709a3	3745	* @arg @ref LL_RCC_PLLP_DIV_7
AnnaBridge	189:f392fc9709a3	3746	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	189:f392fc9709a3	3747	* @arg @ref LL_RCC_PLLP_DIV_9
AnnaBridge	189:f392fc9709a3	3748	* @arg @ref LL_RCC_PLLP_DIV_10
AnnaBridge	189:f392fc9709a3	3749	* @arg @ref LL_RCC_PLLP_DIV_11
AnnaBridge	189:f392fc9709a3	3750	* @arg @ref LL_RCC_PLLP_DIV_12
AnnaBridge	189:f392fc9709a3	3751	* @arg @ref LL_RCC_PLLP_DIV_13
AnnaBridge	189:f392fc9709a3	3752	* @arg @ref LL_RCC_PLLP_DIV_14
AnnaBridge	189:f392fc9709a3	3753	* @arg @ref LL_RCC_PLLP_DIV_15
AnnaBridge	189:f392fc9709a3	3754	* @arg @ref LL_RCC_PLLP_DIV_16
AnnaBridge	189:f392fc9709a3	3755	* @arg @ref LL_RCC_PLLP_DIV_17
AnnaBridge	189:f392fc9709a3	3756	* @arg @ref LL_RCC_PLLP_DIV_18
AnnaBridge	189:f392fc9709a3	3757	* @arg @ref LL_RCC_PLLP_DIV_19
AnnaBridge	189:f392fc9709a3	3758	* @arg @ref LL_RCC_PLLP_DIV_20
AnnaBridge	189:f392fc9709a3	3759	* @arg @ref LL_RCC_PLLP_DIV_21
AnnaBridge	189:f392fc9709a3	3760	* @arg @ref LL_RCC_PLLP_DIV_22
AnnaBridge	189:f392fc9709a3	3761	* @arg @ref LL_RCC_PLLP_DIV_23
AnnaBridge	189:f392fc9709a3	3762	* @arg @ref LL_RCC_PLLP_DIV_24
AnnaBridge	189:f392fc9709a3	3763	* @arg @ref LL_RCC_PLLP_DIV_25
AnnaBridge	189:f392fc9709a3	3764	* @arg @ref LL_RCC_PLLP_DIV_26
AnnaBridge	189:f392fc9709a3	3765	* @arg @ref LL_RCC_PLLP_DIV_27
AnnaBridge	189:f392fc9709a3	3766	* @arg @ref LL_RCC_PLLP_DIV_28
AnnaBridge	189:f392fc9709a3	3767	* @arg @ref LL_RCC_PLLP_DIV_29
AnnaBridge	189:f392fc9709a3	3768	* @arg @ref LL_RCC_PLLP_DIV_30
AnnaBridge	189:f392fc9709a3	3769	* @arg @ref LL_RCC_PLLP_DIV_31
AnnaBridge	189:f392fc9709a3	3770	* @retval None
AnnaBridge	189:f392fc9709a3	3771	*/
AnnaBridge	189:f392fc9709a3	3772	#else
AnnaBridge	189:f392fc9709a3	3773	/**
AnnaBridge	189:f392fc9709a3	3774	* @brief Configure PLL used for SAI domain clock
AnnaBridge	189:f392fc9709a3	3775	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	189:f392fc9709a3	3776	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	3777	* @note PLLN/PLLP can be written only when PLL is disabled.
AnnaBridge	189:f392fc9709a3	3778	* @note This can be selected for SAI1 or SAI2 (*)
AnnaBridge	189:f392fc9709a3	3779	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	3780	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	3781	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	3782	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
AnnaBridge	189:f392fc9709a3	3783	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3784	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	3785	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3786	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3787	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	3788	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3789	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	3790	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	3791	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	3792	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	3793	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	3794	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	3795	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	3796	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	3797	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	3798	* @param PLLP This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3799	* @arg @ref LL_RCC_PLLP_DIV_7
AnnaBridge	189:f392fc9709a3	3800	* @arg @ref LL_RCC_PLLP_DIV_17
AnnaBridge	189:f392fc9709a3	3801	* @retval None
AnnaBridge	189:f392fc9709a3	3802	*/
AnnaBridge	189:f392fc9709a3	3803	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	189:f392fc9709a3	3804	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	189:f392fc9709a3	3805	{
AnnaBridge	189:f392fc9709a3	3806	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	3807	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLPDIV,
AnnaBridge	189:f392fc9709a3	3808	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLP);
AnnaBridge	189:f392fc9709a3	3809	#else
AnnaBridge	189:f392fc9709a3	3810	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLP,
AnnaBridge	189:f392fc9709a3	3811	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLP);
AnnaBridge	189:f392fc9709a3	3812	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	189:f392fc9709a3	3813	}
AnnaBridge	189:f392fc9709a3	3814
AnnaBridge	189:f392fc9709a3	3815	/**
AnnaBridge	189:f392fc9709a3	3816	* @brief Configure PLL used for 48Mhz domain clock
AnnaBridge	189:f392fc9709a3	3817	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	189:f392fc9709a3	3818	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	3819	* @note PLLN/PLLQ can be written only when PLL is disabled.
AnnaBridge	189:f392fc9709a3	3820	* @note This can be selected for USB, RNG, SDMMC
AnnaBridge	189:f392fc9709a3	3821	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	189:f392fc9709a3	3822	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	189:f392fc9709a3	3823	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	189:f392fc9709a3	3824	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
AnnaBridge	189:f392fc9709a3	3825	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3826	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	3827	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3828	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3829	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	3830	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3831	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	3832	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	3833	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	3834	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	3835	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	3836	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	3837	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	3838	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	3839	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	189:f392fc9709a3	3840	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	189:f392fc9709a3	3841	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	189:f392fc9709a3	3842	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	189:f392fc9709a3	3843	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	189:f392fc9709a3	3844	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	189:f392fc9709a3	3845	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	189:f392fc9709a3	3846	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	189:f392fc9709a3	3847	*
AnnaBridge	189:f392fc9709a3	3848	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	3849	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	3850	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3851	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	189:f392fc9709a3	3852	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	189:f392fc9709a3	3853	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	189:f392fc9709a3	3854	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	189:f392fc9709a3	3855	* @retval None
AnnaBridge	189:f392fc9709a3	3856	*/
AnnaBridge	189:f392fc9709a3	3857	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	189:f392fc9709a3	3858	{
AnnaBridge	189:f392fc9709a3	3859	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
AnnaBridge	189:f392fc9709a3	3860	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLQ);
AnnaBridge	189:f392fc9709a3	3861	}
AnnaBridge	189:f392fc9709a3	3862
AnnaBridge	189:f392fc9709a3	3863	/**
AnnaBridge	189:f392fc9709a3	3864	* @brief Configure PLL clock source
AnnaBridge	189:f392fc9709a3	3865	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
AnnaBridge	189:f392fc9709a3	3866	* @param PLLSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	3867	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	3868	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3869	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3870	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	3871	* @retval None
AnnaBridge	189:f392fc9709a3	3872	*/
AnnaBridge	189:f392fc9709a3	3873	__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
AnnaBridge	189:f392fc9709a3	3874	{
AnnaBridge	189:f392fc9709a3	3875	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
AnnaBridge	189:f392fc9709a3	3876	}
AnnaBridge	189:f392fc9709a3	3877
AnnaBridge	189:f392fc9709a3	3878	/**
AnnaBridge	189:f392fc9709a3	3879	* @brief Get the oscillator used as PLL clock source.
AnnaBridge	189:f392fc9709a3	3880	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
AnnaBridge	189:f392fc9709a3	3881	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3882	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	3883	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	3884	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	3885	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	3886	*/
AnnaBridge	189:f392fc9709a3	3887	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
AnnaBridge	189:f392fc9709a3	3888	{
AnnaBridge	189:f392fc9709a3	3889	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
AnnaBridge	189:f392fc9709a3	3890	}
AnnaBridge	189:f392fc9709a3	3891
AnnaBridge	189:f392fc9709a3	3892	/**
AnnaBridge	189:f392fc9709a3	3893	* @brief Get Main PLL multiplication factor for VCO
AnnaBridge	189:f392fc9709a3	3894	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
AnnaBridge	189:f392fc9709a3	3895	* @retval Between 8 and 86
AnnaBridge	189:f392fc9709a3	3896	*/
AnnaBridge	189:f392fc9709a3	3897	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
AnnaBridge	189:f392fc9709a3	3898	{
AnnaBridge	189:f392fc9709a3	3899	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
AnnaBridge	189:f392fc9709a3	3900	}
AnnaBridge	189:f392fc9709a3	3901
AnnaBridge	189:f392fc9709a3	3902	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	3903	/**
AnnaBridge	189:f392fc9709a3	3904	* @brief Get Main PLL division factor for PLLP
AnnaBridge	189:f392fc9709a3	3905	* @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
AnnaBridge	189:f392fc9709a3	3906	* @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP
AnnaBridge	189:f392fc9709a3	3907	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3908	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	189:f392fc9709a3	3909	* @arg @ref LL_RCC_PLLP_DIV_3
AnnaBridge	189:f392fc9709a3	3910	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	189:f392fc9709a3	3911	* @arg @ref LL_RCC_PLLP_DIV_5
AnnaBridge	189:f392fc9709a3	3912	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	189:f392fc9709a3	3913	* @arg @ref LL_RCC_PLLP_DIV_7
AnnaBridge	189:f392fc9709a3	3914	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	189:f392fc9709a3	3915	* @arg @ref LL_RCC_PLLP_DIV_9
AnnaBridge	189:f392fc9709a3	3916	* @arg @ref LL_RCC_PLLP_DIV_10
AnnaBridge	189:f392fc9709a3	3917	* @arg @ref LL_RCC_PLLP_DIV_11
AnnaBridge	189:f392fc9709a3	3918	* @arg @ref LL_RCC_PLLP_DIV_12
AnnaBridge	189:f392fc9709a3	3919	* @arg @ref LL_RCC_PLLP_DIV_13
AnnaBridge	189:f392fc9709a3	3920	* @arg @ref LL_RCC_PLLP_DIV_14
AnnaBridge	189:f392fc9709a3	3921	* @arg @ref LL_RCC_PLLP_DIV_15
AnnaBridge	189:f392fc9709a3	3922	* @arg @ref LL_RCC_PLLP_DIV_16
AnnaBridge	189:f392fc9709a3	3923	* @arg @ref LL_RCC_PLLP_DIV_17
AnnaBridge	189:f392fc9709a3	3924	* @arg @ref LL_RCC_PLLP_DIV_18
AnnaBridge	189:f392fc9709a3	3925	* @arg @ref LL_RCC_PLLP_DIV_19
AnnaBridge	189:f392fc9709a3	3926	* @arg @ref LL_RCC_PLLP_DIV_20
AnnaBridge	189:f392fc9709a3	3927	* @arg @ref LL_RCC_PLLP_DIV_21
AnnaBridge	189:f392fc9709a3	3928	* @arg @ref LL_RCC_PLLP_DIV_22
AnnaBridge	189:f392fc9709a3	3929	* @arg @ref LL_RCC_PLLP_DIV_23
AnnaBridge	189:f392fc9709a3	3930	* @arg @ref LL_RCC_PLLP_DIV_24
AnnaBridge	189:f392fc9709a3	3931	* @arg @ref LL_RCC_PLLP_DIV_25
AnnaBridge	189:f392fc9709a3	3932	* @arg @ref LL_RCC_PLLP_DIV_26
AnnaBridge	189:f392fc9709a3	3933	* @arg @ref LL_RCC_PLLP_DIV_27
AnnaBridge	189:f392fc9709a3	3934	* @arg @ref LL_RCC_PLLP_DIV_28
AnnaBridge	189:f392fc9709a3	3935	* @arg @ref LL_RCC_PLLP_DIV_29
AnnaBridge	189:f392fc9709a3	3936	* @arg @ref LL_RCC_PLLP_DIV_30
AnnaBridge	189:f392fc9709a3	3937	* @arg @ref LL_RCC_PLLP_DIV_31
AnnaBridge	189:f392fc9709a3	3938	*/
AnnaBridge	189:f392fc9709a3	3939	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
AnnaBridge	189:f392fc9709a3	3940	{
AnnaBridge	189:f392fc9709a3	3941	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
AnnaBridge	189:f392fc9709a3	3942	}
AnnaBridge	189:f392fc9709a3	3943	#else
AnnaBridge	189:f392fc9709a3	3944	/**
AnnaBridge	189:f392fc9709a3	3945	* @brief Get Main PLL division factor for PLLP
AnnaBridge	189:f392fc9709a3	3946	* @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
AnnaBridge	189:f392fc9709a3	3947	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
AnnaBridge	189:f392fc9709a3	3948	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3949	* @arg @ref LL_RCC_PLLP_DIV_7
AnnaBridge	189:f392fc9709a3	3950	* @arg @ref LL_RCC_PLLP_DIV_17
AnnaBridge	189:f392fc9709a3	3951	*/
AnnaBridge	189:f392fc9709a3	3952	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
AnnaBridge	189:f392fc9709a3	3953	{
AnnaBridge	189:f392fc9709a3	3954	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
AnnaBridge	189:f392fc9709a3	3955	}
AnnaBridge	189:f392fc9709a3	3956	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	189:f392fc9709a3	3957
AnnaBridge	189:f392fc9709a3	3958	/**
AnnaBridge	189:f392fc9709a3	3959	* @brief Get Main PLL division factor for PLLQ
AnnaBridge	189:f392fc9709a3	3960	* @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
AnnaBridge	189:f392fc9709a3	3961	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
AnnaBridge	189:f392fc9709a3	3962	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3963	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	189:f392fc9709a3	3964	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	189:f392fc9709a3	3965	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	189:f392fc9709a3	3966	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	189:f392fc9709a3	3967	*/
AnnaBridge	189:f392fc9709a3	3968	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
AnnaBridge	189:f392fc9709a3	3969	{
AnnaBridge	189:f392fc9709a3	3970	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
AnnaBridge	189:f392fc9709a3	3971	}
AnnaBridge	189:f392fc9709a3	3972
AnnaBridge	189:f392fc9709a3	3973	/**
AnnaBridge	189:f392fc9709a3	3974	* @brief Get Main PLL division factor for PLLR
AnnaBridge	189:f392fc9709a3	3975	* @note Used for PLLCLK (system clock)
AnnaBridge	189:f392fc9709a3	3976	* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
AnnaBridge	189:f392fc9709a3	3977	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3978	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	189:f392fc9709a3	3979	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	189:f392fc9709a3	3980	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	189:f392fc9709a3	3981	* @arg @ref LL_RCC_PLLR_DIV_8
AnnaBridge	189:f392fc9709a3	3982	*/
AnnaBridge	189:f392fc9709a3	3983	__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
AnnaBridge	189:f392fc9709a3	3984	{
AnnaBridge	189:f392fc9709a3	3985	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
AnnaBridge	189:f392fc9709a3	3986	}
AnnaBridge	189:f392fc9709a3	3987
AnnaBridge	189:f392fc9709a3	3988	/**
AnnaBridge	189:f392fc9709a3	3989	* @brief Get Division factor for the main PLL and other PLL
AnnaBridge	189:f392fc9709a3	3990	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
AnnaBridge	189:f392fc9709a3	3991	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	3992	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	3993	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	3994	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	3995	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	3996	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	3997	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	3998	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	3999	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	4000	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	189:f392fc9709a3	4001	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	189:f392fc9709a3	4002	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	189:f392fc9709a3	4003	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	189:f392fc9709a3	4004	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	189:f392fc9709a3	4005	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	189:f392fc9709a3	4006	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	189:f392fc9709a3	4007	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	189:f392fc9709a3	4008	*
AnnaBridge	189:f392fc9709a3	4009	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	4010	*/
AnnaBridge	189:f392fc9709a3	4011	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
AnnaBridge	189:f392fc9709a3	4012	{
AnnaBridge	189:f392fc9709a3	4013	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
AnnaBridge	189:f392fc9709a3	4014	}
AnnaBridge	189:f392fc9709a3	4015
AnnaBridge	189:f392fc9709a3	4016	/**
AnnaBridge	189:f392fc9709a3	4017	* @brief Enable PLL output mapped on SAI domain clock
AnnaBridge	189:f392fc9709a3	4018	* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
AnnaBridge	189:f392fc9709a3	4019	* @retval None
AnnaBridge	189:f392fc9709a3	4020	*/
AnnaBridge	189:f392fc9709a3	4021	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
AnnaBridge	189:f392fc9709a3	4022	{
AnnaBridge	189:f392fc9709a3	4023	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
AnnaBridge	189:f392fc9709a3	4024	}
AnnaBridge	189:f392fc9709a3	4025
AnnaBridge	189:f392fc9709a3	4026	/**
AnnaBridge	189:f392fc9709a3	4027	* @brief Disable PLL output mapped on SAI domain clock
AnnaBridge	189:f392fc9709a3	4028	* @note Cannot be disabled if the PLL clock is used as the system
AnnaBridge	189:f392fc9709a3	4029	* clock
AnnaBridge	189:f392fc9709a3	4030	* @note In order to save power, when the PLLCLK of the PLL is
AnnaBridge	189:f392fc9709a3	4031	* not used, should be 0
AnnaBridge	189:f392fc9709a3	4032	* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
AnnaBridge	189:f392fc9709a3	4033	* @retval None
AnnaBridge	189:f392fc9709a3	4034	*/
AnnaBridge	189:f392fc9709a3	4035	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
AnnaBridge	189:f392fc9709a3	4036	{
AnnaBridge	189:f392fc9709a3	4037	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
AnnaBridge	189:f392fc9709a3	4038	}
AnnaBridge	189:f392fc9709a3	4039
AnnaBridge	189:f392fc9709a3	4040	/**
AnnaBridge	189:f392fc9709a3	4041	* @brief Enable PLL output mapped on 48MHz domain clock
AnnaBridge	189:f392fc9709a3	4042	* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
AnnaBridge	189:f392fc9709a3	4043	* @retval None
AnnaBridge	189:f392fc9709a3	4044	*/
AnnaBridge	189:f392fc9709a3	4045	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
AnnaBridge	189:f392fc9709a3	4046	{
AnnaBridge	189:f392fc9709a3	4047	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
AnnaBridge	189:f392fc9709a3	4048	}
AnnaBridge	189:f392fc9709a3	4049
AnnaBridge	189:f392fc9709a3	4050	/**
AnnaBridge	189:f392fc9709a3	4051	* @brief Disable PLL output mapped on 48MHz domain clock
AnnaBridge	189:f392fc9709a3	4052	* @note Cannot be disabled if the PLL clock is used as the system
AnnaBridge	189:f392fc9709a3	4053	* clock
AnnaBridge	189:f392fc9709a3	4054	* @note In order to save power, when the PLLCLK of the PLL is
AnnaBridge	189:f392fc9709a3	4055	* not used, should be 0
AnnaBridge	189:f392fc9709a3	4056	* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
AnnaBridge	189:f392fc9709a3	4057	* @retval None
AnnaBridge	189:f392fc9709a3	4058	*/
AnnaBridge	189:f392fc9709a3	4059	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
AnnaBridge	189:f392fc9709a3	4060	{
AnnaBridge	189:f392fc9709a3	4061	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
AnnaBridge	189:f392fc9709a3	4062	}
AnnaBridge	189:f392fc9709a3	4063
AnnaBridge	189:f392fc9709a3	4064	/**
AnnaBridge	189:f392fc9709a3	4065	* @brief Enable PLL output mapped on SYSCLK domain
AnnaBridge	189:f392fc9709a3	4066	* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
AnnaBridge	189:f392fc9709a3	4067	* @retval None
AnnaBridge	189:f392fc9709a3	4068	*/
AnnaBridge	189:f392fc9709a3	4069	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
AnnaBridge	189:f392fc9709a3	4070	{
AnnaBridge	189:f392fc9709a3	4071	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
AnnaBridge	189:f392fc9709a3	4072	}
AnnaBridge	189:f392fc9709a3	4073
AnnaBridge	189:f392fc9709a3	4074	/**
AnnaBridge	189:f392fc9709a3	4075	* @brief Disable PLL output mapped on SYSCLK domain
AnnaBridge	189:f392fc9709a3	4076	* @note Cannot be disabled if the PLL clock is used as the system
AnnaBridge	189:f392fc9709a3	4077	* clock
AnnaBridge	189:f392fc9709a3	4078	* @note In order to save power, when the PLLCLK of the PLL is
AnnaBridge	189:f392fc9709a3	4079	* not used, Main PLL should be 0
AnnaBridge	189:f392fc9709a3	4080	* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
AnnaBridge	189:f392fc9709a3	4081	* @retval None
AnnaBridge	189:f392fc9709a3	4082	*/
AnnaBridge	189:f392fc9709a3	4083	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
AnnaBridge	189:f392fc9709a3	4084	{
AnnaBridge	189:f392fc9709a3	4085	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
AnnaBridge	189:f392fc9709a3	4086	}
AnnaBridge	189:f392fc9709a3	4087
AnnaBridge	189:f392fc9709a3	4088	/**
AnnaBridge	189:f392fc9709a3	4089	* @}
AnnaBridge	189:f392fc9709a3	4090	*/
AnnaBridge	189:f392fc9709a3	4091
AnnaBridge	189:f392fc9709a3	4092	/** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
AnnaBridge	189:f392fc9709a3	4093	* @{
AnnaBridge	189:f392fc9709a3	4094	*/
AnnaBridge	189:f392fc9709a3	4095
AnnaBridge	189:f392fc9709a3	4096	/**
AnnaBridge	189:f392fc9709a3	4097	* @brief Enable PLLSAI1
AnnaBridge	189:f392fc9709a3	4098	* @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
AnnaBridge	189:f392fc9709a3	4099	* @retval None
AnnaBridge	189:f392fc9709a3	4100	*/
AnnaBridge	189:f392fc9709a3	4101	__STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
AnnaBridge	189:f392fc9709a3	4102	{
AnnaBridge	189:f392fc9709a3	4103	SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
AnnaBridge	189:f392fc9709a3	4104	}
AnnaBridge	189:f392fc9709a3	4105
AnnaBridge	189:f392fc9709a3	4106	/**
AnnaBridge	189:f392fc9709a3	4107	* @brief Disable PLLSAI1
AnnaBridge	189:f392fc9709a3	4108	* @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
AnnaBridge	189:f392fc9709a3	4109	* @retval None
AnnaBridge	189:f392fc9709a3	4110	*/
AnnaBridge	189:f392fc9709a3	4111	__STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
AnnaBridge	189:f392fc9709a3	4112	{
AnnaBridge	189:f392fc9709a3	4113	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
AnnaBridge	189:f392fc9709a3	4114	}
AnnaBridge	189:f392fc9709a3	4115
AnnaBridge	189:f392fc9709a3	4116	/**
AnnaBridge	189:f392fc9709a3	4117	* @brief Check if PLLSAI1 Ready
AnnaBridge	189:f392fc9709a3	4118	* @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
AnnaBridge	189:f392fc9709a3	4119	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	4120	*/
AnnaBridge	189:f392fc9709a3	4121	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
AnnaBridge	189:f392fc9709a3	4122	{
AnnaBridge	189:f392fc9709a3	4123	return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY));
AnnaBridge	189:f392fc9709a3	4124	}
AnnaBridge	189:f392fc9709a3	4125
AnnaBridge	189:f392fc9709a3	4126	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	189:f392fc9709a3	4127	/**
AnnaBridge	189:f392fc9709a3	4128	* @brief Configure PLLSAI1 used for 48Mhz domain clock
AnnaBridge	189:f392fc9709a3	4129	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	4130	* @note PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
AnnaBridge	189:f392fc9709a3	4131	* @note This can be selected for USB, RNG, SDMMC
AnnaBridge	189:f392fc9709a3	4132	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	189:f392fc9709a3	4133	* PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	189:f392fc9709a3	4134	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	189:f392fc9709a3	4135	* PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
AnnaBridge	189:f392fc9709a3	4136	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4137	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	4138	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	4139	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	4140	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	4141	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4142	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	189:f392fc9709a3	4143	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	189:f392fc9709a3	4144	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	189:f392fc9709a3	4145	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	189:f392fc9709a3	4146	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	189:f392fc9709a3	4147	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	189:f392fc9709a3	4148	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	189:f392fc9709a3	4149	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	189:f392fc9709a3	4150	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	189:f392fc9709a3	4151	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	189:f392fc9709a3	4152	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	189:f392fc9709a3	4153	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	189:f392fc9709a3	4154	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	189:f392fc9709a3	4155	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	189:f392fc9709a3	4156	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	189:f392fc9709a3	4157	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	189:f392fc9709a3	4158	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	4159	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4160	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
AnnaBridge	189:f392fc9709a3	4161	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
AnnaBridge	189:f392fc9709a3	4162	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
AnnaBridge	189:f392fc9709a3	4163	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
AnnaBridge	189:f392fc9709a3	4164	* @retval None
AnnaBridge	189:f392fc9709a3	4165	*/
AnnaBridge	189:f392fc9709a3	4166	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	189:f392fc9709a3	4167	{
AnnaBridge	189:f392fc9709a3	4168	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	189:f392fc9709a3	4169	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M \| RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1Q,
AnnaBridge	189:f392fc9709a3	4170	PLLM \| PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLQ);
AnnaBridge	189:f392fc9709a3	4171	}
AnnaBridge	189:f392fc9709a3	4172	#else
AnnaBridge	189:f392fc9709a3	4173	/**
AnnaBridge	189:f392fc9709a3	4174	* @brief Configure PLLSAI1 used for 48Mhz domain clock
AnnaBridge	189:f392fc9709a3	4175	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	189:f392fc9709a3	4176	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	4177	* @note PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
AnnaBridge	189:f392fc9709a3	4178	* @note This can be selected for USB, RNG, SDMMC
AnnaBridge	189:f392fc9709a3	4179	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	189:f392fc9709a3	4180	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	189:f392fc9709a3	4181	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	189:f392fc9709a3	4182	* PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
AnnaBridge	189:f392fc9709a3	4183	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4184	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	4185	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	4186	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	4187	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	4188	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4189	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	4190	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	4191	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	4192	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	4193	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	4194	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	4195	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	4196	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	4197	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	4198	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4199	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
AnnaBridge	189:f392fc9709a3	4200	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
AnnaBridge	189:f392fc9709a3	4201	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
AnnaBridge	189:f392fc9709a3	4202	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
AnnaBridge	189:f392fc9709a3	4203	* @retval None
AnnaBridge	189:f392fc9709a3	4204	*/
AnnaBridge	189:f392fc9709a3	4205	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	189:f392fc9709a3	4206	{
AnnaBridge	189:f392fc9709a3	4207	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	189:f392fc9709a3	4208	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLQ);
AnnaBridge	189:f392fc9709a3	4209	}
AnnaBridge	189:f392fc9709a3	4210	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	189:f392fc9709a3	4211
AnnaBridge	189:f392fc9709a3	4212	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	4213	/**
AnnaBridge	189:f392fc9709a3	4214	* @brief Configure PLLSAI1 used for SAI domain clock
AnnaBridge	189:f392fc9709a3	4215	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	4216	* @note PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
AnnaBridge	189:f392fc9709a3	4217	* @note This can be selected for SAI1 or SAI2
AnnaBridge	189:f392fc9709a3	4218	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4219	* PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4220	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4221	* PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
AnnaBridge	189:f392fc9709a3	4222	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4223	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	4224	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	4225	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	4226	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	4227	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4228	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	189:f392fc9709a3	4229	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	189:f392fc9709a3	4230	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	189:f392fc9709a3	4231	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	189:f392fc9709a3	4232	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	189:f392fc9709a3	4233	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	189:f392fc9709a3	4234	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	189:f392fc9709a3	4235	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	189:f392fc9709a3	4236	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	189:f392fc9709a3	4237	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	189:f392fc9709a3	4238	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	189:f392fc9709a3	4239	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	189:f392fc9709a3	4240	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	189:f392fc9709a3	4241	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	189:f392fc9709a3	4242	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	189:f392fc9709a3	4243	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	189:f392fc9709a3	4244	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	4245	* @param PLLP This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4246	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
AnnaBridge	189:f392fc9709a3	4247	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
AnnaBridge	189:f392fc9709a3	4248	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
AnnaBridge	189:f392fc9709a3	4249	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
AnnaBridge	189:f392fc9709a3	4250	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
AnnaBridge	189:f392fc9709a3	4251	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	189:f392fc9709a3	4252	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
AnnaBridge	189:f392fc9709a3	4253	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
AnnaBridge	189:f392fc9709a3	4254	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
AnnaBridge	189:f392fc9709a3	4255	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
AnnaBridge	189:f392fc9709a3	4256	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
AnnaBridge	189:f392fc9709a3	4257	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
AnnaBridge	189:f392fc9709a3	4258	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
AnnaBridge	189:f392fc9709a3	4259	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
AnnaBridge	189:f392fc9709a3	4260	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
AnnaBridge	189:f392fc9709a3	4261	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	189:f392fc9709a3	4262	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
AnnaBridge	189:f392fc9709a3	4263	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
AnnaBridge	189:f392fc9709a3	4264	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
AnnaBridge	189:f392fc9709a3	4265	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
AnnaBridge	189:f392fc9709a3	4266	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
AnnaBridge	189:f392fc9709a3	4267	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
AnnaBridge	189:f392fc9709a3	4268	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
AnnaBridge	189:f392fc9709a3	4269	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
AnnaBridge	189:f392fc9709a3	4270	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
AnnaBridge	189:f392fc9709a3	4271	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
AnnaBridge	189:f392fc9709a3	4272	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
AnnaBridge	189:f392fc9709a3	4273	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
AnnaBridge	189:f392fc9709a3	4274	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
AnnaBridge	189:f392fc9709a3	4275	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
AnnaBridge	189:f392fc9709a3	4276	* @retval None
AnnaBridge	189:f392fc9709a3	4277	*/
AnnaBridge	189:f392fc9709a3	4278	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	189:f392fc9709a3	4279	{
AnnaBridge	189:f392fc9709a3	4280	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	189:f392fc9709a3	4281	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M \| RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1PDIV,
AnnaBridge	189:f392fc9709a3	4282	PLLM \| PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLP);
AnnaBridge	189:f392fc9709a3	4283	}
AnnaBridge	189:f392fc9709a3	4284	#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	4285	/**
AnnaBridge	189:f392fc9709a3	4286	* @brief Configure PLLSAI1 used for SAI domain clock
AnnaBridge	189:f392fc9709a3	4287	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	189:f392fc9709a3	4288	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	4289	* @note PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
AnnaBridge	189:f392fc9709a3	4290	* @note This can be selected for SAI1 or SAI2 (*)
AnnaBridge	189:f392fc9709a3	4291	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4292	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4293	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4294	* PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
AnnaBridge	189:f392fc9709a3	4295	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4296	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	4297	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	4298	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	4299	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	4300	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4301	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	4302	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	4303	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	4304	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	4305	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	4306	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	4307	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	4308	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	4309	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	4310	* @param PLLP This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4311	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
AnnaBridge	189:f392fc9709a3	4312	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
AnnaBridge	189:f392fc9709a3	4313	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
AnnaBridge	189:f392fc9709a3	4314	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
AnnaBridge	189:f392fc9709a3	4315	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
AnnaBridge	189:f392fc9709a3	4316	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	189:f392fc9709a3	4317	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
AnnaBridge	189:f392fc9709a3	4318	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
AnnaBridge	189:f392fc9709a3	4319	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
AnnaBridge	189:f392fc9709a3	4320	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
AnnaBridge	189:f392fc9709a3	4321	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
AnnaBridge	189:f392fc9709a3	4322	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
AnnaBridge	189:f392fc9709a3	4323	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
AnnaBridge	189:f392fc9709a3	4324	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
AnnaBridge	189:f392fc9709a3	4325	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
AnnaBridge	189:f392fc9709a3	4326	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	189:f392fc9709a3	4327	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
AnnaBridge	189:f392fc9709a3	4328	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
AnnaBridge	189:f392fc9709a3	4329	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
AnnaBridge	189:f392fc9709a3	4330	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
AnnaBridge	189:f392fc9709a3	4331	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
AnnaBridge	189:f392fc9709a3	4332	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
AnnaBridge	189:f392fc9709a3	4333	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
AnnaBridge	189:f392fc9709a3	4334	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
AnnaBridge	189:f392fc9709a3	4335	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
AnnaBridge	189:f392fc9709a3	4336	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
AnnaBridge	189:f392fc9709a3	4337	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
AnnaBridge	189:f392fc9709a3	4338	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
AnnaBridge	189:f392fc9709a3	4339	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
AnnaBridge	189:f392fc9709a3	4340	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
AnnaBridge	189:f392fc9709a3	4341	* @retval None
AnnaBridge	189:f392fc9709a3	4342	*/
AnnaBridge	189:f392fc9709a3	4343	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	189:f392fc9709a3	4344	{
AnnaBridge	189:f392fc9709a3	4345	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	189:f392fc9709a3	4346	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1PDIV,
AnnaBridge	189:f392fc9709a3	4347	PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLP);
AnnaBridge	189:f392fc9709a3	4348	}
AnnaBridge	189:f392fc9709a3	4349	#else
AnnaBridge	189:f392fc9709a3	4350	/**
AnnaBridge	189:f392fc9709a3	4351	* @brief Configure PLLSAI1 used for SAI domain clock
AnnaBridge	189:f392fc9709a3	4352	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	189:f392fc9709a3	4353	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	4354	* @note PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled.
AnnaBridge	189:f392fc9709a3	4355	* @note This can be selected for SAI1 or SAI2 (*)
AnnaBridge	189:f392fc9709a3	4356	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4357	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4358	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4359	* PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI
AnnaBridge	189:f392fc9709a3	4360	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4361	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	4362	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	4363	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	4364	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	4365	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4366	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	4367	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	4368	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	4369	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	4370	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	4371	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	4372	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	4373	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	4374	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	4375	* @param PLLP This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4376	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	189:f392fc9709a3	4377	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	189:f392fc9709a3	4378	* @retval None
AnnaBridge	189:f392fc9709a3	4379	*/
AnnaBridge	189:f392fc9709a3	4380	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	189:f392fc9709a3	4381	{
AnnaBridge	189:f392fc9709a3	4382	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	189:f392fc9709a3	4383	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLP);
AnnaBridge	189:f392fc9709a3	4384	}
AnnaBridge	189:f392fc9709a3	4385	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge	189:f392fc9709a3	4386
AnnaBridge	189:f392fc9709a3	4387	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	189:f392fc9709a3	4388	/**
AnnaBridge	189:f392fc9709a3	4389	* @brief Configure PLLSAI1 used for ADC domain clock
AnnaBridge	189:f392fc9709a3	4390	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	4391	* @note PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled.
AnnaBridge	189:f392fc9709a3	4392	* @note This can be selected for ADC
AnnaBridge	189:f392fc9709a3	4393	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	189:f392fc9709a3	4394	* PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	189:f392fc9709a3	4395	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	189:f392fc9709a3	4396	* PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
AnnaBridge	189:f392fc9709a3	4397	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4398	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	4399	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	4400	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	4401	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	4402	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4403	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	189:f392fc9709a3	4404	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	189:f392fc9709a3	4405	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	189:f392fc9709a3	4406	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	189:f392fc9709a3	4407	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	189:f392fc9709a3	4408	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	189:f392fc9709a3	4409	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	189:f392fc9709a3	4410	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	189:f392fc9709a3	4411	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	189:f392fc9709a3	4412	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	189:f392fc9709a3	4413	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	189:f392fc9709a3	4414	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	189:f392fc9709a3	4415	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	189:f392fc9709a3	4416	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	189:f392fc9709a3	4417	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	189:f392fc9709a3	4418	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	189:f392fc9709a3	4419	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	4420	* @param PLLR This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4421	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
AnnaBridge	189:f392fc9709a3	4422	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
AnnaBridge	189:f392fc9709a3	4423	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
AnnaBridge	189:f392fc9709a3	4424	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
AnnaBridge	189:f392fc9709a3	4425	* @retval None
AnnaBridge	189:f392fc9709a3	4426	*/
AnnaBridge	189:f392fc9709a3	4427	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	189:f392fc9709a3	4428	{
AnnaBridge	189:f392fc9709a3	4429	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	189:f392fc9709a3	4430	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M \| RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1R,
AnnaBridge	189:f392fc9709a3	4431	PLLM \| PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLR);
AnnaBridge	189:f392fc9709a3	4432	}
AnnaBridge	189:f392fc9709a3	4433	#else
AnnaBridge	189:f392fc9709a3	4434	/**
AnnaBridge	189:f392fc9709a3	4435	* @brief Configure PLLSAI1 used for ADC domain clock
AnnaBridge	189:f392fc9709a3	4436	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	189:f392fc9709a3	4437	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	4438	* @note PLLN/PLLR can be written only when PLLSAI1 is disabled.
AnnaBridge	189:f392fc9709a3	4439	* @note This can be selected for ADC
AnnaBridge	189:f392fc9709a3	4440	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	189:f392fc9709a3	4441	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	189:f392fc9709a3	4442	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	189:f392fc9709a3	4443	* PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
AnnaBridge	189:f392fc9709a3	4444	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4445	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	4446	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	4447	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	4448	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	4449	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4450	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	4451	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	4452	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	4453	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	4454	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	4455	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	4456	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	4457	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	4458	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	4459	* @param PLLR This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4460	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
AnnaBridge	189:f392fc9709a3	4461	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
AnnaBridge	189:f392fc9709a3	4462	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
AnnaBridge	189:f392fc9709a3	4463	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
AnnaBridge	189:f392fc9709a3	4464	* @retval None
AnnaBridge	189:f392fc9709a3	4465	*/
AnnaBridge	189:f392fc9709a3	4466	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	189:f392fc9709a3	4467	{
AnnaBridge	189:f392fc9709a3	4468	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	189:f392fc9709a3	4469	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLR);
AnnaBridge	189:f392fc9709a3	4470	}
AnnaBridge	189:f392fc9709a3	4471	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	189:f392fc9709a3	4472
AnnaBridge	189:f392fc9709a3	4473	/**
AnnaBridge	189:f392fc9709a3	4474	* @brief Get SAI1PLL multiplication factor for VCO
AnnaBridge	189:f392fc9709a3	4475	* @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN
AnnaBridge	189:f392fc9709a3	4476	* @retval Between 8 and 86
AnnaBridge	189:f392fc9709a3	4477	*/
AnnaBridge	189:f392fc9709a3	4478	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
AnnaBridge	189:f392fc9709a3	4479	{
AnnaBridge	189:f392fc9709a3	4480	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
AnnaBridge	189:f392fc9709a3	4481	}
AnnaBridge	189:f392fc9709a3	4482
AnnaBridge	189:f392fc9709a3	4483	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	4484	/**
AnnaBridge	189:f392fc9709a3	4485	* @brief Get SAI1PLL division factor for PLLSAI1P
AnnaBridge	189:f392fc9709a3	4486	* @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
AnnaBridge	189:f392fc9709a3	4487	* @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP
AnnaBridge	189:f392fc9709a3	4488	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	4489	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
AnnaBridge	189:f392fc9709a3	4490	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
AnnaBridge	189:f392fc9709a3	4491	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
AnnaBridge	189:f392fc9709a3	4492	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
AnnaBridge	189:f392fc9709a3	4493	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
AnnaBridge	189:f392fc9709a3	4494	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	189:f392fc9709a3	4495	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
AnnaBridge	189:f392fc9709a3	4496	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
AnnaBridge	189:f392fc9709a3	4497	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
AnnaBridge	189:f392fc9709a3	4498	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
AnnaBridge	189:f392fc9709a3	4499	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
AnnaBridge	189:f392fc9709a3	4500	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
AnnaBridge	189:f392fc9709a3	4501	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
AnnaBridge	189:f392fc9709a3	4502	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
AnnaBridge	189:f392fc9709a3	4503	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
AnnaBridge	189:f392fc9709a3	4504	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	189:f392fc9709a3	4505	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
AnnaBridge	189:f392fc9709a3	4506	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
AnnaBridge	189:f392fc9709a3	4507	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
AnnaBridge	189:f392fc9709a3	4508	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
AnnaBridge	189:f392fc9709a3	4509	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
AnnaBridge	189:f392fc9709a3	4510	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
AnnaBridge	189:f392fc9709a3	4511	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
AnnaBridge	189:f392fc9709a3	4512	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
AnnaBridge	189:f392fc9709a3	4513	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
AnnaBridge	189:f392fc9709a3	4514	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
AnnaBridge	189:f392fc9709a3	4515	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
AnnaBridge	189:f392fc9709a3	4516	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
AnnaBridge	189:f392fc9709a3	4517	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
AnnaBridge	189:f392fc9709a3	4518	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
AnnaBridge	189:f392fc9709a3	4519	*/
AnnaBridge	189:f392fc9709a3	4520	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
AnnaBridge	189:f392fc9709a3	4521	{
AnnaBridge	189:f392fc9709a3	4522	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
AnnaBridge	189:f392fc9709a3	4523	}
AnnaBridge	189:f392fc9709a3	4524	#else
AnnaBridge	189:f392fc9709a3	4525	/**
AnnaBridge	189:f392fc9709a3	4526	* @brief Get SAI1PLL division factor for PLLSAI1P
AnnaBridge	189:f392fc9709a3	4527	* @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
AnnaBridge	189:f392fc9709a3	4528	* @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP
AnnaBridge	189:f392fc9709a3	4529	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	4530	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	189:f392fc9709a3	4531	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	189:f392fc9709a3	4532	*/
AnnaBridge	189:f392fc9709a3	4533	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
AnnaBridge	189:f392fc9709a3	4534	{
AnnaBridge	189:f392fc9709a3	4535	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
AnnaBridge	189:f392fc9709a3	4536	}
AnnaBridge	189:f392fc9709a3	4537	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge	189:f392fc9709a3	4538
AnnaBridge	189:f392fc9709a3	4539	/**
AnnaBridge	189:f392fc9709a3	4540	* @brief Get SAI1PLL division factor for PLLSAI1Q
AnnaBridge	189:f392fc9709a3	4541	* @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
AnnaBridge	189:f392fc9709a3	4542	* @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
AnnaBridge	189:f392fc9709a3	4543	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	4544	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
AnnaBridge	189:f392fc9709a3	4545	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
AnnaBridge	189:f392fc9709a3	4546	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
AnnaBridge	189:f392fc9709a3	4547	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
AnnaBridge	189:f392fc9709a3	4548	*/
AnnaBridge	189:f392fc9709a3	4549	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
AnnaBridge	189:f392fc9709a3	4550	{
AnnaBridge	189:f392fc9709a3	4551	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
AnnaBridge	189:f392fc9709a3	4552	}
AnnaBridge	189:f392fc9709a3	4553
AnnaBridge	189:f392fc9709a3	4554	/**
AnnaBridge	189:f392fc9709a3	4555	* @brief Get PLLSAI1 division factor for PLLSAIR
AnnaBridge	189:f392fc9709a3	4556	* @note Used for PLLADC1CLK (ADC clock)
AnnaBridge	189:f392fc9709a3	4557	* @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
AnnaBridge	189:f392fc9709a3	4558	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	4559	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
AnnaBridge	189:f392fc9709a3	4560	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
AnnaBridge	189:f392fc9709a3	4561	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
AnnaBridge	189:f392fc9709a3	4562	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
AnnaBridge	189:f392fc9709a3	4563	*/
AnnaBridge	189:f392fc9709a3	4564	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
AnnaBridge	189:f392fc9709a3	4565	{
AnnaBridge	189:f392fc9709a3	4566	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
AnnaBridge	189:f392fc9709a3	4567	}
AnnaBridge	189:f392fc9709a3	4568
AnnaBridge	189:f392fc9709a3	4569	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	189:f392fc9709a3	4570	/**
AnnaBridge	189:f392fc9709a3	4571	* @brief Get Division factor for the PLLSAI1
AnnaBridge	189:f392fc9709a3	4572	* @rmtoll PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider
AnnaBridge	189:f392fc9709a3	4573	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	4574	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	189:f392fc9709a3	4575	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	189:f392fc9709a3	4576	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	189:f392fc9709a3	4577	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	189:f392fc9709a3	4578	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	189:f392fc9709a3	4579	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	189:f392fc9709a3	4580	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	189:f392fc9709a3	4581	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	189:f392fc9709a3	4582	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	189:f392fc9709a3	4583	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	189:f392fc9709a3	4584	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	189:f392fc9709a3	4585	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	189:f392fc9709a3	4586	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	189:f392fc9709a3	4587	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	189:f392fc9709a3	4588	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	189:f392fc9709a3	4589	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	189:f392fc9709a3	4590	*/
AnnaBridge	189:f392fc9709a3	4591	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void)
AnnaBridge	189:f392fc9709a3	4592	{
AnnaBridge	189:f392fc9709a3	4593	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M));
AnnaBridge	189:f392fc9709a3	4594	}
AnnaBridge	189:f392fc9709a3	4595	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	189:f392fc9709a3	4596
AnnaBridge	189:f392fc9709a3	4597	/**
AnnaBridge	189:f392fc9709a3	4598	* @brief Enable PLLSAI1 output mapped on SAI domain clock
AnnaBridge	189:f392fc9709a3	4599	* @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI
AnnaBridge	189:f392fc9709a3	4600	* @retval None
AnnaBridge	189:f392fc9709a3	4601	*/
AnnaBridge	189:f392fc9709a3	4602	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
AnnaBridge	189:f392fc9709a3	4603	{
AnnaBridge	189:f392fc9709a3	4604	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
AnnaBridge	189:f392fc9709a3	4605	}
AnnaBridge	189:f392fc9709a3	4606
AnnaBridge	189:f392fc9709a3	4607	/**
AnnaBridge	189:f392fc9709a3	4608	* @brief Disable PLLSAI1 output mapped on SAI domain clock
AnnaBridge	189:f392fc9709a3	4609	* @note In order to save power, when of the PLLSAI1 is
AnnaBridge	189:f392fc9709a3	4610	* not used, should be 0
AnnaBridge	189:f392fc9709a3	4611	* @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI
AnnaBridge	189:f392fc9709a3	4612	* @retval None
AnnaBridge	189:f392fc9709a3	4613	*/
AnnaBridge	189:f392fc9709a3	4614	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
AnnaBridge	189:f392fc9709a3	4615	{
AnnaBridge	189:f392fc9709a3	4616	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
AnnaBridge	189:f392fc9709a3	4617	}
AnnaBridge	189:f392fc9709a3	4618
AnnaBridge	189:f392fc9709a3	4619	/**
AnnaBridge	189:f392fc9709a3	4620	* @brief Enable PLLSAI1 output mapped on 48MHz domain clock
AnnaBridge	189:f392fc9709a3	4621	* @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M
AnnaBridge	189:f392fc9709a3	4622	* @retval None
AnnaBridge	189:f392fc9709a3	4623	*/
AnnaBridge	189:f392fc9709a3	4624	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
AnnaBridge	189:f392fc9709a3	4625	{
AnnaBridge	189:f392fc9709a3	4626	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
AnnaBridge	189:f392fc9709a3	4627	}
AnnaBridge	189:f392fc9709a3	4628
AnnaBridge	189:f392fc9709a3	4629	/**
AnnaBridge	189:f392fc9709a3	4630	* @brief Disable PLLSAI1 output mapped on 48MHz domain clock
AnnaBridge	189:f392fc9709a3	4631	* @note In order to save power, when of the PLLSAI1 is
AnnaBridge	189:f392fc9709a3	4632	* not used, should be 0
AnnaBridge	189:f392fc9709a3	4633	* @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M
AnnaBridge	189:f392fc9709a3	4634	* @retval None
AnnaBridge	189:f392fc9709a3	4635	*/
AnnaBridge	189:f392fc9709a3	4636	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
AnnaBridge	189:f392fc9709a3	4637	{
AnnaBridge	189:f392fc9709a3	4638	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
AnnaBridge	189:f392fc9709a3	4639	}
AnnaBridge	189:f392fc9709a3	4640
AnnaBridge	189:f392fc9709a3	4641	/**
AnnaBridge	189:f392fc9709a3	4642	* @brief Enable PLLSAI1 output mapped on ADC domain clock
AnnaBridge	189:f392fc9709a3	4643	* @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC
AnnaBridge	189:f392fc9709a3	4644	* @retval None
AnnaBridge	189:f392fc9709a3	4645	*/
AnnaBridge	189:f392fc9709a3	4646	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
AnnaBridge	189:f392fc9709a3	4647	{
AnnaBridge	189:f392fc9709a3	4648	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
AnnaBridge	189:f392fc9709a3	4649	}
AnnaBridge	189:f392fc9709a3	4650
AnnaBridge	189:f392fc9709a3	4651	/**
AnnaBridge	189:f392fc9709a3	4652	* @brief Disable PLLSAI1 output mapped on ADC domain clock
AnnaBridge	189:f392fc9709a3	4653	* @note In order to save power, when of the PLLSAI1 is
AnnaBridge	189:f392fc9709a3	4654	* not used, Main PLLSAI1 should be 0
AnnaBridge	189:f392fc9709a3	4655	* @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC
AnnaBridge	189:f392fc9709a3	4656	* @retval None
AnnaBridge	189:f392fc9709a3	4657	*/
AnnaBridge	189:f392fc9709a3	4658	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
AnnaBridge	189:f392fc9709a3	4659	{
AnnaBridge	189:f392fc9709a3	4660	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
AnnaBridge	189:f392fc9709a3	4661	}
AnnaBridge	189:f392fc9709a3	4662
AnnaBridge	189:f392fc9709a3	4663	/**
AnnaBridge	189:f392fc9709a3	4664	* @}
AnnaBridge	189:f392fc9709a3	4665	*/
AnnaBridge	189:f392fc9709a3	4666
AnnaBridge	189:f392fc9709a3	4667	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	189:f392fc9709a3	4668	/** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
AnnaBridge	189:f392fc9709a3	4669	* @{
AnnaBridge	189:f392fc9709a3	4670	*/
AnnaBridge	189:f392fc9709a3	4671
AnnaBridge	189:f392fc9709a3	4672	/**
AnnaBridge	189:f392fc9709a3	4673	* @brief Enable PLLSAI2
AnnaBridge	189:f392fc9709a3	4674	* @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable
AnnaBridge	189:f392fc9709a3	4675	* @retval None
AnnaBridge	189:f392fc9709a3	4676	*/
AnnaBridge	189:f392fc9709a3	4677	__STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
AnnaBridge	189:f392fc9709a3	4678	{
AnnaBridge	189:f392fc9709a3	4679	SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
AnnaBridge	189:f392fc9709a3	4680	}
AnnaBridge	189:f392fc9709a3	4681
AnnaBridge	189:f392fc9709a3	4682	/**
AnnaBridge	189:f392fc9709a3	4683	* @brief Disable PLLSAI2
AnnaBridge	189:f392fc9709a3	4684	* @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable
AnnaBridge	189:f392fc9709a3	4685	* @retval None
AnnaBridge	189:f392fc9709a3	4686	*/
AnnaBridge	189:f392fc9709a3	4687	__STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
AnnaBridge	189:f392fc9709a3	4688	{
AnnaBridge	189:f392fc9709a3	4689	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
AnnaBridge	189:f392fc9709a3	4690	}
AnnaBridge	189:f392fc9709a3	4691
AnnaBridge	189:f392fc9709a3	4692	/**
AnnaBridge	189:f392fc9709a3	4693	* @brief Check if PLLSAI2 Ready
AnnaBridge	189:f392fc9709a3	4694	* @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady
AnnaBridge	189:f392fc9709a3	4695	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	4696	*/
AnnaBridge	189:f392fc9709a3	4697	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
AnnaBridge	189:f392fc9709a3	4698	{
AnnaBridge	189:f392fc9709a3	4699	return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY));
AnnaBridge	189:f392fc9709a3	4700	}
AnnaBridge	189:f392fc9709a3	4701
AnnaBridge	189:f392fc9709a3	4702	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	4703	/**
AnnaBridge	189:f392fc9709a3	4704	* @brief Configure PLLSAI2 used for SAI domain clock
AnnaBridge	189:f392fc9709a3	4705	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	4706	* @note PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
AnnaBridge	189:f392fc9709a3	4707	* @note This can be selected for SAI1 or SAI2
AnnaBridge	189:f392fc9709a3	4708	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4709	* PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4710	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4711	* PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
AnnaBridge	189:f392fc9709a3	4712	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4713	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	4714	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	4715	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	4716	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	4717	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4718	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	189:f392fc9709a3	4719	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	189:f392fc9709a3	4720	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	189:f392fc9709a3	4721	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	189:f392fc9709a3	4722	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	189:f392fc9709a3	4723	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	189:f392fc9709a3	4724	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	189:f392fc9709a3	4725	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	189:f392fc9709a3	4726	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	189:f392fc9709a3	4727	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	189:f392fc9709a3	4728	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	189:f392fc9709a3	4729	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	189:f392fc9709a3	4730	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	189:f392fc9709a3	4731	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	189:f392fc9709a3	4732	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	189:f392fc9709a3	4733	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	189:f392fc9709a3	4734	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	4735	* @param PLLP This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4736	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	189:f392fc9709a3	4737	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	189:f392fc9709a3	4738	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	189:f392fc9709a3	4739	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	189:f392fc9709a3	4740	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	189:f392fc9709a3	4741	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	189:f392fc9709a3	4742	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	189:f392fc9709a3	4743	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	189:f392fc9709a3	4744	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	189:f392fc9709a3	4745	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	189:f392fc9709a3	4746	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	189:f392fc9709a3	4747	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	189:f392fc9709a3	4748	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	189:f392fc9709a3	4749	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	189:f392fc9709a3	4750	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	189:f392fc9709a3	4751	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	189:f392fc9709a3	4752	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	189:f392fc9709a3	4753	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	189:f392fc9709a3	4754	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	189:f392fc9709a3	4755	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	189:f392fc9709a3	4756	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	189:f392fc9709a3	4757	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	189:f392fc9709a3	4758	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	189:f392fc9709a3	4759	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	189:f392fc9709a3	4760	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	189:f392fc9709a3	4761	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	189:f392fc9709a3	4762	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	189:f392fc9709a3	4763	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	189:f392fc9709a3	4764	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	189:f392fc9709a3	4765	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	189:f392fc9709a3	4766	* @retval None
AnnaBridge	189:f392fc9709a3	4767	*/
AnnaBridge	189:f392fc9709a3	4768	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	189:f392fc9709a3	4769	{
AnnaBridge	189:f392fc9709a3	4770	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	189:f392fc9709a3	4771	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M \| RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2PDIV,
AnnaBridge	189:f392fc9709a3	4772	PLLM \| PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLP);
AnnaBridge	189:f392fc9709a3	4773	}
AnnaBridge	189:f392fc9709a3	4774	#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	4775	/**
AnnaBridge	189:f392fc9709a3	4776	* @brief Configure PLLSAI2 used for SAI domain clock
AnnaBridge	189:f392fc9709a3	4777	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	189:f392fc9709a3	4778	* PLLSAI1 and PLLSAI2 are disabled.
AnnaBridge	189:f392fc9709a3	4779	* @note PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
AnnaBridge	189:f392fc9709a3	4780	* @note This can be selected for SAI1 or SAI2
AnnaBridge	189:f392fc9709a3	4781	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4782	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4783	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4784	* PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
AnnaBridge	189:f392fc9709a3	4785	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4786	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	4787	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	4788	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	4789	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	4790	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4791	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	4792	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	4793	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	4794	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	4795	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	4796	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	4797	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	4798	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	4799	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	4800	* @param PLLP This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4801	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	189:f392fc9709a3	4802	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	189:f392fc9709a3	4803	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	189:f392fc9709a3	4804	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	189:f392fc9709a3	4805	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	189:f392fc9709a3	4806	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	189:f392fc9709a3	4807	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	189:f392fc9709a3	4808	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	189:f392fc9709a3	4809	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	189:f392fc9709a3	4810	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	189:f392fc9709a3	4811	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	189:f392fc9709a3	4812	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	189:f392fc9709a3	4813	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	189:f392fc9709a3	4814	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	189:f392fc9709a3	4815	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	189:f392fc9709a3	4816	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	189:f392fc9709a3	4817	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	189:f392fc9709a3	4818	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	189:f392fc9709a3	4819	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	189:f392fc9709a3	4820	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	189:f392fc9709a3	4821	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	189:f392fc9709a3	4822	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	189:f392fc9709a3	4823	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	189:f392fc9709a3	4824	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	189:f392fc9709a3	4825	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	189:f392fc9709a3	4826	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	189:f392fc9709a3	4827	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	189:f392fc9709a3	4828	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	189:f392fc9709a3	4829	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	189:f392fc9709a3	4830	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	189:f392fc9709a3	4831	* @retval None
AnnaBridge	189:f392fc9709a3	4832	*/
AnnaBridge	189:f392fc9709a3	4833	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	189:f392fc9709a3	4834	{
AnnaBridge	189:f392fc9709a3	4835	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	189:f392fc9709a3	4836	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLP);
AnnaBridge	189:f392fc9709a3	4837	}
AnnaBridge	189:f392fc9709a3	4838	#else
AnnaBridge	189:f392fc9709a3	4839	/**
AnnaBridge	189:f392fc9709a3	4840	* @brief Configure PLLSAI2 used for SAI domain clock
AnnaBridge	189:f392fc9709a3	4841	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	189:f392fc9709a3	4842	* PLLSAI2 and PLLSAI2 are disabled.
AnnaBridge	189:f392fc9709a3	4843	* @note PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled.
AnnaBridge	189:f392fc9709a3	4844	* @note This can be selected for SAI1 or SAI2
AnnaBridge	189:f392fc9709a3	4845	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4846	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4847	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	189:f392fc9709a3	4848	* PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI
AnnaBridge	189:f392fc9709a3	4849	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4850	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	4851	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	4852	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	4853	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	4854	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4855	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	4856	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	4857	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	4858	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	4859	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	4860	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	4861	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	4862	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	4863	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	4864	* @param PLLP This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4865	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	189:f392fc9709a3	4866	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	189:f392fc9709a3	4867	* @retval None
AnnaBridge	189:f392fc9709a3	4868	*/
AnnaBridge	189:f392fc9709a3	4869	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	189:f392fc9709a3	4870	{
AnnaBridge	189:f392fc9709a3	4871	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	189:f392fc9709a3	4872	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLP);
AnnaBridge	189:f392fc9709a3	4873	}
AnnaBridge	189:f392fc9709a3	4874	#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge	189:f392fc9709a3	4875
AnnaBridge	189:f392fc9709a3	4876	#if defined(DSI)
AnnaBridge	189:f392fc9709a3	4877	/**
AnnaBridge	189:f392fc9709a3	4878	* @brief Configure PLLSAI2 used for DSI domain clock
AnnaBridge	189:f392fc9709a3	4879	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	4880	* @note PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled.
AnnaBridge	189:f392fc9709a3	4881	* @note This can be selected for DSI
AnnaBridge	189:f392fc9709a3	4882	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_DSI\n
AnnaBridge	189:f392fc9709a3	4883	* PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_DSI\n
AnnaBridge	189:f392fc9709a3	4884	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_DSI\n
AnnaBridge	189:f392fc9709a3	4885	* PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_ConfigDomain_DSI
AnnaBridge	189:f392fc9709a3	4886	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4887	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	4888	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	4889	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	4890	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	4891	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4892	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	189:f392fc9709a3	4893	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	189:f392fc9709a3	4894	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	189:f392fc9709a3	4895	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	189:f392fc9709a3	4896	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	189:f392fc9709a3	4897	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	189:f392fc9709a3	4898	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	189:f392fc9709a3	4899	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	189:f392fc9709a3	4900	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	189:f392fc9709a3	4901	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	189:f392fc9709a3	4902	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	189:f392fc9709a3	4903	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	189:f392fc9709a3	4904	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	189:f392fc9709a3	4905	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	189:f392fc9709a3	4906	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	189:f392fc9709a3	4907	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	189:f392fc9709a3	4908	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	4909	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4910	* @arg @ref LL_RCC_PLLSAI2Q_DIV_2
AnnaBridge	189:f392fc9709a3	4911	* @arg @ref LL_RCC_PLLSAI2Q_DIV_4
AnnaBridge	189:f392fc9709a3	4912	* @arg @ref LL_RCC_PLLSAI2Q_DIV_6
AnnaBridge	189:f392fc9709a3	4913	* @arg @ref LL_RCC_PLLSAI2Q_DIV_8
AnnaBridge	189:f392fc9709a3	4914	* @retval None
AnnaBridge	189:f392fc9709a3	4915	*/
AnnaBridge	189:f392fc9709a3	4916	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	189:f392fc9709a3	4917	{
AnnaBridge	189:f392fc9709a3	4918	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	189:f392fc9709a3	4919	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M \| RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2Q, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLQ \| PLLM);
AnnaBridge	189:f392fc9709a3	4920	}
AnnaBridge	189:f392fc9709a3	4921	#endif /* DSI */
AnnaBridge	189:f392fc9709a3	4922
AnnaBridge	189:f392fc9709a3	4923	#if defined(LTDC)
AnnaBridge	189:f392fc9709a3	4924	/**
AnnaBridge	189:f392fc9709a3	4925	* @brief Configure PLLSAI2 used for LTDC domain clock
AnnaBridge	189:f392fc9709a3	4926	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	189:f392fc9709a3	4927	* @note PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
AnnaBridge	189:f392fc9709a3	4928	* @note This can be selected for LTDC
AnnaBridge	189:f392fc9709a3	4929	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
AnnaBridge	189:f392fc9709a3	4930	* PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
AnnaBridge	189:f392fc9709a3	4931	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
AnnaBridge	189:f392fc9709a3	4932	* PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
AnnaBridge	189:f392fc9709a3	4933	* CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_ConfigDomain_LTDC
AnnaBridge	189:f392fc9709a3	4934	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4935	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	4936	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	4937	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	4938	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	4939	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4940	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	189:f392fc9709a3	4941	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	189:f392fc9709a3	4942	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	189:f392fc9709a3	4943	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	189:f392fc9709a3	4944	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	189:f392fc9709a3	4945	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	189:f392fc9709a3	4946	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	189:f392fc9709a3	4947	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	189:f392fc9709a3	4948	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	189:f392fc9709a3	4949	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	189:f392fc9709a3	4950	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	189:f392fc9709a3	4951	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	189:f392fc9709a3	4952	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	189:f392fc9709a3	4953	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	189:f392fc9709a3	4954	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	189:f392fc9709a3	4955	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	189:f392fc9709a3	4956	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	4957	* @param PLLR This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4958	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
AnnaBridge	189:f392fc9709a3	4959	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
AnnaBridge	189:f392fc9709a3	4960	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
AnnaBridge	189:f392fc9709a3	4961	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
AnnaBridge	189:f392fc9709a3	4962	* @param PLLDIVR This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4963	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
AnnaBridge	189:f392fc9709a3	4964	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
AnnaBridge	189:f392fc9709a3	4965	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
AnnaBridge	189:f392fc9709a3	4966	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
AnnaBridge	189:f392fc9709a3	4967	* @retval None
AnnaBridge	189:f392fc9709a3	4968	*/
AnnaBridge	189:f392fc9709a3	4969	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
AnnaBridge	189:f392fc9709a3	4970	{
AnnaBridge	189:f392fc9709a3	4971	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	189:f392fc9709a3	4972	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M \| RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLR \| PLLM);
AnnaBridge	189:f392fc9709a3	4973	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR);
AnnaBridge	189:f392fc9709a3	4974	}
AnnaBridge	189:f392fc9709a3	4975	#else
AnnaBridge	189:f392fc9709a3	4976	/**
AnnaBridge	189:f392fc9709a3	4977	* @brief Configure PLLSAI2 used for ADC domain clock
AnnaBridge	189:f392fc9709a3	4978	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	189:f392fc9709a3	4979	* PLLSAI2 and PLLSAI2 are disabled.
AnnaBridge	189:f392fc9709a3	4980	* @note PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
AnnaBridge	189:f392fc9709a3	4981	* @note This can be selected for ADC
AnnaBridge	189:f392fc9709a3	4982	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n
AnnaBridge	189:f392fc9709a3	4983	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n
AnnaBridge	189:f392fc9709a3	4984	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n
AnnaBridge	189:f392fc9709a3	4985	* PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC
AnnaBridge	189:f392fc9709a3	4986	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4987	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	189:f392fc9709a3	4988	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	189:f392fc9709a3	4989	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	4990	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	4991	* @param PLLM This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	4992	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	189:f392fc9709a3	4993	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	189:f392fc9709a3	4994	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	189:f392fc9709a3	4995	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	189:f392fc9709a3	4996	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	189:f392fc9709a3	4997	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	189:f392fc9709a3	4998	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	189:f392fc9709a3	4999	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	189:f392fc9709a3	5000	* @param PLLN Between 8 and 86
AnnaBridge	189:f392fc9709a3	5001	* @param PLLR This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	5002	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
AnnaBridge	189:f392fc9709a3	5003	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
AnnaBridge	189:f392fc9709a3	5004	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
AnnaBridge	189:f392fc9709a3	5005	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
AnnaBridge	189:f392fc9709a3	5006	* @retval None
AnnaBridge	189:f392fc9709a3	5007	*/
AnnaBridge	189:f392fc9709a3	5008	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	189:f392fc9709a3	5009	{
AnnaBridge	189:f392fc9709a3	5010	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	189:f392fc9709a3	5011	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLR);
AnnaBridge	189:f392fc9709a3	5012	}
AnnaBridge	189:f392fc9709a3	5013	#endif /* LTDC */
AnnaBridge	189:f392fc9709a3	5014
AnnaBridge	189:f392fc9709a3	5015	/**
AnnaBridge	189:f392fc9709a3	5016	* @brief Get SAI2PLL multiplication factor for VCO
AnnaBridge	189:f392fc9709a3	5017	* @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN
AnnaBridge	189:f392fc9709a3	5018	* @retval Between 8 and 86
AnnaBridge	189:f392fc9709a3	5019	*/
AnnaBridge	189:f392fc9709a3	5020	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
AnnaBridge	189:f392fc9709a3	5021	{
AnnaBridge	189:f392fc9709a3	5022	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
AnnaBridge	189:f392fc9709a3	5023	}
AnnaBridge	189:f392fc9709a3	5024
AnnaBridge	189:f392fc9709a3	5025	#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	189:f392fc9709a3	5026	/**
AnnaBridge	189:f392fc9709a3	5027	* @brief Get SAI2PLL division factor for PLLSAI2P
AnnaBridge	189:f392fc9709a3	5028	* @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
AnnaBridge	189:f392fc9709a3	5029	* @rmtoll PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP
AnnaBridge	189:f392fc9709a3	5030	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	5031	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	189:f392fc9709a3	5032	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	189:f392fc9709a3	5033	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	189:f392fc9709a3	5034	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	189:f392fc9709a3	5035	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	189:f392fc9709a3	5036	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	189:f392fc9709a3	5037	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	189:f392fc9709a3	5038	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	189:f392fc9709a3	5039	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	189:f392fc9709a3	5040	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	189:f392fc9709a3	5041	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	189:f392fc9709a3	5042	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	189:f392fc9709a3	5043	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	189:f392fc9709a3	5044	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	189:f392fc9709a3	5045	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	189:f392fc9709a3	5046	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	189:f392fc9709a3	5047	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	189:f392fc9709a3	5048	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	189:f392fc9709a3	5049	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	189:f392fc9709a3	5050	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	189:f392fc9709a3	5051	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	189:f392fc9709a3	5052	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	189:f392fc9709a3	5053	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	189:f392fc9709a3	5054	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	189:f392fc9709a3	5055	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	189:f392fc9709a3	5056	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	189:f392fc9709a3	5057	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	189:f392fc9709a3	5058	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	189:f392fc9709a3	5059	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	189:f392fc9709a3	5060	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	189:f392fc9709a3	5061	*/
AnnaBridge	189:f392fc9709a3	5062	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
AnnaBridge	189:f392fc9709a3	5063	{
AnnaBridge	189:f392fc9709a3	5064	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV));
AnnaBridge	189:f392fc9709a3	5065	}
AnnaBridge	189:f392fc9709a3	5066	#else
AnnaBridge	189:f392fc9709a3	5067	/**
AnnaBridge	189:f392fc9709a3	5068	* @brief Get SAI2PLL division factor for PLLSAI2P
AnnaBridge	189:f392fc9709a3	5069	* @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
AnnaBridge	189:f392fc9709a3	5070	* @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP
AnnaBridge	189:f392fc9709a3	5071	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	5072	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	189:f392fc9709a3	5073	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	189:f392fc9709a3	5074	*/
AnnaBridge	189:f392fc9709a3	5075	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
AnnaBridge	189:f392fc9709a3	5076	{
AnnaBridge	189:f392fc9709a3	5077	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
AnnaBridge	189:f392fc9709a3	5078	}
AnnaBridge	189:f392fc9709a3	5079	#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge	189:f392fc9709a3	5080
AnnaBridge	189:f392fc9709a3	5081	#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
AnnaBridge	189:f392fc9709a3	5082	/**
AnnaBridge	189:f392fc9709a3	5083	* @brief Get division factor for PLLSAI2Q
AnnaBridge	189:f392fc9709a3	5084	* @note Used for PLLDSICLK (DSI clock)
AnnaBridge	189:f392fc9709a3	5085	* @rmtoll PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_GetQ
AnnaBridge	189:f392fc9709a3	5086	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	5087	* @arg @ref LL_RCC_PLLSAI2Q_DIV_2
AnnaBridge	189:f392fc9709a3	5088	* @arg @ref LL_RCC_PLLSAI2Q_DIV_4
AnnaBridge	189:f392fc9709a3	5089	* @arg @ref LL_RCC_PLLSAI2Q_DIV_6
AnnaBridge	189:f392fc9709a3	5090	* @arg @ref LL_RCC_PLLSAI2Q_DIV_8
AnnaBridge	189:f392fc9709a3	5091	*/
AnnaBridge	189:f392fc9709a3	5092	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void)
AnnaBridge	189:f392fc9709a3	5093	{
AnnaBridge	189:f392fc9709a3	5094	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q));
AnnaBridge	189:f392fc9709a3	5095	}
AnnaBridge	189:f392fc9709a3	5096	#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
AnnaBridge	189:f392fc9709a3	5097
AnnaBridge	189:f392fc9709a3	5098	/**
AnnaBridge	189:f392fc9709a3	5099	* @brief Get SAI2PLL division factor for PLLSAI2R
AnnaBridge	189:f392fc9709a3	5100	* @note Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices
AnnaBridge	189:f392fc9709a3	5101	* @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR
AnnaBridge	189:f392fc9709a3	5102	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	5103	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
AnnaBridge	189:f392fc9709a3	5104	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
AnnaBridge	189:f392fc9709a3	5105	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
AnnaBridge	189:f392fc9709a3	5106	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
AnnaBridge	189:f392fc9709a3	5107	*/
AnnaBridge	189:f392fc9709a3	5108	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
AnnaBridge	189:f392fc9709a3	5109	{
AnnaBridge	189:f392fc9709a3	5110	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
AnnaBridge	189:f392fc9709a3	5111	}
AnnaBridge	189:f392fc9709a3	5112
AnnaBridge	189:f392fc9709a3	5113	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
AnnaBridge	189:f392fc9709a3	5114	/**
AnnaBridge	189:f392fc9709a3	5115	* @brief Get Division factor for the PLLSAI2
AnnaBridge	189:f392fc9709a3	5116	* @rmtoll PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider
AnnaBridge	189:f392fc9709a3	5117	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	5118	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	189:f392fc9709a3	5119	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	189:f392fc9709a3	5120	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	189:f392fc9709a3	5121	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	189:f392fc9709a3	5122	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	189:f392fc9709a3	5123	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	189:f392fc9709a3	5124	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	189:f392fc9709a3	5125	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	189:f392fc9709a3	5126	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	189:f392fc9709a3	5127	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	189:f392fc9709a3	5128	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	189:f392fc9709a3	5129	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	189:f392fc9709a3	5130	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	189:f392fc9709a3	5131	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	189:f392fc9709a3	5132	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	189:f392fc9709a3	5133	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	189:f392fc9709a3	5134	*/
AnnaBridge	189:f392fc9709a3	5135	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void)
AnnaBridge	189:f392fc9709a3	5136	{
AnnaBridge	189:f392fc9709a3	5137	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M));
AnnaBridge	189:f392fc9709a3	5138	}
AnnaBridge	189:f392fc9709a3	5139	#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
AnnaBridge	189:f392fc9709a3	5140
AnnaBridge	189:f392fc9709a3	5141	#if defined(RCC_CCIPR2_PLLSAI2DIVR)
AnnaBridge	189:f392fc9709a3	5142	/**
AnnaBridge	189:f392fc9709a3	5143	* @brief Get PLLSAI2 division factor for PLLSAI2DIVR
AnnaBridge	189:f392fc9709a3	5144	* @note Used for LTDC domain clock
AnnaBridge	189:f392fc9709a3	5145	* @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_GetDIVR
AnnaBridge	189:f392fc9709a3	5146	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	5147	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
AnnaBridge	189:f392fc9709a3	5148	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
AnnaBridge	189:f392fc9709a3	5149	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
AnnaBridge	189:f392fc9709a3	5150	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
AnnaBridge	189:f392fc9709a3	5151	*/
AnnaBridge	189:f392fc9709a3	5152	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void)
AnnaBridge	189:f392fc9709a3	5153	{
AnnaBridge	189:f392fc9709a3	5154	return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR));
AnnaBridge	189:f392fc9709a3	5155	}
AnnaBridge	189:f392fc9709a3	5156	#endif /* RCC_CCIPR2_PLLSAI2DIVR */
AnnaBridge	189:f392fc9709a3	5157
AnnaBridge	189:f392fc9709a3	5158	/**
AnnaBridge	189:f392fc9709a3	5159	* @brief Enable PLLSAI2 output mapped on SAI domain clock
AnnaBridge	189:f392fc9709a3	5160	* @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI
AnnaBridge	189:f392fc9709a3	5161	* @retval None
AnnaBridge	189:f392fc9709a3	5162	*/
AnnaBridge	189:f392fc9709a3	5163	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
AnnaBridge	189:f392fc9709a3	5164	{
AnnaBridge	189:f392fc9709a3	5165	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
AnnaBridge	189:f392fc9709a3	5166	}
AnnaBridge	189:f392fc9709a3	5167
AnnaBridge	189:f392fc9709a3	5168	/**
AnnaBridge	189:f392fc9709a3	5169	* @brief Disable PLLSAI2 output mapped on SAI domain clock
AnnaBridge	189:f392fc9709a3	5170	* @note In order to save power, when of the PLLSAI2 is
AnnaBridge	189:f392fc9709a3	5171	* not used, should be 0
AnnaBridge	189:f392fc9709a3	5172	* @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI
AnnaBridge	189:f392fc9709a3	5173	* @retval None
AnnaBridge	189:f392fc9709a3	5174	*/
AnnaBridge	189:f392fc9709a3	5175	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
AnnaBridge	189:f392fc9709a3	5176	{
AnnaBridge	189:f392fc9709a3	5177	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
AnnaBridge	189:f392fc9709a3	5178	}
AnnaBridge	189:f392fc9709a3	5179
AnnaBridge	189:f392fc9709a3	5180	#if defined(DSI)
AnnaBridge	189:f392fc9709a3	5181	/**
AnnaBridge	189:f392fc9709a3	5182	* @brief Enable PLLSAI2 output mapped on DSI domain clock
AnnaBridge	189:f392fc9709a3	5183	* @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI
AnnaBridge	189:f392fc9709a3	5184	* @retval None
AnnaBridge	189:f392fc9709a3	5185	*/
AnnaBridge	189:f392fc9709a3	5186	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void)
AnnaBridge	189:f392fc9709a3	5187	{
AnnaBridge	189:f392fc9709a3	5188	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
AnnaBridge	189:f392fc9709a3	5189	}
AnnaBridge	189:f392fc9709a3	5190
AnnaBridge	189:f392fc9709a3	5191	/**
AnnaBridge	189:f392fc9709a3	5192	* @brief Disable PLLSAI2 output mapped on DSI domain clock
AnnaBridge	189:f392fc9709a3	5193	* @note In order to save power, when of the PLLSAI2 is
AnnaBridge	189:f392fc9709a3	5194	* not used, Main PLLSAI2 should be 0
AnnaBridge	189:f392fc9709a3	5195	* @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_DisableDomain_DSI
AnnaBridge	189:f392fc9709a3	5196	* @retval None
AnnaBridge	189:f392fc9709a3	5197	*/
AnnaBridge	189:f392fc9709a3	5198	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void)
AnnaBridge	189:f392fc9709a3	5199	{
AnnaBridge	189:f392fc9709a3	5200	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
AnnaBridge	189:f392fc9709a3	5201	}
AnnaBridge	189:f392fc9709a3	5202	#endif /* DSI */
AnnaBridge	189:f392fc9709a3	5203
AnnaBridge	189:f392fc9709a3	5204	#if defined(LTDC)
AnnaBridge	189:f392fc9709a3	5205	/**
AnnaBridge	189:f392fc9709a3	5206	* @brief Enable PLLSAI2 output mapped on LTDC domain clock
AnnaBridge	189:f392fc9709a3	5207	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC
AnnaBridge	189:f392fc9709a3	5208	* @retval None
AnnaBridge	189:f392fc9709a3	5209	*/
AnnaBridge	189:f392fc9709a3	5210	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void)
AnnaBridge	189:f392fc9709a3	5211	{
AnnaBridge	189:f392fc9709a3	5212	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
AnnaBridge	189:f392fc9709a3	5213	}
AnnaBridge	189:f392fc9709a3	5214
AnnaBridge	189:f392fc9709a3	5215	/**
AnnaBridge	189:f392fc9709a3	5216	* @brief Disable PLLSAI2 output mapped on LTDC domain clock
AnnaBridge	189:f392fc9709a3	5217	* @note In order to save power, when of the PLLSAI2 is
AnnaBridge	189:f392fc9709a3	5218	* not used, Main PLLSAI2 should be 0
AnnaBridge	189:f392fc9709a3	5219	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_LTDC
AnnaBridge	189:f392fc9709a3	5220	* @retval None
AnnaBridge	189:f392fc9709a3	5221	*/
AnnaBridge	189:f392fc9709a3	5222	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void)
AnnaBridge	189:f392fc9709a3	5223	{
AnnaBridge	189:f392fc9709a3	5224	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
AnnaBridge	189:f392fc9709a3	5225	}
AnnaBridge	189:f392fc9709a3	5226	#else
AnnaBridge	189:f392fc9709a3	5227	/**
AnnaBridge	189:f392fc9709a3	5228	* @brief Enable PLLSAI2 output mapped on ADC domain clock
AnnaBridge	189:f392fc9709a3	5229	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC
AnnaBridge	189:f392fc9709a3	5230	* @retval None
AnnaBridge	189:f392fc9709a3	5231	*/
AnnaBridge	189:f392fc9709a3	5232	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
AnnaBridge	189:f392fc9709a3	5233	{
AnnaBridge	189:f392fc9709a3	5234	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
AnnaBridge	189:f392fc9709a3	5235	}
AnnaBridge	189:f392fc9709a3	5236
AnnaBridge	189:f392fc9709a3	5237	/**
AnnaBridge	189:f392fc9709a3	5238	* @brief Disable PLLSAI2 output mapped on ADC domain clock
AnnaBridge	189:f392fc9709a3	5239	* @note In order to save power, when of the PLLSAI2 is
AnnaBridge	189:f392fc9709a3	5240	* not used, Main PLLSAI2 should be 0
AnnaBridge	189:f392fc9709a3	5241	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC
AnnaBridge	189:f392fc9709a3	5242	* @retval None
AnnaBridge	189:f392fc9709a3	5243	*/
AnnaBridge	189:f392fc9709a3	5244	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
AnnaBridge	189:f392fc9709a3	5245	{
AnnaBridge	189:f392fc9709a3	5246	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
AnnaBridge	189:f392fc9709a3	5247	}
AnnaBridge	189:f392fc9709a3	5248	#endif /* LTDC */
AnnaBridge	189:f392fc9709a3	5249
AnnaBridge	189:f392fc9709a3	5250	/**
AnnaBridge	189:f392fc9709a3	5251	* @}
AnnaBridge	189:f392fc9709a3	5252	*/
AnnaBridge	189:f392fc9709a3	5253	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	189:f392fc9709a3	5254
AnnaBridge	189:f392fc9709a3	5255
AnnaBridge	189:f392fc9709a3	5256
AnnaBridge	189:f392fc9709a3	5257	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	189:f392fc9709a3	5258	* @{
AnnaBridge	189:f392fc9709a3	5259	*/
AnnaBridge	189:f392fc9709a3	5260
AnnaBridge	189:f392fc9709a3	5261	/**
AnnaBridge	189:f392fc9709a3	5262	* @brief Clear LSI ready interrupt flag
AnnaBridge	189:f392fc9709a3	5263	* @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
AnnaBridge	189:f392fc9709a3	5264	* @retval None
AnnaBridge	189:f392fc9709a3	5265	*/
AnnaBridge	189:f392fc9709a3	5266	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
AnnaBridge	189:f392fc9709a3	5267	{
AnnaBridge	189:f392fc9709a3	5268	SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
AnnaBridge	189:f392fc9709a3	5269	}
AnnaBridge	189:f392fc9709a3	5270
AnnaBridge	189:f392fc9709a3	5271	/**
AnnaBridge	189:f392fc9709a3	5272	* @brief Clear LSE ready interrupt flag
AnnaBridge	189:f392fc9709a3	5273	* @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
AnnaBridge	189:f392fc9709a3	5274	* @retval None
AnnaBridge	189:f392fc9709a3	5275	*/
AnnaBridge	189:f392fc9709a3	5276	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
AnnaBridge	189:f392fc9709a3	5277	{
AnnaBridge	189:f392fc9709a3	5278	SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
AnnaBridge	189:f392fc9709a3	5279	}
AnnaBridge	189:f392fc9709a3	5280
AnnaBridge	189:f392fc9709a3	5281	/**
AnnaBridge	189:f392fc9709a3	5282	* @brief Clear MSI ready interrupt flag
AnnaBridge	189:f392fc9709a3	5283	* @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
AnnaBridge	189:f392fc9709a3	5284	* @retval None
AnnaBridge	189:f392fc9709a3	5285	*/
AnnaBridge	189:f392fc9709a3	5286	__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
AnnaBridge	189:f392fc9709a3	5287	{
AnnaBridge	189:f392fc9709a3	5288	SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
AnnaBridge	189:f392fc9709a3	5289	}
AnnaBridge	189:f392fc9709a3	5290
AnnaBridge	189:f392fc9709a3	5291	/**
AnnaBridge	189:f392fc9709a3	5292	* @brief Clear HSI ready interrupt flag
AnnaBridge	189:f392fc9709a3	5293	* @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
AnnaBridge	189:f392fc9709a3	5294	* @retval None
AnnaBridge	189:f392fc9709a3	5295	*/
AnnaBridge	189:f392fc9709a3	5296	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
AnnaBridge	189:f392fc9709a3	5297	{
AnnaBridge	189:f392fc9709a3	5298	SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
AnnaBridge	189:f392fc9709a3	5299	}
AnnaBridge	189:f392fc9709a3	5300
AnnaBridge	189:f392fc9709a3	5301	/**
AnnaBridge	189:f392fc9709a3	5302	* @brief Clear HSE ready interrupt flag
AnnaBridge	189:f392fc9709a3	5303	* @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
AnnaBridge	189:f392fc9709a3	5304	* @retval None
AnnaBridge	189:f392fc9709a3	5305	*/
AnnaBridge	189:f392fc9709a3	5306	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
AnnaBridge	189:f392fc9709a3	5307	{
AnnaBridge	189:f392fc9709a3	5308	SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
AnnaBridge	189:f392fc9709a3	5309	}
AnnaBridge	189:f392fc9709a3	5310
AnnaBridge	189:f392fc9709a3	5311	/**
AnnaBridge	189:f392fc9709a3	5312	* @brief Clear PLL ready interrupt flag
AnnaBridge	189:f392fc9709a3	5313	* @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
AnnaBridge	189:f392fc9709a3	5314	* @retval None
AnnaBridge	189:f392fc9709a3	5315	*/
AnnaBridge	189:f392fc9709a3	5316	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
AnnaBridge	189:f392fc9709a3	5317	{
AnnaBridge	189:f392fc9709a3	5318	SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
AnnaBridge	189:f392fc9709a3	5319	}
AnnaBridge	189:f392fc9709a3	5320
AnnaBridge	189:f392fc9709a3	5321	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	5322	/**
AnnaBridge	189:f392fc9709a3	5323	* @brief Clear HSI48 ready interrupt flag
AnnaBridge	189:f392fc9709a3	5324	* @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
AnnaBridge	189:f392fc9709a3	5325	* @retval None
AnnaBridge	189:f392fc9709a3	5326	*/
AnnaBridge	189:f392fc9709a3	5327	__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
AnnaBridge	189:f392fc9709a3	5328	{
AnnaBridge	189:f392fc9709a3	5329	SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
AnnaBridge	189:f392fc9709a3	5330	}
AnnaBridge	189:f392fc9709a3	5331	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	5332
AnnaBridge	189:f392fc9709a3	5333	/**
AnnaBridge	189:f392fc9709a3	5334	* @brief Clear PLLSAI1 ready interrupt flag
AnnaBridge	189:f392fc9709a3	5335	* @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
AnnaBridge	189:f392fc9709a3	5336	* @retval None
AnnaBridge	189:f392fc9709a3	5337	*/
AnnaBridge	189:f392fc9709a3	5338	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
AnnaBridge	189:f392fc9709a3	5339	{
AnnaBridge	189:f392fc9709a3	5340	SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
AnnaBridge	189:f392fc9709a3	5341	}
AnnaBridge	189:f392fc9709a3	5342
AnnaBridge	189:f392fc9709a3	5343	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	189:f392fc9709a3	5344	/**
AnnaBridge	189:f392fc9709a3	5345	* @brief Clear PLLSAI1 ready interrupt flag
AnnaBridge	189:f392fc9709a3	5346	* @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY
AnnaBridge	189:f392fc9709a3	5347	* @retval None
AnnaBridge	189:f392fc9709a3	5348	*/
AnnaBridge	189:f392fc9709a3	5349	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
AnnaBridge	189:f392fc9709a3	5350	{
AnnaBridge	189:f392fc9709a3	5351	SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
AnnaBridge	189:f392fc9709a3	5352	}
AnnaBridge	189:f392fc9709a3	5353	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	189:f392fc9709a3	5354
AnnaBridge	189:f392fc9709a3	5355	/**
AnnaBridge	189:f392fc9709a3	5356	* @brief Clear Clock security system interrupt flag
AnnaBridge	189:f392fc9709a3	5357	* @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
AnnaBridge	189:f392fc9709a3	5358	* @retval None
AnnaBridge	189:f392fc9709a3	5359	*/
AnnaBridge	189:f392fc9709a3	5360	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
AnnaBridge	189:f392fc9709a3	5361	{
AnnaBridge	189:f392fc9709a3	5362	SET_BIT(RCC->CICR, RCC_CICR_CSSC);
AnnaBridge	189:f392fc9709a3	5363	}
AnnaBridge	189:f392fc9709a3	5364
AnnaBridge	189:f392fc9709a3	5365	/**
AnnaBridge	189:f392fc9709a3	5366	* @brief Clear LSE Clock security system interrupt flag
AnnaBridge	189:f392fc9709a3	5367	* @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
AnnaBridge	189:f392fc9709a3	5368	* @retval None
AnnaBridge	189:f392fc9709a3	5369	*/
AnnaBridge	189:f392fc9709a3	5370	__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
AnnaBridge	189:f392fc9709a3	5371	{
AnnaBridge	189:f392fc9709a3	5372	SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
AnnaBridge	189:f392fc9709a3	5373	}
AnnaBridge	189:f392fc9709a3	5374
AnnaBridge	189:f392fc9709a3	5375	/**
AnnaBridge	189:f392fc9709a3	5376	* @brief Check if LSI ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	5377	* @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
AnnaBridge	189:f392fc9709a3	5378	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5379	*/
AnnaBridge	189:f392fc9709a3	5380	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
AnnaBridge	189:f392fc9709a3	5381	{
AnnaBridge	189:f392fc9709a3	5382	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF));
AnnaBridge	189:f392fc9709a3	5383	}
AnnaBridge	189:f392fc9709a3	5384
AnnaBridge	189:f392fc9709a3	5385	/**
AnnaBridge	189:f392fc9709a3	5386	* @brief Check if LSE ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	5387	* @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
AnnaBridge	189:f392fc9709a3	5388	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5389	*/
AnnaBridge	189:f392fc9709a3	5390	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
AnnaBridge	189:f392fc9709a3	5391	{
AnnaBridge	189:f392fc9709a3	5392	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF));
AnnaBridge	189:f392fc9709a3	5393	}
AnnaBridge	189:f392fc9709a3	5394
AnnaBridge	189:f392fc9709a3	5395	/**
AnnaBridge	189:f392fc9709a3	5396	* @brief Check if MSI ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	5397	* @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
AnnaBridge	189:f392fc9709a3	5398	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5399	*/
AnnaBridge	189:f392fc9709a3	5400	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
AnnaBridge	189:f392fc9709a3	5401	{
AnnaBridge	189:f392fc9709a3	5402	return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF));
AnnaBridge	189:f392fc9709a3	5403	}
AnnaBridge	189:f392fc9709a3	5404
AnnaBridge	189:f392fc9709a3	5405	/**
AnnaBridge	189:f392fc9709a3	5406	* @brief Check if HSI ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	5407	* @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
AnnaBridge	189:f392fc9709a3	5408	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5409	*/
AnnaBridge	189:f392fc9709a3	5410	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
AnnaBridge	189:f392fc9709a3	5411	{
AnnaBridge	189:f392fc9709a3	5412	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF));
AnnaBridge	189:f392fc9709a3	5413	}
AnnaBridge	189:f392fc9709a3	5414
AnnaBridge	189:f392fc9709a3	5415	/**
AnnaBridge	189:f392fc9709a3	5416	* @brief Check if HSE ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	5417	* @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
AnnaBridge	189:f392fc9709a3	5418	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5419	*/
AnnaBridge	189:f392fc9709a3	5420	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
AnnaBridge	189:f392fc9709a3	5421	{
AnnaBridge	189:f392fc9709a3	5422	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF));
AnnaBridge	189:f392fc9709a3	5423	}
AnnaBridge	189:f392fc9709a3	5424
AnnaBridge	189:f392fc9709a3	5425	/**
AnnaBridge	189:f392fc9709a3	5426	* @brief Check if PLL ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	5427	* @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
AnnaBridge	189:f392fc9709a3	5428	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5429	*/
AnnaBridge	189:f392fc9709a3	5430	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
AnnaBridge	189:f392fc9709a3	5431	{
AnnaBridge	189:f392fc9709a3	5432	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF));
AnnaBridge	189:f392fc9709a3	5433	}
AnnaBridge	189:f392fc9709a3	5434
AnnaBridge	189:f392fc9709a3	5435	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	5436	/**
AnnaBridge	189:f392fc9709a3	5437	* @brief Check if HSI48 ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	5438	* @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
AnnaBridge	189:f392fc9709a3	5439	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5440	*/
AnnaBridge	189:f392fc9709a3	5441	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
AnnaBridge	189:f392fc9709a3	5442	{
AnnaBridge	189:f392fc9709a3	5443	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF));
AnnaBridge	189:f392fc9709a3	5444	}
AnnaBridge	189:f392fc9709a3	5445	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	5446
AnnaBridge	189:f392fc9709a3	5447	/**
AnnaBridge	189:f392fc9709a3	5448	* @brief Check if PLLSAI1 ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	5449	* @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
AnnaBridge	189:f392fc9709a3	5450	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5451	*/
AnnaBridge	189:f392fc9709a3	5452	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
AnnaBridge	189:f392fc9709a3	5453	{
AnnaBridge	189:f392fc9709a3	5454	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF));
AnnaBridge	189:f392fc9709a3	5455	}
AnnaBridge	189:f392fc9709a3	5456
AnnaBridge	189:f392fc9709a3	5457	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	189:f392fc9709a3	5458	/**
AnnaBridge	189:f392fc9709a3	5459	* @brief Check if PLLSAI1 ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	5460	* @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY
AnnaBridge	189:f392fc9709a3	5461	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5462	*/
AnnaBridge	189:f392fc9709a3	5463	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
AnnaBridge	189:f392fc9709a3	5464	{
AnnaBridge	189:f392fc9709a3	5465	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF));
AnnaBridge	189:f392fc9709a3	5466	}
AnnaBridge	189:f392fc9709a3	5467	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	189:f392fc9709a3	5468
AnnaBridge	189:f392fc9709a3	5469	/**
AnnaBridge	189:f392fc9709a3	5470	* @brief Check if Clock security system interrupt occurred or not
AnnaBridge	189:f392fc9709a3	5471	* @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
AnnaBridge	189:f392fc9709a3	5472	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5473	*/
AnnaBridge	189:f392fc9709a3	5474	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
AnnaBridge	189:f392fc9709a3	5475	{
AnnaBridge	189:f392fc9709a3	5476	return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF));
AnnaBridge	189:f392fc9709a3	5477	}
AnnaBridge	189:f392fc9709a3	5478
AnnaBridge	189:f392fc9709a3	5479	/**
AnnaBridge	189:f392fc9709a3	5480	* @brief Check if LSE Clock security system interrupt occurred or not
AnnaBridge	189:f392fc9709a3	5481	* @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
AnnaBridge	189:f392fc9709a3	5482	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5483	*/
AnnaBridge	189:f392fc9709a3	5484	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
AnnaBridge	189:f392fc9709a3	5485	{
AnnaBridge	189:f392fc9709a3	5486	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF));
AnnaBridge	189:f392fc9709a3	5487	}
AnnaBridge	189:f392fc9709a3	5488
AnnaBridge	189:f392fc9709a3	5489	/**
AnnaBridge	189:f392fc9709a3	5490	* @brief Check if RCC flag FW reset is set or not.
AnnaBridge	189:f392fc9709a3	5491	* @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST
AnnaBridge	189:f392fc9709a3	5492	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5493	*/
AnnaBridge	189:f392fc9709a3	5494	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
AnnaBridge	189:f392fc9709a3	5495	{
AnnaBridge	189:f392fc9709a3	5496	return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF));
AnnaBridge	189:f392fc9709a3	5497	}
AnnaBridge	189:f392fc9709a3	5498
AnnaBridge	189:f392fc9709a3	5499	/**
AnnaBridge	189:f392fc9709a3	5500	* @brief Check if RCC flag Independent Watchdog reset is set or not.
AnnaBridge	189:f392fc9709a3	5501	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
AnnaBridge	189:f392fc9709a3	5502	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5503	*/
AnnaBridge	189:f392fc9709a3	5504	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
AnnaBridge	189:f392fc9709a3	5505	{
AnnaBridge	189:f392fc9709a3	5506	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
AnnaBridge	189:f392fc9709a3	5507	}
AnnaBridge	189:f392fc9709a3	5508
AnnaBridge	189:f392fc9709a3	5509	/**
AnnaBridge	189:f392fc9709a3	5510	* @brief Check if RCC flag Low Power reset is set or not.
AnnaBridge	189:f392fc9709a3	5511	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
AnnaBridge	189:f392fc9709a3	5512	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5513	*/
AnnaBridge	189:f392fc9709a3	5514	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
AnnaBridge	189:f392fc9709a3	5515	{
AnnaBridge	189:f392fc9709a3	5516	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
AnnaBridge	189:f392fc9709a3	5517	}
AnnaBridge	189:f392fc9709a3	5518
AnnaBridge	189:f392fc9709a3	5519	/**
AnnaBridge	189:f392fc9709a3	5520	* @brief Check if RCC flag is set or not.
AnnaBridge	189:f392fc9709a3	5521	* @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
AnnaBridge	189:f392fc9709a3	5522	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5523	*/
AnnaBridge	189:f392fc9709a3	5524	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
AnnaBridge	189:f392fc9709a3	5525	{
AnnaBridge	189:f392fc9709a3	5526	return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
AnnaBridge	189:f392fc9709a3	5527	}
AnnaBridge	189:f392fc9709a3	5528
AnnaBridge	189:f392fc9709a3	5529	/**
AnnaBridge	189:f392fc9709a3	5530	* @brief Check if RCC flag Pin reset is set or not.
AnnaBridge	189:f392fc9709a3	5531	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
AnnaBridge	189:f392fc9709a3	5532	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5533	*/
AnnaBridge	189:f392fc9709a3	5534	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
AnnaBridge	189:f392fc9709a3	5535	{
AnnaBridge	189:f392fc9709a3	5536	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
AnnaBridge	189:f392fc9709a3	5537	}
AnnaBridge	189:f392fc9709a3	5538
AnnaBridge	189:f392fc9709a3	5539	/**
AnnaBridge	189:f392fc9709a3	5540	* @brief Check if RCC flag Software reset is set or not.
AnnaBridge	189:f392fc9709a3	5541	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
AnnaBridge	189:f392fc9709a3	5542	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5543	*/
AnnaBridge	189:f392fc9709a3	5544	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
AnnaBridge	189:f392fc9709a3	5545	{
AnnaBridge	189:f392fc9709a3	5546	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
AnnaBridge	189:f392fc9709a3	5547	}
AnnaBridge	189:f392fc9709a3	5548
AnnaBridge	189:f392fc9709a3	5549	/**
AnnaBridge	189:f392fc9709a3	5550	* @brief Check if RCC flag Window Watchdog reset is set or not.
AnnaBridge	189:f392fc9709a3	5551	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
AnnaBridge	189:f392fc9709a3	5552	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5553	*/
AnnaBridge	189:f392fc9709a3	5554	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
AnnaBridge	189:f392fc9709a3	5555	{
AnnaBridge	189:f392fc9709a3	5556	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
AnnaBridge	189:f392fc9709a3	5557	}
AnnaBridge	189:f392fc9709a3	5558
AnnaBridge	189:f392fc9709a3	5559	/**
AnnaBridge	189:f392fc9709a3	5560	* @brief Check if RCC flag BOR reset is set or not.
AnnaBridge	189:f392fc9709a3	5561	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
AnnaBridge	189:f392fc9709a3	5562	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5563	*/
AnnaBridge	189:f392fc9709a3	5564	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
AnnaBridge	189:f392fc9709a3	5565	{
AnnaBridge	189:f392fc9709a3	5566	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
AnnaBridge	189:f392fc9709a3	5567	}
AnnaBridge	189:f392fc9709a3	5568
AnnaBridge	189:f392fc9709a3	5569	/**
AnnaBridge	189:f392fc9709a3	5570	* @brief Set RMVF bit to clear the reset flags.
AnnaBridge	189:f392fc9709a3	5571	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
AnnaBridge	189:f392fc9709a3	5572	* @retval None
AnnaBridge	189:f392fc9709a3	5573	*/
AnnaBridge	189:f392fc9709a3	5574	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
AnnaBridge	189:f392fc9709a3	5575	{
AnnaBridge	189:f392fc9709a3	5576	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
AnnaBridge	189:f392fc9709a3	5577	}
AnnaBridge	189:f392fc9709a3	5578
AnnaBridge	189:f392fc9709a3	5579	/**
AnnaBridge	189:f392fc9709a3	5580	* @}
AnnaBridge	189:f392fc9709a3	5581	*/
AnnaBridge	189:f392fc9709a3	5582
AnnaBridge	189:f392fc9709a3	5583	/** @defgroup RCC_LL_EF_IT_Management IT Management
AnnaBridge	189:f392fc9709a3	5584	* @{
AnnaBridge	189:f392fc9709a3	5585	*/
AnnaBridge	189:f392fc9709a3	5586
AnnaBridge	189:f392fc9709a3	5587	/**
AnnaBridge	189:f392fc9709a3	5588	* @brief Enable LSI ready interrupt
AnnaBridge	189:f392fc9709a3	5589	* @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
AnnaBridge	189:f392fc9709a3	5590	* @retval None
AnnaBridge	189:f392fc9709a3	5591	*/
AnnaBridge	189:f392fc9709a3	5592	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
AnnaBridge	189:f392fc9709a3	5593	{
AnnaBridge	189:f392fc9709a3	5594	SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
AnnaBridge	189:f392fc9709a3	5595	}
AnnaBridge	189:f392fc9709a3	5596
AnnaBridge	189:f392fc9709a3	5597	/**
AnnaBridge	189:f392fc9709a3	5598	* @brief Enable LSE ready interrupt
AnnaBridge	189:f392fc9709a3	5599	* @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
AnnaBridge	189:f392fc9709a3	5600	* @retval None
AnnaBridge	189:f392fc9709a3	5601	*/
AnnaBridge	189:f392fc9709a3	5602	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
AnnaBridge	189:f392fc9709a3	5603	{
AnnaBridge	189:f392fc9709a3	5604	SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
AnnaBridge	189:f392fc9709a3	5605	}
AnnaBridge	189:f392fc9709a3	5606
AnnaBridge	189:f392fc9709a3	5607	/**
AnnaBridge	189:f392fc9709a3	5608	* @brief Enable MSI ready interrupt
AnnaBridge	189:f392fc9709a3	5609	* @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
AnnaBridge	189:f392fc9709a3	5610	* @retval None
AnnaBridge	189:f392fc9709a3	5611	*/
AnnaBridge	189:f392fc9709a3	5612	__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
AnnaBridge	189:f392fc9709a3	5613	{
AnnaBridge	189:f392fc9709a3	5614	SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
AnnaBridge	189:f392fc9709a3	5615	}
AnnaBridge	189:f392fc9709a3	5616
AnnaBridge	189:f392fc9709a3	5617	/**
AnnaBridge	189:f392fc9709a3	5618	* @brief Enable HSI ready interrupt
AnnaBridge	189:f392fc9709a3	5619	* @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
AnnaBridge	189:f392fc9709a3	5620	* @retval None
AnnaBridge	189:f392fc9709a3	5621	*/
AnnaBridge	189:f392fc9709a3	5622	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
AnnaBridge	189:f392fc9709a3	5623	{
AnnaBridge	189:f392fc9709a3	5624	SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
AnnaBridge	189:f392fc9709a3	5625	}
AnnaBridge	189:f392fc9709a3	5626
AnnaBridge	189:f392fc9709a3	5627	/**
AnnaBridge	189:f392fc9709a3	5628	* @brief Enable HSE ready interrupt
AnnaBridge	189:f392fc9709a3	5629	* @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
AnnaBridge	189:f392fc9709a3	5630	* @retval None
AnnaBridge	189:f392fc9709a3	5631	*/
AnnaBridge	189:f392fc9709a3	5632	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
AnnaBridge	189:f392fc9709a3	5633	{
AnnaBridge	189:f392fc9709a3	5634	SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
AnnaBridge	189:f392fc9709a3	5635	}
AnnaBridge	189:f392fc9709a3	5636
AnnaBridge	189:f392fc9709a3	5637	/**
AnnaBridge	189:f392fc9709a3	5638	* @brief Enable PLL ready interrupt
AnnaBridge	189:f392fc9709a3	5639	* @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
AnnaBridge	189:f392fc9709a3	5640	* @retval None
AnnaBridge	189:f392fc9709a3	5641	*/
AnnaBridge	189:f392fc9709a3	5642	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
AnnaBridge	189:f392fc9709a3	5643	{
AnnaBridge	189:f392fc9709a3	5644	SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
AnnaBridge	189:f392fc9709a3	5645	}
AnnaBridge	189:f392fc9709a3	5646
AnnaBridge	189:f392fc9709a3	5647	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	5648	/**
AnnaBridge	189:f392fc9709a3	5649	* @brief Enable HSI48 ready interrupt
AnnaBridge	189:f392fc9709a3	5650	* @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
AnnaBridge	189:f392fc9709a3	5651	* @retval None
AnnaBridge	189:f392fc9709a3	5652	*/
AnnaBridge	189:f392fc9709a3	5653	__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
AnnaBridge	189:f392fc9709a3	5654	{
AnnaBridge	189:f392fc9709a3	5655	SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
AnnaBridge	189:f392fc9709a3	5656	}
AnnaBridge	189:f392fc9709a3	5657	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	5658
AnnaBridge	189:f392fc9709a3	5659	/**
AnnaBridge	189:f392fc9709a3	5660	* @brief Enable PLLSAI1 ready interrupt
AnnaBridge	189:f392fc9709a3	5661	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
AnnaBridge	189:f392fc9709a3	5662	* @retval None
AnnaBridge	189:f392fc9709a3	5663	*/
AnnaBridge	189:f392fc9709a3	5664	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
AnnaBridge	189:f392fc9709a3	5665	{
AnnaBridge	189:f392fc9709a3	5666	SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
AnnaBridge	189:f392fc9709a3	5667	}
AnnaBridge	189:f392fc9709a3	5668
AnnaBridge	189:f392fc9709a3	5669	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	189:f392fc9709a3	5670	/**
AnnaBridge	189:f392fc9709a3	5671	* @brief Enable PLLSAI2 ready interrupt
AnnaBridge	189:f392fc9709a3	5672	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY
AnnaBridge	189:f392fc9709a3	5673	* @retval None
AnnaBridge	189:f392fc9709a3	5674	*/
AnnaBridge	189:f392fc9709a3	5675	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
AnnaBridge	189:f392fc9709a3	5676	{
AnnaBridge	189:f392fc9709a3	5677	SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
AnnaBridge	189:f392fc9709a3	5678	}
AnnaBridge	189:f392fc9709a3	5679	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	189:f392fc9709a3	5680
AnnaBridge	189:f392fc9709a3	5681	/**
AnnaBridge	189:f392fc9709a3	5682	* @brief Enable LSE clock security system interrupt
AnnaBridge	189:f392fc9709a3	5683	* @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
AnnaBridge	189:f392fc9709a3	5684	* @retval None
AnnaBridge	189:f392fc9709a3	5685	*/
AnnaBridge	189:f392fc9709a3	5686	__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
AnnaBridge	189:f392fc9709a3	5687	{
AnnaBridge	189:f392fc9709a3	5688	SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
AnnaBridge	189:f392fc9709a3	5689	}
AnnaBridge	189:f392fc9709a3	5690
AnnaBridge	189:f392fc9709a3	5691	/**
AnnaBridge	189:f392fc9709a3	5692	* @brief Disable LSI ready interrupt
AnnaBridge	189:f392fc9709a3	5693	* @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
AnnaBridge	189:f392fc9709a3	5694	* @retval None
AnnaBridge	189:f392fc9709a3	5695	*/
AnnaBridge	189:f392fc9709a3	5696	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
AnnaBridge	189:f392fc9709a3	5697	{
AnnaBridge	189:f392fc9709a3	5698	CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
AnnaBridge	189:f392fc9709a3	5699	}
AnnaBridge	189:f392fc9709a3	5700
AnnaBridge	189:f392fc9709a3	5701	/**
AnnaBridge	189:f392fc9709a3	5702	* @brief Disable LSE ready interrupt
AnnaBridge	189:f392fc9709a3	5703	* @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
AnnaBridge	189:f392fc9709a3	5704	* @retval None
AnnaBridge	189:f392fc9709a3	5705	*/
AnnaBridge	189:f392fc9709a3	5706	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
AnnaBridge	189:f392fc9709a3	5707	{
AnnaBridge	189:f392fc9709a3	5708	CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
AnnaBridge	189:f392fc9709a3	5709	}
AnnaBridge	189:f392fc9709a3	5710
AnnaBridge	189:f392fc9709a3	5711	/**
AnnaBridge	189:f392fc9709a3	5712	* @brief Disable MSI ready interrupt
AnnaBridge	189:f392fc9709a3	5713	* @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
AnnaBridge	189:f392fc9709a3	5714	* @retval None
AnnaBridge	189:f392fc9709a3	5715	*/
AnnaBridge	189:f392fc9709a3	5716	__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
AnnaBridge	189:f392fc9709a3	5717	{
AnnaBridge	189:f392fc9709a3	5718	CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
AnnaBridge	189:f392fc9709a3	5719	}
AnnaBridge	189:f392fc9709a3	5720
AnnaBridge	189:f392fc9709a3	5721	/**
AnnaBridge	189:f392fc9709a3	5722	* @brief Disable HSI ready interrupt
AnnaBridge	189:f392fc9709a3	5723	* @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
AnnaBridge	189:f392fc9709a3	5724	* @retval None
AnnaBridge	189:f392fc9709a3	5725	*/
AnnaBridge	189:f392fc9709a3	5726	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
AnnaBridge	189:f392fc9709a3	5727	{
AnnaBridge	189:f392fc9709a3	5728	CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
AnnaBridge	189:f392fc9709a3	5729	}
AnnaBridge	189:f392fc9709a3	5730
AnnaBridge	189:f392fc9709a3	5731	/**
AnnaBridge	189:f392fc9709a3	5732	* @brief Disable HSE ready interrupt
AnnaBridge	189:f392fc9709a3	5733	* @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
AnnaBridge	189:f392fc9709a3	5734	* @retval None
AnnaBridge	189:f392fc9709a3	5735	*/
AnnaBridge	189:f392fc9709a3	5736	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
AnnaBridge	189:f392fc9709a3	5737	{
AnnaBridge	189:f392fc9709a3	5738	CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
AnnaBridge	189:f392fc9709a3	5739	}
AnnaBridge	189:f392fc9709a3	5740
AnnaBridge	189:f392fc9709a3	5741	/**
AnnaBridge	189:f392fc9709a3	5742	* @brief Disable PLL ready interrupt
AnnaBridge	189:f392fc9709a3	5743	* @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
AnnaBridge	189:f392fc9709a3	5744	* @retval None
AnnaBridge	189:f392fc9709a3	5745	*/
AnnaBridge	189:f392fc9709a3	5746	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
AnnaBridge	189:f392fc9709a3	5747	{
AnnaBridge	189:f392fc9709a3	5748	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
AnnaBridge	189:f392fc9709a3	5749	}
AnnaBridge	189:f392fc9709a3	5750
AnnaBridge	189:f392fc9709a3	5751	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	5752	/**
AnnaBridge	189:f392fc9709a3	5753	* @brief Disable HSI48 ready interrupt
AnnaBridge	189:f392fc9709a3	5754	* @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
AnnaBridge	189:f392fc9709a3	5755	* @retval None
AnnaBridge	189:f392fc9709a3	5756	*/
AnnaBridge	189:f392fc9709a3	5757	__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
AnnaBridge	189:f392fc9709a3	5758	{
AnnaBridge	189:f392fc9709a3	5759	CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
AnnaBridge	189:f392fc9709a3	5760	}
AnnaBridge	189:f392fc9709a3	5761	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	5762
AnnaBridge	189:f392fc9709a3	5763	/**
AnnaBridge	189:f392fc9709a3	5764	* @brief Disable PLLSAI1 ready interrupt
AnnaBridge	189:f392fc9709a3	5765	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
AnnaBridge	189:f392fc9709a3	5766	* @retval None
AnnaBridge	189:f392fc9709a3	5767	*/
AnnaBridge	189:f392fc9709a3	5768	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
AnnaBridge	189:f392fc9709a3	5769	{
AnnaBridge	189:f392fc9709a3	5770	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
AnnaBridge	189:f392fc9709a3	5771	}
AnnaBridge	189:f392fc9709a3	5772
AnnaBridge	189:f392fc9709a3	5773	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	189:f392fc9709a3	5774	/**
AnnaBridge	189:f392fc9709a3	5775	* @brief Disable PLLSAI2 ready interrupt
AnnaBridge	189:f392fc9709a3	5776	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY
AnnaBridge	189:f392fc9709a3	5777	* @retval None
AnnaBridge	189:f392fc9709a3	5778	*/
AnnaBridge	189:f392fc9709a3	5779	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
AnnaBridge	189:f392fc9709a3	5780	{
AnnaBridge	189:f392fc9709a3	5781	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
AnnaBridge	189:f392fc9709a3	5782	}
AnnaBridge	189:f392fc9709a3	5783	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	189:f392fc9709a3	5784
AnnaBridge	189:f392fc9709a3	5785	/**
AnnaBridge	189:f392fc9709a3	5786	* @brief Disable LSE clock security system interrupt
AnnaBridge	189:f392fc9709a3	5787	* @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
AnnaBridge	189:f392fc9709a3	5788	* @retval None
AnnaBridge	189:f392fc9709a3	5789	*/
AnnaBridge	189:f392fc9709a3	5790	__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
AnnaBridge	189:f392fc9709a3	5791	{
AnnaBridge	189:f392fc9709a3	5792	CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
AnnaBridge	189:f392fc9709a3	5793	}
AnnaBridge	189:f392fc9709a3	5794
AnnaBridge	189:f392fc9709a3	5795	/**
AnnaBridge	189:f392fc9709a3	5796	* @brief Checks if LSI ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	5797	* @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
AnnaBridge	189:f392fc9709a3	5798	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5799	*/
AnnaBridge	189:f392fc9709a3	5800	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
AnnaBridge	189:f392fc9709a3	5801	{
AnnaBridge	189:f392fc9709a3	5802	return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE));
AnnaBridge	189:f392fc9709a3	5803	}
AnnaBridge	189:f392fc9709a3	5804
AnnaBridge	189:f392fc9709a3	5805	/**
AnnaBridge	189:f392fc9709a3	5806	* @brief Checks if LSE ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	5807	* @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
AnnaBridge	189:f392fc9709a3	5808	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5809	*/
AnnaBridge	189:f392fc9709a3	5810	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
AnnaBridge	189:f392fc9709a3	5811	{
AnnaBridge	189:f392fc9709a3	5812	return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE));
AnnaBridge	189:f392fc9709a3	5813	}
AnnaBridge	189:f392fc9709a3	5814
AnnaBridge	189:f392fc9709a3	5815	/**
AnnaBridge	189:f392fc9709a3	5816	* @brief Checks if MSI ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	5817	* @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
AnnaBridge	189:f392fc9709a3	5818	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5819	*/
AnnaBridge	189:f392fc9709a3	5820	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
AnnaBridge	189:f392fc9709a3	5821	{
AnnaBridge	189:f392fc9709a3	5822	return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE));
AnnaBridge	189:f392fc9709a3	5823	}
AnnaBridge	189:f392fc9709a3	5824
AnnaBridge	189:f392fc9709a3	5825	/**
AnnaBridge	189:f392fc9709a3	5826	* @brief Checks if HSI ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	5827	* @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
AnnaBridge	189:f392fc9709a3	5828	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5829	*/
AnnaBridge	189:f392fc9709a3	5830	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
AnnaBridge	189:f392fc9709a3	5831	{
AnnaBridge	189:f392fc9709a3	5832	return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE));
AnnaBridge	189:f392fc9709a3	5833	}
AnnaBridge	189:f392fc9709a3	5834
AnnaBridge	189:f392fc9709a3	5835	/**
AnnaBridge	189:f392fc9709a3	5836	* @brief Checks if HSE ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	5837	* @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
AnnaBridge	189:f392fc9709a3	5838	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5839	*/
AnnaBridge	189:f392fc9709a3	5840	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
AnnaBridge	189:f392fc9709a3	5841	{
AnnaBridge	189:f392fc9709a3	5842	return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE));
AnnaBridge	189:f392fc9709a3	5843	}
AnnaBridge	189:f392fc9709a3	5844
AnnaBridge	189:f392fc9709a3	5845	/**
AnnaBridge	189:f392fc9709a3	5846	* @brief Checks if PLL ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	5847	* @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
AnnaBridge	189:f392fc9709a3	5848	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5849	*/
AnnaBridge	189:f392fc9709a3	5850	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
AnnaBridge	189:f392fc9709a3	5851	{
AnnaBridge	189:f392fc9709a3	5852	return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE));
AnnaBridge	189:f392fc9709a3	5853	}
AnnaBridge	189:f392fc9709a3	5854
AnnaBridge	189:f392fc9709a3	5855	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	5856	/**
AnnaBridge	189:f392fc9709a3	5857	* @brief Checks if HSI48 ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	5858	* @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
AnnaBridge	189:f392fc9709a3	5859	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5860	*/
AnnaBridge	189:f392fc9709a3	5861	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
AnnaBridge	189:f392fc9709a3	5862	{
AnnaBridge	189:f392fc9709a3	5863	return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE));
AnnaBridge	189:f392fc9709a3	5864	}
AnnaBridge	189:f392fc9709a3	5865	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	5866
AnnaBridge	189:f392fc9709a3	5867	/**
AnnaBridge	189:f392fc9709a3	5868	* @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	5869	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
AnnaBridge	189:f392fc9709a3	5870	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5871	*/
AnnaBridge	189:f392fc9709a3	5872	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
AnnaBridge	189:f392fc9709a3	5873	{
AnnaBridge	189:f392fc9709a3	5874	return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE));
AnnaBridge	189:f392fc9709a3	5875	}
AnnaBridge	189:f392fc9709a3	5876
AnnaBridge	189:f392fc9709a3	5877	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	189:f392fc9709a3	5878	/**
AnnaBridge	189:f392fc9709a3	5879	* @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	5880	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY
AnnaBridge	189:f392fc9709a3	5881	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5882	*/
AnnaBridge	189:f392fc9709a3	5883	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
AnnaBridge	189:f392fc9709a3	5884	{
AnnaBridge	189:f392fc9709a3	5885	return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE));
AnnaBridge	189:f392fc9709a3	5886	}
AnnaBridge	189:f392fc9709a3	5887	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	189:f392fc9709a3	5888
AnnaBridge	189:f392fc9709a3	5889	/**
AnnaBridge	189:f392fc9709a3	5890	* @brief Checks if LSECSS interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	5891	* @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
AnnaBridge	189:f392fc9709a3	5892	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	5893	*/
AnnaBridge	189:f392fc9709a3	5894	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
AnnaBridge	189:f392fc9709a3	5895	{
AnnaBridge	189:f392fc9709a3	5896	return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE));
AnnaBridge	189:f392fc9709a3	5897	}
AnnaBridge	189:f392fc9709a3	5898
AnnaBridge	189:f392fc9709a3	5899	/**
AnnaBridge	189:f392fc9709a3	5900	* @}
AnnaBridge	189:f392fc9709a3	5901	*/
AnnaBridge	189:f392fc9709a3	5902
AnnaBridge	189:f392fc9709a3	5903	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	5904	/** @defgroup RCC_LL_EF_Init De-initialization function
AnnaBridge	189:f392fc9709a3	5905	* @{
AnnaBridge	189:f392fc9709a3	5906	*/
AnnaBridge	189:f392fc9709a3	5907	ErrorStatus LL_RCC_DeInit(void);
AnnaBridge	189:f392fc9709a3	5908	/**
AnnaBridge	189:f392fc9709a3	5909	* @}
AnnaBridge	189:f392fc9709a3	5910	*/
AnnaBridge	189:f392fc9709a3	5911
AnnaBridge	189:f392fc9709a3	5912	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
AnnaBridge	189:f392fc9709a3	5913	* @{
AnnaBridge	189:f392fc9709a3	5914	*/
AnnaBridge	189:f392fc9709a3	5915	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
AnnaBridge	189:f392fc9709a3	5916	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
AnnaBridge	189:f392fc9709a3	5917	#if defined(UART4) \|\| defined(UART5)
AnnaBridge	189:f392fc9709a3	5918	uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
AnnaBridge	189:f392fc9709a3	5919	#endif /* UART4 \|\| UART5 */
AnnaBridge	189:f392fc9709a3	5920	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
AnnaBridge	189:f392fc9709a3	5921	uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
AnnaBridge	189:f392fc9709a3	5922	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
AnnaBridge	189:f392fc9709a3	5923	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
AnnaBridge	189:f392fc9709a3	5924	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	189:f392fc9709a3	5925	uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource);
AnnaBridge	189:f392fc9709a3	5926	#endif
AnnaBridge	189:f392fc9709a3	5927	uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
AnnaBridge	189:f392fc9709a3	5928	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
AnnaBridge	189:f392fc9709a3	5929	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	189:f392fc9709a3	5930	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
AnnaBridge	189:f392fc9709a3	5931	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	189:f392fc9709a3	5932	uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
AnnaBridge	189:f392fc9709a3	5933	#if defined(SWPMI1)
AnnaBridge	189:f392fc9709a3	5934	uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource);
AnnaBridge	189:f392fc9709a3	5935	#endif /* SWPMI1 */
AnnaBridge	189:f392fc9709a3	5936	#if defined(DFSDM1_Channel0)
AnnaBridge	189:f392fc9709a3	5937	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
AnnaBridge	189:f392fc9709a3	5938	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	189:f392fc9709a3	5939	uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
AnnaBridge	189:f392fc9709a3	5940	#endif /* RCC_CCIPR2_DFSDM1SEL */
AnnaBridge	189:f392fc9709a3	5941	#endif /* DFSDM1_Channel0 */
AnnaBridge	189:f392fc9709a3	5942	#if defined(LTDC)
AnnaBridge	189:f392fc9709a3	5943	uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
AnnaBridge	189:f392fc9709a3	5944	#endif /* LTDC */
AnnaBridge	189:f392fc9709a3	5945	#if defined(DSI)
AnnaBridge	189:f392fc9709a3	5946	uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
AnnaBridge	189:f392fc9709a3	5947	#endif /* DSI */
AnnaBridge	189:f392fc9709a3	5948	#if defined(OCTOSPI1)
AnnaBridge	189:f392fc9709a3	5949	uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);
AnnaBridge	189:f392fc9709a3	5950	#endif /* OCTOSPI1 */
AnnaBridge	189:f392fc9709a3	5951	/**
AnnaBridge	189:f392fc9709a3	5952	* @}
AnnaBridge	189:f392fc9709a3	5953	*/
AnnaBridge	189:f392fc9709a3	5954	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	5955
AnnaBridge	189:f392fc9709a3	5956	/**
AnnaBridge	189:f392fc9709a3	5957	* @}
AnnaBridge	189:f392fc9709a3	5958	*/
AnnaBridge	189:f392fc9709a3	5959
AnnaBridge	189:f392fc9709a3	5960	/**
AnnaBridge	189:f392fc9709a3	5961	* @}
AnnaBridge	189:f392fc9709a3	5962	*/
AnnaBridge	189:f392fc9709a3	5963
AnnaBridge	189:f392fc9709a3	5964	#endif /* defined(RCC) */
AnnaBridge	189:f392fc9709a3	5965
AnnaBridge	189:f392fc9709a3	5966	/**
AnnaBridge	189:f392fc9709a3	5967	* @}
AnnaBridge	189:f392fc9709a3	5968	*/
AnnaBridge	189:f392fc9709a3	5969
AnnaBridge	189:f392fc9709a3	5970	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	5971	}
AnnaBridge	189:f392fc9709a3	5972	#endif
AnnaBridge	189:f392fc9709a3	5973
AnnaBridge	189:f392fc9709a3	5974	#endif /* __STM32L4xx_LL_RCC_H */
AnnaBridge	189:f392fc9709a3	5975
AnnaBridge	189:f392fc9709a3	5976	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/