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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_ll_fmc.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_ll_fmc.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of FMC HAL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_LL_FMC_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_LL_FMC_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | #if defined(FMC_BANK1) |
| AnnaBridge | 189:f392fc9709a3 | 52 | |
| AnnaBridge | 189:f392fc9709a3 | 53 | /** @addtogroup FMC_LL |
| AnnaBridge | 189:f392fc9709a3 | 54 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 55 | */ |
| AnnaBridge | 189:f392fc9709a3 | 56 | |
| AnnaBridge | 189:f392fc9709a3 | 57 | /** @addtogroup FMC_LL_Private_Macros |
| AnnaBridge | 189:f392fc9709a3 | 58 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 59 | */ |
| AnnaBridge | 189:f392fc9709a3 | 60 | |
| AnnaBridge | 189:f392fc9709a3 | 61 | #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 62 | ((__BANK__) == FMC_NORSRAM_BANK2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 63 | ((__BANK__) == FMC_NORSRAM_BANK3) || \ |
| AnnaBridge | 189:f392fc9709a3 | 64 | ((__BANK__) == FMC_NORSRAM_BANK4)) |
| AnnaBridge | 189:f392fc9709a3 | 65 | |
| AnnaBridge | 189:f392fc9709a3 | 66 | #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 67 | ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 68 | |
| AnnaBridge | 189:f392fc9709a3 | 69 | #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ |
| AnnaBridge | 189:f392fc9709a3 | 70 | ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ |
| AnnaBridge | 189:f392fc9709a3 | 71 | ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) |
| AnnaBridge | 189:f392fc9709a3 | 72 | |
| AnnaBridge | 189:f392fc9709a3 | 73 | #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 74 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
| AnnaBridge | 189:f392fc9709a3 | 75 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) |
| AnnaBridge | 189:f392fc9709a3 | 76 | |
| AnnaBridge | 189:f392fc9709a3 | 77 | #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 78 | ((__BURST__) == FMC_WRITE_BURST_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 79 | |
| AnnaBridge | 189:f392fc9709a3 | 80 | #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 81 | ((__SIZE__) == FMC_PAGE_SIZE_128) || \ |
| AnnaBridge | 189:f392fc9709a3 | 82 | ((__SIZE__) == FMC_PAGE_SIZE_256) || \ |
| AnnaBridge | 189:f392fc9709a3 | 83 | ((__SIZE__) == FMC_PAGE_SIZE_512) || \ |
| AnnaBridge | 189:f392fc9709a3 | 84 | ((__SIZE__) == FMC_PAGE_SIZE_1024)) |
| AnnaBridge | 189:f392fc9709a3 | 85 | |
| AnnaBridge | 189:f392fc9709a3 | 86 | #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
| AnnaBridge | 189:f392fc9709a3 | 87 | ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
| AnnaBridge | 189:f392fc9709a3 | 88 | |
| AnnaBridge | 189:f392fc9709a3 | 89 | #if defined(FMC_BCR1_WFDIS) |
| AnnaBridge | 189:f392fc9709a3 | 90 | #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 91 | ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 92 | #endif /* FMC_BCR1_WFDIS */ |
| AnnaBridge | 189:f392fc9709a3 | 93 | |
| AnnaBridge | 189:f392fc9709a3 | 94 | #if defined(FMC_BCRx_NBLSET) |
| AnnaBridge | 189:f392fc9709a3 | 95 | #define IS_FMC_NBLSETUP_TIME(__TIME__) ((__TIME__) <= 3) |
| AnnaBridge | 189:f392fc9709a3 | 96 | #endif /* FMC_BCRx_NBLSET */ |
| AnnaBridge | 189:f392fc9709a3 | 97 | |
| AnnaBridge | 189:f392fc9709a3 | 98 | #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ |
| AnnaBridge | 189:f392fc9709a3 | 99 | ((__MODE__) == FMC_ACCESS_MODE_B) || \ |
| AnnaBridge | 189:f392fc9709a3 | 100 | ((__MODE__) == FMC_ACCESS_MODE_C) || \ |
| AnnaBridge | 189:f392fc9709a3 | 101 | ((__MODE__) == FMC_ACCESS_MODE_D)) |
| AnnaBridge | 189:f392fc9709a3 | 102 | |
| AnnaBridge | 189:f392fc9709a3 | 103 | #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) |
| AnnaBridge | 189:f392fc9709a3 | 104 | |
| AnnaBridge | 189:f392fc9709a3 | 105 | #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 106 | ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 107 | |
| AnnaBridge | 189:f392fc9709a3 | 108 | #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 109 | ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) |
| AnnaBridge | 189:f392fc9709a3 | 110 | |
| AnnaBridge | 189:f392fc9709a3 | 111 | #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 112 | ((__STATE__) == FMC_NAND_ECC_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 113 | |
| AnnaBridge | 189:f392fc9709a3 | 114 | #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 115 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 116 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 117 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 118 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 119 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
| AnnaBridge | 189:f392fc9709a3 | 120 | |
| AnnaBridge | 189:f392fc9709a3 | 121 | /** @defgroup FMC_TCLR_Setup_Time FMC_TCLR_Setup_Time |
| AnnaBridge | 189:f392fc9709a3 | 122 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 123 | */ |
| AnnaBridge | 189:f392fc9709a3 | 124 | #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) |
| AnnaBridge | 189:f392fc9709a3 | 125 | /** |
| AnnaBridge | 189:f392fc9709a3 | 126 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 127 | */ |
| AnnaBridge | 189:f392fc9709a3 | 128 | |
| AnnaBridge | 189:f392fc9709a3 | 129 | /** @defgroup FMC_TAR_Setup_Time FMC_TAR_Setup_Time |
| AnnaBridge | 189:f392fc9709a3 | 130 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 131 | */ |
| AnnaBridge | 189:f392fc9709a3 | 132 | #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255) |
| AnnaBridge | 189:f392fc9709a3 | 133 | /** |
| AnnaBridge | 189:f392fc9709a3 | 134 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 135 | */ |
| AnnaBridge | 189:f392fc9709a3 | 136 | |
| AnnaBridge | 189:f392fc9709a3 | 137 | /** @defgroup FMC_Setup_Time FMC_Setup_Time |
| AnnaBridge | 189:f392fc9709a3 | 138 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 139 | */ |
| AnnaBridge | 189:f392fc9709a3 | 140 | #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255) |
| AnnaBridge | 189:f392fc9709a3 | 141 | /** |
| AnnaBridge | 189:f392fc9709a3 | 142 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 143 | */ |
| AnnaBridge | 189:f392fc9709a3 | 144 | |
| AnnaBridge | 189:f392fc9709a3 | 145 | /** @defgroup FMC_Wait_Setup_Time FMC_Wait_Setup_Time |
| AnnaBridge | 189:f392fc9709a3 | 146 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 147 | */ |
| AnnaBridge | 189:f392fc9709a3 | 148 | #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255) |
| AnnaBridge | 189:f392fc9709a3 | 149 | /** |
| AnnaBridge | 189:f392fc9709a3 | 150 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 151 | */ |
| AnnaBridge | 189:f392fc9709a3 | 152 | |
| AnnaBridge | 189:f392fc9709a3 | 153 | /** @defgroup FMC_Hold_Setup_Time FMC_Hold_Setup_Time |
| AnnaBridge | 189:f392fc9709a3 | 154 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 155 | */ |
| AnnaBridge | 189:f392fc9709a3 | 156 | #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255) |
| AnnaBridge | 189:f392fc9709a3 | 157 | /** |
| AnnaBridge | 189:f392fc9709a3 | 158 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 159 | */ |
| AnnaBridge | 189:f392fc9709a3 | 160 | |
| AnnaBridge | 189:f392fc9709a3 | 161 | /** @defgroup FMC_HiZ_Setup_Time FMC_HiZ_Setup_Time |
| AnnaBridge | 189:f392fc9709a3 | 162 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 163 | */ |
| AnnaBridge | 189:f392fc9709a3 | 164 | #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255) |
| AnnaBridge | 189:f392fc9709a3 | 165 | /** |
| AnnaBridge | 189:f392fc9709a3 | 166 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 167 | */ |
| AnnaBridge | 189:f392fc9709a3 | 168 | |
| AnnaBridge | 189:f392fc9709a3 | 169 | /** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance |
| AnnaBridge | 189:f392fc9709a3 | 170 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 171 | */ |
| AnnaBridge | 189:f392fc9709a3 | 172 | |
| AnnaBridge | 189:f392fc9709a3 | 173 | #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) |
| AnnaBridge | 189:f392fc9709a3 | 174 | |
| AnnaBridge | 189:f392fc9709a3 | 175 | /** |
| AnnaBridge | 189:f392fc9709a3 | 176 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 177 | */ |
| AnnaBridge | 189:f392fc9709a3 | 178 | |
| AnnaBridge | 189:f392fc9709a3 | 179 | /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance |
| AnnaBridge | 189:f392fc9709a3 | 180 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 181 | */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | |
| AnnaBridge | 189:f392fc9709a3 | 183 | #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) |
| AnnaBridge | 189:f392fc9709a3 | 184 | |
| AnnaBridge | 189:f392fc9709a3 | 185 | /** |
| AnnaBridge | 189:f392fc9709a3 | 186 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 187 | */ |
| AnnaBridge | 189:f392fc9709a3 | 188 | |
| AnnaBridge | 189:f392fc9709a3 | 189 | /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance |
| AnnaBridge | 189:f392fc9709a3 | 190 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 191 | */ |
| AnnaBridge | 189:f392fc9709a3 | 192 | #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) |
| AnnaBridge | 189:f392fc9709a3 | 193 | /** |
| AnnaBridge | 189:f392fc9709a3 | 194 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 195 | */ |
| AnnaBridge | 189:f392fc9709a3 | 196 | |
| AnnaBridge | 189:f392fc9709a3 | 197 | #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 198 | ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 199 | |
| AnnaBridge | 189:f392fc9709a3 | 200 | #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
| AnnaBridge | 189:f392fc9709a3 | 201 | ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) |
| AnnaBridge | 189:f392fc9709a3 | 202 | |
| AnnaBridge | 189:f392fc9709a3 | 203 | #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ |
| AnnaBridge | 189:f392fc9709a3 | 204 | ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) |
| AnnaBridge | 189:f392fc9709a3 | 205 | |
| AnnaBridge | 189:f392fc9709a3 | 206 | #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 207 | ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 208 | |
| AnnaBridge | 189:f392fc9709a3 | 209 | #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 210 | ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 211 | |
| AnnaBridge | 189:f392fc9709a3 | 212 | #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 213 | ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 214 | |
| AnnaBridge | 189:f392fc9709a3 | 215 | #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 216 | ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 217 | |
| AnnaBridge | 189:f392fc9709a3 | 218 | #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) |
| AnnaBridge | 189:f392fc9709a3 | 219 | |
| AnnaBridge | 189:f392fc9709a3 | 220 | /** @defgroup FMC_Data_Latency FMC Data Latency |
| AnnaBridge | 189:f392fc9709a3 | 221 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 222 | */ |
| AnnaBridge | 189:f392fc9709a3 | 223 | #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) |
| AnnaBridge | 189:f392fc9709a3 | 224 | /** |
| AnnaBridge | 189:f392fc9709a3 | 225 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 226 | */ |
| AnnaBridge | 189:f392fc9709a3 | 227 | |
| AnnaBridge | 189:f392fc9709a3 | 228 | /** @defgroup FMC_Address_Setup_Time FMC Address Setup Time |
| AnnaBridge | 189:f392fc9709a3 | 229 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 230 | */ |
| AnnaBridge | 189:f392fc9709a3 | 231 | #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) |
| AnnaBridge | 189:f392fc9709a3 | 232 | /** |
| AnnaBridge | 189:f392fc9709a3 | 233 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 234 | */ |
| AnnaBridge | 189:f392fc9709a3 | 235 | |
| AnnaBridge | 189:f392fc9709a3 | 236 | /** @defgroup FMC_Address_Hold_Time FMC Address Hold Time |
| AnnaBridge | 189:f392fc9709a3 | 237 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 238 | */ |
| AnnaBridge | 189:f392fc9709a3 | 239 | #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) |
| AnnaBridge | 189:f392fc9709a3 | 240 | /** |
| AnnaBridge | 189:f392fc9709a3 | 241 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 242 | */ |
| AnnaBridge | 189:f392fc9709a3 | 243 | |
| AnnaBridge | 189:f392fc9709a3 | 244 | /** @defgroup FMC_Data_Setup_Time FMC Data Setup Time |
| AnnaBridge | 189:f392fc9709a3 | 245 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 246 | */ |
| AnnaBridge | 189:f392fc9709a3 | 247 | #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) |
| AnnaBridge | 189:f392fc9709a3 | 248 | /** |
| AnnaBridge | 189:f392fc9709a3 | 249 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 250 | */ |
| AnnaBridge | 189:f392fc9709a3 | 251 | |
| AnnaBridge | 189:f392fc9709a3 | 252 | #if defined(FMC_BTRx_DATAHLD) |
| AnnaBridge | 189:f392fc9709a3 | 253 | /** @defgroup FMC_Data_Hold_Time |
| AnnaBridge | 189:f392fc9709a3 | 254 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 255 | */ |
| AnnaBridge | 189:f392fc9709a3 | 256 | #define IS_FMC_DATAHOLD_TIME(__TIME__) ((__TIME__) <= 3) |
| AnnaBridge | 189:f392fc9709a3 | 257 | /** |
| AnnaBridge | 189:f392fc9709a3 | 258 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 259 | */ |
| AnnaBridge | 189:f392fc9709a3 | 260 | #endif /* FMC_BTRx_DATAHLD */ |
| AnnaBridge | 189:f392fc9709a3 | 261 | |
| AnnaBridge | 189:f392fc9709a3 | 262 | /** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration |
| AnnaBridge | 189:f392fc9709a3 | 263 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 264 | */ |
| AnnaBridge | 189:f392fc9709a3 | 265 | #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) |
| AnnaBridge | 189:f392fc9709a3 | 266 | /** |
| AnnaBridge | 189:f392fc9709a3 | 267 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 268 | */ |
| AnnaBridge | 189:f392fc9709a3 | 269 | |
| AnnaBridge | 189:f392fc9709a3 | 270 | /** |
| AnnaBridge | 189:f392fc9709a3 | 271 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 272 | */ |
| AnnaBridge | 189:f392fc9709a3 | 273 | |
| AnnaBridge | 189:f392fc9709a3 | 274 | /* Exported typedef ----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 275 | |
| AnnaBridge | 189:f392fc9709a3 | 276 | /** @defgroup FMC_NORSRAM_Exported_typedef FMC Low Layer Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 277 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 278 | */ |
| AnnaBridge | 189:f392fc9709a3 | 279 | |
| AnnaBridge | 189:f392fc9709a3 | 280 | #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef |
| AnnaBridge | 189:f392fc9709a3 | 281 | #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef |
| AnnaBridge | 189:f392fc9709a3 | 282 | #define FMC_NAND_TypeDef FMC_Bank3_TypeDef |
| AnnaBridge | 189:f392fc9709a3 | 283 | |
| AnnaBridge | 189:f392fc9709a3 | 284 | #define FMC_NORSRAM_DEVICE FMC_Bank1_R |
| AnnaBridge | 189:f392fc9709a3 | 285 | #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R |
| AnnaBridge | 189:f392fc9709a3 | 286 | #define FMC_NAND_DEVICE FMC_Bank3_R |
| AnnaBridge | 189:f392fc9709a3 | 287 | |
| AnnaBridge | 189:f392fc9709a3 | 288 | /** |
| AnnaBridge | 189:f392fc9709a3 | 289 | * @brief FMC_NORSRAM Configuration Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 290 | */ |
| AnnaBridge | 189:f392fc9709a3 | 291 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 292 | { |
| AnnaBridge | 189:f392fc9709a3 | 293 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
| AnnaBridge | 189:f392fc9709a3 | 294 | This parameter can be a value of @ref FMC_NORSRAM_Bank */ |
| AnnaBridge | 189:f392fc9709a3 | 295 | |
| AnnaBridge | 189:f392fc9709a3 | 296 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
| AnnaBridge | 189:f392fc9709a3 | 297 | multiplexed on the data bus or not. |
| AnnaBridge | 189:f392fc9709a3 | 298 | This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ |
| AnnaBridge | 189:f392fc9709a3 | 299 | |
| AnnaBridge | 189:f392fc9709a3 | 300 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
| AnnaBridge | 189:f392fc9709a3 | 301 | the corresponding memory device. |
| AnnaBridge | 189:f392fc9709a3 | 302 | This parameter can be a value of @ref FMC_Memory_Type */ |
| AnnaBridge | 189:f392fc9709a3 | 303 | |
| AnnaBridge | 189:f392fc9709a3 | 304 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| AnnaBridge | 189:f392fc9709a3 | 305 | This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ |
| AnnaBridge | 189:f392fc9709a3 | 306 | |
| AnnaBridge | 189:f392fc9709a3 | 307 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
| AnnaBridge | 189:f392fc9709a3 | 308 | valid only with synchronous burst Flash memories. |
| AnnaBridge | 189:f392fc9709a3 | 309 | This parameter can be a value of @ref FMC_Burst_Access_Mode */ |
| AnnaBridge | 189:f392fc9709a3 | 310 | |
| AnnaBridge | 189:f392fc9709a3 | 311 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
| AnnaBridge | 189:f392fc9709a3 | 312 | the Flash memory in burst mode. |
| AnnaBridge | 189:f392fc9709a3 | 313 | This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ |
| AnnaBridge | 189:f392fc9709a3 | 314 | |
| AnnaBridge | 189:f392fc9709a3 | 315 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
| AnnaBridge | 189:f392fc9709a3 | 316 | clock cycle before the wait state or during the wait state, |
| AnnaBridge | 189:f392fc9709a3 | 317 | valid only when accessing memories in burst mode. |
| AnnaBridge | 189:f392fc9709a3 | 318 | This parameter can be a value of @ref FMC_Wait_Timing */ |
| AnnaBridge | 189:f392fc9709a3 | 319 | |
| AnnaBridge | 189:f392fc9709a3 | 320 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. |
| AnnaBridge | 189:f392fc9709a3 | 321 | This parameter can be a value of @ref FMC_Write_Operation */ |
| AnnaBridge | 189:f392fc9709a3 | 322 | |
| AnnaBridge | 189:f392fc9709a3 | 323 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
| AnnaBridge | 189:f392fc9709a3 | 324 | signal, valid for Flash memory access in burst mode. |
| AnnaBridge | 189:f392fc9709a3 | 325 | This parameter can be a value of @ref FMC_Wait_Signal */ |
| AnnaBridge | 189:f392fc9709a3 | 326 | |
| AnnaBridge | 189:f392fc9709a3 | 327 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
| AnnaBridge | 189:f392fc9709a3 | 328 | This parameter can be a value of @ref FMC_Extended_Mode */ |
| AnnaBridge | 189:f392fc9709a3 | 329 | |
| AnnaBridge | 189:f392fc9709a3 | 330 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
| AnnaBridge | 189:f392fc9709a3 | 331 | valid only with asynchronous Flash memories. |
| AnnaBridge | 189:f392fc9709a3 | 332 | This parameter can be a value of @ref FMC_AsynchronousWait */ |
| AnnaBridge | 189:f392fc9709a3 | 333 | |
| AnnaBridge | 189:f392fc9709a3 | 334 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
| AnnaBridge | 189:f392fc9709a3 | 335 | This parameter can be a value of @ref FMC_Write_Burst */ |
| AnnaBridge | 189:f392fc9709a3 | 336 | |
| AnnaBridge | 189:f392fc9709a3 | 337 | uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. |
| AnnaBridge | 189:f392fc9709a3 | 338 | This parameter is only enabled through the FMC_BCR1 register, and don't care |
| AnnaBridge | 189:f392fc9709a3 | 339 | through FMC_BCR2..4 registers. |
| AnnaBridge | 189:f392fc9709a3 | 340 | This parameter can be a value of @ref FMC_Continous_Clock */ |
| AnnaBridge | 189:f392fc9709a3 | 341 | |
| AnnaBridge | 189:f392fc9709a3 | 342 | uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. |
| AnnaBridge | 189:f392fc9709a3 | 343 | This parameter is only enabled through the FMC_BCR1 register, and don't care |
| AnnaBridge | 189:f392fc9709a3 | 344 | through FMC_BCR2..4 registers. |
| AnnaBridge | 189:f392fc9709a3 | 345 | This parameter can be a value of @ref FMC_Write_FIFO. |
| AnnaBridge | 189:f392fc9709a3 | 346 | @note This Parameter is not available for STM32L47x/L48x devices. */ |
| AnnaBridge | 189:f392fc9709a3 | 347 | |
| AnnaBridge | 189:f392fc9709a3 | 348 | #if defined(FMC_BCRx_NBLSET) |
| AnnaBridge | 189:f392fc9709a3 | 349 | uint32_t NBLSetupTime; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 189:f392fc9709a3 | 350 | the duration of the byte lane (NBL) setup time from NBLx low to Chip select NEx low. |
| AnnaBridge | 189:f392fc9709a3 | 351 | This parameter can be a value between Min_Data = 0 and Max_Data = 3. |
| AnnaBridge | 189:f392fc9709a3 | 352 | @note This parameter is used for SRAMs, ROMs and NOR Flash memories. */ |
| AnnaBridge | 189:f392fc9709a3 | 353 | #endif /* FMC_BCRx_NBLSET */ |
| AnnaBridge | 189:f392fc9709a3 | 354 | |
| AnnaBridge | 189:f392fc9709a3 | 355 | uint32_t PageSize; /*!< Specifies the memory page size. |
| AnnaBridge | 189:f392fc9709a3 | 356 | This parameter can be a value of @ref FMC_Page_Size */ |
| AnnaBridge | 189:f392fc9709a3 | 357 | }FMC_NORSRAM_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 358 | |
| AnnaBridge | 189:f392fc9709a3 | 359 | /** |
| AnnaBridge | 189:f392fc9709a3 | 360 | * @brief FMC_NORSRAM Timing parameters structure definition |
| AnnaBridge | 189:f392fc9709a3 | 361 | */ |
| AnnaBridge | 189:f392fc9709a3 | 362 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 363 | { |
| AnnaBridge | 189:f392fc9709a3 | 364 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 189:f392fc9709a3 | 365 | the duration of the address setup time. |
| AnnaBridge | 189:f392fc9709a3 | 366 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| AnnaBridge | 189:f392fc9709a3 | 367 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| AnnaBridge | 189:f392fc9709a3 | 368 | |
| AnnaBridge | 189:f392fc9709a3 | 369 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 189:f392fc9709a3 | 370 | the duration of the address hold time. |
| AnnaBridge | 189:f392fc9709a3 | 371 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
| AnnaBridge | 189:f392fc9709a3 | 372 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| AnnaBridge | 189:f392fc9709a3 | 373 | |
| AnnaBridge | 189:f392fc9709a3 | 374 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 189:f392fc9709a3 | 375 | the duration of the data setup time. |
| AnnaBridge | 189:f392fc9709a3 | 376 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
| AnnaBridge | 189:f392fc9709a3 | 377 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| AnnaBridge | 189:f392fc9709a3 | 378 | NOR Flash memories. */ |
| AnnaBridge | 189:f392fc9709a3 | 379 | |
| AnnaBridge | 189:f392fc9709a3 | 380 | #if defined(FMC_BTRx_DATAHLD) |
| AnnaBridge | 189:f392fc9709a3 | 381 | uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 189:f392fc9709a3 | 382 | the duration of the data hold time. |
| AnnaBridge | 189:f392fc9709a3 | 383 | This parameter can be a value between Min_Data = 0 and Max_Data = 3. |
| AnnaBridge | 189:f392fc9709a3 | 384 | @note This parameter value corresponds to x HCLK cycles for read and |
| AnnaBridge | 189:f392fc9709a3 | 385 | x+1 HCLK cycles for write. |
| AnnaBridge | 189:f392fc9709a3 | 386 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| AnnaBridge | 189:f392fc9709a3 | 387 | NOR Flash memories. */ |
| AnnaBridge | 189:f392fc9709a3 | 388 | #endif /* FMC_BTRx_DATAHLD */ |
| AnnaBridge | 189:f392fc9709a3 | 389 | |
| AnnaBridge | 189:f392fc9709a3 | 390 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
| AnnaBridge | 189:f392fc9709a3 | 391 | the duration of the bus turnaround. |
| AnnaBridge | 189:f392fc9709a3 | 392 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| AnnaBridge | 189:f392fc9709a3 | 393 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
| AnnaBridge | 189:f392fc9709a3 | 394 | |
| AnnaBridge | 189:f392fc9709a3 | 395 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
| AnnaBridge | 189:f392fc9709a3 | 396 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
| AnnaBridge | 189:f392fc9709a3 | 397 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
| AnnaBridge | 189:f392fc9709a3 | 398 | accesses. */ |
| AnnaBridge | 189:f392fc9709a3 | 399 | |
| AnnaBridge | 189:f392fc9709a3 | 400 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
| AnnaBridge | 189:f392fc9709a3 | 401 | to the memory before getting the first data. |
| AnnaBridge | 189:f392fc9709a3 | 402 | The parameter value depends on the memory type as shown below: |
| AnnaBridge | 189:f392fc9709a3 | 403 | - It must be set to 0 in case of a CRAM |
| AnnaBridge | 189:f392fc9709a3 | 404 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| AnnaBridge | 189:f392fc9709a3 | 405 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
| AnnaBridge | 189:f392fc9709a3 | 406 | with synchronous burst mode enable */ |
| AnnaBridge | 189:f392fc9709a3 | 407 | |
| AnnaBridge | 189:f392fc9709a3 | 408 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
| AnnaBridge | 189:f392fc9709a3 | 409 | This parameter can be a value of @ref FMC_Access_Mode */ |
| AnnaBridge | 189:f392fc9709a3 | 410 | |
| AnnaBridge | 189:f392fc9709a3 | 411 | }FMC_NORSRAM_TimingTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 412 | |
| AnnaBridge | 189:f392fc9709a3 | 413 | /** |
| AnnaBridge | 189:f392fc9709a3 | 414 | * @brief FMC_NAND Configuration Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 415 | */ |
| AnnaBridge | 189:f392fc9709a3 | 416 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 417 | { |
| AnnaBridge | 189:f392fc9709a3 | 418 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
| AnnaBridge | 189:f392fc9709a3 | 419 | This parameter can be a value of @ref FMC_NAND_Bank */ |
| AnnaBridge | 189:f392fc9709a3 | 420 | |
| AnnaBridge | 189:f392fc9709a3 | 421 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
| AnnaBridge | 189:f392fc9709a3 | 422 | This parameter can be any value of @ref FMC_Wait_feature */ |
| AnnaBridge | 189:f392fc9709a3 | 423 | |
| AnnaBridge | 189:f392fc9709a3 | 424 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| AnnaBridge | 189:f392fc9709a3 | 425 | This parameter can be any value of @ref FMC_NAND_Data_Width */ |
| AnnaBridge | 189:f392fc9709a3 | 426 | |
| AnnaBridge | 189:f392fc9709a3 | 427 | uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
| AnnaBridge | 189:f392fc9709a3 | 428 | This parameter can be any value of @ref FMC_ECC */ |
| AnnaBridge | 189:f392fc9709a3 | 429 | |
| AnnaBridge | 189:f392fc9709a3 | 430 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
| AnnaBridge | 189:f392fc9709a3 | 431 | This parameter can be any value of @ref FMC_ECC_Page_Size */ |
| AnnaBridge | 189:f392fc9709a3 | 432 | |
| AnnaBridge | 189:f392fc9709a3 | 433 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| AnnaBridge | 189:f392fc9709a3 | 434 | delay between CLE low and RE low. |
| AnnaBridge | 189:f392fc9709a3 | 435 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 189:f392fc9709a3 | 436 | |
| AnnaBridge | 189:f392fc9709a3 | 437 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| AnnaBridge | 189:f392fc9709a3 | 438 | delay between ALE low and RE low. |
| AnnaBridge | 189:f392fc9709a3 | 439 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 189:f392fc9709a3 | 440 | |
| AnnaBridge | 189:f392fc9709a3 | 441 | }FMC_NAND_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 442 | |
| AnnaBridge | 189:f392fc9709a3 | 443 | /** |
| AnnaBridge | 189:f392fc9709a3 | 444 | * @brief FMC_NAND Timing parameters structure definition |
| AnnaBridge | 189:f392fc9709a3 | 445 | */ |
| AnnaBridge | 189:f392fc9709a3 | 446 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 447 | { |
| AnnaBridge | 189:f392fc9709a3 | 448 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
| AnnaBridge | 189:f392fc9709a3 | 449 | the command assertion for NAND-Flash read or write access |
| AnnaBridge | 189:f392fc9709a3 | 450 | to common/Attribute or I/O memory space (depending on |
| AnnaBridge | 189:f392fc9709a3 | 451 | the memory space timing to be configured). |
| AnnaBridge | 189:f392fc9709a3 | 452 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 189:f392fc9709a3 | 453 | |
| AnnaBridge | 189:f392fc9709a3 | 454 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
| AnnaBridge | 189:f392fc9709a3 | 455 | command for NAND-Flash read or write access to |
| AnnaBridge | 189:f392fc9709a3 | 456 | common/Attribute or I/O memory space (depending on the |
| AnnaBridge | 189:f392fc9709a3 | 457 | memory space timing to be configured). |
| AnnaBridge | 189:f392fc9709a3 | 458 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 189:f392fc9709a3 | 459 | |
| AnnaBridge | 189:f392fc9709a3 | 460 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
| AnnaBridge | 189:f392fc9709a3 | 461 | (and data for write access) after the command de-assertion |
| AnnaBridge | 189:f392fc9709a3 | 462 | for NAND-Flash read or write access to common/Attribute |
| AnnaBridge | 189:f392fc9709a3 | 463 | or I/O memory space (depending on the memory space timing |
| AnnaBridge | 189:f392fc9709a3 | 464 | to be configured). |
| AnnaBridge | 189:f392fc9709a3 | 465 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 189:f392fc9709a3 | 466 | |
| AnnaBridge | 189:f392fc9709a3 | 467 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
| AnnaBridge | 189:f392fc9709a3 | 468 | data bus is kept in HiZ after the start of a NAND-Flash |
| AnnaBridge | 189:f392fc9709a3 | 469 | write access to common/Attribute or I/O memory space (depending |
| AnnaBridge | 189:f392fc9709a3 | 470 | on the memory space timing to be configured). |
| AnnaBridge | 189:f392fc9709a3 | 471 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 189:f392fc9709a3 | 472 | |
| AnnaBridge | 189:f392fc9709a3 | 473 | }FMC_NAND_PCC_TimingTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 474 | |
| AnnaBridge | 189:f392fc9709a3 | 475 | /** |
| AnnaBridge | 189:f392fc9709a3 | 476 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 477 | */ |
| AnnaBridge | 189:f392fc9709a3 | 478 | |
| AnnaBridge | 189:f392fc9709a3 | 479 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 480 | |
| AnnaBridge | 189:f392fc9709a3 | 481 | /** @defgroup FMC_Exported_Constants FMC Low Layer Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 482 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 483 | */ |
| AnnaBridge | 189:f392fc9709a3 | 484 | |
| AnnaBridge | 189:f392fc9709a3 | 485 | /** @defgroup FMC_NORSRAM_Exported_constants FMC NOR/SRAM Exported constants |
| AnnaBridge | 189:f392fc9709a3 | 486 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 487 | */ |
| AnnaBridge | 189:f392fc9709a3 | 488 | |
| AnnaBridge | 189:f392fc9709a3 | 489 | /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank |
| AnnaBridge | 189:f392fc9709a3 | 490 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 491 | */ |
| AnnaBridge | 189:f392fc9709a3 | 492 | #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 493 | #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) |
| AnnaBridge | 189:f392fc9709a3 | 494 | #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) |
| AnnaBridge | 189:f392fc9709a3 | 495 | #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) |
| AnnaBridge | 189:f392fc9709a3 | 496 | |
| AnnaBridge | 189:f392fc9709a3 | 497 | /** |
| AnnaBridge | 189:f392fc9709a3 | 498 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 499 | */ |
| AnnaBridge | 189:f392fc9709a3 | 500 | |
| AnnaBridge | 189:f392fc9709a3 | 501 | /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing |
| AnnaBridge | 189:f392fc9709a3 | 502 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 503 | */ |
| AnnaBridge | 189:f392fc9709a3 | 504 | |
| AnnaBridge | 189:f392fc9709a3 | 505 | #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 506 | #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN) |
| AnnaBridge | 189:f392fc9709a3 | 507 | |
| AnnaBridge | 189:f392fc9709a3 | 508 | /** |
| AnnaBridge | 189:f392fc9709a3 | 509 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 510 | */ |
| AnnaBridge | 189:f392fc9709a3 | 511 | |
| AnnaBridge | 189:f392fc9709a3 | 512 | /** @defgroup FMC_Memory_Type FMC Memory Type |
| AnnaBridge | 189:f392fc9709a3 | 513 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 514 | */ |
| AnnaBridge | 189:f392fc9709a3 | 515 | |
| AnnaBridge | 189:f392fc9709a3 | 516 | #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 517 | #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0) |
| AnnaBridge | 189:f392fc9709a3 | 518 | #define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1) |
| AnnaBridge | 189:f392fc9709a3 | 519 | |
| AnnaBridge | 189:f392fc9709a3 | 520 | /** |
| AnnaBridge | 189:f392fc9709a3 | 521 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 522 | */ |
| AnnaBridge | 189:f392fc9709a3 | 523 | |
| AnnaBridge | 189:f392fc9709a3 | 524 | /** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width |
| AnnaBridge | 189:f392fc9709a3 | 525 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 526 | */ |
| AnnaBridge | 189:f392fc9709a3 | 527 | |
| AnnaBridge | 189:f392fc9709a3 | 528 | #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 529 | #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0) |
| AnnaBridge | 189:f392fc9709a3 | 530 | #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1) |
| AnnaBridge | 189:f392fc9709a3 | 531 | |
| AnnaBridge | 189:f392fc9709a3 | 532 | /** |
| AnnaBridge | 189:f392fc9709a3 | 533 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 534 | */ |
| AnnaBridge | 189:f392fc9709a3 | 535 | |
| AnnaBridge | 189:f392fc9709a3 | 536 | /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access |
| AnnaBridge | 189:f392fc9709a3 | 537 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 538 | */ |
| AnnaBridge | 189:f392fc9709a3 | 539 | |
| AnnaBridge | 189:f392fc9709a3 | 540 | #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN) |
| AnnaBridge | 189:f392fc9709a3 | 541 | #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 542 | /** |
| AnnaBridge | 189:f392fc9709a3 | 543 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 544 | */ |
| AnnaBridge | 189:f392fc9709a3 | 545 | |
| AnnaBridge | 189:f392fc9709a3 | 546 | /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode |
| AnnaBridge | 189:f392fc9709a3 | 547 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 548 | */ |
| AnnaBridge | 189:f392fc9709a3 | 549 | |
| AnnaBridge | 189:f392fc9709a3 | 550 | #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 551 | #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN) |
| AnnaBridge | 189:f392fc9709a3 | 552 | |
| AnnaBridge | 189:f392fc9709a3 | 553 | /** |
| AnnaBridge | 189:f392fc9709a3 | 554 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 555 | */ |
| AnnaBridge | 189:f392fc9709a3 | 556 | |
| AnnaBridge | 189:f392fc9709a3 | 557 | |
| AnnaBridge | 189:f392fc9709a3 | 558 | /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity |
| AnnaBridge | 189:f392fc9709a3 | 559 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 560 | */ |
| AnnaBridge | 189:f392fc9709a3 | 561 | |
| AnnaBridge | 189:f392fc9709a3 | 562 | #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 563 | #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL) |
| AnnaBridge | 189:f392fc9709a3 | 564 | |
| AnnaBridge | 189:f392fc9709a3 | 565 | /** |
| AnnaBridge | 189:f392fc9709a3 | 566 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 567 | */ |
| AnnaBridge | 189:f392fc9709a3 | 568 | |
| AnnaBridge | 189:f392fc9709a3 | 569 | /** |
| AnnaBridge | 189:f392fc9709a3 | 570 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 571 | */ |
| AnnaBridge | 189:f392fc9709a3 | 572 | |
| AnnaBridge | 189:f392fc9709a3 | 573 | /** @defgroup FMC_Wait_Timing FMC Wait Timing |
| AnnaBridge | 189:f392fc9709a3 | 574 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 575 | */ |
| AnnaBridge | 189:f392fc9709a3 | 576 | |
| AnnaBridge | 189:f392fc9709a3 | 577 | #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 578 | #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG) |
| AnnaBridge | 189:f392fc9709a3 | 579 | |
| AnnaBridge | 189:f392fc9709a3 | 580 | /** |
| AnnaBridge | 189:f392fc9709a3 | 581 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 582 | */ |
| AnnaBridge | 189:f392fc9709a3 | 583 | |
| AnnaBridge | 189:f392fc9709a3 | 584 | /** @defgroup FMC_Write_Operation FMC Write Operation |
| AnnaBridge | 189:f392fc9709a3 | 585 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 586 | */ |
| AnnaBridge | 189:f392fc9709a3 | 587 | |
| AnnaBridge | 189:f392fc9709a3 | 588 | #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 589 | #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN) |
| AnnaBridge | 189:f392fc9709a3 | 590 | |
| AnnaBridge | 189:f392fc9709a3 | 591 | /** |
| AnnaBridge | 189:f392fc9709a3 | 592 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 593 | */ |
| AnnaBridge | 189:f392fc9709a3 | 594 | |
| AnnaBridge | 189:f392fc9709a3 | 595 | /** @defgroup FMC_Wait_Signal FMC Wait Signal |
| AnnaBridge | 189:f392fc9709a3 | 596 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 597 | */ |
| AnnaBridge | 189:f392fc9709a3 | 598 | |
| AnnaBridge | 189:f392fc9709a3 | 599 | #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 600 | #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN) |
| AnnaBridge | 189:f392fc9709a3 | 601 | |
| AnnaBridge | 189:f392fc9709a3 | 602 | /** |
| AnnaBridge | 189:f392fc9709a3 | 603 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 604 | */ |
| AnnaBridge | 189:f392fc9709a3 | 605 | |
| AnnaBridge | 189:f392fc9709a3 | 606 | /** @defgroup FMC_Extended_Mode FMC Extended Mode |
| AnnaBridge | 189:f392fc9709a3 | 607 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 608 | */ |
| AnnaBridge | 189:f392fc9709a3 | 609 | |
| AnnaBridge | 189:f392fc9709a3 | 610 | #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 611 | #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD) |
| AnnaBridge | 189:f392fc9709a3 | 612 | |
| AnnaBridge | 189:f392fc9709a3 | 613 | /** |
| AnnaBridge | 189:f392fc9709a3 | 614 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 615 | */ |
| AnnaBridge | 189:f392fc9709a3 | 616 | |
| AnnaBridge | 189:f392fc9709a3 | 617 | /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait |
| AnnaBridge | 189:f392fc9709a3 | 618 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 619 | */ |
| AnnaBridge | 189:f392fc9709a3 | 620 | |
| AnnaBridge | 189:f392fc9709a3 | 621 | #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 622 | #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT) |
| AnnaBridge | 189:f392fc9709a3 | 623 | |
| AnnaBridge | 189:f392fc9709a3 | 624 | /** |
| AnnaBridge | 189:f392fc9709a3 | 625 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 626 | */ |
| AnnaBridge | 189:f392fc9709a3 | 627 | |
| AnnaBridge | 189:f392fc9709a3 | 628 | /** @defgroup FMC_Page_Size FMC Page Size |
| AnnaBridge | 189:f392fc9709a3 | 629 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 630 | */ |
| AnnaBridge | 189:f392fc9709a3 | 631 | #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 632 | #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) |
| AnnaBridge | 189:f392fc9709a3 | 633 | #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) |
| AnnaBridge | 189:f392fc9709a3 | 634 | #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1)) |
| AnnaBridge | 189:f392fc9709a3 | 635 | #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2) |
| AnnaBridge | 189:f392fc9709a3 | 636 | /** |
| AnnaBridge | 189:f392fc9709a3 | 637 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 638 | */ |
| AnnaBridge | 189:f392fc9709a3 | 639 | |
| AnnaBridge | 189:f392fc9709a3 | 640 | /** @defgroup FMC_Write_Burst FMC Write Burst |
| AnnaBridge | 189:f392fc9709a3 | 641 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 642 | */ |
| AnnaBridge | 189:f392fc9709a3 | 643 | |
| AnnaBridge | 189:f392fc9709a3 | 644 | #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 645 | #define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW) |
| AnnaBridge | 189:f392fc9709a3 | 646 | |
| AnnaBridge | 189:f392fc9709a3 | 647 | /** |
| AnnaBridge | 189:f392fc9709a3 | 648 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 649 | */ |
| AnnaBridge | 189:f392fc9709a3 | 650 | |
| AnnaBridge | 189:f392fc9709a3 | 651 | /** @defgroup FMC_Continous_Clock FMC Continous Clock |
| AnnaBridge | 189:f392fc9709a3 | 652 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 653 | */ |
| AnnaBridge | 189:f392fc9709a3 | 654 | #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 655 | #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN) |
| AnnaBridge | 189:f392fc9709a3 | 656 | /** |
| AnnaBridge | 189:f392fc9709a3 | 657 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 658 | */ |
| AnnaBridge | 189:f392fc9709a3 | 659 | |
| AnnaBridge | 189:f392fc9709a3 | 660 | #if defined(FMC_BCR1_WFDIS) |
| AnnaBridge | 189:f392fc9709a3 | 661 | /** @defgroup FMC_Write_FIFO FMC Write FIFO |
| AnnaBridge | 189:f392fc9709a3 | 662 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 663 | */ |
| AnnaBridge | 189:f392fc9709a3 | 664 | #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) |
| AnnaBridge | 189:f392fc9709a3 | 665 | #define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 666 | /** |
| AnnaBridge | 189:f392fc9709a3 | 667 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 668 | */ |
| AnnaBridge | 189:f392fc9709a3 | 669 | |
| AnnaBridge | 189:f392fc9709a3 | 670 | #endif /* FMC_BCR1_WFDIS */ |
| AnnaBridge | 189:f392fc9709a3 | 671 | /** @defgroup FMC_Access_Mode FMC Access Mode |
| AnnaBridge | 189:f392fc9709a3 | 672 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 673 | */ |
| AnnaBridge | 189:f392fc9709a3 | 674 | |
| AnnaBridge | 189:f392fc9709a3 | 675 | #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 676 | #define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0) |
| AnnaBridge | 189:f392fc9709a3 | 677 | #define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1) |
| AnnaBridge | 189:f392fc9709a3 | 678 | #define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1)) |
| AnnaBridge | 189:f392fc9709a3 | 679 | |
| AnnaBridge | 189:f392fc9709a3 | 680 | /** |
| AnnaBridge | 189:f392fc9709a3 | 681 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 682 | */ |
| AnnaBridge | 189:f392fc9709a3 | 683 | |
| AnnaBridge | 189:f392fc9709a3 | 684 | /** |
| AnnaBridge | 189:f392fc9709a3 | 685 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 686 | */ |
| AnnaBridge | 189:f392fc9709a3 | 687 | |
| AnnaBridge | 189:f392fc9709a3 | 688 | /** @defgroup FMC_NAND_Controller FMC NAND and PCCARD Controller |
| AnnaBridge | 189:f392fc9709a3 | 689 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 690 | */ |
| AnnaBridge | 189:f392fc9709a3 | 691 | |
| AnnaBridge | 189:f392fc9709a3 | 692 | /** @defgroup FMC_NAND_Bank FMC NAND Bank |
| AnnaBridge | 189:f392fc9709a3 | 693 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 694 | */ |
| AnnaBridge | 189:f392fc9709a3 | 695 | #define FMC_NAND_BANK3 ((uint32_t)0x00000100) |
| AnnaBridge | 189:f392fc9709a3 | 696 | |
| AnnaBridge | 189:f392fc9709a3 | 697 | /** |
| AnnaBridge | 189:f392fc9709a3 | 698 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 699 | */ |
| AnnaBridge | 189:f392fc9709a3 | 700 | |
| AnnaBridge | 189:f392fc9709a3 | 701 | /** @defgroup FMC_Wait_feature FMC Wait feature |
| AnnaBridge | 189:f392fc9709a3 | 702 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 703 | */ |
| AnnaBridge | 189:f392fc9709a3 | 704 | #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 705 | #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCR_PWAITEN) |
| AnnaBridge | 189:f392fc9709a3 | 706 | |
| AnnaBridge | 189:f392fc9709a3 | 707 | /** |
| AnnaBridge | 189:f392fc9709a3 | 708 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 709 | */ |
| AnnaBridge | 189:f392fc9709a3 | 710 | |
| AnnaBridge | 189:f392fc9709a3 | 711 | /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type |
| AnnaBridge | 189:f392fc9709a3 | 712 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 713 | */ |
| AnnaBridge | 189:f392fc9709a3 | 714 | #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCR_PTYP) |
| AnnaBridge | 189:f392fc9709a3 | 715 | /** |
| AnnaBridge | 189:f392fc9709a3 | 716 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 717 | */ |
| AnnaBridge | 189:f392fc9709a3 | 718 | |
| AnnaBridge | 189:f392fc9709a3 | 719 | /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width |
| AnnaBridge | 189:f392fc9709a3 | 720 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 721 | */ |
| AnnaBridge | 189:f392fc9709a3 | 722 | #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 723 | #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCR_PWID_0) |
| AnnaBridge | 189:f392fc9709a3 | 724 | |
| AnnaBridge | 189:f392fc9709a3 | 725 | /** |
| AnnaBridge | 189:f392fc9709a3 | 726 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 727 | */ |
| AnnaBridge | 189:f392fc9709a3 | 728 | |
| AnnaBridge | 189:f392fc9709a3 | 729 | /** @defgroup FMC_ECC FMC NAND ECC |
| AnnaBridge | 189:f392fc9709a3 | 730 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 731 | */ |
| AnnaBridge | 189:f392fc9709a3 | 732 | #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 733 | #define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCR_ECCEN) |
| AnnaBridge | 189:f392fc9709a3 | 734 | |
| AnnaBridge | 189:f392fc9709a3 | 735 | /** |
| AnnaBridge | 189:f392fc9709a3 | 736 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 737 | */ |
| AnnaBridge | 189:f392fc9709a3 | 738 | |
| AnnaBridge | 189:f392fc9709a3 | 739 | /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size |
| AnnaBridge | 189:f392fc9709a3 | 740 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 741 | */ |
| AnnaBridge | 189:f392fc9709a3 | 742 | #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 743 | #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCR_ECCPS_0) |
| AnnaBridge | 189:f392fc9709a3 | 744 | #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCR_ECCPS_1) |
| AnnaBridge | 189:f392fc9709a3 | 745 | #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_1) |
| AnnaBridge | 189:f392fc9709a3 | 746 | #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCR_ECCPS_2) |
| AnnaBridge | 189:f392fc9709a3 | 747 | #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_2) |
| AnnaBridge | 189:f392fc9709a3 | 748 | |
| AnnaBridge | 189:f392fc9709a3 | 749 | /** |
| AnnaBridge | 189:f392fc9709a3 | 750 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 751 | */ |
| AnnaBridge | 189:f392fc9709a3 | 752 | |
| AnnaBridge | 189:f392fc9709a3 | 753 | /** @defgroup FMC_Interrupt_definition FMC Interrupt definition |
| AnnaBridge | 189:f392fc9709a3 | 754 | * @brief FMC Interrupt definition |
| AnnaBridge | 189:f392fc9709a3 | 755 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 756 | */ |
| AnnaBridge | 189:f392fc9709a3 | 757 | #define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN) |
| AnnaBridge | 189:f392fc9709a3 | 758 | #define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN) |
| AnnaBridge | 189:f392fc9709a3 | 759 | #define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN) |
| AnnaBridge | 189:f392fc9709a3 | 760 | |
| AnnaBridge | 189:f392fc9709a3 | 761 | /** |
| AnnaBridge | 189:f392fc9709a3 | 762 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 763 | */ |
| AnnaBridge | 189:f392fc9709a3 | 764 | |
| AnnaBridge | 189:f392fc9709a3 | 765 | /** @defgroup FMC_Flag_definition FMC Flag definition |
| AnnaBridge | 189:f392fc9709a3 | 766 | * @brief FMC Flag definition |
| AnnaBridge | 189:f392fc9709a3 | 767 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 768 | */ |
| AnnaBridge | 189:f392fc9709a3 | 769 | #define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SR_IRS) |
| AnnaBridge | 189:f392fc9709a3 | 770 | #define FMC_FLAG_LEVEL ((uint32_t)FMC_SR_ILS) |
| AnnaBridge | 189:f392fc9709a3 | 771 | #define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SR_IFS) |
| AnnaBridge | 189:f392fc9709a3 | 772 | #define FMC_FLAG_FEMPT ((uint32_t)FMC_SR_FEMPT) |
| AnnaBridge | 189:f392fc9709a3 | 773 | |
| AnnaBridge | 189:f392fc9709a3 | 774 | /** |
| AnnaBridge | 189:f392fc9709a3 | 775 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 776 | */ |
| AnnaBridge | 189:f392fc9709a3 | 777 | |
| AnnaBridge | 189:f392fc9709a3 | 778 | /** |
| AnnaBridge | 189:f392fc9709a3 | 779 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 780 | */ |
| AnnaBridge | 189:f392fc9709a3 | 781 | |
| AnnaBridge | 189:f392fc9709a3 | 782 | /** |
| AnnaBridge | 189:f392fc9709a3 | 783 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 784 | */ |
| AnnaBridge | 189:f392fc9709a3 | 785 | |
| AnnaBridge | 189:f392fc9709a3 | 786 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 787 | |
| AnnaBridge | 189:f392fc9709a3 | 788 | /** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 789 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 790 | */ |
| AnnaBridge | 189:f392fc9709a3 | 791 | |
| AnnaBridge | 189:f392fc9709a3 | 792 | /** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 793 | * @brief macros to handle NOR device enable/disable and read/write operations |
| AnnaBridge | 189:f392fc9709a3 | 794 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 795 | */ |
| AnnaBridge | 189:f392fc9709a3 | 796 | |
| AnnaBridge | 189:f392fc9709a3 | 797 | /** |
| AnnaBridge | 189:f392fc9709a3 | 798 | * @brief Enable the NORSRAM device access. |
| AnnaBridge | 189:f392fc9709a3 | 799 | * @param __INSTANCE__ FMC_NORSRAM Instance |
| AnnaBridge | 189:f392fc9709a3 | 800 | * @param __BANK__ FMC_NORSRAM Bank |
| AnnaBridge | 189:f392fc9709a3 | 801 | * @retval none |
| AnnaBridge | 189:f392fc9709a3 | 802 | */ |
| AnnaBridge | 189:f392fc9709a3 | 803 | #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) |
| AnnaBridge | 189:f392fc9709a3 | 804 | |
| AnnaBridge | 189:f392fc9709a3 | 805 | /** |
| AnnaBridge | 189:f392fc9709a3 | 806 | * @brief Disable the NORSRAM device access. |
| AnnaBridge | 189:f392fc9709a3 | 807 | * @param __INSTANCE__ FMC_NORSRAM Instance |
| AnnaBridge | 189:f392fc9709a3 | 808 | * @param __BANK__ FMC_NORSRAM Bank |
| AnnaBridge | 189:f392fc9709a3 | 809 | * @retval none |
| AnnaBridge | 189:f392fc9709a3 | 810 | */ |
| AnnaBridge | 189:f392fc9709a3 | 811 | #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) |
| AnnaBridge | 189:f392fc9709a3 | 812 | |
| AnnaBridge | 189:f392fc9709a3 | 813 | /** |
| AnnaBridge | 189:f392fc9709a3 | 814 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 815 | */ |
| AnnaBridge | 189:f392fc9709a3 | 816 | |
| AnnaBridge | 189:f392fc9709a3 | 817 | /** @defgroup FMC_NAND_Macros FMC NAND Macros |
| AnnaBridge | 189:f392fc9709a3 | 818 | * @brief macros to handle NAND device enable/disable |
| AnnaBridge | 189:f392fc9709a3 | 819 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 820 | */ |
| AnnaBridge | 189:f392fc9709a3 | 821 | |
| AnnaBridge | 189:f392fc9709a3 | 822 | /** |
| AnnaBridge | 189:f392fc9709a3 | 823 | * @brief Enable the NAND device access. |
| AnnaBridge | 189:f392fc9709a3 | 824 | * @param __INSTANCE__ FMC_NAND Instance |
| AnnaBridge | 189:f392fc9709a3 | 825 | * @param __BANK__ FMC_NAND Bank |
| AnnaBridge | 189:f392fc9709a3 | 826 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 827 | */ |
| AnnaBridge | 189:f392fc9709a3 | 828 | #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) |
| AnnaBridge | 189:f392fc9709a3 | 829 | |
| AnnaBridge | 189:f392fc9709a3 | 830 | /** |
| AnnaBridge | 189:f392fc9709a3 | 831 | * @brief Disable the NAND device access. |
| AnnaBridge | 189:f392fc9709a3 | 832 | * @param __INSTANCE__ FMC_NAND Instance |
| AnnaBridge | 189:f392fc9709a3 | 833 | * @param __BANK__ FMC_NAND Bank |
| AnnaBridge | 189:f392fc9709a3 | 834 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 835 | */ |
| AnnaBridge | 189:f392fc9709a3 | 836 | #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) |
| AnnaBridge | 189:f392fc9709a3 | 837 | |
| AnnaBridge | 189:f392fc9709a3 | 838 | /** |
| AnnaBridge | 189:f392fc9709a3 | 839 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 840 | */ |
| AnnaBridge | 189:f392fc9709a3 | 841 | |
| AnnaBridge | 189:f392fc9709a3 | 842 | /** @defgroup FMC_Interrupt FMC Interrupt |
| AnnaBridge | 189:f392fc9709a3 | 843 | * @brief macros to handle FMC interrupts |
| AnnaBridge | 189:f392fc9709a3 | 844 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 845 | */ |
| AnnaBridge | 189:f392fc9709a3 | 846 | |
| AnnaBridge | 189:f392fc9709a3 | 847 | /** |
| AnnaBridge | 189:f392fc9709a3 | 848 | * @brief Enable the NAND device interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 849 | * @param __INSTANCE__ FMC_NAND Instance |
| AnnaBridge | 189:f392fc9709a3 | 850 | * @param __BANK__ FMC_NAND Bank |
| AnnaBridge | 189:f392fc9709a3 | 851 | * @param __INTERRUPT__ FMC_NAND interrupt |
| AnnaBridge | 189:f392fc9709a3 | 852 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 853 | * @arg FMC_IT_RISING_EDGE Interrupt rising edge. |
| AnnaBridge | 189:f392fc9709a3 | 854 | * @arg FMC_IT_LEVEL Interrupt level. |
| AnnaBridge | 189:f392fc9709a3 | 855 | * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. |
| AnnaBridge | 189:f392fc9709a3 | 856 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 857 | */ |
| AnnaBridge | 189:f392fc9709a3 | 858 | #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 859 | |
| AnnaBridge | 189:f392fc9709a3 | 860 | /** |
| AnnaBridge | 189:f392fc9709a3 | 861 | * @brief Disable the NAND device interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 862 | * @param __INSTANCE__ FMC_NAND Instance |
| AnnaBridge | 189:f392fc9709a3 | 863 | * @param __BANK__ FMC_NAND Bank |
| AnnaBridge | 189:f392fc9709a3 | 864 | * @param __INTERRUPT__ FMC_NAND interrupt |
| AnnaBridge | 189:f392fc9709a3 | 865 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 866 | * @arg FMC_IT_RISING_EDGE Interrupt rising edge. |
| AnnaBridge | 189:f392fc9709a3 | 867 | * @arg FMC_IT_LEVEL Interrupt level. |
| AnnaBridge | 189:f392fc9709a3 | 868 | * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. |
| AnnaBridge | 189:f392fc9709a3 | 869 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 870 | */ |
| AnnaBridge | 189:f392fc9709a3 | 871 | #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 872 | |
| AnnaBridge | 189:f392fc9709a3 | 873 | /** |
| AnnaBridge | 189:f392fc9709a3 | 874 | * @brief Get flag status of the NAND device. |
| AnnaBridge | 189:f392fc9709a3 | 875 | * @param __INSTANCE__ FMC_NAND Instance |
| AnnaBridge | 189:f392fc9709a3 | 876 | * @param __BANK__ FMC_NAND Bank |
| AnnaBridge | 189:f392fc9709a3 | 877 | * @param __FLAG__ FMC_NAND flag |
| AnnaBridge | 189:f392fc9709a3 | 878 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 879 | * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag. |
| AnnaBridge | 189:f392fc9709a3 | 880 | * @arg FMC_FLAG_LEVEL Interrupt level edge flag. |
| AnnaBridge | 189:f392fc9709a3 | 881 | * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag. |
| AnnaBridge | 189:f392fc9709a3 | 882 | * @arg FMC_FLAG_FEMPT FIFO empty flag. |
| AnnaBridge | 189:f392fc9709a3 | 883 | * @retval The state of FLAG (SET or RESET). |
| AnnaBridge | 189:f392fc9709a3 | 884 | */ |
| AnnaBridge | 189:f392fc9709a3 | 885 | #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 189:f392fc9709a3 | 886 | |
| AnnaBridge | 189:f392fc9709a3 | 887 | /** |
| AnnaBridge | 189:f392fc9709a3 | 888 | * @brief Clear flag status of the NAND device. |
| AnnaBridge | 189:f392fc9709a3 | 889 | * @param __INSTANCE__ FMC_NAND Instance |
| AnnaBridge | 189:f392fc9709a3 | 890 | * @param __BANK__ FMC_NAND Bank |
| AnnaBridge | 189:f392fc9709a3 | 891 | * @param __FLAG__ FMC_NAND flag |
| AnnaBridge | 189:f392fc9709a3 | 892 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 893 | * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag. |
| AnnaBridge | 189:f392fc9709a3 | 894 | * @arg FMC_FLAG_LEVEL Interrupt level edge flag. |
| AnnaBridge | 189:f392fc9709a3 | 895 | * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag. |
| AnnaBridge | 189:f392fc9709a3 | 896 | * @arg FMC_FLAG_FEMPT FIFO empty flag. |
| AnnaBridge | 189:f392fc9709a3 | 897 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 898 | */ |
| AnnaBridge | 189:f392fc9709a3 | 899 | #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR, (__FLAG__)) |
| AnnaBridge | 189:f392fc9709a3 | 900 | |
| AnnaBridge | 189:f392fc9709a3 | 901 | /** |
| AnnaBridge | 189:f392fc9709a3 | 902 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 903 | */ |
| AnnaBridge | 189:f392fc9709a3 | 904 | |
| AnnaBridge | 189:f392fc9709a3 | 905 | |
| AnnaBridge | 189:f392fc9709a3 | 906 | /** |
| AnnaBridge | 189:f392fc9709a3 | 907 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 908 | */ |
| AnnaBridge | 189:f392fc9709a3 | 909 | |
| AnnaBridge | 189:f392fc9709a3 | 910 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 911 | |
| AnnaBridge | 189:f392fc9709a3 | 912 | /** @addtogroup FMC_LL_Exported_Functions |
| AnnaBridge | 189:f392fc9709a3 | 913 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 914 | */ |
| AnnaBridge | 189:f392fc9709a3 | 915 | |
| AnnaBridge | 189:f392fc9709a3 | 916 | /** @addtogroup FMC_NORSRAM |
| AnnaBridge | 189:f392fc9709a3 | 917 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 918 | */ |
| AnnaBridge | 189:f392fc9709a3 | 919 | |
| AnnaBridge | 189:f392fc9709a3 | 920 | /** @addtogroup FMC_NORSRAM_Group1 |
| AnnaBridge | 189:f392fc9709a3 | 921 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 922 | */ |
| AnnaBridge | 189:f392fc9709a3 | 923 | |
| AnnaBridge | 189:f392fc9709a3 | 924 | /* FMC_NORSRAM Controller functions ******************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 925 | /* Initialization/de-initialization functions */ |
| AnnaBridge | 189:f392fc9709a3 | 926 | HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); |
| AnnaBridge | 189:f392fc9709a3 | 927 | HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
| AnnaBridge | 189:f392fc9709a3 | 928 | HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
| AnnaBridge | 189:f392fc9709a3 | 929 | HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
| AnnaBridge | 189:f392fc9709a3 | 930 | |
| AnnaBridge | 189:f392fc9709a3 | 931 | /** |
| AnnaBridge | 189:f392fc9709a3 | 932 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 933 | */ |
| AnnaBridge | 189:f392fc9709a3 | 934 | |
| AnnaBridge | 189:f392fc9709a3 | 935 | /** @addtogroup FMC_NORSRAM_Group2 |
| AnnaBridge | 189:f392fc9709a3 | 936 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 937 | */ |
| AnnaBridge | 189:f392fc9709a3 | 938 | |
| AnnaBridge | 189:f392fc9709a3 | 939 | /* FMC_NORSRAM Control functions */ |
| AnnaBridge | 189:f392fc9709a3 | 940 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| AnnaBridge | 189:f392fc9709a3 | 941 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| AnnaBridge | 189:f392fc9709a3 | 942 | |
| AnnaBridge | 189:f392fc9709a3 | 943 | /** |
| AnnaBridge | 189:f392fc9709a3 | 944 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 945 | */ |
| AnnaBridge | 189:f392fc9709a3 | 946 | |
| AnnaBridge | 189:f392fc9709a3 | 947 | /** |
| AnnaBridge | 189:f392fc9709a3 | 948 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 949 | */ |
| AnnaBridge | 189:f392fc9709a3 | 950 | |
| AnnaBridge | 189:f392fc9709a3 | 951 | /** @addtogroup FMC_NAND |
| AnnaBridge | 189:f392fc9709a3 | 952 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 953 | */ |
| AnnaBridge | 189:f392fc9709a3 | 954 | |
| AnnaBridge | 189:f392fc9709a3 | 955 | /* FMC_NAND Controller functions **********************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 956 | /* Initialization/de-initialization functions */ |
| AnnaBridge | 189:f392fc9709a3 | 957 | /** @addtogroup FMC_NAND_Exported_Functions_Group1 |
| AnnaBridge | 189:f392fc9709a3 | 958 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 959 | */ |
| AnnaBridge | 189:f392fc9709a3 | 960 | |
| AnnaBridge | 189:f392fc9709a3 | 961 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); |
| AnnaBridge | 189:f392fc9709a3 | 962 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| AnnaBridge | 189:f392fc9709a3 | 963 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| AnnaBridge | 189:f392fc9709a3 | 964 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); |
| AnnaBridge | 189:f392fc9709a3 | 965 | |
| AnnaBridge | 189:f392fc9709a3 | 966 | /** |
| AnnaBridge | 189:f392fc9709a3 | 967 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 968 | */ |
| AnnaBridge | 189:f392fc9709a3 | 969 | |
| AnnaBridge | 189:f392fc9709a3 | 970 | /* FMC_NAND Control functions */ |
| AnnaBridge | 189:f392fc9709a3 | 971 | /** @addtogroup FMC_NAND_Exported_Functions_Group2 |
| AnnaBridge | 189:f392fc9709a3 | 972 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 973 | */ |
| AnnaBridge | 189:f392fc9709a3 | 974 | |
| AnnaBridge | 189:f392fc9709a3 | 975 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); |
| AnnaBridge | 189:f392fc9709a3 | 976 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); |
| AnnaBridge | 189:f392fc9709a3 | 977 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 978 | |
| AnnaBridge | 189:f392fc9709a3 | 979 | /** |
| AnnaBridge | 189:f392fc9709a3 | 980 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 981 | */ |
| AnnaBridge | 189:f392fc9709a3 | 982 | |
| AnnaBridge | 189:f392fc9709a3 | 983 | /** |
| AnnaBridge | 189:f392fc9709a3 | 984 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 985 | */ |
| AnnaBridge | 189:f392fc9709a3 | 986 | |
| AnnaBridge | 189:f392fc9709a3 | 987 | /** |
| AnnaBridge | 189:f392fc9709a3 | 988 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 989 | */ |
| AnnaBridge | 189:f392fc9709a3 | 990 | |
| AnnaBridge | 189:f392fc9709a3 | 991 | /** |
| AnnaBridge | 189:f392fc9709a3 | 992 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 993 | */ |
| AnnaBridge | 189:f392fc9709a3 | 994 | |
| AnnaBridge | 189:f392fc9709a3 | 995 | #endif /* FMC_BANK1 */ |
| AnnaBridge | 189:f392fc9709a3 | 996 | |
| AnnaBridge | 189:f392fc9709a3 | 997 | /** |
| AnnaBridge | 189:f392fc9709a3 | 998 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 999 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1000 | |
| AnnaBridge | 189:f392fc9709a3 | 1001 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 1002 | } |
| AnnaBridge | 189:f392fc9709a3 | 1003 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 1004 | |
| AnnaBridge | 189:f392fc9709a3 | 1005 | #endif /* __STM32L4xx_LL_FMC_H */ |
| AnnaBridge | 189:f392fc9709a3 | 1006 | |
| AnnaBridge | 189:f392fc9709a3 | 1007 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| AnnaBridge | 189:f392fc9709a3 | 1008 |
