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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_ll_dma.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l4xx_ll_dma.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of DMA LL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L4xx_LL_DMA_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L4xx_LL_DMA_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	45	#include "stm32l4xx.h"
AnnaBridge	189:f392fc9709a3	46	#if defined(DMAMUX1)
AnnaBridge	189:f392fc9709a3	47	#include "stm32l4xx_ll_dmamux.h"
AnnaBridge	189:f392fc9709a3	48	#endif /* DMAMUX1 */
AnnaBridge	189:f392fc9709a3	49
AnnaBridge	189:f392fc9709a3	50	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	189:f392fc9709a3	51	* @{
AnnaBridge	189:f392fc9709a3	52	*/
AnnaBridge	189:f392fc9709a3	53
AnnaBridge	189:f392fc9709a3	54	#if defined (DMA1) \|\| defined (DMA2)
AnnaBridge	189:f392fc9709a3	55
AnnaBridge	189:f392fc9709a3	56	/** @defgroup DMA_LL DMA
AnnaBridge	189:f392fc9709a3	57	* @{
AnnaBridge	189:f392fc9709a3	58	*/
AnnaBridge	189:f392fc9709a3	59
AnnaBridge	189:f392fc9709a3	60	/* Private types -------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	61	/* Private variables ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	62	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge	189:f392fc9709a3	63	* @{
AnnaBridge	189:f392fc9709a3	64	*/
AnnaBridge	189:f392fc9709a3	65	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
AnnaBridge	189:f392fc9709a3	66	static const uint8_t CHANNEL_OFFSET_TAB[] =
AnnaBridge	189:f392fc9709a3	67	{
AnnaBridge	189:f392fc9709a3	68	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
AnnaBridge	189:f392fc9709a3	69	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
AnnaBridge	189:f392fc9709a3	70	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
AnnaBridge	189:f392fc9709a3	71	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
AnnaBridge	189:f392fc9709a3	72	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
AnnaBridge	189:f392fc9709a3	73	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
AnnaBridge	189:f392fc9709a3	74	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
AnnaBridge	189:f392fc9709a3	75	};
AnnaBridge	189:f392fc9709a3	76	/**
AnnaBridge	189:f392fc9709a3	77	* @}
AnnaBridge	189:f392fc9709a3	78	*/
AnnaBridge	189:f392fc9709a3	79
AnnaBridge	189:f392fc9709a3	80	/* Private constants ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	81	#if defined(DMAMUX1)
AnnaBridge	189:f392fc9709a3	82	#else
AnnaBridge	189:f392fc9709a3	83	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
AnnaBridge	189:f392fc9709a3	84	* @{
AnnaBridge	189:f392fc9709a3	85	*/
AnnaBridge	189:f392fc9709a3	86	/* Define used to get CSELR register offset */
AnnaBridge	189:f392fc9709a3	87	#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
AnnaBridge	189:f392fc9709a3	88
AnnaBridge	189:f392fc9709a3	89	/* Defines used for the bit position in the register and perform offsets */
AnnaBridge	189:f392fc9709a3	90	#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
AnnaBridge	189:f392fc9709a3	91	/**
AnnaBridge	189:f392fc9709a3	92	* @}
AnnaBridge	189:f392fc9709a3	93	*/
AnnaBridge	189:f392fc9709a3	94	#endif /* DMAMUX1 */
AnnaBridge	189:f392fc9709a3	95
AnnaBridge	189:f392fc9709a3	96	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	97	#if defined(DMAMUX1)
AnnaBridge	189:f392fc9709a3	98	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge	189:f392fc9709a3	99	* @{
AnnaBridge	189:f392fc9709a3	100	*/
AnnaBridge	189:f392fc9709a3	101	/**
AnnaBridge	189:f392fc9709a3	102	* @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
AnnaBridge	189:f392fc9709a3	103	* @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
AnnaBridge	189:f392fc9709a3	104	* DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
AnnaBridge	189:f392fc9709a3	105	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	189:f392fc9709a3	106	* @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0).
AnnaBridge	189:f392fc9709a3	107	*/
AnnaBridge	189:f392fc9709a3	108	#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
AnnaBridge	189:f392fc9709a3	109	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7)
AnnaBridge	189:f392fc9709a3	110
AnnaBridge	189:f392fc9709a3	111	/**
AnnaBridge	189:f392fc9709a3	112	* @}
AnnaBridge	189:f392fc9709a3	113	*/
AnnaBridge	189:f392fc9709a3	114	#else
AnnaBridge	189:f392fc9709a3	115	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	116	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge	189:f392fc9709a3	117	* @{
AnnaBridge	189:f392fc9709a3	118	*/
AnnaBridge	189:f392fc9709a3	119	/**
AnnaBridge	189:f392fc9709a3	120	* @}
AnnaBridge	189:f392fc9709a3	121	*/
AnnaBridge	189:f392fc9709a3	122	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	189:f392fc9709a3	123	#endif /* DMAMUX1 */
AnnaBridge	189:f392fc9709a3	124
AnnaBridge	189:f392fc9709a3	125	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	126	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	127	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge	189:f392fc9709a3	128	* @{
AnnaBridge	189:f392fc9709a3	129	*/
AnnaBridge	189:f392fc9709a3	130	typedef struct
AnnaBridge	189:f392fc9709a3	131	{
AnnaBridge	189:f392fc9709a3	132	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge	189:f392fc9709a3	133	or as Source base address in case of memory to memory transfer direction.
AnnaBridge	189:f392fc9709a3	134
AnnaBridge	189:f392fc9709a3	135	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	189:f392fc9709a3	136
AnnaBridge	189:f392fc9709a3	137	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge	189:f392fc9709a3	138	or as Destination base address in case of memory to memory transfer direction.
AnnaBridge	189:f392fc9709a3	139
AnnaBridge	189:f392fc9709a3	140	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	189:f392fc9709a3	141
AnnaBridge	189:f392fc9709a3	142	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge	189:f392fc9709a3	143	from memory to memory or from peripheral to memory.
AnnaBridge	189:f392fc9709a3	144	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge	189:f392fc9709a3	145
AnnaBridge	189:f392fc9709a3	146	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge	189:f392fc9709a3	147
AnnaBridge	189:f392fc9709a3	148	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge	189:f392fc9709a3	149	This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge	189:f392fc9709a3	150	@note: The circular buffer mode cannot be used if the memory to memory
AnnaBridge	189:f392fc9709a3	151	data transfer direction is configured on the selected Channel
AnnaBridge	189:f392fc9709a3	152
AnnaBridge	189:f392fc9709a3	153	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge	189:f392fc9709a3	154
AnnaBridge	189:f392fc9709a3	155	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge	189:f392fc9709a3	156	is incremented or not.
AnnaBridge	189:f392fc9709a3	157	This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge	189:f392fc9709a3	158
AnnaBridge	189:f392fc9709a3	159	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge	189:f392fc9709a3	160
AnnaBridge	189:f392fc9709a3	161	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge	189:f392fc9709a3	162	is incremented or not.
AnnaBridge	189:f392fc9709a3	163	This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge	189:f392fc9709a3	164
AnnaBridge	189:f392fc9709a3	165	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge	189:f392fc9709a3	166
AnnaBridge	189:f392fc9709a3	167	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge	189:f392fc9709a3	168	in case of memory to memory transfer direction.
AnnaBridge	189:f392fc9709a3	169	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge	189:f392fc9709a3	170
AnnaBridge	189:f392fc9709a3	171	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge	189:f392fc9709a3	172
AnnaBridge	189:f392fc9709a3	173	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge	189:f392fc9709a3	174	in case of memory to memory transfer direction.
AnnaBridge	189:f392fc9709a3	175	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge	189:f392fc9709a3	176
AnnaBridge	189:f392fc9709a3	177	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge	189:f392fc9709a3	178
AnnaBridge	189:f392fc9709a3	179	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge	189:f392fc9709a3	180	The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge	189:f392fc9709a3	181	or MemorySize parameters depending in the transfer direction.
AnnaBridge	189:f392fc9709a3	182	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	189:f392fc9709a3	183
AnnaBridge	189:f392fc9709a3	184	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge	189:f392fc9709a3	185	#if defined(DMAMUX1)
AnnaBridge	189:f392fc9709a3	186
AnnaBridge	189:f392fc9709a3	187	uint32_t PeriphRequest; /*!< Specifies the peripheral request.
AnnaBridge	189:f392fc9709a3	188	This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
AnnaBridge	189:f392fc9709a3	189
AnnaBridge	189:f392fc9709a3	190	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
AnnaBridge	189:f392fc9709a3	191	#else
AnnaBridge	189:f392fc9709a3	192
AnnaBridge	189:f392fc9709a3	193	uint32_t PeriphRequest; /*!< Specifies the peripheral request.
AnnaBridge	189:f392fc9709a3	194	This parameter can be a value of @ref DMA_LL_EC_REQUEST
AnnaBridge	189:f392fc9709a3	195
AnnaBridge	189:f392fc9709a3	196	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
AnnaBridge	189:f392fc9709a3	197	#endif /* DMAMUX1 */
AnnaBridge	189:f392fc9709a3	198
AnnaBridge	189:f392fc9709a3	199	uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge	189:f392fc9709a3	200	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge	189:f392fc9709a3	201
AnnaBridge	189:f392fc9709a3	202	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
AnnaBridge	189:f392fc9709a3	203
AnnaBridge	189:f392fc9709a3	204	} LL_DMA_InitTypeDef;
AnnaBridge	189:f392fc9709a3	205	/**
AnnaBridge	189:f392fc9709a3	206	* @}
AnnaBridge	189:f392fc9709a3	207	*/
AnnaBridge	189:f392fc9709a3	208	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	189:f392fc9709a3	209
AnnaBridge	189:f392fc9709a3	210	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	211	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge	189:f392fc9709a3	212	* @{
AnnaBridge	189:f392fc9709a3	213	*/
AnnaBridge	189:f392fc9709a3	214	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	189:f392fc9709a3	215	* @brief Flags defines which can be used with LL_DMA_WriteReg function
AnnaBridge	189:f392fc9709a3	216	* @{
AnnaBridge	189:f392fc9709a3	217	*/
AnnaBridge	189:f392fc9709a3	218	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
AnnaBridge	189:f392fc9709a3	219	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	189:f392fc9709a3	220	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	189:f392fc9709a3	221	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	189:f392fc9709a3	222	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
AnnaBridge	189:f392fc9709a3	223	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	189:f392fc9709a3	224	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	189:f392fc9709a3	225	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	189:f392fc9709a3	226	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
AnnaBridge	189:f392fc9709a3	227	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	189:f392fc9709a3	228	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	189:f392fc9709a3	229	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	189:f392fc9709a3	230	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
AnnaBridge	189:f392fc9709a3	231	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	189:f392fc9709a3	232	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	189:f392fc9709a3	233	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	189:f392fc9709a3	234	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
AnnaBridge	189:f392fc9709a3	235	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	189:f392fc9709a3	236	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	189:f392fc9709a3	237	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	189:f392fc9709a3	238	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
AnnaBridge	189:f392fc9709a3	239	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	189:f392fc9709a3	240	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	189:f392fc9709a3	241	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	189:f392fc9709a3	242	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
AnnaBridge	189:f392fc9709a3	243	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	189:f392fc9709a3	244	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	189:f392fc9709a3	245	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	189:f392fc9709a3	246	/**
AnnaBridge	189:f392fc9709a3	247	* @}
AnnaBridge	189:f392fc9709a3	248	*/
AnnaBridge	189:f392fc9709a3	249
AnnaBridge	189:f392fc9709a3	250	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	189:f392fc9709a3	251	* @brief Flags defines which can be used with LL_DMA_ReadReg function
AnnaBridge	189:f392fc9709a3	252	* @{
AnnaBridge	189:f392fc9709a3	253	*/
AnnaBridge	189:f392fc9709a3	254	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
AnnaBridge	189:f392fc9709a3	255	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	189:f392fc9709a3	256	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	189:f392fc9709a3	257	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	189:f392fc9709a3	258	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
AnnaBridge	189:f392fc9709a3	259	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	189:f392fc9709a3	260	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	189:f392fc9709a3	261	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	189:f392fc9709a3	262	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
AnnaBridge	189:f392fc9709a3	263	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	189:f392fc9709a3	264	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	189:f392fc9709a3	265	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	189:f392fc9709a3	266	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
AnnaBridge	189:f392fc9709a3	267	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	189:f392fc9709a3	268	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	189:f392fc9709a3	269	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	189:f392fc9709a3	270	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
AnnaBridge	189:f392fc9709a3	271	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	189:f392fc9709a3	272	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	189:f392fc9709a3	273	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	189:f392fc9709a3	274	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
AnnaBridge	189:f392fc9709a3	275	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	189:f392fc9709a3	276	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	189:f392fc9709a3	277	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	189:f392fc9709a3	278	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
AnnaBridge	189:f392fc9709a3	279	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	189:f392fc9709a3	280	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	189:f392fc9709a3	281	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	189:f392fc9709a3	282	/**
AnnaBridge	189:f392fc9709a3	283	* @}
AnnaBridge	189:f392fc9709a3	284	*/
AnnaBridge	189:f392fc9709a3	285
AnnaBridge	189:f392fc9709a3	286	/** @defgroup DMA_LL_EC_IT IT Defines
AnnaBridge	189:f392fc9709a3	287	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
AnnaBridge	189:f392fc9709a3	288	* @{
AnnaBridge	189:f392fc9709a3	289	*/
AnnaBridge	189:f392fc9709a3	290	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
AnnaBridge	189:f392fc9709a3	291	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
AnnaBridge	189:f392fc9709a3	292	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
AnnaBridge	189:f392fc9709a3	293	/**
AnnaBridge	189:f392fc9709a3	294	* @}
AnnaBridge	189:f392fc9709a3	295	*/
AnnaBridge	189:f392fc9709a3	296
AnnaBridge	189:f392fc9709a3	297	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge	189:f392fc9709a3	298	* @{
AnnaBridge	189:f392fc9709a3	299	*/
AnnaBridge	189:f392fc9709a3	300	#define LL_DMA_CHANNEL_1 0x00000001U /!< DMA Channel 1 /
AnnaBridge	189:f392fc9709a3	301	#define LL_DMA_CHANNEL_2 0x00000002U /!< DMA Channel 2 /
AnnaBridge	189:f392fc9709a3	302	#define LL_DMA_CHANNEL_3 0x00000003U /!< DMA Channel 3 /
AnnaBridge	189:f392fc9709a3	303	#define LL_DMA_CHANNEL_4 0x00000004U /!< DMA Channel 4 /
AnnaBridge	189:f392fc9709a3	304	#define LL_DMA_CHANNEL_5 0x00000005U /!< DMA Channel 5 /
AnnaBridge	189:f392fc9709a3	305	#define LL_DMA_CHANNEL_6 0x00000006U /!< DMA Channel 6 /
AnnaBridge	189:f392fc9709a3	306	#define LL_DMA_CHANNEL_7 0x00000007U /!< DMA Channel 7 /
AnnaBridge	189:f392fc9709a3	307	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	308	#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
AnnaBridge	189:f392fc9709a3	309	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	189:f392fc9709a3	310	/**
AnnaBridge	189:f392fc9709a3	311	* @}
AnnaBridge	189:f392fc9709a3	312	*/
AnnaBridge	189:f392fc9709a3	313
AnnaBridge	189:f392fc9709a3	314	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
AnnaBridge	189:f392fc9709a3	315	* @{
AnnaBridge	189:f392fc9709a3	316	*/
AnnaBridge	189:f392fc9709a3	317	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
AnnaBridge	189:f392fc9709a3	318	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
AnnaBridge	189:f392fc9709a3	319	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
AnnaBridge	189:f392fc9709a3	320	/**
AnnaBridge	189:f392fc9709a3	321	* @}
AnnaBridge	189:f392fc9709a3	322	*/
AnnaBridge	189:f392fc9709a3	323
AnnaBridge	189:f392fc9709a3	324	/** @defgroup DMA_LL_EC_MODE Transfer mode
AnnaBridge	189:f392fc9709a3	325	* @{
AnnaBridge	189:f392fc9709a3	326	*/
AnnaBridge	189:f392fc9709a3	327	#define LL_DMA_MODE_NORMAL 0x00000000U /!< Normal Mode /
AnnaBridge	189:f392fc9709a3	328	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
AnnaBridge	189:f392fc9709a3	329	/**
AnnaBridge	189:f392fc9709a3	330	* @}
AnnaBridge	189:f392fc9709a3	331	*/
AnnaBridge	189:f392fc9709a3	332
AnnaBridge	189:f392fc9709a3	333	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
AnnaBridge	189:f392fc9709a3	334	* @{
AnnaBridge	189:f392fc9709a3	335	*/
AnnaBridge	189:f392fc9709a3	336	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
AnnaBridge	189:f392fc9709a3	337	#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /!< Peripheral increment mode Disable /
AnnaBridge	189:f392fc9709a3	338	/**
AnnaBridge	189:f392fc9709a3	339	* @}
AnnaBridge	189:f392fc9709a3	340	*/
AnnaBridge	189:f392fc9709a3	341
AnnaBridge	189:f392fc9709a3	342	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
AnnaBridge	189:f392fc9709a3	343	* @{
AnnaBridge	189:f392fc9709a3	344	*/
AnnaBridge	189:f392fc9709a3	345	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
AnnaBridge	189:f392fc9709a3	346	#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /!< Memory increment mode Disable /
AnnaBridge	189:f392fc9709a3	347	/**
AnnaBridge	189:f392fc9709a3	348	* @}
AnnaBridge	189:f392fc9709a3	349	*/
AnnaBridge	189:f392fc9709a3	350
AnnaBridge	189:f392fc9709a3	351	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
AnnaBridge	189:f392fc9709a3	352	* @{
AnnaBridge	189:f392fc9709a3	353	*/
AnnaBridge	189:f392fc9709a3	354	#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment : Byte /
AnnaBridge	189:f392fc9709a3	355	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
AnnaBridge	189:f392fc9709a3	356	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
AnnaBridge	189:f392fc9709a3	357	/**
AnnaBridge	189:f392fc9709a3	358	* @}
AnnaBridge	189:f392fc9709a3	359	*/
AnnaBridge	189:f392fc9709a3	360
AnnaBridge	189:f392fc9709a3	361	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
AnnaBridge	189:f392fc9709a3	362	* @{
AnnaBridge	189:f392fc9709a3	363	*/
AnnaBridge	189:f392fc9709a3	364	#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment : Byte /
AnnaBridge	189:f392fc9709a3	365	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
AnnaBridge	189:f392fc9709a3	366	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
AnnaBridge	189:f392fc9709a3	367	/**
AnnaBridge	189:f392fc9709a3	368	* @}
AnnaBridge	189:f392fc9709a3	369	*/
AnnaBridge	189:f392fc9709a3	370
AnnaBridge	189:f392fc9709a3	371	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
AnnaBridge	189:f392fc9709a3	372	* @{
AnnaBridge	189:f392fc9709a3	373	*/
AnnaBridge	189:f392fc9709a3	374	#define LL_DMA_PRIORITY_LOW 0x00000000U /!< Priority level : Low /
AnnaBridge	189:f392fc9709a3	375	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
AnnaBridge	189:f392fc9709a3	376	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
AnnaBridge	189:f392fc9709a3	377	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
AnnaBridge	189:f392fc9709a3	378	/**
AnnaBridge	189:f392fc9709a3	379	* @}
AnnaBridge	189:f392fc9709a3	380	*/
AnnaBridge	189:f392fc9709a3	381
AnnaBridge	189:f392fc9709a3	382	#if defined(DMAMUX1)
AnnaBridge	189:f392fc9709a3	383	/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
AnnaBridge	189:f392fc9709a3	384	* @{
AnnaBridge	189:f392fc9709a3	385	*/
AnnaBridge	189:f392fc9709a3	386	#define LL_DMAMUX_REQUEST_MEM2MEM 0U /!< Memory to memory transfer /
AnnaBridge	189:f392fc9709a3	387	#define LL_DMAMUX_REQUEST_GENERATOR0 1U /!< DMAMUX request generator 0 /
AnnaBridge	189:f392fc9709a3	388	#define LL_DMAMUX_REQUEST_GENERATOR1 2U /!< DMAMUX request generator 1 /
AnnaBridge	189:f392fc9709a3	389	#define LL_DMAMUX_REQUEST_GENERATOR2 3U /!< DMAMUX request generator 2 /
AnnaBridge	189:f392fc9709a3	390	#define LL_DMAMUX_REQUEST_GENERATOR3 4U /!< DMAMUX request generator 3 /
AnnaBridge	189:f392fc9709a3	391	#define LL_DMAMUX_REQUEST_ADC1 5U /!< DMAMUX ADC1 request /
AnnaBridge	189:f392fc9709a3	392	#define LL_DMAMUX_REQUEST_DAC1_CH1 6U /!< DMAMUX DAC1 CH1 request /
AnnaBridge	189:f392fc9709a3	393	#define LL_DMAMUX_REQUEST_DAC1_CH2 7U /!< DMAMUX DAC1 CH2 request /
AnnaBridge	189:f392fc9709a3	394	#define LL_DMAMUX_REQUEST_TIM6_UP 8U /!< DMAMUX TIM6 UP request /
AnnaBridge	189:f392fc9709a3	395	#define LL_DMAMUX_REQUEST_TIM7_UP 9U /!< DMAMUX TIM7 UP request /
AnnaBridge	189:f392fc9709a3	396	#define LL_DMAMUX_REQUEST_SPI1_RX 10U /!< DMAMUX SPI1 RX request /
AnnaBridge	189:f392fc9709a3	397	#define LL_DMAMUX_REQUEST_SPI1_TX 11U /!< DMAMUX SPI1 TX request /
AnnaBridge	189:f392fc9709a3	398	#define LL_DMAMUX_REQUEST_SPI2_RX 12U /!< DMAMUX SPI2 RX request /
AnnaBridge	189:f392fc9709a3	399	#define LL_DMAMUX_REQUEST_SPI2_TX 13U /!< DMAMUX SPI2 TX request /
AnnaBridge	189:f392fc9709a3	400	#define LL_DMAMUX_REQUEST_SPI3_RX 14U /!< DMAMUX SPI3 RX request /
AnnaBridge	189:f392fc9709a3	401	#define LL_DMAMUX_REQUEST_SPI3_TX 15U /!< DMAMUX SPI3 TX request /
AnnaBridge	189:f392fc9709a3	402	#define LL_DMAMUX_REQUEST_I2C1_RX 16U /!< DMAMUX I2C1 RX request /
AnnaBridge	189:f392fc9709a3	403	#define LL_DMAMUX_REQUEST_I2C1_TX 17U /!< DMAMUX I2C1 TX request /
AnnaBridge	189:f392fc9709a3	404	#define LL_DMAMUX_REQUEST_I2C2_RX 18U /!< DMAMUX I2C2 RX request /
AnnaBridge	189:f392fc9709a3	405	#define LL_DMAMUX_REQUEST_I2C2_TX 19U /!< DMAMUX I2C2 TX request /
AnnaBridge	189:f392fc9709a3	406	#define LL_DMAMUX_REQUEST_I2C3_RX 20U /!< DMAMUX I2C3 RX request /
AnnaBridge	189:f392fc9709a3	407	#define LL_DMAMUX_REQUEST_I2C3_TX 21U /!< DMAMUX I2C3 TX request /
AnnaBridge	189:f392fc9709a3	408	#define LL_DMAMUX_REQUEST_I2C4_RX 22U /!< DMAMUX I2C4 RX request /
AnnaBridge	189:f392fc9709a3	409	#define LL_DMAMUX_REQUEST_I2C4_TX 23U /!< DMAMUX I2C4 TX request /
AnnaBridge	189:f392fc9709a3	410	#define LL_DMAMUX_REQUEST_USART1_RX 24U /!< DMAMUX USART1 RX request /
AnnaBridge	189:f392fc9709a3	411	#define LL_DMAMUX_REQUEST_USART1_TX 25U /!< DMAMUX USART1 TX request /
AnnaBridge	189:f392fc9709a3	412	#define LL_DMAMUX_REQUEST_USART2_RX 26U /!< DMAMUX USART2 RX request /
AnnaBridge	189:f392fc9709a3	413	#define LL_DMAMUX_REQUEST_USART2_TX 27U /!< DMAMUX USART2 TX request /
AnnaBridge	189:f392fc9709a3	414	#define LL_DMAMUX_REQUEST_USART3_RX 28U /!< DMAMUX USART3 RX request /
AnnaBridge	189:f392fc9709a3	415	#define LL_DMAMUX_REQUEST_USART3_TX 29U /!< DMAMUX USART3 TX request /
AnnaBridge	189:f392fc9709a3	416	#define LL_DMAMUX_REQUEST_UART4_RX 30U /!< DMAMUX UART4 RX request /
AnnaBridge	189:f392fc9709a3	417	#define LL_DMAMUX_REQUEST_UART4_TX 31U /!< DMAMUX UART4 TX request /
AnnaBridge	189:f392fc9709a3	418	#define LL_DMAMUX_REQUEST_UART5_RX 32U /!< DMAMUX UART5 RX request /
AnnaBridge	189:f392fc9709a3	419	#define LL_DMAMUX_REQUEST_UART5_TX 33U /!< DMAMUX UART5 TX request /
AnnaBridge	189:f392fc9709a3	420	#define LL_DMAMUX_REQUEST_LPUART1_RX 34U /!< DMAMUX LPUART1 RX request /
AnnaBridge	189:f392fc9709a3	421	#define LL_DMAMUX_REQUEST_LPUART1_TX 35U /!< DMAMUX LPUART1 TX request /
AnnaBridge	189:f392fc9709a3	422	#define LL_DMAMUX_REQUEST_SAI1_A 36U /!< DMAMUX SAI1 A request /
AnnaBridge	189:f392fc9709a3	423	#define LL_DMAMUX_REQUEST_SAI1_B 37U /!< DMAMUX SAI1 B request /
AnnaBridge	189:f392fc9709a3	424	#define LL_DMAMUX_REQUEST_SAI2_A 38U /!< DMAMUX SAI2 A request /
AnnaBridge	189:f392fc9709a3	425	#define LL_DMAMUX_REQUEST_SAI2_B 39U /!< DMAMUX SAI2 B request /
AnnaBridge	189:f392fc9709a3	426	#define LL_DMAMUX_REQUEST_OSPI1 40U /!< DMAMUX OCTOSPI1 request /
AnnaBridge	189:f392fc9709a3	427	#define LL_DMAMUX_REQUEST_OSPI2 41U /!< DMAMUX OCTOSPI2 request /
AnnaBridge	189:f392fc9709a3	428	#define LL_DMAMUX_REQUEST_TIM1_CH1 42U /!< DMAMUX TIM1 CH1 request /
AnnaBridge	189:f392fc9709a3	429	#define LL_DMAMUX_REQUEST_TIM1_CH2 43U /!< DMAMUX TIM1 CH2 request /
AnnaBridge	189:f392fc9709a3	430	#define LL_DMAMUX_REQUEST_TIM1_CH3 44U /!< DMAMUX TIM1 CH3 request /
AnnaBridge	189:f392fc9709a3	431	#define LL_DMAMUX_REQUEST_TIM1_CH4 45U /!< DMAMUX TIM1 CH4 request /
AnnaBridge	189:f392fc9709a3	432	#define LL_DMAMUX_REQUEST_TIM1_UP 46U /!< DMAMUX TIM1 UP request /
AnnaBridge	189:f392fc9709a3	433	#define LL_DMAMUX_REQUEST_TIM1_TRIG 47U /!< DMAMUX TIM1 TRIG request /
AnnaBridge	189:f392fc9709a3	434	#define LL_DMAMUX_REQUEST_TIM1_COM 48U /!< DMAMUX TIM1 COM request /
AnnaBridge	189:f392fc9709a3	435	#define LL_DMAMUX_REQUEST_TIM8_CH1 49U /!< DMAMUX TIM8 CH1 request /
AnnaBridge	189:f392fc9709a3	436	#define LL_DMAMUX_REQUEST_TIM8_CH2 50U /!< DMAMUX TIM8 CH2 request /
AnnaBridge	189:f392fc9709a3	437	#define LL_DMAMUX_REQUEST_TIM8_CH3 51U /!< DMAMUX TIM8 CH3 request /
AnnaBridge	189:f392fc9709a3	438	#define LL_DMAMUX_REQUEST_TIM8_CH4 52U /!< DMAMUX TIM8 CH4 request /
AnnaBridge	189:f392fc9709a3	439	#define LL_DMAMUX_REQUEST_TIM8_UP 53U /!< DMAMUX TIM8 UP request /
AnnaBridge	189:f392fc9709a3	440	#define LL_DMAMUX_REQUEST_TIM8_TRIG 54U /!< DMAMUX TIM8 TRIG request /
AnnaBridge	189:f392fc9709a3	441	#define LL_DMAMUX_REQUEST_TIM8_COM 55U /!< DMAMUX TIM8 COM request /
AnnaBridge	189:f392fc9709a3	442	#define LL_DMAMUX_REQUEST_TIM2_CH1 56U /!< DMAMUX TIM2 CH1 request /
AnnaBridge	189:f392fc9709a3	443	#define LL_DMAMUX_REQUEST_TIM2_CH2 57U /!< DMAMUX TIM2 CH2 request /
AnnaBridge	189:f392fc9709a3	444	#define LL_DMAMUX_REQUEST_TIM2_CH3 58U /!< DMAMUX TIM2 CH3 request /
AnnaBridge	189:f392fc9709a3	445	#define LL_DMAMUX_REQUEST_TIM2_CH4 59U /!< DMAMUX TIM2 CH4 request /
AnnaBridge	189:f392fc9709a3	446	#define LL_DMAMUX_REQUEST_TIM2_UP 60U /!< DMAMUX TIM2 UP request /
AnnaBridge	189:f392fc9709a3	447	#define LL_DMAMUX_REQUEST_TIM3_CH1 61U /!< DMAMUX TIM3 CH1 request /
AnnaBridge	189:f392fc9709a3	448	#define LL_DMAMUX_REQUEST_TIM3_CH2 62U /!< DMAMUX TIM3 CH2 request /
AnnaBridge	189:f392fc9709a3	449	#define LL_DMAMUX_REQUEST_TIM3_CH3 63U /!< DMAMUX TIM3 CH3 request /
AnnaBridge	189:f392fc9709a3	450	#define LL_DMAMUX_REQUEST_TIM3_CH4 64U /!< DMAMUX TIM3 CH4 request /
AnnaBridge	189:f392fc9709a3	451	#define LL_DMAMUX_REQUEST_TIM3_UP 65U /!< DMAMUX TIM3 UP request /
AnnaBridge	189:f392fc9709a3	452	#define LL_DMAMUX_REQUEST_TIM3_TRIG 66U /!< DMAMUX TIM3 TRIG request /
AnnaBridge	189:f392fc9709a3	453	#define LL_DMAMUX_REQUEST_TIM4_CH1 67U /!< DMAMUX TIM4 CH1 request /
AnnaBridge	189:f392fc9709a3	454	#define LL_DMAMUX_REQUEST_TIM4_CH2 68U /!< DMAMUX TIM4 CH2 request /
AnnaBridge	189:f392fc9709a3	455	#define LL_DMAMUX_REQUEST_TIM4_CH3 69U /!< DMAMUX TIM4 CH3 request /
AnnaBridge	189:f392fc9709a3	456	#define LL_DMAMUX_REQUEST_TIM4_CH4 70U /!< DMAMUX TIM4 CH4 request /
AnnaBridge	189:f392fc9709a3	457	#define LL_DMAMUX_REQUEST_TIM4_UP 71U /!< DMAMUX TIM4 UP request /
AnnaBridge	189:f392fc9709a3	458	#define LL_DMAMUX_REQUEST_TIM5_CH1 72U /!< DMAMUX TIM5 CH1 request /
AnnaBridge	189:f392fc9709a3	459	#define LL_DMAMUX_REQUEST_TIM5_CH2 73U /!< DMAMUX TIM5 CH2 request /
AnnaBridge	189:f392fc9709a3	460	#define LL_DMAMUX_REQUEST_TIM5_CH3 74U /!< DMAMUX TIM5 CH3 request /
AnnaBridge	189:f392fc9709a3	461	#define LL_DMAMUX_REQUEST_TIM5_CH4 75U /!< DMAMUX TIM5 CH4 request /
AnnaBridge	189:f392fc9709a3	462	#define LL_DMAMUX_REQUEST_TIM5_UP 76U /!< DMAMUX TIM5 UP request /
AnnaBridge	189:f392fc9709a3	463	#define LL_DMAMUX_REQUEST_TIM5_TRIG 77U /!< DMAMUX TIM5 TRIG request /
AnnaBridge	189:f392fc9709a3	464	#define LL_DMAMUX_REQUEST_TIM15_CH1 78U /!< DMAMUX TIM15 CH1 request /
AnnaBridge	189:f392fc9709a3	465	#define LL_DMAMUX_REQUEST_TIM15_UP 79U /!< DMAMUX TIM15 UP request /
AnnaBridge	189:f392fc9709a3	466	#define LL_DMAMUX_REQUEST_TIM15_TRIG 80U /!< DMAMUX TIM15 TRIG request /
AnnaBridge	189:f392fc9709a3	467	#define LL_DMAMUX_REQUEST_TIM15_COM 81U /!< DMAMUX TIM15 COM request /
AnnaBridge	189:f392fc9709a3	468	#define LL_DMAMUX_REQUEST_TIM16_CH1 82U /!< DMAMUX TIM16 CH1 request /
AnnaBridge	189:f392fc9709a3	469	#define LL_DMAMUX_REQUEST_TIM16_UP 83U /!< DMAMUX TIM16 UP request /
AnnaBridge	189:f392fc9709a3	470	#define LL_DMAMUX_REQUEST_TIM17_CH1 84U /!< DMAMUX TIM17 CH1 request /
AnnaBridge	189:f392fc9709a3	471	#define LL_DMAMUX_REQUEST_TIM17_UP 85U /!< DMAMUX TIM17 UP request /
AnnaBridge	189:f392fc9709a3	472	#define LL_DMAMUX_REQUEST_DFSDM1_FLT0 86U /!< DMAMUX DFSDM1_FLT0 request /
AnnaBridge	189:f392fc9709a3	473	#define LL_DMAMUX_REQUEST_DFSDM1_FLT1 87U /!< DMAMUX DFSDM1_FLT1 request /
AnnaBridge	189:f392fc9709a3	474	#define LL_DMAMUX_REQUEST_DFSDM1_FLT2 88U /!< DMAMUX DFSDM1_FLT2 request /
AnnaBridge	189:f392fc9709a3	475	#define LL_DMAMUX_REQUEST_DFSDM1_FLT3 89U /!< DMAMUX DFSDM1_FLT3 request /
AnnaBridge	189:f392fc9709a3	476	#define LL_DMAMUX_REQUEST_DCMI 90U /!< DMAMUX DCMI request /
AnnaBridge	189:f392fc9709a3	477	#define LL_DMAMUX_REQUEST_AES_IN 91U /!< DMAMUX AES_IN request /
AnnaBridge	189:f392fc9709a3	478	#define LL_DMAMUX_REQUEST_AES_OUT 92U /!< DMAMUX AES_OUT request /
AnnaBridge	189:f392fc9709a3	479	#define LL_DMAMUX_REQUEST_HASH_IN 93U /!< DMAMUX HASH_IN request /
AnnaBridge	189:f392fc9709a3	480	/**
AnnaBridge	189:f392fc9709a3	481	* @}
AnnaBridge	189:f392fc9709a3	482	*/
AnnaBridge	189:f392fc9709a3	483	#else
AnnaBridge	189:f392fc9709a3	484	/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
AnnaBridge	189:f392fc9709a3	485	* @{
AnnaBridge	189:f392fc9709a3	486	*/
AnnaBridge	189:f392fc9709a3	487	#define LL_DMA_REQUEST_0 0x00000000U /!< DMA peripheral request 0 /
AnnaBridge	189:f392fc9709a3	488	#define LL_DMA_REQUEST_1 0x00000001U /!< DMA peripheral request 1 /
AnnaBridge	189:f392fc9709a3	489	#define LL_DMA_REQUEST_2 0x00000002U /!< DMA peripheral request 2 /
AnnaBridge	189:f392fc9709a3	490	#define LL_DMA_REQUEST_3 0x00000003U /!< DMA peripheral request 3 /
AnnaBridge	189:f392fc9709a3	491	#define LL_DMA_REQUEST_4 0x00000004U /!< DMA peripheral request 4 /
AnnaBridge	189:f392fc9709a3	492	#define LL_DMA_REQUEST_5 0x00000005U /!< DMA peripheral request 5 /
AnnaBridge	189:f392fc9709a3	493	#define LL_DMA_REQUEST_6 0x00000006U /!< DMA peripheral request 6 /
AnnaBridge	189:f392fc9709a3	494	#define LL_DMA_REQUEST_7 0x00000007U /!< DMA peripheral request 7 /
AnnaBridge	189:f392fc9709a3	495	/**
AnnaBridge	189:f392fc9709a3	496	* @}
AnnaBridge	189:f392fc9709a3	497	*/
AnnaBridge	189:f392fc9709a3	498	#endif /* DMAMUX1 */
AnnaBridge	189:f392fc9709a3	499
AnnaBridge	189:f392fc9709a3	500	/**
AnnaBridge	189:f392fc9709a3	501	* @}
AnnaBridge	189:f392fc9709a3	502	*/
AnnaBridge	189:f392fc9709a3	503
AnnaBridge	189:f392fc9709a3	504	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	505	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge	189:f392fc9709a3	506	* @{
AnnaBridge	189:f392fc9709a3	507	*/
AnnaBridge	189:f392fc9709a3	508
AnnaBridge	189:f392fc9709a3	509	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge	189:f392fc9709a3	510	* @{
AnnaBridge	189:f392fc9709a3	511	*/
AnnaBridge	189:f392fc9709a3	512	/**
AnnaBridge	189:f392fc9709a3	513	* @brief Write a value in DMA register
AnnaBridge	189:f392fc9709a3	514	* @param __INSTANCE__ DMA Instance
AnnaBridge	189:f392fc9709a3	515	* @param __REG__ Register to be written
AnnaBridge	189:f392fc9709a3	516	* @param __VALUE__ Value to be written in the register
AnnaBridge	189:f392fc9709a3	517	* @retval None
AnnaBridge	189:f392fc9709a3	518	*/
AnnaBridge	189:f392fc9709a3	519	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	189:f392fc9709a3	520
AnnaBridge	189:f392fc9709a3	521	/**
AnnaBridge	189:f392fc9709a3	522	* @brief Read a value in DMA register
AnnaBridge	189:f392fc9709a3	523	* @param __INSTANCE__ DMA Instance
AnnaBridge	189:f392fc9709a3	524	* @param __REG__ Register to be read
AnnaBridge	189:f392fc9709a3	525	* @retval Register value
AnnaBridge	189:f392fc9709a3	526	*/
AnnaBridge	189:f392fc9709a3	527	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	189:f392fc9709a3	528	/**
AnnaBridge	189:f392fc9709a3	529	* @}
AnnaBridge	189:f392fc9709a3	530	*/
AnnaBridge	189:f392fc9709a3	531
AnnaBridge	189:f392fc9709a3	532	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
AnnaBridge	189:f392fc9709a3	533	* @{
AnnaBridge	189:f392fc9709a3	534	*/
AnnaBridge	189:f392fc9709a3	535	/**
AnnaBridge	189:f392fc9709a3	536	* @brief Convert DMAx_Channely into DMAx
AnnaBridge	189:f392fc9709a3	537	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	189:f392fc9709a3	538	* @retval DMAx
AnnaBridge	189:f392fc9709a3	539	*/
AnnaBridge	189:f392fc9709a3	540	#if defined(DMA2)
AnnaBridge	189:f392fc9709a3	541	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
AnnaBridge	189:f392fc9709a3	542	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
AnnaBridge	189:f392fc9709a3	543	#else
AnnaBridge	189:f392fc9709a3	544	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
AnnaBridge	189:f392fc9709a3	545	#endif
AnnaBridge	189:f392fc9709a3	546
AnnaBridge	189:f392fc9709a3	547	/**
AnnaBridge	189:f392fc9709a3	548	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
AnnaBridge	189:f392fc9709a3	549	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	189:f392fc9709a3	550	* @retval LL_DMA_CHANNEL_y
AnnaBridge	189:f392fc9709a3	551	*/
AnnaBridge	189:f392fc9709a3	552	#if defined (DMA2)
AnnaBridge	189:f392fc9709a3	553	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge	189:f392fc9709a3	554	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	189:f392fc9709a3	555	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	189:f392fc9709a3	556	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	189:f392fc9709a3	557	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	189:f392fc9709a3	558	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	189:f392fc9709a3	559	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	189:f392fc9709a3	560	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	189:f392fc9709a3	561	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	189:f392fc9709a3	562	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	189:f392fc9709a3	563	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	189:f392fc9709a3	564	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	189:f392fc9709a3	565	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	189:f392fc9709a3	566	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	189:f392fc9709a3	567	LL_DMA_CHANNEL_7)
AnnaBridge	189:f392fc9709a3	568	#else
AnnaBridge	189:f392fc9709a3	569	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	189:f392fc9709a3	570	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	189:f392fc9709a3	571	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	189:f392fc9709a3	572	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	189:f392fc9709a3	573	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	189:f392fc9709a3	574	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	189:f392fc9709a3	575	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	189:f392fc9709a3	576	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	189:f392fc9709a3	577	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	189:f392fc9709a3	578	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	189:f392fc9709a3	579	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	189:f392fc9709a3	580	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	189:f392fc9709a3	581	LL_DMA_CHANNEL_7)
AnnaBridge	189:f392fc9709a3	582	#endif
AnnaBridge	189:f392fc9709a3	583	#else
AnnaBridge	189:f392fc9709a3	584	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	189:f392fc9709a3	585	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	189:f392fc9709a3	586	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	189:f392fc9709a3	587	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	189:f392fc9709a3	588	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	189:f392fc9709a3	589	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	189:f392fc9709a3	590	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	189:f392fc9709a3	591	LL_DMA_CHANNEL_7)
AnnaBridge	189:f392fc9709a3	592	#endif
AnnaBridge	189:f392fc9709a3	593
AnnaBridge	189:f392fc9709a3	594	/**
AnnaBridge	189:f392fc9709a3	595	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
AnnaBridge	189:f392fc9709a3	596	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	189:f392fc9709a3	597	* @param __CHANNEL__ LL_DMA_CHANNEL_y
AnnaBridge	189:f392fc9709a3	598	* @retval DMAx_Channely
AnnaBridge	189:f392fc9709a3	599	*/
AnnaBridge	189:f392fc9709a3	600	#if defined (DMA2)
AnnaBridge	189:f392fc9709a3	601	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge	189:f392fc9709a3	602	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	603	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	189:f392fc9709a3	604	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge	189:f392fc9709a3	605	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	189:f392fc9709a3	606	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge	189:f392fc9709a3	607	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	189:f392fc9709a3	608	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge	189:f392fc9709a3	609	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	189:f392fc9709a3	610	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge	189:f392fc9709a3	611	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	189:f392fc9709a3	612	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge	189:f392fc9709a3	613	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	189:f392fc9709a3	614	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
AnnaBridge	189:f392fc9709a3	615	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
AnnaBridge	189:f392fc9709a3	616	DMA2_Channel7)
AnnaBridge	189:f392fc9709a3	617	#else
AnnaBridge	189:f392fc9709a3	618	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	619	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	189:f392fc9709a3	620	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge	189:f392fc9709a3	621	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	189:f392fc9709a3	622	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge	189:f392fc9709a3	623	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	189:f392fc9709a3	624	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge	189:f392fc9709a3	625	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	189:f392fc9709a3	626	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge	189:f392fc9709a3	627	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	189:f392fc9709a3	628	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge	189:f392fc9709a3	629	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	189:f392fc9709a3	630	DMA1_Channel7)
AnnaBridge	189:f392fc9709a3	631	#endif
AnnaBridge	189:f392fc9709a3	632	#else
AnnaBridge	189:f392fc9709a3	633	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	634	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	189:f392fc9709a3	635	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	189:f392fc9709a3	636	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	189:f392fc9709a3	637	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	189:f392fc9709a3	638	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	189:f392fc9709a3	639	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	189:f392fc9709a3	640	DMA1_Channel7)
AnnaBridge	189:f392fc9709a3	641	#endif
AnnaBridge	189:f392fc9709a3	642
AnnaBridge	189:f392fc9709a3	643	/**
AnnaBridge	189:f392fc9709a3	644	* @}
AnnaBridge	189:f392fc9709a3	645	*/
AnnaBridge	189:f392fc9709a3	646
AnnaBridge	189:f392fc9709a3	647	/**
AnnaBridge	189:f392fc9709a3	648	* @}
AnnaBridge	189:f392fc9709a3	649	*/
AnnaBridge	189:f392fc9709a3	650
AnnaBridge	189:f392fc9709a3	651	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	652	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge	189:f392fc9709a3	653	* @{
AnnaBridge	189:f392fc9709a3	654	*/
AnnaBridge	189:f392fc9709a3	655
AnnaBridge	189:f392fc9709a3	656	/** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge	189:f392fc9709a3	657	* @{
AnnaBridge	189:f392fc9709a3	658	*/
AnnaBridge	189:f392fc9709a3	659	/**
AnnaBridge	189:f392fc9709a3	660	* @brief Enable DMA channel.
AnnaBridge	189:f392fc9709a3	661	* @rmtoll CCR EN LL_DMA_EnableChannel
AnnaBridge	189:f392fc9709a3	662	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	663	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	664	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	665	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	666	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	667	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	668	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	669	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	670	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	671	* @retval None
AnnaBridge	189:f392fc9709a3	672	*/
AnnaBridge	189:f392fc9709a3	673	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	674	{
AnnaBridge	189:f392fc9709a3	675	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	189:f392fc9709a3	676	}
AnnaBridge	189:f392fc9709a3	677
AnnaBridge	189:f392fc9709a3	678	/**
AnnaBridge	189:f392fc9709a3	679	* @brief Disable DMA channel.
AnnaBridge	189:f392fc9709a3	680	* @rmtoll CCR EN LL_DMA_DisableChannel
AnnaBridge	189:f392fc9709a3	681	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	682	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	683	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	684	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	685	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	686	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	687	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	688	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	689	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	690	* @retval None
AnnaBridge	189:f392fc9709a3	691	*/
AnnaBridge	189:f392fc9709a3	692	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	693	{
AnnaBridge	189:f392fc9709a3	694	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	189:f392fc9709a3	695	}
AnnaBridge	189:f392fc9709a3	696
AnnaBridge	189:f392fc9709a3	697	/**
AnnaBridge	189:f392fc9709a3	698	* @brief Check if DMA channel is enabled or disabled.
AnnaBridge	189:f392fc9709a3	699	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
AnnaBridge	189:f392fc9709a3	700	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	701	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	702	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	703	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	704	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	705	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	706	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	707	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	708	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	709	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	710	*/
AnnaBridge	189:f392fc9709a3	711	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	712	{
AnnaBridge	189:f392fc9709a3	713	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	189:f392fc9709a3	714	DMA_CCR_EN) == (DMA_CCR_EN));
AnnaBridge	189:f392fc9709a3	715	}
AnnaBridge	189:f392fc9709a3	716
AnnaBridge	189:f392fc9709a3	717	/**
AnnaBridge	189:f392fc9709a3	718	* @brief Configure all parameters link to DMA transfer.
AnnaBridge	189:f392fc9709a3	719	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
AnnaBridge	189:f392fc9709a3	720	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
AnnaBridge	189:f392fc9709a3	721	* CCR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge	189:f392fc9709a3	722	* CCR PINC LL_DMA_ConfigTransfer\n
AnnaBridge	189:f392fc9709a3	723	* CCR MINC LL_DMA_ConfigTransfer\n
AnnaBridge	189:f392fc9709a3	724	* CCR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	189:f392fc9709a3	725	* CCR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	189:f392fc9709a3	726	* CCR PL LL_DMA_ConfigTransfer
AnnaBridge	189:f392fc9709a3	727	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	728	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	729	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	730	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	731	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	732	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	733	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	734	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	735	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	736	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	189:f392fc9709a3	737	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	189:f392fc9709a3	738	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	189:f392fc9709a3	739	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	189:f392fc9709a3	740	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	189:f392fc9709a3	741	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	189:f392fc9709a3	742	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	189:f392fc9709a3	743	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	189:f392fc9709a3	744	* @retval None
AnnaBridge	189:f392fc9709a3	745	*/
AnnaBridge	189:f392fc9709a3	746	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	189:f392fc9709a3	747	{
AnnaBridge	189:f392fc9709a3	748	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	189:f392fc9709a3	749	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
AnnaBridge	189:f392fc9709a3	750	Configuration);
AnnaBridge	189:f392fc9709a3	751	}
AnnaBridge	189:f392fc9709a3	752
AnnaBridge	189:f392fc9709a3	753	/**
AnnaBridge	189:f392fc9709a3	754	* @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge	189:f392fc9709a3	755	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
AnnaBridge	189:f392fc9709a3	756	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
AnnaBridge	189:f392fc9709a3	757	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	758	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	759	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	760	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	761	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	762	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	763	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	764	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	765	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	766	* @param Direction This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	767	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	189:f392fc9709a3	768	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	189:f392fc9709a3	769	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	189:f392fc9709a3	770	* @retval None
AnnaBridge	189:f392fc9709a3	771	*/
AnnaBridge	189:f392fc9709a3	772	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
AnnaBridge	189:f392fc9709a3	773	{
AnnaBridge	189:f392fc9709a3	774	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	189:f392fc9709a3	775	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
AnnaBridge	189:f392fc9709a3	776	}
AnnaBridge	189:f392fc9709a3	777
AnnaBridge	189:f392fc9709a3	778	/**
AnnaBridge	189:f392fc9709a3	779	* @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge	189:f392fc9709a3	780	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
AnnaBridge	189:f392fc9709a3	781	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
AnnaBridge	189:f392fc9709a3	782	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	783	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	784	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	785	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	786	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	787	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	788	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	789	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	790	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	791	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	792	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	189:f392fc9709a3	793	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	189:f392fc9709a3	794	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	189:f392fc9709a3	795	*/
AnnaBridge	189:f392fc9709a3	796	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	797	{
AnnaBridge	189:f392fc9709a3	798	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	189:f392fc9709a3	799	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
AnnaBridge	189:f392fc9709a3	800	}
AnnaBridge	189:f392fc9709a3	801
AnnaBridge	189:f392fc9709a3	802	/**
AnnaBridge	189:f392fc9709a3	803	* @brief Set DMA mode circular or normal.
AnnaBridge	189:f392fc9709a3	804	* @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge	189:f392fc9709a3	805	* data transfer is configured on the selected Channel.
AnnaBridge	189:f392fc9709a3	806	* @rmtoll CCR CIRC LL_DMA_SetMode
AnnaBridge	189:f392fc9709a3	807	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	808	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	809	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	810	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	811	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	812	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	813	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	814	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	815	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	816	* @param Mode This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	817	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	189:f392fc9709a3	818	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	189:f392fc9709a3	819	* @retval None
AnnaBridge	189:f392fc9709a3	820	*/
AnnaBridge	189:f392fc9709a3	821	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
AnnaBridge	189:f392fc9709a3	822	{
AnnaBridge	189:f392fc9709a3	823	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
AnnaBridge	189:f392fc9709a3	824	Mode);
AnnaBridge	189:f392fc9709a3	825	}
AnnaBridge	189:f392fc9709a3	826
AnnaBridge	189:f392fc9709a3	827	/**
AnnaBridge	189:f392fc9709a3	828	* @brief Get DMA mode circular or normal.
AnnaBridge	189:f392fc9709a3	829	* @rmtoll CCR CIRC LL_DMA_GetMode
AnnaBridge	189:f392fc9709a3	830	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	831	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	832	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	833	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	834	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	835	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	836	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	837	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	838	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	839	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	840	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	189:f392fc9709a3	841	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	189:f392fc9709a3	842	*/
AnnaBridge	189:f392fc9709a3	843	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	844	{
AnnaBridge	189:f392fc9709a3	845	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	189:f392fc9709a3	846	DMA_CCR_CIRC));
AnnaBridge	189:f392fc9709a3	847	}
AnnaBridge	189:f392fc9709a3	848
AnnaBridge	189:f392fc9709a3	849	/**
AnnaBridge	189:f392fc9709a3	850	* @brief Set Peripheral increment mode.
AnnaBridge	189:f392fc9709a3	851	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
AnnaBridge	189:f392fc9709a3	852	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	853	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	854	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	855	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	856	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	857	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	858	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	859	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	860	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	861	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	862	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	189:f392fc9709a3	863	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	189:f392fc9709a3	864	* @retval None
AnnaBridge	189:f392fc9709a3	865	*/
AnnaBridge	189:f392fc9709a3	866	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
AnnaBridge	189:f392fc9709a3	867	{
AnnaBridge	189:f392fc9709a3	868	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
AnnaBridge	189:f392fc9709a3	869	PeriphOrM2MSrcIncMode);
AnnaBridge	189:f392fc9709a3	870	}
AnnaBridge	189:f392fc9709a3	871
AnnaBridge	189:f392fc9709a3	872	/**
AnnaBridge	189:f392fc9709a3	873	* @brief Get Peripheral increment mode.
AnnaBridge	189:f392fc9709a3	874	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
AnnaBridge	189:f392fc9709a3	875	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	876	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	877	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	878	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	879	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	880	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	881	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	882	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	883	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	884	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	885	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	189:f392fc9709a3	886	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	189:f392fc9709a3	887	*/
AnnaBridge	189:f392fc9709a3	888	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	889	{
AnnaBridge	189:f392fc9709a3	890	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	189:f392fc9709a3	891	DMA_CCR_PINC));
AnnaBridge	189:f392fc9709a3	892	}
AnnaBridge	189:f392fc9709a3	893
AnnaBridge	189:f392fc9709a3	894	/**
AnnaBridge	189:f392fc9709a3	895	* @brief Set Memory increment mode.
AnnaBridge	189:f392fc9709a3	896	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
AnnaBridge	189:f392fc9709a3	897	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	898	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	899	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	900	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	901	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	902	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	903	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	904	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	905	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	906	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	907	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	189:f392fc9709a3	908	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	189:f392fc9709a3	909	* @retval None
AnnaBridge	189:f392fc9709a3	910	*/
AnnaBridge	189:f392fc9709a3	911	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
AnnaBridge	189:f392fc9709a3	912	{
AnnaBridge	189:f392fc9709a3	913	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
AnnaBridge	189:f392fc9709a3	914	MemoryOrM2MDstIncMode);
AnnaBridge	189:f392fc9709a3	915	}
AnnaBridge	189:f392fc9709a3	916
AnnaBridge	189:f392fc9709a3	917	/**
AnnaBridge	189:f392fc9709a3	918	* @brief Get Memory increment mode.
AnnaBridge	189:f392fc9709a3	919	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
AnnaBridge	189:f392fc9709a3	920	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	921	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	922	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	923	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	924	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	925	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	926	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	927	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	928	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	929	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	930	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	189:f392fc9709a3	931	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	189:f392fc9709a3	932	*/
AnnaBridge	189:f392fc9709a3	933	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	934	{
AnnaBridge	189:f392fc9709a3	935	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	189:f392fc9709a3	936	DMA_CCR_MINC));
AnnaBridge	189:f392fc9709a3	937	}
AnnaBridge	189:f392fc9709a3	938
AnnaBridge	189:f392fc9709a3	939	/**
AnnaBridge	189:f392fc9709a3	940	* @brief Set Peripheral size.
AnnaBridge	189:f392fc9709a3	941	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
AnnaBridge	189:f392fc9709a3	942	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	943	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	944	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	945	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	946	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	947	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	948	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	949	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	950	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	951	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	952	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	189:f392fc9709a3	953	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	189:f392fc9709a3	954	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	189:f392fc9709a3	955	* @retval None
AnnaBridge	189:f392fc9709a3	956	*/
AnnaBridge	189:f392fc9709a3	957	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
AnnaBridge	189:f392fc9709a3	958	{
AnnaBridge	189:f392fc9709a3	959	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
AnnaBridge	189:f392fc9709a3	960	PeriphOrM2MSrcDataSize);
AnnaBridge	189:f392fc9709a3	961	}
AnnaBridge	189:f392fc9709a3	962
AnnaBridge	189:f392fc9709a3	963	/**
AnnaBridge	189:f392fc9709a3	964	* @brief Get Peripheral size.
AnnaBridge	189:f392fc9709a3	965	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
AnnaBridge	189:f392fc9709a3	966	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	967	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	968	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	969	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	970	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	971	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	972	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	973	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	974	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	975	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	976	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	189:f392fc9709a3	977	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	189:f392fc9709a3	978	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	189:f392fc9709a3	979	*/
AnnaBridge	189:f392fc9709a3	980	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	981	{
AnnaBridge	189:f392fc9709a3	982	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	189:f392fc9709a3	983	DMA_CCR_PSIZE));
AnnaBridge	189:f392fc9709a3	984	}
AnnaBridge	189:f392fc9709a3	985
AnnaBridge	189:f392fc9709a3	986	/**
AnnaBridge	189:f392fc9709a3	987	* @brief Set Memory size.
AnnaBridge	189:f392fc9709a3	988	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
AnnaBridge	189:f392fc9709a3	989	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	990	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	991	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	992	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	993	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	994	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	995	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	996	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	997	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	998	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	999	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	189:f392fc9709a3	1000	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	189:f392fc9709a3	1001	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	189:f392fc9709a3	1002	* @retval None
AnnaBridge	189:f392fc9709a3	1003	*/
AnnaBridge	189:f392fc9709a3	1004	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
AnnaBridge	189:f392fc9709a3	1005	{
AnnaBridge	189:f392fc9709a3	1006	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
AnnaBridge	189:f392fc9709a3	1007	MemoryOrM2MDstDataSize);
AnnaBridge	189:f392fc9709a3	1008	}
AnnaBridge	189:f392fc9709a3	1009
AnnaBridge	189:f392fc9709a3	1010	/**
AnnaBridge	189:f392fc9709a3	1011	* @brief Get Memory size.
AnnaBridge	189:f392fc9709a3	1012	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
AnnaBridge	189:f392fc9709a3	1013	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1014	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1015	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1016	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1017	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1018	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1019	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1020	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1021	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1022	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1023	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	189:f392fc9709a3	1024	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	189:f392fc9709a3	1025	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	189:f392fc9709a3	1026	*/
AnnaBridge	189:f392fc9709a3	1027	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	1028	{
AnnaBridge	189:f392fc9709a3	1029	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	189:f392fc9709a3	1030	DMA_CCR_MSIZE));
AnnaBridge	189:f392fc9709a3	1031	}
AnnaBridge	189:f392fc9709a3	1032
AnnaBridge	189:f392fc9709a3	1033	/**
AnnaBridge	189:f392fc9709a3	1034	* @brief Set Channel priority level.
AnnaBridge	189:f392fc9709a3	1035	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
AnnaBridge	189:f392fc9709a3	1036	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1037	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1038	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1039	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1040	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1041	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1042	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1043	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1044	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1045	* @param Priority This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1046	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	189:f392fc9709a3	1047	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	189:f392fc9709a3	1048	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	189:f392fc9709a3	1049	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	189:f392fc9709a3	1050	* @retval None
AnnaBridge	189:f392fc9709a3	1051	*/
AnnaBridge	189:f392fc9709a3	1052	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
AnnaBridge	189:f392fc9709a3	1053	{
AnnaBridge	189:f392fc9709a3	1054	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
AnnaBridge	189:f392fc9709a3	1055	Priority);
AnnaBridge	189:f392fc9709a3	1056	}
AnnaBridge	189:f392fc9709a3	1057
AnnaBridge	189:f392fc9709a3	1058	/**
AnnaBridge	189:f392fc9709a3	1059	* @brief Get Channel priority level.
AnnaBridge	189:f392fc9709a3	1060	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
AnnaBridge	189:f392fc9709a3	1061	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1062	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1063	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1064	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1065	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1066	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1067	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1068	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1069	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1070	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1071	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	189:f392fc9709a3	1072	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	189:f392fc9709a3	1073	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	189:f392fc9709a3	1074	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	189:f392fc9709a3	1075	*/
AnnaBridge	189:f392fc9709a3	1076	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	1077	{
AnnaBridge	189:f392fc9709a3	1078	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	189:f392fc9709a3	1079	DMA_CCR_PL));
AnnaBridge	189:f392fc9709a3	1080	}
AnnaBridge	189:f392fc9709a3	1081
AnnaBridge	189:f392fc9709a3	1082	/**
AnnaBridge	189:f392fc9709a3	1083	* @brief Set Number of data to transfer.
AnnaBridge	189:f392fc9709a3	1084	* @note This action has no effect if
AnnaBridge	189:f392fc9709a3	1085	* channel is enabled.
AnnaBridge	189:f392fc9709a3	1086	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
AnnaBridge	189:f392fc9709a3	1087	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1088	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1089	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1090	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1091	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1092	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1093	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1094	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1095	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1096	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	189:f392fc9709a3	1097	* @retval None
AnnaBridge	189:f392fc9709a3	1098	*/
AnnaBridge	189:f392fc9709a3	1099	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
AnnaBridge	189:f392fc9709a3	1100	{
AnnaBridge	189:f392fc9709a3	1101	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	189:f392fc9709a3	1102	DMA_CNDTR_NDT, NbData);
AnnaBridge	189:f392fc9709a3	1103	}
AnnaBridge	189:f392fc9709a3	1104
AnnaBridge	189:f392fc9709a3	1105	/**
AnnaBridge	189:f392fc9709a3	1106	* @brief Get Number of data to transfer.
AnnaBridge	189:f392fc9709a3	1107	* @note Once the channel is enabled, the return value indicate the
AnnaBridge	189:f392fc9709a3	1108	* remaining bytes to be transmitted.
AnnaBridge	189:f392fc9709a3	1109	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
AnnaBridge	189:f392fc9709a3	1110	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1111	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1112	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1113	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1114	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1115	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1116	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1117	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1118	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1119	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	189:f392fc9709a3	1120	*/
AnnaBridge	189:f392fc9709a3	1121	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	1122	{
AnnaBridge	189:f392fc9709a3	1123	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	189:f392fc9709a3	1124	DMA_CNDTR_NDT));
AnnaBridge	189:f392fc9709a3	1125	}
AnnaBridge	189:f392fc9709a3	1126
AnnaBridge	189:f392fc9709a3	1127	/**
AnnaBridge	189:f392fc9709a3	1128	* @brief Configure the Source and Destination addresses.
AnnaBridge	189:f392fc9709a3	1129	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	189:f392fc9709a3	1130	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
AnnaBridge	189:f392fc9709a3	1131	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
AnnaBridge	189:f392fc9709a3	1132	* CMAR MA LL_DMA_ConfigAddresses
AnnaBridge	189:f392fc9709a3	1133	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1134	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1135	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1136	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1137	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1138	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1139	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1140	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1141	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1142	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	189:f392fc9709a3	1143	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	189:f392fc9709a3	1144	* @param Direction This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1145	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	189:f392fc9709a3	1146	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	189:f392fc9709a3	1147	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	189:f392fc9709a3	1148	* @retval None
AnnaBridge	189:f392fc9709a3	1149	*/
AnnaBridge	189:f392fc9709a3	1150	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
AnnaBridge	189:f392fc9709a3	1151	uint32_t DstAddress, uint32_t Direction)
AnnaBridge	189:f392fc9709a3	1152	{
AnnaBridge	189:f392fc9709a3	1153	/* Direction Memory to Periph */
AnnaBridge	189:f392fc9709a3	1154	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge	189:f392fc9709a3	1155	{
AnnaBridge	189:f392fc9709a3	1156	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
AnnaBridge	189:f392fc9709a3	1157	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
AnnaBridge	189:f392fc9709a3	1158	}
AnnaBridge	189:f392fc9709a3	1159	/* Direction Periph to Memory and Memory to Memory */
AnnaBridge	189:f392fc9709a3	1160	else
AnnaBridge	189:f392fc9709a3	1161	{
AnnaBridge	189:f392fc9709a3	1162	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
AnnaBridge	189:f392fc9709a3	1163	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
AnnaBridge	189:f392fc9709a3	1164	}
AnnaBridge	189:f392fc9709a3	1165	}
AnnaBridge	189:f392fc9709a3	1166
AnnaBridge	189:f392fc9709a3	1167	/**
AnnaBridge	189:f392fc9709a3	1168	* @brief Set the Memory address.
AnnaBridge	189:f392fc9709a3	1169	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	189:f392fc9709a3	1170	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	189:f392fc9709a3	1171	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
AnnaBridge	189:f392fc9709a3	1172	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1173	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1174	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1175	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1176	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1177	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1178	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1179	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1180	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1181	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	189:f392fc9709a3	1182	* @retval None
AnnaBridge	189:f392fc9709a3	1183	*/
AnnaBridge	189:f392fc9709a3	1184	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	189:f392fc9709a3	1185	{
AnnaBridge	189:f392fc9709a3	1186	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge	189:f392fc9709a3	1187	}
AnnaBridge	189:f392fc9709a3	1188
AnnaBridge	189:f392fc9709a3	1189	/**
AnnaBridge	189:f392fc9709a3	1190	* @brief Set the Peripheral address.
AnnaBridge	189:f392fc9709a3	1191	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	189:f392fc9709a3	1192	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	189:f392fc9709a3	1193	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
AnnaBridge	189:f392fc9709a3	1194	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1195	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1196	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1197	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1198	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1199	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1200	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1201	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1202	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1203	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	189:f392fc9709a3	1204	* @retval None
AnnaBridge	189:f392fc9709a3	1205	*/
AnnaBridge	189:f392fc9709a3	1206	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
AnnaBridge	189:f392fc9709a3	1207	{
AnnaBridge	189:f392fc9709a3	1208	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
AnnaBridge	189:f392fc9709a3	1209	}
AnnaBridge	189:f392fc9709a3	1210
AnnaBridge	189:f392fc9709a3	1211	/**
AnnaBridge	189:f392fc9709a3	1212	* @brief Get Memory address.
AnnaBridge	189:f392fc9709a3	1213	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	189:f392fc9709a3	1214	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
AnnaBridge	189:f392fc9709a3	1215	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1216	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1217	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1218	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1219	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1220	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1221	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1222	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1223	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1224	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	189:f392fc9709a3	1225	*/
AnnaBridge	189:f392fc9709a3	1226	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	1227	{
AnnaBridge	189:f392fc9709a3	1228	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge	189:f392fc9709a3	1229	}
AnnaBridge	189:f392fc9709a3	1230
AnnaBridge	189:f392fc9709a3	1231	/**
AnnaBridge	189:f392fc9709a3	1232	* @brief Get Peripheral address.
AnnaBridge	189:f392fc9709a3	1233	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	189:f392fc9709a3	1234	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
AnnaBridge	189:f392fc9709a3	1235	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1236	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1237	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1238	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1239	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1240	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1241	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1242	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1243	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1244	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	189:f392fc9709a3	1245	*/
AnnaBridge	189:f392fc9709a3	1246	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	1247	{
AnnaBridge	189:f392fc9709a3	1248	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge	189:f392fc9709a3	1249	}
AnnaBridge	189:f392fc9709a3	1250
AnnaBridge	189:f392fc9709a3	1251	/**
AnnaBridge	189:f392fc9709a3	1252	* @brief Set the Memory to Memory Source address.
AnnaBridge	189:f392fc9709a3	1253	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	189:f392fc9709a3	1254	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	189:f392fc9709a3	1255	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge	189:f392fc9709a3	1256	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1257	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1258	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1259	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1260	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1261	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1262	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1263	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1264	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1265	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	189:f392fc9709a3	1266	* @retval None
AnnaBridge	189:f392fc9709a3	1267	*/
AnnaBridge	189:f392fc9709a3	1268	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	189:f392fc9709a3	1269	{
AnnaBridge	189:f392fc9709a3	1270	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
AnnaBridge	189:f392fc9709a3	1271	}
AnnaBridge	189:f392fc9709a3	1272
AnnaBridge	189:f392fc9709a3	1273	/**
AnnaBridge	189:f392fc9709a3	1274	* @brief Set the Memory to Memory Destination address.
AnnaBridge	189:f392fc9709a3	1275	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	189:f392fc9709a3	1276	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	189:f392fc9709a3	1277	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
AnnaBridge	189:f392fc9709a3	1278	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1279	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1280	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1281	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1282	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1283	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1284	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1285	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1286	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1287	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	189:f392fc9709a3	1288	* @retval None
AnnaBridge	189:f392fc9709a3	1289	*/
AnnaBridge	189:f392fc9709a3	1290	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	189:f392fc9709a3	1291	{
AnnaBridge	189:f392fc9709a3	1292	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge	189:f392fc9709a3	1293	}
AnnaBridge	189:f392fc9709a3	1294
AnnaBridge	189:f392fc9709a3	1295	/**
AnnaBridge	189:f392fc9709a3	1296	* @brief Get the Memory to Memory Source address.
AnnaBridge	189:f392fc9709a3	1297	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	189:f392fc9709a3	1298	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge	189:f392fc9709a3	1299	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1300	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1301	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1302	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1303	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1304	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1305	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1306	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1307	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1308	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	189:f392fc9709a3	1309	*/
AnnaBridge	189:f392fc9709a3	1310	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	1311	{
AnnaBridge	189:f392fc9709a3	1312	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge	189:f392fc9709a3	1313	}
AnnaBridge	189:f392fc9709a3	1314
AnnaBridge	189:f392fc9709a3	1315	/**
AnnaBridge	189:f392fc9709a3	1316	* @brief Get the Memory to Memory Destination address.
AnnaBridge	189:f392fc9709a3	1317	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	189:f392fc9709a3	1318	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
AnnaBridge	189:f392fc9709a3	1319	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1320	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1321	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1322	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1323	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1324	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1325	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1326	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1327	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1328	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	189:f392fc9709a3	1329	*/
AnnaBridge	189:f392fc9709a3	1330	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	1331	{
AnnaBridge	189:f392fc9709a3	1332	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge	189:f392fc9709a3	1333	}
AnnaBridge	189:f392fc9709a3	1334
AnnaBridge	189:f392fc9709a3	1335	#if defined(DMAMUX1)
AnnaBridge	189:f392fc9709a3	1336	/**
AnnaBridge	189:f392fc9709a3	1337	* @brief Set DMA request for DMA Channels on DMAMUX Channel x.
AnnaBridge	189:f392fc9709a3	1338	* @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
AnnaBridge	189:f392fc9709a3	1339	* DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
AnnaBridge	189:f392fc9709a3	1340	* @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
AnnaBridge	189:f392fc9709a3	1341	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1342	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1343	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1344	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1345	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1346	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1347	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1348	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1349	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1350	* @param Request This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1351	* @arg @ref LL_DMAMUX_REQUEST_MEM2MEM
AnnaBridge	189:f392fc9709a3	1352	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR0
AnnaBridge	189:f392fc9709a3	1353	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR1
AnnaBridge	189:f392fc9709a3	1354	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR2
AnnaBridge	189:f392fc9709a3	1355	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR3
AnnaBridge	189:f392fc9709a3	1356	* @arg @ref LL_DMAMUX_REQUEST_ADC1
AnnaBridge	189:f392fc9709a3	1357	* @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1
AnnaBridge	189:f392fc9709a3	1358	* @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2
AnnaBridge	189:f392fc9709a3	1359	* @arg @ref LL_DMAMUX_REQUEST_TIM6_UP
AnnaBridge	189:f392fc9709a3	1360	* @arg @ref LL_DMAMUX_REQUEST_TIM7_UP
AnnaBridge	189:f392fc9709a3	1361	* @arg @ref LL_DMAMUX_REQUEST_SPI1_RX
AnnaBridge	189:f392fc9709a3	1362	* @arg @ref LL_DMAMUX_REQUEST_SPI1_TX
AnnaBridge	189:f392fc9709a3	1363	* @arg @ref LL_DMAMUX_REQUEST_SPI2_RX
AnnaBridge	189:f392fc9709a3	1364	* @arg @ref LL_DMAMUX_REQUEST_SPI2_TX
AnnaBridge	189:f392fc9709a3	1365	* @arg @ref LL_DMAMUX_REQUEST_SPI3_RX
AnnaBridge	189:f392fc9709a3	1366	* @arg @ref LL_DMAMUX_REQUEST_SPI3_TX
AnnaBridge	189:f392fc9709a3	1367	* @arg @ref LL_DMAMUX_REQUEST_I2C1_RX
AnnaBridge	189:f392fc9709a3	1368	* @arg @ref LL_DMAMUX_REQUEST_I2C1_TX
AnnaBridge	189:f392fc9709a3	1369	* @arg @ref LL_DMAMUX_REQUEST_I2C2_RX
AnnaBridge	189:f392fc9709a3	1370	* @arg @ref LL_DMAMUX_REQUEST_I2C2_TX
AnnaBridge	189:f392fc9709a3	1371	* @arg @ref LL_DMAMUX_REQUEST_I2C3_RX
AnnaBridge	189:f392fc9709a3	1372	* @arg @ref LL_DMAMUX_REQUEST_I2C3_TX
AnnaBridge	189:f392fc9709a3	1373	* @arg @ref LL_DMAMUX_REQUEST_I2C4_RX
AnnaBridge	189:f392fc9709a3	1374	* @arg @ref LL_DMAMUX_REQUEST_I2C4_TX
AnnaBridge	189:f392fc9709a3	1375	* @arg @ref LL_DMAMUX_REQUEST_USART1_RX
AnnaBridge	189:f392fc9709a3	1376	* @arg @ref LL_DMAMUX_REQUEST_USART1_TX
AnnaBridge	189:f392fc9709a3	1377	* @arg @ref LL_DMAMUX_REQUEST_USART2_RX
AnnaBridge	189:f392fc9709a3	1378	* @arg @ref LL_DMAMUX_REQUEST_USART2_TX
AnnaBridge	189:f392fc9709a3	1379	* @arg @ref LL_DMAMUX_REQUEST_USART3_RX
AnnaBridge	189:f392fc9709a3	1380	* @arg @ref LL_DMAMUX_REQUEST_USART3_TX
AnnaBridge	189:f392fc9709a3	1381	* @arg @ref LL_DMAMUX_REQUEST_UART4_RX
AnnaBridge	189:f392fc9709a3	1382	* @arg @ref LL_DMAMUX_REQUEST_UART4_TX
AnnaBridge	189:f392fc9709a3	1383	* @arg @ref LL_DMAMUX_REQUEST_UART5_RX
AnnaBridge	189:f392fc9709a3	1384	* @arg @ref LL_DMAMUX_REQUEST_UART5_TX
AnnaBridge	189:f392fc9709a3	1385	* @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX
AnnaBridge	189:f392fc9709a3	1386	* @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX
AnnaBridge	189:f392fc9709a3	1387	* @arg @ref LL_DMAMUX_REQUEST_SAI1_A
AnnaBridge	189:f392fc9709a3	1388	* @arg @ref LL_DMAMUX_REQUEST_SAI1_B
AnnaBridge	189:f392fc9709a3	1389	* @arg @ref LL_DMAMUX_REQUEST_SAI2_A
AnnaBridge	189:f392fc9709a3	1390	* @arg @ref LL_DMAMUX_REQUEST_SAI2_B
AnnaBridge	189:f392fc9709a3	1391	* @arg @ref LL_DMAMUX_REQUEST_OSPI1
AnnaBridge	189:f392fc9709a3	1392	* @arg @ref LL_DMAMUX_REQUEST_OSPI2
AnnaBridge	189:f392fc9709a3	1393	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1
AnnaBridge	189:f392fc9709a3	1394	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2
AnnaBridge	189:f392fc9709a3	1395	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3
AnnaBridge	189:f392fc9709a3	1396	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4
AnnaBridge	189:f392fc9709a3	1397	* @arg @ref LL_DMAMUX_REQUEST_TIM1_UP
AnnaBridge	189:f392fc9709a3	1398	* @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG
AnnaBridge	189:f392fc9709a3	1399	* @arg @ref LL_DMAMUX_REQUEST_TIM1_COM
AnnaBridge	189:f392fc9709a3	1400	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1
AnnaBridge	189:f392fc9709a3	1401	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2
AnnaBridge	189:f392fc9709a3	1402	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3
AnnaBridge	189:f392fc9709a3	1403	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4
AnnaBridge	189:f392fc9709a3	1404	* @arg @ref LL_DMAMUX_REQUEST_TIM8_UP
AnnaBridge	189:f392fc9709a3	1405	* @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG
AnnaBridge	189:f392fc9709a3	1406	* @arg @ref LL_DMAMUX_REQUEST_TIM8_COM
AnnaBridge	189:f392fc9709a3	1407	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1
AnnaBridge	189:f392fc9709a3	1408	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2
AnnaBridge	189:f392fc9709a3	1409	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3
AnnaBridge	189:f392fc9709a3	1410	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4
AnnaBridge	189:f392fc9709a3	1411	* @arg @ref LL_DMAMUX_REQUEST_TIM2_UP
AnnaBridge	189:f392fc9709a3	1412	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1
AnnaBridge	189:f392fc9709a3	1413	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2
AnnaBridge	189:f392fc9709a3	1414	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3
AnnaBridge	189:f392fc9709a3	1415	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4
AnnaBridge	189:f392fc9709a3	1416	* @arg @ref LL_DMAMUX_REQUEST_TIM3_UP
AnnaBridge	189:f392fc9709a3	1417	* @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG
AnnaBridge	189:f392fc9709a3	1418	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1
AnnaBridge	189:f392fc9709a3	1419	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2
AnnaBridge	189:f392fc9709a3	1420	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3
AnnaBridge	189:f392fc9709a3	1421	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4
AnnaBridge	189:f392fc9709a3	1422	* @arg @ref LL_DMAMUX_REQUEST_TIM4_UP
AnnaBridge	189:f392fc9709a3	1423	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1
AnnaBridge	189:f392fc9709a3	1424	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2
AnnaBridge	189:f392fc9709a3	1425	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3
AnnaBridge	189:f392fc9709a3	1426	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4
AnnaBridge	189:f392fc9709a3	1427	* @arg @ref LL_DMAMUX_REQUEST_TIM5_UP
AnnaBridge	189:f392fc9709a3	1428	* @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG
AnnaBridge	189:f392fc9709a3	1429	* @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1
AnnaBridge	189:f392fc9709a3	1430	* @arg @ref LL_DMAMUX_REQUEST_TIM15_UP
AnnaBridge	189:f392fc9709a3	1431	* @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG
AnnaBridge	189:f392fc9709a3	1432	* @arg @ref LL_DMAMUX_REQUEST_TIM15_COM
AnnaBridge	189:f392fc9709a3	1433	* @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1
AnnaBridge	189:f392fc9709a3	1434	* @arg @ref LL_DMAMUX_REQUEST_TIM16_UP
AnnaBridge	189:f392fc9709a3	1435	* @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1
AnnaBridge	189:f392fc9709a3	1436	* @arg @ref LL_DMAMUX_REQUEST_TIM17_UP
AnnaBridge	189:f392fc9709a3	1437	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0
AnnaBridge	189:f392fc9709a3	1438	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1
AnnaBridge	189:f392fc9709a3	1439	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2
AnnaBridge	189:f392fc9709a3	1440	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3
AnnaBridge	189:f392fc9709a3	1441	* @arg @ref LL_DMAMUX_REQUEST_DCMI
AnnaBridge	189:f392fc9709a3	1442	* @arg @ref LL_DMAMUX_REQUEST_AES_IN
AnnaBridge	189:f392fc9709a3	1443	* @arg @ref LL_DMAMUX_REQUEST_AES_OUT
AnnaBridge	189:f392fc9709a3	1444	* @arg @ref LL_DMAMUX_REQUEST_HASH_IN
AnnaBridge	189:f392fc9709a3	1445	* @retval None
AnnaBridge	189:f392fc9709a3	1446	*/
AnnaBridge	189:f392fc9709a3	1447	__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
AnnaBridge	189:f392fc9709a3	1448	{
AnnaBridge	189:f392fc9709a3	1449	MODIFY_REG(((DMAMUX_Channel_TypeDef)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
AnnaBridge	189:f392fc9709a3	1450	}
AnnaBridge	189:f392fc9709a3	1451
AnnaBridge	189:f392fc9709a3	1452	/**
AnnaBridge	189:f392fc9709a3	1453	* @brief Get DMA request for DMA Channels on DMAMUX Channel x.
AnnaBridge	189:f392fc9709a3	1454	* @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
AnnaBridge	189:f392fc9709a3	1455	* DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
AnnaBridge	189:f392fc9709a3	1456	* @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
AnnaBridge	189:f392fc9709a3	1457	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1458	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1459	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1460	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1461	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1462	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1463	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1464	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1465	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1466	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1467	* @arg @ref LL_DMAMUX_REQUEST_MEM2MEM
AnnaBridge	189:f392fc9709a3	1468	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR0
AnnaBridge	189:f392fc9709a3	1469	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR1
AnnaBridge	189:f392fc9709a3	1470	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR2
AnnaBridge	189:f392fc9709a3	1471	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR3
AnnaBridge	189:f392fc9709a3	1472	* @arg @ref LL_DMAMUX_REQUEST_ADC1
AnnaBridge	189:f392fc9709a3	1473	* @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1
AnnaBridge	189:f392fc9709a3	1474	* @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2
AnnaBridge	189:f392fc9709a3	1475	* @arg @ref LL_DMAMUX_REQUEST_TIM6_UP
AnnaBridge	189:f392fc9709a3	1476	* @arg @ref LL_DMAMUX_REQUEST_TIM7_UP
AnnaBridge	189:f392fc9709a3	1477	* @arg @ref LL_DMAMUX_REQUEST_SPI1_RX
AnnaBridge	189:f392fc9709a3	1478	* @arg @ref LL_DMAMUX_REQUEST_SPI1_TX
AnnaBridge	189:f392fc9709a3	1479	* @arg @ref LL_DMAMUX_REQUEST_SPI2_RX
AnnaBridge	189:f392fc9709a3	1480	* @arg @ref LL_DMAMUX_REQUEST_SPI2_TX
AnnaBridge	189:f392fc9709a3	1481	* @arg @ref LL_DMAMUX_REQUEST_SPI3_RX
AnnaBridge	189:f392fc9709a3	1482	* @arg @ref LL_DMAMUX_REQUEST_SPI3_TX
AnnaBridge	189:f392fc9709a3	1483	* @arg @ref LL_DMAMUX_REQUEST_I2C1_RX
AnnaBridge	189:f392fc9709a3	1484	* @arg @ref LL_DMAMUX_REQUEST_I2C1_TX
AnnaBridge	189:f392fc9709a3	1485	* @arg @ref LL_DMAMUX_REQUEST_I2C2_RX
AnnaBridge	189:f392fc9709a3	1486	* @arg @ref LL_DMAMUX_REQUEST_I2C2_TX
AnnaBridge	189:f392fc9709a3	1487	* @arg @ref LL_DMAMUX_REQUEST_I2C3_RX
AnnaBridge	189:f392fc9709a3	1488	* @arg @ref LL_DMAMUX_REQUEST_I2C3_TX
AnnaBridge	189:f392fc9709a3	1489	* @arg @ref LL_DMAMUX_REQUEST_I2C4_RX
AnnaBridge	189:f392fc9709a3	1490	* @arg @ref LL_DMAMUX_REQUEST_I2C4_TX
AnnaBridge	189:f392fc9709a3	1491	* @arg @ref LL_DMAMUX_REQUEST_USART1_RX
AnnaBridge	189:f392fc9709a3	1492	* @arg @ref LL_DMAMUX_REQUEST_USART1_TX
AnnaBridge	189:f392fc9709a3	1493	* @arg @ref LL_DMAMUX_REQUEST_USART2_RX
AnnaBridge	189:f392fc9709a3	1494	* @arg @ref LL_DMAMUX_REQUEST_USART2_TX
AnnaBridge	189:f392fc9709a3	1495	* @arg @ref LL_DMAMUX_REQUEST_USART3_RX
AnnaBridge	189:f392fc9709a3	1496	* @arg @ref LL_DMAMUX_REQUEST_USART3_TX
AnnaBridge	189:f392fc9709a3	1497	* @arg @ref LL_DMAMUX_REQUEST_UART4_RX
AnnaBridge	189:f392fc9709a3	1498	* @arg @ref LL_DMAMUX_REQUEST_UART4_TX
AnnaBridge	189:f392fc9709a3	1499	* @arg @ref LL_DMAMUX_REQUEST_UART5_RX
AnnaBridge	189:f392fc9709a3	1500	* @arg @ref LL_DMAMUX_REQUEST_UART5_TX
AnnaBridge	189:f392fc9709a3	1501	* @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX
AnnaBridge	189:f392fc9709a3	1502	* @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX
AnnaBridge	189:f392fc9709a3	1503	* @arg @ref LL_DMAMUX_REQUEST_SAI1_A
AnnaBridge	189:f392fc9709a3	1504	* @arg @ref LL_DMAMUX_REQUEST_SAI1_B
AnnaBridge	189:f392fc9709a3	1505	* @arg @ref LL_DMAMUX_REQUEST_SAI2_A
AnnaBridge	189:f392fc9709a3	1506	* @arg @ref LL_DMAMUX_REQUEST_SAI2_B
AnnaBridge	189:f392fc9709a3	1507	* @arg @ref LL_DMAMUX_REQUEST_OSPI1
AnnaBridge	189:f392fc9709a3	1508	* @arg @ref LL_DMAMUX_REQUEST_OSPI2
AnnaBridge	189:f392fc9709a3	1509	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1
AnnaBridge	189:f392fc9709a3	1510	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2
AnnaBridge	189:f392fc9709a3	1511	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3
AnnaBridge	189:f392fc9709a3	1512	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4
AnnaBridge	189:f392fc9709a3	1513	* @arg @ref LL_DMAMUX_REQUEST_TIM1_UP
AnnaBridge	189:f392fc9709a3	1514	* @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG
AnnaBridge	189:f392fc9709a3	1515	* @arg @ref LL_DMAMUX_REQUEST_TIM1_COM
AnnaBridge	189:f392fc9709a3	1516	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1
AnnaBridge	189:f392fc9709a3	1517	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2
AnnaBridge	189:f392fc9709a3	1518	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3
AnnaBridge	189:f392fc9709a3	1519	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4
AnnaBridge	189:f392fc9709a3	1520	* @arg @ref LL_DMAMUX_REQUEST_TIM8_UP
AnnaBridge	189:f392fc9709a3	1521	* @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG
AnnaBridge	189:f392fc9709a3	1522	* @arg @ref LL_DMAMUX_REQUEST_TIM8_COM
AnnaBridge	189:f392fc9709a3	1523	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1
AnnaBridge	189:f392fc9709a3	1524	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2
AnnaBridge	189:f392fc9709a3	1525	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3
AnnaBridge	189:f392fc9709a3	1526	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4
AnnaBridge	189:f392fc9709a3	1527	* @arg @ref LL_DMAMUX_REQUEST_TIM2_UP
AnnaBridge	189:f392fc9709a3	1528	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1
AnnaBridge	189:f392fc9709a3	1529	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2
AnnaBridge	189:f392fc9709a3	1530	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3
AnnaBridge	189:f392fc9709a3	1531	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4
AnnaBridge	189:f392fc9709a3	1532	* @arg @ref LL_DMAMUX_REQUEST_TIM3_UP
AnnaBridge	189:f392fc9709a3	1533	* @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG
AnnaBridge	189:f392fc9709a3	1534	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1
AnnaBridge	189:f392fc9709a3	1535	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2
AnnaBridge	189:f392fc9709a3	1536	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3
AnnaBridge	189:f392fc9709a3	1537	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4
AnnaBridge	189:f392fc9709a3	1538	* @arg @ref LL_DMAMUX_REQUEST_TIM4_UP
AnnaBridge	189:f392fc9709a3	1539	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1
AnnaBridge	189:f392fc9709a3	1540	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2
AnnaBridge	189:f392fc9709a3	1541	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3
AnnaBridge	189:f392fc9709a3	1542	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4
AnnaBridge	189:f392fc9709a3	1543	* @arg @ref LL_DMAMUX_REQUEST_TIM5_UP
AnnaBridge	189:f392fc9709a3	1544	* @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG
AnnaBridge	189:f392fc9709a3	1545	* @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1
AnnaBridge	189:f392fc9709a3	1546	* @arg @ref LL_DMAMUX_REQUEST_TIM15_UP
AnnaBridge	189:f392fc9709a3	1547	* @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG
AnnaBridge	189:f392fc9709a3	1548	* @arg @ref LL_DMAMUX_REQUEST_TIM15_COM
AnnaBridge	189:f392fc9709a3	1549	* @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1
AnnaBridge	189:f392fc9709a3	1550	* @arg @ref LL_DMAMUX_REQUEST_TIM16_UP
AnnaBridge	189:f392fc9709a3	1551	* @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1
AnnaBridge	189:f392fc9709a3	1552	* @arg @ref LL_DMAMUX_REQUEST_TIM17_UP
AnnaBridge	189:f392fc9709a3	1553	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0
AnnaBridge	189:f392fc9709a3	1554	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1
AnnaBridge	189:f392fc9709a3	1555	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2
AnnaBridge	189:f392fc9709a3	1556	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3
AnnaBridge	189:f392fc9709a3	1557	* @arg @ref LL_DMAMUX_REQUEST_DCMI
AnnaBridge	189:f392fc9709a3	1558	* @arg @ref LL_DMAMUX_REQUEST_AES_IN
AnnaBridge	189:f392fc9709a3	1559	* @arg @ref LL_DMAMUX_REQUEST_AES_OUT
AnnaBridge	189:f392fc9709a3	1560	* @arg @ref LL_DMAMUX_REQUEST_HASH_IN
AnnaBridge	189:f392fc9709a3	1561	*/
AnnaBridge	189:f392fc9709a3	1562	__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	1563	{
AnnaBridge	189:f392fc9709a3	1564	return (READ_BIT(((DMAMUX_Channel_TypeDef)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
AnnaBridge	189:f392fc9709a3	1565	}
AnnaBridge	189:f392fc9709a3	1566	#else
AnnaBridge	189:f392fc9709a3	1567	/**
AnnaBridge	189:f392fc9709a3	1568	* @brief Set DMA request for DMA instance on Channel x.
AnnaBridge	189:f392fc9709a3	1569	* @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
AnnaBridge	189:f392fc9709a3	1570	* @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
AnnaBridge	189:f392fc9709a3	1571	* CSELR C2S LL_DMA_SetPeriphRequest\n
AnnaBridge	189:f392fc9709a3	1572	* CSELR C3S LL_DMA_SetPeriphRequest\n
AnnaBridge	189:f392fc9709a3	1573	* CSELR C4S LL_DMA_SetPeriphRequest\n
AnnaBridge	189:f392fc9709a3	1574	* CSELR C5S LL_DMA_SetPeriphRequest\n
AnnaBridge	189:f392fc9709a3	1575	* CSELR C6S LL_DMA_SetPeriphRequest\n
AnnaBridge	189:f392fc9709a3	1576	* CSELR C7S LL_DMA_SetPeriphRequest
AnnaBridge	189:f392fc9709a3	1577	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1578	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1579	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1580	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1581	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1582	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1583	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1584	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1585	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1586	* @param PeriphRequest This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1587	* @arg @ref LL_DMA_REQUEST_0
AnnaBridge	189:f392fc9709a3	1588	* @arg @ref LL_DMA_REQUEST_1
AnnaBridge	189:f392fc9709a3	1589	* @arg @ref LL_DMA_REQUEST_2
AnnaBridge	189:f392fc9709a3	1590	* @arg @ref LL_DMA_REQUEST_3
AnnaBridge	189:f392fc9709a3	1591	* @arg @ref LL_DMA_REQUEST_4
AnnaBridge	189:f392fc9709a3	1592	* @arg @ref LL_DMA_REQUEST_5
AnnaBridge	189:f392fc9709a3	1593	* @arg @ref LL_DMA_REQUEST_6
AnnaBridge	189:f392fc9709a3	1594	* @arg @ref LL_DMA_REQUEST_7
AnnaBridge	189:f392fc9709a3	1595	* @retval None
AnnaBridge	189:f392fc9709a3	1596	*/
AnnaBridge	189:f392fc9709a3	1597	__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
AnnaBridge	189:f392fc9709a3	1598	{
AnnaBridge	189:f392fc9709a3	1599	MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
AnnaBridge	189:f392fc9709a3	1600	DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
AnnaBridge	189:f392fc9709a3	1601	}
AnnaBridge	189:f392fc9709a3	1602
AnnaBridge	189:f392fc9709a3	1603	/**
AnnaBridge	189:f392fc9709a3	1604	* @brief Get DMA request for DMA instance on Channel x.
AnnaBridge	189:f392fc9709a3	1605	* @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
AnnaBridge	189:f392fc9709a3	1606	* CSELR C2S LL_DMA_GetPeriphRequest\n
AnnaBridge	189:f392fc9709a3	1607	* CSELR C3S LL_DMA_GetPeriphRequest\n
AnnaBridge	189:f392fc9709a3	1608	* CSELR C4S LL_DMA_GetPeriphRequest\n
AnnaBridge	189:f392fc9709a3	1609	* CSELR C5S LL_DMA_GetPeriphRequest\n
AnnaBridge	189:f392fc9709a3	1610	* CSELR C6S LL_DMA_GetPeriphRequest\n
AnnaBridge	189:f392fc9709a3	1611	* CSELR C7S LL_DMA_GetPeriphRequest
AnnaBridge	189:f392fc9709a3	1612	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1613	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1614	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1615	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	1616	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	1617	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	1618	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	1619	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	1620	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	1621	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1622	* @arg @ref LL_DMA_REQUEST_0
AnnaBridge	189:f392fc9709a3	1623	* @arg @ref LL_DMA_REQUEST_1
AnnaBridge	189:f392fc9709a3	1624	* @arg @ref LL_DMA_REQUEST_2
AnnaBridge	189:f392fc9709a3	1625	* @arg @ref LL_DMA_REQUEST_3
AnnaBridge	189:f392fc9709a3	1626	* @arg @ref LL_DMA_REQUEST_4
AnnaBridge	189:f392fc9709a3	1627	* @arg @ref LL_DMA_REQUEST_5
AnnaBridge	189:f392fc9709a3	1628	* @arg @ref LL_DMA_REQUEST_6
AnnaBridge	189:f392fc9709a3	1629	* @arg @ref LL_DMA_REQUEST_7
AnnaBridge	189:f392fc9709a3	1630	*/
AnnaBridge	189:f392fc9709a3	1631	__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	1632	{
AnnaBridge	189:f392fc9709a3	1633	return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
AnnaBridge	189:f392fc9709a3	1634	DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
AnnaBridge	189:f392fc9709a3	1635	}
AnnaBridge	189:f392fc9709a3	1636	#endif /* DMAMUX1 */
AnnaBridge	189:f392fc9709a3	1637
AnnaBridge	189:f392fc9709a3	1638	/**
AnnaBridge	189:f392fc9709a3	1639	* @}
AnnaBridge	189:f392fc9709a3	1640	*/
AnnaBridge	189:f392fc9709a3	1641
AnnaBridge	189:f392fc9709a3	1642	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	189:f392fc9709a3	1643	* @{
AnnaBridge	189:f392fc9709a3	1644	*/
AnnaBridge	189:f392fc9709a3	1645
AnnaBridge	189:f392fc9709a3	1646	/**
AnnaBridge	189:f392fc9709a3	1647	* @brief Get Channel 1 global interrupt flag.
AnnaBridge	189:f392fc9709a3	1648	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
AnnaBridge	189:f392fc9709a3	1649	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1650	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1651	*/
AnnaBridge	189:f392fc9709a3	1652	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1653	{
AnnaBridge	189:f392fc9709a3	1654	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
AnnaBridge	189:f392fc9709a3	1655	}
AnnaBridge	189:f392fc9709a3	1656
AnnaBridge	189:f392fc9709a3	1657	/**
AnnaBridge	189:f392fc9709a3	1658	* @brief Get Channel 2 global interrupt flag.
AnnaBridge	189:f392fc9709a3	1659	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
AnnaBridge	189:f392fc9709a3	1660	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1661	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1662	*/
AnnaBridge	189:f392fc9709a3	1663	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1664	{
AnnaBridge	189:f392fc9709a3	1665	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
AnnaBridge	189:f392fc9709a3	1666	}
AnnaBridge	189:f392fc9709a3	1667
AnnaBridge	189:f392fc9709a3	1668	/**
AnnaBridge	189:f392fc9709a3	1669	* @brief Get Channel 3 global interrupt flag.
AnnaBridge	189:f392fc9709a3	1670	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
AnnaBridge	189:f392fc9709a3	1671	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1672	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1673	*/
AnnaBridge	189:f392fc9709a3	1674	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1675	{
AnnaBridge	189:f392fc9709a3	1676	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
AnnaBridge	189:f392fc9709a3	1677	}
AnnaBridge	189:f392fc9709a3	1678
AnnaBridge	189:f392fc9709a3	1679	/**
AnnaBridge	189:f392fc9709a3	1680	* @brief Get Channel 4 global interrupt flag.
AnnaBridge	189:f392fc9709a3	1681	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
AnnaBridge	189:f392fc9709a3	1682	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1683	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1684	*/
AnnaBridge	189:f392fc9709a3	1685	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1686	{
AnnaBridge	189:f392fc9709a3	1687	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
AnnaBridge	189:f392fc9709a3	1688	}
AnnaBridge	189:f392fc9709a3	1689
AnnaBridge	189:f392fc9709a3	1690	/**
AnnaBridge	189:f392fc9709a3	1691	* @brief Get Channel 5 global interrupt flag.
AnnaBridge	189:f392fc9709a3	1692	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
AnnaBridge	189:f392fc9709a3	1693	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1694	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1695	*/
AnnaBridge	189:f392fc9709a3	1696	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1697	{
AnnaBridge	189:f392fc9709a3	1698	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
AnnaBridge	189:f392fc9709a3	1699	}
AnnaBridge	189:f392fc9709a3	1700
AnnaBridge	189:f392fc9709a3	1701	/**
AnnaBridge	189:f392fc9709a3	1702	* @brief Get Channel 6 global interrupt flag.
AnnaBridge	189:f392fc9709a3	1703	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
AnnaBridge	189:f392fc9709a3	1704	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1705	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1706	*/
AnnaBridge	189:f392fc9709a3	1707	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1708	{
AnnaBridge	189:f392fc9709a3	1709	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
AnnaBridge	189:f392fc9709a3	1710	}
AnnaBridge	189:f392fc9709a3	1711
AnnaBridge	189:f392fc9709a3	1712	/**
AnnaBridge	189:f392fc9709a3	1713	* @brief Get Channel 7 global interrupt flag.
AnnaBridge	189:f392fc9709a3	1714	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
AnnaBridge	189:f392fc9709a3	1715	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1716	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1717	*/
AnnaBridge	189:f392fc9709a3	1718	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1719	{
AnnaBridge	189:f392fc9709a3	1720	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
AnnaBridge	189:f392fc9709a3	1721	}
AnnaBridge	189:f392fc9709a3	1722
AnnaBridge	189:f392fc9709a3	1723	/**
AnnaBridge	189:f392fc9709a3	1724	* @brief Get Channel 1 transfer complete flag.
AnnaBridge	189:f392fc9709a3	1725	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge	189:f392fc9709a3	1726	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1727	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1728	*/
AnnaBridge	189:f392fc9709a3	1729	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1730	{
AnnaBridge	189:f392fc9709a3	1731	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
AnnaBridge	189:f392fc9709a3	1732	}
AnnaBridge	189:f392fc9709a3	1733
AnnaBridge	189:f392fc9709a3	1734	/**
AnnaBridge	189:f392fc9709a3	1735	* @brief Get Channel 2 transfer complete flag.
AnnaBridge	189:f392fc9709a3	1736	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge	189:f392fc9709a3	1737	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1738	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1739	*/
AnnaBridge	189:f392fc9709a3	1740	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1741	{
AnnaBridge	189:f392fc9709a3	1742	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
AnnaBridge	189:f392fc9709a3	1743	}
AnnaBridge	189:f392fc9709a3	1744
AnnaBridge	189:f392fc9709a3	1745	/**
AnnaBridge	189:f392fc9709a3	1746	* @brief Get Channel 3 transfer complete flag.
AnnaBridge	189:f392fc9709a3	1747	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge	189:f392fc9709a3	1748	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1749	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1750	*/
AnnaBridge	189:f392fc9709a3	1751	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1752	{
AnnaBridge	189:f392fc9709a3	1753	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
AnnaBridge	189:f392fc9709a3	1754	}
AnnaBridge	189:f392fc9709a3	1755
AnnaBridge	189:f392fc9709a3	1756	/**
AnnaBridge	189:f392fc9709a3	1757	* @brief Get Channel 4 transfer complete flag.
AnnaBridge	189:f392fc9709a3	1758	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge	189:f392fc9709a3	1759	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1760	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1761	*/
AnnaBridge	189:f392fc9709a3	1762	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1763	{
AnnaBridge	189:f392fc9709a3	1764	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
AnnaBridge	189:f392fc9709a3	1765	}
AnnaBridge	189:f392fc9709a3	1766
AnnaBridge	189:f392fc9709a3	1767	/**
AnnaBridge	189:f392fc9709a3	1768	* @brief Get Channel 5 transfer complete flag.
AnnaBridge	189:f392fc9709a3	1769	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
AnnaBridge	189:f392fc9709a3	1770	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1771	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1772	*/
AnnaBridge	189:f392fc9709a3	1773	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1774	{
AnnaBridge	189:f392fc9709a3	1775	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
AnnaBridge	189:f392fc9709a3	1776	}
AnnaBridge	189:f392fc9709a3	1777
AnnaBridge	189:f392fc9709a3	1778	/**
AnnaBridge	189:f392fc9709a3	1779	* @brief Get Channel 6 transfer complete flag.
AnnaBridge	189:f392fc9709a3	1780	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge	189:f392fc9709a3	1781	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1782	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1783	*/
AnnaBridge	189:f392fc9709a3	1784	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1785	{
AnnaBridge	189:f392fc9709a3	1786	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
AnnaBridge	189:f392fc9709a3	1787	}
AnnaBridge	189:f392fc9709a3	1788
AnnaBridge	189:f392fc9709a3	1789	/**
AnnaBridge	189:f392fc9709a3	1790	* @brief Get Channel 7 transfer complete flag.
AnnaBridge	189:f392fc9709a3	1791	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge	189:f392fc9709a3	1792	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1793	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1794	*/
AnnaBridge	189:f392fc9709a3	1795	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1796	{
AnnaBridge	189:f392fc9709a3	1797	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
AnnaBridge	189:f392fc9709a3	1798	}
AnnaBridge	189:f392fc9709a3	1799
AnnaBridge	189:f392fc9709a3	1800	/**
AnnaBridge	189:f392fc9709a3	1801	* @brief Get Channel 1 half transfer flag.
AnnaBridge	189:f392fc9709a3	1802	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge	189:f392fc9709a3	1803	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1804	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1805	*/
AnnaBridge	189:f392fc9709a3	1806	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1807	{
AnnaBridge	189:f392fc9709a3	1808	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
AnnaBridge	189:f392fc9709a3	1809	}
AnnaBridge	189:f392fc9709a3	1810
AnnaBridge	189:f392fc9709a3	1811	/**
AnnaBridge	189:f392fc9709a3	1812	* @brief Get Channel 2 half transfer flag.
AnnaBridge	189:f392fc9709a3	1813	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge	189:f392fc9709a3	1814	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1815	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1816	*/
AnnaBridge	189:f392fc9709a3	1817	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1818	{
AnnaBridge	189:f392fc9709a3	1819	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
AnnaBridge	189:f392fc9709a3	1820	}
AnnaBridge	189:f392fc9709a3	1821
AnnaBridge	189:f392fc9709a3	1822	/**
AnnaBridge	189:f392fc9709a3	1823	* @brief Get Channel 3 half transfer flag.
AnnaBridge	189:f392fc9709a3	1824	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge	189:f392fc9709a3	1825	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1826	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1827	*/
AnnaBridge	189:f392fc9709a3	1828	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1829	{
AnnaBridge	189:f392fc9709a3	1830	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
AnnaBridge	189:f392fc9709a3	1831	}
AnnaBridge	189:f392fc9709a3	1832
AnnaBridge	189:f392fc9709a3	1833	/**
AnnaBridge	189:f392fc9709a3	1834	* @brief Get Channel 4 half transfer flag.
AnnaBridge	189:f392fc9709a3	1835	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge	189:f392fc9709a3	1836	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1837	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1838	*/
AnnaBridge	189:f392fc9709a3	1839	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1840	{
AnnaBridge	189:f392fc9709a3	1841	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
AnnaBridge	189:f392fc9709a3	1842	}
AnnaBridge	189:f392fc9709a3	1843
AnnaBridge	189:f392fc9709a3	1844	/**
AnnaBridge	189:f392fc9709a3	1845	* @brief Get Channel 5 half transfer flag.
AnnaBridge	189:f392fc9709a3	1846	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
AnnaBridge	189:f392fc9709a3	1847	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1848	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1849	*/
AnnaBridge	189:f392fc9709a3	1850	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1851	{
AnnaBridge	189:f392fc9709a3	1852	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
AnnaBridge	189:f392fc9709a3	1853	}
AnnaBridge	189:f392fc9709a3	1854
AnnaBridge	189:f392fc9709a3	1855	/**
AnnaBridge	189:f392fc9709a3	1856	* @brief Get Channel 6 half transfer flag.
AnnaBridge	189:f392fc9709a3	1857	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge	189:f392fc9709a3	1858	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1859	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1860	*/
AnnaBridge	189:f392fc9709a3	1861	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1862	{
AnnaBridge	189:f392fc9709a3	1863	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
AnnaBridge	189:f392fc9709a3	1864	}
AnnaBridge	189:f392fc9709a3	1865
AnnaBridge	189:f392fc9709a3	1866	/**
AnnaBridge	189:f392fc9709a3	1867	* @brief Get Channel 7 half transfer flag.
AnnaBridge	189:f392fc9709a3	1868	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge	189:f392fc9709a3	1869	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1870	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1871	*/
AnnaBridge	189:f392fc9709a3	1872	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1873	{
AnnaBridge	189:f392fc9709a3	1874	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
AnnaBridge	189:f392fc9709a3	1875	}
AnnaBridge	189:f392fc9709a3	1876
AnnaBridge	189:f392fc9709a3	1877	/**
AnnaBridge	189:f392fc9709a3	1878	* @brief Get Channel 1 transfer error flag.
AnnaBridge	189:f392fc9709a3	1879	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge	189:f392fc9709a3	1880	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1881	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1882	*/
AnnaBridge	189:f392fc9709a3	1883	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1884	{
AnnaBridge	189:f392fc9709a3	1885	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
AnnaBridge	189:f392fc9709a3	1886	}
AnnaBridge	189:f392fc9709a3	1887
AnnaBridge	189:f392fc9709a3	1888	/**
AnnaBridge	189:f392fc9709a3	1889	* @brief Get Channel 2 transfer error flag.
AnnaBridge	189:f392fc9709a3	1890	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge	189:f392fc9709a3	1891	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1892	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1893	*/
AnnaBridge	189:f392fc9709a3	1894	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1895	{
AnnaBridge	189:f392fc9709a3	1896	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
AnnaBridge	189:f392fc9709a3	1897	}
AnnaBridge	189:f392fc9709a3	1898
AnnaBridge	189:f392fc9709a3	1899	/**
AnnaBridge	189:f392fc9709a3	1900	* @brief Get Channel 3 transfer error flag.
AnnaBridge	189:f392fc9709a3	1901	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge	189:f392fc9709a3	1902	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1903	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1904	*/
AnnaBridge	189:f392fc9709a3	1905	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1906	{
AnnaBridge	189:f392fc9709a3	1907	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
AnnaBridge	189:f392fc9709a3	1908	}
AnnaBridge	189:f392fc9709a3	1909
AnnaBridge	189:f392fc9709a3	1910	/**
AnnaBridge	189:f392fc9709a3	1911	* @brief Get Channel 4 transfer error flag.
AnnaBridge	189:f392fc9709a3	1912	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge	189:f392fc9709a3	1913	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1914	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1915	*/
AnnaBridge	189:f392fc9709a3	1916	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1917	{
AnnaBridge	189:f392fc9709a3	1918	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
AnnaBridge	189:f392fc9709a3	1919	}
AnnaBridge	189:f392fc9709a3	1920
AnnaBridge	189:f392fc9709a3	1921	/**
AnnaBridge	189:f392fc9709a3	1922	* @brief Get Channel 5 transfer error flag.
AnnaBridge	189:f392fc9709a3	1923	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
AnnaBridge	189:f392fc9709a3	1924	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1925	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1926	*/
AnnaBridge	189:f392fc9709a3	1927	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1928	{
AnnaBridge	189:f392fc9709a3	1929	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
AnnaBridge	189:f392fc9709a3	1930	}
AnnaBridge	189:f392fc9709a3	1931
AnnaBridge	189:f392fc9709a3	1932	/**
AnnaBridge	189:f392fc9709a3	1933	* @brief Get Channel 6 transfer error flag.
AnnaBridge	189:f392fc9709a3	1934	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge	189:f392fc9709a3	1935	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1936	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1937	*/
AnnaBridge	189:f392fc9709a3	1938	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1939	{
AnnaBridge	189:f392fc9709a3	1940	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
AnnaBridge	189:f392fc9709a3	1941	}
AnnaBridge	189:f392fc9709a3	1942
AnnaBridge	189:f392fc9709a3	1943	/**
AnnaBridge	189:f392fc9709a3	1944	* @brief Get Channel 7 transfer error flag.
AnnaBridge	189:f392fc9709a3	1945	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge	189:f392fc9709a3	1946	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1947	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1948	*/
AnnaBridge	189:f392fc9709a3	1949	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1950	{
AnnaBridge	189:f392fc9709a3	1951	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
AnnaBridge	189:f392fc9709a3	1952	}
AnnaBridge	189:f392fc9709a3	1953
AnnaBridge	189:f392fc9709a3	1954	/**
AnnaBridge	189:f392fc9709a3	1955	* @brief Clear Channel 1 global interrupt flag.
AnnaBridge	189:f392fc9709a3	1956	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
AnnaBridge	189:f392fc9709a3	1957	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1958	* @retval None
AnnaBridge	189:f392fc9709a3	1959	*/
AnnaBridge	189:f392fc9709a3	1960	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1961	{
AnnaBridge	189:f392fc9709a3	1962	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
AnnaBridge	189:f392fc9709a3	1963	}
AnnaBridge	189:f392fc9709a3	1964
AnnaBridge	189:f392fc9709a3	1965	/**
AnnaBridge	189:f392fc9709a3	1966	* @brief Clear Channel 2 global interrupt flag.
AnnaBridge	189:f392fc9709a3	1967	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
AnnaBridge	189:f392fc9709a3	1968	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1969	* @retval None
AnnaBridge	189:f392fc9709a3	1970	*/
AnnaBridge	189:f392fc9709a3	1971	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1972	{
AnnaBridge	189:f392fc9709a3	1973	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
AnnaBridge	189:f392fc9709a3	1974	}
AnnaBridge	189:f392fc9709a3	1975
AnnaBridge	189:f392fc9709a3	1976	/**
AnnaBridge	189:f392fc9709a3	1977	* @brief Clear Channel 3 global interrupt flag.
AnnaBridge	189:f392fc9709a3	1978	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
AnnaBridge	189:f392fc9709a3	1979	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1980	* @retval None
AnnaBridge	189:f392fc9709a3	1981	*/
AnnaBridge	189:f392fc9709a3	1982	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1983	{
AnnaBridge	189:f392fc9709a3	1984	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
AnnaBridge	189:f392fc9709a3	1985	}
AnnaBridge	189:f392fc9709a3	1986
AnnaBridge	189:f392fc9709a3	1987	/**
AnnaBridge	189:f392fc9709a3	1988	* @brief Clear Channel 4 global interrupt flag.
AnnaBridge	189:f392fc9709a3	1989	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
AnnaBridge	189:f392fc9709a3	1990	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	1991	* @retval None
AnnaBridge	189:f392fc9709a3	1992	*/
AnnaBridge	189:f392fc9709a3	1993	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	1994	{
AnnaBridge	189:f392fc9709a3	1995	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
AnnaBridge	189:f392fc9709a3	1996	}
AnnaBridge	189:f392fc9709a3	1997
AnnaBridge	189:f392fc9709a3	1998	/**
AnnaBridge	189:f392fc9709a3	1999	* @brief Clear Channel 5 global interrupt flag.
AnnaBridge	189:f392fc9709a3	2000	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
AnnaBridge	189:f392fc9709a3	2001	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2002	* @retval None
AnnaBridge	189:f392fc9709a3	2003	*/
AnnaBridge	189:f392fc9709a3	2004	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2005	{
AnnaBridge	189:f392fc9709a3	2006	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
AnnaBridge	189:f392fc9709a3	2007	}
AnnaBridge	189:f392fc9709a3	2008
AnnaBridge	189:f392fc9709a3	2009	/**
AnnaBridge	189:f392fc9709a3	2010	* @brief Clear Channel 6 global interrupt flag.
AnnaBridge	189:f392fc9709a3	2011	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
AnnaBridge	189:f392fc9709a3	2012	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2013	* @retval None
AnnaBridge	189:f392fc9709a3	2014	*/
AnnaBridge	189:f392fc9709a3	2015	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2016	{
AnnaBridge	189:f392fc9709a3	2017	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
AnnaBridge	189:f392fc9709a3	2018	}
AnnaBridge	189:f392fc9709a3	2019
AnnaBridge	189:f392fc9709a3	2020	/**
AnnaBridge	189:f392fc9709a3	2021	* @brief Clear Channel 7 global interrupt flag.
AnnaBridge	189:f392fc9709a3	2022	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
AnnaBridge	189:f392fc9709a3	2023	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2024	* @retval None
AnnaBridge	189:f392fc9709a3	2025	*/
AnnaBridge	189:f392fc9709a3	2026	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2027	{
AnnaBridge	189:f392fc9709a3	2028	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
AnnaBridge	189:f392fc9709a3	2029	}
AnnaBridge	189:f392fc9709a3	2030
AnnaBridge	189:f392fc9709a3	2031	/**
AnnaBridge	189:f392fc9709a3	2032	* @brief Clear Channel 1 transfer complete flag.
AnnaBridge	189:f392fc9709a3	2033	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge	189:f392fc9709a3	2034	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2035	* @retval None
AnnaBridge	189:f392fc9709a3	2036	*/
AnnaBridge	189:f392fc9709a3	2037	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2038	{
AnnaBridge	189:f392fc9709a3	2039	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
AnnaBridge	189:f392fc9709a3	2040	}
AnnaBridge	189:f392fc9709a3	2041
AnnaBridge	189:f392fc9709a3	2042	/**
AnnaBridge	189:f392fc9709a3	2043	* @brief Clear Channel 2 transfer complete flag.
AnnaBridge	189:f392fc9709a3	2044	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge	189:f392fc9709a3	2045	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2046	* @retval None
AnnaBridge	189:f392fc9709a3	2047	*/
AnnaBridge	189:f392fc9709a3	2048	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2049	{
AnnaBridge	189:f392fc9709a3	2050	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
AnnaBridge	189:f392fc9709a3	2051	}
AnnaBridge	189:f392fc9709a3	2052
AnnaBridge	189:f392fc9709a3	2053	/**
AnnaBridge	189:f392fc9709a3	2054	* @brief Clear Channel 3 transfer complete flag.
AnnaBridge	189:f392fc9709a3	2055	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge	189:f392fc9709a3	2056	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2057	* @retval None
AnnaBridge	189:f392fc9709a3	2058	*/
AnnaBridge	189:f392fc9709a3	2059	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2060	{
AnnaBridge	189:f392fc9709a3	2061	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
AnnaBridge	189:f392fc9709a3	2062	}
AnnaBridge	189:f392fc9709a3	2063
AnnaBridge	189:f392fc9709a3	2064	/**
AnnaBridge	189:f392fc9709a3	2065	* @brief Clear Channel 4 transfer complete flag.
AnnaBridge	189:f392fc9709a3	2066	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge	189:f392fc9709a3	2067	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2068	* @retval None
AnnaBridge	189:f392fc9709a3	2069	*/
AnnaBridge	189:f392fc9709a3	2070	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2071	{
AnnaBridge	189:f392fc9709a3	2072	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
AnnaBridge	189:f392fc9709a3	2073	}
AnnaBridge	189:f392fc9709a3	2074
AnnaBridge	189:f392fc9709a3	2075	/**
AnnaBridge	189:f392fc9709a3	2076	* @brief Clear Channel 5 transfer complete flag.
AnnaBridge	189:f392fc9709a3	2077	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge	189:f392fc9709a3	2078	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2079	* @retval None
AnnaBridge	189:f392fc9709a3	2080	*/
AnnaBridge	189:f392fc9709a3	2081	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2082	{
AnnaBridge	189:f392fc9709a3	2083	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
AnnaBridge	189:f392fc9709a3	2084	}
AnnaBridge	189:f392fc9709a3	2085
AnnaBridge	189:f392fc9709a3	2086	/**
AnnaBridge	189:f392fc9709a3	2087	* @brief Clear Channel 6 transfer complete flag.
AnnaBridge	189:f392fc9709a3	2088	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge	189:f392fc9709a3	2089	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2090	* @retval None
AnnaBridge	189:f392fc9709a3	2091	*/
AnnaBridge	189:f392fc9709a3	2092	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2093	{
AnnaBridge	189:f392fc9709a3	2094	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
AnnaBridge	189:f392fc9709a3	2095	}
AnnaBridge	189:f392fc9709a3	2096
AnnaBridge	189:f392fc9709a3	2097	/**
AnnaBridge	189:f392fc9709a3	2098	* @brief Clear Channel 7 transfer complete flag.
AnnaBridge	189:f392fc9709a3	2099	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge	189:f392fc9709a3	2100	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2101	* @retval None
AnnaBridge	189:f392fc9709a3	2102	*/
AnnaBridge	189:f392fc9709a3	2103	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2104	{
AnnaBridge	189:f392fc9709a3	2105	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
AnnaBridge	189:f392fc9709a3	2106	}
AnnaBridge	189:f392fc9709a3	2107
AnnaBridge	189:f392fc9709a3	2108	/**
AnnaBridge	189:f392fc9709a3	2109	* @brief Clear Channel 1 half transfer flag.
AnnaBridge	189:f392fc9709a3	2110	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge	189:f392fc9709a3	2111	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2112	* @retval None
AnnaBridge	189:f392fc9709a3	2113	*/
AnnaBridge	189:f392fc9709a3	2114	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2115	{
AnnaBridge	189:f392fc9709a3	2116	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
AnnaBridge	189:f392fc9709a3	2117	}
AnnaBridge	189:f392fc9709a3	2118
AnnaBridge	189:f392fc9709a3	2119	/**
AnnaBridge	189:f392fc9709a3	2120	* @brief Clear Channel 2 half transfer flag.
AnnaBridge	189:f392fc9709a3	2121	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge	189:f392fc9709a3	2122	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2123	* @retval None
AnnaBridge	189:f392fc9709a3	2124	*/
AnnaBridge	189:f392fc9709a3	2125	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2126	{
AnnaBridge	189:f392fc9709a3	2127	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
AnnaBridge	189:f392fc9709a3	2128	}
AnnaBridge	189:f392fc9709a3	2129
AnnaBridge	189:f392fc9709a3	2130	/**
AnnaBridge	189:f392fc9709a3	2131	* @brief Clear Channel 3 half transfer flag.
AnnaBridge	189:f392fc9709a3	2132	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge	189:f392fc9709a3	2133	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2134	* @retval None
AnnaBridge	189:f392fc9709a3	2135	*/
AnnaBridge	189:f392fc9709a3	2136	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2137	{
AnnaBridge	189:f392fc9709a3	2138	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
AnnaBridge	189:f392fc9709a3	2139	}
AnnaBridge	189:f392fc9709a3	2140
AnnaBridge	189:f392fc9709a3	2141	/**
AnnaBridge	189:f392fc9709a3	2142	* @brief Clear Channel 4 half transfer flag.
AnnaBridge	189:f392fc9709a3	2143	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge	189:f392fc9709a3	2144	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2145	* @retval None
AnnaBridge	189:f392fc9709a3	2146	*/
AnnaBridge	189:f392fc9709a3	2147	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2148	{
AnnaBridge	189:f392fc9709a3	2149	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
AnnaBridge	189:f392fc9709a3	2150	}
AnnaBridge	189:f392fc9709a3	2151
AnnaBridge	189:f392fc9709a3	2152	/**
AnnaBridge	189:f392fc9709a3	2153	* @brief Clear Channel 5 half transfer flag.
AnnaBridge	189:f392fc9709a3	2154	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge	189:f392fc9709a3	2155	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2156	* @retval None
AnnaBridge	189:f392fc9709a3	2157	*/
AnnaBridge	189:f392fc9709a3	2158	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2159	{
AnnaBridge	189:f392fc9709a3	2160	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
AnnaBridge	189:f392fc9709a3	2161	}
AnnaBridge	189:f392fc9709a3	2162
AnnaBridge	189:f392fc9709a3	2163	/**
AnnaBridge	189:f392fc9709a3	2164	* @brief Clear Channel 6 half transfer flag.
AnnaBridge	189:f392fc9709a3	2165	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge	189:f392fc9709a3	2166	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2167	* @retval None
AnnaBridge	189:f392fc9709a3	2168	*/
AnnaBridge	189:f392fc9709a3	2169	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2170	{
AnnaBridge	189:f392fc9709a3	2171	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
AnnaBridge	189:f392fc9709a3	2172	}
AnnaBridge	189:f392fc9709a3	2173
AnnaBridge	189:f392fc9709a3	2174	/**
AnnaBridge	189:f392fc9709a3	2175	* @brief Clear Channel 7 half transfer flag.
AnnaBridge	189:f392fc9709a3	2176	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge	189:f392fc9709a3	2177	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2178	* @retval None
AnnaBridge	189:f392fc9709a3	2179	*/
AnnaBridge	189:f392fc9709a3	2180	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2181	{
AnnaBridge	189:f392fc9709a3	2182	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
AnnaBridge	189:f392fc9709a3	2183	}
AnnaBridge	189:f392fc9709a3	2184
AnnaBridge	189:f392fc9709a3	2185	/**
AnnaBridge	189:f392fc9709a3	2186	* @brief Clear Channel 1 transfer error flag.
AnnaBridge	189:f392fc9709a3	2187	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge	189:f392fc9709a3	2188	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2189	* @retval None
AnnaBridge	189:f392fc9709a3	2190	*/
AnnaBridge	189:f392fc9709a3	2191	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2192	{
AnnaBridge	189:f392fc9709a3	2193	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
AnnaBridge	189:f392fc9709a3	2194	}
AnnaBridge	189:f392fc9709a3	2195
AnnaBridge	189:f392fc9709a3	2196	/**
AnnaBridge	189:f392fc9709a3	2197	* @brief Clear Channel 2 transfer error flag.
AnnaBridge	189:f392fc9709a3	2198	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge	189:f392fc9709a3	2199	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2200	* @retval None
AnnaBridge	189:f392fc9709a3	2201	*/
AnnaBridge	189:f392fc9709a3	2202	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2203	{
AnnaBridge	189:f392fc9709a3	2204	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
AnnaBridge	189:f392fc9709a3	2205	}
AnnaBridge	189:f392fc9709a3	2206
AnnaBridge	189:f392fc9709a3	2207	/**
AnnaBridge	189:f392fc9709a3	2208	* @brief Clear Channel 3 transfer error flag.
AnnaBridge	189:f392fc9709a3	2209	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge	189:f392fc9709a3	2210	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2211	* @retval None
AnnaBridge	189:f392fc9709a3	2212	*/
AnnaBridge	189:f392fc9709a3	2213	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2214	{
AnnaBridge	189:f392fc9709a3	2215	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
AnnaBridge	189:f392fc9709a3	2216	}
AnnaBridge	189:f392fc9709a3	2217
AnnaBridge	189:f392fc9709a3	2218	/**
AnnaBridge	189:f392fc9709a3	2219	* @brief Clear Channel 4 transfer error flag.
AnnaBridge	189:f392fc9709a3	2220	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge	189:f392fc9709a3	2221	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2222	* @retval None
AnnaBridge	189:f392fc9709a3	2223	*/
AnnaBridge	189:f392fc9709a3	2224	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2225	{
AnnaBridge	189:f392fc9709a3	2226	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
AnnaBridge	189:f392fc9709a3	2227	}
AnnaBridge	189:f392fc9709a3	2228
AnnaBridge	189:f392fc9709a3	2229	/**
AnnaBridge	189:f392fc9709a3	2230	* @brief Clear Channel 5 transfer error flag.
AnnaBridge	189:f392fc9709a3	2231	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge	189:f392fc9709a3	2232	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2233	* @retval None
AnnaBridge	189:f392fc9709a3	2234	*/
AnnaBridge	189:f392fc9709a3	2235	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2236	{
AnnaBridge	189:f392fc9709a3	2237	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
AnnaBridge	189:f392fc9709a3	2238	}
AnnaBridge	189:f392fc9709a3	2239
AnnaBridge	189:f392fc9709a3	2240	/**
AnnaBridge	189:f392fc9709a3	2241	* @brief Clear Channel 6 transfer error flag.
AnnaBridge	189:f392fc9709a3	2242	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge	189:f392fc9709a3	2243	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2244	* @retval None
AnnaBridge	189:f392fc9709a3	2245	*/
AnnaBridge	189:f392fc9709a3	2246	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2247	{
AnnaBridge	189:f392fc9709a3	2248	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
AnnaBridge	189:f392fc9709a3	2249	}
AnnaBridge	189:f392fc9709a3	2250
AnnaBridge	189:f392fc9709a3	2251	/**
AnnaBridge	189:f392fc9709a3	2252	* @brief Clear Channel 7 transfer error flag.
AnnaBridge	189:f392fc9709a3	2253	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge	189:f392fc9709a3	2254	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2255	* @retval None
AnnaBridge	189:f392fc9709a3	2256	*/
AnnaBridge	189:f392fc9709a3	2257	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	189:f392fc9709a3	2258	{
AnnaBridge	189:f392fc9709a3	2259	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
AnnaBridge	189:f392fc9709a3	2260	}
AnnaBridge	189:f392fc9709a3	2261
AnnaBridge	189:f392fc9709a3	2262	/**
AnnaBridge	189:f392fc9709a3	2263	* @}
AnnaBridge	189:f392fc9709a3	2264	*/
AnnaBridge	189:f392fc9709a3	2265
AnnaBridge	189:f392fc9709a3	2266	/** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge	189:f392fc9709a3	2267	* @{
AnnaBridge	189:f392fc9709a3	2268	*/
AnnaBridge	189:f392fc9709a3	2269	/**
AnnaBridge	189:f392fc9709a3	2270	* @brief Enable Transfer complete interrupt.
AnnaBridge	189:f392fc9709a3	2271	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
AnnaBridge	189:f392fc9709a3	2272	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2273	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2274	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	2275	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	2276	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	2277	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	2278	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	2279	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	2280	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	2281	* @retval None
AnnaBridge	189:f392fc9709a3	2282	*/
AnnaBridge	189:f392fc9709a3	2283	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	2284	{
AnnaBridge	189:f392fc9709a3	2285	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	189:f392fc9709a3	2286	}
AnnaBridge	189:f392fc9709a3	2287
AnnaBridge	189:f392fc9709a3	2288	/**
AnnaBridge	189:f392fc9709a3	2289	* @brief Enable Half transfer interrupt.
AnnaBridge	189:f392fc9709a3	2290	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
AnnaBridge	189:f392fc9709a3	2291	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2292	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2293	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	2294	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	2295	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	2296	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	2297	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	2298	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	2299	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	2300	* @retval None
AnnaBridge	189:f392fc9709a3	2301	*/
AnnaBridge	189:f392fc9709a3	2302	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	2303	{
AnnaBridge	189:f392fc9709a3	2304	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	189:f392fc9709a3	2305	}
AnnaBridge	189:f392fc9709a3	2306
AnnaBridge	189:f392fc9709a3	2307	/**
AnnaBridge	189:f392fc9709a3	2308	* @brief Enable Transfer error interrupt.
AnnaBridge	189:f392fc9709a3	2309	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
AnnaBridge	189:f392fc9709a3	2310	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2311	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2312	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	2313	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	2314	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	2315	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	2316	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	2317	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	2318	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	2319	* @retval None
AnnaBridge	189:f392fc9709a3	2320	*/
AnnaBridge	189:f392fc9709a3	2321	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	2322	{
AnnaBridge	189:f392fc9709a3	2323	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	189:f392fc9709a3	2324	}
AnnaBridge	189:f392fc9709a3	2325
AnnaBridge	189:f392fc9709a3	2326	/**
AnnaBridge	189:f392fc9709a3	2327	* @brief Disable Transfer complete interrupt.
AnnaBridge	189:f392fc9709a3	2328	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
AnnaBridge	189:f392fc9709a3	2329	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2330	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2331	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	2332	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	2333	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	2334	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	2335	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	2336	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	2337	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	2338	* @retval None
AnnaBridge	189:f392fc9709a3	2339	*/
AnnaBridge	189:f392fc9709a3	2340	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	2341	{
AnnaBridge	189:f392fc9709a3	2342	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	189:f392fc9709a3	2343	}
AnnaBridge	189:f392fc9709a3	2344
AnnaBridge	189:f392fc9709a3	2345	/**
AnnaBridge	189:f392fc9709a3	2346	* @brief Disable Half transfer interrupt.
AnnaBridge	189:f392fc9709a3	2347	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
AnnaBridge	189:f392fc9709a3	2348	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2349	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2350	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	2351	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	2352	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	2353	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	2354	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	2355	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	2356	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	2357	* @retval None
AnnaBridge	189:f392fc9709a3	2358	*/
AnnaBridge	189:f392fc9709a3	2359	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	2360	{
AnnaBridge	189:f392fc9709a3	2361	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	189:f392fc9709a3	2362	}
AnnaBridge	189:f392fc9709a3	2363
AnnaBridge	189:f392fc9709a3	2364	/**
AnnaBridge	189:f392fc9709a3	2365	* @brief Disable Transfer error interrupt.
AnnaBridge	189:f392fc9709a3	2366	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
AnnaBridge	189:f392fc9709a3	2367	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2368	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2369	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	2370	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	2371	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	2372	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	2373	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	2374	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	2375	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	2376	* @retval None
AnnaBridge	189:f392fc9709a3	2377	*/
AnnaBridge	189:f392fc9709a3	2378	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	2379	{
AnnaBridge	189:f392fc9709a3	2380	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	189:f392fc9709a3	2381	}
AnnaBridge	189:f392fc9709a3	2382
AnnaBridge	189:f392fc9709a3	2383	/**
AnnaBridge	189:f392fc9709a3	2384	* @brief Check if Transfer complete Interrupt is enabled.
AnnaBridge	189:f392fc9709a3	2385	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge	189:f392fc9709a3	2386	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2387	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2388	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	2389	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	2390	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	2391	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	2392	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	2393	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	2394	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	2395	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2396	*/
AnnaBridge	189:f392fc9709a3	2397	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	2398	{
AnnaBridge	189:f392fc9709a3	2399	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	189:f392fc9709a3	2400	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
AnnaBridge	189:f392fc9709a3	2401	}
AnnaBridge	189:f392fc9709a3	2402
AnnaBridge	189:f392fc9709a3	2403	/**
AnnaBridge	189:f392fc9709a3	2404	* @brief Check if Half transfer Interrupt is enabled.
AnnaBridge	189:f392fc9709a3	2405	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge	189:f392fc9709a3	2406	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2407	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2408	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	2409	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	2410	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	2411	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	2412	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	2413	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	2414	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	2415	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2416	*/
AnnaBridge	189:f392fc9709a3	2417	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	2418	{
AnnaBridge	189:f392fc9709a3	2419	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	189:f392fc9709a3	2420	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
AnnaBridge	189:f392fc9709a3	2421	}
AnnaBridge	189:f392fc9709a3	2422
AnnaBridge	189:f392fc9709a3	2423	/**
AnnaBridge	189:f392fc9709a3	2424	* @brief Check if Transfer error Interrupt is enabled.
AnnaBridge	189:f392fc9709a3	2425	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge	189:f392fc9709a3	2426	* @param DMAx DMAx Instance
AnnaBridge	189:f392fc9709a3	2427	* @param Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2428	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	189:f392fc9709a3	2429	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	189:f392fc9709a3	2430	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	189:f392fc9709a3	2431	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	189:f392fc9709a3	2432	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	189:f392fc9709a3	2433	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	189:f392fc9709a3	2434	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	189:f392fc9709a3	2435	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2436	*/
AnnaBridge	189:f392fc9709a3	2437	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	189:f392fc9709a3	2438	{
AnnaBridge	189:f392fc9709a3	2439	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	189:f392fc9709a3	2440	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
AnnaBridge	189:f392fc9709a3	2441	}
AnnaBridge	189:f392fc9709a3	2442
AnnaBridge	189:f392fc9709a3	2443	/**
AnnaBridge	189:f392fc9709a3	2444	* @}
AnnaBridge	189:f392fc9709a3	2445	*/
AnnaBridge	189:f392fc9709a3	2446
AnnaBridge	189:f392fc9709a3	2447	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	2448	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	189:f392fc9709a3	2449	* @{
AnnaBridge	189:f392fc9709a3	2450	*/
AnnaBridge	189:f392fc9709a3	2451
AnnaBridge	189:f392fc9709a3	2452	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
AnnaBridge	189:f392fc9709a3	2453	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	2454	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge	189:f392fc9709a3	2455
AnnaBridge	189:f392fc9709a3	2456	/**
AnnaBridge	189:f392fc9709a3	2457	* @}
AnnaBridge	189:f392fc9709a3	2458	*/
AnnaBridge	189:f392fc9709a3	2459	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	2460
AnnaBridge	189:f392fc9709a3	2461	/**
AnnaBridge	189:f392fc9709a3	2462	* @}
AnnaBridge	189:f392fc9709a3	2463	*/
AnnaBridge	189:f392fc9709a3	2464
AnnaBridge	189:f392fc9709a3	2465	/**
AnnaBridge	189:f392fc9709a3	2466	* @}
AnnaBridge	189:f392fc9709a3	2467	*/
AnnaBridge	189:f392fc9709a3	2468
AnnaBridge	189:f392fc9709a3	2469	#endif /* DMA1 \|\| DMA2 */
AnnaBridge	189:f392fc9709a3	2470
AnnaBridge	189:f392fc9709a3	2471	/**
AnnaBridge	189:f392fc9709a3	2472	* @}
AnnaBridge	189:f392fc9709a3	2473	*/
AnnaBridge	189:f392fc9709a3	2474
AnnaBridge	189:f392fc9709a3	2475	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	2476	}
AnnaBridge	189:f392fc9709a3	2477	#endif
AnnaBridge	189:f392fc9709a3	2478
AnnaBridge	189:f392fc9709a3	2479	#endif /* __STM32L4xx_LL_DMA_H */
AnnaBridge	189:f392fc9709a3	2480
AnnaBridge	189:f392fc9709a3	2481	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/