mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_ll_dac.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l4xx_ll_dac.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of DAC LL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L4xx_LL_DAC_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L4xx_LL_DAC_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	45	#include "stm32l4xx.h"
AnnaBridge	189:f392fc9709a3	46
AnnaBridge	189:f392fc9709a3	47	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	189:f392fc9709a3	48	* @{
AnnaBridge	189:f392fc9709a3	49	*/
AnnaBridge	189:f392fc9709a3	50
AnnaBridge	189:f392fc9709a3	51	#if defined (DAC1)
AnnaBridge	189:f392fc9709a3	52
AnnaBridge	189:f392fc9709a3	53	/** @defgroup DAC_LL DAC
AnnaBridge	189:f392fc9709a3	54	* @{
AnnaBridge	189:f392fc9709a3	55	*/
AnnaBridge	189:f392fc9709a3	56
AnnaBridge	189:f392fc9709a3	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	59
AnnaBridge	189:f392fc9709a3	60	/* Private constants ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	61	/** @defgroup DAC_LL_Private_Constants DAC Private Constants
AnnaBridge	189:f392fc9709a3	62	* @{
AnnaBridge	189:f392fc9709a3	63	*/
AnnaBridge	189:f392fc9709a3	64
AnnaBridge	189:f392fc9709a3	65	/* Internal masks for DAC channels definition */
AnnaBridge	189:f392fc9709a3	66	/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
AnnaBridge	189:f392fc9709a3	67	/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
AnnaBridge	189:f392fc9709a3	68	/* - channel bits position into register SWTRIG */
AnnaBridge	189:f392fc9709a3	69	/* - channel register offset of data holding register DHRx */
AnnaBridge	189:f392fc9709a3	70	/* - channel register offset of data output register DORx */
AnnaBridge	189:f392fc9709a3	71	/* - channel register offset of sample-and-hold sample time register SHSRx */
AnnaBridge	189:f392fc9709a3	72
AnnaBridge	189:f392fc9709a3	73	#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
AnnaBridge	189:f392fc9709a3	74	#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
AnnaBridge	189:f392fc9709a3	75	#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET \| DAC_CR_CH2_BITOFFSET)
AnnaBridge	189:f392fc9709a3	76
AnnaBridge	189:f392fc9709a3	77	#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
AnnaBridge	189:f392fc9709a3	78	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	79	#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
AnnaBridge	189:f392fc9709a3	80	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 \| DAC_SWTR_CH2)
AnnaBridge	189:f392fc9709a3	81	#else
AnnaBridge	189:f392fc9709a3	82	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
AnnaBridge	189:f392fc9709a3	83	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	84
AnnaBridge	189:f392fc9709a3	85	#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
AnnaBridge	189:f392fc9709a3	86	#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
AnnaBridge	189:f392fc9709a3	87	#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
AnnaBridge	189:f392fc9709a3	88	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	89	#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
AnnaBridge	189:f392fc9709a3	90	#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
AnnaBridge	189:f392fc9709a3	91	#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
AnnaBridge	189:f392fc9709a3	92	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	93	#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
AnnaBridge	189:f392fc9709a3	94	#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
AnnaBridge	189:f392fc9709a3	95	#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
AnnaBridge	189:f392fc9709a3	96	#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK \| DAC_REG_DHR12LX_REGOFFSET_MASK \| DAC_REG_DHR8RX_REGOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	97
AnnaBridge	189:f392fc9709a3	98	#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
AnnaBridge	189:f392fc9709a3	99	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	100	#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
AnnaBridge	189:f392fc9709a3	101	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DOR2_REGOFFSET)
AnnaBridge	189:f392fc9709a3	102	#else
AnnaBridge	189:f392fc9709a3	103	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
AnnaBridge	189:f392fc9709a3	104	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	105
AnnaBridge	189:f392fc9709a3	106	#define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */
AnnaBridge	189:f392fc9709a3	107	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	108	#define DAC_REG_SHSR2_REGOFFSET 0x00001000U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 12 bits) */
AnnaBridge	189:f392fc9709a3	109	#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET \| DAC_REG_SHSR2_REGOFFSET)
AnnaBridge	189:f392fc9709a3	110	#else
AnnaBridge	189:f392fc9709a3	111	#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET)
AnnaBridge	189:f392fc9709a3	112	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	113
AnnaBridge	189:f392fc9709a3	114	/* DAC registers bits positions */
AnnaBridge	189:f392fc9709a3	115	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	116	#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
AnnaBridge	189:f392fc9709a3	117	#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
AnnaBridge	189:f392fc9709a3	118	#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
AnnaBridge	189:f392fc9709a3	119	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	120
AnnaBridge	189:f392fc9709a3	121	/* Miscellaneous data */
AnnaBridge	189:f392fc9709a3	122	#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
AnnaBridge	189:f392fc9709a3	123
AnnaBridge	189:f392fc9709a3	124	/**
AnnaBridge	189:f392fc9709a3	125	* @}
AnnaBridge	189:f392fc9709a3	126	*/
AnnaBridge	189:f392fc9709a3	127
AnnaBridge	189:f392fc9709a3	128
AnnaBridge	189:f392fc9709a3	129	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	130	/** @defgroup DAC_LL_Private_Macros DAC Private Macros
AnnaBridge	189:f392fc9709a3	131	* @{
AnnaBridge	189:f392fc9709a3	132	*/
AnnaBridge	189:f392fc9709a3	133
AnnaBridge	189:f392fc9709a3	134	/**
AnnaBridge	189:f392fc9709a3	135	* @brief Driver macro reserved for internal use: isolate bits with the
AnnaBridge	189:f392fc9709a3	136	* selected mask and shift them to the register LSB
AnnaBridge	189:f392fc9709a3	137	* (shift mask on register position bit 0).
AnnaBridge	189:f392fc9709a3	138	* @param __BITS__ Bits in register 32 bits
AnnaBridge	189:f392fc9709a3	139	* @param __MASK__ Mask in register 32 bits
AnnaBridge	189:f392fc9709a3	140	* @retval Bits in register 32 bits
AnnaBridge	189:f392fc9709a3	141	*/
AnnaBridge	189:f392fc9709a3	142	#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
AnnaBridge	189:f392fc9709a3	143	(((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
AnnaBridge	189:f392fc9709a3	144
AnnaBridge	189:f392fc9709a3	145	/**
AnnaBridge	189:f392fc9709a3	146	* @brief Driver macro reserved for internal use: set a pointer to
AnnaBridge	189:f392fc9709a3	147	* a register from a register basis from which an offset
AnnaBridge	189:f392fc9709a3	148	* is applied.
AnnaBridge	189:f392fc9709a3	149	* @param __REG__ Register basis from which the offset is applied.
AnnaBridge	189:f392fc9709a3	150	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
AnnaBridge	189:f392fc9709a3	151	* @retval Pointer to register address
AnnaBridge	189:f392fc9709a3	152	*/
AnnaBridge	189:f392fc9709a3	153	#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
AnnaBridge	189:f392fc9709a3	154	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
AnnaBridge	189:f392fc9709a3	155
AnnaBridge	189:f392fc9709a3	156	/**
AnnaBridge	189:f392fc9709a3	157	* @}
AnnaBridge	189:f392fc9709a3	158	*/
AnnaBridge	189:f392fc9709a3	159
AnnaBridge	189:f392fc9709a3	160
AnnaBridge	189:f392fc9709a3	161	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	162	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	163	/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
AnnaBridge	189:f392fc9709a3	164	* @{
AnnaBridge	189:f392fc9709a3	165	*/
AnnaBridge	189:f392fc9709a3	166
AnnaBridge	189:f392fc9709a3	167	/**
AnnaBridge	189:f392fc9709a3	168	* @brief Structure definition of some features of DAC instance.
AnnaBridge	189:f392fc9709a3	169	*/
AnnaBridge	189:f392fc9709a3	170	typedef struct
AnnaBridge	189:f392fc9709a3	171	{
AnnaBridge	189:f392fc9709a3	172	uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
AnnaBridge	189:f392fc9709a3	173	This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
AnnaBridge	189:f392fc9709a3	174
AnnaBridge	189:f392fc9709a3	175	This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
AnnaBridge	189:f392fc9709a3	176
AnnaBridge	189:f392fc9709a3	177	uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	178	This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
AnnaBridge	189:f392fc9709a3	179
AnnaBridge	189:f392fc9709a3	180	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
AnnaBridge	189:f392fc9709a3	181
AnnaBridge	189:f392fc9709a3	182	uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	183	If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
AnnaBridge	189:f392fc9709a3	184	If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
AnnaBridge	189:f392fc9709a3	185	@note If waveform automatic generation mode is disabled, this parameter is discarded.
AnnaBridge	189:f392fc9709a3	186
AnnaBridge	189:f392fc9709a3	187	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
AnnaBridge	189:f392fc9709a3	188
AnnaBridge	189:f392fc9709a3	189	uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	190	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
AnnaBridge	189:f392fc9709a3	191
AnnaBridge	189:f392fc9709a3	192	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
AnnaBridge	189:f392fc9709a3	193
AnnaBridge	189:f392fc9709a3	194	uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	195	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
AnnaBridge	189:f392fc9709a3	196
AnnaBridge	189:f392fc9709a3	197	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
AnnaBridge	189:f392fc9709a3	198
AnnaBridge	189:f392fc9709a3	199	uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	200	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
AnnaBridge	189:f392fc9709a3	201
AnnaBridge	189:f392fc9709a3	202	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
AnnaBridge	189:f392fc9709a3	203
AnnaBridge	189:f392fc9709a3	204	} LL_DAC_InitTypeDef;
AnnaBridge	189:f392fc9709a3	205
AnnaBridge	189:f392fc9709a3	206	/**
AnnaBridge	189:f392fc9709a3	207	* @}
AnnaBridge	189:f392fc9709a3	208	*/
AnnaBridge	189:f392fc9709a3	209	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	210
AnnaBridge	189:f392fc9709a3	211	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	212	/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
AnnaBridge	189:f392fc9709a3	213	* @{
AnnaBridge	189:f392fc9709a3	214	*/
AnnaBridge	189:f392fc9709a3	215
AnnaBridge	189:f392fc9709a3	216	/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
AnnaBridge	189:f392fc9709a3	217	* @brief Flags defines which can be used with LL_DAC_ReadReg function
AnnaBridge	189:f392fc9709a3	218	* @{
AnnaBridge	189:f392fc9709a3	219	*/
AnnaBridge	189:f392fc9709a3	220	/* DAC channel 1 flags */
AnnaBridge	189:f392fc9709a3	221	#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /!< DAC channel 1 flag DMA underrun /
AnnaBridge	189:f392fc9709a3	222	#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /!< DAC channel 1 flag offset calibration status /
AnnaBridge	189:f392fc9709a3	223	#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /!< DAC channel 1 flag busy writing sample time /
AnnaBridge	189:f392fc9709a3	224
AnnaBridge	189:f392fc9709a3	225	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	226	/* DAC channel 2 flags */
AnnaBridge	189:f392fc9709a3	227	#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /!< DAC channel 2 flag DMA underrun /
AnnaBridge	189:f392fc9709a3	228	#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /!< DAC channel 2 flag offset calibration status /
AnnaBridge	189:f392fc9709a3	229	#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /!< DAC channel 2 flag busy writing sample time /
AnnaBridge	189:f392fc9709a3	230	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	231	/**
AnnaBridge	189:f392fc9709a3	232	* @}
AnnaBridge	189:f392fc9709a3	233	*/
AnnaBridge	189:f392fc9709a3	234
AnnaBridge	189:f392fc9709a3	235	/** @defgroup DAC_LL_EC_IT DAC interruptions
AnnaBridge	189:f392fc9709a3	236	* @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
AnnaBridge	189:f392fc9709a3	237	* @{
AnnaBridge	189:f392fc9709a3	238	*/
AnnaBridge	189:f392fc9709a3	239	#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /!< DAC channel 1 interruption DMA underrun /
AnnaBridge	189:f392fc9709a3	240	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	241	#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /!< DAC channel 2 interruption DMA underrun /
AnnaBridge	189:f392fc9709a3	242	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	243	/**
AnnaBridge	189:f392fc9709a3	244	* @}
AnnaBridge	189:f392fc9709a3	245	*/
AnnaBridge	189:f392fc9709a3	246
AnnaBridge	189:f392fc9709a3	247	/** @defgroup DAC_LL_EC_CHANNEL DAC channels
AnnaBridge	189:f392fc9709a3	248	* @{
AnnaBridge	189:f392fc9709a3	249	*/
AnnaBridge	189:f392fc9709a3	250	#define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET \| DAC_REG_DOR1_REGOFFSET \| DAC_REG_DHR12R1_REGOFFSET \| DAC_REG_DHR12L1_REGOFFSET \| DAC_REG_DHR8R1_REGOFFSET \| DAC_CR_CH1_BITOFFSET \| DAC_SWTR_CH1) /!< DAC channel 1 /
AnnaBridge	189:f392fc9709a3	251	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	252	#define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET \| DAC_REG_DOR2_REGOFFSET \| DAC_REG_DHR12R2_REGOFFSET \| DAC_REG_DHR12L2_REGOFFSET \| DAC_REG_DHR8R2_REGOFFSET \| DAC_CR_CH2_BITOFFSET \| DAC_SWTR_CH2) /!< DAC channel 2 /
AnnaBridge	189:f392fc9709a3	253	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	254	/**
AnnaBridge	189:f392fc9709a3	255	* @}
AnnaBridge	189:f392fc9709a3	256	*/
AnnaBridge	189:f392fc9709a3	257
AnnaBridge	189:f392fc9709a3	258	/** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
AnnaBridge	189:f392fc9709a3	259	* @{
AnnaBridge	189:f392fc9709a3	260	*/
AnnaBridge	189:f392fc9709a3	261	#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000U /!< DAC channel in mode normal operation /
AnnaBridge	189:f392fc9709a3	262	#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /!< DAC channel in mode calibration /
AnnaBridge	189:f392fc9709a3	263	/**
AnnaBridge	189:f392fc9709a3	264	* @}
AnnaBridge	189:f392fc9709a3	265	*/
AnnaBridge	189:f392fc9709a3	266
AnnaBridge	189:f392fc9709a3	267	/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
AnnaBridge	189:f392fc9709a3	268	* @{
AnnaBridge	189:f392fc9709a3	269	*/
AnnaBridge	189:f392fc9709a3	270	#if defined (DAC_CR_TSEL1_3)
AnnaBridge	189:f392fc9709a3	271	#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM1 TRGO. /
AnnaBridge	189:f392fc9709a3	272	#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: TIM2 TRGO. /
AnnaBridge	189:f392fc9709a3	273	#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM4 TRGO. /
AnnaBridge	189:f392fc9709a3	274	#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /!< DAC channel conversion trigger from external IP: TIM4 TRGO. /
AnnaBridge	189:f392fc9709a3	275	#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM6 TRGO. /
AnnaBridge	189:f392fc9709a3	276	#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: TIM7 TRGO. /
AnnaBridge	189:f392fc9709a3	277	#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM8 TRGO. /
AnnaBridge	189:f392fc9709a3	278	#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /!< DAC channel conversion trigger from external IP: TIM15 TRGO. /
AnnaBridge	189:f392fc9709a3	279	#define LL_DAC_TRIG_EXT_LPTIM1_OUT_TRGO (DAC_CR_TSEL1_3 \| DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: LPTIM1 OUT TRGO. /
AnnaBridge	189:f392fc9709a3	280	#define LL_DAC_TRIG_EXT_LPTIM2_OUT_TRGO (DAC_CR_TSEL1_3 \| DAC_CR_TSEL1_2 ) /!< DAC channel conversion trigger from external IP: LPTIM2 OUT TRGO. /
AnnaBridge	189:f392fc9709a3	281	#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 \| DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: external interrupt line 9. /
AnnaBridge	189:f392fc9709a3	282	#define LL_DAC_TRIG_SOFTWARE 0x00000000U /!< DAC channel conversion trigger internal (SW start) /
AnnaBridge	189:f392fc9709a3	283	#else
AnnaBridge	189:f392fc9709a3	284	#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger internal (SW start) /
AnnaBridge	189:f392fc9709a3	285	#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /!< DAC channel conversion trigger from external IP: TIM2 TRGO. /
AnnaBridge	189:f392fc9709a3	286	#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM4 TRGO. /
AnnaBridge	189:f392fc9709a3	287	#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM5 TRGO. /
AnnaBridge	189:f392fc9709a3	288	#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /!< DAC channel conversion trigger from external IP: TIM6 TRGO. /
AnnaBridge	189:f392fc9709a3	289	#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: TIM7 TRGO. /
AnnaBridge	189:f392fc9709a3	290	#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM8 TRGO. /
AnnaBridge	189:f392fc9709a3	291	#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: external interrupt line 9. /
AnnaBridge	189:f392fc9709a3	292	#endif
AnnaBridge	189:f392fc9709a3	293
AnnaBridge	189:f392fc9709a3	294	/**
AnnaBridge	189:f392fc9709a3	295	* @}
AnnaBridge	189:f392fc9709a3	296	*/
AnnaBridge	189:f392fc9709a3	297
AnnaBridge	189:f392fc9709a3	298	/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
AnnaBridge	189:f392fc9709a3	299	* @{
AnnaBridge	189:f392fc9709a3	300	*/
AnnaBridge	189:f392fc9709a3	301	#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /!< DAC channel wave auto generation mode disabled. /
AnnaBridge	189:f392fc9709a3	302	#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /!< DAC channel wave auto generation mode enabled, set generated noise waveform. /
AnnaBridge	189:f392fc9709a3	303	#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /!< DAC channel wave auto generation mode enabled, set generated triangle waveform. /
AnnaBridge	189:f392fc9709a3	304	/**
AnnaBridge	189:f392fc9709a3	305	* @}
AnnaBridge	189:f392fc9709a3	306	*/
AnnaBridge	189:f392fc9709a3	307
AnnaBridge	189:f392fc9709a3	308	/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
AnnaBridge	189:f392fc9709a3	309	* @{
AnnaBridge	189:f392fc9709a3	310	*/
AnnaBridge	189:f392fc9709a3	311	#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	312	#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	313	#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	314	#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	315	#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	316	#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	317	#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	318	#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	319	#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	320	#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	321	#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	322	#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	323	/**
AnnaBridge	189:f392fc9709a3	324	* @}
AnnaBridge	189:f392fc9709a3	325	*/
AnnaBridge	189:f392fc9709a3	326
AnnaBridge	189:f392fc9709a3	327	/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
AnnaBridge	189:f392fc9709a3	328	* @{
AnnaBridge	189:f392fc9709a3	329	*/
AnnaBridge	189:f392fc9709a3	330	#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	331	#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	332	#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	333	#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	334	#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	335	#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	336	#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	337	#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	338	#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	339	#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	340	#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	341	#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	342	/**
AnnaBridge	189:f392fc9709a3	343	* @}
AnnaBridge	189:f392fc9709a3	344	*/
AnnaBridge	189:f392fc9709a3	345
AnnaBridge	189:f392fc9709a3	346	/** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
AnnaBridge	189:f392fc9709a3	347	* @{
AnnaBridge	189:f392fc9709a3	348	*/
AnnaBridge	189:f392fc9709a3	349	#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000U /!< The selected DAC channel output is on mode normal. /
AnnaBridge	189:f392fc9709a3	350	#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). /
AnnaBridge	189:f392fc9709a3	351	/**
AnnaBridge	189:f392fc9709a3	352	* @}
AnnaBridge	189:f392fc9709a3	353	*/
AnnaBridge	189:f392fc9709a3	354
AnnaBridge	189:f392fc9709a3	355	/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
AnnaBridge	189:f392fc9709a3	356	* @{
AnnaBridge	189:f392fc9709a3	357	*/
AnnaBridge	189:f392fc9709a3	358	#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption /
AnnaBridge	189:f392fc9709a3	359	#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption /
AnnaBridge	189:f392fc9709a3	360	/**
AnnaBridge	189:f392fc9709a3	361	* @}
AnnaBridge	189:f392fc9709a3	362	*/
AnnaBridge	189:f392fc9709a3	363
AnnaBridge	189:f392fc9709a3	364	/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
AnnaBridge	189:f392fc9709a3	365	* @{
AnnaBridge	189:f392fc9709a3	366	*/
AnnaBridge	189:f392fc9709a3	367	#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /!< The selected DAC channel output is connected to external pin /
AnnaBridge	189:f392fc9709a3	368	#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). /
AnnaBridge	189:f392fc9709a3	369	/**
AnnaBridge	189:f392fc9709a3	370	* @}
AnnaBridge	189:f392fc9709a3	371	*/
AnnaBridge	189:f392fc9709a3	372
AnnaBridge	189:f392fc9709a3	373	/** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming
AnnaBridge	189:f392fc9709a3	374	* @{
AnnaBridge	189:f392fc9709a3	375	*/
AnnaBridge	189:f392fc9709a3	376	#define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE)
AnnaBridge	189:f392fc9709a3	377	#define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO)
AnnaBridge	189:f392fc9709a3	378	#define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO)
AnnaBridge	189:f392fc9709a3	379	#define LL_DAC_TRIGGER_TIM5_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO)
AnnaBridge	189:f392fc9709a3	380	#define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO)
AnnaBridge	189:f392fc9709a3	381	#define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO)
AnnaBridge	189:f392fc9709a3	382	#define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO)
AnnaBridge	189:f392fc9709a3	383	#define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9)
AnnaBridge	189:f392fc9709a3	384
AnnaBridge	189:f392fc9709a3	385	#define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE)
AnnaBridge	189:f392fc9709a3	386	#define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
AnnaBridge	189:f392fc9709a3	387	#define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
AnnaBridge	189:f392fc9709a3	388
AnnaBridge	189:f392fc9709a3	389	#define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO)
AnnaBridge	189:f392fc9709a3	390	#define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL)
AnnaBridge	189:f392fc9709a3	391	/**
AnnaBridge	189:f392fc9709a3	392	* @}
AnnaBridge	189:f392fc9709a3	393	*/
AnnaBridge	189:f392fc9709a3	394
AnnaBridge	189:f392fc9709a3	395	/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
AnnaBridge	189:f392fc9709a3	396	* @{
AnnaBridge	189:f392fc9709a3	397	*/
AnnaBridge	189:f392fc9709a3	398	#define LL_DAC_RESOLUTION_12B 0x00000000U /!< DAC channel resolution 12 bits /
AnnaBridge	189:f392fc9709a3	399	#define LL_DAC_RESOLUTION_8B 0x00000002U /!< DAC channel resolution 8 bits /
AnnaBridge	189:f392fc9709a3	400	/**
AnnaBridge	189:f392fc9709a3	401	* @}
AnnaBridge	189:f392fc9709a3	402	*/
AnnaBridge	189:f392fc9709a3	403
AnnaBridge	189:f392fc9709a3	404	/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
AnnaBridge	189:f392fc9709a3	405	* @{
AnnaBridge	189:f392fc9709a3	406	*/
AnnaBridge	189:f392fc9709a3	407	/* List of DAC registers intended to be used (most commonly) with */
AnnaBridge	189:f392fc9709a3	408	/* DMA transfer. */
AnnaBridge	189:f392fc9709a3	409	/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
AnnaBridge	189:f392fc9709a3	410	#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /!< DAC channel data holding register 12 bits right aligned /
AnnaBridge	189:f392fc9709a3	411	#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /!< DAC channel data holding register 12 bits left aligned /
AnnaBridge	189:f392fc9709a3	412	#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /!< DAC channel data holding register 8 bits right aligned /
AnnaBridge	189:f392fc9709a3	413	/**
AnnaBridge	189:f392fc9709a3	414	* @}
AnnaBridge	189:f392fc9709a3	415	*/
AnnaBridge	189:f392fc9709a3	416
AnnaBridge	189:f392fc9709a3	417	/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
AnnaBridge	189:f392fc9709a3	418	* @note Only DAC IP HW delays are defined in DAC LL driver driver,
AnnaBridge	189:f392fc9709a3	419	* not timeout values.
AnnaBridge	189:f392fc9709a3	420	* For details on delays values, refer to descriptions in source code
AnnaBridge	189:f392fc9709a3	421	* above each literal definition.
AnnaBridge	189:f392fc9709a3	422	* @{
AnnaBridge	189:f392fc9709a3	423	*/
AnnaBridge	189:f392fc9709a3	424
AnnaBridge	189:f392fc9709a3	425	/* Delay for DAC channel voltage settling time from DAC channel startup */
AnnaBridge	189:f392fc9709a3	426	/* (transition from disable to enable). */
AnnaBridge	189:f392fc9709a3	427	/* Note: DAC channel startup time depends on board application environment: */
AnnaBridge	189:f392fc9709a3	428	/* impedance connected to DAC channel output. */
AnnaBridge	189:f392fc9709a3	429	/* The delay below is specified under conditions: */
AnnaBridge	189:f392fc9709a3	430	/* - voltage maximum transition (lowest to highest value) */
AnnaBridge	189:f392fc9709a3	431	/* - until voltage reaches final value +-1LSB */
AnnaBridge	189:f392fc9709a3	432	/* - DAC channel output buffer enabled */
AnnaBridge	189:f392fc9709a3	433	/* - load impedance of 5kOhm (min), 50pF (max) */
AnnaBridge	189:f392fc9709a3	434	/* Literal set to maximum value (refer to device datasheet, */
AnnaBridge	189:f392fc9709a3	435	/* parameter "tWAKEUP"). */
AnnaBridge	189:f392fc9709a3	436	/* Unit: us */
AnnaBridge	189:f392fc9709a3	437	#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8U /!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) /
AnnaBridge	189:f392fc9709a3	438
AnnaBridge	189:f392fc9709a3	439
AnnaBridge	189:f392fc9709a3	440	/* Delay for DAC channel voltage settling time. */
AnnaBridge	189:f392fc9709a3	441	/* Note: DAC channel startup time depends on board application environment: */
AnnaBridge	189:f392fc9709a3	442	/* impedance connected to DAC channel output. */
AnnaBridge	189:f392fc9709a3	443	/* The delay below is specified under conditions: */
AnnaBridge	189:f392fc9709a3	444	/* - voltage maximum transition (lowest to highest value) */
AnnaBridge	189:f392fc9709a3	445	/* - until voltage reaches final value +-1LSB */
AnnaBridge	189:f392fc9709a3	446	/* - DAC channel output buffer enabled */
AnnaBridge	189:f392fc9709a3	447	/* - load impedance of 5kOhm min, 50pF max */
AnnaBridge	189:f392fc9709a3	448	/* Literal set to maximum value (refer to device datasheet, */
AnnaBridge	189:f392fc9709a3	449	/* parameter "tSETTLING"). */
AnnaBridge	189:f392fc9709a3	450	/* Unit: us */
AnnaBridge	189:f392fc9709a3	451	#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 2U /!< Delay for DAC channel voltage settling time /
AnnaBridge	189:f392fc9709a3	452
AnnaBridge	189:f392fc9709a3	453	/**
AnnaBridge	189:f392fc9709a3	454	* @}
AnnaBridge	189:f392fc9709a3	455	*/
AnnaBridge	189:f392fc9709a3	456
AnnaBridge	189:f392fc9709a3	457	/**
AnnaBridge	189:f392fc9709a3	458	* @}
AnnaBridge	189:f392fc9709a3	459	*/
AnnaBridge	189:f392fc9709a3	460
AnnaBridge	189:f392fc9709a3	461	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	462	/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
AnnaBridge	189:f392fc9709a3	463	* @{
AnnaBridge	189:f392fc9709a3	464	*/
AnnaBridge	189:f392fc9709a3	465
AnnaBridge	189:f392fc9709a3	466	/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
AnnaBridge	189:f392fc9709a3	467	* @{
AnnaBridge	189:f392fc9709a3	468	*/
AnnaBridge	189:f392fc9709a3	469
AnnaBridge	189:f392fc9709a3	470	/**
AnnaBridge	189:f392fc9709a3	471	* @brief Write a value in DAC register
AnnaBridge	189:f392fc9709a3	472	* @param __INSTANCE__ DAC Instance
AnnaBridge	189:f392fc9709a3	473	* @param __REG__ Register to be written
AnnaBridge	189:f392fc9709a3	474	* @param __VALUE__ Value to be written in the register
AnnaBridge	189:f392fc9709a3	475	* @retval None
AnnaBridge	189:f392fc9709a3	476	*/
AnnaBridge	189:f392fc9709a3	477	#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	189:f392fc9709a3	478
AnnaBridge	189:f392fc9709a3	479	/**
AnnaBridge	189:f392fc9709a3	480	* @brief Read a value in DAC register
AnnaBridge	189:f392fc9709a3	481	* @param __INSTANCE__ DAC Instance
AnnaBridge	189:f392fc9709a3	482	* @param __REG__ Register to be read
AnnaBridge	189:f392fc9709a3	483	* @retval Register value
AnnaBridge	189:f392fc9709a3	484	*/
AnnaBridge	189:f392fc9709a3	485	#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	189:f392fc9709a3	486
AnnaBridge	189:f392fc9709a3	487	/**
AnnaBridge	189:f392fc9709a3	488	* @}
AnnaBridge	189:f392fc9709a3	489	*/
AnnaBridge	189:f392fc9709a3	490
AnnaBridge	189:f392fc9709a3	491	/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
AnnaBridge	189:f392fc9709a3	492	* @{
AnnaBridge	189:f392fc9709a3	493	*/
AnnaBridge	189:f392fc9709a3	494
AnnaBridge	189:f392fc9709a3	495	/**
AnnaBridge	189:f392fc9709a3	496	* @brief Helper macro to get DAC channel number in decimal format
AnnaBridge	189:f392fc9709a3	497	* from literals LL_DAC_CHANNEL_x.
AnnaBridge	189:f392fc9709a3	498	* Example:
AnnaBridge	189:f392fc9709a3	499	* __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
AnnaBridge	189:f392fc9709a3	500	* will return decimal number "1".
AnnaBridge	189:f392fc9709a3	501	* @note The input can be a value from functions where a channel
AnnaBridge	189:f392fc9709a3	502	* number is returned.
AnnaBridge	189:f392fc9709a3	503	* @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	504	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	505	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	506	*
AnnaBridge	189:f392fc9709a3	507	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	508	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	509	* @retval 1...2 (value "2" depending on DAC channel 2 availability)
AnnaBridge	189:f392fc9709a3	510	*/
AnnaBridge	189:f392fc9709a3	511	#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
AnnaBridge	189:f392fc9709a3	512	((__CHANNEL__) & DAC_SWTR_CHX_MASK)
AnnaBridge	189:f392fc9709a3	513
AnnaBridge	189:f392fc9709a3	514	/**
AnnaBridge	189:f392fc9709a3	515	* @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
AnnaBridge	189:f392fc9709a3	516	* from number in decimal format.
AnnaBridge	189:f392fc9709a3	517	* Example:
AnnaBridge	189:f392fc9709a3	518	* __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
AnnaBridge	189:f392fc9709a3	519	* will return a data equivalent to "LL_DAC_CHANNEL_1".
AnnaBridge	189:f392fc9709a3	520	* @note If the input parameter does not correspond to a DAC channel,
AnnaBridge	189:f392fc9709a3	521	* this macro returns value '0'.
AnnaBridge	189:f392fc9709a3	522	* @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
AnnaBridge	189:f392fc9709a3	523	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	524	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	525	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	526	*
AnnaBridge	189:f392fc9709a3	527	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	528	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	529	*/
AnnaBridge	189:f392fc9709a3	530	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	531	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
AnnaBridge	189:f392fc9709a3	532	(((__DECIMAL_NB__) == 1U) \
AnnaBridge	189:f392fc9709a3	533	? ( \
AnnaBridge	189:f392fc9709a3	534	LL_DAC_CHANNEL_1 \
AnnaBridge	189:f392fc9709a3	535	) \
AnnaBridge	189:f392fc9709a3	536	: \
AnnaBridge	189:f392fc9709a3	537	(((__DECIMAL_NB__) == 2U) \
AnnaBridge	189:f392fc9709a3	538	? ( \
AnnaBridge	189:f392fc9709a3	539	LL_DAC_CHANNEL_2 \
AnnaBridge	189:f392fc9709a3	540	) \
AnnaBridge	189:f392fc9709a3	541	: \
AnnaBridge	189:f392fc9709a3	542	( \
AnnaBridge	189:f392fc9709a3	543	0 \
AnnaBridge	189:f392fc9709a3	544	) \
AnnaBridge	189:f392fc9709a3	545	) \
AnnaBridge	189:f392fc9709a3	546	)
AnnaBridge	189:f392fc9709a3	547	#else
AnnaBridge	189:f392fc9709a3	548	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
AnnaBridge	189:f392fc9709a3	549	(((__DECIMAL_NB__) == 1U) \
AnnaBridge	189:f392fc9709a3	550	? ( \
AnnaBridge	189:f392fc9709a3	551	LL_DAC_CHANNEL_1 \
AnnaBridge	189:f392fc9709a3	552	) \
AnnaBridge	189:f392fc9709a3	553	: \
AnnaBridge	189:f392fc9709a3	554	( \
AnnaBridge	189:f392fc9709a3	555	0 \
AnnaBridge	189:f392fc9709a3	556	) \
AnnaBridge	189:f392fc9709a3	557	)
AnnaBridge	189:f392fc9709a3	558	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	559
AnnaBridge	189:f392fc9709a3	560	/**
AnnaBridge	189:f392fc9709a3	561	* @brief Helper macro to define the DAC conversion data full-scale digital
AnnaBridge	189:f392fc9709a3	562	* value corresponding to the selected DAC resolution.
AnnaBridge	189:f392fc9709a3	563	* @note DAC conversion data full-scale corresponds to voltage range
AnnaBridge	189:f392fc9709a3	564	* determined by analog voltage references Vref+ and Vref-
AnnaBridge	189:f392fc9709a3	565	* (refer to reference manual).
AnnaBridge	189:f392fc9709a3	566	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	567	* @arg @ref LL_DAC_RESOLUTION_12B
AnnaBridge	189:f392fc9709a3	568	* @arg @ref LL_DAC_RESOLUTION_8B
AnnaBridge	189:f392fc9709a3	569	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
AnnaBridge	189:f392fc9709a3	570	*/
AnnaBridge	189:f392fc9709a3	571	#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
AnnaBridge	189:f392fc9709a3	572	((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
AnnaBridge	189:f392fc9709a3	573
AnnaBridge	189:f392fc9709a3	574	/**
AnnaBridge	189:f392fc9709a3	575	* @brief Helper macro to calculate the DAC conversion data (unit: digital
AnnaBridge	189:f392fc9709a3	576	* value) corresponding to a voltage (unit: mVolt).
AnnaBridge	189:f392fc9709a3	577	* @note This helper macro is intended to provide input data in voltage
AnnaBridge	189:f392fc9709a3	578	* rather than digital value,
AnnaBridge	189:f392fc9709a3	579	* to be used with LL DAC functions such as
AnnaBridge	189:f392fc9709a3	580	* @ref LL_DAC_ConvertData12RightAligned().
AnnaBridge	189:f392fc9709a3	581	* @note Analog reference voltage (Vref+) must be either known from
AnnaBridge	189:f392fc9709a3	582	* user board environment or can be calculated using ADC measurement
AnnaBridge	189:f392fc9709a3	583	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
AnnaBridge	189:f392fc9709a3	584	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
AnnaBridge	189:f392fc9709a3	585	* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
AnnaBridge	189:f392fc9709a3	586	* (unit: mVolt).
AnnaBridge	189:f392fc9709a3	587	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	588	* @arg @ref LL_DAC_RESOLUTION_12B
AnnaBridge	189:f392fc9709a3	589	* @arg @ref LL_DAC_RESOLUTION_8B
AnnaBridge	189:f392fc9709a3	590	* @retval DAC conversion data (unit: digital value)
AnnaBridge	189:f392fc9709a3	591	*/
AnnaBridge	189:f392fc9709a3	592	#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
AnnaBridge	189:f392fc9709a3	593	__DAC_VOLTAGE__,\
AnnaBridge	189:f392fc9709a3	594	__DAC_RESOLUTION__) \
AnnaBridge	189:f392fc9709a3	595	((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
AnnaBridge	189:f392fc9709a3	596	/ (__VREFANALOG_VOLTAGE__) \
AnnaBridge	189:f392fc9709a3	597	)
AnnaBridge	189:f392fc9709a3	598
AnnaBridge	189:f392fc9709a3	599	/**
AnnaBridge	189:f392fc9709a3	600	* @}
AnnaBridge	189:f392fc9709a3	601	*/
AnnaBridge	189:f392fc9709a3	602
AnnaBridge	189:f392fc9709a3	603	/**
AnnaBridge	189:f392fc9709a3	604	* @}
AnnaBridge	189:f392fc9709a3	605	*/
AnnaBridge	189:f392fc9709a3	606
AnnaBridge	189:f392fc9709a3	607
AnnaBridge	189:f392fc9709a3	608	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	609	/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
AnnaBridge	189:f392fc9709a3	610	* @{
AnnaBridge	189:f392fc9709a3	611	*/
AnnaBridge	189:f392fc9709a3	612	/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
AnnaBridge	189:f392fc9709a3	613	* @{
AnnaBridge	189:f392fc9709a3	614	*/
AnnaBridge	189:f392fc9709a3	615
AnnaBridge	189:f392fc9709a3	616	/**
AnnaBridge	189:f392fc9709a3	617	* @brief Set the operating mode for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	618	* calibration or normal operating mode.
AnnaBridge	189:f392fc9709a3	619	* @rmtoll CR CEN1 LL_DAC_SetMode\n
AnnaBridge	189:f392fc9709a3	620	* CR CEN2 LL_DAC_SetMode
AnnaBridge	189:f392fc9709a3	621	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	622	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	623	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	624	*
AnnaBridge	189:f392fc9709a3	625	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	626	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	627	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	628	* @param ChannelMode This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	629	* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
AnnaBridge	189:f392fc9709a3	630	* @arg @ref LL_DAC_MODE_CALIBRATION
AnnaBridge	189:f392fc9709a3	631	* @retval None
AnnaBridge	189:f392fc9709a3	632	*/
AnnaBridge	189:f392fc9709a3	633	__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
AnnaBridge	189:f392fc9709a3	634	{
AnnaBridge	189:f392fc9709a3	635	MODIFY_REG(DACx->CR,
AnnaBridge	189:f392fc9709a3	636	DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	637	ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	638	}
AnnaBridge	189:f392fc9709a3	639
AnnaBridge	189:f392fc9709a3	640	/**
AnnaBridge	189:f392fc9709a3	641	* @brief Get the operating mode for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	642	* calibration or normal operating mode.
AnnaBridge	189:f392fc9709a3	643	* @rmtoll CR CEN1 LL_DAC_GetMode\n
AnnaBridge	189:f392fc9709a3	644	* CR CEN2 LL_DAC_GetMode
AnnaBridge	189:f392fc9709a3	645	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	646	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	647	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	648	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	649	*
AnnaBridge	189:f392fc9709a3	650	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	651	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	652	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	653	* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
AnnaBridge	189:f392fc9709a3	654	* @arg @ref LL_DAC_MODE_CALIBRATION
AnnaBridge	189:f392fc9709a3	655	*/
AnnaBridge	189:f392fc9709a3	656	__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	657	{
AnnaBridge	189:f392fc9709a3	658	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	659	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	660	);
AnnaBridge	189:f392fc9709a3	661	}
AnnaBridge	189:f392fc9709a3	662
AnnaBridge	189:f392fc9709a3	663	/**
AnnaBridge	189:f392fc9709a3	664	* @brief Set the offset trimming value for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	665	* Trimming has an impact when output buffer is enabled
AnnaBridge	189:f392fc9709a3	666	* and is intended to replace factory calibration default values.
AnnaBridge	189:f392fc9709a3	667	* @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
AnnaBridge	189:f392fc9709a3	668	* CCR OTRIM2 LL_DAC_SetTrimmingValue
AnnaBridge	189:f392fc9709a3	669	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	670	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	671	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	672	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	673	*
AnnaBridge	189:f392fc9709a3	674	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	675	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	676	* @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
AnnaBridge	189:f392fc9709a3	677	* @retval None
AnnaBridge	189:f392fc9709a3	678	*/
AnnaBridge	189:f392fc9709a3	679	__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
AnnaBridge	189:f392fc9709a3	680	{
AnnaBridge	189:f392fc9709a3	681	MODIFY_REG(DACx->CCR,
AnnaBridge	189:f392fc9709a3	682	DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	683	TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	684	}
AnnaBridge	189:f392fc9709a3	685
AnnaBridge	189:f392fc9709a3	686	/**
AnnaBridge	189:f392fc9709a3	687	* @brief Get the offset trimming value for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	688	* Trimming has an impact when output buffer is enabled
AnnaBridge	189:f392fc9709a3	689	* and is intended to replace factory calibration default values.
AnnaBridge	189:f392fc9709a3	690	* @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
AnnaBridge	189:f392fc9709a3	691	* CCR OTRIM2 LL_DAC_GetTrimmingValue
AnnaBridge	189:f392fc9709a3	692	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	693	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	694	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	695	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	696	*
AnnaBridge	189:f392fc9709a3	697	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	698	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	699	* @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
AnnaBridge	189:f392fc9709a3	700	*/
AnnaBridge	189:f392fc9709a3	701	__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	702	{
AnnaBridge	189:f392fc9709a3	703	return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	704	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	705	);
AnnaBridge	189:f392fc9709a3	706	}
AnnaBridge	189:f392fc9709a3	707
AnnaBridge	189:f392fc9709a3	708	/**
AnnaBridge	189:f392fc9709a3	709	* @brief Set the conversion trigger source for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	710	* @note For conversion trigger source to be effective, DAC trigger
AnnaBridge	189:f392fc9709a3	711	* must be enabled using function @ref LL_DAC_EnableTrigger().
AnnaBridge	189:f392fc9709a3	712	* @note To set conversion trigger source, DAC channel must be disabled.
AnnaBridge	189:f392fc9709a3	713	* Otherwise, the setting is discarded.
AnnaBridge	189:f392fc9709a3	714	* @note Availability of parameters of trigger sources from timer
AnnaBridge	189:f392fc9709a3	715	* depends on timers availability on the selected device.
AnnaBridge	189:f392fc9709a3	716	* @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
AnnaBridge	189:f392fc9709a3	717	* CR TSEL2 LL_DAC_SetTriggerSource
AnnaBridge	189:f392fc9709a3	718	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	719	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	720	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	721	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	722	*
AnnaBridge	189:f392fc9709a3	723	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	724	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	725	* @param TriggerSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	726	* @arg @ref LL_DAC_TRIG_SOFTWARE
AnnaBridge	189:f392fc9709a3	727	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
AnnaBridge	189:f392fc9709a3	728	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
AnnaBridge	189:f392fc9709a3	729	* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
AnnaBridge	189:f392fc9709a3	730	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
AnnaBridge	189:f392fc9709a3	731	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
AnnaBridge	189:f392fc9709a3	732	* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
AnnaBridge	189:f392fc9709a3	733	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
AnnaBridge	189:f392fc9709a3	734	* @retval None
AnnaBridge	189:f392fc9709a3	735	*/
AnnaBridge	189:f392fc9709a3	736	__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
AnnaBridge	189:f392fc9709a3	737	{
AnnaBridge	189:f392fc9709a3	738	MODIFY_REG(DACx->CR,
AnnaBridge	189:f392fc9709a3	739	DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	740	TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	741	}
AnnaBridge	189:f392fc9709a3	742
AnnaBridge	189:f392fc9709a3	743	/**
AnnaBridge	189:f392fc9709a3	744	* @brief Get the conversion trigger source for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	745	* @note For conversion trigger source to be effective, DAC trigger
AnnaBridge	189:f392fc9709a3	746	* must be enabled using function @ref LL_DAC_EnableTrigger().
AnnaBridge	189:f392fc9709a3	747	* @note Availability of parameters of trigger sources from timer
AnnaBridge	189:f392fc9709a3	748	* depends on timers availability on the selected device.
AnnaBridge	189:f392fc9709a3	749	* @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
AnnaBridge	189:f392fc9709a3	750	* CR TSEL2 LL_DAC_GetTriggerSource
AnnaBridge	189:f392fc9709a3	751	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	752	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	753	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	754	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	755	*
AnnaBridge	189:f392fc9709a3	756	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	757	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	758	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	759	* @arg @ref LL_DAC_TRIG_SOFTWARE
AnnaBridge	189:f392fc9709a3	760	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
AnnaBridge	189:f392fc9709a3	761	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
AnnaBridge	189:f392fc9709a3	762	* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
AnnaBridge	189:f392fc9709a3	763	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
AnnaBridge	189:f392fc9709a3	764	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
AnnaBridge	189:f392fc9709a3	765	* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
AnnaBridge	189:f392fc9709a3	766	* @arg @ref LL_DAC_TRIGGER_EXT_IT9
AnnaBridge	189:f392fc9709a3	767	*/
AnnaBridge	189:f392fc9709a3	768	__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	769	{
AnnaBridge	189:f392fc9709a3	770	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	771	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	772	);
AnnaBridge	189:f392fc9709a3	773	}
AnnaBridge	189:f392fc9709a3	774
AnnaBridge	189:f392fc9709a3	775	/**
AnnaBridge	189:f392fc9709a3	776	* @brief Set the waveform automatic generation mode
AnnaBridge	189:f392fc9709a3	777	* for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	778	* @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
AnnaBridge	189:f392fc9709a3	779	* CR WAVE2 LL_DAC_SetWaveAutoGeneration
AnnaBridge	189:f392fc9709a3	780	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	781	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	782	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	783	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	784	*
AnnaBridge	189:f392fc9709a3	785	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	786	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	787	* @param WaveAutoGeneration This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	788	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
AnnaBridge	189:f392fc9709a3	789	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
AnnaBridge	189:f392fc9709a3	790	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
AnnaBridge	189:f392fc9709a3	791	* @retval None
AnnaBridge	189:f392fc9709a3	792	*/
AnnaBridge	189:f392fc9709a3	793	__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
AnnaBridge	189:f392fc9709a3	794	{
AnnaBridge	189:f392fc9709a3	795	MODIFY_REG(DACx->CR,
AnnaBridge	189:f392fc9709a3	796	DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	797	WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	798	}
AnnaBridge	189:f392fc9709a3	799
AnnaBridge	189:f392fc9709a3	800	/**
AnnaBridge	189:f392fc9709a3	801	* @brief Get the waveform automatic generation mode
AnnaBridge	189:f392fc9709a3	802	* for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	803	* @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
AnnaBridge	189:f392fc9709a3	804	* CR WAVE2 LL_DAC_GetWaveAutoGeneration
AnnaBridge	189:f392fc9709a3	805	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	806	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	807	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	808	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	809	*
AnnaBridge	189:f392fc9709a3	810	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	811	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	812	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	813	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
AnnaBridge	189:f392fc9709a3	814	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
AnnaBridge	189:f392fc9709a3	815	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
AnnaBridge	189:f392fc9709a3	816	*/
AnnaBridge	189:f392fc9709a3	817	__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	818	{
AnnaBridge	189:f392fc9709a3	819	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	820	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	821	);
AnnaBridge	189:f392fc9709a3	822	}
AnnaBridge	189:f392fc9709a3	823
AnnaBridge	189:f392fc9709a3	824	/**
AnnaBridge	189:f392fc9709a3	825	* @brief Set the noise waveform generation for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	826	* Noise mode and parameters LFSR (linear feedback shift register).
AnnaBridge	189:f392fc9709a3	827	* @note For wave generation to be effective, DAC channel
AnnaBridge	189:f392fc9709a3	828	* wave generation mode must be enabled using
AnnaBridge	189:f392fc9709a3	829	* function @ref LL_DAC_SetWaveAutoGeneration().
AnnaBridge	189:f392fc9709a3	830	* @note This setting can be set when the selected DAC channel is disabled
AnnaBridge	189:f392fc9709a3	831	* (otherwise, the setting operation is ignored).
AnnaBridge	189:f392fc9709a3	832	* @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
AnnaBridge	189:f392fc9709a3	833	* CR MAMP2 LL_DAC_SetWaveNoiseLFSR
AnnaBridge	189:f392fc9709a3	834	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	835	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	836	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	837	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	838	*
AnnaBridge	189:f392fc9709a3	839	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	840	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	841	* @param NoiseLFSRMask This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	842	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
AnnaBridge	189:f392fc9709a3	843	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
AnnaBridge	189:f392fc9709a3	844	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
AnnaBridge	189:f392fc9709a3	845	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
AnnaBridge	189:f392fc9709a3	846	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
AnnaBridge	189:f392fc9709a3	847	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
AnnaBridge	189:f392fc9709a3	848	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
AnnaBridge	189:f392fc9709a3	849	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
AnnaBridge	189:f392fc9709a3	850	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
AnnaBridge	189:f392fc9709a3	851	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
AnnaBridge	189:f392fc9709a3	852	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
AnnaBridge	189:f392fc9709a3	853	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
AnnaBridge	189:f392fc9709a3	854	* @retval None
AnnaBridge	189:f392fc9709a3	855	*/
AnnaBridge	189:f392fc9709a3	856	__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
AnnaBridge	189:f392fc9709a3	857	{
AnnaBridge	189:f392fc9709a3	858	MODIFY_REG(DACx->CR,
AnnaBridge	189:f392fc9709a3	859	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	860	NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	861	}
AnnaBridge	189:f392fc9709a3	862
AnnaBridge	189:f392fc9709a3	863	/**
AnnaBridge	189:f392fc9709a3	864	* @brief Set the noise waveform generation for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	865	* Noise mode and parameters LFSR (linear feedback shift register).
AnnaBridge	189:f392fc9709a3	866	* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
AnnaBridge	189:f392fc9709a3	867	* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
AnnaBridge	189:f392fc9709a3	868	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	869	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	870	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	871	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	872	*
AnnaBridge	189:f392fc9709a3	873	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	874	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	875	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	876	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
AnnaBridge	189:f392fc9709a3	877	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
AnnaBridge	189:f392fc9709a3	878	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
AnnaBridge	189:f392fc9709a3	879	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
AnnaBridge	189:f392fc9709a3	880	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
AnnaBridge	189:f392fc9709a3	881	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
AnnaBridge	189:f392fc9709a3	882	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
AnnaBridge	189:f392fc9709a3	883	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
AnnaBridge	189:f392fc9709a3	884	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
AnnaBridge	189:f392fc9709a3	885	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
AnnaBridge	189:f392fc9709a3	886	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
AnnaBridge	189:f392fc9709a3	887	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
AnnaBridge	189:f392fc9709a3	888	*/
AnnaBridge	189:f392fc9709a3	889	__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	890	{
AnnaBridge	189:f392fc9709a3	891	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	892	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	893	);
AnnaBridge	189:f392fc9709a3	894	}
AnnaBridge	189:f392fc9709a3	895
AnnaBridge	189:f392fc9709a3	896	/**
AnnaBridge	189:f392fc9709a3	897	* @brief Set the triangle waveform generation for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	898	* triangle mode and amplitude.
AnnaBridge	189:f392fc9709a3	899	* @note For wave generation to be effective, DAC channel
AnnaBridge	189:f392fc9709a3	900	* wave generation mode must be enabled using
AnnaBridge	189:f392fc9709a3	901	* function @ref LL_DAC_SetWaveAutoGeneration().
AnnaBridge	189:f392fc9709a3	902	* @note This setting can be set when the selected DAC channel is disabled
AnnaBridge	189:f392fc9709a3	903	* (otherwise, the setting operation is ignored).
AnnaBridge	189:f392fc9709a3	904	* @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
AnnaBridge	189:f392fc9709a3	905	* CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
AnnaBridge	189:f392fc9709a3	906	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	907	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	908	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	909	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	910	*
AnnaBridge	189:f392fc9709a3	911	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	912	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	913	* @param TriangleAmplitude This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	914	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
AnnaBridge	189:f392fc9709a3	915	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
AnnaBridge	189:f392fc9709a3	916	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
AnnaBridge	189:f392fc9709a3	917	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
AnnaBridge	189:f392fc9709a3	918	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
AnnaBridge	189:f392fc9709a3	919	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
AnnaBridge	189:f392fc9709a3	920	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
AnnaBridge	189:f392fc9709a3	921	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
AnnaBridge	189:f392fc9709a3	922	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
AnnaBridge	189:f392fc9709a3	923	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
AnnaBridge	189:f392fc9709a3	924	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
AnnaBridge	189:f392fc9709a3	925	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
AnnaBridge	189:f392fc9709a3	926	* @retval None
AnnaBridge	189:f392fc9709a3	927	*/
AnnaBridge	189:f392fc9709a3	928	__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
AnnaBridge	189:f392fc9709a3	929	{
AnnaBridge	189:f392fc9709a3	930	MODIFY_REG(DACx->CR,
AnnaBridge	189:f392fc9709a3	931	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	932	TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	933	}
AnnaBridge	189:f392fc9709a3	934
AnnaBridge	189:f392fc9709a3	935	/**
AnnaBridge	189:f392fc9709a3	936	* @brief Set the triangle waveform generation for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	937	* triangle mode and amplitude.
AnnaBridge	189:f392fc9709a3	938	* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
AnnaBridge	189:f392fc9709a3	939	* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
AnnaBridge	189:f392fc9709a3	940	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	941	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	942	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	943	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	944	*
AnnaBridge	189:f392fc9709a3	945	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	946	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	947	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	948	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
AnnaBridge	189:f392fc9709a3	949	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
AnnaBridge	189:f392fc9709a3	950	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
AnnaBridge	189:f392fc9709a3	951	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
AnnaBridge	189:f392fc9709a3	952	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
AnnaBridge	189:f392fc9709a3	953	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
AnnaBridge	189:f392fc9709a3	954	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
AnnaBridge	189:f392fc9709a3	955	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
AnnaBridge	189:f392fc9709a3	956	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
AnnaBridge	189:f392fc9709a3	957	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
AnnaBridge	189:f392fc9709a3	958	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
AnnaBridge	189:f392fc9709a3	959	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
AnnaBridge	189:f392fc9709a3	960	*/
AnnaBridge	189:f392fc9709a3	961	__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	962	{
AnnaBridge	189:f392fc9709a3	963	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	964	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	965	);
AnnaBridge	189:f392fc9709a3	966	}
AnnaBridge	189:f392fc9709a3	967
AnnaBridge	189:f392fc9709a3	968	/**
AnnaBridge	189:f392fc9709a3	969	* @brief Set the output for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	970	* @note This function set several features:
AnnaBridge	189:f392fc9709a3	971	* - mode normal or sample-and-hold
AnnaBridge	189:f392fc9709a3	972	* - buffer
AnnaBridge	189:f392fc9709a3	973	* - connection to GPIO or internal path.
AnnaBridge	189:f392fc9709a3	974	* These features can also be set individually using
AnnaBridge	189:f392fc9709a3	975	* dedicated functions:
AnnaBridge	189:f392fc9709a3	976	* - @ref LL_DAC_SetOutputBuffer()
AnnaBridge	189:f392fc9709a3	977	* - @ref LL_DAC_SetOutputMode()
AnnaBridge	189:f392fc9709a3	978	* - @ref LL_DAC_SetOutputConnection()
AnnaBridge	189:f392fc9709a3	979	* @note On this STM32 serie, output connection depends on output mode
AnnaBridge	189:f392fc9709a3	980	* (normal or sample and hold) and output buffer state.
AnnaBridge	189:f392fc9709a3	981	* - if output connection is set to internal path and output buffer
AnnaBridge	189:f392fc9709a3	982	* is enabled (whatever output mode):
AnnaBridge	189:f392fc9709a3	983	* output connection is also connected to GPIO pin
AnnaBridge	189:f392fc9709a3	984	* (both connections to GPIO pin and internal path).
AnnaBridge	189:f392fc9709a3	985	* - if output connection is set to GPIO pin, output buffer
AnnaBridge	189:f392fc9709a3	986	* is disabled, output mode set to sample and hold:
AnnaBridge	189:f392fc9709a3	987	* output connection is also connected to internal path
AnnaBridge	189:f392fc9709a3	988	* (both connections to GPIO pin and internal path).
AnnaBridge	189:f392fc9709a3	989	* @note Mode sample-and-hold requires an external capacitor
AnnaBridge	189:f392fc9709a3	990	* to be connected between DAC channel output and ground.
AnnaBridge	189:f392fc9709a3	991	* Capacitor value depends on load on DAC channel output and
AnnaBridge	189:f392fc9709a3	992	* sample-and-hold timings configured.
AnnaBridge	189:f392fc9709a3	993	* As indication, capacitor typical value is 100nF
AnnaBridge	189:f392fc9709a3	994	* (refer to device datasheet, parameter "CSH").
AnnaBridge	189:f392fc9709a3	995	* @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
AnnaBridge	189:f392fc9709a3	996	* CR MODE2 LL_DAC_ConfigOutput
AnnaBridge	189:f392fc9709a3	997	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	998	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	999	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1000	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1001	*
AnnaBridge	189:f392fc9709a3	1002	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1003	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1004	* @param OutputMode This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1005	* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
AnnaBridge	189:f392fc9709a3	1006	* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
AnnaBridge	189:f392fc9709a3	1007	* @param OutputBuffer This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1008	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
AnnaBridge	189:f392fc9709a3	1009	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
AnnaBridge	189:f392fc9709a3	1010	* @param OutputConnection This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1011	* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
AnnaBridge	189:f392fc9709a3	1012	* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
AnnaBridge	189:f392fc9709a3	1013	* @retval None
AnnaBridge	189:f392fc9709a3	1014	*/
AnnaBridge	189:f392fc9709a3	1015	__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
AnnaBridge	189:f392fc9709a3	1016	{
AnnaBridge	189:f392fc9709a3	1017	MODIFY_REG(DACx->MCR,
AnnaBridge	189:f392fc9709a3	1018	(DAC_MCR_MODE1_2 \| DAC_MCR_MODE1_1 \| DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	1019	(OutputMode \| OutputBuffer \| OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1020	}
AnnaBridge	189:f392fc9709a3	1021
AnnaBridge	189:f392fc9709a3	1022	/**
AnnaBridge	189:f392fc9709a3	1023	* @brief Set the output mode normal or sample-and-hold
AnnaBridge	189:f392fc9709a3	1024	* for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1025	* @note Mode sample-and-hold requires an external capacitor
AnnaBridge	189:f392fc9709a3	1026	* to be connected between DAC channel output and ground.
AnnaBridge	189:f392fc9709a3	1027	* Capacitor value depends on load on DAC channel output and
AnnaBridge	189:f392fc9709a3	1028	* sample-and-hold timings configured.
AnnaBridge	189:f392fc9709a3	1029	* As indication, capacitor typical value is 100nF
AnnaBridge	189:f392fc9709a3	1030	* (refer to device datasheet, parameter "CSH").
AnnaBridge	189:f392fc9709a3	1031	* @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
AnnaBridge	189:f392fc9709a3	1032	* CR MODE2 LL_DAC_SetOutputMode
AnnaBridge	189:f392fc9709a3	1033	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1034	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1035	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1036	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1037	*
AnnaBridge	189:f392fc9709a3	1038	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1039	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1040	* @param OutputMode This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1041	* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
AnnaBridge	189:f392fc9709a3	1042	* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
AnnaBridge	189:f392fc9709a3	1043	* @retval None
AnnaBridge	189:f392fc9709a3	1044	*/
AnnaBridge	189:f392fc9709a3	1045	__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
AnnaBridge	189:f392fc9709a3	1046	{
AnnaBridge	189:f392fc9709a3	1047	MODIFY_REG(DACx->MCR,
AnnaBridge	189:f392fc9709a3	1048	DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	1049	OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1050	}
AnnaBridge	189:f392fc9709a3	1051
AnnaBridge	189:f392fc9709a3	1052	/**
AnnaBridge	189:f392fc9709a3	1053	* @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1054	* @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
AnnaBridge	189:f392fc9709a3	1055	* CR MODE2 LL_DAC_GetOutputMode
AnnaBridge	189:f392fc9709a3	1056	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1057	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1058	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1059	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1060	*
AnnaBridge	189:f392fc9709a3	1061	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1062	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1063	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1064	* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
AnnaBridge	189:f392fc9709a3	1065	* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
AnnaBridge	189:f392fc9709a3	1066	*/
AnnaBridge	189:f392fc9709a3	1067	__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1068	{
AnnaBridge	189:f392fc9709a3	1069	return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	1070	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	1071	);
AnnaBridge	189:f392fc9709a3	1072	}
AnnaBridge	189:f392fc9709a3	1073
AnnaBridge	189:f392fc9709a3	1074	/**
AnnaBridge	189:f392fc9709a3	1075	* @brief Set the output buffer for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1076	* @note On this STM32 serie, when buffer is enabled, its offset can be
AnnaBridge	189:f392fc9709a3	1077	* trimmed: factory calibration default values can be
AnnaBridge	189:f392fc9709a3	1078	* replaced by user trimming values, using function
AnnaBridge	189:f392fc9709a3	1079	* @ref LL_DAC_SetTrimmingValue().
AnnaBridge	189:f392fc9709a3	1080	* @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
AnnaBridge	189:f392fc9709a3	1081	* CR MODE2 LL_DAC_SetOutputBuffer
AnnaBridge	189:f392fc9709a3	1082	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1083	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1084	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1085	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1086	*
AnnaBridge	189:f392fc9709a3	1087	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1088	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1089	* @param OutputBuffer This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1090	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
AnnaBridge	189:f392fc9709a3	1091	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
AnnaBridge	189:f392fc9709a3	1092	* @retval None
AnnaBridge	189:f392fc9709a3	1093	*/
AnnaBridge	189:f392fc9709a3	1094	__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
AnnaBridge	189:f392fc9709a3	1095	{
AnnaBridge	189:f392fc9709a3	1096	MODIFY_REG(DACx->MCR,
AnnaBridge	189:f392fc9709a3	1097	DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	1098	OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1099	}
AnnaBridge	189:f392fc9709a3	1100
AnnaBridge	189:f392fc9709a3	1101	/**
AnnaBridge	189:f392fc9709a3	1102	* @brief Get the output buffer state for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1103	* @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
AnnaBridge	189:f392fc9709a3	1104	* CR MODE2 LL_DAC_GetOutputBuffer
AnnaBridge	189:f392fc9709a3	1105	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1106	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1107	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1108	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1109	*
AnnaBridge	189:f392fc9709a3	1110	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1111	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1112	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1113	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
AnnaBridge	189:f392fc9709a3	1114	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
AnnaBridge	189:f392fc9709a3	1115	*/
AnnaBridge	189:f392fc9709a3	1116	__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1117	{
AnnaBridge	189:f392fc9709a3	1118	return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	1119	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	1120	);
AnnaBridge	189:f392fc9709a3	1121	}
AnnaBridge	189:f392fc9709a3	1122
AnnaBridge	189:f392fc9709a3	1123	/**
AnnaBridge	189:f392fc9709a3	1124	* @brief Set the output connection for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1125	* @note On this STM32 serie, output connection depends on output mode (normal or
AnnaBridge	189:f392fc9709a3	1126	* sample and hold) and output buffer state.
AnnaBridge	189:f392fc9709a3	1127	* - if output connection is set to internal path and output buffer
AnnaBridge	189:f392fc9709a3	1128	* is enabled (whatever output mode):
AnnaBridge	189:f392fc9709a3	1129	* output connection is also connected to GPIO pin
AnnaBridge	189:f392fc9709a3	1130	* (both connections to GPIO pin and internal path).
AnnaBridge	189:f392fc9709a3	1131	* - if output connection is set to GPIO pin, output buffer
AnnaBridge	189:f392fc9709a3	1132	* is disabled, output mode set to sample and hold:
AnnaBridge	189:f392fc9709a3	1133	* output connection is also connected to internal path
AnnaBridge	189:f392fc9709a3	1134	* (both connections to GPIO pin and internal path).
AnnaBridge	189:f392fc9709a3	1135	* @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
AnnaBridge	189:f392fc9709a3	1136	* CR MODE2 LL_DAC_SetOutputConnection
AnnaBridge	189:f392fc9709a3	1137	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1138	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1139	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1140	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1141	*
AnnaBridge	189:f392fc9709a3	1142	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1143	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1144	* @param OutputConnection This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1145	* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
AnnaBridge	189:f392fc9709a3	1146	* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
AnnaBridge	189:f392fc9709a3	1147	* @retval None
AnnaBridge	189:f392fc9709a3	1148	*/
AnnaBridge	189:f392fc9709a3	1149	__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
AnnaBridge	189:f392fc9709a3	1150	{
AnnaBridge	189:f392fc9709a3	1151	MODIFY_REG(DACx->MCR,
AnnaBridge	189:f392fc9709a3	1152	DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	1153	OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1154	}
AnnaBridge	189:f392fc9709a3	1155
AnnaBridge	189:f392fc9709a3	1156	/**
AnnaBridge	189:f392fc9709a3	1157	* @brief Get the output connection for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1158	* @note On this STM32 serie, output connection depends on output mode (normal or
AnnaBridge	189:f392fc9709a3	1159	* sample and hold) and output buffer state.
AnnaBridge	189:f392fc9709a3	1160	* - if output connection is set to internal path and output buffer
AnnaBridge	189:f392fc9709a3	1161	* is enabled (whatever output mode):
AnnaBridge	189:f392fc9709a3	1162	* output connection is also connected to GPIO pin
AnnaBridge	189:f392fc9709a3	1163	* (both connections to GPIO pin and internal path).
AnnaBridge	189:f392fc9709a3	1164	* - if output connection is set to GPIO pin, output buffer
AnnaBridge	189:f392fc9709a3	1165	* is disabled, output mode set to sample and hold:
AnnaBridge	189:f392fc9709a3	1166	* output connection is also connected to internal path
AnnaBridge	189:f392fc9709a3	1167	* (both connections to GPIO pin and internal path).
AnnaBridge	189:f392fc9709a3	1168	* @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
AnnaBridge	189:f392fc9709a3	1169	* CR MODE2 LL_DAC_GetOutputConnection
AnnaBridge	189:f392fc9709a3	1170	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1171	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1172	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1173	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1174	*
AnnaBridge	189:f392fc9709a3	1175	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1176	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1177	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1178	* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
AnnaBridge	189:f392fc9709a3	1179	* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
AnnaBridge	189:f392fc9709a3	1180	*/
AnnaBridge	189:f392fc9709a3	1181	__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1182	{
AnnaBridge	189:f392fc9709a3	1183	return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	1184	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	1185	);
AnnaBridge	189:f392fc9709a3	1186	}
AnnaBridge	189:f392fc9709a3	1187
AnnaBridge	189:f392fc9709a3	1188	/**
AnnaBridge	189:f392fc9709a3	1189	* @brief Set the sample-and-hold timing for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	1190	* sample time
AnnaBridge	189:f392fc9709a3	1191	* @note Sample time must be set when DAC channel is disabled
AnnaBridge	189:f392fc9709a3	1192	* or during DAC operation when DAC channel flag BWSTx is reset,
AnnaBridge	189:f392fc9709a3	1193	* otherwise the setting is ignored.
AnnaBridge	189:f392fc9709a3	1194	* Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
AnnaBridge	189:f392fc9709a3	1195	* @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
AnnaBridge	189:f392fc9709a3	1196	* SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
AnnaBridge	189:f392fc9709a3	1197	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1198	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1199	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1200	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1201	*
AnnaBridge	189:f392fc9709a3	1202	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1203	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1204	* @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
AnnaBridge	189:f392fc9709a3	1205	* @retval None
AnnaBridge	189:f392fc9709a3	1206	*/
AnnaBridge	189:f392fc9709a3	1207	__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
AnnaBridge	189:f392fc9709a3	1208	{
AnnaBridge	189:f392fc9709a3	1209	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1210
AnnaBridge	189:f392fc9709a3	1211	MODIFY_REG(*preg,
AnnaBridge	189:f392fc9709a3	1212	DAC_SHSR1_TSAMPLE1,
AnnaBridge	189:f392fc9709a3	1213	SampleTime);
AnnaBridge	189:f392fc9709a3	1214	}
AnnaBridge	189:f392fc9709a3	1215
AnnaBridge	189:f392fc9709a3	1216	/**
AnnaBridge	189:f392fc9709a3	1217	* @brief Get the sample-and-hold timing for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	1218	* sample time
AnnaBridge	189:f392fc9709a3	1219	* @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
AnnaBridge	189:f392fc9709a3	1220	* SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
AnnaBridge	189:f392fc9709a3	1221	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1222	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1223	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1224	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1225	*
AnnaBridge	189:f392fc9709a3	1226	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1227	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1228	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
AnnaBridge	189:f392fc9709a3	1229	*/
AnnaBridge	189:f392fc9709a3	1230	__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1231	{
AnnaBridge	189:f392fc9709a3	1232	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1233
AnnaBridge	189:f392fc9709a3	1234	return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
AnnaBridge	189:f392fc9709a3	1235	}
AnnaBridge	189:f392fc9709a3	1236
AnnaBridge	189:f392fc9709a3	1237	/**
AnnaBridge	189:f392fc9709a3	1238	* @brief Set the sample-and-hold timing for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	1239	* hold time
AnnaBridge	189:f392fc9709a3	1240	* @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
AnnaBridge	189:f392fc9709a3	1241	* SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
AnnaBridge	189:f392fc9709a3	1242	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1243	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1244	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1245	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1246	*
AnnaBridge	189:f392fc9709a3	1247	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1248	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1249	* @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
AnnaBridge	189:f392fc9709a3	1250	* @retval None
AnnaBridge	189:f392fc9709a3	1251	*/
AnnaBridge	189:f392fc9709a3	1252	__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
AnnaBridge	189:f392fc9709a3	1253	{
AnnaBridge	189:f392fc9709a3	1254	MODIFY_REG(DACx->SHHR,
AnnaBridge	189:f392fc9709a3	1255	DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	1256	HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1257	}
AnnaBridge	189:f392fc9709a3	1258
AnnaBridge	189:f392fc9709a3	1259	/**
AnnaBridge	189:f392fc9709a3	1260	* @brief Get the sample-and-hold timing for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	1261	* hold time
AnnaBridge	189:f392fc9709a3	1262	* @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
AnnaBridge	189:f392fc9709a3	1263	* SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
AnnaBridge	189:f392fc9709a3	1264	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1265	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1266	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1267	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1268	*
AnnaBridge	189:f392fc9709a3	1269	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1270	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1271	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
AnnaBridge	189:f392fc9709a3	1272	*/
AnnaBridge	189:f392fc9709a3	1273	__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1274	{
AnnaBridge	189:f392fc9709a3	1275	return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	1276	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	1277	);
AnnaBridge	189:f392fc9709a3	1278	}
AnnaBridge	189:f392fc9709a3	1279
AnnaBridge	189:f392fc9709a3	1280	/**
AnnaBridge	189:f392fc9709a3	1281	* @brief Set the sample-and-hold timing for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	1282	* refresh time
AnnaBridge	189:f392fc9709a3	1283	* @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
AnnaBridge	189:f392fc9709a3	1284	* SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
AnnaBridge	189:f392fc9709a3	1285	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1286	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1287	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1288	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1289	*
AnnaBridge	189:f392fc9709a3	1290	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1291	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1292	* @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	1293	* @retval None
AnnaBridge	189:f392fc9709a3	1294	*/
AnnaBridge	189:f392fc9709a3	1295	__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
AnnaBridge	189:f392fc9709a3	1296	{
AnnaBridge	189:f392fc9709a3	1297	MODIFY_REG(DACx->SHRR,
AnnaBridge	189:f392fc9709a3	1298	DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	1299	RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1300	}
AnnaBridge	189:f392fc9709a3	1301
AnnaBridge	189:f392fc9709a3	1302	/**
AnnaBridge	189:f392fc9709a3	1303	* @brief Get the sample-and-hold timing for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	1304	* refresh time
AnnaBridge	189:f392fc9709a3	1305	* @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
AnnaBridge	189:f392fc9709a3	1306	* SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
AnnaBridge	189:f392fc9709a3	1307	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1308	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1309	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1310	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1311	*
AnnaBridge	189:f392fc9709a3	1312	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1313	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1314	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	1315	*/
AnnaBridge	189:f392fc9709a3	1316	__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1317	{
AnnaBridge	189:f392fc9709a3	1318	return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	1319	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	1320	);
AnnaBridge	189:f392fc9709a3	1321	}
AnnaBridge	189:f392fc9709a3	1322
AnnaBridge	189:f392fc9709a3	1323	/**
AnnaBridge	189:f392fc9709a3	1324	* @}
AnnaBridge	189:f392fc9709a3	1325	*/
AnnaBridge	189:f392fc9709a3	1326
AnnaBridge	189:f392fc9709a3	1327	/** @defgroup DAC_LL_EF_Configuration_Legacy_Functions DAC configuration, legacy functions name
AnnaBridge	189:f392fc9709a3	1328	* @{
AnnaBridge	189:f392fc9709a3	1329	*/
AnnaBridge	189:f392fc9709a3	1330	/* Old functions name kept for legacy purpose, to be replaced by the */
AnnaBridge	189:f392fc9709a3	1331	/* current functions name. */
AnnaBridge	189:f392fc9709a3	1332	__STATIC_INLINE void LL_DAC_SetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveMode)
AnnaBridge	189:f392fc9709a3	1333	{
AnnaBridge	189:f392fc9709a3	1334	LL_DAC_SetWaveAutoGeneration(DACx, DAC_Channel, WaveMode);
AnnaBridge	189:f392fc9709a3	1335	}
AnnaBridge	189:f392fc9709a3	1336	__STATIC_INLINE uint32_t LL_DAC_GetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1337	{
AnnaBridge	189:f392fc9709a3	1338	return LL_DAC_GetWaveAutoGeneration(DACx, DAC_Channel);
AnnaBridge	189:f392fc9709a3	1339	}
AnnaBridge	189:f392fc9709a3	1340
AnnaBridge	189:f392fc9709a3	1341	/**
AnnaBridge	189:f392fc9709a3	1342	* @}
AnnaBridge	189:f392fc9709a3	1343	*/
AnnaBridge	189:f392fc9709a3	1344
AnnaBridge	189:f392fc9709a3	1345	/** @defgroup DAC_LL_EF_DMA_Management DMA Management
AnnaBridge	189:f392fc9709a3	1346	* @{
AnnaBridge	189:f392fc9709a3	1347	*/
AnnaBridge	189:f392fc9709a3	1348
AnnaBridge	189:f392fc9709a3	1349	/**
AnnaBridge	189:f392fc9709a3	1350	* @brief Enable DAC DMA transfer request of the selected channel.
AnnaBridge	189:f392fc9709a3	1351	* @note To configure DMA source address (peripheral address),
AnnaBridge	189:f392fc9709a3	1352	* use function @ref LL_DAC_DMA_GetRegAddr().
AnnaBridge	189:f392fc9709a3	1353	* @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
AnnaBridge	189:f392fc9709a3	1354	* CR DMAEN2 LL_DAC_EnableDMAReq
AnnaBridge	189:f392fc9709a3	1355	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1356	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1357	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1358	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1359	*
AnnaBridge	189:f392fc9709a3	1360	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1361	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1362	* @retval None
AnnaBridge	189:f392fc9709a3	1363	*/
AnnaBridge	189:f392fc9709a3	1364	__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1365	{
AnnaBridge	189:f392fc9709a3	1366	SET_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	1367	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1368	}
AnnaBridge	189:f392fc9709a3	1369
AnnaBridge	189:f392fc9709a3	1370	/**
AnnaBridge	189:f392fc9709a3	1371	* @brief Disable DAC DMA transfer request of the selected channel.
AnnaBridge	189:f392fc9709a3	1372	* @note To configure DMA source address (peripheral address),
AnnaBridge	189:f392fc9709a3	1373	* use function @ref LL_DAC_DMA_GetRegAddr().
AnnaBridge	189:f392fc9709a3	1374	* @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
AnnaBridge	189:f392fc9709a3	1375	* CR DMAEN2 LL_DAC_DisableDMAReq
AnnaBridge	189:f392fc9709a3	1376	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1377	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1378	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1379	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1380	*
AnnaBridge	189:f392fc9709a3	1381	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1382	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1383	* @retval None
AnnaBridge	189:f392fc9709a3	1384	*/
AnnaBridge	189:f392fc9709a3	1385	__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1386	{
AnnaBridge	189:f392fc9709a3	1387	CLEAR_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	1388	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1389	}
AnnaBridge	189:f392fc9709a3	1390
AnnaBridge	189:f392fc9709a3	1391	/**
AnnaBridge	189:f392fc9709a3	1392	* @brief Get DAC DMA transfer request state of the selected channel.
AnnaBridge	189:f392fc9709a3	1393	* (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
AnnaBridge	189:f392fc9709a3	1394	* @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
AnnaBridge	189:f392fc9709a3	1395	* CR DMAEN2 LL_DAC_IsDMAReqEnabled
AnnaBridge	189:f392fc9709a3	1396	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1397	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1398	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1399	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1400	*
AnnaBridge	189:f392fc9709a3	1401	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1402	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1403	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1404	*/
AnnaBridge	189:f392fc9709a3	1405	__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1406	{
AnnaBridge	189:f392fc9709a3	1407	return (READ_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	1408	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	1409	== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
AnnaBridge	189:f392fc9709a3	1410	}
AnnaBridge	189:f392fc9709a3	1411
AnnaBridge	189:f392fc9709a3	1412	/**
AnnaBridge	189:f392fc9709a3	1413	* @brief Function to help to configure DMA transfer to DAC: retrieve the
AnnaBridge	189:f392fc9709a3	1414	* DAC register address from DAC instance and a list of DAC registers
AnnaBridge	189:f392fc9709a3	1415	* intended to be used (most commonly) with DMA transfer.
AnnaBridge	189:f392fc9709a3	1416	* @note These DAC registers are data holding registers:
AnnaBridge	189:f392fc9709a3	1417	* when DAC conversion is requested, DAC generates a DMA transfer
AnnaBridge	189:f392fc9709a3	1418	* request to have data available in DAC data holding registers.
AnnaBridge	189:f392fc9709a3	1419	* @note This macro is intended to be used with LL DMA driver, refer to
AnnaBridge	189:f392fc9709a3	1420	* function "LL_DMA_ConfigAddresses()".
AnnaBridge	189:f392fc9709a3	1421	* Example:
AnnaBridge	189:f392fc9709a3	1422	* LL_DMA_ConfigAddresses(DMA1,
AnnaBridge	189:f392fc9709a3	1423	* LL_DMA_CHANNEL_1,
AnnaBridge	189:f392fc9709a3	1424	* (uint32_t)&< array or variable >,
AnnaBridge	189:f392fc9709a3	1425	* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
AnnaBridge	189:f392fc9709a3	1426	* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
AnnaBridge	189:f392fc9709a3	1427	* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	189:f392fc9709a3	1428	* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	189:f392fc9709a3	1429	* DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	189:f392fc9709a3	1430	* DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	189:f392fc9709a3	1431	* DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	189:f392fc9709a3	1432	* DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
AnnaBridge	189:f392fc9709a3	1433	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1434	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1435	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1436	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1437	*
AnnaBridge	189:f392fc9709a3	1438	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1439	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1440	* @param Register This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1441	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
AnnaBridge	189:f392fc9709a3	1442	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
AnnaBridge	189:f392fc9709a3	1443	* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
AnnaBridge	189:f392fc9709a3	1444	* @retval DAC register address
AnnaBridge	189:f392fc9709a3	1445	*/
AnnaBridge	189:f392fc9709a3	1446	__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
AnnaBridge	189:f392fc9709a3	1447	{
AnnaBridge	189:f392fc9709a3	1448	/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
AnnaBridge	189:f392fc9709a3	1449	/* DAC channel selected. */
AnnaBridge	189:f392fc9709a3	1450	return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
AnnaBridge	189:f392fc9709a3	1451	}
AnnaBridge	189:f392fc9709a3	1452	/**
AnnaBridge	189:f392fc9709a3	1453	* @}
AnnaBridge	189:f392fc9709a3	1454	*/
AnnaBridge	189:f392fc9709a3	1455
AnnaBridge	189:f392fc9709a3	1456	/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
AnnaBridge	189:f392fc9709a3	1457	* @{
AnnaBridge	189:f392fc9709a3	1458	*/
AnnaBridge	189:f392fc9709a3	1459
AnnaBridge	189:f392fc9709a3	1460	/**
AnnaBridge	189:f392fc9709a3	1461	* @brief Enable DAC selected channel.
AnnaBridge	189:f392fc9709a3	1462	* @rmtoll CR EN1 LL_DAC_Enable\n
AnnaBridge	189:f392fc9709a3	1463	* CR EN2 LL_DAC_Enable
AnnaBridge	189:f392fc9709a3	1464	* @note After enable from off state, DAC channel requires a delay
AnnaBridge	189:f392fc9709a3	1465	* for output voltage to reach accuracy +/- 1 LSB.
AnnaBridge	189:f392fc9709a3	1466	* Refer to device datasheet, parameter "tWAKEUP".
AnnaBridge	189:f392fc9709a3	1467	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1468	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1469	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1470	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1471	*
AnnaBridge	189:f392fc9709a3	1472	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1473	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1474	* @retval None
AnnaBridge	189:f392fc9709a3	1475	*/
AnnaBridge	189:f392fc9709a3	1476	__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1477	{
AnnaBridge	189:f392fc9709a3	1478	SET_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	1479	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1480	}
AnnaBridge	189:f392fc9709a3	1481
AnnaBridge	189:f392fc9709a3	1482	/**
AnnaBridge	189:f392fc9709a3	1483	* @brief Disable DAC selected channel.
AnnaBridge	189:f392fc9709a3	1484	* @rmtoll CR EN1 LL_DAC_Disable\n
AnnaBridge	189:f392fc9709a3	1485	* CR EN2 LL_DAC_Disable
AnnaBridge	189:f392fc9709a3	1486	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1487	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1488	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1489	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1490	*
AnnaBridge	189:f392fc9709a3	1491	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1492	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1493	* @retval None
AnnaBridge	189:f392fc9709a3	1494	*/
AnnaBridge	189:f392fc9709a3	1495	__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1496	{
AnnaBridge	189:f392fc9709a3	1497	CLEAR_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	1498	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1499	}
AnnaBridge	189:f392fc9709a3	1500
AnnaBridge	189:f392fc9709a3	1501	/**
AnnaBridge	189:f392fc9709a3	1502	* @brief Get DAC enable state of the selected channel.
AnnaBridge	189:f392fc9709a3	1503	* (0: DAC channel is disabled, 1: DAC channel is enabled)
AnnaBridge	189:f392fc9709a3	1504	* @rmtoll CR EN1 LL_DAC_IsEnabled\n
AnnaBridge	189:f392fc9709a3	1505	* CR EN2 LL_DAC_IsEnabled
AnnaBridge	189:f392fc9709a3	1506	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1507	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1508	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1509	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1510	*
AnnaBridge	189:f392fc9709a3	1511	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1512	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1513	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1514	*/
AnnaBridge	189:f392fc9709a3	1515	__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1516	{
AnnaBridge	189:f392fc9709a3	1517	return (READ_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	1518	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	1519	== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
AnnaBridge	189:f392fc9709a3	1520	}
AnnaBridge	189:f392fc9709a3	1521
AnnaBridge	189:f392fc9709a3	1522	/**
AnnaBridge	189:f392fc9709a3	1523	* @brief Enable DAC trigger of the selected channel.
AnnaBridge	189:f392fc9709a3	1524	* @note - If DAC trigger is disabled, DAC conversion is performed
AnnaBridge	189:f392fc9709a3	1525	* automatically once the data holding register is updated,
AnnaBridge	189:f392fc9709a3	1526	* using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
AnnaBridge	189:f392fc9709a3	1527	* @ref LL_DAC_ConvertData12RightAligned(), ...
AnnaBridge	189:f392fc9709a3	1528	* - If DAC trigger is enabled, DAC conversion is performed
AnnaBridge	189:f392fc9709a3	1529	* only when a hardware of software trigger event is occurring.
AnnaBridge	189:f392fc9709a3	1530	* Select trigger source using
AnnaBridge	189:f392fc9709a3	1531	* function @ref LL_DAC_SetTriggerSource().
AnnaBridge	189:f392fc9709a3	1532	* @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
AnnaBridge	189:f392fc9709a3	1533	* CR TEN2 LL_DAC_EnableTrigger
AnnaBridge	189:f392fc9709a3	1534	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1535	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1536	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1537	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1538	*
AnnaBridge	189:f392fc9709a3	1539	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1540	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1541	* @retval None
AnnaBridge	189:f392fc9709a3	1542	*/
AnnaBridge	189:f392fc9709a3	1543	__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1544	{
AnnaBridge	189:f392fc9709a3	1545	SET_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	1546	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1547	}
AnnaBridge	189:f392fc9709a3	1548
AnnaBridge	189:f392fc9709a3	1549	/**
AnnaBridge	189:f392fc9709a3	1550	* @brief Disable DAC trigger of the selected channel.
AnnaBridge	189:f392fc9709a3	1551	* @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
AnnaBridge	189:f392fc9709a3	1552	* CR TEN2 LL_DAC_DisableTrigger
AnnaBridge	189:f392fc9709a3	1553	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1554	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1555	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1556	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1557	*
AnnaBridge	189:f392fc9709a3	1558	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1559	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1560	* @retval None
AnnaBridge	189:f392fc9709a3	1561	*/
AnnaBridge	189:f392fc9709a3	1562	__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1563	{
AnnaBridge	189:f392fc9709a3	1564	CLEAR_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	1565	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1566	}
AnnaBridge	189:f392fc9709a3	1567
AnnaBridge	189:f392fc9709a3	1568	/**
AnnaBridge	189:f392fc9709a3	1569	* @brief Get DAC trigger state of the selected channel.
AnnaBridge	189:f392fc9709a3	1570	* (0: DAC trigger is disabled, 1: DAC trigger is enabled)
AnnaBridge	189:f392fc9709a3	1571	* @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
AnnaBridge	189:f392fc9709a3	1572	* CR TEN2 LL_DAC_IsTriggerEnabled
AnnaBridge	189:f392fc9709a3	1573	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1574	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1575	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1576	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1577	*
AnnaBridge	189:f392fc9709a3	1578	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1579	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1580	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1581	*/
AnnaBridge	189:f392fc9709a3	1582	__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1583	{
AnnaBridge	189:f392fc9709a3	1584	return (READ_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	1585	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	1586	== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
AnnaBridge	189:f392fc9709a3	1587	}
AnnaBridge	189:f392fc9709a3	1588
AnnaBridge	189:f392fc9709a3	1589	/**
AnnaBridge	189:f392fc9709a3	1590	* @brief Trig DAC conversion by software for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1591	* @note Preliminarily, DAC trigger must be set to software trigger
AnnaBridge	189:f392fc9709a3	1592	* using function @ref LL_DAC_SetTriggerSource()
AnnaBridge	189:f392fc9709a3	1593	* with parameter "LL_DAC_TRIGGER_SOFTWARE".
AnnaBridge	189:f392fc9709a3	1594	* and DAC trigger must be enabled using
AnnaBridge	189:f392fc9709a3	1595	* function @ref LL_DAC_EnableTrigger().
AnnaBridge	189:f392fc9709a3	1596	* @note For devices featuring DAC with 2 channels: this function
AnnaBridge	189:f392fc9709a3	1597	* can perform a SW start of both DAC channels simultaneously.
AnnaBridge	189:f392fc9709a3	1598	* Two channels can be selected as parameter.
AnnaBridge	189:f392fc9709a3	1599	* Example: (LL_DAC_CHANNEL_1 \| LL_DAC_CHANNEL_2)
AnnaBridge	189:f392fc9709a3	1600	* @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
AnnaBridge	189:f392fc9709a3	1601	* SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
AnnaBridge	189:f392fc9709a3	1602	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1603	* @param DAC_Channel This parameter can a combination of the following values:
AnnaBridge	189:f392fc9709a3	1604	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1605	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1606	*
AnnaBridge	189:f392fc9709a3	1607	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1608	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1609	* @retval None
AnnaBridge	189:f392fc9709a3	1610	*/
AnnaBridge	189:f392fc9709a3	1611	__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1612	{
AnnaBridge	189:f392fc9709a3	1613	SET_BIT(DACx->SWTRIGR,
AnnaBridge	189:f392fc9709a3	1614	(DAC_Channel & DAC_SWTR_CHX_MASK));
AnnaBridge	189:f392fc9709a3	1615	}
AnnaBridge	189:f392fc9709a3	1616
AnnaBridge	189:f392fc9709a3	1617	/**
AnnaBridge	189:f392fc9709a3	1618	* @brief Set the data to be loaded in the data holding register
AnnaBridge	189:f392fc9709a3	1619	* in format 12 bits left alignment (LSB aligned on bit 0),
AnnaBridge	189:f392fc9709a3	1620	* for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1621	* @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
AnnaBridge	189:f392fc9709a3	1622	* DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
AnnaBridge	189:f392fc9709a3	1623	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1624	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1625	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1626	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1627	*
AnnaBridge	189:f392fc9709a3	1628	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1629	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1630	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1631	* @retval None
AnnaBridge	189:f392fc9709a3	1632	*/
AnnaBridge	189:f392fc9709a3	1633	__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge	189:f392fc9709a3	1634	{
AnnaBridge	189:f392fc9709a3	1635	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1636
AnnaBridge	189:f392fc9709a3	1637	MODIFY_REG(*preg,
AnnaBridge	189:f392fc9709a3	1638	DAC_DHR12R1_DACC1DHR,
AnnaBridge	189:f392fc9709a3	1639	Data);
AnnaBridge	189:f392fc9709a3	1640	}
AnnaBridge	189:f392fc9709a3	1641
AnnaBridge	189:f392fc9709a3	1642	/**
AnnaBridge	189:f392fc9709a3	1643	* @brief Set the data to be loaded in the data holding register
AnnaBridge	189:f392fc9709a3	1644	* in format 12 bits left alignment (MSB aligned on bit 15),
AnnaBridge	189:f392fc9709a3	1645	* for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1646	* @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
AnnaBridge	189:f392fc9709a3	1647	* DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
AnnaBridge	189:f392fc9709a3	1648	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1649	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1650	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1651	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1652	*
AnnaBridge	189:f392fc9709a3	1653	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1654	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1655	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1656	* @retval None
AnnaBridge	189:f392fc9709a3	1657	*/
AnnaBridge	189:f392fc9709a3	1658	__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge	189:f392fc9709a3	1659	{
AnnaBridge	189:f392fc9709a3	1660	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1661
AnnaBridge	189:f392fc9709a3	1662	MODIFY_REG(*preg,
AnnaBridge	189:f392fc9709a3	1663	DAC_DHR12L1_DACC1DHR,
AnnaBridge	189:f392fc9709a3	1664	Data);
AnnaBridge	189:f392fc9709a3	1665	}
AnnaBridge	189:f392fc9709a3	1666
AnnaBridge	189:f392fc9709a3	1667	/**
AnnaBridge	189:f392fc9709a3	1668	* @brief Set the data to be loaded in the data holding register
AnnaBridge	189:f392fc9709a3	1669	* in format 8 bits left alignment (LSB aligned on bit 0),
AnnaBridge	189:f392fc9709a3	1670	* for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1671	* @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
AnnaBridge	189:f392fc9709a3	1672	* DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
AnnaBridge	189:f392fc9709a3	1673	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1674	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1675	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1676	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1677	*
AnnaBridge	189:f392fc9709a3	1678	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1679	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1680	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	1681	* @retval None
AnnaBridge	189:f392fc9709a3	1682	*/
AnnaBridge	189:f392fc9709a3	1683	__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge	189:f392fc9709a3	1684	{
AnnaBridge	189:f392fc9709a3	1685	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1686
AnnaBridge	189:f392fc9709a3	1687	MODIFY_REG(*preg,
AnnaBridge	189:f392fc9709a3	1688	DAC_DHR8R1_DACC1DHR,
AnnaBridge	189:f392fc9709a3	1689	Data);
AnnaBridge	189:f392fc9709a3	1690	}
AnnaBridge	189:f392fc9709a3	1691
AnnaBridge	189:f392fc9709a3	1692	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1693	/**
AnnaBridge	189:f392fc9709a3	1694	* @brief Set the data to be loaded in the data holding register
AnnaBridge	189:f392fc9709a3	1695	* in format 12 bits left alignment (LSB aligned on bit 0),
AnnaBridge	189:f392fc9709a3	1696	* for both DAC channels.
AnnaBridge	189:f392fc9709a3	1697	* @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
AnnaBridge	189:f392fc9709a3	1698	* DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
AnnaBridge	189:f392fc9709a3	1699	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1700	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1701	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1702	* @retval None
AnnaBridge	189:f392fc9709a3	1703	*/
AnnaBridge	189:f392fc9709a3	1704	__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge	189:f392fc9709a3	1705	{
AnnaBridge	189:f392fc9709a3	1706	MODIFY_REG(DACx->DHR12RD,
AnnaBridge	189:f392fc9709a3	1707	(DAC_DHR12RD_DACC2DHR \| DAC_DHR12RD_DACC1DHR),
AnnaBridge	189:f392fc9709a3	1708	((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
AnnaBridge	189:f392fc9709a3	1709	}
AnnaBridge	189:f392fc9709a3	1710
AnnaBridge	189:f392fc9709a3	1711	/**
AnnaBridge	189:f392fc9709a3	1712	* @brief Set the data to be loaded in the data holding register
AnnaBridge	189:f392fc9709a3	1713	* in format 12 bits left alignment (MSB aligned on bit 15),
AnnaBridge	189:f392fc9709a3	1714	* for both DAC channels.
AnnaBridge	189:f392fc9709a3	1715	* @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
AnnaBridge	189:f392fc9709a3	1716	* DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
AnnaBridge	189:f392fc9709a3	1717	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1718	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1719	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1720	* @retval None
AnnaBridge	189:f392fc9709a3	1721	*/
AnnaBridge	189:f392fc9709a3	1722	__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge	189:f392fc9709a3	1723	{
AnnaBridge	189:f392fc9709a3	1724	/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
AnnaBridge	189:f392fc9709a3	1725	/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
AnnaBridge	189:f392fc9709a3	1726	/* the 4 LSB must be taken into account for the shift value. */
AnnaBridge	189:f392fc9709a3	1727	MODIFY_REG(DACx->DHR12LD,
AnnaBridge	189:f392fc9709a3	1728	(DAC_DHR12LD_DACC2DHR \| DAC_DHR12LD_DACC1DHR),
AnnaBridge	189:f392fc9709a3	1729	((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) \| DataChannel1));
AnnaBridge	189:f392fc9709a3	1730	}
AnnaBridge	189:f392fc9709a3	1731
AnnaBridge	189:f392fc9709a3	1732	/**
AnnaBridge	189:f392fc9709a3	1733	* @brief Set the data to be loaded in the data holding register
AnnaBridge	189:f392fc9709a3	1734	* in format 8 bits left alignment (LSB aligned on bit 0),
AnnaBridge	189:f392fc9709a3	1735	* for both DAC channels.
AnnaBridge	189:f392fc9709a3	1736	* @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
AnnaBridge	189:f392fc9709a3	1737	* DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
AnnaBridge	189:f392fc9709a3	1738	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1739	* @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	1740	* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	1741	* @retval None
AnnaBridge	189:f392fc9709a3	1742	*/
AnnaBridge	189:f392fc9709a3	1743	__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge	189:f392fc9709a3	1744	{
AnnaBridge	189:f392fc9709a3	1745	MODIFY_REG(DACx->DHR8RD,
AnnaBridge	189:f392fc9709a3	1746	(DAC_DHR8RD_DACC2DHR \| DAC_DHR8RD_DACC1DHR),
AnnaBridge	189:f392fc9709a3	1747	((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
AnnaBridge	189:f392fc9709a3	1748	}
AnnaBridge	189:f392fc9709a3	1749
AnnaBridge	189:f392fc9709a3	1750	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1751	/**
AnnaBridge	189:f392fc9709a3	1752	* @brief Retrieve output data currently generated for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1753	* @note Whatever alignment and resolution settings
AnnaBridge	189:f392fc9709a3	1754	* (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
AnnaBridge	189:f392fc9709a3	1755	* @ref LL_DAC_ConvertData12RightAligned(), ...),
AnnaBridge	189:f392fc9709a3	1756	* output data format is 12 bits right aligned (LSB aligned on bit 0).
AnnaBridge	189:f392fc9709a3	1757	* @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
AnnaBridge	189:f392fc9709a3	1758	* DOR2 DACC2DOR LL_DAC_RetrieveOutputData
AnnaBridge	189:f392fc9709a3	1759	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1760	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1761	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1762	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1763	*
AnnaBridge	189:f392fc9709a3	1764	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1765	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1766	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1767	*/
AnnaBridge	189:f392fc9709a3	1768	__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1769	{
AnnaBridge	189:f392fc9709a3	1770	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1771
AnnaBridge	189:f392fc9709a3	1772	return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
AnnaBridge	189:f392fc9709a3	1773	}
AnnaBridge	189:f392fc9709a3	1774
AnnaBridge	189:f392fc9709a3	1775	/**
AnnaBridge	189:f392fc9709a3	1776	* @}
AnnaBridge	189:f392fc9709a3	1777	*/
AnnaBridge	189:f392fc9709a3	1778
AnnaBridge	189:f392fc9709a3	1779	/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	189:f392fc9709a3	1780	* @{
AnnaBridge	189:f392fc9709a3	1781	*/
AnnaBridge	189:f392fc9709a3	1782	/**
AnnaBridge	189:f392fc9709a3	1783	* @brief Get DAC calibration offset flag for DAC channel 1
AnnaBridge	189:f392fc9709a3	1784	* @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
AnnaBridge	189:f392fc9709a3	1785	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1786	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1787	*/
AnnaBridge	189:f392fc9709a3	1788	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1789	{
AnnaBridge	189:f392fc9709a3	1790	return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1));
AnnaBridge	189:f392fc9709a3	1791	}
AnnaBridge	189:f392fc9709a3	1792
AnnaBridge	189:f392fc9709a3	1793	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1794	/**
AnnaBridge	189:f392fc9709a3	1795	* @brief Get DAC calibration offset flag for DAC channel 2
AnnaBridge	189:f392fc9709a3	1796	* @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
AnnaBridge	189:f392fc9709a3	1797	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1798	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1799	*/
AnnaBridge	189:f392fc9709a3	1800	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1801	{
AnnaBridge	189:f392fc9709a3	1802	return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2));
AnnaBridge	189:f392fc9709a3	1803	}
AnnaBridge	189:f392fc9709a3	1804
AnnaBridge	189:f392fc9709a3	1805	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1806	/**
AnnaBridge	189:f392fc9709a3	1807	* @brief Get DAC busy writing sample time flag for DAC channel 1
AnnaBridge	189:f392fc9709a3	1808	* @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
AnnaBridge	189:f392fc9709a3	1809	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1810	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1811	*/
AnnaBridge	189:f392fc9709a3	1812	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1813	{
AnnaBridge	189:f392fc9709a3	1814	return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1));
AnnaBridge	189:f392fc9709a3	1815	}
AnnaBridge	189:f392fc9709a3	1816
AnnaBridge	189:f392fc9709a3	1817	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1818	/**
AnnaBridge	189:f392fc9709a3	1819	* @brief Get DAC busy writing sample time flag for DAC channel 2
AnnaBridge	189:f392fc9709a3	1820	* @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
AnnaBridge	189:f392fc9709a3	1821	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1822	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1823	*/
AnnaBridge	189:f392fc9709a3	1824	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1825	{
AnnaBridge	189:f392fc9709a3	1826	return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2));
AnnaBridge	189:f392fc9709a3	1827	}
AnnaBridge	189:f392fc9709a3	1828
AnnaBridge	189:f392fc9709a3	1829	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1830	/**
AnnaBridge	189:f392fc9709a3	1831	* @brief Get DAC underrun flag for DAC channel 1
AnnaBridge	189:f392fc9709a3	1832	* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
AnnaBridge	189:f392fc9709a3	1833	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1834	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1835	*/
AnnaBridge	189:f392fc9709a3	1836	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1837	{
AnnaBridge	189:f392fc9709a3	1838	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
AnnaBridge	189:f392fc9709a3	1839	}
AnnaBridge	189:f392fc9709a3	1840
AnnaBridge	189:f392fc9709a3	1841	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1842	/**
AnnaBridge	189:f392fc9709a3	1843	* @brief Get DAC underrun flag for DAC channel 2
AnnaBridge	189:f392fc9709a3	1844	* @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
AnnaBridge	189:f392fc9709a3	1845	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1846	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1847	*/
AnnaBridge	189:f392fc9709a3	1848	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1849	{
AnnaBridge	189:f392fc9709a3	1850	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
AnnaBridge	189:f392fc9709a3	1851	}
AnnaBridge	189:f392fc9709a3	1852	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1853
AnnaBridge	189:f392fc9709a3	1854	/**
AnnaBridge	189:f392fc9709a3	1855	* @brief Clear DAC underrun flag for DAC channel 1
AnnaBridge	189:f392fc9709a3	1856	* @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
AnnaBridge	189:f392fc9709a3	1857	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1858	* @retval None
AnnaBridge	189:f392fc9709a3	1859	*/
AnnaBridge	189:f392fc9709a3	1860	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1861	{
AnnaBridge	189:f392fc9709a3	1862	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
AnnaBridge	189:f392fc9709a3	1863	}
AnnaBridge	189:f392fc9709a3	1864
AnnaBridge	189:f392fc9709a3	1865	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1866	/**
AnnaBridge	189:f392fc9709a3	1867	* @brief Clear DAC underrun flag for DAC channel 2
AnnaBridge	189:f392fc9709a3	1868	* @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
AnnaBridge	189:f392fc9709a3	1869	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1870	* @retval None
AnnaBridge	189:f392fc9709a3	1871	*/
AnnaBridge	189:f392fc9709a3	1872	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1873	{
AnnaBridge	189:f392fc9709a3	1874	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
AnnaBridge	189:f392fc9709a3	1875	}
AnnaBridge	189:f392fc9709a3	1876	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1877
AnnaBridge	189:f392fc9709a3	1878	/**
AnnaBridge	189:f392fc9709a3	1879	* @}
AnnaBridge	189:f392fc9709a3	1880	*/
AnnaBridge	189:f392fc9709a3	1881
AnnaBridge	189:f392fc9709a3	1882	/** @defgroup DAC_LL_EF_IT_Management IT management
AnnaBridge	189:f392fc9709a3	1883	* @{
AnnaBridge	189:f392fc9709a3	1884	*/
AnnaBridge	189:f392fc9709a3	1885
AnnaBridge	189:f392fc9709a3	1886	/**
AnnaBridge	189:f392fc9709a3	1887	* @brief Enable DMA underrun interrupt for DAC channel 1
AnnaBridge	189:f392fc9709a3	1888	* @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
AnnaBridge	189:f392fc9709a3	1889	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1890	* @retval None
AnnaBridge	189:f392fc9709a3	1891	*/
AnnaBridge	189:f392fc9709a3	1892	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1893	{
AnnaBridge	189:f392fc9709a3	1894	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
AnnaBridge	189:f392fc9709a3	1895	}
AnnaBridge	189:f392fc9709a3	1896
AnnaBridge	189:f392fc9709a3	1897	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1898	/**
AnnaBridge	189:f392fc9709a3	1899	* @brief Enable DMA underrun interrupt for DAC channel 2
AnnaBridge	189:f392fc9709a3	1900	* @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
AnnaBridge	189:f392fc9709a3	1901	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1902	* @retval None
AnnaBridge	189:f392fc9709a3	1903	*/
AnnaBridge	189:f392fc9709a3	1904	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1905	{
AnnaBridge	189:f392fc9709a3	1906	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
AnnaBridge	189:f392fc9709a3	1907	}
AnnaBridge	189:f392fc9709a3	1908	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1909
AnnaBridge	189:f392fc9709a3	1910	/**
AnnaBridge	189:f392fc9709a3	1911	* @brief Disable DMA underrun interrupt for DAC channel 1
AnnaBridge	189:f392fc9709a3	1912	* @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
AnnaBridge	189:f392fc9709a3	1913	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1914	* @retval None
AnnaBridge	189:f392fc9709a3	1915	*/
AnnaBridge	189:f392fc9709a3	1916	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1917	{
AnnaBridge	189:f392fc9709a3	1918	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
AnnaBridge	189:f392fc9709a3	1919	}
AnnaBridge	189:f392fc9709a3	1920
AnnaBridge	189:f392fc9709a3	1921	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1922	/**
AnnaBridge	189:f392fc9709a3	1923	* @brief Disable DMA underrun interrupt for DAC channel 2
AnnaBridge	189:f392fc9709a3	1924	* @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
AnnaBridge	189:f392fc9709a3	1925	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1926	* @retval None
AnnaBridge	189:f392fc9709a3	1927	*/
AnnaBridge	189:f392fc9709a3	1928	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1929	{
AnnaBridge	189:f392fc9709a3	1930	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
AnnaBridge	189:f392fc9709a3	1931	}
AnnaBridge	189:f392fc9709a3	1932	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1933
AnnaBridge	189:f392fc9709a3	1934	/**
AnnaBridge	189:f392fc9709a3	1935	* @brief Get DMA underrun interrupt for DAC channel 1
AnnaBridge	189:f392fc9709a3	1936	* @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
AnnaBridge	189:f392fc9709a3	1937	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1938	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1939	*/
AnnaBridge	189:f392fc9709a3	1940	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1941	{
AnnaBridge	189:f392fc9709a3	1942	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
AnnaBridge	189:f392fc9709a3	1943	}
AnnaBridge	189:f392fc9709a3	1944
AnnaBridge	189:f392fc9709a3	1945	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1946	/**
AnnaBridge	189:f392fc9709a3	1947	* @brief Get DMA underrun interrupt for DAC channel 2
AnnaBridge	189:f392fc9709a3	1948	* @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
AnnaBridge	189:f392fc9709a3	1949	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1950	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1951	*/
AnnaBridge	189:f392fc9709a3	1952	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1953	{
AnnaBridge	189:f392fc9709a3	1954	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
AnnaBridge	189:f392fc9709a3	1955	}
AnnaBridge	189:f392fc9709a3	1956	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1957
AnnaBridge	189:f392fc9709a3	1958	/**
AnnaBridge	189:f392fc9709a3	1959	* @}
AnnaBridge	189:f392fc9709a3	1960	*/
AnnaBridge	189:f392fc9709a3	1961
AnnaBridge	189:f392fc9709a3	1962	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	1963	/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	189:f392fc9709a3	1964	* @{
AnnaBridge	189:f392fc9709a3	1965	*/
AnnaBridge	189:f392fc9709a3	1966
AnnaBridge	189:f392fc9709a3	1967	ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
AnnaBridge	189:f392fc9709a3	1968	ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
AnnaBridge	189:f392fc9709a3	1969	void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
AnnaBridge	189:f392fc9709a3	1970
AnnaBridge	189:f392fc9709a3	1971	/**
AnnaBridge	189:f392fc9709a3	1972	* @}
AnnaBridge	189:f392fc9709a3	1973	*/
AnnaBridge	189:f392fc9709a3	1974	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	1975
AnnaBridge	189:f392fc9709a3	1976	/**
AnnaBridge	189:f392fc9709a3	1977	* @}
AnnaBridge	189:f392fc9709a3	1978	*/
AnnaBridge	189:f392fc9709a3	1979
AnnaBridge	189:f392fc9709a3	1980	/**
AnnaBridge	189:f392fc9709a3	1981	* @}
AnnaBridge	189:f392fc9709a3	1982	*/
AnnaBridge	189:f392fc9709a3	1983
AnnaBridge	189:f392fc9709a3	1984	#endif /* DAC1 */
AnnaBridge	189:f392fc9709a3	1985
AnnaBridge	189:f392fc9709a3	1986	/**
AnnaBridge	189:f392fc9709a3	1987	* @}
AnnaBridge	189:f392fc9709a3	1988	*/
AnnaBridge	189:f392fc9709a3	1989
AnnaBridge	189:f392fc9709a3	1990	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	1991	}
AnnaBridge	189:f392fc9709a3	1992	#endif
AnnaBridge	189:f392fc9709a3	1993
AnnaBridge	189:f392fc9709a3	1994	#endif /* __STM32L4xx_LL_DAC_H */
AnnaBridge	189:f392fc9709a3	1995
AnnaBridge	189:f392fc9709a3	1996	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/