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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_ll_cortex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /**
AnnaBridge 189:f392fc9709a3 2 ******************************************************************************
AnnaBridge 189:f392fc9709a3 3 * @file stm32l4xx_ll_cortex.h
AnnaBridge 189:f392fc9709a3 4 * @author MCD Application Team
AnnaBridge 189:f392fc9709a3 5 * @brief Header file of CORTEX LL module.
AnnaBridge 189:f392fc9709a3 6 @verbatim
AnnaBridge 189:f392fc9709a3 7 ==============================================================================
AnnaBridge 189:f392fc9709a3 8 ##### How to use this driver #####
AnnaBridge 189:f392fc9709a3 9 ==============================================================================
AnnaBridge 189:f392fc9709a3 10 [..]
AnnaBridge 189:f392fc9709a3 11 The LL CORTEX driver contains a set of generic APIs that can be
AnnaBridge 189:f392fc9709a3 12 used by user:
AnnaBridge 189:f392fc9709a3 13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
AnnaBridge 189:f392fc9709a3 14 functions
AnnaBridge 189:f392fc9709a3 15 (+) Low power mode configuration (SCB register of Cortex-MCU)
AnnaBridge 189:f392fc9709a3 16 (+) MPU API to configure and enable regions
AnnaBridge 189:f392fc9709a3 17 (+) API to access to MCU info (CPUID register)
AnnaBridge 189:f392fc9709a3 18 (+) API to enable fault handler (SHCSR accesses)
AnnaBridge 189:f392fc9709a3 19
AnnaBridge 189:f392fc9709a3 20 @endverbatim
AnnaBridge 189:f392fc9709a3 21 ******************************************************************************
AnnaBridge 189:f392fc9709a3 22 * @attention
AnnaBridge 189:f392fc9709a3 23 *
AnnaBridge 189:f392fc9709a3 24 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 189:f392fc9709a3 25 *
AnnaBridge 189:f392fc9709a3 26 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 27 * are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 28 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 189:f392fc9709a3 29 * this list of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 30 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 189:f392fc9709a3 31 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 189:f392fc9709a3 32 * and/or other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 33 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 189:f392fc9709a3 34 * may be used to endorse or promote products derived from this software
AnnaBridge 189:f392fc9709a3 35 * without specific prior written permission.
AnnaBridge 189:f392fc9709a3 36 *
AnnaBridge 189:f392fc9709a3 37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 189:f392fc9709a3 38 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 189:f392fc9709a3 39 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 189:f392fc9709a3 40 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 189:f392fc9709a3 41 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 189:f392fc9709a3 42 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 189:f392fc9709a3 43 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 189:f392fc9709a3 44 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 189:f392fc9709a3 45 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 189:f392fc9709a3 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 47 *
AnnaBridge 189:f392fc9709a3 48 ******************************************************************************
AnnaBridge 189:f392fc9709a3 49 */
AnnaBridge 189:f392fc9709a3 50
AnnaBridge 189:f392fc9709a3 51 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 189:f392fc9709a3 52 #ifndef __STM32L4xx_LL_CORTEX_H
AnnaBridge 189:f392fc9709a3 53 #define __STM32L4xx_LL_CORTEX_H
AnnaBridge 189:f392fc9709a3 54
AnnaBridge 189:f392fc9709a3 55 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 56 extern "C" {
AnnaBridge 189:f392fc9709a3 57 #endif
AnnaBridge 189:f392fc9709a3 58
AnnaBridge 189:f392fc9709a3 59 /* Includes ------------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 60 #include "stm32l4xx.h"
AnnaBridge 189:f392fc9709a3 61
AnnaBridge 189:f392fc9709a3 62 /** @addtogroup STM32L4xx_LL_Driver
AnnaBridge 189:f392fc9709a3 63 * @{
AnnaBridge 189:f392fc9709a3 64 */
AnnaBridge 189:f392fc9709a3 65
AnnaBridge 189:f392fc9709a3 66 /** @defgroup CORTEX_LL CORTEX
AnnaBridge 189:f392fc9709a3 67 * @{
AnnaBridge 189:f392fc9709a3 68 */
AnnaBridge 189:f392fc9709a3 69
AnnaBridge 189:f392fc9709a3 70 /* Private types -------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 71 /* Private variables ---------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 72
AnnaBridge 189:f392fc9709a3 73 /* Private constants ---------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 74
AnnaBridge 189:f392fc9709a3 75 /* Private macros ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 76
AnnaBridge 189:f392fc9709a3 77 /* Exported types ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 78 /* Exported constants --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 79 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
AnnaBridge 189:f392fc9709a3 80 * @{
AnnaBridge 189:f392fc9709a3 81 */
AnnaBridge 189:f392fc9709a3 82
AnnaBridge 189:f392fc9709a3 83 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
AnnaBridge 189:f392fc9709a3 84 * @{
AnnaBridge 189:f392fc9709a3 85 */
AnnaBridge 189:f392fc9709a3 86 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
AnnaBridge 189:f392fc9709a3 87 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
AnnaBridge 189:f392fc9709a3 88 /**
AnnaBridge 189:f392fc9709a3 89 * @}
AnnaBridge 189:f392fc9709a3 90 */
AnnaBridge 189:f392fc9709a3 91
AnnaBridge 189:f392fc9709a3 92 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
AnnaBridge 189:f392fc9709a3 93 * @{
AnnaBridge 189:f392fc9709a3 94 */
AnnaBridge 189:f392fc9709a3 95 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
AnnaBridge 189:f392fc9709a3 96 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
AnnaBridge 189:f392fc9709a3 97 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
AnnaBridge 189:f392fc9709a3 98 /**
AnnaBridge 189:f392fc9709a3 99 * @}
AnnaBridge 189:f392fc9709a3 100 */
AnnaBridge 189:f392fc9709a3 101
AnnaBridge 189:f392fc9709a3 102 #if __MPU_PRESENT
AnnaBridge 189:f392fc9709a3 103
AnnaBridge 189:f392fc9709a3 104 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
AnnaBridge 189:f392fc9709a3 105 * @{
AnnaBridge 189:f392fc9709a3 106 */
AnnaBridge 189:f392fc9709a3 107 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
AnnaBridge 189:f392fc9709a3 108 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
AnnaBridge 189:f392fc9709a3 109 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
AnnaBridge 189:f392fc9709a3 110 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
AnnaBridge 189:f392fc9709a3 111 /**
AnnaBridge 189:f392fc9709a3 112 * @}
AnnaBridge 189:f392fc9709a3 113 */
AnnaBridge 189:f392fc9709a3 114
AnnaBridge 189:f392fc9709a3 115 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
AnnaBridge 189:f392fc9709a3 116 * @{
AnnaBridge 189:f392fc9709a3 117 */
AnnaBridge 189:f392fc9709a3 118 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
AnnaBridge 189:f392fc9709a3 119 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
AnnaBridge 189:f392fc9709a3 120 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
AnnaBridge 189:f392fc9709a3 121 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
AnnaBridge 189:f392fc9709a3 122 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
AnnaBridge 189:f392fc9709a3 123 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
AnnaBridge 189:f392fc9709a3 124 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
AnnaBridge 189:f392fc9709a3 125 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
AnnaBridge 189:f392fc9709a3 126 /**
AnnaBridge 189:f392fc9709a3 127 * @}
AnnaBridge 189:f392fc9709a3 128 */
AnnaBridge 189:f392fc9709a3 129
AnnaBridge 189:f392fc9709a3 130 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
AnnaBridge 189:f392fc9709a3 131 * @{
AnnaBridge 189:f392fc9709a3 132 */
AnnaBridge 189:f392fc9709a3 133 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 134 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 135 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 136 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 137 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 138 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 139 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 140 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 141 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 142 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 143 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 144 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 145 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 146 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 147 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 148 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 149 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 150 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 151 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 152 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 153 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 154 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 155 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 156 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 157 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 158 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 159 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 160 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 161 /**
AnnaBridge 189:f392fc9709a3 162 * @}
AnnaBridge 189:f392fc9709a3 163 */
AnnaBridge 189:f392fc9709a3 164
AnnaBridge 189:f392fc9709a3 165 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
AnnaBridge 189:f392fc9709a3 166 * @{
AnnaBridge 189:f392fc9709a3 167 */
AnnaBridge 189:f392fc9709a3 168 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
AnnaBridge 189:f392fc9709a3 169 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
AnnaBridge 189:f392fc9709a3 170 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
AnnaBridge 189:f392fc9709a3 171 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
AnnaBridge 189:f392fc9709a3 172 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
AnnaBridge 189:f392fc9709a3 173 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
AnnaBridge 189:f392fc9709a3 174 /**
AnnaBridge 189:f392fc9709a3 175 * @}
AnnaBridge 189:f392fc9709a3 176 */
AnnaBridge 189:f392fc9709a3 177
AnnaBridge 189:f392fc9709a3 178 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
AnnaBridge 189:f392fc9709a3 179 * @{
AnnaBridge 189:f392fc9709a3 180 */
AnnaBridge 189:f392fc9709a3 181 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
AnnaBridge 189:f392fc9709a3 182 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
AnnaBridge 189:f392fc9709a3 183 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
AnnaBridge 189:f392fc9709a3 184 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
AnnaBridge 189:f392fc9709a3 185 /**
AnnaBridge 189:f392fc9709a3 186 * @}
AnnaBridge 189:f392fc9709a3 187 */
AnnaBridge 189:f392fc9709a3 188
AnnaBridge 189:f392fc9709a3 189 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
AnnaBridge 189:f392fc9709a3 190 * @{
AnnaBridge 189:f392fc9709a3 191 */
AnnaBridge 189:f392fc9709a3 192 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
AnnaBridge 189:f392fc9709a3 193 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
AnnaBridge 189:f392fc9709a3 194 /**
AnnaBridge 189:f392fc9709a3 195 * @}
AnnaBridge 189:f392fc9709a3 196 */
AnnaBridge 189:f392fc9709a3 197
AnnaBridge 189:f392fc9709a3 198 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
AnnaBridge 189:f392fc9709a3 199 * @{
AnnaBridge 189:f392fc9709a3 200 */
AnnaBridge 189:f392fc9709a3 201 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
AnnaBridge 189:f392fc9709a3 202 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
AnnaBridge 189:f392fc9709a3 203 /**
AnnaBridge 189:f392fc9709a3 204 * @}
AnnaBridge 189:f392fc9709a3 205 */
AnnaBridge 189:f392fc9709a3 206
AnnaBridge 189:f392fc9709a3 207 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
AnnaBridge 189:f392fc9709a3 208 * @{
AnnaBridge 189:f392fc9709a3 209 */
AnnaBridge 189:f392fc9709a3 210 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
AnnaBridge 189:f392fc9709a3 211 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
AnnaBridge 189:f392fc9709a3 212 /**
AnnaBridge 189:f392fc9709a3 213 * @}
AnnaBridge 189:f392fc9709a3 214 */
AnnaBridge 189:f392fc9709a3 215
AnnaBridge 189:f392fc9709a3 216 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
AnnaBridge 189:f392fc9709a3 217 * @{
AnnaBridge 189:f392fc9709a3 218 */
AnnaBridge 189:f392fc9709a3 219 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
AnnaBridge 189:f392fc9709a3 220 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
AnnaBridge 189:f392fc9709a3 221 /**
AnnaBridge 189:f392fc9709a3 222 * @}
AnnaBridge 189:f392fc9709a3 223 */
AnnaBridge 189:f392fc9709a3 224 #endif /* __MPU_PRESENT */
AnnaBridge 189:f392fc9709a3 225 /**
AnnaBridge 189:f392fc9709a3 226 * @}
AnnaBridge 189:f392fc9709a3 227 */
AnnaBridge 189:f392fc9709a3 228
AnnaBridge 189:f392fc9709a3 229 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 230
AnnaBridge 189:f392fc9709a3 231 /* Exported functions --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 232 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
AnnaBridge 189:f392fc9709a3 233 * @{
AnnaBridge 189:f392fc9709a3 234 */
AnnaBridge 189:f392fc9709a3 235
AnnaBridge 189:f392fc9709a3 236 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
AnnaBridge 189:f392fc9709a3 237 * @{
AnnaBridge 189:f392fc9709a3 238 */
AnnaBridge 189:f392fc9709a3 239
AnnaBridge 189:f392fc9709a3 240 /**
AnnaBridge 189:f392fc9709a3 241 * @brief This function checks if the Systick counter flag is active or not.
AnnaBridge 189:f392fc9709a3 242 * @note It can be used in timeout function on application side.
AnnaBridge 189:f392fc9709a3 243 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
AnnaBridge 189:f392fc9709a3 244 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 245 */
AnnaBridge 189:f392fc9709a3 246 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
AnnaBridge 189:f392fc9709a3 247 {
AnnaBridge 189:f392fc9709a3 248 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
AnnaBridge 189:f392fc9709a3 249 }
AnnaBridge 189:f392fc9709a3 250
AnnaBridge 189:f392fc9709a3 251 /**
AnnaBridge 189:f392fc9709a3 252 * @brief Configures the SysTick clock source
AnnaBridge 189:f392fc9709a3 253 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
AnnaBridge 189:f392fc9709a3 254 * @param Source This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 255 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 189:f392fc9709a3 256 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 189:f392fc9709a3 257 * @retval None
AnnaBridge 189:f392fc9709a3 258 */
AnnaBridge 189:f392fc9709a3 259 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
AnnaBridge 189:f392fc9709a3 260 {
AnnaBridge 189:f392fc9709a3 261 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
AnnaBridge 189:f392fc9709a3 262 {
AnnaBridge 189:f392fc9709a3 263 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 189:f392fc9709a3 264 }
AnnaBridge 189:f392fc9709a3 265 else
AnnaBridge 189:f392fc9709a3 266 {
AnnaBridge 189:f392fc9709a3 267 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 189:f392fc9709a3 268 }
AnnaBridge 189:f392fc9709a3 269 }
AnnaBridge 189:f392fc9709a3 270
AnnaBridge 189:f392fc9709a3 271 /**
AnnaBridge 189:f392fc9709a3 272 * @brief Get the SysTick clock source
AnnaBridge 189:f392fc9709a3 273 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
AnnaBridge 189:f392fc9709a3 274 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 275 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 189:f392fc9709a3 276 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 189:f392fc9709a3 277 */
AnnaBridge 189:f392fc9709a3 278 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
AnnaBridge 189:f392fc9709a3 279 {
AnnaBridge 189:f392fc9709a3 280 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 189:f392fc9709a3 281 }
AnnaBridge 189:f392fc9709a3 282
AnnaBridge 189:f392fc9709a3 283 /**
AnnaBridge 189:f392fc9709a3 284 * @brief Enable SysTick exception request
AnnaBridge 189:f392fc9709a3 285 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
AnnaBridge 189:f392fc9709a3 286 * @retval None
AnnaBridge 189:f392fc9709a3 287 */
AnnaBridge 189:f392fc9709a3 288 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
AnnaBridge 189:f392fc9709a3 289 {
AnnaBridge 189:f392fc9709a3 290 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 189:f392fc9709a3 291 }
AnnaBridge 189:f392fc9709a3 292
AnnaBridge 189:f392fc9709a3 293 /**
AnnaBridge 189:f392fc9709a3 294 * @brief Disable SysTick exception request
AnnaBridge 189:f392fc9709a3 295 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
AnnaBridge 189:f392fc9709a3 296 * @retval None
AnnaBridge 189:f392fc9709a3 297 */
AnnaBridge 189:f392fc9709a3 298 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
AnnaBridge 189:f392fc9709a3 299 {
AnnaBridge 189:f392fc9709a3 300 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 189:f392fc9709a3 301 }
AnnaBridge 189:f392fc9709a3 302
AnnaBridge 189:f392fc9709a3 303 /**
AnnaBridge 189:f392fc9709a3 304 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
AnnaBridge 189:f392fc9709a3 305 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
AnnaBridge 189:f392fc9709a3 306 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 307 */
AnnaBridge 189:f392fc9709a3 308 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
AnnaBridge 189:f392fc9709a3 309 {
AnnaBridge 189:f392fc9709a3 310 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
AnnaBridge 189:f392fc9709a3 311 }
AnnaBridge 189:f392fc9709a3 312
AnnaBridge 189:f392fc9709a3 313 /**
AnnaBridge 189:f392fc9709a3 314 * @}
AnnaBridge 189:f392fc9709a3 315 */
AnnaBridge 189:f392fc9709a3 316
AnnaBridge 189:f392fc9709a3 317 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
AnnaBridge 189:f392fc9709a3 318 * @{
AnnaBridge 189:f392fc9709a3 319 */
AnnaBridge 189:f392fc9709a3 320
AnnaBridge 189:f392fc9709a3 321 /**
AnnaBridge 189:f392fc9709a3 322 * @brief Processor uses sleep as its low power mode
AnnaBridge 189:f392fc9709a3 323 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
AnnaBridge 189:f392fc9709a3 324 * @retval None
AnnaBridge 189:f392fc9709a3 325 */
AnnaBridge 189:f392fc9709a3 326 __STATIC_INLINE void LL_LPM_EnableSleep(void)
AnnaBridge 189:f392fc9709a3 327 {
AnnaBridge 189:f392fc9709a3 328 /* Clear SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 329 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 189:f392fc9709a3 330 }
AnnaBridge 189:f392fc9709a3 331
AnnaBridge 189:f392fc9709a3 332 /**
AnnaBridge 189:f392fc9709a3 333 * @brief Processor uses deep sleep as its low power mode
AnnaBridge 189:f392fc9709a3 334 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
AnnaBridge 189:f392fc9709a3 335 * @retval None
AnnaBridge 189:f392fc9709a3 336 */
AnnaBridge 189:f392fc9709a3 337 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
AnnaBridge 189:f392fc9709a3 338 {
AnnaBridge 189:f392fc9709a3 339 /* Set SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 189:f392fc9709a3 341 }
AnnaBridge 189:f392fc9709a3 342
AnnaBridge 189:f392fc9709a3 343 /**
AnnaBridge 189:f392fc9709a3 344 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
AnnaBridge 189:f392fc9709a3 345 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
AnnaBridge 189:f392fc9709a3 346 * empty main application.
AnnaBridge 189:f392fc9709a3 347 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
AnnaBridge 189:f392fc9709a3 348 * @retval None
AnnaBridge 189:f392fc9709a3 349 */
AnnaBridge 189:f392fc9709a3 350 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
AnnaBridge 189:f392fc9709a3 351 {
AnnaBridge 189:f392fc9709a3 352 /* Set SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 353 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 189:f392fc9709a3 354 }
AnnaBridge 189:f392fc9709a3 355
AnnaBridge 189:f392fc9709a3 356 /**
AnnaBridge 189:f392fc9709a3 357 * @brief Do not sleep when returning to Thread mode.
AnnaBridge 189:f392fc9709a3 358 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
AnnaBridge 189:f392fc9709a3 359 * @retval None
AnnaBridge 189:f392fc9709a3 360 */
AnnaBridge 189:f392fc9709a3 361 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
AnnaBridge 189:f392fc9709a3 362 {
AnnaBridge 189:f392fc9709a3 363 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 364 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 189:f392fc9709a3 365 }
AnnaBridge 189:f392fc9709a3 366
AnnaBridge 189:f392fc9709a3 367 /**
AnnaBridge 189:f392fc9709a3 368 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
AnnaBridge 189:f392fc9709a3 369 * processor.
AnnaBridge 189:f392fc9709a3 370 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
AnnaBridge 189:f392fc9709a3 371 * @retval None
AnnaBridge 189:f392fc9709a3 372 */
AnnaBridge 189:f392fc9709a3 373 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
AnnaBridge 189:f392fc9709a3 374 {
AnnaBridge 189:f392fc9709a3 375 /* Set SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 376 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 189:f392fc9709a3 377 }
AnnaBridge 189:f392fc9709a3 378
AnnaBridge 189:f392fc9709a3 379 /**
AnnaBridge 189:f392fc9709a3 380 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
AnnaBridge 189:f392fc9709a3 381 * excluded
AnnaBridge 189:f392fc9709a3 382 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
AnnaBridge 189:f392fc9709a3 383 * @retval None
AnnaBridge 189:f392fc9709a3 384 */
AnnaBridge 189:f392fc9709a3 385 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
AnnaBridge 189:f392fc9709a3 386 {
AnnaBridge 189:f392fc9709a3 387 /* Clear SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 189:f392fc9709a3 389 }
AnnaBridge 189:f392fc9709a3 390
AnnaBridge 189:f392fc9709a3 391 /**
AnnaBridge 189:f392fc9709a3 392 * @}
AnnaBridge 189:f392fc9709a3 393 */
AnnaBridge 189:f392fc9709a3 394
AnnaBridge 189:f392fc9709a3 395 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
AnnaBridge 189:f392fc9709a3 396 * @{
AnnaBridge 189:f392fc9709a3 397 */
AnnaBridge 189:f392fc9709a3 398
AnnaBridge 189:f392fc9709a3 399 /**
AnnaBridge 189:f392fc9709a3 400 * @brief Enable a fault in System handler control register (SHCSR)
AnnaBridge 189:f392fc9709a3 401 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
AnnaBridge 189:f392fc9709a3 402 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 189:f392fc9709a3 403 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 189:f392fc9709a3 404 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 189:f392fc9709a3 405 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 189:f392fc9709a3 406 * @retval None
AnnaBridge 189:f392fc9709a3 407 */
AnnaBridge 189:f392fc9709a3 408 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
AnnaBridge 189:f392fc9709a3 409 {
AnnaBridge 189:f392fc9709a3 410 /* Enable the system handler fault */
AnnaBridge 189:f392fc9709a3 411 SET_BIT(SCB->SHCSR, Fault);
AnnaBridge 189:f392fc9709a3 412 }
AnnaBridge 189:f392fc9709a3 413
AnnaBridge 189:f392fc9709a3 414 /**
AnnaBridge 189:f392fc9709a3 415 * @brief Disable a fault in System handler control register (SHCSR)
AnnaBridge 189:f392fc9709a3 416 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
AnnaBridge 189:f392fc9709a3 417 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 189:f392fc9709a3 418 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 189:f392fc9709a3 419 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 189:f392fc9709a3 420 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 189:f392fc9709a3 421 * @retval None
AnnaBridge 189:f392fc9709a3 422 */
AnnaBridge 189:f392fc9709a3 423 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
AnnaBridge 189:f392fc9709a3 424 {
AnnaBridge 189:f392fc9709a3 425 /* Disable the system handler fault */
AnnaBridge 189:f392fc9709a3 426 CLEAR_BIT(SCB->SHCSR, Fault);
AnnaBridge 189:f392fc9709a3 427 }
AnnaBridge 189:f392fc9709a3 428
AnnaBridge 189:f392fc9709a3 429 /**
AnnaBridge 189:f392fc9709a3 430 * @}
AnnaBridge 189:f392fc9709a3 431 */
AnnaBridge 189:f392fc9709a3 432
AnnaBridge 189:f392fc9709a3 433 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
AnnaBridge 189:f392fc9709a3 434 * @{
AnnaBridge 189:f392fc9709a3 435 */
AnnaBridge 189:f392fc9709a3 436
AnnaBridge 189:f392fc9709a3 437 /**
AnnaBridge 189:f392fc9709a3 438 * @brief Get Implementer code
AnnaBridge 189:f392fc9709a3 439 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
AnnaBridge 189:f392fc9709a3 440 * @retval Value should be equal to 0x41 for ARM
AnnaBridge 189:f392fc9709a3 441 */
AnnaBridge 189:f392fc9709a3 442 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
AnnaBridge 189:f392fc9709a3 443 {
AnnaBridge 189:f392fc9709a3 444 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
AnnaBridge 189:f392fc9709a3 445 }
AnnaBridge 189:f392fc9709a3 446
AnnaBridge 189:f392fc9709a3 447 /**
AnnaBridge 189:f392fc9709a3 448 * @brief Get Variant number (The r value in the rnpn product revision identifier)
AnnaBridge 189:f392fc9709a3 449 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
AnnaBridge 189:f392fc9709a3 450 * @retval Value between 0 and 255 (0x0: revision 0)
AnnaBridge 189:f392fc9709a3 451 */
AnnaBridge 189:f392fc9709a3 452 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
AnnaBridge 189:f392fc9709a3 453 {
AnnaBridge 189:f392fc9709a3 454 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
AnnaBridge 189:f392fc9709a3 455 }
AnnaBridge 189:f392fc9709a3 456
AnnaBridge 189:f392fc9709a3 457 /**
AnnaBridge 189:f392fc9709a3 458 * @brief Get Constant number
AnnaBridge 189:f392fc9709a3 459 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
AnnaBridge 189:f392fc9709a3 460 * @retval Value should be equal to 0xF for Cortex-M4 devices
AnnaBridge 189:f392fc9709a3 461 */
AnnaBridge 189:f392fc9709a3 462 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
AnnaBridge 189:f392fc9709a3 463 {
AnnaBridge 189:f392fc9709a3 464 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
AnnaBridge 189:f392fc9709a3 465 }
AnnaBridge 189:f392fc9709a3 466
AnnaBridge 189:f392fc9709a3 467 /**
AnnaBridge 189:f392fc9709a3 468 * @brief Get Part number
AnnaBridge 189:f392fc9709a3 469 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
AnnaBridge 189:f392fc9709a3 470 * @retval Value should be equal to 0xC24 for Cortex-M4
AnnaBridge 189:f392fc9709a3 471 */
AnnaBridge 189:f392fc9709a3 472 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
AnnaBridge 189:f392fc9709a3 473 {
AnnaBridge 189:f392fc9709a3 474 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
AnnaBridge 189:f392fc9709a3 475 }
AnnaBridge 189:f392fc9709a3 476
AnnaBridge 189:f392fc9709a3 477 /**
AnnaBridge 189:f392fc9709a3 478 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
AnnaBridge 189:f392fc9709a3 479 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
AnnaBridge 189:f392fc9709a3 480 * @retval Value between 0 and 255 (0x1: patch 1)
AnnaBridge 189:f392fc9709a3 481 */
AnnaBridge 189:f392fc9709a3 482 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
AnnaBridge 189:f392fc9709a3 483 {
AnnaBridge 189:f392fc9709a3 484 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
AnnaBridge 189:f392fc9709a3 485 }
AnnaBridge 189:f392fc9709a3 486
AnnaBridge 189:f392fc9709a3 487 /**
AnnaBridge 189:f392fc9709a3 488 * @}
AnnaBridge 189:f392fc9709a3 489 */
AnnaBridge 189:f392fc9709a3 490
AnnaBridge 189:f392fc9709a3 491 #if __MPU_PRESENT
AnnaBridge 189:f392fc9709a3 492 /** @defgroup CORTEX_LL_EF_MPU MPU
AnnaBridge 189:f392fc9709a3 493 * @{
AnnaBridge 189:f392fc9709a3 494 */
AnnaBridge 189:f392fc9709a3 495
AnnaBridge 189:f392fc9709a3 496 /**
AnnaBridge 189:f392fc9709a3 497 * @brief Enable MPU with input options
AnnaBridge 189:f392fc9709a3 498 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
AnnaBridge 189:f392fc9709a3 499 * @param Options This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 500 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
AnnaBridge 189:f392fc9709a3 501 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
AnnaBridge 189:f392fc9709a3 502 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
AnnaBridge 189:f392fc9709a3 503 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
AnnaBridge 189:f392fc9709a3 504 * @retval None
AnnaBridge 189:f392fc9709a3 505 */
AnnaBridge 189:f392fc9709a3 506 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
AnnaBridge 189:f392fc9709a3 507 {
AnnaBridge 189:f392fc9709a3 508 /* Enable the MPU*/
AnnaBridge 189:f392fc9709a3 509 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
AnnaBridge 189:f392fc9709a3 510 /* Ensure MPU settings take effects */
AnnaBridge 189:f392fc9709a3 511 __DSB();
AnnaBridge 189:f392fc9709a3 512 /* Sequence instruction fetches using update settings */
AnnaBridge 189:f392fc9709a3 513 __ISB();
AnnaBridge 189:f392fc9709a3 514 }
AnnaBridge 189:f392fc9709a3 515
AnnaBridge 189:f392fc9709a3 516 /**
AnnaBridge 189:f392fc9709a3 517 * @brief Disable MPU
AnnaBridge 189:f392fc9709a3 518 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
AnnaBridge 189:f392fc9709a3 519 * @retval None
AnnaBridge 189:f392fc9709a3 520 */
AnnaBridge 189:f392fc9709a3 521 __STATIC_INLINE void LL_MPU_Disable(void)
AnnaBridge 189:f392fc9709a3 522 {
AnnaBridge 189:f392fc9709a3 523 /* Make sure outstanding transfers are done */
AnnaBridge 189:f392fc9709a3 524 __DMB();
AnnaBridge 189:f392fc9709a3 525 /* Disable MPU*/
AnnaBridge 189:f392fc9709a3 526 WRITE_REG(MPU->CTRL, 0U);
AnnaBridge 189:f392fc9709a3 527 }
AnnaBridge 189:f392fc9709a3 528
AnnaBridge 189:f392fc9709a3 529 /**
AnnaBridge 189:f392fc9709a3 530 * @brief Check if MPU is enabled or not
AnnaBridge 189:f392fc9709a3 531 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
AnnaBridge 189:f392fc9709a3 532 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 533 */
AnnaBridge 189:f392fc9709a3 534 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
AnnaBridge 189:f392fc9709a3 535 {
AnnaBridge 189:f392fc9709a3 536 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
AnnaBridge 189:f392fc9709a3 537 }
AnnaBridge 189:f392fc9709a3 538
AnnaBridge 189:f392fc9709a3 539 /**
AnnaBridge 189:f392fc9709a3 540 * @brief Enable a MPU region
AnnaBridge 189:f392fc9709a3 541 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
AnnaBridge 189:f392fc9709a3 542 * @param Region This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 543 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 189:f392fc9709a3 544 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 189:f392fc9709a3 545 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 189:f392fc9709a3 546 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 189:f392fc9709a3 547 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 189:f392fc9709a3 548 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 189:f392fc9709a3 549 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 189:f392fc9709a3 550 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 189:f392fc9709a3 551 * @retval None
AnnaBridge 189:f392fc9709a3 552 */
AnnaBridge 189:f392fc9709a3 553 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
AnnaBridge 189:f392fc9709a3 554 {
AnnaBridge 189:f392fc9709a3 555 /* Set Region number */
AnnaBridge 189:f392fc9709a3 556 WRITE_REG(MPU->RNR, Region);
AnnaBridge 189:f392fc9709a3 557 /* Enable the MPU region */
AnnaBridge 189:f392fc9709a3 558 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 189:f392fc9709a3 559 }
AnnaBridge 189:f392fc9709a3 560
AnnaBridge 189:f392fc9709a3 561 /**
AnnaBridge 189:f392fc9709a3 562 * @brief Configure and enable a region
AnnaBridge 189:f392fc9709a3 563 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 564 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 565 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 566 * MPU_RASR XN LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 567 * MPU_RASR AP LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 568 * MPU_RASR S LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 569 * MPU_RASR C LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 570 * MPU_RASR B LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 571 * MPU_RASR SIZE LL_MPU_ConfigRegion
AnnaBridge 189:f392fc9709a3 572 * @param Region This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 573 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 189:f392fc9709a3 574 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 189:f392fc9709a3 575 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 189:f392fc9709a3 576 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 189:f392fc9709a3 577 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 189:f392fc9709a3 578 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 189:f392fc9709a3 579 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 189:f392fc9709a3 580 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 189:f392fc9709a3 581 * @param Address Value of region base address
AnnaBridge 189:f392fc9709a3 582 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge 189:f392fc9709a3 583 * @param Attributes This parameter can be a combination of the following values:
AnnaBridge 189:f392fc9709a3 584 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
AnnaBridge 189:f392fc9709a3 585 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
AnnaBridge 189:f392fc9709a3 586 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
AnnaBridge 189:f392fc9709a3 587 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
AnnaBridge 189:f392fc9709a3 588 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
AnnaBridge 189:f392fc9709a3 589 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
AnnaBridge 189:f392fc9709a3 590 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
AnnaBridge 189:f392fc9709a3 591 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
AnnaBridge 189:f392fc9709a3 592 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
AnnaBridge 189:f392fc9709a3 593 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
AnnaBridge 189:f392fc9709a3 594 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
AnnaBridge 189:f392fc9709a3 595 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
AnnaBridge 189:f392fc9709a3 596 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
AnnaBridge 189:f392fc9709a3 597 * @retval None
AnnaBridge 189:f392fc9709a3 598 */
AnnaBridge 189:f392fc9709a3 599 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
AnnaBridge 189:f392fc9709a3 600 {
AnnaBridge 189:f392fc9709a3 601 /* Set Region number */
AnnaBridge 189:f392fc9709a3 602 WRITE_REG(MPU->RNR, Region);
AnnaBridge 189:f392fc9709a3 603 /* Set base address */
AnnaBridge 189:f392fc9709a3 604 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
AnnaBridge 189:f392fc9709a3 605 /* Configure MPU */
AnnaBridge 189:f392fc9709a3 606 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
AnnaBridge 189:f392fc9709a3 607 }
AnnaBridge 189:f392fc9709a3 608
AnnaBridge 189:f392fc9709a3 609 /**
AnnaBridge 189:f392fc9709a3 610 * @brief Disable a region
AnnaBridge 189:f392fc9709a3 611 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
AnnaBridge 189:f392fc9709a3 612 * MPU_RASR ENABLE LL_MPU_DisableRegion
AnnaBridge 189:f392fc9709a3 613 * @param Region This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 614 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 189:f392fc9709a3 615 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 189:f392fc9709a3 616 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 189:f392fc9709a3 617 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 189:f392fc9709a3 618 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 189:f392fc9709a3 619 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 189:f392fc9709a3 620 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 189:f392fc9709a3 621 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 189:f392fc9709a3 622 * @retval None
AnnaBridge 189:f392fc9709a3 623 */
AnnaBridge 189:f392fc9709a3 624 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
AnnaBridge 189:f392fc9709a3 625 {
AnnaBridge 189:f392fc9709a3 626 /* Set Region number */
AnnaBridge 189:f392fc9709a3 627 WRITE_REG(MPU->RNR, Region);
AnnaBridge 189:f392fc9709a3 628 /* Disable the MPU region */
AnnaBridge 189:f392fc9709a3 629 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 189:f392fc9709a3 630 }
AnnaBridge 189:f392fc9709a3 631
AnnaBridge 189:f392fc9709a3 632 /**
AnnaBridge 189:f392fc9709a3 633 * @}
AnnaBridge 189:f392fc9709a3 634 */
AnnaBridge 189:f392fc9709a3 635
AnnaBridge 189:f392fc9709a3 636 #endif /* __MPU_PRESENT */
AnnaBridge 189:f392fc9709a3 637 /**
AnnaBridge 189:f392fc9709a3 638 * @}
AnnaBridge 189:f392fc9709a3 639 */
AnnaBridge 189:f392fc9709a3 640
AnnaBridge 189:f392fc9709a3 641 /**
AnnaBridge 189:f392fc9709a3 642 * @}
AnnaBridge 189:f392fc9709a3 643 */
AnnaBridge 189:f392fc9709a3 644
AnnaBridge 189:f392fc9709a3 645 /**
AnnaBridge 189:f392fc9709a3 646 * @}
AnnaBridge 189:f392fc9709a3 647 */
AnnaBridge 189:f392fc9709a3 648
AnnaBridge 189:f392fc9709a3 649 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 650 }
AnnaBridge 189:f392fc9709a3 651 #endif
AnnaBridge 189:f392fc9709a3 652
AnnaBridge 189:f392fc9709a3 653 #endif /* __STM32L4xx_LL_CORTEX_H */
AnnaBridge 189:f392fc9709a3 654
AnnaBridge 189:f392fc9709a3 655 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/