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mbed library sources. Supersedes mbed-src.

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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_ll_bus.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l4xx_ll_bus.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of BUS LL module.
AnnaBridge	189:f392fc9709a3	6
AnnaBridge	189:f392fc9709a3	7	@verbatim
AnnaBridge	189:f392fc9709a3	8	##### RCC Limitations #####
AnnaBridge	189:f392fc9709a3	9	==============================================================================
AnnaBridge	189:f392fc9709a3	10	[..]
AnnaBridge	189:f392fc9709a3	11	A delay between an RCC peripheral clock enable and the effective peripheral
AnnaBridge	189:f392fc9709a3	12	enabling should be taken into account in order to manage the peripheral read/write
AnnaBridge	189:f392fc9709a3	13	from/to registers.
AnnaBridge	189:f392fc9709a3	14	(+) This delay depends on the peripheral mapping.
AnnaBridge	189:f392fc9709a3	15	(++) AHB & APB peripherals, 1 dummy read is necessary
AnnaBridge	189:f392fc9709a3	16
AnnaBridge	189:f392fc9709a3	17	[..]
AnnaBridge	189:f392fc9709a3	18	Workarounds:
AnnaBridge	189:f392fc9709a3	19	(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
AnnaBridge	189:f392fc9709a3	20	inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
AnnaBridge	189:f392fc9709a3	21
AnnaBridge	189:f392fc9709a3	22	@endverbatim
AnnaBridge	189:f392fc9709a3	23	******************************************************************************
AnnaBridge	189:f392fc9709a3	24	* @attention
AnnaBridge	189:f392fc9709a3	25	*
AnnaBridge	189:f392fc9709a3	26	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	27	*
AnnaBridge	189:f392fc9709a3	28	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	29	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	30	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	31	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	32	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	33	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	34	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	35	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	36	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	37	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	38	*
AnnaBridge	189:f392fc9709a3	39	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	40	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	41	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	42	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	43	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	44	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	45	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	46	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	47	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	48	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	49	*
AnnaBridge	189:f392fc9709a3	50	******************************************************************************
AnnaBridge	189:f392fc9709a3	51	*/
AnnaBridge	189:f392fc9709a3	52
AnnaBridge	189:f392fc9709a3	53	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	54	#ifndef __STM32L4xx_LL_BUS_H
AnnaBridge	189:f392fc9709a3	55	#define __STM32L4xx_LL_BUS_H
AnnaBridge	189:f392fc9709a3	56
AnnaBridge	189:f392fc9709a3	57	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	58	extern "C" {
AnnaBridge	189:f392fc9709a3	59	#endif
AnnaBridge	189:f392fc9709a3	60
AnnaBridge	189:f392fc9709a3	61	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	62	#include "stm32l4xx.h"
AnnaBridge	189:f392fc9709a3	63
AnnaBridge	189:f392fc9709a3	64	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	189:f392fc9709a3	65	* @{
AnnaBridge	189:f392fc9709a3	66	*/
AnnaBridge	189:f392fc9709a3	67
AnnaBridge	189:f392fc9709a3	68	#if defined(RCC)
AnnaBridge	189:f392fc9709a3	69
AnnaBridge	189:f392fc9709a3	70	/** @defgroup BUS_LL BUS
AnnaBridge	189:f392fc9709a3	71	* @{
AnnaBridge	189:f392fc9709a3	72	*/
AnnaBridge	189:f392fc9709a3	73
AnnaBridge	189:f392fc9709a3	74	/* Private types -------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	75	/* Private variables ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	76
AnnaBridge	189:f392fc9709a3	77	/* Private constants ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	78
AnnaBridge	189:f392fc9709a3	79	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	80
AnnaBridge	189:f392fc9709a3	81	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	82	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	83	/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
AnnaBridge	189:f392fc9709a3	84	* @{
AnnaBridge	189:f392fc9709a3	85	*/
AnnaBridge	189:f392fc9709a3	86
AnnaBridge	189:f392fc9709a3	87	/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
AnnaBridge	189:f392fc9709a3	88	* @{
AnnaBridge	189:f392fc9709a3	89	*/
AnnaBridge	189:f392fc9709a3	90	#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	189:f392fc9709a3	91	#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
AnnaBridge	189:f392fc9709a3	92	#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
AnnaBridge	189:f392fc9709a3	93	#if defined(DMAMUX1)
AnnaBridge	189:f392fc9709a3	94	#define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
AnnaBridge	189:f392fc9709a3	95	#endif /* DMAMUX1 */
AnnaBridge	189:f392fc9709a3	96	#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
AnnaBridge	189:f392fc9709a3	97	#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
AnnaBridge	189:f392fc9709a3	98	#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
AnnaBridge	189:f392fc9709a3	99	#if defined(DMA2D)
AnnaBridge	189:f392fc9709a3	100	#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
AnnaBridge	189:f392fc9709a3	101	#endif /* DMA2D */
AnnaBridge	189:f392fc9709a3	102	#if defined(GFXMMU)
AnnaBridge	189:f392fc9709a3	103	#define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN
AnnaBridge	189:f392fc9709a3	104	#endif /* GFXMMU */
AnnaBridge	189:f392fc9709a3	105	#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
AnnaBridge	189:f392fc9709a3	106	/**
AnnaBridge	189:f392fc9709a3	107	* @}
AnnaBridge	189:f392fc9709a3	108	*/
AnnaBridge	189:f392fc9709a3	109
AnnaBridge	189:f392fc9709a3	110	/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
AnnaBridge	189:f392fc9709a3	111	* @{
AnnaBridge	189:f392fc9709a3	112	*/
AnnaBridge	189:f392fc9709a3	113	#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	189:f392fc9709a3	114	#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
AnnaBridge	189:f392fc9709a3	115	#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
AnnaBridge	189:f392fc9709a3	116	#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
AnnaBridge	189:f392fc9709a3	117	#if defined(GPIOD)
AnnaBridge	189:f392fc9709a3	118	#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
AnnaBridge	189:f392fc9709a3	119	#endif /GPIOD/
AnnaBridge	189:f392fc9709a3	120	#if defined(GPIOE)
AnnaBridge	189:f392fc9709a3	121	#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
AnnaBridge	189:f392fc9709a3	122	#endif /GPIOE/
AnnaBridge	189:f392fc9709a3	123	#if defined(GPIOF)
AnnaBridge	189:f392fc9709a3	124	#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
AnnaBridge	189:f392fc9709a3	125	#endif /* GPIOF */
AnnaBridge	189:f392fc9709a3	126	#if defined(GPIOG)
AnnaBridge	189:f392fc9709a3	127	#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
AnnaBridge	189:f392fc9709a3	128	#endif /* GPIOG */
AnnaBridge	189:f392fc9709a3	129	#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
AnnaBridge	189:f392fc9709a3	130	#if defined(GPIOI)
AnnaBridge	189:f392fc9709a3	131	#define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN
AnnaBridge	189:f392fc9709a3	132	#endif /* GPIOI */
AnnaBridge	189:f392fc9709a3	133	#if defined(USB_OTG_FS)
AnnaBridge	189:f392fc9709a3	134	#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
AnnaBridge	189:f392fc9709a3	135	#endif /* USB_OTG_FS */
AnnaBridge	189:f392fc9709a3	136	#define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
AnnaBridge	189:f392fc9709a3	137	#if defined(DCMI)
AnnaBridge	189:f392fc9709a3	138	#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
AnnaBridge	189:f392fc9709a3	139	#endif /* DCMI */
AnnaBridge	189:f392fc9709a3	140	#if defined(AES)
AnnaBridge	189:f392fc9709a3	141	#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
AnnaBridge	189:f392fc9709a3	142	#endif /* AES */
AnnaBridge	189:f392fc9709a3	143	#if defined(HASH)
AnnaBridge	189:f392fc9709a3	144	#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
AnnaBridge	189:f392fc9709a3	145	#endif /* HASH */
AnnaBridge	189:f392fc9709a3	146	#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
AnnaBridge	189:f392fc9709a3	147	#if defined(OCTOSPIM)
AnnaBridge	189:f392fc9709a3	148	#define LL_AHB2_GRP1_PERIPH_OSPIM RCC_AHB2ENR_OSPIMEN
AnnaBridge	189:f392fc9709a3	149	#endif /* OCTOSPIM */
AnnaBridge	189:f392fc9709a3	150	#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
AnnaBridge	189:f392fc9709a3	151	#define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR_SDMMC1EN
AnnaBridge	189:f392fc9709a3	152	#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
AnnaBridge	189:f392fc9709a3	153	#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
AnnaBridge	189:f392fc9709a3	154	#if defined(SRAM3_BASE)
AnnaBridge	189:f392fc9709a3	155	#define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2SMENR_SRAM3SMEN
AnnaBridge	189:f392fc9709a3	156	#endif /* SRAM3_BASE */
AnnaBridge	189:f392fc9709a3	157	/**
AnnaBridge	189:f392fc9709a3	158	* @}
AnnaBridge	189:f392fc9709a3	159	*/
AnnaBridge	189:f392fc9709a3	160
AnnaBridge	189:f392fc9709a3	161	/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
AnnaBridge	189:f392fc9709a3	162	* @{
AnnaBridge	189:f392fc9709a3	163	*/
AnnaBridge	189:f392fc9709a3	164	#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	189:f392fc9709a3	165	#if defined(FMC_Bank1_R)
AnnaBridge	189:f392fc9709a3	166	#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
AnnaBridge	189:f392fc9709a3	167	#endif /* FMC_Bank1_R */
AnnaBridge	189:f392fc9709a3	168	#if defined(QUADSPI)
AnnaBridge	189:f392fc9709a3	169	#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
AnnaBridge	189:f392fc9709a3	170	#endif /* QUADSPI */
AnnaBridge	189:f392fc9709a3	171	#if defined(OCTOSPI1)
AnnaBridge	189:f392fc9709a3	172	#define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN
AnnaBridge	189:f392fc9709a3	173	#endif /* OCTOSPI1 */
AnnaBridge	189:f392fc9709a3	174	#if defined(OCTOSPI2)
AnnaBridge	189:f392fc9709a3	175	#define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN
AnnaBridge	189:f392fc9709a3	176	#endif /* OCTOSPI2 */
AnnaBridge	189:f392fc9709a3	177	/**
AnnaBridge	189:f392fc9709a3	178	* @}
AnnaBridge	189:f392fc9709a3	179	*/
AnnaBridge	189:f392fc9709a3	180
AnnaBridge	189:f392fc9709a3	181	/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
AnnaBridge	189:f392fc9709a3	182	* @{
AnnaBridge	189:f392fc9709a3	183	*/
AnnaBridge	189:f392fc9709a3	184	#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	189:f392fc9709a3	185	#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
AnnaBridge	189:f392fc9709a3	186	#if defined(TIM3)
AnnaBridge	189:f392fc9709a3	187	#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
AnnaBridge	189:f392fc9709a3	188	#endif /* TIM3 */
AnnaBridge	189:f392fc9709a3	189	#if defined(TIM4)
AnnaBridge	189:f392fc9709a3	190	#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
AnnaBridge	189:f392fc9709a3	191	#endif /* TIM4 */
AnnaBridge	189:f392fc9709a3	192	#if defined(TIM5)
AnnaBridge	189:f392fc9709a3	193	#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
AnnaBridge	189:f392fc9709a3	194	#endif /* TIM5 */
AnnaBridge	189:f392fc9709a3	195	#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
AnnaBridge	189:f392fc9709a3	196	#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
AnnaBridge	189:f392fc9709a3	197	#if defined(LCD)
AnnaBridge	189:f392fc9709a3	198	#define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
AnnaBridge	189:f392fc9709a3	199	#endif /* LCD */
AnnaBridge	189:f392fc9709a3	200	#if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge	189:f392fc9709a3	201	#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
AnnaBridge	189:f392fc9709a3	202	#endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge	189:f392fc9709a3	203	#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
AnnaBridge	189:f392fc9709a3	204	#if defined(SPI2)
AnnaBridge	189:f392fc9709a3	205	#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
AnnaBridge	189:f392fc9709a3	206	#endif /* SPI2 */
AnnaBridge	189:f392fc9709a3	207	#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
AnnaBridge	189:f392fc9709a3	208	#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
AnnaBridge	189:f392fc9709a3	209	#if defined(USART3)
AnnaBridge	189:f392fc9709a3	210	#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
AnnaBridge	189:f392fc9709a3	211	#endif /* USART3 */
AnnaBridge	189:f392fc9709a3	212	#if defined(UART4)
AnnaBridge	189:f392fc9709a3	213	#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
AnnaBridge	189:f392fc9709a3	214	#endif /* UART4 */
AnnaBridge	189:f392fc9709a3	215	#if defined(UART5)
AnnaBridge	189:f392fc9709a3	216	#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
AnnaBridge	189:f392fc9709a3	217	#endif /* UART5 */
AnnaBridge	189:f392fc9709a3	218	#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
AnnaBridge	189:f392fc9709a3	219	#if defined(I2C2)
AnnaBridge	189:f392fc9709a3	220	#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
AnnaBridge	189:f392fc9709a3	221	#endif /* I2C2 */
AnnaBridge	189:f392fc9709a3	222	#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
AnnaBridge	189:f392fc9709a3	223	#if defined(CRS)
AnnaBridge	189:f392fc9709a3	224	#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
AnnaBridge	189:f392fc9709a3	225	#endif /* CRS */
AnnaBridge	189:f392fc9709a3	226	#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN
AnnaBridge	189:f392fc9709a3	227	#if defined(CAN2)
AnnaBridge	189:f392fc9709a3	228	#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR1_CAN2EN
AnnaBridge	189:f392fc9709a3	229	#endif /* CAN2 */
AnnaBridge	189:f392fc9709a3	230	#if defined(USB)
AnnaBridge	189:f392fc9709a3	231	#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN
AnnaBridge	189:f392fc9709a3	232	#endif /* USB */
AnnaBridge	189:f392fc9709a3	233	#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
AnnaBridge	189:f392fc9709a3	234	#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN
AnnaBridge	189:f392fc9709a3	235	#define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN
AnnaBridge	189:f392fc9709a3	236	#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
AnnaBridge	189:f392fc9709a3	237	/**
AnnaBridge	189:f392fc9709a3	238	* @}
AnnaBridge	189:f392fc9709a3	239	*/
AnnaBridge	189:f392fc9709a3	240
AnnaBridge	189:f392fc9709a3	241
AnnaBridge	189:f392fc9709a3	242	/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
AnnaBridge	189:f392fc9709a3	243	* @{
AnnaBridge	189:f392fc9709a3	244	*/
AnnaBridge	189:f392fc9709a3	245	#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	189:f392fc9709a3	246	#define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
AnnaBridge	189:f392fc9709a3	247	#if defined(I2C4)
AnnaBridge	189:f392fc9709a3	248	#define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
AnnaBridge	189:f392fc9709a3	249	#endif /* I2C4 */
AnnaBridge	189:f392fc9709a3	250	#if defined(SWPMI1)
AnnaBridge	189:f392fc9709a3	251	#define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN
AnnaBridge	189:f392fc9709a3	252	#endif /* SWPMI1 */
AnnaBridge	189:f392fc9709a3	253	#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
AnnaBridge	189:f392fc9709a3	254	/**
AnnaBridge	189:f392fc9709a3	255	* @}
AnnaBridge	189:f392fc9709a3	256	*/
AnnaBridge	189:f392fc9709a3	257
AnnaBridge	189:f392fc9709a3	258	/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
AnnaBridge	189:f392fc9709a3	259	* @{
AnnaBridge	189:f392fc9709a3	260	*/
AnnaBridge	189:f392fc9709a3	261	#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	189:f392fc9709a3	262	#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
AnnaBridge	189:f392fc9709a3	263	#define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN
AnnaBridge	189:f392fc9709a3	264	#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
AnnaBridge	189:f392fc9709a3	265	#define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
AnnaBridge	189:f392fc9709a3	266	#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
AnnaBridge	189:f392fc9709a3	267	#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
AnnaBridge	189:f392fc9709a3	268	#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
AnnaBridge	189:f392fc9709a3	269	#if defined(TIM8)
AnnaBridge	189:f392fc9709a3	270	#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
AnnaBridge	189:f392fc9709a3	271	#endif /* TIM8 */
AnnaBridge	189:f392fc9709a3	272	#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
AnnaBridge	189:f392fc9709a3	273	#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
AnnaBridge	189:f392fc9709a3	274	#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
AnnaBridge	189:f392fc9709a3	275	#if defined(TIM17)
AnnaBridge	189:f392fc9709a3	276	#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
AnnaBridge	189:f392fc9709a3	277	#endif /* TIM17 */
AnnaBridge	189:f392fc9709a3	278	#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
AnnaBridge	189:f392fc9709a3	279	#if defined(SAI2)
AnnaBridge	189:f392fc9709a3	280	#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
AnnaBridge	189:f392fc9709a3	281	#endif /* SAI2 */
AnnaBridge	189:f392fc9709a3	282	#if defined(DFSDM1_Channel0)
AnnaBridge	189:f392fc9709a3	283	#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
AnnaBridge	189:f392fc9709a3	284	#endif /* DFSDM1_Channel0 */
AnnaBridge	189:f392fc9709a3	285	#if defined(LTDC)
AnnaBridge	189:f392fc9709a3	286	#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
AnnaBridge	189:f392fc9709a3	287	#endif /* LTDC */
AnnaBridge	189:f392fc9709a3	288	#if defined(DSI)
AnnaBridge	189:f392fc9709a3	289	#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
AnnaBridge	189:f392fc9709a3	290	#endif /* DSI */
AnnaBridge	189:f392fc9709a3	291	/**
AnnaBridge	189:f392fc9709a3	292	* @}
AnnaBridge	189:f392fc9709a3	293	*/
AnnaBridge	189:f392fc9709a3	294
AnnaBridge	189:f392fc9709a3	295	/** Legacy definitions for compatibility purpose
AnnaBridge	189:f392fc9709a3	296	@cond 0
AnnaBridge	189:f392fc9709a3	297	*/
AnnaBridge	189:f392fc9709a3	298	#if defined(DFSDM1_Channel0)
AnnaBridge	189:f392fc9709a3	299	#define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1
AnnaBridge	189:f392fc9709a3	300	#endif /* DFSDM1_Channel0 */
AnnaBridge	189:f392fc9709a3	301	/**
AnnaBridge	189:f392fc9709a3	302	@endcond
AnnaBridge	189:f392fc9709a3	303	*/
AnnaBridge	189:f392fc9709a3	304
AnnaBridge	189:f392fc9709a3	305	/**
AnnaBridge	189:f392fc9709a3	306	* @}
AnnaBridge	189:f392fc9709a3	307	*/
AnnaBridge	189:f392fc9709a3	308
AnnaBridge	189:f392fc9709a3	309	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	310	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	311	/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
AnnaBridge	189:f392fc9709a3	312	* @{
AnnaBridge	189:f392fc9709a3	313	*/
AnnaBridge	189:f392fc9709a3	314
AnnaBridge	189:f392fc9709a3	315	/** @defgroup BUS_LL_EF_AHB1 AHB1
AnnaBridge	189:f392fc9709a3	316	* @{
AnnaBridge	189:f392fc9709a3	317	*/
AnnaBridge	189:f392fc9709a3	318
AnnaBridge	189:f392fc9709a3	319	/**
AnnaBridge	189:f392fc9709a3	320	* @brief Enable AHB1 peripherals clock.
AnnaBridge	189:f392fc9709a3	321	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	322	* AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	323	* AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	324	* AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	325	* AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	326	* AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	327	* AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	328	* AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock
AnnaBridge	189:f392fc9709a3	329	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	330	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	189:f392fc9709a3	331	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	189:f392fc9709a3	332	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	189:f392fc9709a3	333	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	189:f392fc9709a3	334	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	189:f392fc9709a3	335	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	189:f392fc9709a3	336	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	189:f392fc9709a3	337	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	189:f392fc9709a3	338	*
AnnaBridge	189:f392fc9709a3	339	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	340	* @retval None
AnnaBridge	189:f392fc9709a3	341	*/
AnnaBridge	189:f392fc9709a3	342	__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	343	{
AnnaBridge	189:f392fc9709a3	344	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	345	SET_BIT(RCC->AHB1ENR, Periphs);
AnnaBridge	189:f392fc9709a3	346	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	189:f392fc9709a3	347	tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
AnnaBridge	189:f392fc9709a3	348	(void)tmpreg;
AnnaBridge	189:f392fc9709a3	349	}
AnnaBridge	189:f392fc9709a3	350
AnnaBridge	189:f392fc9709a3	351	/**
AnnaBridge	189:f392fc9709a3	352	* @brief Check if AHB1 peripheral clock is enabled or not
AnnaBridge	189:f392fc9709a3	353	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	354	* AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	355	* AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	356	* AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	357	* AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	358	* AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	359	* AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	360	* AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock
AnnaBridge	189:f392fc9709a3	361	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	362	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	189:f392fc9709a3	363	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	189:f392fc9709a3	364	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	189:f392fc9709a3	365	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	189:f392fc9709a3	366	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	189:f392fc9709a3	367	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	189:f392fc9709a3	368	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	189:f392fc9709a3	369	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	189:f392fc9709a3	370	*
AnnaBridge	189:f392fc9709a3	371	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	372	* @retval State of Periphs (1 or 0).
AnnaBridge	189:f392fc9709a3	373	*/
AnnaBridge	189:f392fc9709a3	374	__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	375	{
AnnaBridge	189:f392fc9709a3	376	return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
AnnaBridge	189:f392fc9709a3	377	}
AnnaBridge	189:f392fc9709a3	378
AnnaBridge	189:f392fc9709a3	379	/**
AnnaBridge	189:f392fc9709a3	380	* @brief Disable AHB1 peripherals clock.
AnnaBridge	189:f392fc9709a3	381	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	382	* AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	383	* AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	384	* AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	385	* AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	386	* AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	387	* AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	388	* AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock
AnnaBridge	189:f392fc9709a3	389	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	390	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	189:f392fc9709a3	391	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	189:f392fc9709a3	392	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	189:f392fc9709a3	393	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	189:f392fc9709a3	394	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	189:f392fc9709a3	395	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	189:f392fc9709a3	396	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	189:f392fc9709a3	397	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	189:f392fc9709a3	398	*
AnnaBridge	189:f392fc9709a3	399	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	400	* @retval None
AnnaBridge	189:f392fc9709a3	401	*/
AnnaBridge	189:f392fc9709a3	402	__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	403	{
AnnaBridge	189:f392fc9709a3	404	CLEAR_BIT(RCC->AHB1ENR, Periphs);
AnnaBridge	189:f392fc9709a3	405	}
AnnaBridge	189:f392fc9709a3	406
AnnaBridge	189:f392fc9709a3	407	/**
AnnaBridge	189:f392fc9709a3	408	* @brief Force AHB1 peripherals reset.
AnnaBridge	189:f392fc9709a3	409	* @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	410	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	411	* AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	412	* AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	413	* AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	414	* AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	415	* AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	416	* AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset
AnnaBridge	189:f392fc9709a3	417	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	418	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
AnnaBridge	189:f392fc9709a3	419	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	189:f392fc9709a3	420	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	189:f392fc9709a3	421	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	189:f392fc9709a3	422	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	189:f392fc9709a3	423	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	189:f392fc9709a3	424	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	189:f392fc9709a3	425	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	189:f392fc9709a3	426	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	189:f392fc9709a3	427	*
AnnaBridge	189:f392fc9709a3	428	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	429	* @retval None
AnnaBridge	189:f392fc9709a3	430	*/
AnnaBridge	189:f392fc9709a3	431	__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	432	{
AnnaBridge	189:f392fc9709a3	433	SET_BIT(RCC->AHB1RSTR, Periphs);
AnnaBridge	189:f392fc9709a3	434	}
AnnaBridge	189:f392fc9709a3	435
AnnaBridge	189:f392fc9709a3	436	/**
AnnaBridge	189:f392fc9709a3	437	* @brief Release AHB1 peripherals reset.
AnnaBridge	189:f392fc9709a3	438	* @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	439	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	440	* AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	441	* AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	442	* AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	443	* AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	444	* AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	445	* AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset
AnnaBridge	189:f392fc9709a3	446	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	447	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
AnnaBridge	189:f392fc9709a3	448	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	189:f392fc9709a3	449	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	189:f392fc9709a3	450	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	189:f392fc9709a3	451	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	189:f392fc9709a3	452	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	189:f392fc9709a3	453	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	189:f392fc9709a3	454	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	189:f392fc9709a3	455	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	189:f392fc9709a3	456	*
AnnaBridge	189:f392fc9709a3	457	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	458	* @retval None
AnnaBridge	189:f392fc9709a3	459	*/
AnnaBridge	189:f392fc9709a3	460	__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	461	{
AnnaBridge	189:f392fc9709a3	462	CLEAR_BIT(RCC->AHB1RSTR, Periphs);
AnnaBridge	189:f392fc9709a3	463	}
AnnaBridge	189:f392fc9709a3	464
AnnaBridge	189:f392fc9709a3	465	/**
AnnaBridge	189:f392fc9709a3	466	* @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
AnnaBridge	189:f392fc9709a3	467	* @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	468	* AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	469	* AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	470	* AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	471	* AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	472	* AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	473	* AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	474	* AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	475	* AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep
AnnaBridge	189:f392fc9709a3	476	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	477	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	189:f392fc9709a3	478	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	189:f392fc9709a3	479	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	189:f392fc9709a3	480	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	189:f392fc9709a3	481	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
AnnaBridge	189:f392fc9709a3	482	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	189:f392fc9709a3	483	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	189:f392fc9709a3	484	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	189:f392fc9709a3	485	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	189:f392fc9709a3	486	*
AnnaBridge	189:f392fc9709a3	487	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	488	* @retval None
AnnaBridge	189:f392fc9709a3	489	*/
AnnaBridge	189:f392fc9709a3	490	__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	491	{
AnnaBridge	189:f392fc9709a3	492	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	493	SET_BIT(RCC->AHB1SMENR, Periphs);
AnnaBridge	189:f392fc9709a3	494	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	189:f392fc9709a3	495	tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
AnnaBridge	189:f392fc9709a3	496	(void)tmpreg;
AnnaBridge	189:f392fc9709a3	497	}
AnnaBridge	189:f392fc9709a3	498
AnnaBridge	189:f392fc9709a3	499	/**
AnnaBridge	189:f392fc9709a3	500	* @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
AnnaBridge	189:f392fc9709a3	501	* @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	502	* AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	503	* AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	504	* AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	505	* AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	506	* AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	507	* AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	508	* AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	509	* AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep
AnnaBridge	189:f392fc9709a3	510	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	511	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	189:f392fc9709a3	512	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	189:f392fc9709a3	513	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	189:f392fc9709a3	514	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	189:f392fc9709a3	515	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
AnnaBridge	189:f392fc9709a3	516	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	189:f392fc9709a3	517	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	189:f392fc9709a3	518	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	189:f392fc9709a3	519	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	189:f392fc9709a3	520	*
AnnaBridge	189:f392fc9709a3	521	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	522	* @retval None
AnnaBridge	189:f392fc9709a3	523	*/
AnnaBridge	189:f392fc9709a3	524	__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	525	{
AnnaBridge	189:f392fc9709a3	526	CLEAR_BIT(RCC->AHB1SMENR, Periphs);
AnnaBridge	189:f392fc9709a3	527	}
AnnaBridge	189:f392fc9709a3	528
AnnaBridge	189:f392fc9709a3	529	/**
AnnaBridge	189:f392fc9709a3	530	* @}
AnnaBridge	189:f392fc9709a3	531	*/
AnnaBridge	189:f392fc9709a3	532
AnnaBridge	189:f392fc9709a3	533	/** @defgroup BUS_LL_EF_AHB2 AHB2
AnnaBridge	189:f392fc9709a3	534	* @{
AnnaBridge	189:f392fc9709a3	535	*/
AnnaBridge	189:f392fc9709a3	536
AnnaBridge	189:f392fc9709a3	537	/**
AnnaBridge	189:f392fc9709a3	538	* @brief Enable AHB2 peripherals clock.
AnnaBridge	189:f392fc9709a3	539	* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	540	* AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	541	* AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	542	* AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	543	* AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	544	* AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	545	* AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	546	* AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	547	* AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	548	* AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	549	* AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	550	* AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	551	* AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	552	* AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	553	* AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	554	* AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	555	* AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock
AnnaBridge	189:f392fc9709a3	556	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	557	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	189:f392fc9709a3	558	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	189:f392fc9709a3	559	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	189:f392fc9709a3	560	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	189:f392fc9709a3	561	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	189:f392fc9709a3	562	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	189:f392fc9709a3	563	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	189:f392fc9709a3	564	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	189:f392fc9709a3	565	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	189:f392fc9709a3	566	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	189:f392fc9709a3	567	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	189:f392fc9709a3	568	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	189:f392fc9709a3	569	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	189:f392fc9709a3	570	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	189:f392fc9709a3	571	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	189:f392fc9709a3	572	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	189:f392fc9709a3	573	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	574	*
AnnaBridge	189:f392fc9709a3	575	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	576	* @retval None
AnnaBridge	189:f392fc9709a3	577	*/
AnnaBridge	189:f392fc9709a3	578	__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	579	{
AnnaBridge	189:f392fc9709a3	580	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	581	SET_BIT(RCC->AHB2ENR, Periphs);
AnnaBridge	189:f392fc9709a3	582	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	189:f392fc9709a3	583	tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
AnnaBridge	189:f392fc9709a3	584	(void)tmpreg;
AnnaBridge	189:f392fc9709a3	585	}
AnnaBridge	189:f392fc9709a3	586
AnnaBridge	189:f392fc9709a3	587	/**
AnnaBridge	189:f392fc9709a3	588	* @brief Check if AHB2 peripheral clock is enabled or not
AnnaBridge	189:f392fc9709a3	589	* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	590	* AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	591	* AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	592	* AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	593	* AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	594	* AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	595	* AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	596	* AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	597	* AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	598	* AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	599	* AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	600	* AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	601	* AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	602	* AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	603	* AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	604	* AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	605	* AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock
AnnaBridge	189:f392fc9709a3	606	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	607	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	189:f392fc9709a3	608	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	189:f392fc9709a3	609	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	189:f392fc9709a3	610	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	189:f392fc9709a3	611	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	189:f392fc9709a3	612	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	189:f392fc9709a3	613	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	189:f392fc9709a3	614	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	189:f392fc9709a3	615	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	189:f392fc9709a3	616	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	189:f392fc9709a3	617	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	189:f392fc9709a3	618	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	189:f392fc9709a3	619	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	189:f392fc9709a3	620	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	189:f392fc9709a3	621	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	189:f392fc9709a3	622	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	189:f392fc9709a3	623	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	624	*
AnnaBridge	189:f392fc9709a3	625	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	626	* @retval State of Periphs (1 or 0).
AnnaBridge	189:f392fc9709a3	627	*/
AnnaBridge	189:f392fc9709a3	628	__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	629	{
AnnaBridge	189:f392fc9709a3	630	return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
AnnaBridge	189:f392fc9709a3	631	}
AnnaBridge	189:f392fc9709a3	632
AnnaBridge	189:f392fc9709a3	633	/**
AnnaBridge	189:f392fc9709a3	634	* @brief Disable AHB2 peripherals clock.
AnnaBridge	189:f392fc9709a3	635	* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	636	* AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	637	* AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	638	* AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	639	* AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	640	* AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	641	* AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	642	* AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	643	* AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	644	* AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	645	* AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	646	* AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	647	* AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	648	* AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	649	* AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	650	* AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	651	* AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock
AnnaBridge	189:f392fc9709a3	652	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	653	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	189:f392fc9709a3	654	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	189:f392fc9709a3	655	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	189:f392fc9709a3	656	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	189:f392fc9709a3	657	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	189:f392fc9709a3	658	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	189:f392fc9709a3	659	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	189:f392fc9709a3	660	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	189:f392fc9709a3	661	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	189:f392fc9709a3	662	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	189:f392fc9709a3	663	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	189:f392fc9709a3	664	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	189:f392fc9709a3	665	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	189:f392fc9709a3	666	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	189:f392fc9709a3	667	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	189:f392fc9709a3	668	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	189:f392fc9709a3	669	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	670	*
AnnaBridge	189:f392fc9709a3	671	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	672	* @retval None
AnnaBridge	189:f392fc9709a3	673	*/
AnnaBridge	189:f392fc9709a3	674	__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	675	{
AnnaBridge	189:f392fc9709a3	676	CLEAR_BIT(RCC->AHB2ENR, Periphs);
AnnaBridge	189:f392fc9709a3	677	}
AnnaBridge	189:f392fc9709a3	678
AnnaBridge	189:f392fc9709a3	679	/**
AnnaBridge	189:f392fc9709a3	680	* @brief Force AHB2 peripherals reset.
AnnaBridge	189:f392fc9709a3	681	* @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	682	* AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	683	* AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	684	* AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	685	* AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	686	* AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	687	* AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	688	* AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	689	* AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	690	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	691	* AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	692	* AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	693	* AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	694	* AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	695	* AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	696	* AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	697	* AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset
AnnaBridge	189:f392fc9709a3	698	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	699	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
AnnaBridge	189:f392fc9709a3	700	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	189:f392fc9709a3	701	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	189:f392fc9709a3	702	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	189:f392fc9709a3	703	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	189:f392fc9709a3	704	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	189:f392fc9709a3	705	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	189:f392fc9709a3	706	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	189:f392fc9709a3	707	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	189:f392fc9709a3	708	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	189:f392fc9709a3	709	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	189:f392fc9709a3	710	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	189:f392fc9709a3	711	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	189:f392fc9709a3	712	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	189:f392fc9709a3	713	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	189:f392fc9709a3	714	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	189:f392fc9709a3	715	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	189:f392fc9709a3	716	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	717	*
AnnaBridge	189:f392fc9709a3	718	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	719	* @retval None
AnnaBridge	189:f392fc9709a3	720	*/
AnnaBridge	189:f392fc9709a3	721	__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	722	{
AnnaBridge	189:f392fc9709a3	723	SET_BIT(RCC->AHB2RSTR, Periphs);
AnnaBridge	189:f392fc9709a3	724	}
AnnaBridge	189:f392fc9709a3	725
AnnaBridge	189:f392fc9709a3	726	/**
AnnaBridge	189:f392fc9709a3	727	* @brief Release AHB2 peripherals reset.
AnnaBridge	189:f392fc9709a3	728	* @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	729	* AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	730	* AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	731	* AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	732	* AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	733	* AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	734	* AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	735	* AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	736	* AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	737	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	738	* AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	739	* AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	740	* AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	741	* AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	742	* AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	743	* AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	744	* AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset
AnnaBridge	189:f392fc9709a3	745	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	746	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
AnnaBridge	189:f392fc9709a3	747	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	189:f392fc9709a3	748	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	189:f392fc9709a3	749	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	189:f392fc9709a3	750	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	189:f392fc9709a3	751	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	189:f392fc9709a3	752	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	189:f392fc9709a3	753	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	189:f392fc9709a3	754	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	189:f392fc9709a3	755	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	189:f392fc9709a3	756	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	189:f392fc9709a3	757	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	189:f392fc9709a3	758	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	189:f392fc9709a3	759	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	189:f392fc9709a3	760	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	189:f392fc9709a3	761	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	189:f392fc9709a3	762	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	189:f392fc9709a3	763	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	764	*
AnnaBridge	189:f392fc9709a3	765	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	766	* @retval None
AnnaBridge	189:f392fc9709a3	767	*/
AnnaBridge	189:f392fc9709a3	768	__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	769	{
AnnaBridge	189:f392fc9709a3	770	CLEAR_BIT(RCC->AHB2RSTR, Periphs);
AnnaBridge	189:f392fc9709a3	771	}
AnnaBridge	189:f392fc9709a3	772
AnnaBridge	189:f392fc9709a3	773	/**
AnnaBridge	189:f392fc9709a3	774	* @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
AnnaBridge	189:f392fc9709a3	775	* @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	776	* AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	777	* AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	778	* AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	779	* AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	780	* AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	781	* AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	782	* AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	783	* AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	784	* AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	785	* AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	786	* AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	787	* AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	788	* AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	789	* AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	790	* AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	791	* AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	792	* AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	793	* AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep
AnnaBridge	189:f392fc9709a3	794	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	795	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	189:f392fc9709a3	796	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	189:f392fc9709a3	797	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	189:f392fc9709a3	798	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	189:f392fc9709a3	799	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	189:f392fc9709a3	800	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	189:f392fc9709a3	801	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	189:f392fc9709a3	802	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	189:f392fc9709a3	803	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	189:f392fc9709a3	804	* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
AnnaBridge	189:f392fc9709a3	805	* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
AnnaBridge	189:f392fc9709a3	806	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	189:f392fc9709a3	807	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	189:f392fc9709a3	808	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	189:f392fc9709a3	809	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	189:f392fc9709a3	810	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	189:f392fc9709a3	811	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	189:f392fc9709a3	812	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	189:f392fc9709a3	813	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	814	*
AnnaBridge	189:f392fc9709a3	815	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	816	* @retval None
AnnaBridge	189:f392fc9709a3	817	*/
AnnaBridge	189:f392fc9709a3	818	__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	819	{
AnnaBridge	189:f392fc9709a3	820	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	821	SET_BIT(RCC->AHB2SMENR, Periphs);
AnnaBridge	189:f392fc9709a3	822	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	189:f392fc9709a3	823	tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
AnnaBridge	189:f392fc9709a3	824	(void)tmpreg;
AnnaBridge	189:f392fc9709a3	825	}
AnnaBridge	189:f392fc9709a3	826
AnnaBridge	189:f392fc9709a3	827	/**
AnnaBridge	189:f392fc9709a3	828	* @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
AnnaBridge	189:f392fc9709a3	829	* @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	830	* AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	831	* AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	832	* AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	833	* AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	834	* AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	835	* AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	836	* AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	837	* AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	838	* AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	839	* AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	840	* AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	841	* AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	842	* AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	843	* AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	844	* AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	845	* AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	846	* AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	847	* AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep
AnnaBridge	189:f392fc9709a3	848	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	849	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	189:f392fc9709a3	850	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	189:f392fc9709a3	851	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	189:f392fc9709a3	852	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	189:f392fc9709a3	853	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	189:f392fc9709a3	854	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	189:f392fc9709a3	855	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	189:f392fc9709a3	856	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	189:f392fc9709a3	857	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	189:f392fc9709a3	858	* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
AnnaBridge	189:f392fc9709a3	859	* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
AnnaBridge	189:f392fc9709a3	860	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	189:f392fc9709a3	861	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	189:f392fc9709a3	862	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	189:f392fc9709a3	863	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	189:f392fc9709a3	864	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	189:f392fc9709a3	865	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	189:f392fc9709a3	866	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	189:f392fc9709a3	867	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	868	*
AnnaBridge	189:f392fc9709a3	869	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	870	* @retval None
AnnaBridge	189:f392fc9709a3	871	*/
AnnaBridge	189:f392fc9709a3	872	__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	873	{
AnnaBridge	189:f392fc9709a3	874	CLEAR_BIT(RCC->AHB2SMENR, Periphs);
AnnaBridge	189:f392fc9709a3	875	}
AnnaBridge	189:f392fc9709a3	876
AnnaBridge	189:f392fc9709a3	877	/**
AnnaBridge	189:f392fc9709a3	878	* @}
AnnaBridge	189:f392fc9709a3	879	*/
AnnaBridge	189:f392fc9709a3	880
AnnaBridge	189:f392fc9709a3	881	/** @defgroup BUS_LL_EF_AHB3 AHB3
AnnaBridge	189:f392fc9709a3	882	* @{
AnnaBridge	189:f392fc9709a3	883	*/
AnnaBridge	189:f392fc9709a3	884
AnnaBridge	189:f392fc9709a3	885	/**
AnnaBridge	189:f392fc9709a3	886	* @brief Enable AHB3 peripherals clock.
AnnaBridge	189:f392fc9709a3	887	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	888	* AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	889	* AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	890	* AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock
AnnaBridge	189:f392fc9709a3	891	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	892	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	189:f392fc9709a3	893	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	189:f392fc9709a3	894	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	189:f392fc9709a3	895	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	189:f392fc9709a3	896	*
AnnaBridge	189:f392fc9709a3	897	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	898	* @retval None
AnnaBridge	189:f392fc9709a3	899	*/
AnnaBridge	189:f392fc9709a3	900	__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	901	{
AnnaBridge	189:f392fc9709a3	902	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	903	SET_BIT(RCC->AHB3ENR, Periphs);
AnnaBridge	189:f392fc9709a3	904	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	189:f392fc9709a3	905	tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
AnnaBridge	189:f392fc9709a3	906	(void)tmpreg;
AnnaBridge	189:f392fc9709a3	907	}
AnnaBridge	189:f392fc9709a3	908
AnnaBridge	189:f392fc9709a3	909	/**
AnnaBridge	189:f392fc9709a3	910	* @brief Check if AHB3 peripheral clock is enabled or not
AnnaBridge	189:f392fc9709a3	911	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	912	* AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	913	* AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	914	* AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock
AnnaBridge	189:f392fc9709a3	915	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	916	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	189:f392fc9709a3	917	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	189:f392fc9709a3	918	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	189:f392fc9709a3	919	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	189:f392fc9709a3	920	*
AnnaBridge	189:f392fc9709a3	921	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	922	* @retval State of Periphs (1 or 0).
AnnaBridge	189:f392fc9709a3	923	*/
AnnaBridge	189:f392fc9709a3	924	__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	925	{
AnnaBridge	189:f392fc9709a3	926	return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
AnnaBridge	189:f392fc9709a3	927	}
AnnaBridge	189:f392fc9709a3	928
AnnaBridge	189:f392fc9709a3	929	/**
AnnaBridge	189:f392fc9709a3	930	* @brief Disable AHB3 peripherals clock.
AnnaBridge	189:f392fc9709a3	931	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	932	* AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	933	* AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	934	* AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock
AnnaBridge	189:f392fc9709a3	935	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	936	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	189:f392fc9709a3	937	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	189:f392fc9709a3	938	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	189:f392fc9709a3	939	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	189:f392fc9709a3	940	*
AnnaBridge	189:f392fc9709a3	941	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	942	* @retval None
AnnaBridge	189:f392fc9709a3	943	*/
AnnaBridge	189:f392fc9709a3	944	__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	945	{
AnnaBridge	189:f392fc9709a3	946	CLEAR_BIT(RCC->AHB3ENR, Periphs);
AnnaBridge	189:f392fc9709a3	947	}
AnnaBridge	189:f392fc9709a3	948
AnnaBridge	189:f392fc9709a3	949	/**
AnnaBridge	189:f392fc9709a3	950	* @brief Force AHB3 peripherals reset.
AnnaBridge	189:f392fc9709a3	951	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	952	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	953	* AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	954	* AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset
AnnaBridge	189:f392fc9709a3	955	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	956	* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
AnnaBridge	189:f392fc9709a3	957	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	189:f392fc9709a3	958	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	189:f392fc9709a3	959	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	189:f392fc9709a3	960	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	189:f392fc9709a3	961	*
AnnaBridge	189:f392fc9709a3	962	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	963	* @retval None
AnnaBridge	189:f392fc9709a3	964	*/
AnnaBridge	189:f392fc9709a3	965	__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	966	{
AnnaBridge	189:f392fc9709a3	967	SET_BIT(RCC->AHB3RSTR, Periphs);
AnnaBridge	189:f392fc9709a3	968	}
AnnaBridge	189:f392fc9709a3	969
AnnaBridge	189:f392fc9709a3	970	/**
AnnaBridge	189:f392fc9709a3	971	* @brief Release AHB3 peripherals reset.
AnnaBridge	189:f392fc9709a3	972	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	973	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	974	* AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	975	* AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset
AnnaBridge	189:f392fc9709a3	976	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	977	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
AnnaBridge	189:f392fc9709a3	978	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	189:f392fc9709a3	979	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	189:f392fc9709a3	980	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	189:f392fc9709a3	981	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	189:f392fc9709a3	982	*
AnnaBridge	189:f392fc9709a3	983	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	984	* @retval None
AnnaBridge	189:f392fc9709a3	985	*/
AnnaBridge	189:f392fc9709a3	986	__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	987	{
AnnaBridge	189:f392fc9709a3	988	CLEAR_BIT(RCC->AHB3RSTR, Periphs);
AnnaBridge	189:f392fc9709a3	989	}
AnnaBridge	189:f392fc9709a3	990
AnnaBridge	189:f392fc9709a3	991	/**
AnnaBridge	189:f392fc9709a3	992	* @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
AnnaBridge	189:f392fc9709a3	993	* @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	994	* AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	995	* AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	996	* AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_EnableClockStopSleep
AnnaBridge	189:f392fc9709a3	997	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	998	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	189:f392fc9709a3	999	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	189:f392fc9709a3	1000	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	189:f392fc9709a3	1001	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	189:f392fc9709a3	1002	*
AnnaBridge	189:f392fc9709a3	1003	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1004	* @retval None
AnnaBridge	189:f392fc9709a3	1005	*/
AnnaBridge	189:f392fc9709a3	1006	__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1007	{
AnnaBridge	189:f392fc9709a3	1008	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	1009	SET_BIT(RCC->AHB3SMENR, Periphs);
AnnaBridge	189:f392fc9709a3	1010	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	189:f392fc9709a3	1011	tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
AnnaBridge	189:f392fc9709a3	1012	(void)tmpreg;
AnnaBridge	189:f392fc9709a3	1013	}
AnnaBridge	189:f392fc9709a3	1014
AnnaBridge	189:f392fc9709a3	1015	/**
AnnaBridge	189:f392fc9709a3	1016	* @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
AnnaBridge	189:f392fc9709a3	1017	* @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1018	* AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1019	* AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1020	* AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1021	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1022	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	189:f392fc9709a3	1023	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	189:f392fc9709a3	1024	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	189:f392fc9709a3	1025	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	189:f392fc9709a3	1026	*
AnnaBridge	189:f392fc9709a3	1027	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1028	* @retval None
AnnaBridge	189:f392fc9709a3	1029	*/
AnnaBridge	189:f392fc9709a3	1030	__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1031	{
AnnaBridge	189:f392fc9709a3	1032	CLEAR_BIT(RCC->AHB3SMENR, Periphs);
AnnaBridge	189:f392fc9709a3	1033	}
AnnaBridge	189:f392fc9709a3	1034
AnnaBridge	189:f392fc9709a3	1035	/**
AnnaBridge	189:f392fc9709a3	1036	* @}
AnnaBridge	189:f392fc9709a3	1037	*/
AnnaBridge	189:f392fc9709a3	1038
AnnaBridge	189:f392fc9709a3	1039	/** @defgroup BUS_LL_EF_APB1 APB1
AnnaBridge	189:f392fc9709a3	1040	* @{
AnnaBridge	189:f392fc9709a3	1041	*/
AnnaBridge	189:f392fc9709a3	1042
AnnaBridge	189:f392fc9709a3	1043	/**
AnnaBridge	189:f392fc9709a3	1044	* @brief Enable APB1 peripherals clock.
AnnaBridge	189:f392fc9709a3	1045	* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1046	* APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1047	* APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1048	* APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1049	* APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1050	* APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1051	* APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1052	* APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1053	* APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1054	* APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1055	* APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1056	* APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1057	* APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1058	* APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1059	* APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1060	* APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1061	* APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1062	* APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1063	* APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1064	* APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1065	* APB1ENR1 USBFSEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1066	* APB1ENR1 CAN2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1067	* APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1068	* APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1069	* APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1070	* APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
AnnaBridge	189:f392fc9709a3	1071	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1072	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	189:f392fc9709a3	1073	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	189:f392fc9709a3	1074	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	189:f392fc9709a3	1075	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	189:f392fc9709a3	1076	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	189:f392fc9709a3	1077	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	189:f392fc9709a3	1078	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	189:f392fc9709a3	1079	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	189:f392fc9709a3	1080	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	189:f392fc9709a3	1081	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	189:f392fc9709a3	1082	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	189:f392fc9709a3	1083	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	189:f392fc9709a3	1084	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	189:f392fc9709a3	1085	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	189:f392fc9709a3	1086	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	189:f392fc9709a3	1087	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	189:f392fc9709a3	1088	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	189:f392fc9709a3	1089	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	189:f392fc9709a3	1090	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	189:f392fc9709a3	1091	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	189:f392fc9709a3	1092	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	189:f392fc9709a3	1093	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	189:f392fc9709a3	1094	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	189:f392fc9709a3	1095	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	189:f392fc9709a3	1096	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	189:f392fc9709a3	1097	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	189:f392fc9709a3	1098	*
AnnaBridge	189:f392fc9709a3	1099	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1100	* @retval None
AnnaBridge	189:f392fc9709a3	1101	*/
AnnaBridge	189:f392fc9709a3	1102	__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1103	{
AnnaBridge	189:f392fc9709a3	1104	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	1105	SET_BIT(RCC->APB1ENR1, Periphs);
AnnaBridge	189:f392fc9709a3	1106	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	189:f392fc9709a3	1107	tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
AnnaBridge	189:f392fc9709a3	1108	(void)tmpreg;
AnnaBridge	189:f392fc9709a3	1109	}
AnnaBridge	189:f392fc9709a3	1110
AnnaBridge	189:f392fc9709a3	1111	/**
AnnaBridge	189:f392fc9709a3	1112	* @brief Enable APB1 peripherals clock.
AnnaBridge	189:f392fc9709a3	1113	* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
AnnaBridge	189:f392fc9709a3	1114	* APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
AnnaBridge	189:f392fc9709a3	1115	* APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n
AnnaBridge	189:f392fc9709a3	1116	* APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
AnnaBridge	189:f392fc9709a3	1117	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1118	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	189:f392fc9709a3	1119	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	189:f392fc9709a3	1120	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	189:f392fc9709a3	1121	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	189:f392fc9709a3	1122	*
AnnaBridge	189:f392fc9709a3	1123	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1124	* @retval None
AnnaBridge	189:f392fc9709a3	1125	*/
AnnaBridge	189:f392fc9709a3	1126	__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1127	{
AnnaBridge	189:f392fc9709a3	1128	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	1129	SET_BIT(RCC->APB1ENR2, Periphs);
AnnaBridge	189:f392fc9709a3	1130	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	189:f392fc9709a3	1131	tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
AnnaBridge	189:f392fc9709a3	1132	(void)tmpreg;
AnnaBridge	189:f392fc9709a3	1133	}
AnnaBridge	189:f392fc9709a3	1134
AnnaBridge	189:f392fc9709a3	1135	/**
AnnaBridge	189:f392fc9709a3	1136	* @brief Check if APB1 peripheral clock is enabled or not
AnnaBridge	189:f392fc9709a3	1137	* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1138	* APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1139	* APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1140	* APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1141	* APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1142	* APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1143	* APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1144	* APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1145	* APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1146	* APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1147	* APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1148	* APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1149	* APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1150	* APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1151	* APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1152	* APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1153	* APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1154	* APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1155	* APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1156	* APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1157	* APB1ENR1 USBFSEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1158	* APB1ENR1 CAN2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1159	* APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1160	* APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1161	* APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1162	* APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
AnnaBridge	189:f392fc9709a3	1163	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1164	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	189:f392fc9709a3	1165	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	189:f392fc9709a3	1166	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	189:f392fc9709a3	1167	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	189:f392fc9709a3	1168	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	189:f392fc9709a3	1169	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	189:f392fc9709a3	1170	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	189:f392fc9709a3	1171	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	189:f392fc9709a3	1172	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	189:f392fc9709a3	1173	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	189:f392fc9709a3	1174	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	189:f392fc9709a3	1175	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	189:f392fc9709a3	1176	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	189:f392fc9709a3	1177	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	189:f392fc9709a3	1178	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	189:f392fc9709a3	1179	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	189:f392fc9709a3	1180	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	189:f392fc9709a3	1181	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	189:f392fc9709a3	1182	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	189:f392fc9709a3	1183	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	189:f392fc9709a3	1184	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	189:f392fc9709a3	1185	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	189:f392fc9709a3	1186	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	189:f392fc9709a3	1187	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	189:f392fc9709a3	1188	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	189:f392fc9709a3	1189	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	189:f392fc9709a3	1190	*
AnnaBridge	189:f392fc9709a3	1191	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1192	* @retval State of Periphs (1 or 0).
AnnaBridge	189:f392fc9709a3	1193	*/
AnnaBridge	189:f392fc9709a3	1194	__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1195	{
AnnaBridge	189:f392fc9709a3	1196	return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs);
AnnaBridge	189:f392fc9709a3	1197	}
AnnaBridge	189:f392fc9709a3	1198
AnnaBridge	189:f392fc9709a3	1199	/**
AnnaBridge	189:f392fc9709a3	1200	* @brief Check if APB1 peripheral clock is enabled or not
AnnaBridge	189:f392fc9709a3	1201	* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1202	* APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1203	* APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1204	* APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
AnnaBridge	189:f392fc9709a3	1205	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1206	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	189:f392fc9709a3	1207	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	189:f392fc9709a3	1208	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	189:f392fc9709a3	1209	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	189:f392fc9709a3	1210	*
AnnaBridge	189:f392fc9709a3	1211	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1212	* @retval State of Periphs (1 or 0).
AnnaBridge	189:f392fc9709a3	1213	*/
AnnaBridge	189:f392fc9709a3	1214	__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1215	{
AnnaBridge	189:f392fc9709a3	1216	return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs);
AnnaBridge	189:f392fc9709a3	1217	}
AnnaBridge	189:f392fc9709a3	1218
AnnaBridge	189:f392fc9709a3	1219	/**
AnnaBridge	189:f392fc9709a3	1220	* @brief Disable APB1 peripherals clock.
AnnaBridge	189:f392fc9709a3	1221	* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1222	* APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1223	* APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1224	* APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1225	* APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1226	* APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1227	* APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1228	* APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1229	* APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1230	* APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1231	* APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1232	* APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1233	* APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1234	* APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1235	* APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1236	* APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1237	* APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1238	* APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1239	* APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1240	* APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1241	* APB1ENR1 USBFSEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1242	* APB1ENR1 CAN2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1243	* APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1244	* APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1245	* APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1246	* APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
AnnaBridge	189:f392fc9709a3	1247	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1248	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	189:f392fc9709a3	1249	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	189:f392fc9709a3	1250	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	189:f392fc9709a3	1251	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	189:f392fc9709a3	1252	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	189:f392fc9709a3	1253	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	189:f392fc9709a3	1254	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	189:f392fc9709a3	1255	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	189:f392fc9709a3	1256	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	189:f392fc9709a3	1257	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	189:f392fc9709a3	1258	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	189:f392fc9709a3	1259	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	189:f392fc9709a3	1260	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	189:f392fc9709a3	1261	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	189:f392fc9709a3	1262	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	189:f392fc9709a3	1263	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	189:f392fc9709a3	1264	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	189:f392fc9709a3	1265	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	189:f392fc9709a3	1266	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	189:f392fc9709a3	1267	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	189:f392fc9709a3	1268	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	189:f392fc9709a3	1269	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	189:f392fc9709a3	1270	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	189:f392fc9709a3	1271	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	189:f392fc9709a3	1272	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	189:f392fc9709a3	1273	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	189:f392fc9709a3	1274	*
AnnaBridge	189:f392fc9709a3	1275	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1276	* @retval None
AnnaBridge	189:f392fc9709a3	1277	*/
AnnaBridge	189:f392fc9709a3	1278	__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1279	{
AnnaBridge	189:f392fc9709a3	1280	CLEAR_BIT(RCC->APB1ENR1, Periphs);
AnnaBridge	189:f392fc9709a3	1281	}
AnnaBridge	189:f392fc9709a3	1282
AnnaBridge	189:f392fc9709a3	1283	/**
AnnaBridge	189:f392fc9709a3	1284	* @brief Disable APB1 peripherals clock.
AnnaBridge	189:f392fc9709a3	1285	* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
AnnaBridge	189:f392fc9709a3	1286	* APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
AnnaBridge	189:f392fc9709a3	1287	* APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n
AnnaBridge	189:f392fc9709a3	1288	* APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
AnnaBridge	189:f392fc9709a3	1289	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1290	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	189:f392fc9709a3	1291	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	189:f392fc9709a3	1292	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	189:f392fc9709a3	1293	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	189:f392fc9709a3	1294	*
AnnaBridge	189:f392fc9709a3	1295	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1296	* @retval None
AnnaBridge	189:f392fc9709a3	1297	*/
AnnaBridge	189:f392fc9709a3	1298	__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1299	{
AnnaBridge	189:f392fc9709a3	1300	CLEAR_BIT(RCC->APB1ENR2, Periphs);
AnnaBridge	189:f392fc9709a3	1301	}
AnnaBridge	189:f392fc9709a3	1302
AnnaBridge	189:f392fc9709a3	1303	/**
AnnaBridge	189:f392fc9709a3	1304	* @brief Force APB1 peripherals reset.
AnnaBridge	189:f392fc9709a3	1305	* @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1306	* APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1307	* APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1308	* APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1309	* APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1310	* APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1311	* APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1312	* APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1313	* APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1314	* APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1315	* APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1316	* APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1317	* APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1318	* APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1319	* APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1320	* APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1321	* APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1322	* APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1323	* APB1RSTR1 USBFSRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1324	* APB1RSTR1 CAN2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1325	* APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1326	* APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1327	* APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1328	* APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
AnnaBridge	189:f392fc9709a3	1329	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1330	* @arg @ref LL_APB1_GRP1_PERIPH_ALL
AnnaBridge	189:f392fc9709a3	1331	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	189:f392fc9709a3	1332	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	189:f392fc9709a3	1333	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	189:f392fc9709a3	1334	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	189:f392fc9709a3	1335	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	189:f392fc9709a3	1336	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	189:f392fc9709a3	1337	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	189:f392fc9709a3	1338	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	189:f392fc9709a3	1339	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	189:f392fc9709a3	1340	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	189:f392fc9709a3	1341	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	189:f392fc9709a3	1342	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	189:f392fc9709a3	1343	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	189:f392fc9709a3	1344	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	189:f392fc9709a3	1345	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	189:f392fc9709a3	1346	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	189:f392fc9709a3	1347	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	189:f392fc9709a3	1348	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	189:f392fc9709a3	1349	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	189:f392fc9709a3	1350	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	189:f392fc9709a3	1351	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	189:f392fc9709a3	1352	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	189:f392fc9709a3	1353	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	189:f392fc9709a3	1354	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	189:f392fc9709a3	1355	*
AnnaBridge	189:f392fc9709a3	1356	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1357	* @retval None
AnnaBridge	189:f392fc9709a3	1358	*/
AnnaBridge	189:f392fc9709a3	1359	__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1360	{
AnnaBridge	189:f392fc9709a3	1361	SET_BIT(RCC->APB1RSTR1, Periphs);
AnnaBridge	189:f392fc9709a3	1362	}
AnnaBridge	189:f392fc9709a3	1363
AnnaBridge	189:f392fc9709a3	1364	/**
AnnaBridge	189:f392fc9709a3	1365	* @brief Force APB1 peripherals reset.
AnnaBridge	189:f392fc9709a3	1366	* @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
AnnaBridge	189:f392fc9709a3	1367	* APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n
AnnaBridge	189:f392fc9709a3	1368	* APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n
AnnaBridge	189:f392fc9709a3	1369	* APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
AnnaBridge	189:f392fc9709a3	1370	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1371	* @arg @ref LL_APB1_GRP2_PERIPH_ALL
AnnaBridge	189:f392fc9709a3	1372	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	189:f392fc9709a3	1373	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	189:f392fc9709a3	1374	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	189:f392fc9709a3	1375	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	189:f392fc9709a3	1376	*
AnnaBridge	189:f392fc9709a3	1377	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1378	* @retval None
AnnaBridge	189:f392fc9709a3	1379	*/
AnnaBridge	189:f392fc9709a3	1380	__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1381	{
AnnaBridge	189:f392fc9709a3	1382	SET_BIT(RCC->APB1RSTR2, Periphs);
AnnaBridge	189:f392fc9709a3	1383	}
AnnaBridge	189:f392fc9709a3	1384
AnnaBridge	189:f392fc9709a3	1385	/**
AnnaBridge	189:f392fc9709a3	1386	* @brief Release APB1 peripherals reset.
AnnaBridge	189:f392fc9709a3	1387	* @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1388	* APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1389	* APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1390	* APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1391	* APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1392	* APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1393	* APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1394	* APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1395	* APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1396	* APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1397	* APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1398	* APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1399	* APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1400	* APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1401	* APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1402	* APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1403	* APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1404	* APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1405	* APB1RSTR1 USBFSRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1406	* APB1RSTR1 CAN2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1407	* APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1408	* APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1409	* APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1410	* APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
AnnaBridge	189:f392fc9709a3	1411	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1412	* @arg @ref LL_APB1_GRP1_PERIPH_ALL
AnnaBridge	189:f392fc9709a3	1413	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	189:f392fc9709a3	1414	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	189:f392fc9709a3	1415	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	189:f392fc9709a3	1416	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	189:f392fc9709a3	1417	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	189:f392fc9709a3	1418	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	189:f392fc9709a3	1419	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	189:f392fc9709a3	1420	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	189:f392fc9709a3	1421	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	189:f392fc9709a3	1422	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	189:f392fc9709a3	1423	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	189:f392fc9709a3	1424	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	189:f392fc9709a3	1425	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	189:f392fc9709a3	1426	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	189:f392fc9709a3	1427	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	189:f392fc9709a3	1428	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	189:f392fc9709a3	1429	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	189:f392fc9709a3	1430	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	189:f392fc9709a3	1431	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	189:f392fc9709a3	1432	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	189:f392fc9709a3	1433	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	189:f392fc9709a3	1434	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	189:f392fc9709a3	1435	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	189:f392fc9709a3	1436	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	189:f392fc9709a3	1437	*
AnnaBridge	189:f392fc9709a3	1438	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1439	* @retval None
AnnaBridge	189:f392fc9709a3	1440	*/
AnnaBridge	189:f392fc9709a3	1441	__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1442	{
AnnaBridge	189:f392fc9709a3	1443	CLEAR_BIT(RCC->APB1RSTR1, Periphs);
AnnaBridge	189:f392fc9709a3	1444	}
AnnaBridge	189:f392fc9709a3	1445
AnnaBridge	189:f392fc9709a3	1446	/**
AnnaBridge	189:f392fc9709a3	1447	* @brief Release APB1 peripherals reset.
AnnaBridge	189:f392fc9709a3	1448	* @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1449	* APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1450	* APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1451	* APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
AnnaBridge	189:f392fc9709a3	1452	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1453	* @arg @ref LL_APB1_GRP2_PERIPH_ALL
AnnaBridge	189:f392fc9709a3	1454	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	189:f392fc9709a3	1455	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	189:f392fc9709a3	1456	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	189:f392fc9709a3	1457	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	189:f392fc9709a3	1458	*
AnnaBridge	189:f392fc9709a3	1459	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1460	* @retval None
AnnaBridge	189:f392fc9709a3	1461	*/
AnnaBridge	189:f392fc9709a3	1462	__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1463	{
AnnaBridge	189:f392fc9709a3	1464	CLEAR_BIT(RCC->APB1RSTR2, Periphs);
AnnaBridge	189:f392fc9709a3	1465	}
AnnaBridge	189:f392fc9709a3	1466
AnnaBridge	189:f392fc9709a3	1467	/**
AnnaBridge	189:f392fc9709a3	1468	* @brief Enable APB1 peripheral clocks in Sleep and Stop modes
AnnaBridge	189:f392fc9709a3	1469	* @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1470	* APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1471	* APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1472	* APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1473	* APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1474	* APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1475	* APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1476	* APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1477	* APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1478	* APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1479	* APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1480	* APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1481	* APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1482	* APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1483	* APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1484	* APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1485	* APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1486	* APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1487	* APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1488	* APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1489	* APB1SMENR1 USBFSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1490	* APB1SMENR1 CAN2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1491	* APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1492	* APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1493	* APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1494	* APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
AnnaBridge	189:f392fc9709a3	1495	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1496	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	189:f392fc9709a3	1497	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	189:f392fc9709a3	1498	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	189:f392fc9709a3	1499	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	189:f392fc9709a3	1500	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	189:f392fc9709a3	1501	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	189:f392fc9709a3	1502	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	189:f392fc9709a3	1503	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	189:f392fc9709a3	1504	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	189:f392fc9709a3	1505	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	189:f392fc9709a3	1506	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	189:f392fc9709a3	1507	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	189:f392fc9709a3	1508	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	189:f392fc9709a3	1509	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	189:f392fc9709a3	1510	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	189:f392fc9709a3	1511	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	189:f392fc9709a3	1512	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	189:f392fc9709a3	1513	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	189:f392fc9709a3	1514	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	189:f392fc9709a3	1515	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	189:f392fc9709a3	1516	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	189:f392fc9709a3	1517	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	189:f392fc9709a3	1518	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	189:f392fc9709a3	1519	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	189:f392fc9709a3	1520	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	189:f392fc9709a3	1521	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	189:f392fc9709a3	1522	*
AnnaBridge	189:f392fc9709a3	1523	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1524	* @retval None
AnnaBridge	189:f392fc9709a3	1525	*/
AnnaBridge	189:f392fc9709a3	1526	__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1527	{
AnnaBridge	189:f392fc9709a3	1528	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	1529	SET_BIT(RCC->APB1SMENR1, Periphs);
AnnaBridge	189:f392fc9709a3	1530	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	189:f392fc9709a3	1531	tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
AnnaBridge	189:f392fc9709a3	1532	(void)tmpreg;
AnnaBridge	189:f392fc9709a3	1533	}
AnnaBridge	189:f392fc9709a3	1534
AnnaBridge	189:f392fc9709a3	1535	/**
AnnaBridge	189:f392fc9709a3	1536	* @brief Enable APB1 peripheral clocks in Sleep and Stop modes
AnnaBridge	189:f392fc9709a3	1537	* @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1538	* APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1539	* APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1540	* APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep
AnnaBridge	189:f392fc9709a3	1541	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1542	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	189:f392fc9709a3	1543	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	189:f392fc9709a3	1544	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	189:f392fc9709a3	1545	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	189:f392fc9709a3	1546	*
AnnaBridge	189:f392fc9709a3	1547	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1548	* @retval None
AnnaBridge	189:f392fc9709a3	1549	*/
AnnaBridge	189:f392fc9709a3	1550	__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1551	{
AnnaBridge	189:f392fc9709a3	1552	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	1553	SET_BIT(RCC->APB1SMENR2, Periphs);
AnnaBridge	189:f392fc9709a3	1554	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	189:f392fc9709a3	1555	tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
AnnaBridge	189:f392fc9709a3	1556	(void)tmpreg;
AnnaBridge	189:f392fc9709a3	1557	}
AnnaBridge	189:f392fc9709a3	1558
AnnaBridge	189:f392fc9709a3	1559	/**
AnnaBridge	189:f392fc9709a3	1560	* @brief Disable APB1 peripheral clocks in Sleep and Stop modes
AnnaBridge	189:f392fc9709a3	1561	* @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1562	* APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1563	* APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1564	* APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1565	* APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1566	* APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1567	* APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1568	* APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1569	* APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1570	* APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1571	* APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1572	* APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1573	* APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1574	* APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1575	* APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1576	* APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1577	* APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1578	* APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1579	* APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1580	* APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1581	* APB1SMENR1 USBFSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1582	* APB1SMENR1 CAN2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1583	* APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1584	* APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1585	* APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1586	* APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
AnnaBridge	189:f392fc9709a3	1587	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1588	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	189:f392fc9709a3	1589	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	189:f392fc9709a3	1590	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	189:f392fc9709a3	1591	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	189:f392fc9709a3	1592	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	189:f392fc9709a3	1593	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	189:f392fc9709a3	1594	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	189:f392fc9709a3	1595	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	189:f392fc9709a3	1596	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	189:f392fc9709a3	1597	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	189:f392fc9709a3	1598	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	189:f392fc9709a3	1599	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	189:f392fc9709a3	1600	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	189:f392fc9709a3	1601	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	189:f392fc9709a3	1602	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	189:f392fc9709a3	1603	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	189:f392fc9709a3	1604	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	189:f392fc9709a3	1605	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	189:f392fc9709a3	1606	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	189:f392fc9709a3	1607	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	189:f392fc9709a3	1608	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	189:f392fc9709a3	1609	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	189:f392fc9709a3	1610	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	189:f392fc9709a3	1611	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	189:f392fc9709a3	1612	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	189:f392fc9709a3	1613	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	189:f392fc9709a3	1614	*
AnnaBridge	189:f392fc9709a3	1615	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1616	* @retval None
AnnaBridge	189:f392fc9709a3	1617	*/
AnnaBridge	189:f392fc9709a3	1618	__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1619	{
AnnaBridge	189:f392fc9709a3	1620	CLEAR_BIT(RCC->APB1SMENR1, Periphs);
AnnaBridge	189:f392fc9709a3	1621	}
AnnaBridge	189:f392fc9709a3	1622
AnnaBridge	189:f392fc9709a3	1623	/**
AnnaBridge	189:f392fc9709a3	1624	* @brief Disable APB1 peripheral clocks in Sleep and Stop modes
AnnaBridge	189:f392fc9709a3	1625	* @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1626	* APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1627	* APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1628	* APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep
AnnaBridge	189:f392fc9709a3	1629	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1630	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	189:f392fc9709a3	1631	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	189:f392fc9709a3	1632	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	189:f392fc9709a3	1633	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	189:f392fc9709a3	1634	*
AnnaBridge	189:f392fc9709a3	1635	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1636	* @retval None
AnnaBridge	189:f392fc9709a3	1637	*/
AnnaBridge	189:f392fc9709a3	1638	__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1639	{
AnnaBridge	189:f392fc9709a3	1640	CLEAR_BIT(RCC->APB1SMENR2, Periphs);
AnnaBridge	189:f392fc9709a3	1641	}
AnnaBridge	189:f392fc9709a3	1642
AnnaBridge	189:f392fc9709a3	1643	/**
AnnaBridge	189:f392fc9709a3	1644	* @}
AnnaBridge	189:f392fc9709a3	1645	*/
AnnaBridge	189:f392fc9709a3	1646
AnnaBridge	189:f392fc9709a3	1647	/** @defgroup BUS_LL_EF_APB2 APB2
AnnaBridge	189:f392fc9709a3	1648	* @{
AnnaBridge	189:f392fc9709a3	1649	*/
AnnaBridge	189:f392fc9709a3	1650
AnnaBridge	189:f392fc9709a3	1651	/**
AnnaBridge	189:f392fc9709a3	1652	* @brief Enable APB2 peripherals clock.
AnnaBridge	189:f392fc9709a3	1653	* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1654	* APB2ENR FWEN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1655	* APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1656	* APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1657	* APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1658	* APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1659	* APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1660	* APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1661	* APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1662	* APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1663	* APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1664	* APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1665	* APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1666	* APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
AnnaBridge	189:f392fc9709a3	1667	* APB2ENR DSIEN LL_APB2_GRP1_EnableClock
AnnaBridge	189:f392fc9709a3	1668	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1669	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	189:f392fc9709a3	1670	* @arg @ref LL_APB2_GRP1_PERIPH_FW
AnnaBridge	189:f392fc9709a3	1671	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	1672	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	189:f392fc9709a3	1673	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	189:f392fc9709a3	1674	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	189:f392fc9709a3	1675	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	189:f392fc9709a3	1676	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	189:f392fc9709a3	1677	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	189:f392fc9709a3	1678	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	189:f392fc9709a3	1679	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	189:f392fc9709a3	1680	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	189:f392fc9709a3	1681	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	189:f392fc9709a3	1682	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	189:f392fc9709a3	1683	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	189:f392fc9709a3	1684	*
AnnaBridge	189:f392fc9709a3	1685	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1686	* @retval None
AnnaBridge	189:f392fc9709a3	1687	*/
AnnaBridge	189:f392fc9709a3	1688	__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1689	{
AnnaBridge	189:f392fc9709a3	1690	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	1691	SET_BIT(RCC->APB2ENR, Periphs);
AnnaBridge	189:f392fc9709a3	1692	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	189:f392fc9709a3	1693	tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
AnnaBridge	189:f392fc9709a3	1694	(void)tmpreg;
AnnaBridge	189:f392fc9709a3	1695	}
AnnaBridge	189:f392fc9709a3	1696
AnnaBridge	189:f392fc9709a3	1697	/**
AnnaBridge	189:f392fc9709a3	1698	* @brief Check if APB2 peripheral clock is enabled or not
AnnaBridge	189:f392fc9709a3	1699	* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1700	* APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1701	* APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1702	* APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1703	* APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1704	* APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1705	* APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1706	* APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1707	* APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1708	* APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1709	* APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1710	* APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1711	* APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1712	* APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	189:f392fc9709a3	1713	* APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock
AnnaBridge	189:f392fc9709a3	1714	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1715	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	189:f392fc9709a3	1716	* @arg @ref LL_APB2_GRP1_PERIPH_FW
AnnaBridge	189:f392fc9709a3	1717	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	1718	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	189:f392fc9709a3	1719	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	189:f392fc9709a3	1720	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	189:f392fc9709a3	1721	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	189:f392fc9709a3	1722	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	189:f392fc9709a3	1723	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	189:f392fc9709a3	1724	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	189:f392fc9709a3	1725	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	189:f392fc9709a3	1726	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	189:f392fc9709a3	1727	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	189:f392fc9709a3	1728	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	189:f392fc9709a3	1729	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	189:f392fc9709a3	1730	*
AnnaBridge	189:f392fc9709a3	1731	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1732	* @retval State of Periphs (1 or 0).
AnnaBridge	189:f392fc9709a3	1733	*/
AnnaBridge	189:f392fc9709a3	1734	__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1735	{
AnnaBridge	189:f392fc9709a3	1736	return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
AnnaBridge	189:f392fc9709a3	1737	}
AnnaBridge	189:f392fc9709a3	1738
AnnaBridge	189:f392fc9709a3	1739	/**
AnnaBridge	189:f392fc9709a3	1740	* @brief Disable APB2 peripherals clock.
AnnaBridge	189:f392fc9709a3	1741	* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1742	* APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1743	* APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1744	* APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1745	* APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1746	* APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1747	* APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1748	* APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1749	* APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1750	* APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1751	* APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1752	* APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1753	* APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
AnnaBridge	189:f392fc9709a3	1754	* APB2ENR DSIEN LL_APB2_GRP1_DisableClock
AnnaBridge	189:f392fc9709a3	1755	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1756	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	189:f392fc9709a3	1757	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	1758	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	189:f392fc9709a3	1759	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	189:f392fc9709a3	1760	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	189:f392fc9709a3	1761	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	189:f392fc9709a3	1762	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	189:f392fc9709a3	1763	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	189:f392fc9709a3	1764	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	189:f392fc9709a3	1765	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	189:f392fc9709a3	1766	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	189:f392fc9709a3	1767	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	189:f392fc9709a3	1768	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	189:f392fc9709a3	1769	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	189:f392fc9709a3	1770	*
AnnaBridge	189:f392fc9709a3	1771	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1772	* @retval None
AnnaBridge	189:f392fc9709a3	1773	*/
AnnaBridge	189:f392fc9709a3	1774	__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1775	{
AnnaBridge	189:f392fc9709a3	1776	CLEAR_BIT(RCC->APB2ENR, Periphs);
AnnaBridge	189:f392fc9709a3	1777	}
AnnaBridge	189:f392fc9709a3	1778
AnnaBridge	189:f392fc9709a3	1779	/**
AnnaBridge	189:f392fc9709a3	1780	* @brief Force APB2 peripherals reset.
AnnaBridge	189:f392fc9709a3	1781	* @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1782	* APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1783	* APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1784	* APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1785	* APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1786	* APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1787	* APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1788	* APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1789	* APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1790	* APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1791	* APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1792	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1793	* APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
AnnaBridge	189:f392fc9709a3	1794	* APB2RSTR DSIRST LL_APB2_GRP1_ForceReset
AnnaBridge	189:f392fc9709a3	1795	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1796	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
AnnaBridge	189:f392fc9709a3	1797	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	189:f392fc9709a3	1798	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	1799	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	189:f392fc9709a3	1800	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	189:f392fc9709a3	1801	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	189:f392fc9709a3	1802	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	189:f392fc9709a3	1803	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	189:f392fc9709a3	1804	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	189:f392fc9709a3	1805	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	189:f392fc9709a3	1806	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	189:f392fc9709a3	1807	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	189:f392fc9709a3	1808	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	189:f392fc9709a3	1809	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	189:f392fc9709a3	1810	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	189:f392fc9709a3	1811	*
AnnaBridge	189:f392fc9709a3	1812	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1813	* @retval None
AnnaBridge	189:f392fc9709a3	1814	*/
AnnaBridge	189:f392fc9709a3	1815	__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1816	{
AnnaBridge	189:f392fc9709a3	1817	SET_BIT(RCC->APB2RSTR, Periphs);
AnnaBridge	189:f392fc9709a3	1818	}
AnnaBridge	189:f392fc9709a3	1819
AnnaBridge	189:f392fc9709a3	1820	/**
AnnaBridge	189:f392fc9709a3	1821	* @brief Release APB2 peripherals reset.
AnnaBridge	189:f392fc9709a3	1822	* @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1823	* APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1824	* APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1825	* APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1826	* APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1827	* APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1828	* APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1829	* APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1830	* APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1831	* APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1832	* APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1833	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1834	* APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	189:f392fc9709a3	1835	* APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset
AnnaBridge	189:f392fc9709a3	1836	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1837	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
AnnaBridge	189:f392fc9709a3	1838	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	189:f392fc9709a3	1839	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	1840	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	189:f392fc9709a3	1841	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	189:f392fc9709a3	1842	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	189:f392fc9709a3	1843	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	189:f392fc9709a3	1844	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	189:f392fc9709a3	1845	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	189:f392fc9709a3	1846	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	189:f392fc9709a3	1847	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	189:f392fc9709a3	1848	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	189:f392fc9709a3	1849	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	189:f392fc9709a3	1850	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	189:f392fc9709a3	1851	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	189:f392fc9709a3	1852	*
AnnaBridge	189:f392fc9709a3	1853	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1854	* @retval None
AnnaBridge	189:f392fc9709a3	1855	*/
AnnaBridge	189:f392fc9709a3	1856	__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1857	{
AnnaBridge	189:f392fc9709a3	1858	CLEAR_BIT(RCC->APB2RSTR, Periphs);
AnnaBridge	189:f392fc9709a3	1859	}
AnnaBridge	189:f392fc9709a3	1860
AnnaBridge	189:f392fc9709a3	1861	/**
AnnaBridge	189:f392fc9709a3	1862	* @brief Enable APB2 peripheral clocks in Sleep and Stop modes
AnnaBridge	189:f392fc9709a3	1863	* @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1864	* APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1865	* APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1866	* APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1867	* APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1868	* APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1869	* APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1870	* APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1871	* APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1872	* APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1873	* APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1874	* APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1875	* APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1876	* APB2SMENR DSISMEN LL_APB2_GRP1_EnableClockStopSleep
AnnaBridge	189:f392fc9709a3	1877	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1878	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	189:f392fc9709a3	1879	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	1880	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	189:f392fc9709a3	1881	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	189:f392fc9709a3	1882	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	189:f392fc9709a3	1883	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	189:f392fc9709a3	1884	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	189:f392fc9709a3	1885	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	189:f392fc9709a3	1886	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	189:f392fc9709a3	1887	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	189:f392fc9709a3	1888	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	189:f392fc9709a3	1889	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	189:f392fc9709a3	1890	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	189:f392fc9709a3	1891	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	189:f392fc9709a3	1892	*
AnnaBridge	189:f392fc9709a3	1893	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1894	* @retval None
AnnaBridge	189:f392fc9709a3	1895	*/
AnnaBridge	189:f392fc9709a3	1896	__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1897	{
AnnaBridge	189:f392fc9709a3	1898	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	1899	SET_BIT(RCC->APB2SMENR, Periphs);
AnnaBridge	189:f392fc9709a3	1900	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	189:f392fc9709a3	1901	tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
AnnaBridge	189:f392fc9709a3	1902	(void)tmpreg;
AnnaBridge	189:f392fc9709a3	1903	}
AnnaBridge	189:f392fc9709a3	1904
AnnaBridge	189:f392fc9709a3	1905	/**
AnnaBridge	189:f392fc9709a3	1906	* @brief Disable APB2 peripheral clocks in Sleep and Stop modes
AnnaBridge	189:f392fc9709a3	1907	* @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1908	* APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1909	* APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1910	* APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1911	* APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1912	* APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1913	* APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1914	* APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1915	* APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1916	* APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1917	* APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1918	* APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1919	* APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	189:f392fc9709a3	1920	* APB2SMENR DSISMEN LL_APB2_GRP1_DisableClockStopSleep
AnnaBridge	189:f392fc9709a3	1921	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	189:f392fc9709a3	1922	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	189:f392fc9709a3	1923	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	189:f392fc9709a3	1924	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	189:f392fc9709a3	1925	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	189:f392fc9709a3	1926	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	189:f392fc9709a3	1927	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	189:f392fc9709a3	1928	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	189:f392fc9709a3	1929	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	189:f392fc9709a3	1930	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	189:f392fc9709a3	1931	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	189:f392fc9709a3	1932	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	189:f392fc9709a3	1933	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	189:f392fc9709a3	1934	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	189:f392fc9709a3	1935	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	189:f392fc9709a3	1936	*
AnnaBridge	189:f392fc9709a3	1937	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1938	* @retval None
AnnaBridge	189:f392fc9709a3	1939	*/
AnnaBridge	189:f392fc9709a3	1940	__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
AnnaBridge	189:f392fc9709a3	1941	{
AnnaBridge	189:f392fc9709a3	1942	CLEAR_BIT(RCC->APB2SMENR, Periphs);
AnnaBridge	189:f392fc9709a3	1943	}
AnnaBridge	189:f392fc9709a3	1944
AnnaBridge	189:f392fc9709a3	1945	/**
AnnaBridge	189:f392fc9709a3	1946	* @}
AnnaBridge	189:f392fc9709a3	1947	*/
AnnaBridge	189:f392fc9709a3	1948
AnnaBridge	189:f392fc9709a3	1949
AnnaBridge	189:f392fc9709a3	1950	/**
AnnaBridge	189:f392fc9709a3	1951	* @}
AnnaBridge	189:f392fc9709a3	1952	*/
AnnaBridge	189:f392fc9709a3	1953
AnnaBridge	189:f392fc9709a3	1954	/**
AnnaBridge	189:f392fc9709a3	1955	* @}
AnnaBridge	189:f392fc9709a3	1956	*/
AnnaBridge	189:f392fc9709a3	1957
AnnaBridge	189:f392fc9709a3	1958	#endif /* defined(RCC) */
AnnaBridge	189:f392fc9709a3	1959
AnnaBridge	189:f392fc9709a3	1960	/**
AnnaBridge	189:f392fc9709a3	1961	* @}
AnnaBridge	189:f392fc9709a3	1962	*/
AnnaBridge	189:f392fc9709a3	1963
AnnaBridge	189:f392fc9709a3	1964	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	1965	}
AnnaBridge	189:f392fc9709a3	1966	#endif
AnnaBridge	189:f392fc9709a3	1967
AnnaBridge	189:f392fc9709a3	1968	#endif /* __STM32L4xx_LL_BUS_H */
AnnaBridge	189:f392fc9709a3	1969
AnnaBridge	189:f392fc9709a3	1970	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/