mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_hal_tim.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l4xx_hal_tim.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of TIM HAL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L4xx_HAL_TIM_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L4xx_HAL_TIM_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	45	#include "stm32l4xx_hal_def.h"
AnnaBridge	189:f392fc9709a3	46
AnnaBridge	189:f392fc9709a3	47	/** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge	189:f392fc9709a3	48	* @{
AnnaBridge	189:f392fc9709a3	49	*/
AnnaBridge	189:f392fc9709a3	50
AnnaBridge	189:f392fc9709a3	51	/** @addtogroup TIM
AnnaBridge	189:f392fc9709a3	52	* @{
AnnaBridge	189:f392fc9709a3	53	*/
AnnaBridge	189:f392fc9709a3	54
AnnaBridge	189:f392fc9709a3	55	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	56	/** @defgroup TIM_Exported_Types TIM Exported Types
AnnaBridge	189:f392fc9709a3	57	* @{
AnnaBridge	189:f392fc9709a3	58	*/
AnnaBridge	189:f392fc9709a3	59
AnnaBridge	189:f392fc9709a3	60	/**
AnnaBridge	189:f392fc9709a3	61	* @brief TIM Time base Configuration Structure definition
AnnaBridge	189:f392fc9709a3	62	*/
AnnaBridge	189:f392fc9709a3	63	typedef struct
AnnaBridge	189:f392fc9709a3	64	{
AnnaBridge	189:f392fc9709a3	65	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge	189:f392fc9709a3	66	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge	189:f392fc9709a3	67
AnnaBridge	189:f392fc9709a3	68	uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge	189:f392fc9709a3	69	This parameter can be a value of @ref TIM_Counter_Mode */
AnnaBridge	189:f392fc9709a3	70
AnnaBridge	189:f392fc9709a3	71	uint32_t Period; /*!< Specifies the period value to be loaded into the active
AnnaBridge	189:f392fc9709a3	72	Auto-Reload Register at the next update event.
AnnaBridge	189:f392fc9709a3	73	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
AnnaBridge	189:f392fc9709a3	74
AnnaBridge	189:f392fc9709a3	75	uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge	189:f392fc9709a3	76	This parameter can be a value of @ref TIM_ClockDivision */
AnnaBridge	189:f392fc9709a3	77
AnnaBridge	189:f392fc9709a3	78	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
AnnaBridge	189:f392fc9709a3	79	reaches zero, an update event is generated and counting restarts
AnnaBridge	189:f392fc9709a3	80	from the RCR value (N).
AnnaBridge	189:f392fc9709a3	81	This means in PWM mode that (N+1) corresponds to:
AnnaBridge	189:f392fc9709a3	82	- the number of PWM periods in edge-aligned mode
AnnaBridge	189:f392fc9709a3	83	- the number of half PWM period in center-aligned mode
AnnaBridge	189:f392fc9709a3	84	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
AnnaBridge	189:f392fc9709a3	85	@note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge	189:f392fc9709a3	86
AnnaBridge	189:f392fc9709a3	87	uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
AnnaBridge	189:f392fc9709a3	88	This parameter can be a value of @ref TIM_AutoReloadPreload */
AnnaBridge	189:f392fc9709a3	89	} TIM_Base_InitTypeDef;
AnnaBridge	189:f392fc9709a3	90
AnnaBridge	189:f392fc9709a3	91	/**
AnnaBridge	189:f392fc9709a3	92	* @brief TIM Output Compare Configuration Structure definition
AnnaBridge	189:f392fc9709a3	93	*/
AnnaBridge	189:f392fc9709a3	94	typedef struct
AnnaBridge	189:f392fc9709a3	95	{
AnnaBridge	189:f392fc9709a3	96	uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge	189:f392fc9709a3	97	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge	189:f392fc9709a3	98
AnnaBridge	189:f392fc9709a3	99	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge	189:f392fc9709a3	100	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge	189:f392fc9709a3	101
AnnaBridge	189:f392fc9709a3	102	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	189:f392fc9709a3	103	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge	189:f392fc9709a3	104
AnnaBridge	189:f392fc9709a3	105	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge	189:f392fc9709a3	106	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
AnnaBridge	189:f392fc9709a3	107	@note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge	189:f392fc9709a3	108
AnnaBridge	189:f392fc9709a3	109	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
AnnaBridge	189:f392fc9709a3	110	This parameter can be a value of @ref TIM_Output_Fast_State
AnnaBridge	189:f392fc9709a3	111	@note This parameter is valid only in PWM1 and PWM2 mode. */
AnnaBridge	189:f392fc9709a3	112
AnnaBridge	189:f392fc9709a3	113
AnnaBridge	189:f392fc9709a3	114	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	189:f392fc9709a3	115	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
AnnaBridge	189:f392fc9709a3	116	@note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge	189:f392fc9709a3	117
AnnaBridge	189:f392fc9709a3	118	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	189:f392fc9709a3	119	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
AnnaBridge	189:f392fc9709a3	120	@note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge	189:f392fc9709a3	121	} TIM_OC_InitTypeDef;
AnnaBridge	189:f392fc9709a3	122
AnnaBridge	189:f392fc9709a3	123	/**
AnnaBridge	189:f392fc9709a3	124	* @brief TIM One Pulse Mode Configuration Structure definition
AnnaBridge	189:f392fc9709a3	125	*/
AnnaBridge	189:f392fc9709a3	126	typedef struct
AnnaBridge	189:f392fc9709a3	127	{
AnnaBridge	189:f392fc9709a3	128	uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge	189:f392fc9709a3	129	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge	189:f392fc9709a3	130
AnnaBridge	189:f392fc9709a3	131	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge	189:f392fc9709a3	132	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge	189:f392fc9709a3	133
AnnaBridge	189:f392fc9709a3	134	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	189:f392fc9709a3	135	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge	189:f392fc9709a3	136
AnnaBridge	189:f392fc9709a3	137	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge	189:f392fc9709a3	138	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
AnnaBridge	189:f392fc9709a3	139	@note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge	189:f392fc9709a3	140
AnnaBridge	189:f392fc9709a3	141	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	189:f392fc9709a3	142	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
AnnaBridge	189:f392fc9709a3	143	@note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge	189:f392fc9709a3	144
AnnaBridge	189:f392fc9709a3	145	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	189:f392fc9709a3	146	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
AnnaBridge	189:f392fc9709a3	147	@note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge	189:f392fc9709a3	148
AnnaBridge	189:f392fc9709a3	149	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	189:f392fc9709a3	150	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge	189:f392fc9709a3	151
AnnaBridge	189:f392fc9709a3	152	uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge	189:f392fc9709a3	153	This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge	189:f392fc9709a3	154
AnnaBridge	189:f392fc9709a3	155	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	189:f392fc9709a3	156	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	157	} TIM_OnePulse_InitTypeDef;
AnnaBridge	189:f392fc9709a3	158
AnnaBridge	189:f392fc9709a3	159
AnnaBridge	189:f392fc9709a3	160	/**
AnnaBridge	189:f392fc9709a3	161	* @brief TIM Input Capture Configuration Structure definition
AnnaBridge	189:f392fc9709a3	162	*/
AnnaBridge	189:f392fc9709a3	163	typedef struct
AnnaBridge	189:f392fc9709a3	164	{
AnnaBridge	189:f392fc9709a3	165	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	189:f392fc9709a3	166	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge	189:f392fc9709a3	167
AnnaBridge	189:f392fc9709a3	168	uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge	189:f392fc9709a3	169	This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge	189:f392fc9709a3	170
AnnaBridge	189:f392fc9709a3	171	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	189:f392fc9709a3	172	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge	189:f392fc9709a3	173
AnnaBridge	189:f392fc9709a3	174	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	189:f392fc9709a3	175	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	176	} TIM_IC_InitTypeDef;
AnnaBridge	189:f392fc9709a3	177
AnnaBridge	189:f392fc9709a3	178	/**
AnnaBridge	189:f392fc9709a3	179	* @brief TIM Encoder Configuration Structure definition
AnnaBridge	189:f392fc9709a3	180	*/
AnnaBridge	189:f392fc9709a3	181	typedef struct
AnnaBridge	189:f392fc9709a3	182	{
AnnaBridge	189:f392fc9709a3	183	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
AnnaBridge	189:f392fc9709a3	184	This parameter can be a value of @ref TIM_Encoder_Mode */
AnnaBridge	189:f392fc9709a3	185
AnnaBridge	189:f392fc9709a3	186	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	189:f392fc9709a3	187	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge	189:f392fc9709a3	188
AnnaBridge	189:f392fc9709a3	189	uint32_t IC1Selection; /*!< Specifies the input.
AnnaBridge	189:f392fc9709a3	190	This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge	189:f392fc9709a3	191
AnnaBridge	189:f392fc9709a3	192	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	189:f392fc9709a3	193	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge	189:f392fc9709a3	194
AnnaBridge	189:f392fc9709a3	195	uint32_t IC1Filter; /*!< Specifies the input capture filter.
AnnaBridge	189:f392fc9709a3	196	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	197
AnnaBridge	189:f392fc9709a3	198	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	189:f392fc9709a3	199	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge	189:f392fc9709a3	200
AnnaBridge	189:f392fc9709a3	201	uint32_t IC2Selection; /*!< Specifies the input.
AnnaBridge	189:f392fc9709a3	202	This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge	189:f392fc9709a3	203
AnnaBridge	189:f392fc9709a3	204	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	189:f392fc9709a3	205	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge	189:f392fc9709a3	206
AnnaBridge	189:f392fc9709a3	207	uint32_t IC2Filter; /*!< Specifies the input capture filter.
AnnaBridge	189:f392fc9709a3	208	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	209	} TIM_Encoder_InitTypeDef;
AnnaBridge	189:f392fc9709a3	210
AnnaBridge	189:f392fc9709a3	211
AnnaBridge	189:f392fc9709a3	212	/**
AnnaBridge	189:f392fc9709a3	213	* @brief Clock Configuration Handle Structure definition
AnnaBridge	189:f392fc9709a3	214	*/
AnnaBridge	189:f392fc9709a3	215	typedef struct
AnnaBridge	189:f392fc9709a3	216	{
AnnaBridge	189:f392fc9709a3	217	uint32_t ClockSource; /*!< TIM clock sources
AnnaBridge	189:f392fc9709a3	218	This parameter can be a value of @ref TIM_Clock_Source */
AnnaBridge	189:f392fc9709a3	219	uint32_t ClockPolarity; /*!< TIM clock polarity
AnnaBridge	189:f392fc9709a3	220	This parameter can be a value of @ref TIM_Clock_Polarity */
AnnaBridge	189:f392fc9709a3	221	uint32_t ClockPrescaler; /*!< TIM clock prescaler
AnnaBridge	189:f392fc9709a3	222	This parameter can be a value of @ref TIM_Clock_Prescaler */
AnnaBridge	189:f392fc9709a3	223	uint32_t ClockFilter; /*!< TIM clock filter
AnnaBridge	189:f392fc9709a3	224	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	225	}TIM_ClockConfigTypeDef;
AnnaBridge	189:f392fc9709a3	226
AnnaBridge	189:f392fc9709a3	227	/**
AnnaBridge	189:f392fc9709a3	228	* @brief Clear Input Configuration Handle Structure definition
AnnaBridge	189:f392fc9709a3	229	*/
AnnaBridge	189:f392fc9709a3	230	typedef struct
AnnaBridge	189:f392fc9709a3	231	{
AnnaBridge	189:f392fc9709a3	232	uint32_t ClearInputState; /*!< TIM clear Input state
AnnaBridge	189:f392fc9709a3	233	This parameter can be ENABLE or DISABLE */
AnnaBridge	189:f392fc9709a3	234	uint32_t ClearInputSource; /*!< TIM clear Input sources
AnnaBridge	189:f392fc9709a3	235	This parameter can be a value of @ref TIM_ClearInput_Source */
AnnaBridge	189:f392fc9709a3	236	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
AnnaBridge	189:f392fc9709a3	237	This parameter can be a value of @ref TIM_ClearInput_Polarity */
AnnaBridge	189:f392fc9709a3	238	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
AnnaBridge	189:f392fc9709a3	239	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
AnnaBridge	189:f392fc9709a3	240	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
AnnaBridge	189:f392fc9709a3	241	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	242	}TIM_ClearInputConfigTypeDef;
AnnaBridge	189:f392fc9709a3	243
AnnaBridge	189:f392fc9709a3	244	/**
AnnaBridge	189:f392fc9709a3	245	* @brief TIM Master configuration Structure definition
AnnaBridge	189:f392fc9709a3	246	* @note Advanced timers provide TRGO2 internal line which is redirected
AnnaBridge	189:f392fc9709a3	247	* to the ADC
AnnaBridge	189:f392fc9709a3	248	*/
AnnaBridge	189:f392fc9709a3	249	typedef struct {
AnnaBridge	189:f392fc9709a3	250	uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
AnnaBridge	189:f392fc9709a3	251	This parameter can be a value of @ref TIM_Master_Mode_Selection */
AnnaBridge	189:f392fc9709a3	252	uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
AnnaBridge	189:f392fc9709a3	253	This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
AnnaBridge	189:f392fc9709a3	254	uint32_t MasterSlaveMode; /*!< Master/slave mode selection
AnnaBridge	189:f392fc9709a3	255	This parameter can be a value of @ref TIM_Master_Slave_Mode */
AnnaBridge	189:f392fc9709a3	256	}TIM_MasterConfigTypeDef;
AnnaBridge	189:f392fc9709a3	257
AnnaBridge	189:f392fc9709a3	258	/**
AnnaBridge	189:f392fc9709a3	259	* @brief TIM Slave configuration Structure definition
AnnaBridge	189:f392fc9709a3	260	*/
AnnaBridge	189:f392fc9709a3	261	typedef struct {
AnnaBridge	189:f392fc9709a3	262	uint32_t SlaveMode; /*!< Slave mode selection
AnnaBridge	189:f392fc9709a3	263	This parameter can be a value of @ref TIM_Slave_Mode */
AnnaBridge	189:f392fc9709a3	264	uint32_t InputTrigger; /*!< Input Trigger source
AnnaBridge	189:f392fc9709a3	265	This parameter can be a value of @ref TIM_Trigger_Selection */
AnnaBridge	189:f392fc9709a3	266	uint32_t TriggerPolarity; /*!< Input Trigger polarity
AnnaBridge	189:f392fc9709a3	267	This parameter can be a value of @ref TIM_Trigger_Polarity */
AnnaBridge	189:f392fc9709a3	268	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
AnnaBridge	189:f392fc9709a3	269	This parameter can be a value of @ref TIM_Trigger_Prescaler */
AnnaBridge	189:f392fc9709a3	270	uint32_t TriggerFilter; /*!< Input trigger filter
AnnaBridge	189:f392fc9709a3	271	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	272
AnnaBridge	189:f392fc9709a3	273	}TIM_SlaveConfigTypeDef;
AnnaBridge	189:f392fc9709a3	274
AnnaBridge	189:f392fc9709a3	275	/**
AnnaBridge	189:f392fc9709a3	276	* @brief TIM Break input(s) and Dead time configuration Structure definition
AnnaBridge	189:f392fc9709a3	277	* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
AnnaBridge	189:f392fc9709a3	278	* filter and polarity.
AnnaBridge	189:f392fc9709a3	279	*/
AnnaBridge	189:f392fc9709a3	280	typedef struct
AnnaBridge	189:f392fc9709a3	281	{
AnnaBridge	189:f392fc9709a3	282	uint32_t OffStateRunMode; /*!< TIM off state in run mode
AnnaBridge	189:f392fc9709a3	283	This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
AnnaBridge	189:f392fc9709a3	284	uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
AnnaBridge	189:f392fc9709a3	285	This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
AnnaBridge	189:f392fc9709a3	286	uint32_t LockLevel; /*!< TIM Lock level
AnnaBridge	189:f392fc9709a3	287	This parameter can be a value of @ref TIM_Lock_level */
AnnaBridge	189:f392fc9709a3	288	uint32_t DeadTime; /*!< TIM dead Time
AnnaBridge	189:f392fc9709a3	289	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
AnnaBridge	189:f392fc9709a3	290	uint32_t BreakState; /*!< TIM Break State
AnnaBridge	189:f392fc9709a3	291	This parameter can be a value of @ref TIM_Break_Input_enable_disable */
AnnaBridge	189:f392fc9709a3	292	uint32_t BreakPolarity; /*!< TIM Break input polarity
AnnaBridge	189:f392fc9709a3	293	This parameter can be a value of @ref TIM_Break_Polarity */
AnnaBridge	189:f392fc9709a3	294	uint32_t BreakFilter; /*!< Specifies the break input filter.
AnnaBridge	189:f392fc9709a3	295	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	296	uint32_t Break2State; /*!< TIM Break2 State
AnnaBridge	189:f392fc9709a3	297	This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
AnnaBridge	189:f392fc9709a3	298	uint32_t Break2Polarity; /*!< TIM Break2 input polarity
AnnaBridge	189:f392fc9709a3	299	This parameter can be a value of @ref TIM_Break2_Polarity */
AnnaBridge	189:f392fc9709a3	300	uint32_t Break2Filter; /*!< TIM break2 input filter.
AnnaBridge	189:f392fc9709a3	301	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	302	uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
AnnaBridge	189:f392fc9709a3	303	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
AnnaBridge	189:f392fc9709a3	304	} TIM_BreakDeadTimeConfigTypeDef;
AnnaBridge	189:f392fc9709a3	305
AnnaBridge	189:f392fc9709a3	306	/**
AnnaBridge	189:f392fc9709a3	307	* @brief HAL State structures definition
AnnaBridge	189:f392fc9709a3	308	*/
AnnaBridge	189:f392fc9709a3	309	typedef enum
AnnaBridge	189:f392fc9709a3	310	{
AnnaBridge	189:f392fc9709a3	311	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
AnnaBridge	189:f392fc9709a3	312	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
AnnaBridge	189:f392fc9709a3	313	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
AnnaBridge	189:f392fc9709a3	314	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
AnnaBridge	189:f392fc9709a3	315	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
AnnaBridge	189:f392fc9709a3	316	}HAL_TIM_StateTypeDef;
AnnaBridge	189:f392fc9709a3	317
AnnaBridge	189:f392fc9709a3	318	/**
AnnaBridge	189:f392fc9709a3	319	* @brief HAL Active channel structures definition
AnnaBridge	189:f392fc9709a3	320	*/
AnnaBridge	189:f392fc9709a3	321	typedef enum
AnnaBridge	189:f392fc9709a3	322	{
AnnaBridge	189:f392fc9709a3	323	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
AnnaBridge	189:f392fc9709a3	324	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
AnnaBridge	189:f392fc9709a3	325	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
AnnaBridge	189:f392fc9709a3	326	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
AnnaBridge	189:f392fc9709a3	327	HAL_TIM_ACTIVE_CHANNEL_5 = 0x10, /!< The active channel is 5 /
AnnaBridge	189:f392fc9709a3	328	HAL_TIM_ACTIVE_CHANNEL_6 = 0x20, /!< The active channel is 6 /
AnnaBridge	189:f392fc9709a3	329	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
AnnaBridge	189:f392fc9709a3	330	}HAL_TIM_ActiveChannel;
AnnaBridge	189:f392fc9709a3	331
AnnaBridge	189:f392fc9709a3	332	/**
AnnaBridge	189:f392fc9709a3	333	* @brief TIM Time Base Handle Structure definition
AnnaBridge	189:f392fc9709a3	334	*/
AnnaBridge	189:f392fc9709a3	335	typedef struct
AnnaBridge	189:f392fc9709a3	336	{
AnnaBridge	189:f392fc9709a3	337	TIM_TypeDef Instance; /!< Register base address */
AnnaBridge	189:f392fc9709a3	338	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
AnnaBridge	189:f392fc9709a3	339	HAL_TIM_ActiveChannel Channel; /!< Active channel /
AnnaBridge	189:f392fc9709a3	340	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
AnnaBridge	189:f392fc9709a3	341	This array is accessed by a @ref DMA_Handle_index */
AnnaBridge	189:f392fc9709a3	342	HAL_LockTypeDef Lock; /!< Locking object /
AnnaBridge	189:f392fc9709a3	343	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
AnnaBridge	189:f392fc9709a3	344	}TIM_HandleTypeDef;
AnnaBridge	189:f392fc9709a3	345
AnnaBridge	189:f392fc9709a3	346	/**
AnnaBridge	189:f392fc9709a3	347	* @}
AnnaBridge	189:f392fc9709a3	348	*/
AnnaBridge	189:f392fc9709a3	349	/* End of exported types -----------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	350
AnnaBridge	189:f392fc9709a3	351	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	352	/** @defgroup TIM_Exported_Constants TIM Exported Constants
AnnaBridge	189:f392fc9709a3	353	* @{
AnnaBridge	189:f392fc9709a3	354	*/
AnnaBridge	189:f392fc9709a3	355
AnnaBridge	189:f392fc9709a3	356	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
AnnaBridge	189:f392fc9709a3	357	* @{
AnnaBridge	189:f392fc9709a3	358	*/
AnnaBridge	189:f392fc9709a3	359	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
AnnaBridge	189:f392fc9709a3	360	#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
AnnaBridge	189:f392fc9709a3	361	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	362	/**
AnnaBridge	189:f392fc9709a3	363	* @}
AnnaBridge	189:f392fc9709a3	364	*/
AnnaBridge	189:f392fc9709a3	365
AnnaBridge	189:f392fc9709a3	366	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
AnnaBridge	189:f392fc9709a3	367	* @{
AnnaBridge	189:f392fc9709a3	368	*/
AnnaBridge	189:f392fc9709a3	369	#define TIM_DMABASE_CR1 (0x00000000)
AnnaBridge	189:f392fc9709a3	370	#define TIM_DMABASE_CR2 (0x00000001)
AnnaBridge	189:f392fc9709a3	371	#define TIM_DMABASE_SMCR (0x00000002)
AnnaBridge	189:f392fc9709a3	372	#define TIM_DMABASE_DIER (0x00000003)
AnnaBridge	189:f392fc9709a3	373	#define TIM_DMABASE_SR (0x00000004)
AnnaBridge	189:f392fc9709a3	374	#define TIM_DMABASE_EGR (0x00000005)
AnnaBridge	189:f392fc9709a3	375	#define TIM_DMABASE_CCMR1 (0x00000006)
AnnaBridge	189:f392fc9709a3	376	#define TIM_DMABASE_CCMR2 (0x00000007)
AnnaBridge	189:f392fc9709a3	377	#define TIM_DMABASE_CCER (0x00000008)
AnnaBridge	189:f392fc9709a3	378	#define TIM_DMABASE_CNT (0x00000009)
AnnaBridge	189:f392fc9709a3	379	#define TIM_DMABASE_PSC (0x0000000A)
AnnaBridge	189:f392fc9709a3	380	#define TIM_DMABASE_ARR (0x0000000B)
AnnaBridge	189:f392fc9709a3	381	#define TIM_DMABASE_RCR (0x0000000C)
AnnaBridge	189:f392fc9709a3	382	#define TIM_DMABASE_CCR1 (0x0000000D)
AnnaBridge	189:f392fc9709a3	383	#define TIM_DMABASE_CCR2 (0x0000000E)
AnnaBridge	189:f392fc9709a3	384	#define TIM_DMABASE_CCR3 (0x0000000F)
AnnaBridge	189:f392fc9709a3	385	#define TIM_DMABASE_CCR4 (0x00000010)
AnnaBridge	189:f392fc9709a3	386	#define TIM_DMABASE_BDTR (0x00000011)
AnnaBridge	189:f392fc9709a3	387	#define TIM_DMABASE_DCR (0x00000012)
AnnaBridge	189:f392fc9709a3	388	#define TIM_DMABASE_DMAR (0x00000013)
AnnaBridge	189:f392fc9709a3	389	#define TIM_DMABASE_OR1 (0x00000014)
AnnaBridge	189:f392fc9709a3	390	#define TIM_DMABASE_CCMR3 (0x00000015)
AnnaBridge	189:f392fc9709a3	391	#define TIM_DMABASE_CCR5 (0x00000016)
AnnaBridge	189:f392fc9709a3	392	#define TIM_DMABASE_CCR6 (0x00000017)
AnnaBridge	189:f392fc9709a3	393	#define TIM_DMABASE_OR2 (0x00000018)
AnnaBridge	189:f392fc9709a3	394	#define TIM_DMABASE_OR3 (0x00000019)
AnnaBridge	189:f392fc9709a3	395	/**
AnnaBridge	189:f392fc9709a3	396	* @}
AnnaBridge	189:f392fc9709a3	397	*/
AnnaBridge	189:f392fc9709a3	398
AnnaBridge	189:f392fc9709a3	399	/** @defgroup TIM_Event_Source TIM Extended Event Source
AnnaBridge	189:f392fc9709a3	400	* @{
AnnaBridge	189:f392fc9709a3	401	*/
AnnaBridge	189:f392fc9709a3	402	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /!< Reinitialize the counter and generates an update of the registers /
AnnaBridge	189:f392fc9709a3	403	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /!< A capture/compare event is generated on channel 1 /
AnnaBridge	189:f392fc9709a3	404	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /!< A capture/compare event is generated on channel 2 /
AnnaBridge	189:f392fc9709a3	405	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /!< A capture/compare event is generated on channel 3 /
AnnaBridge	189:f392fc9709a3	406	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /!< A capture/compare event is generated on channel 4 /
AnnaBridge	189:f392fc9709a3	407	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /!< A commutation event is generated /
AnnaBridge	189:f392fc9709a3	408	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /!< A trigger event is generated /
AnnaBridge	189:f392fc9709a3	409	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /!< A break event is generated /
AnnaBridge	189:f392fc9709a3	410	#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /!< A break 2 event is generated /
AnnaBridge	189:f392fc9709a3	411	/**
AnnaBridge	189:f392fc9709a3	412	* @}
AnnaBridge	189:f392fc9709a3	413	*/
AnnaBridge	189:f392fc9709a3	414
AnnaBridge	189:f392fc9709a3	415	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
AnnaBridge	189:f392fc9709a3	416	* @{
AnnaBridge	189:f392fc9709a3	417	*/
AnnaBridge	189:f392fc9709a3	418	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
AnnaBridge	189:f392fc9709a3	419	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
AnnaBridge	189:f392fc9709a3	420	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
AnnaBridge	189:f392fc9709a3	421	/**
AnnaBridge	189:f392fc9709a3	422	* @}
AnnaBridge	189:f392fc9709a3	423	*/
AnnaBridge	189:f392fc9709a3	424
AnnaBridge	189:f392fc9709a3	425	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
AnnaBridge	189:f392fc9709a3	426	* @{
AnnaBridge	189:f392fc9709a3	427	*/
AnnaBridge	189:f392fc9709a3	428	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
AnnaBridge	189:f392fc9709a3	429	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
AnnaBridge	189:f392fc9709a3	430	/**
AnnaBridge	189:f392fc9709a3	431	* @}
AnnaBridge	189:f392fc9709a3	432	*/
AnnaBridge	189:f392fc9709a3	433
AnnaBridge	189:f392fc9709a3	434	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
AnnaBridge	189:f392fc9709a3	435	* @{
AnnaBridge	189:f392fc9709a3	436	*/
AnnaBridge	189:f392fc9709a3	437	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
AnnaBridge	189:f392fc9709a3	438	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
AnnaBridge	189:f392fc9709a3	439	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
AnnaBridge	189:f392fc9709a3	440	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
AnnaBridge	189:f392fc9709a3	441	/**
AnnaBridge	189:f392fc9709a3	442	* @}
AnnaBridge	189:f392fc9709a3	443	*/
AnnaBridge	189:f392fc9709a3	444
AnnaBridge	189:f392fc9709a3	445	/** @defgroup TIM_Counter_Mode TIM Counter Mode
AnnaBridge	189:f392fc9709a3	446	* @{
AnnaBridge	189:f392fc9709a3	447	*/
AnnaBridge	189:f392fc9709a3	448	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	449	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
AnnaBridge	189:f392fc9709a3	450	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
AnnaBridge	189:f392fc9709a3	451	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
AnnaBridge	189:f392fc9709a3	452	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
AnnaBridge	189:f392fc9709a3	453	/**
AnnaBridge	189:f392fc9709a3	454	* @}
AnnaBridge	189:f392fc9709a3	455	*/
AnnaBridge	189:f392fc9709a3	456
AnnaBridge	189:f392fc9709a3	457	/** @defgroup TIM_ClockDivision TIM Clock Division
AnnaBridge	189:f392fc9709a3	458	* @{
AnnaBridge	189:f392fc9709a3	459	*/
AnnaBridge	189:f392fc9709a3	460	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	461	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
AnnaBridge	189:f392fc9709a3	462	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
AnnaBridge	189:f392fc9709a3	463	/**
AnnaBridge	189:f392fc9709a3	464	* @}
AnnaBridge	189:f392fc9709a3	465	*/
AnnaBridge	189:f392fc9709a3	466
AnnaBridge	189:f392fc9709a3	467	/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
AnnaBridge	189:f392fc9709a3	468	* @{
AnnaBridge	189:f392fc9709a3	469	*/
AnnaBridge	189:f392fc9709a3	470	#define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000) /!< TIMx_ARR register is not buffered /
AnnaBridge	189:f392fc9709a3	471	#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /!< TIMx_ARR register is buffered /
AnnaBridge	189:f392fc9709a3	472	/**
AnnaBridge	189:f392fc9709a3	473	* @}
AnnaBridge	189:f392fc9709a3	474	*/
AnnaBridge	189:f392fc9709a3	475
AnnaBridge	189:f392fc9709a3	476	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
AnnaBridge	189:f392fc9709a3	477	* @{
AnnaBridge	189:f392fc9709a3	478	*/
AnnaBridge	189:f392fc9709a3	479	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	480	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
AnnaBridge	189:f392fc9709a3	481	/**
AnnaBridge	189:f392fc9709a3	482	* @}
AnnaBridge	189:f392fc9709a3	483	*/
AnnaBridge	189:f392fc9709a3	484
AnnaBridge	189:f392fc9709a3	485	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
AnnaBridge	189:f392fc9709a3	486	* @{
AnnaBridge	189:f392fc9709a3	487	*/
AnnaBridge	189:f392fc9709a3	488	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	489	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
AnnaBridge	189:f392fc9709a3	490	/**
AnnaBridge	189:f392fc9709a3	491	* @}
AnnaBridge	189:f392fc9709a3	492	*/
AnnaBridge	189:f392fc9709a3	493
AnnaBridge	189:f392fc9709a3	494	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
AnnaBridge	189:f392fc9709a3	495	* @{
AnnaBridge	189:f392fc9709a3	496	*/
AnnaBridge	189:f392fc9709a3	497	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	498	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
AnnaBridge	189:f392fc9709a3	499	/**
AnnaBridge	189:f392fc9709a3	500	* @}
AnnaBridge	189:f392fc9709a3	501	*/
AnnaBridge	189:f392fc9709a3	502
AnnaBridge	189:f392fc9709a3	503	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
AnnaBridge	189:f392fc9709a3	504	* @{
AnnaBridge	189:f392fc9709a3	505	*/
AnnaBridge	189:f392fc9709a3	506	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	507	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
AnnaBridge	189:f392fc9709a3	508	/**
AnnaBridge	189:f392fc9709a3	509	* @}
AnnaBridge	189:f392fc9709a3	510	*/
AnnaBridge	189:f392fc9709a3	511
AnnaBridge	189:f392fc9709a3	512	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
AnnaBridge	189:f392fc9709a3	513	* @{
AnnaBridge	189:f392fc9709a3	514	*/
AnnaBridge	189:f392fc9709a3	515	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	516	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
AnnaBridge	189:f392fc9709a3	517	/**
AnnaBridge	189:f392fc9709a3	518	* @}
AnnaBridge	189:f392fc9709a3	519	*/
AnnaBridge	189:f392fc9709a3	520
AnnaBridge	189:f392fc9709a3	521	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
AnnaBridge	189:f392fc9709a3	522	* @{
AnnaBridge	189:f392fc9709a3	523	*/
AnnaBridge	189:f392fc9709a3	524	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
AnnaBridge	189:f392fc9709a3	525	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	526	/**
AnnaBridge	189:f392fc9709a3	527	* @}
AnnaBridge	189:f392fc9709a3	528	*/
AnnaBridge	189:f392fc9709a3	529
AnnaBridge	189:f392fc9709a3	530	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
AnnaBridge	189:f392fc9709a3	531	* @{
AnnaBridge	189:f392fc9709a3	532	*/
AnnaBridge	189:f392fc9709a3	533	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
AnnaBridge	189:f392fc9709a3	534	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	535	/**
AnnaBridge	189:f392fc9709a3	536	* @}
AnnaBridge	189:f392fc9709a3	537	*/
AnnaBridge	189:f392fc9709a3	538
AnnaBridge	189:f392fc9709a3	539	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
AnnaBridge	189:f392fc9709a3	540	* @{
AnnaBridge	189:f392fc9709a3	541	*/
AnnaBridge	189:f392fc9709a3	542	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
AnnaBridge	189:f392fc9709a3	543	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
AnnaBridge	189:f392fc9709a3	544	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
AnnaBridge	189:f392fc9709a3	545	/**
AnnaBridge	189:f392fc9709a3	546	* @}
AnnaBridge	189:f392fc9709a3	547	*/
AnnaBridge	189:f392fc9709a3	548
AnnaBridge	189:f392fc9709a3	549	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
AnnaBridge	189:f392fc9709a3	550	* @{
AnnaBridge	189:f392fc9709a3	551	*/
AnnaBridge	189:f392fc9709a3	552	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge	189:f392fc9709a3	553	connected to IC1, IC2, IC3 or IC4, respectively */
AnnaBridge	189:f392fc9709a3	554	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge	189:f392fc9709a3	555	connected to IC2, IC1, IC4 or IC3, respectively */
AnnaBridge	189:f392fc9709a3	556	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
AnnaBridge	189:f392fc9709a3	557	/**
AnnaBridge	189:f392fc9709a3	558	* @}
AnnaBridge	189:f392fc9709a3	559	*/
AnnaBridge	189:f392fc9709a3	560
AnnaBridge	189:f392fc9709a3	561	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
AnnaBridge	189:f392fc9709a3	562	* @{
AnnaBridge	189:f392fc9709a3	563	*/
AnnaBridge	189:f392fc9709a3	564	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
AnnaBridge	189:f392fc9709a3	565	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
AnnaBridge	189:f392fc9709a3	566	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
AnnaBridge	189:f392fc9709a3	567	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
AnnaBridge	189:f392fc9709a3	568	/**
AnnaBridge	189:f392fc9709a3	569	* @}
AnnaBridge	189:f392fc9709a3	570	*/
AnnaBridge	189:f392fc9709a3	571
AnnaBridge	189:f392fc9709a3	572	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
AnnaBridge	189:f392fc9709a3	573	* @{
AnnaBridge	189:f392fc9709a3	574	*/
AnnaBridge	189:f392fc9709a3	575	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
AnnaBridge	189:f392fc9709a3	576	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	577	/**
AnnaBridge	189:f392fc9709a3	578	* @}
AnnaBridge	189:f392fc9709a3	579	*/
AnnaBridge	189:f392fc9709a3	580
AnnaBridge	189:f392fc9709a3	581	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
AnnaBridge	189:f392fc9709a3	582	* @{
AnnaBridge	189:f392fc9709a3	583	*/
AnnaBridge	189:f392fc9709a3	584	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
AnnaBridge	189:f392fc9709a3	585	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
AnnaBridge	189:f392fc9709a3	586	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
AnnaBridge	189:f392fc9709a3	587	/**
AnnaBridge	189:f392fc9709a3	588	* @}
AnnaBridge	189:f392fc9709a3	589	*/
AnnaBridge	189:f392fc9709a3	590
AnnaBridge	189:f392fc9709a3	591	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
AnnaBridge	189:f392fc9709a3	592	* @{
AnnaBridge	189:f392fc9709a3	593	*/
AnnaBridge	189:f392fc9709a3	594	#define TIM_IT_UPDATE (TIM_DIER_UIE)
AnnaBridge	189:f392fc9709a3	595	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
AnnaBridge	189:f392fc9709a3	596	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
AnnaBridge	189:f392fc9709a3	597	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
AnnaBridge	189:f392fc9709a3	598	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
AnnaBridge	189:f392fc9709a3	599	#define TIM_IT_COM (TIM_DIER_COMIE)
AnnaBridge	189:f392fc9709a3	600	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
AnnaBridge	189:f392fc9709a3	601	#define TIM_IT_BREAK (TIM_DIER_BIE)
AnnaBridge	189:f392fc9709a3	602	/**
AnnaBridge	189:f392fc9709a3	603	* @}
AnnaBridge	189:f392fc9709a3	604	*/
AnnaBridge	189:f392fc9709a3	605
AnnaBridge	189:f392fc9709a3	606	/** @defgroup TIM_Commutation_Source TIM Commutation Source
AnnaBridge	189:f392fc9709a3	607	* @{
AnnaBridge	189:f392fc9709a3	608	*/
AnnaBridge	189:f392fc9709a3	609	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
AnnaBridge	189:f392fc9709a3	610	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	611	/**
AnnaBridge	189:f392fc9709a3	612	* @}
AnnaBridge	189:f392fc9709a3	613	*/
AnnaBridge	189:f392fc9709a3	614
AnnaBridge	189:f392fc9709a3	615	/** @defgroup TIM_DMA_sources TIM DMA Sources
AnnaBridge	189:f392fc9709a3	616	* @{
AnnaBridge	189:f392fc9709a3	617	*/
AnnaBridge	189:f392fc9709a3	618	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
AnnaBridge	189:f392fc9709a3	619	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
AnnaBridge	189:f392fc9709a3	620	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
AnnaBridge	189:f392fc9709a3	621	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
AnnaBridge	189:f392fc9709a3	622	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
AnnaBridge	189:f392fc9709a3	623	#define TIM_DMA_COM (TIM_DIER_COMDE)
AnnaBridge	189:f392fc9709a3	624	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
AnnaBridge	189:f392fc9709a3	625	/**
AnnaBridge	189:f392fc9709a3	626	* @}
AnnaBridge	189:f392fc9709a3	627	*/
AnnaBridge	189:f392fc9709a3	628
AnnaBridge	189:f392fc9709a3	629	/** @defgroup TIM_Flag_definition TIM Flag Definition
AnnaBridge	189:f392fc9709a3	630	* @{
AnnaBridge	189:f392fc9709a3	631	*/
AnnaBridge	189:f392fc9709a3	632	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
AnnaBridge	189:f392fc9709a3	633	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
AnnaBridge	189:f392fc9709a3	634	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
AnnaBridge	189:f392fc9709a3	635	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
AnnaBridge	189:f392fc9709a3	636	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
AnnaBridge	189:f392fc9709a3	637	#define TIM_FLAG_CC5 (TIM_SR_CC5IF)
AnnaBridge	189:f392fc9709a3	638	#define TIM_FLAG_CC6 (TIM_SR_CC6IF)
AnnaBridge	189:f392fc9709a3	639	#define TIM_FLAG_COM (TIM_SR_COMIF)
AnnaBridge	189:f392fc9709a3	640	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
AnnaBridge	189:f392fc9709a3	641	#define TIM_FLAG_BREAK (TIM_SR_BIF)
AnnaBridge	189:f392fc9709a3	642	#define TIM_FLAG_BREAK2 (TIM_SR_B2IF)
AnnaBridge	189:f392fc9709a3	643	#define TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF)
AnnaBridge	189:f392fc9709a3	644	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
AnnaBridge	189:f392fc9709a3	645	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
AnnaBridge	189:f392fc9709a3	646	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
AnnaBridge	189:f392fc9709a3	647	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
AnnaBridge	189:f392fc9709a3	648	/**
AnnaBridge	189:f392fc9709a3	649	* @}
AnnaBridge	189:f392fc9709a3	650	*/
AnnaBridge	189:f392fc9709a3	651
AnnaBridge	189:f392fc9709a3	652	/** @defgroup TIM_Channel TIM Channel
AnnaBridge	189:f392fc9709a3	653	* @{
AnnaBridge	189:f392fc9709a3	654	*/
AnnaBridge	189:f392fc9709a3	655	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	656	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
AnnaBridge	189:f392fc9709a3	657	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
AnnaBridge	189:f392fc9709a3	658	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
AnnaBridge	189:f392fc9709a3	659	#define TIM_CHANNEL_5 ((uint32_t)0x0010)
AnnaBridge	189:f392fc9709a3	660	#define TIM_CHANNEL_6 ((uint32_t)0x0014)
AnnaBridge	189:f392fc9709a3	661	#define TIM_CHANNEL_ALL ((uint32_t)0x003C)
AnnaBridge	189:f392fc9709a3	662	/**
AnnaBridge	189:f392fc9709a3	663	* @}
AnnaBridge	189:f392fc9709a3	664	*/
AnnaBridge	189:f392fc9709a3	665
AnnaBridge	189:f392fc9709a3	666	/** @defgroup TIM_Clock_Source TIM Clock Source
AnnaBridge	189:f392fc9709a3	667	* @{
AnnaBridge	189:f392fc9709a3	668	*/
AnnaBridge	189:f392fc9709a3	669	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
AnnaBridge	189:f392fc9709a3	670	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
AnnaBridge	189:f392fc9709a3	671	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	672	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
AnnaBridge	189:f392fc9709a3	673	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
AnnaBridge	189:f392fc9709a3	674	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
AnnaBridge	189:f392fc9709a3	675	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
AnnaBridge	189:f392fc9709a3	676	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
AnnaBridge	189:f392fc9709a3	677	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
AnnaBridge	189:f392fc9709a3	678	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
AnnaBridge	189:f392fc9709a3	679	/**
AnnaBridge	189:f392fc9709a3	680	* @}
AnnaBridge	189:f392fc9709a3	681	*/
AnnaBridge	189:f392fc9709a3	682
AnnaBridge	189:f392fc9709a3	683	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
AnnaBridge	189:f392fc9709a3	684	* @{
AnnaBridge	189:f392fc9709a3	685	*/
AnnaBridge	189:f392fc9709a3	686	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
AnnaBridge	189:f392fc9709a3	687	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
AnnaBridge	189:f392fc9709a3	688	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
AnnaBridge	189:f392fc9709a3	689	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
AnnaBridge	189:f392fc9709a3	690	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
AnnaBridge	189:f392fc9709a3	691	/**
AnnaBridge	189:f392fc9709a3	692	* @}
AnnaBridge	189:f392fc9709a3	693	*/
AnnaBridge	189:f392fc9709a3	694
AnnaBridge	189:f392fc9709a3	695	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
AnnaBridge	189:f392fc9709a3	696	* @{
AnnaBridge	189:f392fc9709a3	697	*/
AnnaBridge	189:f392fc9709a3	698	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
AnnaBridge	189:f392fc9709a3	699	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
AnnaBridge	189:f392fc9709a3	700	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
AnnaBridge	189:f392fc9709a3	701	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
AnnaBridge	189:f392fc9709a3	702	/**
AnnaBridge	189:f392fc9709a3	703	* @}
AnnaBridge	189:f392fc9709a3	704	*/
AnnaBridge	189:f392fc9709a3	705
AnnaBridge	189:f392fc9709a3	706	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
AnnaBridge	189:f392fc9709a3	707	* @{
AnnaBridge	189:f392fc9709a3	708	*/
AnnaBridge	189:f392fc9709a3	709	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
AnnaBridge	189:f392fc9709a3	710	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
AnnaBridge	189:f392fc9709a3	711	/**
AnnaBridge	189:f392fc9709a3	712	* @}
AnnaBridge	189:f392fc9709a3	713	*/
AnnaBridge	189:f392fc9709a3	714
AnnaBridge	189:f392fc9709a3	715	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
AnnaBridge	189:f392fc9709a3	716	* @{
AnnaBridge	189:f392fc9709a3	717	*/
AnnaBridge	189:f392fc9709a3	718	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
AnnaBridge	189:f392fc9709a3	719	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
AnnaBridge	189:f392fc9709a3	720	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
AnnaBridge	189:f392fc9709a3	721	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
AnnaBridge	189:f392fc9709a3	722	/**
AnnaBridge	189:f392fc9709a3	723	* @}
AnnaBridge	189:f392fc9709a3	724	*/
AnnaBridge	189:f392fc9709a3	725
AnnaBridge	189:f392fc9709a3	726	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
AnnaBridge	189:f392fc9709a3	727	* @{
AnnaBridge	189:f392fc9709a3	728	*/
AnnaBridge	189:f392fc9709a3	729	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
AnnaBridge	189:f392fc9709a3	730	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	731	/**
AnnaBridge	189:f392fc9709a3	732	* @}
AnnaBridge	189:f392fc9709a3	733	*/
AnnaBridge	189:f392fc9709a3	734
AnnaBridge	189:f392fc9709a3	735	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
AnnaBridge	189:f392fc9709a3	736	* @{
AnnaBridge	189:f392fc9709a3	737	*/
AnnaBridge	189:f392fc9709a3	738	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
AnnaBridge	189:f392fc9709a3	739	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	740	/**
AnnaBridge	189:f392fc9709a3	741	* @}
AnnaBridge	189:f392fc9709a3	742	*/
AnnaBridge	189:f392fc9709a3	743	/** @defgroup TIM_Lock_level TIM Lock level
AnnaBridge	189:f392fc9709a3	744	* @{
AnnaBridge	189:f392fc9709a3	745	*/
AnnaBridge	189:f392fc9709a3	746	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	747	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
AnnaBridge	189:f392fc9709a3	748	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
AnnaBridge	189:f392fc9709a3	749	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
AnnaBridge	189:f392fc9709a3	750	/**
AnnaBridge	189:f392fc9709a3	751	* @}
AnnaBridge	189:f392fc9709a3	752	*/
AnnaBridge	189:f392fc9709a3	753
AnnaBridge	189:f392fc9709a3	754	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
AnnaBridge	189:f392fc9709a3	755	* @{
AnnaBridge	189:f392fc9709a3	756	*/
AnnaBridge	189:f392fc9709a3	757	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
AnnaBridge	189:f392fc9709a3	758	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	759	/**
AnnaBridge	189:f392fc9709a3	760	* @}
AnnaBridge	189:f392fc9709a3	761	*/
AnnaBridge	189:f392fc9709a3	762
AnnaBridge	189:f392fc9709a3	763	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
AnnaBridge	189:f392fc9709a3	764	* @{
AnnaBridge	189:f392fc9709a3	765	*/
AnnaBridge	189:f392fc9709a3	766	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	767	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
AnnaBridge	189:f392fc9709a3	768	/**
AnnaBridge	189:f392fc9709a3	769	* @}
AnnaBridge	189:f392fc9709a3	770	*/
AnnaBridge	189:f392fc9709a3	771
AnnaBridge	189:f392fc9709a3	772	/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
AnnaBridge	189:f392fc9709a3	773	* @{
AnnaBridge	189:f392fc9709a3	774	*/
AnnaBridge	189:f392fc9709a3	775	#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
AnnaBridge	189:f392fc9709a3	776	#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
AnnaBridge	189:f392fc9709a3	777	/**
AnnaBridge	189:f392fc9709a3	778	* @}
AnnaBridge	189:f392fc9709a3	779	*/
AnnaBridge	189:f392fc9709a3	780
AnnaBridge	189:f392fc9709a3	781	/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
AnnaBridge	189:f392fc9709a3	782	* @{
AnnaBridge	189:f392fc9709a3	783	*/
AnnaBridge	189:f392fc9709a3	784	#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
AnnaBridge	189:f392fc9709a3	785	#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
AnnaBridge	189:f392fc9709a3	786	/**
AnnaBridge	189:f392fc9709a3	787	* @}
AnnaBridge	189:f392fc9709a3	788	*/
AnnaBridge	189:f392fc9709a3	789
AnnaBridge	189:f392fc9709a3	790	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
AnnaBridge	189:f392fc9709a3	791	* @{
AnnaBridge	189:f392fc9709a3	792	*/
AnnaBridge	189:f392fc9709a3	793	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
AnnaBridge	189:f392fc9709a3	794	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	795	/**
AnnaBridge	189:f392fc9709a3	796	* @}
AnnaBridge	189:f392fc9709a3	797	*/
AnnaBridge	189:f392fc9709a3	798
AnnaBridge	189:f392fc9709a3	799	/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
AnnaBridge	189:f392fc9709a3	800	* @{
AnnaBridge	189:f392fc9709a3	801	*/
AnnaBridge	189:f392fc9709a3	802	#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
AnnaBridge	189:f392fc9709a3	803	#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
AnnaBridge	189:f392fc9709a3	804	#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
AnnaBridge	189:f392fc9709a3	805	#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
AnnaBridge	189:f392fc9709a3	806	/**
AnnaBridge	189:f392fc9709a3	807	* @}
AnnaBridge	189:f392fc9709a3	808	*/
AnnaBridge	189:f392fc9709a3	809
AnnaBridge	189:f392fc9709a3	810	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
AnnaBridge	189:f392fc9709a3	811	* @{
AnnaBridge	189:f392fc9709a3	812	*/
AnnaBridge	189:f392fc9709a3	813	#define TIM_TRGO_RESET ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	814	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
AnnaBridge	189:f392fc9709a3	815	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
AnnaBridge	189:f392fc9709a3	816	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
AnnaBridge	189:f392fc9709a3	817	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
AnnaBridge	189:f392fc9709a3	818	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
AnnaBridge	189:f392fc9709a3	819	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
AnnaBridge	189:f392fc9709a3	820	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
AnnaBridge	189:f392fc9709a3	821	/**
AnnaBridge	189:f392fc9709a3	822	* @}
AnnaBridge	189:f392fc9709a3	823	*/
AnnaBridge	189:f392fc9709a3	824
AnnaBridge	189:f392fc9709a3	825	/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
AnnaBridge	189:f392fc9709a3	826	* @{
AnnaBridge	189:f392fc9709a3	827	*/
AnnaBridge	189:f392fc9709a3	828	#define TIM_TRGO2_RESET ((uint32_t)0x00000000)
AnnaBridge	189:f392fc9709a3	829	#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
AnnaBridge	189:f392fc9709a3	830	#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
AnnaBridge	189:f392fc9709a3	831	#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
AnnaBridge	189:f392fc9709a3	832	#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
AnnaBridge	189:f392fc9709a3	833	#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0))
AnnaBridge	189:f392fc9709a3	834	#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1))
AnnaBridge	189:f392fc9709a3	835	#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
AnnaBridge	189:f392fc9709a3	836	#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
AnnaBridge	189:f392fc9709a3	837	#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0))
AnnaBridge	189:f392fc9709a3	838	#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1))
AnnaBridge	189:f392fc9709a3	839	#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
AnnaBridge	189:f392fc9709a3	840	#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2))
AnnaBridge	189:f392fc9709a3	841	#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0))
AnnaBridge	189:f392fc9709a3	842	#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1))
AnnaBridge	189:f392fc9709a3	843	#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0))
AnnaBridge	189:f392fc9709a3	844	/**
AnnaBridge	189:f392fc9709a3	845	* @}
AnnaBridge	189:f392fc9709a3	846	*/
AnnaBridge	189:f392fc9709a3	847
AnnaBridge	189:f392fc9709a3	848	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
AnnaBridge	189:f392fc9709a3	849	* @{
AnnaBridge	189:f392fc9709a3	850	*/
AnnaBridge	189:f392fc9709a3	851	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
AnnaBridge	189:f392fc9709a3	852	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	853	/**
AnnaBridge	189:f392fc9709a3	854	* @}
AnnaBridge	189:f392fc9709a3	855	*/
AnnaBridge	189:f392fc9709a3	856
AnnaBridge	189:f392fc9709a3	857	/** @defgroup TIM_Slave_Mode TIM Slave mode
AnnaBridge	189:f392fc9709a3	858	* @{
AnnaBridge	189:f392fc9709a3	859	*/
AnnaBridge	189:f392fc9709a3	860	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	861	#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
AnnaBridge	189:f392fc9709a3	862	#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0))
AnnaBridge	189:f392fc9709a3	863	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1))
AnnaBridge	189:f392fc9709a3	864	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0))
AnnaBridge	189:f392fc9709a3	865	#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
AnnaBridge	189:f392fc9709a3	866	/**
AnnaBridge	189:f392fc9709a3	867	* @}
AnnaBridge	189:f392fc9709a3	868	*/
AnnaBridge	189:f392fc9709a3	869
AnnaBridge	189:f392fc9709a3	870	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
AnnaBridge	189:f392fc9709a3	871	* @{
AnnaBridge	189:f392fc9709a3	872	*/
AnnaBridge	189:f392fc9709a3	873	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	874	#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
AnnaBridge	189:f392fc9709a3	875	#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
AnnaBridge	189:f392fc9709a3	876	#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0)
AnnaBridge	189:f392fc9709a3	877	#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1)
AnnaBridge	189:f392fc9709a3	878	#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0)
AnnaBridge	189:f392fc9709a3	879	#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0)
AnnaBridge	189:f392fc9709a3	880	#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
AnnaBridge	189:f392fc9709a3	881
AnnaBridge	189:f392fc9709a3	882	#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
AnnaBridge	189:f392fc9709a3	883	#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0)
AnnaBridge	189:f392fc9709a3	884	#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2)
AnnaBridge	189:f392fc9709a3	885	#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
AnnaBridge	189:f392fc9709a3	886	#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
AnnaBridge	189:f392fc9709a3	887	#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M)
AnnaBridge	189:f392fc9709a3	888	/**
AnnaBridge	189:f392fc9709a3	889	* @}
AnnaBridge	189:f392fc9709a3	890	*/
AnnaBridge	189:f392fc9709a3	891
AnnaBridge	189:f392fc9709a3	892	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
AnnaBridge	189:f392fc9709a3	893	* @{
AnnaBridge	189:f392fc9709a3	894	*/
AnnaBridge	189:f392fc9709a3	895	#define TIM_TS_ITR0 ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	896	#define TIM_TS_ITR1 ((uint32_t)0x0010)
AnnaBridge	189:f392fc9709a3	897	#define TIM_TS_ITR2 ((uint32_t)0x0020)
AnnaBridge	189:f392fc9709a3	898	#define TIM_TS_ITR3 ((uint32_t)0x0030)
AnnaBridge	189:f392fc9709a3	899	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
AnnaBridge	189:f392fc9709a3	900	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
AnnaBridge	189:f392fc9709a3	901	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
AnnaBridge	189:f392fc9709a3	902	#define TIM_TS_ETRF ((uint32_t)0x0070)
AnnaBridge	189:f392fc9709a3	903	#define TIM_TS_NONE ((uint32_t)0xFFFF)
AnnaBridge	189:f392fc9709a3	904	/**
AnnaBridge	189:f392fc9709a3	905	* @}
AnnaBridge	189:f392fc9709a3	906	*/
AnnaBridge	189:f392fc9709a3	907
AnnaBridge	189:f392fc9709a3	908	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
AnnaBridge	189:f392fc9709a3	909	* @{
AnnaBridge	189:f392fc9709a3	910	*/
AnnaBridge	189:f392fc9709a3	911	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
AnnaBridge	189:f392fc9709a3	912	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
AnnaBridge	189:f392fc9709a3	913	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
AnnaBridge	189:f392fc9709a3	914	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
AnnaBridge	189:f392fc9709a3	915	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
AnnaBridge	189:f392fc9709a3	916	/**
AnnaBridge	189:f392fc9709a3	917	* @}
AnnaBridge	189:f392fc9709a3	918	*/
AnnaBridge	189:f392fc9709a3	919
AnnaBridge	189:f392fc9709a3	920	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
AnnaBridge	189:f392fc9709a3	921	* @{
AnnaBridge	189:f392fc9709a3	922	*/
AnnaBridge	189:f392fc9709a3	923	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
AnnaBridge	189:f392fc9709a3	924	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
AnnaBridge	189:f392fc9709a3	925	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
AnnaBridge	189:f392fc9709a3	926	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
AnnaBridge	189:f392fc9709a3	927	/**
AnnaBridge	189:f392fc9709a3	928	* @}
AnnaBridge	189:f392fc9709a3	929	*/
AnnaBridge	189:f392fc9709a3	930
AnnaBridge	189:f392fc9709a3	931	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
AnnaBridge	189:f392fc9709a3	932	* @{
AnnaBridge	189:f392fc9709a3	933	*/
AnnaBridge	189:f392fc9709a3	934	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	935	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
AnnaBridge	189:f392fc9709a3	936	/**
AnnaBridge	189:f392fc9709a3	937	* @}
AnnaBridge	189:f392fc9709a3	938	*/
AnnaBridge	189:f392fc9709a3	939
AnnaBridge	189:f392fc9709a3	940	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
AnnaBridge	189:f392fc9709a3	941	* @{
AnnaBridge	189:f392fc9709a3	942	*/
AnnaBridge	189:f392fc9709a3	943	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
AnnaBridge	189:f392fc9709a3	944	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
AnnaBridge	189:f392fc9709a3	945	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
AnnaBridge	189:f392fc9709a3	946	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
AnnaBridge	189:f392fc9709a3	947	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
AnnaBridge	189:f392fc9709a3	948	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
AnnaBridge	189:f392fc9709a3	949	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
AnnaBridge	189:f392fc9709a3	950	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
AnnaBridge	189:f392fc9709a3	951	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
AnnaBridge	189:f392fc9709a3	952	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
AnnaBridge	189:f392fc9709a3	953	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
AnnaBridge	189:f392fc9709a3	954	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
AnnaBridge	189:f392fc9709a3	955	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
AnnaBridge	189:f392fc9709a3	956	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
AnnaBridge	189:f392fc9709a3	957	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
AnnaBridge	189:f392fc9709a3	958	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
AnnaBridge	189:f392fc9709a3	959	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
AnnaBridge	189:f392fc9709a3	960	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
AnnaBridge	189:f392fc9709a3	961	/**
AnnaBridge	189:f392fc9709a3	962	* @}
AnnaBridge	189:f392fc9709a3	963	*/
AnnaBridge	189:f392fc9709a3	964
AnnaBridge	189:f392fc9709a3	965	/** @defgroup DMA_Handle_index TIM DMA Handle Index
AnnaBridge	189:f392fc9709a3	966	* @{
AnnaBridge	189:f392fc9709a3	967	*/
AnnaBridge	189:f392fc9709a3	968	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
AnnaBridge	189:f392fc9709a3	969	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
AnnaBridge	189:f392fc9709a3	970	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
AnnaBridge	189:f392fc9709a3	971	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
AnnaBridge	189:f392fc9709a3	972	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
AnnaBridge	189:f392fc9709a3	973	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
AnnaBridge	189:f392fc9709a3	974	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
AnnaBridge	189:f392fc9709a3	975	/**
AnnaBridge	189:f392fc9709a3	976	* @}
AnnaBridge	189:f392fc9709a3	977	*/
AnnaBridge	189:f392fc9709a3	978
AnnaBridge	189:f392fc9709a3	979	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
AnnaBridge	189:f392fc9709a3	980	* @{
AnnaBridge	189:f392fc9709a3	981	*/
AnnaBridge	189:f392fc9709a3	982	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
AnnaBridge	189:f392fc9709a3	983	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	984	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
AnnaBridge	189:f392fc9709a3	985	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
AnnaBridge	189:f392fc9709a3	986	/**
AnnaBridge	189:f392fc9709a3	987	* @}
AnnaBridge	189:f392fc9709a3	988	*/
AnnaBridge	189:f392fc9709a3	989
AnnaBridge	189:f392fc9709a3	990	/** @defgroup TIM_Break_System TIM Break System
AnnaBridge	189:f392fc9709a3	991	* @{
AnnaBridge	189:f392fc9709a3	992	*/
AnnaBridge	189:f392fc9709a3	993	#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 /
AnnaBridge	189:f392fc9709a3	994	#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface /
AnnaBridge	189:f392fc9709a3	995	#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 /
AnnaBridge	189:f392fc9709a3	996	#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 /
AnnaBridge	189:f392fc9709a3	997	/**
AnnaBridge	189:f392fc9709a3	998	* @}
AnnaBridge	189:f392fc9709a3	999	*/
AnnaBridge	189:f392fc9709a3	1000
AnnaBridge	189:f392fc9709a3	1001	/**
AnnaBridge	189:f392fc9709a3	1002	* @}
AnnaBridge	189:f392fc9709a3	1003	*/
AnnaBridge	189:f392fc9709a3	1004	/* End of exported constants -------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1005
AnnaBridge	189:f392fc9709a3	1006	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1007	/** @defgroup TIM_Exported_Macros TIM Exported Macros
AnnaBridge	189:f392fc9709a3	1008	* @{
AnnaBridge	189:f392fc9709a3	1009	*/
AnnaBridge	189:f392fc9709a3	1010
AnnaBridge	189:f392fc9709a3	1011	/** @brief Reset TIM handle state.
AnnaBridge	189:f392fc9709a3	1012	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1013	* @retval None
AnnaBridge	189:f392fc9709a3	1014	*/
AnnaBridge	189:f392fc9709a3	1015	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
AnnaBridge	189:f392fc9709a3	1016
AnnaBridge	189:f392fc9709a3	1017	/**
AnnaBridge	189:f392fc9709a3	1018	* @brief Enable the TIM peripheral.
AnnaBridge	189:f392fc9709a3	1019	* @param __HANDLE__ TIM handle
AnnaBridge	189:f392fc9709a3	1020	* @retval None
AnnaBridge	189:f392fc9709a3	1021	*/
AnnaBridge	189:f392fc9709a3	1022	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
AnnaBridge	189:f392fc9709a3	1023
AnnaBridge	189:f392fc9709a3	1024	/**
AnnaBridge	189:f392fc9709a3	1025	* @brief Enable the TIM main Output.
AnnaBridge	189:f392fc9709a3	1026	* @param __HANDLE__ TIM handle
AnnaBridge	189:f392fc9709a3	1027	* @retval None
AnnaBridge	189:f392fc9709a3	1028	*/
AnnaBridge	189:f392fc9709a3	1029	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
AnnaBridge	189:f392fc9709a3	1030
AnnaBridge	189:f392fc9709a3	1031	/**
AnnaBridge	189:f392fc9709a3	1032	* @brief Disable the TIM peripheral.
AnnaBridge	189:f392fc9709a3	1033	* @param __HANDLE__ TIM handle
AnnaBridge	189:f392fc9709a3	1034	* @retval None
AnnaBridge	189:f392fc9709a3	1035	*/
AnnaBridge	189:f392fc9709a3	1036	#define __HAL_TIM_DISABLE(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	1037	do { \
AnnaBridge	189:f392fc9709a3	1038	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
AnnaBridge	189:f392fc9709a3	1039	{ \
AnnaBridge	189:f392fc9709a3	1040	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
AnnaBridge	189:f392fc9709a3	1041	{ \
AnnaBridge	189:f392fc9709a3	1042	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
AnnaBridge	189:f392fc9709a3	1043	} \
AnnaBridge	189:f392fc9709a3	1044	} \
AnnaBridge	189:f392fc9709a3	1045	} while(0)
AnnaBridge	189:f392fc9709a3	1046
AnnaBridge	189:f392fc9709a3	1047	/**
AnnaBridge	189:f392fc9709a3	1048	* @brief Disable the TIM main Output.
AnnaBridge	189:f392fc9709a3	1049	* @param __HANDLE__ TIM handle
AnnaBridge	189:f392fc9709a3	1050	* @retval None
AnnaBridge	189:f392fc9709a3	1051	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
AnnaBridge	189:f392fc9709a3	1052	*/
AnnaBridge	189:f392fc9709a3	1053	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	1054	do { \
AnnaBridge	189:f392fc9709a3	1055	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
AnnaBridge	189:f392fc9709a3	1056	{ \
AnnaBridge	189:f392fc9709a3	1057	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
AnnaBridge	189:f392fc9709a3	1058	{ \
AnnaBridge	189:f392fc9709a3	1059	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
AnnaBridge	189:f392fc9709a3	1060	} \
AnnaBridge	189:f392fc9709a3	1061	} \
AnnaBridge	189:f392fc9709a3	1062	} while(0)
AnnaBridge	189:f392fc9709a3	1063
AnnaBridge	189:f392fc9709a3	1064	/**
AnnaBridge	189:f392fc9709a3	1065	* @brief Disable the TIM main Output.
AnnaBridge	189:f392fc9709a3	1066	* @param __HANDLE__ TIM handle
AnnaBridge	189:f392fc9709a3	1067	* @retval None
AnnaBridge	189:f392fc9709a3	1068	* @note The Main Output Enable of a timer instance is disabled unconditionally
AnnaBridge	189:f392fc9709a3	1069	*/
AnnaBridge	189:f392fc9709a3	1070	#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
AnnaBridge	189:f392fc9709a3	1071
AnnaBridge	189:f392fc9709a3	1072	/** @brief Enable the specified TIM interrupt.
AnnaBridge	189:f392fc9709a3	1073	* @param __HANDLE__ specifies the TIM Handle.
AnnaBridge	189:f392fc9709a3	1074	* @param __INTERRUPT__ specifies the TIM interrupt source to enable.
AnnaBridge	189:f392fc9709a3	1075	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1076	* @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge	189:f392fc9709a3	1077	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge	189:f392fc9709a3	1078	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge	189:f392fc9709a3	1079	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge	189:f392fc9709a3	1080	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge	189:f392fc9709a3	1081	* @arg TIM_IT_COM: Commutation interrupt
AnnaBridge	189:f392fc9709a3	1082	* @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge	189:f392fc9709a3	1083	* @arg TIM_IT_BREAK: Break interrupt
AnnaBridge	189:f392fc9709a3	1084	* @retval None
AnnaBridge	189:f392fc9709a3	1085	*/
AnnaBridge	189:f392fc9709a3	1086	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	1087
AnnaBridge	189:f392fc9709a3	1088
AnnaBridge	189:f392fc9709a3	1089	/** @brief Disable the specified TIM interrupt.
AnnaBridge	189:f392fc9709a3	1090	* @param __HANDLE__ specifies the TIM Handle.
AnnaBridge	189:f392fc9709a3	1091	* @param __INTERRUPT__ specifies the TIM interrupt source to disable.
AnnaBridge	189:f392fc9709a3	1092	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1093	* @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge	189:f392fc9709a3	1094	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge	189:f392fc9709a3	1095	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge	189:f392fc9709a3	1096	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge	189:f392fc9709a3	1097	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge	189:f392fc9709a3	1098	* @arg TIM_IT_COM: Commutation interrupt
AnnaBridge	189:f392fc9709a3	1099	* @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge	189:f392fc9709a3	1100	* @arg TIM_IT_BREAK: Break interrupt
AnnaBridge	189:f392fc9709a3	1101	* @retval None
AnnaBridge	189:f392fc9709a3	1102	*/
AnnaBridge	189:f392fc9709a3	1103	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	1104
AnnaBridge	189:f392fc9709a3	1105	/** @brief Enable the specified DMA request.
AnnaBridge	189:f392fc9709a3	1106	* @param __HANDLE__ specifies the TIM Handle.
AnnaBridge	189:f392fc9709a3	1107	* @param __DMA__ specifies the TIM DMA request to enable.
AnnaBridge	189:f392fc9709a3	1108	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1109	* @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge	189:f392fc9709a3	1110	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge	189:f392fc9709a3	1111	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge	189:f392fc9709a3	1112	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge	189:f392fc9709a3	1113	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge	189:f392fc9709a3	1114	* @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge	189:f392fc9709a3	1115	* @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge	189:f392fc9709a3	1116	* @retval None
AnnaBridge	189:f392fc9709a3	1117	*/
AnnaBridge	189:f392fc9709a3	1118	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
AnnaBridge	189:f392fc9709a3	1119
AnnaBridge	189:f392fc9709a3	1120	/** @brief Disable the specified DMA request.
AnnaBridge	189:f392fc9709a3	1121	* @param __HANDLE__ specifies the TIM Handle.
AnnaBridge	189:f392fc9709a3	1122	* @param __DMA__ specifies the TIM DMA request to disable.
AnnaBridge	189:f392fc9709a3	1123	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1124	* @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge	189:f392fc9709a3	1125	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge	189:f392fc9709a3	1126	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge	189:f392fc9709a3	1127	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge	189:f392fc9709a3	1128	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge	189:f392fc9709a3	1129	* @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge	189:f392fc9709a3	1130	* @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge	189:f392fc9709a3	1131	* @retval None
AnnaBridge	189:f392fc9709a3	1132	*/
AnnaBridge	189:f392fc9709a3	1133	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
AnnaBridge	189:f392fc9709a3	1134
AnnaBridge	189:f392fc9709a3	1135	/** @brief Check whether the specified TIM interrupt flag is set or not.
AnnaBridge	189:f392fc9709a3	1136	* @param __HANDLE__ specifies the TIM Handle.
AnnaBridge	189:f392fc9709a3	1137	* @param __FLAG__ specifies the TIM interrupt flag to check.
AnnaBridge	189:f392fc9709a3	1138	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1139	* @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge	189:f392fc9709a3	1140	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge	189:f392fc9709a3	1141	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge	189:f392fc9709a3	1142	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge	189:f392fc9709a3	1143	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge	189:f392fc9709a3	1144	* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
AnnaBridge	189:f392fc9709a3	1145	* @arg TIM_FLAG_CC6: Compare 6 interrupt flag
AnnaBridge	189:f392fc9709a3	1146	* @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge	189:f392fc9709a3	1147	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge	189:f392fc9709a3	1148	* @arg TIM_FLAG_BREAK: Break interrupt flag
AnnaBridge	189:f392fc9709a3	1149	* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
AnnaBridge	189:f392fc9709a3	1150	* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
AnnaBridge	189:f392fc9709a3	1151	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge	189:f392fc9709a3	1152	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge	189:f392fc9709a3	1153	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge	189:f392fc9709a3	1154	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge	189:f392fc9709a3	1155	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	189:f392fc9709a3	1156	*/
AnnaBridge	189:f392fc9709a3	1157	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge	189:f392fc9709a3	1158
AnnaBridge	189:f392fc9709a3	1159	/** @brief Clear the specified TIM interrupt flag.
AnnaBridge	189:f392fc9709a3	1160	* @param __HANDLE__ specifies the TIM Handle.
AnnaBridge	189:f392fc9709a3	1161	* @param __FLAG__ specifies the TIM interrupt flag to clear.
AnnaBridge	189:f392fc9709a3	1162	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1163	* @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge	189:f392fc9709a3	1164	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge	189:f392fc9709a3	1165	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge	189:f392fc9709a3	1166	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge	189:f392fc9709a3	1167	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge	189:f392fc9709a3	1168	* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
AnnaBridge	189:f392fc9709a3	1169	* @arg TIM_FLAG_CC6: Compare 6 interrupt flag
AnnaBridge	189:f392fc9709a3	1170	* @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge	189:f392fc9709a3	1171	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge	189:f392fc9709a3	1172	* @arg TIM_FLAG_BREAK: Break interrupt flag
AnnaBridge	189:f392fc9709a3	1173	* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
AnnaBridge	189:f392fc9709a3	1174	* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
AnnaBridge	189:f392fc9709a3	1175	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge	189:f392fc9709a3	1176	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge	189:f392fc9709a3	1177	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge	189:f392fc9709a3	1178	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge	189:f392fc9709a3	1179	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	189:f392fc9709a3	1180	*/
AnnaBridge	189:f392fc9709a3	1181	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
AnnaBridge	189:f392fc9709a3	1182
AnnaBridge	189:f392fc9709a3	1183	/**
AnnaBridge	189:f392fc9709a3	1184	* @brief Check whether the specified TIM interrupt source is enabled or not.
AnnaBridge	189:f392fc9709a3	1185	* @param __HANDLE__ TIM handle
AnnaBridge	189:f392fc9709a3	1186	* @param __INTERRUPT__ specifies the TIM interrupt source to check.
AnnaBridge	189:f392fc9709a3	1187	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1188	* @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge	189:f392fc9709a3	1189	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge	189:f392fc9709a3	1190	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge	189:f392fc9709a3	1191	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge	189:f392fc9709a3	1192	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge	189:f392fc9709a3	1193	* @arg TIM_IT_COM: Commutation interrupt
AnnaBridge	189:f392fc9709a3	1194	* @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge	189:f392fc9709a3	1195	* @arg TIM_IT_BREAK: Break interrupt
AnnaBridge	189:f392fc9709a3	1196	* @retval The state of TIM_IT (SET or RESET).
AnnaBridge	189:f392fc9709a3	1197	*/
AnnaBridge	189:f392fc9709a3	1198	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge	189:f392fc9709a3	1199
AnnaBridge	189:f392fc9709a3	1200	/** @brief Clear the TIM interrupt pending bits.
AnnaBridge	189:f392fc9709a3	1201	* @param __HANDLE__ TIM handle
AnnaBridge	189:f392fc9709a3	1202	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	189:f392fc9709a3	1203	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1204	* @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge	189:f392fc9709a3	1205	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge	189:f392fc9709a3	1206	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge	189:f392fc9709a3	1207	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge	189:f392fc9709a3	1208	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge	189:f392fc9709a3	1209	* @arg TIM_IT_COM: Commutation interrupt
AnnaBridge	189:f392fc9709a3	1210	* @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge	189:f392fc9709a3	1211	* @arg TIM_IT_BREAK: Break interrupt
AnnaBridge	189:f392fc9709a3	1212	* @retval None
AnnaBridge	189:f392fc9709a3	1213	*/
AnnaBridge	189:f392fc9709a3	1214	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	1215
AnnaBridge	189:f392fc9709a3	1216	/**
AnnaBridge	189:f392fc9709a3	1217	* @brief Indicates whether or not the TIM Counter is used as downcounter.
AnnaBridge	189:f392fc9709a3	1218	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1219	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
AnnaBridge	189:f392fc9709a3	1220	* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
AnnaBridge	189:f392fc9709a3	1221	mode.
AnnaBridge	189:f392fc9709a3	1222	*/
AnnaBridge	189:f392fc9709a3	1223	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
AnnaBridge	189:f392fc9709a3	1224
AnnaBridge	189:f392fc9709a3	1225
AnnaBridge	189:f392fc9709a3	1226	/**
AnnaBridge	189:f392fc9709a3	1227	* @brief Set the TIM Prescaler on runtime.
AnnaBridge	189:f392fc9709a3	1228	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1229	* @param __PRESC__ specifies the Prescaler new value.
AnnaBridge	189:f392fc9709a3	1230	* @retval None
AnnaBridge	189:f392fc9709a3	1231	*/
AnnaBridge	189:f392fc9709a3	1232	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
AnnaBridge	189:f392fc9709a3	1233
AnnaBridge	189:f392fc9709a3	1234	/**
AnnaBridge	189:f392fc9709a3	1235	* @brief Set the TIM Counter Register value on runtime.
AnnaBridge	189:f392fc9709a3	1236	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1237	* @param __COUNTER__ specifies the Counter register new value.
AnnaBridge	189:f392fc9709a3	1238	* @retval None
AnnaBridge	189:f392fc9709a3	1239	*/
AnnaBridge	189:f392fc9709a3	1240	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
AnnaBridge	189:f392fc9709a3	1241
AnnaBridge	189:f392fc9709a3	1242	/**
AnnaBridge	189:f392fc9709a3	1243	* @brief Get the TIM Counter Register value on runtime.
AnnaBridge	189:f392fc9709a3	1244	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1245	* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
AnnaBridge	189:f392fc9709a3	1246	*/
AnnaBridge	189:f392fc9709a3	1247	#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	1248	((__HANDLE__)->Instance->CNT)
AnnaBridge	189:f392fc9709a3	1249
AnnaBridge	189:f392fc9709a3	1250	/**
AnnaBridge	189:f392fc9709a3	1251	* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
AnnaBridge	189:f392fc9709a3	1252	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1253	* @param __AUTORELOAD__ specifies the Counter register new value.
AnnaBridge	189:f392fc9709a3	1254	* @retval None
AnnaBridge	189:f392fc9709a3	1255	*/
AnnaBridge	189:f392fc9709a3	1256	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
AnnaBridge	189:f392fc9709a3	1257	do{ \
AnnaBridge	189:f392fc9709a3	1258	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
AnnaBridge	189:f392fc9709a3	1259	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
AnnaBridge	189:f392fc9709a3	1260	} while(0)
AnnaBridge	189:f392fc9709a3	1261
AnnaBridge	189:f392fc9709a3	1262	/**
AnnaBridge	189:f392fc9709a3	1263	* @brief Get the TIM Autoreload Register value on runtime.
AnnaBridge	189:f392fc9709a3	1264	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1265	* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
AnnaBridge	189:f392fc9709a3	1266	*/
AnnaBridge	189:f392fc9709a3	1267	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	1268	((__HANDLE__)->Instance->ARR)
AnnaBridge	189:f392fc9709a3	1269
AnnaBridge	189:f392fc9709a3	1270	/**
AnnaBridge	189:f392fc9709a3	1271	* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
AnnaBridge	189:f392fc9709a3	1272	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1273	* @param __CKD__ specifies the clock division value.
AnnaBridge	189:f392fc9709a3	1274	* This parameter can be one of the following value:
AnnaBridge	189:f392fc9709a3	1275	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
AnnaBridge	189:f392fc9709a3	1276	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
AnnaBridge	189:f392fc9709a3	1277	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
AnnaBridge	189:f392fc9709a3	1278	* @retval None
AnnaBridge	189:f392fc9709a3	1279	*/
AnnaBridge	189:f392fc9709a3	1280	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
AnnaBridge	189:f392fc9709a3	1281	do{ \
AnnaBridge	189:f392fc9709a3	1282	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
AnnaBridge	189:f392fc9709a3	1283	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
AnnaBridge	189:f392fc9709a3	1284	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
AnnaBridge	189:f392fc9709a3	1285	} while(0)
AnnaBridge	189:f392fc9709a3	1286
AnnaBridge	189:f392fc9709a3	1287	/**
AnnaBridge	189:f392fc9709a3	1288	* @brief Get the TIM Clock Division value on runtime.
AnnaBridge	189:f392fc9709a3	1289	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1290	* @retval The clock division can be one of the following values:
AnnaBridge	189:f392fc9709a3	1291	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
AnnaBridge	189:f392fc9709a3	1292	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
AnnaBridge	189:f392fc9709a3	1293	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
AnnaBridge	189:f392fc9709a3	1294	*/
AnnaBridge	189:f392fc9709a3	1295	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	1296	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
AnnaBridge	189:f392fc9709a3	1297
AnnaBridge	189:f392fc9709a3	1298	/**
AnnaBridge	189:f392fc9709a3	1299	* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
AnnaBridge	189:f392fc9709a3	1300	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1301	* @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge	189:f392fc9709a3	1302	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1303	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge	189:f392fc9709a3	1304	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge	189:f392fc9709a3	1305	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge	189:f392fc9709a3	1306	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge	189:f392fc9709a3	1307	* @param __ICPSC__ specifies the Input Capture4 prescaler new value.
AnnaBridge	189:f392fc9709a3	1308	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1309	* @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge	189:f392fc9709a3	1310	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge	189:f392fc9709a3	1311	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge	189:f392fc9709a3	1312	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
AnnaBridge	189:f392fc9709a3	1313	* @retval None
AnnaBridge	189:f392fc9709a3	1314	*/
AnnaBridge	189:f392fc9709a3	1315	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge	189:f392fc9709a3	1316	do{ \
AnnaBridge	189:f392fc9709a3	1317	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
AnnaBridge	189:f392fc9709a3	1318	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
AnnaBridge	189:f392fc9709a3	1319	} while(0)
AnnaBridge	189:f392fc9709a3	1320
AnnaBridge	189:f392fc9709a3	1321	/**
AnnaBridge	189:f392fc9709a3	1322	* @brief Get the TIM Input Capture prescaler on runtime.
AnnaBridge	189:f392fc9709a3	1323	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1324	* @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge	189:f392fc9709a3	1325	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1326	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
AnnaBridge	189:f392fc9709a3	1327	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
AnnaBridge	189:f392fc9709a3	1328	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
AnnaBridge	189:f392fc9709a3	1329	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
AnnaBridge	189:f392fc9709a3	1330	* @retval The input capture prescaler can be one of the following values:
AnnaBridge	189:f392fc9709a3	1331	* @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge	189:f392fc9709a3	1332	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge	189:f392fc9709a3	1333	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge	189:f392fc9709a3	1334	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
AnnaBridge	189:f392fc9709a3	1335	*/
AnnaBridge	189:f392fc9709a3	1336	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	1337	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
AnnaBridge	189:f392fc9709a3	1338	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
AnnaBridge	189:f392fc9709a3	1339	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
AnnaBridge	189:f392fc9709a3	1340	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
AnnaBridge	189:f392fc9709a3	1341
AnnaBridge	189:f392fc9709a3	1342	/**
AnnaBridge	189:f392fc9709a3	1343	* @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
AnnaBridge	189:f392fc9709a3	1344	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1345	* @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge	189:f392fc9709a3	1346	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1347	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge	189:f392fc9709a3	1348	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge	189:f392fc9709a3	1349	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge	189:f392fc9709a3	1350	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge	189:f392fc9709a3	1351	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
AnnaBridge	189:f392fc9709a3	1352	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
AnnaBridge	189:f392fc9709a3	1353	* @param __COMPARE__ specifies the Capture Compare register new value.
AnnaBridge	189:f392fc9709a3	1354	* @retval None
AnnaBridge	189:f392fc9709a3	1355	*/
AnnaBridge	189:f392fc9709a3	1356	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
AnnaBridge	189:f392fc9709a3	1357	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
AnnaBridge	189:f392fc9709a3	1358	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
AnnaBridge	189:f392fc9709a3	1359	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
AnnaBridge	189:f392fc9709a3	1360	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
AnnaBridge	189:f392fc9709a3	1361	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
AnnaBridge	189:f392fc9709a3	1362	((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
AnnaBridge	189:f392fc9709a3	1363
AnnaBridge	189:f392fc9709a3	1364	/**
AnnaBridge	189:f392fc9709a3	1365	* @brief Get the TIM Capture Compare Register value on runtime.
AnnaBridge	189:f392fc9709a3	1366	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1367	* @param __CHANNEL__ TIM Channel associated with the capture compare register
AnnaBridge	189:f392fc9709a3	1368	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1369	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
AnnaBridge	189:f392fc9709a3	1370	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
AnnaBridge	189:f392fc9709a3	1371	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
AnnaBridge	189:f392fc9709a3	1372	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
AnnaBridge	189:f392fc9709a3	1373	* @arg TIM_CHANNEL_5: get capture/compare 5 register value
AnnaBridge	189:f392fc9709a3	1374	* @arg TIM_CHANNEL_6: get capture/compare 6 register value
AnnaBridge	189:f392fc9709a3	1375	* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
AnnaBridge	189:f392fc9709a3	1376	*/
AnnaBridge	189:f392fc9709a3	1377	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	1378	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
AnnaBridge	189:f392fc9709a3	1379	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
AnnaBridge	189:f392fc9709a3	1380	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
AnnaBridge	189:f392fc9709a3	1381	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
AnnaBridge	189:f392fc9709a3	1382	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
AnnaBridge	189:f392fc9709a3	1383	((__HANDLE__)->Instance->CCR6))
AnnaBridge	189:f392fc9709a3	1384
AnnaBridge	189:f392fc9709a3	1385	/**
AnnaBridge	189:f392fc9709a3	1386	* @brief Set the TIM Output compare preload.
AnnaBridge	189:f392fc9709a3	1387	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1388	* @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge	189:f392fc9709a3	1389	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1390	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge	189:f392fc9709a3	1391	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge	189:f392fc9709a3	1392	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge	189:f392fc9709a3	1393	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge	189:f392fc9709a3	1394	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
AnnaBridge	189:f392fc9709a3	1395	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
AnnaBridge	189:f392fc9709a3	1396	* @retval None
AnnaBridge	189:f392fc9709a3	1397	*/
AnnaBridge	189:f392fc9709a3	1398	#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	1399	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1PE) :\
AnnaBridge	189:f392fc9709a3	1400	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2PE) :\
AnnaBridge	189:f392fc9709a3	1401	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3PE) :\
AnnaBridge	189:f392fc9709a3	1402	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4PE) :\
AnnaBridge	189:f392fc9709a3	1403	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 \|= TIM_CCMR3_OC5PE) :\
AnnaBridge	189:f392fc9709a3	1404	((__HANDLE__)->Instance->CCMR3 \|= TIM_CCMR3_OC6PE))
AnnaBridge	189:f392fc9709a3	1405
AnnaBridge	189:f392fc9709a3	1406	/**
AnnaBridge	189:f392fc9709a3	1407	* @brief Reset the TIM Output compare preload.
AnnaBridge	189:f392fc9709a3	1408	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1409	* @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge	189:f392fc9709a3	1410	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1411	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge	189:f392fc9709a3	1412	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge	189:f392fc9709a3	1413	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge	189:f392fc9709a3	1414	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge	189:f392fc9709a3	1415	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
AnnaBridge	189:f392fc9709a3	1416	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
AnnaBridge	189:f392fc9709a3	1417	* @retval None
AnnaBridge	189:f392fc9709a3	1418	*/
AnnaBridge	189:f392fc9709a3	1419	#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	1420	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
AnnaBridge	189:f392fc9709a3	1421	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
AnnaBridge	189:f392fc9709a3	1422	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
AnnaBridge	189:f392fc9709a3	1423	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
AnnaBridge	189:f392fc9709a3	1424	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
AnnaBridge	189:f392fc9709a3	1425	((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
AnnaBridge	189:f392fc9709a3	1426
AnnaBridge	189:f392fc9709a3	1427	/**
AnnaBridge	189:f392fc9709a3	1428	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
AnnaBridge	189:f392fc9709a3	1429	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1430	* @note When the USR bit of the TIMx_CR1 register is set, only counter
AnnaBridge	189:f392fc9709a3	1431	* overflow/underflow generates an update interrupt or DMA request (if
AnnaBridge	189:f392fc9709a3	1432	* enabled)
AnnaBridge	189:f392fc9709a3	1433	* @retval None
AnnaBridge	189:f392fc9709a3	1434	*/
AnnaBridge	189:f392fc9709a3	1435	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	1436	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
AnnaBridge	189:f392fc9709a3	1437
AnnaBridge	189:f392fc9709a3	1438	/**
AnnaBridge	189:f392fc9709a3	1439	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
AnnaBridge	189:f392fc9709a3	1440	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1441	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
AnnaBridge	189:f392fc9709a3	1442	* following events generate an update interrupt or DMA request (if
AnnaBridge	189:f392fc9709a3	1443	* enabled):
AnnaBridge	189:f392fc9709a3	1444	* _ Counter overflow underflow
AnnaBridge	189:f392fc9709a3	1445	* _ Setting the UG bit
AnnaBridge	189:f392fc9709a3	1446	* _ Update generation through the slave mode controller
AnnaBridge	189:f392fc9709a3	1447	* @retval None
AnnaBridge	189:f392fc9709a3	1448	*/
AnnaBridge	189:f392fc9709a3	1449	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	1450	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
AnnaBridge	189:f392fc9709a3	1451
AnnaBridge	189:f392fc9709a3	1452	/**
AnnaBridge	189:f392fc9709a3	1453	* @brief Set the TIM Capture x input polarity on runtime.
AnnaBridge	189:f392fc9709a3	1454	* @param __HANDLE__ TIM handle.
AnnaBridge	189:f392fc9709a3	1455	* @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge	189:f392fc9709a3	1456	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1457	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge	189:f392fc9709a3	1458	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge	189:f392fc9709a3	1459	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge	189:f392fc9709a3	1460	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge	189:f392fc9709a3	1461	* @param __POLARITY__ Polarity for TIx source
AnnaBridge	189:f392fc9709a3	1462	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
AnnaBridge	189:f392fc9709a3	1463	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
AnnaBridge	189:f392fc9709a3	1464	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
AnnaBridge	189:f392fc9709a3	1465	* @retval None
AnnaBridge	189:f392fc9709a3	1466	*/
AnnaBridge	189:f392fc9709a3	1467	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge	189:f392fc9709a3	1468	do{ \
AnnaBridge	189:f392fc9709a3	1469	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
AnnaBridge	189:f392fc9709a3	1470	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
AnnaBridge	189:f392fc9709a3	1471	}while(0)
AnnaBridge	189:f392fc9709a3	1472
AnnaBridge	189:f392fc9709a3	1473	/**
AnnaBridge	189:f392fc9709a3	1474	* @}
AnnaBridge	189:f392fc9709a3	1475	*/
AnnaBridge	189:f392fc9709a3	1476	/* End of exported macros ----------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1477
AnnaBridge	189:f392fc9709a3	1478	/* Private constants ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1479	/** @defgroup TIM_Private_Constants TIM Private Constants
AnnaBridge	189:f392fc9709a3	1480	* @{
AnnaBridge	189:f392fc9709a3	1481	*/
AnnaBridge	189:f392fc9709a3	1482	/* The counter of a timer instance is disabled only if all the CCx and CCxN
AnnaBridge	189:f392fc9709a3	1483	channels have been disabled */
AnnaBridge	189:f392fc9709a3	1484	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
AnnaBridge	189:f392fc9709a3	1485	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
AnnaBridge	189:f392fc9709a3	1486	/**
AnnaBridge	189:f392fc9709a3	1487	* @}
AnnaBridge	189:f392fc9709a3	1488	*/
AnnaBridge	189:f392fc9709a3	1489	/* End of private constants --------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1490
AnnaBridge	189:f392fc9709a3	1491	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1492	/** @defgroup TIM_Private_Macros TIM Private Macros
AnnaBridge	189:f392fc9709a3	1493	* @{
AnnaBridge	189:f392fc9709a3	1494	*/
AnnaBridge	189:f392fc9709a3	1495
AnnaBridge	189:f392fc9709a3	1496	#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
AnnaBridge	189:f392fc9709a3	1497	((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) \|\| \
AnnaBridge	189:f392fc9709a3	1498	((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
AnnaBridge	189:f392fc9709a3	1499
AnnaBridge	189:f392fc9709a3	1500	#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) \|\| \
AnnaBridge	189:f392fc9709a3	1501	((__BASE__) == TIM_DMABASE_CR2) \|\| \
AnnaBridge	189:f392fc9709a3	1502	((__BASE__) == TIM_DMABASE_SMCR) \|\| \
AnnaBridge	189:f392fc9709a3	1503	((__BASE__) == TIM_DMABASE_DIER) \|\| \
AnnaBridge	189:f392fc9709a3	1504	((__BASE__) == TIM_DMABASE_SR) \|\| \
AnnaBridge	189:f392fc9709a3	1505	((__BASE__) == TIM_DMABASE_EGR) \|\| \
AnnaBridge	189:f392fc9709a3	1506	((__BASE__) == TIM_DMABASE_CCMR1) \|\| \
AnnaBridge	189:f392fc9709a3	1507	((__BASE__) == TIM_DMABASE_CCMR2) \|\| \
AnnaBridge	189:f392fc9709a3	1508	((__BASE__) == TIM_DMABASE_CCER) \|\| \
AnnaBridge	189:f392fc9709a3	1509	((__BASE__) == TIM_DMABASE_CNT) \|\| \
AnnaBridge	189:f392fc9709a3	1510	((__BASE__) == TIM_DMABASE_PSC) \|\| \
AnnaBridge	189:f392fc9709a3	1511	((__BASE__) == TIM_DMABASE_ARR) \|\| \
AnnaBridge	189:f392fc9709a3	1512	((__BASE__) == TIM_DMABASE_RCR) \|\| \
AnnaBridge	189:f392fc9709a3	1513	((__BASE__) == TIM_DMABASE_CCR1) \|\| \
AnnaBridge	189:f392fc9709a3	1514	((__BASE__) == TIM_DMABASE_CCR2) \|\| \
AnnaBridge	189:f392fc9709a3	1515	((__BASE__) == TIM_DMABASE_CCR3) \|\| \
AnnaBridge	189:f392fc9709a3	1516	((__BASE__) == TIM_DMABASE_CCR4) \|\| \
AnnaBridge	189:f392fc9709a3	1517	((__BASE__) == TIM_DMABASE_BDTR) \|\| \
AnnaBridge	189:f392fc9709a3	1518	((__BASE__) == TIM_DMABASE_CCMR3) \|\| \
AnnaBridge	189:f392fc9709a3	1519	((__BASE__) == TIM_DMABASE_CCR5) \|\| \
AnnaBridge	189:f392fc9709a3	1520	((__BASE__) == TIM_DMABASE_CCR6) \|\| \
AnnaBridge	189:f392fc9709a3	1521	((__BASE__) == TIM_DMABASE_OR1) \|\| \
AnnaBridge	189:f392fc9709a3	1522	((__BASE__) == TIM_DMABASE_OR2) \|\| \
AnnaBridge	189:f392fc9709a3	1523	((__BASE__) == TIM_DMABASE_OR3))
AnnaBridge	189:f392fc9709a3	1524
AnnaBridge	189:f392fc9709a3	1525
AnnaBridge	189:f392fc9709a3	1526	#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
AnnaBridge	189:f392fc9709a3	1527
AnnaBridge	189:f392fc9709a3	1528
AnnaBridge	189:f392fc9709a3	1529	#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) \|\| \
AnnaBridge	189:f392fc9709a3	1530	((__MODE__) == TIM_COUNTERMODE_DOWN) \|\| \
AnnaBridge	189:f392fc9709a3	1531	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
AnnaBridge	189:f392fc9709a3	1532	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
AnnaBridge	189:f392fc9709a3	1533	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
AnnaBridge	189:f392fc9709a3	1534
AnnaBridge	189:f392fc9709a3	1535	#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) \|\| \
AnnaBridge	189:f392fc9709a3	1536	((__DIV__) == TIM_CLOCKDIVISION_DIV2) \|\| \
AnnaBridge	189:f392fc9709a3	1537	((__DIV__) == TIM_CLOCKDIVISION_DIV4))
AnnaBridge	189:f392fc9709a3	1538
AnnaBridge	189:f392fc9709a3	1539	#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) \|\| \
AnnaBridge	189:f392fc9709a3	1540	((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
AnnaBridge	189:f392fc9709a3	1541
AnnaBridge	189:f392fc9709a3	1542	#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) \|\| \
AnnaBridge	189:f392fc9709a3	1543	((__STATE__) == TIM_OCFAST_ENABLE))
AnnaBridge	189:f392fc9709a3	1544
AnnaBridge	189:f392fc9709a3	1545	#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) \|\| \
AnnaBridge	189:f392fc9709a3	1546	((__POLARITY__) == TIM_OCPOLARITY_LOW))
AnnaBridge	189:f392fc9709a3	1547
AnnaBridge	189:f392fc9709a3	1548	#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) \|\| \
AnnaBridge	189:f392fc9709a3	1549	((__POLARITY__) == TIM_OCNPOLARITY_LOW))
AnnaBridge	189:f392fc9709a3	1550
AnnaBridge	189:f392fc9709a3	1551	#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) \|\| \
AnnaBridge	189:f392fc9709a3	1552	((__STATE__) == TIM_OCIDLESTATE_RESET))
AnnaBridge	189:f392fc9709a3	1553
AnnaBridge	189:f392fc9709a3	1554	#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) \|\| \
AnnaBridge	189:f392fc9709a3	1555	((__STATE__) == TIM_OCNIDLESTATE_RESET))
AnnaBridge	189:f392fc9709a3	1556
AnnaBridge	189:f392fc9709a3	1557	#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) \|\| \
AnnaBridge	189:f392fc9709a3	1558	((__POLARITY__) == TIM_ICPOLARITY_FALLING) \|\| \
AnnaBridge	189:f392fc9709a3	1559	((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
AnnaBridge	189:f392fc9709a3	1560
AnnaBridge	189:f392fc9709a3	1561	#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) \|\| \
AnnaBridge	189:f392fc9709a3	1562	((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) \|\| \
AnnaBridge	189:f392fc9709a3	1563	((__SELECTION__) == TIM_ICSELECTION_TRC))
AnnaBridge	189:f392fc9709a3	1564
AnnaBridge	189:f392fc9709a3	1565	#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) \|\| \
AnnaBridge	189:f392fc9709a3	1566	((__PRESCALER__) == TIM_ICPSC_DIV2) \|\| \
AnnaBridge	189:f392fc9709a3	1567	((__PRESCALER__) == TIM_ICPSC_DIV4) \|\| \
AnnaBridge	189:f392fc9709a3	1568	((__PRESCALER__) == TIM_ICPSC_DIV8))
AnnaBridge	189:f392fc9709a3	1569
AnnaBridge	189:f392fc9709a3	1570	#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) \|\| \
AnnaBridge	189:f392fc9709a3	1571	((__MODE__) == TIM_OPMODE_REPETITIVE))
AnnaBridge	189:f392fc9709a3	1572
AnnaBridge	189:f392fc9709a3	1573	#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) \|\| \
AnnaBridge	189:f392fc9709a3	1574	((__MODE__) == TIM_ENCODERMODE_TI2) \|\| \
AnnaBridge	189:f392fc9709a3	1575	((__MODE__) == TIM_ENCODERMODE_TI12))
AnnaBridge	189:f392fc9709a3	1576
AnnaBridge	189:f392fc9709a3	1577	#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
AnnaBridge	189:f392fc9709a3	1578
AnnaBridge	189:f392fc9709a3	1579	#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	1580	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
AnnaBridge	189:f392fc9709a3	1581	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
AnnaBridge	189:f392fc9709a3	1582	((__CHANNEL__) == TIM_CHANNEL_4) \|\| \
AnnaBridge	189:f392fc9709a3	1583	((__CHANNEL__) == TIM_CHANNEL_5) \|\| \
AnnaBridge	189:f392fc9709a3	1584	((__CHANNEL__) == TIM_CHANNEL_6) \|\| \
AnnaBridge	189:f392fc9709a3	1585	((__CHANNEL__) == TIM_CHANNEL_ALL))
AnnaBridge	189:f392fc9709a3	1586
AnnaBridge	189:f392fc9709a3	1587	#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	1588	((__CHANNEL__) == TIM_CHANNEL_2))
AnnaBridge	189:f392fc9709a3	1589
AnnaBridge	189:f392fc9709a3	1590	#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	1591	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
AnnaBridge	189:f392fc9709a3	1592	((__CHANNEL__) == TIM_CHANNEL_3))
AnnaBridge	189:f392fc9709a3	1593
AnnaBridge	189:f392fc9709a3	1594	#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
AnnaBridge	189:f392fc9709a3	1595	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
AnnaBridge	189:f392fc9709a3	1596	((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) \|\| \
AnnaBridge	189:f392fc9709a3	1597	((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \|\| \
AnnaBridge	189:f392fc9709a3	1598	((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) \|\| \
AnnaBridge	189:f392fc9709a3	1599	((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) \|\| \
AnnaBridge	189:f392fc9709a3	1600	((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) \|\| \
AnnaBridge	189:f392fc9709a3	1601	((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \|\| \
AnnaBridge	189:f392fc9709a3	1602	((__CLOCK__) == TIM_CLOCKSOURCE_TI2) \|\| \
AnnaBridge	189:f392fc9709a3	1603	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
AnnaBridge	189:f392fc9709a3	1604
AnnaBridge	189:f392fc9709a3	1605	#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
AnnaBridge	189:f392fc9709a3	1606	((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
AnnaBridge	189:f392fc9709a3	1607	((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \|\| \
AnnaBridge	189:f392fc9709a3	1608	((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) \|\| \
AnnaBridge	189:f392fc9709a3	1609	((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
AnnaBridge	189:f392fc9709a3	1610
AnnaBridge	189:f392fc9709a3	1611	#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) \|\| \
AnnaBridge	189:f392fc9709a3	1612	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) \|\| \
AnnaBridge	189:f392fc9709a3	1613	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) \|\| \
AnnaBridge	189:f392fc9709a3	1614	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
AnnaBridge	189:f392fc9709a3	1615
AnnaBridge	189:f392fc9709a3	1616	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
AnnaBridge	189:f392fc9709a3	1617
AnnaBridge	189:f392fc9709a3	1618	#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
AnnaBridge	189:f392fc9709a3	1619	((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
AnnaBridge	189:f392fc9709a3	1620
AnnaBridge	189:f392fc9709a3	1621	#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
AnnaBridge	189:f392fc9709a3	1622	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
AnnaBridge	189:f392fc9709a3	1623	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
AnnaBridge	189:f392fc9709a3	1624	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
AnnaBridge	189:f392fc9709a3	1625
AnnaBridge	189:f392fc9709a3	1626	#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
AnnaBridge	189:f392fc9709a3	1627
AnnaBridge	189:f392fc9709a3	1628
AnnaBridge	189:f392fc9709a3	1629	#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) \|\| \
AnnaBridge	189:f392fc9709a3	1630	((__STATE__) == TIM_OSSR_DISABLE))
AnnaBridge	189:f392fc9709a3	1631
AnnaBridge	189:f392fc9709a3	1632	#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) \|\| \
AnnaBridge	189:f392fc9709a3	1633	((__STATE__) == TIM_OSSI_DISABLE))
AnnaBridge	189:f392fc9709a3	1634
AnnaBridge	189:f392fc9709a3	1635	#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) \|\| \
AnnaBridge	189:f392fc9709a3	1636	((__LEVEL__) == TIM_LOCKLEVEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	1637	((__LEVEL__) == TIM_LOCKLEVEL_2) \|\| \
AnnaBridge	189:f392fc9709a3	1638	((__LEVEL__) == TIM_LOCKLEVEL_3))
AnnaBridge	189:f392fc9709a3	1639
AnnaBridge	189:f392fc9709a3	1640	#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
AnnaBridge	189:f392fc9709a3	1641
AnnaBridge	189:f392fc9709a3	1642
AnnaBridge	189:f392fc9709a3	1643	#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) \|\| \
AnnaBridge	189:f392fc9709a3	1644	((__STATE__) == TIM_BREAK_DISABLE))
AnnaBridge	189:f392fc9709a3	1645
AnnaBridge	189:f392fc9709a3	1646	#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) \|\| \
AnnaBridge	189:f392fc9709a3	1647	((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
AnnaBridge	189:f392fc9709a3	1648
AnnaBridge	189:f392fc9709a3	1649	#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) \|\| \
AnnaBridge	189:f392fc9709a3	1650	((__STATE__) == TIM_BREAK2_DISABLE))
AnnaBridge	189:f392fc9709a3	1651
AnnaBridge	189:f392fc9709a3	1652	#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) \|\| \
AnnaBridge	189:f392fc9709a3	1653	((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
AnnaBridge	189:f392fc9709a3	1654
AnnaBridge	189:f392fc9709a3	1655	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
AnnaBridge	189:f392fc9709a3	1656	((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
AnnaBridge	189:f392fc9709a3	1657
AnnaBridge	189:f392fc9709a3	1658	#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000))
AnnaBridge	189:f392fc9709a3	1659
AnnaBridge	189:f392fc9709a3	1660	#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) \|\| \
AnnaBridge	189:f392fc9709a3	1661	((__SOURCE__) == TIM_TRGO_ENABLE) \|\| \
AnnaBridge	189:f392fc9709a3	1662	((__SOURCE__) == TIM_TRGO_UPDATE) \|\| \
AnnaBridge	189:f392fc9709a3	1663	((__SOURCE__) == TIM_TRGO_OC1) \|\| \
AnnaBridge	189:f392fc9709a3	1664	((__SOURCE__) == TIM_TRGO_OC1REF) \|\| \
AnnaBridge	189:f392fc9709a3	1665	((__SOURCE__) == TIM_TRGO_OC2REF) \|\| \
AnnaBridge	189:f392fc9709a3	1666	((__SOURCE__) == TIM_TRGO_OC3REF) \|\| \
AnnaBridge	189:f392fc9709a3	1667	((__SOURCE__) == TIM_TRGO_OC4REF))
AnnaBridge	189:f392fc9709a3	1668
AnnaBridge	189:f392fc9709a3	1669	#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) \|\| \
AnnaBridge	189:f392fc9709a3	1670	((__SOURCE__) == TIM_TRGO2_ENABLE) \|\| \
AnnaBridge	189:f392fc9709a3	1671	((__SOURCE__) == TIM_TRGO2_UPDATE) \|\| \
AnnaBridge	189:f392fc9709a3	1672	((__SOURCE__) == TIM_TRGO2_OC1) \|\| \
AnnaBridge	189:f392fc9709a3	1673	((__SOURCE__) == TIM_TRGO2_OC1REF) \|\| \
AnnaBridge	189:f392fc9709a3	1674	((__SOURCE__) == TIM_TRGO2_OC2REF) \|\| \
AnnaBridge	189:f392fc9709a3	1675	((__SOURCE__) == TIM_TRGO2_OC3REF) \|\| \
AnnaBridge	189:f392fc9709a3	1676	((__SOURCE__) == TIM_TRGO2_OC3REF) \|\| \
AnnaBridge	189:f392fc9709a3	1677	((__SOURCE__) == TIM_TRGO2_OC4REF) \|\| \
AnnaBridge	189:f392fc9709a3	1678	((__SOURCE__) == TIM_TRGO2_OC5REF) \|\| \
AnnaBridge	189:f392fc9709a3	1679	((__SOURCE__) == TIM_TRGO2_OC6REF) \|\| \
AnnaBridge	189:f392fc9709a3	1680	((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) \|\| \
AnnaBridge	189:f392fc9709a3	1681	((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) \|\| \
AnnaBridge	189:f392fc9709a3	1682	((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) \|\| \
AnnaBridge	189:f392fc9709a3	1683	((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) \|\| \
AnnaBridge	189:f392fc9709a3	1684	((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) \|\| \
AnnaBridge	189:f392fc9709a3	1685	((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
AnnaBridge	189:f392fc9709a3	1686
AnnaBridge	189:f392fc9709a3	1687	#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
AnnaBridge	189:f392fc9709a3	1688	((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
AnnaBridge	189:f392fc9709a3	1689
AnnaBridge	189:f392fc9709a3	1690	#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) \|\| \
AnnaBridge	189:f392fc9709a3	1691	((__MODE__) == TIM_SLAVEMODE_RESET) \|\| \
AnnaBridge	189:f392fc9709a3	1692	((__MODE__) == TIM_SLAVEMODE_GATED) \|\| \
AnnaBridge	189:f392fc9709a3	1693	((__MODE__) == TIM_SLAVEMODE_TRIGGER) \|\| \
AnnaBridge	189:f392fc9709a3	1694	((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) \|\| \
AnnaBridge	189:f392fc9709a3	1695	((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
AnnaBridge	189:f392fc9709a3	1696
AnnaBridge	189:f392fc9709a3	1697	#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) \|\| \
AnnaBridge	189:f392fc9709a3	1698	((__MODE__) == TIM_OCMODE_PWM2) \|\| \
AnnaBridge	189:f392fc9709a3	1699	((__MODE__) == TIM_OCMODE_COMBINED_PWM1) \|\| \
AnnaBridge	189:f392fc9709a3	1700	((__MODE__) == TIM_OCMODE_COMBINED_PWM2) \|\| \
AnnaBridge	189:f392fc9709a3	1701	((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) \|\| \
AnnaBridge	189:f392fc9709a3	1702	((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
AnnaBridge	189:f392fc9709a3	1703
AnnaBridge	189:f392fc9709a3	1704	#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) \|\| \
AnnaBridge	189:f392fc9709a3	1705	((__MODE__) == TIM_OCMODE_ACTIVE) \|\| \
AnnaBridge	189:f392fc9709a3	1706	((__MODE__) == TIM_OCMODE_INACTIVE) \|\| \
AnnaBridge	189:f392fc9709a3	1707	((__MODE__) == TIM_OCMODE_TOGGLE) \|\| \
AnnaBridge	189:f392fc9709a3	1708	((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
AnnaBridge	189:f392fc9709a3	1709	((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) \|\| \
AnnaBridge	189:f392fc9709a3	1710	((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) \|\| \
AnnaBridge	189:f392fc9709a3	1711	((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
AnnaBridge	189:f392fc9709a3	1712
AnnaBridge	189:f392fc9709a3	1713	#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
AnnaBridge	189:f392fc9709a3	1714	((__SELECTION__) == TIM_TS_ITR1) \|\| \
AnnaBridge	189:f392fc9709a3	1715	((__SELECTION__) == TIM_TS_ITR2) \|\| \
AnnaBridge	189:f392fc9709a3	1716	((__SELECTION__) == TIM_TS_ITR3) \|\| \
AnnaBridge	189:f392fc9709a3	1717	((__SELECTION__) == TIM_TS_TI1F_ED) \|\| \
AnnaBridge	189:f392fc9709a3	1718	((__SELECTION__) == TIM_TS_TI1FP1) \|\| \
AnnaBridge	189:f392fc9709a3	1719	((__SELECTION__) == TIM_TS_TI2FP2) \|\| \
AnnaBridge	189:f392fc9709a3	1720	((__SELECTION__) == TIM_TS_ETRF))
AnnaBridge	189:f392fc9709a3	1721
AnnaBridge	189:f392fc9709a3	1722	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
AnnaBridge	189:f392fc9709a3	1723	((__SELECTION__) == TIM_TS_ITR1) \|\| \
AnnaBridge	189:f392fc9709a3	1724	((__SELECTION__) == TIM_TS_ITR2) \|\| \
AnnaBridge	189:f392fc9709a3	1725	((__SELECTION__) == TIM_TS_ITR3) \|\| \
AnnaBridge	189:f392fc9709a3	1726	((__SELECTION__) == TIM_TS_NONE))
AnnaBridge	189:f392fc9709a3	1727
AnnaBridge	189:f392fc9709a3	1728
AnnaBridge	189:f392fc9709a3	1729	#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
AnnaBridge	189:f392fc9709a3	1730	((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
AnnaBridge	189:f392fc9709a3	1731	((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
AnnaBridge	189:f392fc9709a3	1732	((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
AnnaBridge	189:f392fc9709a3	1733	((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
AnnaBridge	189:f392fc9709a3	1734
AnnaBridge	189:f392fc9709a3	1735	#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
AnnaBridge	189:f392fc9709a3	1736	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
AnnaBridge	189:f392fc9709a3	1737	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
AnnaBridge	189:f392fc9709a3	1738	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
AnnaBridge	189:f392fc9709a3	1739
AnnaBridge	189:f392fc9709a3	1740	#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
AnnaBridge	189:f392fc9709a3	1741
AnnaBridge	189:f392fc9709a3	1742	#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) \|\| \
AnnaBridge	189:f392fc9709a3	1743	((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
AnnaBridge	189:f392fc9709a3	1744
AnnaBridge	189:f392fc9709a3	1745	#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
AnnaBridge	189:f392fc9709a3	1746	((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1747	((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1748	((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1749	((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1750	((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1751	((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1752	((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1753	((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1754	((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1755	((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1756	((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1757	((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1758	((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1759	((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1760	((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1761	((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	1762	((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
AnnaBridge	189:f392fc9709a3	1763
AnnaBridge	189:f392fc9709a3	1764	#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
AnnaBridge	189:f392fc9709a3	1765
AnnaBridge	189:f392fc9709a3	1766	#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF)
AnnaBridge	189:f392fc9709a3	1767
AnnaBridge	189:f392fc9709a3	1768	#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) \|\| \
AnnaBridge	189:f392fc9709a3	1769	((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) \|\| \
AnnaBridge	189:f392fc9709a3	1770	((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) \|\| \
AnnaBridge	189:f392fc9709a3	1771	((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
AnnaBridge	189:f392fc9709a3	1772
AnnaBridge	189:f392fc9709a3	1773	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge	189:f392fc9709a3	1774	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
AnnaBridge	189:f392fc9709a3	1775	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
AnnaBridge	189:f392fc9709a3	1776	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
AnnaBridge	189:f392fc9709a3	1777	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
AnnaBridge	189:f392fc9709a3	1778
AnnaBridge	189:f392fc9709a3	1779	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	1780	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
AnnaBridge	189:f392fc9709a3	1781	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
AnnaBridge	189:f392fc9709a3	1782	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
AnnaBridge	189:f392fc9709a3	1783	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
AnnaBridge	189:f392fc9709a3	1784
AnnaBridge	189:f392fc9709a3	1785	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge	189:f392fc9709a3	1786	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
AnnaBridge	189:f392fc9709a3	1787	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4)) :\
AnnaBridge	189:f392fc9709a3	1788	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8)) :\
AnnaBridge	189:f392fc9709a3	1789	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12))))
AnnaBridge	189:f392fc9709a3	1790
AnnaBridge	189:f392fc9709a3	1791	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	1792	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
AnnaBridge	189:f392fc9709a3	1793	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
AnnaBridge	189:f392fc9709a3	1794	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
AnnaBridge	189:f392fc9709a3	1795	((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P \| TIM_CCER_CC4NP)))
AnnaBridge	189:f392fc9709a3	1796
AnnaBridge	189:f392fc9709a3	1797	/**
AnnaBridge	189:f392fc9709a3	1798	* @}
AnnaBridge	189:f392fc9709a3	1799	*/
AnnaBridge	189:f392fc9709a3	1800	/* End of private macros -----------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1801
AnnaBridge	189:f392fc9709a3	1802	/* Include TIM HAL Extended module */
AnnaBridge	189:f392fc9709a3	1803	#include "stm32l4xx_hal_tim_ex.h"
AnnaBridge	189:f392fc9709a3	1804
AnnaBridge	189:f392fc9709a3	1805	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1806	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
AnnaBridge	189:f392fc9709a3	1807	* @{
AnnaBridge	189:f392fc9709a3	1808	*/
AnnaBridge	189:f392fc9709a3	1809
AnnaBridge	189:f392fc9709a3	1810	/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
AnnaBridge	189:f392fc9709a3	1811	* @brief Time Base functions
AnnaBridge	189:f392fc9709a3	1812	* @{
AnnaBridge	189:f392fc9709a3	1813	*/
AnnaBridge	189:f392fc9709a3	1814	/* Time Base functions ********************************************************/
AnnaBridge	189:f392fc9709a3	1815	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1816	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1817	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1818	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1819	/* Blocking mode: Polling */
AnnaBridge	189:f392fc9709a3	1820	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1821	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1822	/* Non-Blocking mode: Interrupt */
AnnaBridge	189:f392fc9709a3	1823	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1824	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1825	/* Non-Blocking mode: DMA */
AnnaBridge	189:f392fc9709a3	1826	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
AnnaBridge	189:f392fc9709a3	1827	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1828	/**
AnnaBridge	189:f392fc9709a3	1829	* @}
AnnaBridge	189:f392fc9709a3	1830	*/
AnnaBridge	189:f392fc9709a3	1831
AnnaBridge	189:f392fc9709a3	1832	/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
AnnaBridge	189:f392fc9709a3	1833	* @brief Time Output Compare functions
AnnaBridge	189:f392fc9709a3	1834	* @{
AnnaBridge	189:f392fc9709a3	1835	*/
AnnaBridge	189:f392fc9709a3	1836	/* Timer Output Compare functions *********************************************/
AnnaBridge	189:f392fc9709a3	1837	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1838	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1839	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1840	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1841	/* Blocking mode: Polling */
AnnaBridge	189:f392fc9709a3	1842	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1843	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1844	/* Non-Blocking mode: Interrupt */
AnnaBridge	189:f392fc9709a3	1845	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1846	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1847	/* Non-Blocking mode: DMA */
AnnaBridge	189:f392fc9709a3	1848	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
AnnaBridge	189:f392fc9709a3	1849	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1850	/**
AnnaBridge	189:f392fc9709a3	1851	* @}
AnnaBridge	189:f392fc9709a3	1852	*/
AnnaBridge	189:f392fc9709a3	1853
AnnaBridge	189:f392fc9709a3	1854	/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
AnnaBridge	189:f392fc9709a3	1855	* @brief Time PWM functions
AnnaBridge	189:f392fc9709a3	1856	* @{
AnnaBridge	189:f392fc9709a3	1857	*/
AnnaBridge	189:f392fc9709a3	1858	/* Timer PWM functions ********************************************************/
AnnaBridge	189:f392fc9709a3	1859	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1860	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1861	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1862	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1863	/* Blocking mode: Polling */
AnnaBridge	189:f392fc9709a3	1864	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1865	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1866	/* Non-Blocking mode: Interrupt */
AnnaBridge	189:f392fc9709a3	1867	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1868	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1869	/* Non-Blocking mode: DMA */
AnnaBridge	189:f392fc9709a3	1870	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
AnnaBridge	189:f392fc9709a3	1871	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1872	/**
AnnaBridge	189:f392fc9709a3	1873	* @}
AnnaBridge	189:f392fc9709a3	1874	*/
AnnaBridge	189:f392fc9709a3	1875
AnnaBridge	189:f392fc9709a3	1876	/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
AnnaBridge	189:f392fc9709a3	1877	* @brief Time Input Capture functions
AnnaBridge	189:f392fc9709a3	1878	* @{
AnnaBridge	189:f392fc9709a3	1879	*/
AnnaBridge	189:f392fc9709a3	1880	/* Timer Input Capture functions **********************************************/
AnnaBridge	189:f392fc9709a3	1881	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1882	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1883	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1884	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1885	/* Blocking mode: Polling */
AnnaBridge	189:f392fc9709a3	1886	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1887	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1888	/* Non-Blocking mode: Interrupt */
AnnaBridge	189:f392fc9709a3	1889	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1890	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1891	/* Non-Blocking mode: DMA */
AnnaBridge	189:f392fc9709a3	1892	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
AnnaBridge	189:f392fc9709a3	1893	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1894	/**
AnnaBridge	189:f392fc9709a3	1895	* @}
AnnaBridge	189:f392fc9709a3	1896	*/
AnnaBridge	189:f392fc9709a3	1897
AnnaBridge	189:f392fc9709a3	1898	/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
AnnaBridge	189:f392fc9709a3	1899	* @brief Time One Pulse functions
AnnaBridge	189:f392fc9709a3	1900	* @{
AnnaBridge	189:f392fc9709a3	1901	*/
AnnaBridge	189:f392fc9709a3	1902	/* Timer One Pulse functions **************************************************/
AnnaBridge	189:f392fc9709a3	1903	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
AnnaBridge	189:f392fc9709a3	1904	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1905	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1906	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1907	/* Blocking mode: Polling */
AnnaBridge	189:f392fc9709a3	1908	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	189:f392fc9709a3	1909	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	189:f392fc9709a3	1910	/* Non-Blocking mode: Interrupt */
AnnaBridge	189:f392fc9709a3	1911	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	189:f392fc9709a3	1912	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	189:f392fc9709a3	1913	/**
AnnaBridge	189:f392fc9709a3	1914	* @}
AnnaBridge	189:f392fc9709a3	1915	*/
AnnaBridge	189:f392fc9709a3	1916
AnnaBridge	189:f392fc9709a3	1917	/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
AnnaBridge	189:f392fc9709a3	1918	* @brief Time Encoder functions
AnnaBridge	189:f392fc9709a3	1919	* @{
AnnaBridge	189:f392fc9709a3	1920	*/
AnnaBridge	189:f392fc9709a3	1921	/* Timer Encoder functions ****************************************************/
AnnaBridge	189:f392fc9709a3	1922	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
AnnaBridge	189:f392fc9709a3	1923	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1924	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1925	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1926	/* Blocking mode: Polling */
AnnaBridge	189:f392fc9709a3	1927	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1928	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1929	/* Non-Blocking mode: Interrupt */
AnnaBridge	189:f392fc9709a3	1930	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1931	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1932	/* Non-Blocking mode: DMA */
AnnaBridge	189:f392fc9709a3	1933	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
AnnaBridge	189:f392fc9709a3	1934	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1935	/**
AnnaBridge	189:f392fc9709a3	1936	* @}
AnnaBridge	189:f392fc9709a3	1937	*/
AnnaBridge	189:f392fc9709a3	1938
AnnaBridge	189:f392fc9709a3	1939	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
AnnaBridge	189:f392fc9709a3	1940	* @brief IRQ handler management
AnnaBridge	189:f392fc9709a3	1941	* @{
AnnaBridge	189:f392fc9709a3	1942	*/
AnnaBridge	189:f392fc9709a3	1943	/* Interrupt Handler functions ***********************************************/
AnnaBridge	189:f392fc9709a3	1944	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1945	/**
AnnaBridge	189:f392fc9709a3	1946	* @}
AnnaBridge	189:f392fc9709a3	1947	*/
AnnaBridge	189:f392fc9709a3	1948
AnnaBridge	189:f392fc9709a3	1949	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
AnnaBridge	189:f392fc9709a3	1950	* @brief Peripheral Control functions
AnnaBridge	189:f392fc9709a3	1951	* @{
AnnaBridge	189:f392fc9709a3	1952	*/
AnnaBridge	189:f392fc9709a3	1953	/* Control functions *********************************************************/
AnnaBridge	189:f392fc9709a3	1954	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1955	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1956	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1957	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
AnnaBridge	189:f392fc9709a3	1958	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1959	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
AnnaBridge	189:f392fc9709a3	1960	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
AnnaBridge	189:f392fc9709a3	1961	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
AnnaBridge	189:f392fc9709a3	1962	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
AnnaBridge	189:f392fc9709a3	1963	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge	189:f392fc9709a3	1964	uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge	189:f392fc9709a3	1965	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge	189:f392fc9709a3	1966	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge	189:f392fc9709a3	1967	uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge	189:f392fc9709a3	1968	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge	189:f392fc9709a3	1969	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
AnnaBridge	189:f392fc9709a3	1970	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1971	/**
AnnaBridge	189:f392fc9709a3	1972	* @}
AnnaBridge	189:f392fc9709a3	1973	*/
AnnaBridge	189:f392fc9709a3	1974
AnnaBridge	189:f392fc9709a3	1975	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
AnnaBridge	189:f392fc9709a3	1976	* @brief TIM Callbacks functions
AnnaBridge	189:f392fc9709a3	1977	* @{
AnnaBridge	189:f392fc9709a3	1978	*/
AnnaBridge	189:f392fc9709a3	1979	/* Callback in non blocking modes (Interrupt and DMA) *************************/
AnnaBridge	189:f392fc9709a3	1980	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1981	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1982	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1983	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1984	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1985	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1986	/**
AnnaBridge	189:f392fc9709a3	1987	* @}
AnnaBridge	189:f392fc9709a3	1988	*/
AnnaBridge	189:f392fc9709a3	1989
AnnaBridge	189:f392fc9709a3	1990	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
AnnaBridge	189:f392fc9709a3	1991	* @brief Peripheral State functions
AnnaBridge	189:f392fc9709a3	1992	* @{
AnnaBridge	189:f392fc9709a3	1993	*/
AnnaBridge	189:f392fc9709a3	1994	/* Peripheral State functions ************************************************/
AnnaBridge	189:f392fc9709a3	1995	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1996	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1997	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1998	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1999	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	2000	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	2001	/**
AnnaBridge	189:f392fc9709a3	2002	* @}
AnnaBridge	189:f392fc9709a3	2003	*/
AnnaBridge	189:f392fc9709a3	2004
AnnaBridge	189:f392fc9709a3	2005	/**
AnnaBridge	189:f392fc9709a3	2006	* @}
AnnaBridge	189:f392fc9709a3	2007	*/
AnnaBridge	189:f392fc9709a3	2008	/* End of exported functions -------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	2009
AnnaBridge	189:f392fc9709a3	2010	/* Private functions----------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	2011	/** @defgroup TIM_Private_Functions TIM Private Functions
AnnaBridge	189:f392fc9709a3	2012	* @{
AnnaBridge	189:f392fc9709a3	2013	*/
AnnaBridge	189:f392fc9709a3	2014	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
AnnaBridge	189:f392fc9709a3	2015	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
AnnaBridge	189:f392fc9709a3	2016	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
AnnaBridge	189:f392fc9709a3	2017	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
AnnaBridge	189:f392fc9709a3	2018	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
AnnaBridge	189:f392fc9709a3	2019
AnnaBridge	189:f392fc9709a3	2020	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
AnnaBridge	189:f392fc9709a3	2021	void TIM_DMAError(DMA_HandleTypeDef *hdma);
AnnaBridge	189:f392fc9709a3	2022	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
AnnaBridge	189:f392fc9709a3	2023	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
AnnaBridge	189:f392fc9709a3	2024	/**
AnnaBridge	189:f392fc9709a3	2025	* @}
AnnaBridge	189:f392fc9709a3	2026	*/
AnnaBridge	189:f392fc9709a3	2027	/* End of private functions --------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	2028
AnnaBridge	189:f392fc9709a3	2029	/**
AnnaBridge	189:f392fc9709a3	2030	* @}
AnnaBridge	189:f392fc9709a3	2031	*/
AnnaBridge	189:f392fc9709a3	2032
AnnaBridge	189:f392fc9709a3	2033	/**
AnnaBridge	189:f392fc9709a3	2034	* @}
AnnaBridge	189:f392fc9709a3	2035	*/
AnnaBridge	189:f392fc9709a3	2036
AnnaBridge	189:f392fc9709a3	2037	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	2038	}
AnnaBridge	189:f392fc9709a3	2039	#endif
AnnaBridge	189:f392fc9709a3	2040
AnnaBridge	189:f392fc9709a3	2041	#endif /* __STM32L4xx_HAL_TIM_H */
AnnaBridge	189:f392fc9709a3	2042
AnnaBridge	189:f392fc9709a3	2043	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/