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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_hal_spi.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_hal_spi.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of SPI HAL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_HAL_SPI_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_HAL_SPI_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | /** @addtogroup SPI |
| AnnaBridge | 189:f392fc9709a3 | 52 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 53 | */ |
| AnnaBridge | 189:f392fc9709a3 | 54 | |
| AnnaBridge | 189:f392fc9709a3 | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 56 | /** @defgroup SPI_Exported_Types SPI Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 57 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 58 | */ |
| AnnaBridge | 189:f392fc9709a3 | 59 | |
| AnnaBridge | 189:f392fc9709a3 | 60 | /** |
| AnnaBridge | 189:f392fc9709a3 | 61 | * @brief SPI Configuration Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 62 | */ |
| AnnaBridge | 189:f392fc9709a3 | 63 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 64 | { |
| AnnaBridge | 189:f392fc9709a3 | 65 | uint32_t Mode; /*!< Specifies the SPI operating mode. |
| AnnaBridge | 189:f392fc9709a3 | 66 | This parameter can be a value of @ref SPI_Mode */ |
| AnnaBridge | 189:f392fc9709a3 | 67 | |
| AnnaBridge | 189:f392fc9709a3 | 68 | uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. |
| AnnaBridge | 189:f392fc9709a3 | 69 | This parameter can be a value of @ref SPI_Direction */ |
| AnnaBridge | 189:f392fc9709a3 | 70 | |
| AnnaBridge | 189:f392fc9709a3 | 71 | uint32_t DataSize; /*!< Specifies the SPI data size. |
| AnnaBridge | 189:f392fc9709a3 | 72 | This parameter can be a value of @ref SPI_Data_Size */ |
| AnnaBridge | 189:f392fc9709a3 | 73 | |
| AnnaBridge | 189:f392fc9709a3 | 74 | uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. |
| AnnaBridge | 189:f392fc9709a3 | 75 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
| AnnaBridge | 189:f392fc9709a3 | 76 | |
| AnnaBridge | 189:f392fc9709a3 | 77 | uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. |
| AnnaBridge | 189:f392fc9709a3 | 78 | This parameter can be a value of @ref SPI_Clock_Phase */ |
| AnnaBridge | 189:f392fc9709a3 | 79 | |
| AnnaBridge | 189:f392fc9709a3 | 80 | uint32_t NSS; /*!< Specifies whether the NSS signal is managed by |
| AnnaBridge | 189:f392fc9709a3 | 81 | hardware (NSS pin) or by software using the SSI bit. |
| AnnaBridge | 189:f392fc9709a3 | 82 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
| AnnaBridge | 189:f392fc9709a3 | 83 | |
| AnnaBridge | 189:f392fc9709a3 | 84 | uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
| AnnaBridge | 189:f392fc9709a3 | 85 | used to configure the transmit and receive SCK clock. |
| AnnaBridge | 189:f392fc9709a3 | 86 | This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| AnnaBridge | 189:f392fc9709a3 | 87 | @note The communication clock is derived from the master |
| AnnaBridge | 189:f392fc9709a3 | 88 | clock. The slave clock does not need to be set. */ |
| AnnaBridge | 189:f392fc9709a3 | 89 | |
| AnnaBridge | 189:f392fc9709a3 | 90 | uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
| AnnaBridge | 189:f392fc9709a3 | 91 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
| AnnaBridge | 189:f392fc9709a3 | 92 | |
| AnnaBridge | 189:f392fc9709a3 | 93 | uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. |
| AnnaBridge | 189:f392fc9709a3 | 94 | This parameter can be a value of @ref SPI_TI_mode */ |
| AnnaBridge | 189:f392fc9709a3 | 95 | |
| AnnaBridge | 189:f392fc9709a3 | 96 | uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. |
| AnnaBridge | 189:f392fc9709a3 | 97 | This parameter can be a value of @ref SPI_CRC_Calculation */ |
| AnnaBridge | 189:f392fc9709a3 | 98 | |
| AnnaBridge | 189:f392fc9709a3 | 99 | uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. |
| AnnaBridge | 189:f392fc9709a3 | 100 | This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ |
| AnnaBridge | 189:f392fc9709a3 | 101 | |
| AnnaBridge | 189:f392fc9709a3 | 102 | uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. |
| AnnaBridge | 189:f392fc9709a3 | 103 | CRC Length is only used with Data8 and Data16, not other data size |
| AnnaBridge | 189:f392fc9709a3 | 104 | This parameter can be a value of @ref SPI_CRC_length */ |
| AnnaBridge | 189:f392fc9709a3 | 105 | |
| AnnaBridge | 189:f392fc9709a3 | 106 | uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . |
| AnnaBridge | 189:f392fc9709a3 | 107 | This parameter can be a value of @ref SPI_NSSP_Mode |
| AnnaBridge | 189:f392fc9709a3 | 108 | This mode is activated by the NSSP bit in the SPIx_CR2 register and |
| AnnaBridge | 189:f392fc9709a3 | 109 | it takes effect only if the SPI interface is configured as Motorola SPI |
| AnnaBridge | 189:f392fc9709a3 | 110 | master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, |
| AnnaBridge | 189:f392fc9709a3 | 111 | CPOL setting is ignored).. */ |
| AnnaBridge | 189:f392fc9709a3 | 112 | } SPI_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 113 | |
| AnnaBridge | 189:f392fc9709a3 | 114 | /** |
| AnnaBridge | 189:f392fc9709a3 | 115 | * @brief HAL SPI State structure definition |
| AnnaBridge | 189:f392fc9709a3 | 116 | */ |
| AnnaBridge | 189:f392fc9709a3 | 117 | typedef enum |
| AnnaBridge | 189:f392fc9709a3 | 118 | { |
| AnnaBridge | 189:f392fc9709a3 | 119 | HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ |
| AnnaBridge | 189:f392fc9709a3 | 120 | HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 123 | HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 124 | HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 125 | HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ |
| AnnaBridge | 189:f392fc9709a3 | 126 | HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 127 | } HAL_SPI_StateTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 128 | |
| AnnaBridge | 189:f392fc9709a3 | 129 | /** |
| AnnaBridge | 189:f392fc9709a3 | 130 | * @brief SPI handle Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 131 | */ |
| AnnaBridge | 189:f392fc9709a3 | 132 | typedef struct __SPI_HandleTypeDef |
| AnnaBridge | 189:f392fc9709a3 | 133 | { |
| AnnaBridge | 189:f392fc9709a3 | 134 | SPI_TypeDef *Instance; /*!< SPI registers base address */ |
| AnnaBridge | 189:f392fc9709a3 | 135 | |
| AnnaBridge | 189:f392fc9709a3 | 136 | SPI_InitTypeDef Init; /*!< SPI communication parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | |
| AnnaBridge | 189:f392fc9709a3 | 138 | uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ |
| AnnaBridge | 189:f392fc9709a3 | 139 | |
| AnnaBridge | 189:f392fc9709a3 | 140 | uint16_t TxXferSize; /*!< SPI Tx Transfer size */ |
| AnnaBridge | 189:f392fc9709a3 | 141 | |
| AnnaBridge | 189:f392fc9709a3 | 142 | __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ |
| AnnaBridge | 189:f392fc9709a3 | 143 | |
| AnnaBridge | 189:f392fc9709a3 | 144 | uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ |
| AnnaBridge | 189:f392fc9709a3 | 145 | |
| AnnaBridge | 189:f392fc9709a3 | 146 | uint16_t RxXferSize; /*!< SPI Rx Transfer size */ |
| AnnaBridge | 189:f392fc9709a3 | 147 | |
| AnnaBridge | 189:f392fc9709a3 | 148 | __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ |
| AnnaBridge | 189:f392fc9709a3 | 149 | |
| AnnaBridge | 189:f392fc9709a3 | 150 | uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ |
| AnnaBridge | 189:f392fc9709a3 | 151 | |
| AnnaBridge | 189:f392fc9709a3 | 152 | void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ |
| AnnaBridge | 189:f392fc9709a3 | 153 | |
| AnnaBridge | 189:f392fc9709a3 | 154 | void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ |
| AnnaBridge | 189:f392fc9709a3 | 155 | |
| AnnaBridge | 189:f392fc9709a3 | 156 | DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 157 | |
| AnnaBridge | 189:f392fc9709a3 | 158 | DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 159 | |
| AnnaBridge | 189:f392fc9709a3 | 160 | HAL_LockTypeDef Lock; /*!< Locking object */ |
| AnnaBridge | 189:f392fc9709a3 | 161 | |
| AnnaBridge | 189:f392fc9709a3 | 162 | __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ |
| AnnaBridge | 189:f392fc9709a3 | 163 | |
| AnnaBridge | 189:f392fc9709a3 | 164 | __IO uint32_t ErrorCode; /*!< SPI Error code */ |
| AnnaBridge | 189:f392fc9709a3 | 165 | |
| AnnaBridge | 189:f392fc9709a3 | 166 | } SPI_HandleTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 167 | |
| AnnaBridge | 189:f392fc9709a3 | 168 | /** |
| AnnaBridge | 189:f392fc9709a3 | 169 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 170 | */ |
| AnnaBridge | 189:f392fc9709a3 | 171 | |
| AnnaBridge | 189:f392fc9709a3 | 172 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 173 | /** @defgroup SPI_Exported_Constants SPI Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 174 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 175 | */ |
| AnnaBridge | 189:f392fc9709a3 | 176 | |
| AnnaBridge | 189:f392fc9709a3 | 177 | /** @defgroup SPI_Error_Code SPI Error Code |
| AnnaBridge | 189:f392fc9709a3 | 178 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 179 | */ |
| AnnaBridge | 189:f392fc9709a3 | 180 | #define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ |
| AnnaBridge | 189:f392fc9709a3 | 181 | #define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | #define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ |
| AnnaBridge | 189:f392fc9709a3 | 183 | #define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ |
| AnnaBridge | 189:f392fc9709a3 | 184 | #define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ |
| AnnaBridge | 189:f392fc9709a3 | 185 | #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ |
| AnnaBridge | 189:f392fc9709a3 | 186 | #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ |
| AnnaBridge | 189:f392fc9709a3 | 187 | #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ |
| AnnaBridge | 189:f392fc9709a3 | 188 | /** |
| AnnaBridge | 189:f392fc9709a3 | 189 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 190 | */ |
| AnnaBridge | 189:f392fc9709a3 | 191 | |
| AnnaBridge | 189:f392fc9709a3 | 192 | /** @defgroup SPI_Mode SPI Mode |
| AnnaBridge | 189:f392fc9709a3 | 193 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 194 | */ |
| AnnaBridge | 189:f392fc9709a3 | 195 | #define SPI_MODE_SLAVE (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 196 | #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
| AnnaBridge | 189:f392fc9709a3 | 197 | /** |
| AnnaBridge | 189:f392fc9709a3 | 198 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 199 | */ |
| AnnaBridge | 189:f392fc9709a3 | 200 | |
| AnnaBridge | 189:f392fc9709a3 | 201 | /** @defgroup SPI_Direction SPI Direction Mode |
| AnnaBridge | 189:f392fc9709a3 | 202 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 203 | */ |
| AnnaBridge | 189:f392fc9709a3 | 204 | #define SPI_DIRECTION_2LINES (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 205 | #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
| AnnaBridge | 189:f392fc9709a3 | 206 | #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
| AnnaBridge | 189:f392fc9709a3 | 207 | /** |
| AnnaBridge | 189:f392fc9709a3 | 208 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 209 | */ |
| AnnaBridge | 189:f392fc9709a3 | 210 | |
| AnnaBridge | 189:f392fc9709a3 | 211 | /** @defgroup SPI_Data_Size SPI Data Size |
| AnnaBridge | 189:f392fc9709a3 | 212 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 213 | */ |
| AnnaBridge | 189:f392fc9709a3 | 214 | #define SPI_DATASIZE_4BIT (0x00000300U) |
| AnnaBridge | 189:f392fc9709a3 | 215 | #define SPI_DATASIZE_5BIT (0x00000400U) |
| AnnaBridge | 189:f392fc9709a3 | 216 | #define SPI_DATASIZE_6BIT (0x00000500U) |
| AnnaBridge | 189:f392fc9709a3 | 217 | #define SPI_DATASIZE_7BIT (0x00000600U) |
| AnnaBridge | 189:f392fc9709a3 | 218 | #define SPI_DATASIZE_8BIT (0x00000700U) |
| AnnaBridge | 189:f392fc9709a3 | 219 | #define SPI_DATASIZE_9BIT (0x00000800U) |
| AnnaBridge | 189:f392fc9709a3 | 220 | #define SPI_DATASIZE_10BIT (0x00000900U) |
| AnnaBridge | 189:f392fc9709a3 | 221 | #define SPI_DATASIZE_11BIT (0x00000A00U) |
| AnnaBridge | 189:f392fc9709a3 | 222 | #define SPI_DATASIZE_12BIT (0x00000B00U) |
| AnnaBridge | 189:f392fc9709a3 | 223 | #define SPI_DATASIZE_13BIT (0x00000C00U) |
| AnnaBridge | 189:f392fc9709a3 | 224 | #define SPI_DATASIZE_14BIT (0x00000D00U) |
| AnnaBridge | 189:f392fc9709a3 | 225 | #define SPI_DATASIZE_15BIT (0x00000E00U) |
| AnnaBridge | 189:f392fc9709a3 | 226 | #define SPI_DATASIZE_16BIT (0x00000F00U) |
| AnnaBridge | 189:f392fc9709a3 | 227 | /** |
| AnnaBridge | 189:f392fc9709a3 | 228 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 229 | */ |
| AnnaBridge | 189:f392fc9709a3 | 230 | |
| AnnaBridge | 189:f392fc9709a3 | 231 | /** @defgroup SPI_Clock_Polarity SPI Clock Polarity |
| AnnaBridge | 189:f392fc9709a3 | 232 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 233 | */ |
| AnnaBridge | 189:f392fc9709a3 | 234 | #define SPI_POLARITY_LOW (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 235 | #define SPI_POLARITY_HIGH SPI_CR1_CPOL |
| AnnaBridge | 189:f392fc9709a3 | 236 | /** |
| AnnaBridge | 189:f392fc9709a3 | 237 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 238 | */ |
| AnnaBridge | 189:f392fc9709a3 | 239 | |
| AnnaBridge | 189:f392fc9709a3 | 240 | /** @defgroup SPI_Clock_Phase SPI Clock Phase |
| AnnaBridge | 189:f392fc9709a3 | 241 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 242 | */ |
| AnnaBridge | 189:f392fc9709a3 | 243 | #define SPI_PHASE_1EDGE (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 244 | #define SPI_PHASE_2EDGE SPI_CR1_CPHA |
| AnnaBridge | 189:f392fc9709a3 | 245 | /** |
| AnnaBridge | 189:f392fc9709a3 | 246 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 247 | */ |
| AnnaBridge | 189:f392fc9709a3 | 248 | |
| AnnaBridge | 189:f392fc9709a3 | 249 | /** @defgroup SPI_Slave_Select_management SPI Slave Select Management |
| AnnaBridge | 189:f392fc9709a3 | 250 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 251 | */ |
| AnnaBridge | 189:f392fc9709a3 | 252 | #define SPI_NSS_SOFT SPI_CR1_SSM |
| AnnaBridge | 189:f392fc9709a3 | 253 | #define SPI_NSS_HARD_INPUT (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 254 | #define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) |
| AnnaBridge | 189:f392fc9709a3 | 255 | /** |
| AnnaBridge | 189:f392fc9709a3 | 256 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 257 | */ |
| AnnaBridge | 189:f392fc9709a3 | 258 | |
| AnnaBridge | 189:f392fc9709a3 | 259 | /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode |
| AnnaBridge | 189:f392fc9709a3 | 260 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 261 | */ |
| AnnaBridge | 189:f392fc9709a3 | 262 | #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP |
| AnnaBridge | 189:f392fc9709a3 | 263 | #define SPI_NSS_PULSE_DISABLE (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 264 | /** |
| AnnaBridge | 189:f392fc9709a3 | 265 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 266 | */ |
| AnnaBridge | 189:f392fc9709a3 | 267 | |
| AnnaBridge | 189:f392fc9709a3 | 268 | /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler |
| AnnaBridge | 189:f392fc9709a3 | 269 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 270 | */ |
| AnnaBridge | 189:f392fc9709a3 | 271 | #define SPI_BAUDRATEPRESCALER_2 (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 272 | #define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) |
| AnnaBridge | 189:f392fc9709a3 | 273 | #define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) |
| AnnaBridge | 189:f392fc9709a3 | 274 | #define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) |
| AnnaBridge | 189:f392fc9709a3 | 275 | #define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) |
| AnnaBridge | 189:f392fc9709a3 | 276 | #define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) |
| AnnaBridge | 189:f392fc9709a3 | 277 | #define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) |
| AnnaBridge | 189:f392fc9709a3 | 278 | #define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) |
| AnnaBridge | 189:f392fc9709a3 | 279 | /** |
| AnnaBridge | 189:f392fc9709a3 | 280 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 281 | */ |
| AnnaBridge | 189:f392fc9709a3 | 282 | |
| AnnaBridge | 189:f392fc9709a3 | 283 | /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission |
| AnnaBridge | 189:f392fc9709a3 | 284 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 285 | */ |
| AnnaBridge | 189:f392fc9709a3 | 286 | #define SPI_FIRSTBIT_MSB (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 287 | #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
| AnnaBridge | 189:f392fc9709a3 | 288 | /** |
| AnnaBridge | 189:f392fc9709a3 | 289 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 290 | */ |
| AnnaBridge | 189:f392fc9709a3 | 291 | |
| AnnaBridge | 189:f392fc9709a3 | 292 | /** @defgroup SPI_TI_mode SPI TI Mode |
| AnnaBridge | 189:f392fc9709a3 | 293 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 294 | */ |
| AnnaBridge | 189:f392fc9709a3 | 295 | #define SPI_TIMODE_DISABLE (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 296 | #define SPI_TIMODE_ENABLE SPI_CR2_FRF |
| AnnaBridge | 189:f392fc9709a3 | 297 | /** |
| AnnaBridge | 189:f392fc9709a3 | 298 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 299 | */ |
| AnnaBridge | 189:f392fc9709a3 | 300 | |
| AnnaBridge | 189:f392fc9709a3 | 301 | /** @defgroup SPI_CRC_Calculation SPI CRC Calculation |
| AnnaBridge | 189:f392fc9709a3 | 302 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 303 | */ |
| AnnaBridge | 189:f392fc9709a3 | 304 | #define SPI_CRCCALCULATION_DISABLE (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 305 | #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
| AnnaBridge | 189:f392fc9709a3 | 306 | /** |
| AnnaBridge | 189:f392fc9709a3 | 307 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 308 | */ |
| AnnaBridge | 189:f392fc9709a3 | 309 | |
| AnnaBridge | 189:f392fc9709a3 | 310 | /** @defgroup SPI_CRC_length SPI CRC Length |
| AnnaBridge | 189:f392fc9709a3 | 311 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 312 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 313 | * SPI_CRC_LENGTH_DATASIZE: aligned with the data size |
| AnnaBridge | 189:f392fc9709a3 | 314 | * SPI_CRC_LENGTH_8BIT : CRC 8bit |
| AnnaBridge | 189:f392fc9709a3 | 315 | * SPI_CRC_LENGTH_16BIT : CRC 16bit |
| AnnaBridge | 189:f392fc9709a3 | 316 | */ |
| AnnaBridge | 189:f392fc9709a3 | 317 | #define SPI_CRC_LENGTH_DATASIZE (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 318 | #define SPI_CRC_LENGTH_8BIT (0x00000001U) |
| AnnaBridge | 189:f392fc9709a3 | 319 | #define SPI_CRC_LENGTH_16BIT (0x00000002U) |
| AnnaBridge | 189:f392fc9709a3 | 320 | /** |
| AnnaBridge | 189:f392fc9709a3 | 321 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 322 | */ |
| AnnaBridge | 189:f392fc9709a3 | 323 | |
| AnnaBridge | 189:f392fc9709a3 | 324 | /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold |
| AnnaBridge | 189:f392fc9709a3 | 325 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 326 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 327 | * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : |
| AnnaBridge | 189:f392fc9709a3 | 328 | * RXNE event is generated if the FIFO |
| AnnaBridge | 189:f392fc9709a3 | 329 | * level is greater or equal to 1/2(16-bits). |
| AnnaBridge | 189:f392fc9709a3 | 330 | * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO |
| AnnaBridge | 189:f392fc9709a3 | 331 | * level is greater or equal to 1/4(8 bits). */ |
| AnnaBridge | 189:f392fc9709a3 | 332 | #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH |
| AnnaBridge | 189:f392fc9709a3 | 333 | #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH |
| AnnaBridge | 189:f392fc9709a3 | 334 | #define SPI_RXFIFO_THRESHOLD_HF (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 335 | |
| AnnaBridge | 189:f392fc9709a3 | 336 | /** |
| AnnaBridge | 189:f392fc9709a3 | 337 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 338 | */ |
| AnnaBridge | 189:f392fc9709a3 | 339 | |
| AnnaBridge | 189:f392fc9709a3 | 340 | /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition |
| AnnaBridge | 189:f392fc9709a3 | 341 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 342 | */ |
| AnnaBridge | 189:f392fc9709a3 | 343 | #define SPI_IT_TXE SPI_CR2_TXEIE |
| AnnaBridge | 189:f392fc9709a3 | 344 | #define SPI_IT_RXNE SPI_CR2_RXNEIE |
| AnnaBridge | 189:f392fc9709a3 | 345 | #define SPI_IT_ERR SPI_CR2_ERRIE |
| AnnaBridge | 189:f392fc9709a3 | 346 | /** |
| AnnaBridge | 189:f392fc9709a3 | 347 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 348 | */ |
| AnnaBridge | 189:f392fc9709a3 | 349 | |
| AnnaBridge | 189:f392fc9709a3 | 350 | /** @defgroup SPI_Flags_definition SPI Flags Definition |
| AnnaBridge | 189:f392fc9709a3 | 351 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 352 | */ |
| AnnaBridge | 189:f392fc9709a3 | 353 | #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ |
| AnnaBridge | 189:f392fc9709a3 | 354 | #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ |
| AnnaBridge | 189:f392fc9709a3 | 355 | #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ |
| AnnaBridge | 189:f392fc9709a3 | 356 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ |
| AnnaBridge | 189:f392fc9709a3 | 357 | #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ |
| AnnaBridge | 189:f392fc9709a3 | 358 | #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ |
| AnnaBridge | 189:f392fc9709a3 | 359 | #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ |
| AnnaBridge | 189:f392fc9709a3 | 360 | #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ |
| AnnaBridge | 189:f392fc9709a3 | 361 | #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ |
| AnnaBridge | 189:f392fc9709a3 | 362 | /** |
| AnnaBridge | 189:f392fc9709a3 | 363 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 364 | */ |
| AnnaBridge | 189:f392fc9709a3 | 365 | |
| AnnaBridge | 189:f392fc9709a3 | 366 | /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level |
| AnnaBridge | 189:f392fc9709a3 | 367 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 368 | */ |
| AnnaBridge | 189:f392fc9709a3 | 369 | #define SPI_FTLVL_EMPTY (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 370 | #define SPI_FTLVL_QUARTER_FULL (0x00000800U) |
| AnnaBridge | 189:f392fc9709a3 | 371 | #define SPI_FTLVL_HALF_FULL (0x00001000U) |
| AnnaBridge | 189:f392fc9709a3 | 372 | #define SPI_FTLVL_FULL (0x00001800U) |
| AnnaBridge | 189:f392fc9709a3 | 373 | |
| AnnaBridge | 189:f392fc9709a3 | 374 | /** |
| AnnaBridge | 189:f392fc9709a3 | 375 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 376 | */ |
| AnnaBridge | 189:f392fc9709a3 | 377 | |
| AnnaBridge | 189:f392fc9709a3 | 378 | /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level |
| AnnaBridge | 189:f392fc9709a3 | 379 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 380 | */ |
| AnnaBridge | 189:f392fc9709a3 | 381 | #define SPI_FRLVL_EMPTY (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 382 | #define SPI_FRLVL_QUARTER_FULL (0x00000200U) |
| AnnaBridge | 189:f392fc9709a3 | 383 | #define SPI_FRLVL_HALF_FULL (0x00000400U) |
| AnnaBridge | 189:f392fc9709a3 | 384 | #define SPI_FRLVL_FULL (0x00000600U) |
| AnnaBridge | 189:f392fc9709a3 | 385 | /** |
| AnnaBridge | 189:f392fc9709a3 | 386 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 387 | */ |
| AnnaBridge | 189:f392fc9709a3 | 388 | |
| AnnaBridge | 189:f392fc9709a3 | 389 | /** |
| AnnaBridge | 189:f392fc9709a3 | 390 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 391 | */ |
| AnnaBridge | 189:f392fc9709a3 | 392 | |
| AnnaBridge | 189:f392fc9709a3 | 393 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 394 | /** @defgroup SPI_Exported_Macros SPI Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 395 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 396 | */ |
| AnnaBridge | 189:f392fc9709a3 | 397 | |
| AnnaBridge | 189:f392fc9709a3 | 398 | /** @brief Reset SPI handle state. |
| AnnaBridge | 189:f392fc9709a3 | 399 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 400 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 401 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 402 | */ |
| AnnaBridge | 189:f392fc9709a3 | 403 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
| AnnaBridge | 189:f392fc9709a3 | 404 | |
| AnnaBridge | 189:f392fc9709a3 | 405 | /** @brief Enable the specified SPI interrupts. |
| AnnaBridge | 189:f392fc9709a3 | 406 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 407 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 408 | * @param __INTERRUPT__ specifies the interrupt source to enable. |
| AnnaBridge | 189:f392fc9709a3 | 409 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 410 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 411 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 412 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 413 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 414 | */ |
| AnnaBridge | 189:f392fc9709a3 | 415 | #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 416 | |
| AnnaBridge | 189:f392fc9709a3 | 417 | /** @brief Disable the specified SPI interrupts. |
| AnnaBridge | 189:f392fc9709a3 | 418 | * @param __HANDLE__ specifies the SPI handle. |
| AnnaBridge | 189:f392fc9709a3 | 419 | * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 420 | * @param __INTERRUPT__ specifies the interrupt source to disable. |
| AnnaBridge | 189:f392fc9709a3 | 421 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 422 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 423 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 424 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 425 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 426 | */ |
| AnnaBridge | 189:f392fc9709a3 | 427 | #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 428 | |
| AnnaBridge | 189:f392fc9709a3 | 429 | /** @brief Check whether the specified SPI interrupt source is enabled or not. |
| AnnaBridge | 189:f392fc9709a3 | 430 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 431 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 432 | * @param __INTERRUPT__ specifies the SPI interrupt source to check. |
| AnnaBridge | 189:f392fc9709a3 | 433 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 434 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 435 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 436 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 437 | * @retval The new state of __IT__ (TRUE or FALSE). |
| AnnaBridge | 189:f392fc9709a3 | 438 | */ |
| AnnaBridge | 189:f392fc9709a3 | 439 | #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| AnnaBridge | 189:f392fc9709a3 | 440 | |
| AnnaBridge | 189:f392fc9709a3 | 441 | /** @brief Check whether the specified SPI flag is set or not. |
| AnnaBridge | 189:f392fc9709a3 | 442 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 443 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 444 | * @param __FLAG__ specifies the flag to check. |
| AnnaBridge | 189:f392fc9709a3 | 445 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 446 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
| AnnaBridge | 189:f392fc9709a3 | 447 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
| AnnaBridge | 189:f392fc9709a3 | 448 | * @arg SPI_FLAG_CRCERR: CRC error flag |
| AnnaBridge | 189:f392fc9709a3 | 449 | * @arg SPI_FLAG_MODF: Mode fault flag |
| AnnaBridge | 189:f392fc9709a3 | 450 | * @arg SPI_FLAG_OVR: Overrun flag |
| AnnaBridge | 189:f392fc9709a3 | 451 | * @arg SPI_FLAG_BSY: Busy flag |
| AnnaBridge | 189:f392fc9709a3 | 452 | * @arg SPI_FLAG_FRE: Frame format error flag |
| AnnaBridge | 189:f392fc9709a3 | 453 | * @arg SPI_FLAG_FTLVL: SPI fifo transmission level |
| AnnaBridge | 189:f392fc9709a3 | 454 | * @arg SPI_FLAG_FRLVL: SPI fifo reception level |
| AnnaBridge | 189:f392fc9709a3 | 455 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 189:f392fc9709a3 | 456 | */ |
| AnnaBridge | 189:f392fc9709a3 | 457 | #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 189:f392fc9709a3 | 458 | |
| AnnaBridge | 189:f392fc9709a3 | 459 | /** @brief Clear the SPI CRCERR pending flag. |
| AnnaBridge | 189:f392fc9709a3 | 460 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 461 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 462 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 463 | */ |
| AnnaBridge | 189:f392fc9709a3 | 464 | #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) |
| AnnaBridge | 189:f392fc9709a3 | 465 | |
| AnnaBridge | 189:f392fc9709a3 | 466 | /** @brief Clear the SPI MODF pending flag. |
| AnnaBridge | 189:f392fc9709a3 | 467 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 468 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 469 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 470 | */ |
| AnnaBridge | 189:f392fc9709a3 | 471 | #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ |
| AnnaBridge | 189:f392fc9709a3 | 472 | do{ \ |
| AnnaBridge | 189:f392fc9709a3 | 473 | __IO uint32_t tmpreg_modf = 0x00U; \ |
| AnnaBridge | 189:f392fc9709a3 | 474 | tmpreg_modf = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 189:f392fc9709a3 | 475 | CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ |
| AnnaBridge | 189:f392fc9709a3 | 476 | UNUSED(tmpreg_modf); \ |
| AnnaBridge | 189:f392fc9709a3 | 477 | } while(0U) |
| AnnaBridge | 189:f392fc9709a3 | 478 | |
| AnnaBridge | 189:f392fc9709a3 | 479 | /** @brief Clear the SPI OVR pending flag. |
| AnnaBridge | 189:f392fc9709a3 | 480 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 481 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 482 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 483 | */ |
| AnnaBridge | 189:f392fc9709a3 | 484 | #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ |
| AnnaBridge | 189:f392fc9709a3 | 485 | do{ \ |
| AnnaBridge | 189:f392fc9709a3 | 486 | __IO uint32_t tmpreg_ovr = 0x00U; \ |
| AnnaBridge | 189:f392fc9709a3 | 487 | tmpreg_ovr = (__HANDLE__)->Instance->DR; \ |
| AnnaBridge | 189:f392fc9709a3 | 488 | tmpreg_ovr = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 189:f392fc9709a3 | 489 | UNUSED(tmpreg_ovr); \ |
| AnnaBridge | 189:f392fc9709a3 | 490 | } while(0U) |
| AnnaBridge | 189:f392fc9709a3 | 491 | |
| AnnaBridge | 189:f392fc9709a3 | 492 | /** @brief Clear the SPI FRE pending flag. |
| AnnaBridge | 189:f392fc9709a3 | 493 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 494 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 495 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 496 | */ |
| AnnaBridge | 189:f392fc9709a3 | 497 | #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ |
| AnnaBridge | 189:f392fc9709a3 | 498 | do{ \ |
| AnnaBridge | 189:f392fc9709a3 | 499 | __IO uint32_t tmpreg_fre = 0x00U; \ |
| AnnaBridge | 189:f392fc9709a3 | 500 | tmpreg_fre = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 189:f392fc9709a3 | 501 | UNUSED(tmpreg_fre); \ |
| AnnaBridge | 189:f392fc9709a3 | 502 | }while(0U) |
| AnnaBridge | 189:f392fc9709a3 | 503 | |
| AnnaBridge | 189:f392fc9709a3 | 504 | /** @brief Enable the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 505 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 506 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 507 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 508 | */ |
| AnnaBridge | 189:f392fc9709a3 | 509 | #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
| AnnaBridge | 189:f392fc9709a3 | 510 | |
| AnnaBridge | 189:f392fc9709a3 | 511 | /** @brief Disable the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 512 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 513 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 514 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 515 | */ |
| AnnaBridge | 189:f392fc9709a3 | 516 | #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
| AnnaBridge | 189:f392fc9709a3 | 517 | |
| AnnaBridge | 189:f392fc9709a3 | 518 | /** |
| AnnaBridge | 189:f392fc9709a3 | 519 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 520 | */ |
| AnnaBridge | 189:f392fc9709a3 | 521 | |
| AnnaBridge | 189:f392fc9709a3 | 522 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 523 | /** @defgroup SPI_Private_Macros SPI Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 524 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 525 | */ |
| AnnaBridge | 189:f392fc9709a3 | 526 | |
| AnnaBridge | 189:f392fc9709a3 | 527 | /** @brief Set the SPI transmit-only mode. |
| AnnaBridge | 189:f392fc9709a3 | 528 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 529 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 530 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 531 | */ |
| AnnaBridge | 189:f392fc9709a3 | 532 | #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
| AnnaBridge | 189:f392fc9709a3 | 533 | |
| AnnaBridge | 189:f392fc9709a3 | 534 | /** @brief Set the SPI receive-only mode. |
| AnnaBridge | 189:f392fc9709a3 | 535 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 536 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 537 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 538 | */ |
| AnnaBridge | 189:f392fc9709a3 | 539 | #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
| AnnaBridge | 189:f392fc9709a3 | 540 | |
| AnnaBridge | 189:f392fc9709a3 | 541 | /** @brief Reset the CRC calculation of the SPI. |
| AnnaBridge | 189:f392fc9709a3 | 542 | * @param __HANDLE__ specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 543 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 544 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 545 | */ |
| AnnaBridge | 189:f392fc9709a3 | 546 | #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 547 | SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) |
| AnnaBridge | 189:f392fc9709a3 | 548 | |
| AnnaBridge | 189:f392fc9709a3 | 549 | /** @brief Checks if SPI Mode parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 550 | * @param __MODE__ specifies the SPI Mode. |
| AnnaBridge | 189:f392fc9709a3 | 551 | * This parameter can be a value of @ref SPI_Mode |
| AnnaBridge | 189:f392fc9709a3 | 552 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 553 | */ |
| AnnaBridge | 189:f392fc9709a3 | 554 | #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 555 | ((__MODE__) == SPI_MODE_MASTER)) |
| AnnaBridge | 189:f392fc9709a3 | 556 | |
| AnnaBridge | 189:f392fc9709a3 | 557 | /** @brief Checks if SPI Direction Mode parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 558 | * @param __MODE__ specifies the SPI Direction Mode. |
| AnnaBridge | 189:f392fc9709a3 | 559 | * This parameter can be a value of @ref SPI_Direction |
| AnnaBridge | 189:f392fc9709a3 | 560 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 561 | */ |
| AnnaBridge | 189:f392fc9709a3 | 562 | #define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 563 | ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ |
| AnnaBridge | 189:f392fc9709a3 | 564 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
| AnnaBridge | 189:f392fc9709a3 | 565 | |
| AnnaBridge | 189:f392fc9709a3 | 566 | /** @brief Checks if SPI Direction Mode parameter is 2 lines. |
| AnnaBridge | 189:f392fc9709a3 | 567 | * @param __MODE__ specifies the SPI Direction Mode. |
| AnnaBridge | 189:f392fc9709a3 | 568 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 569 | */ |
| AnnaBridge | 189:f392fc9709a3 | 570 | #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) |
| AnnaBridge | 189:f392fc9709a3 | 571 | |
| AnnaBridge | 189:f392fc9709a3 | 572 | /** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. |
| AnnaBridge | 189:f392fc9709a3 | 573 | * @param __MODE__ specifies the SPI Direction Mode. |
| AnnaBridge | 189:f392fc9709a3 | 574 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 575 | */ |
| AnnaBridge | 189:f392fc9709a3 | 576 | #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 577 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
| AnnaBridge | 189:f392fc9709a3 | 578 | |
| AnnaBridge | 189:f392fc9709a3 | 579 | /** @brief Checks if SPI Data Size parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 580 | * @param __DATASIZE__ specifies the SPI Data Size. |
| AnnaBridge | 189:f392fc9709a3 | 581 | * This parameter can be a value of @ref SPI_Data_Size |
| AnnaBridge | 189:f392fc9709a3 | 582 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 583 | */ |
| AnnaBridge | 189:f392fc9709a3 | 584 | #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 585 | ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 586 | ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 587 | ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 588 | ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 589 | ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 590 | ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 591 | ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 592 | ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 593 | ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 594 | ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 595 | ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 596 | ((__DATASIZE__) == SPI_DATASIZE_4BIT)) |
| AnnaBridge | 189:f392fc9709a3 | 597 | |
| AnnaBridge | 189:f392fc9709a3 | 598 | /** @brief Checks if SPI Serial clock steady state parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 599 | * @param __CPOL__ specifies the SPI serial clock steady state. |
| AnnaBridge | 189:f392fc9709a3 | 600 | * This parameter can be a value of @ref SPI_Clock_Polarity |
| AnnaBridge | 189:f392fc9709a3 | 601 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 602 | */ |
| AnnaBridge | 189:f392fc9709a3 | 603 | #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ |
| AnnaBridge | 189:f392fc9709a3 | 604 | ((__CPOL__) == SPI_POLARITY_HIGH)) |
| AnnaBridge | 189:f392fc9709a3 | 605 | |
| AnnaBridge | 189:f392fc9709a3 | 606 | /** @brief Checks if SPI Clock Phase parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 607 | * @param __CPHA__ specifies the SPI Clock Phase. |
| AnnaBridge | 189:f392fc9709a3 | 608 | * This parameter can be a value of @ref SPI_Clock_Phase |
| AnnaBridge | 189:f392fc9709a3 | 609 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 610 | */ |
| AnnaBridge | 189:f392fc9709a3 | 611 | #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 612 | ((__CPHA__) == SPI_PHASE_2EDGE)) |
| AnnaBridge | 189:f392fc9709a3 | 613 | |
| AnnaBridge | 189:f392fc9709a3 | 614 | /** @brief Checks if SPI Slave Select parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 615 | * @param __NSS__ specifies the SPI Slave Slelect management parameter. |
| AnnaBridge | 189:f392fc9709a3 | 616 | * This parameter can be a value of @ref SPI_Slave_Select_management |
| AnnaBridge | 189:f392fc9709a3 | 617 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 618 | */ |
| AnnaBridge | 189:f392fc9709a3 | 619 | #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 620 | ((__NSS__) == SPI_NSS_HARD_INPUT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 621 | ((__NSS__) == SPI_NSS_HARD_OUTPUT)) |
| AnnaBridge | 189:f392fc9709a3 | 622 | |
| AnnaBridge | 189:f392fc9709a3 | 623 | /** @brief Checks if SPI NSS Pulse parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 624 | * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. |
| AnnaBridge | 189:f392fc9709a3 | 625 | * This parameter can be a value of @ref SPI_NSSP_Mode |
| AnnaBridge | 189:f392fc9709a3 | 626 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 627 | */ |
| AnnaBridge | 189:f392fc9709a3 | 628 | #define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 629 | ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 630 | |
| AnnaBridge | 189:f392fc9709a3 | 631 | /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 632 | * @param __PRESCALER__ specifies the SPI Baudrate prescaler. |
| AnnaBridge | 189:f392fc9709a3 | 633 | * This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| AnnaBridge | 189:f392fc9709a3 | 634 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 635 | */ |
| AnnaBridge | 189:f392fc9709a3 | 636 | #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 637 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 638 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 639 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ |
| AnnaBridge | 189:f392fc9709a3 | 640 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ |
| AnnaBridge | 189:f392fc9709a3 | 641 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ |
| AnnaBridge | 189:f392fc9709a3 | 642 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ |
| AnnaBridge | 189:f392fc9709a3 | 643 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) |
| AnnaBridge | 189:f392fc9709a3 | 644 | |
| AnnaBridge | 189:f392fc9709a3 | 645 | /** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 646 | * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). |
| AnnaBridge | 189:f392fc9709a3 | 647 | * This parameter can be a value of @ref SPI_MSB_LSB_transmission |
| AnnaBridge | 189:f392fc9709a3 | 648 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 649 | */ |
| AnnaBridge | 189:f392fc9709a3 | 650 | #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 651 | ((__BIT__) == SPI_FIRSTBIT_LSB)) |
| AnnaBridge | 189:f392fc9709a3 | 652 | |
| AnnaBridge | 189:f392fc9709a3 | 653 | /** @brief Checks if SPI TI mode parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 654 | * @param __MODE__ specifies the SPI TI mode. |
| AnnaBridge | 189:f392fc9709a3 | 655 | * This parameter can be a value of @ref SPI_TI_mode |
| AnnaBridge | 189:f392fc9709a3 | 656 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 657 | */ |
| AnnaBridge | 189:f392fc9709a3 | 658 | #define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 659 | ((__MODE__) == SPI_TIMODE_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 660 | |
| AnnaBridge | 189:f392fc9709a3 | 661 | /** @brief Checks if SPI CRC calculation enabled state is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 662 | * @param __CALCULATION__ specifies the SPI CRC calculation enable state. |
| AnnaBridge | 189:f392fc9709a3 | 663 | * This parameter can be a value of @ref SPI_CRC_Calculation |
| AnnaBridge | 189:f392fc9709a3 | 664 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 665 | */ |
| AnnaBridge | 189:f392fc9709a3 | 666 | #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 667 | ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 668 | |
| AnnaBridge | 189:f392fc9709a3 | 669 | /** @brief Checks if SPI CRC length is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 670 | * @param __LENGTH__ specifies the SPI CRC length. |
| AnnaBridge | 189:f392fc9709a3 | 671 | * This parameter can be a value of @ref SPI_CRC_length |
| AnnaBridge | 189:f392fc9709a3 | 672 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 673 | */ |
| AnnaBridge | 189:f392fc9709a3 | 674 | #define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 675 | ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 676 | ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) |
| AnnaBridge | 189:f392fc9709a3 | 677 | |
| AnnaBridge | 189:f392fc9709a3 | 678 | /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 679 | * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. |
| AnnaBridge | 189:f392fc9709a3 | 680 | * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 |
| AnnaBridge | 189:f392fc9709a3 | 681 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 682 | */ |
| AnnaBridge | 189:f392fc9709a3 | 683 | #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) |
| AnnaBridge | 189:f392fc9709a3 | 684 | |
| AnnaBridge | 189:f392fc9709a3 | 685 | /** @brief Checks if DMA handle is valid. |
| AnnaBridge | 189:f392fc9709a3 | 686 | * @param __HANDLE__ specifies a DMA Handle. |
| AnnaBridge | 189:f392fc9709a3 | 687 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 688 | */ |
| AnnaBridge | 189:f392fc9709a3 | 689 | #define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) |
| AnnaBridge | 189:f392fc9709a3 | 690 | |
| AnnaBridge | 189:f392fc9709a3 | 691 | /** |
| AnnaBridge | 189:f392fc9709a3 | 692 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 693 | */ |
| AnnaBridge | 189:f392fc9709a3 | 694 | |
| AnnaBridge | 189:f392fc9709a3 | 695 | /* Include SPI HAL Extended module */ |
| AnnaBridge | 189:f392fc9709a3 | 696 | #include "stm32l4xx_hal_spi_ex.h" |
| AnnaBridge | 189:f392fc9709a3 | 697 | |
| AnnaBridge | 189:f392fc9709a3 | 698 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 699 | /** @addtogroup SPI_Exported_Functions |
| AnnaBridge | 189:f392fc9709a3 | 700 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 701 | */ |
| AnnaBridge | 189:f392fc9709a3 | 702 | |
| AnnaBridge | 189:f392fc9709a3 | 703 | /** @addtogroup SPI_Exported_Functions_Group1 |
| AnnaBridge | 189:f392fc9709a3 | 704 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 705 | */ |
| AnnaBridge | 189:f392fc9709a3 | 706 | /* Initialization/de-initialization functions ********************************/ |
| AnnaBridge | 189:f392fc9709a3 | 707 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 708 | HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 709 | void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 710 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 711 | /** |
| AnnaBridge | 189:f392fc9709a3 | 712 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 713 | */ |
| AnnaBridge | 189:f392fc9709a3 | 714 | |
| AnnaBridge | 189:f392fc9709a3 | 715 | /** @addtogroup SPI_Exported_Functions_Group2 |
| AnnaBridge | 189:f392fc9709a3 | 716 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 717 | */ |
| AnnaBridge | 189:f392fc9709a3 | 718 | /* I/O operation functions ***************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 719 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 720 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 721 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, |
| AnnaBridge | 189:f392fc9709a3 | 722 | uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 723 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 189:f392fc9709a3 | 724 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 189:f392fc9709a3 | 725 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
| AnnaBridge | 189:f392fc9709a3 | 726 | uint16_t Size); |
| AnnaBridge | 189:f392fc9709a3 | 727 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 189:f392fc9709a3 | 728 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 189:f392fc9709a3 | 729 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
| AnnaBridge | 189:f392fc9709a3 | 730 | uint16_t Size); |
| AnnaBridge | 189:f392fc9709a3 | 731 | HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 732 | HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 733 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 734 | /* Transfer Abort functions */ |
| AnnaBridge | 189:f392fc9709a3 | 735 | HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 736 | HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 737 | |
| AnnaBridge | 189:f392fc9709a3 | 738 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 739 | void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 740 | void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 741 | void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 742 | void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 743 | void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 744 | void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 745 | void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 746 | void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 747 | /** |
| AnnaBridge | 189:f392fc9709a3 | 748 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 749 | */ |
| AnnaBridge | 189:f392fc9709a3 | 750 | |
| AnnaBridge | 189:f392fc9709a3 | 751 | /** @addtogroup SPI_Exported_Functions_Group3 |
| AnnaBridge | 189:f392fc9709a3 | 752 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 753 | */ |
| AnnaBridge | 189:f392fc9709a3 | 754 | /* Peripheral State and Error functions ***************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 755 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 756 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 757 | /** |
| AnnaBridge | 189:f392fc9709a3 | 758 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 759 | */ |
| AnnaBridge | 189:f392fc9709a3 | 760 | |
| AnnaBridge | 189:f392fc9709a3 | 761 | /** |
| AnnaBridge | 189:f392fc9709a3 | 762 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 763 | */ |
| AnnaBridge | 189:f392fc9709a3 | 764 | |
| AnnaBridge | 189:f392fc9709a3 | 765 | /** |
| AnnaBridge | 189:f392fc9709a3 | 766 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 767 | */ |
| AnnaBridge | 189:f392fc9709a3 | 768 | |
| AnnaBridge | 189:f392fc9709a3 | 769 | /** |
| AnnaBridge | 189:f392fc9709a3 | 770 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 771 | */ |
| AnnaBridge | 189:f392fc9709a3 | 772 | |
| AnnaBridge | 189:f392fc9709a3 | 773 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 774 | } |
| AnnaBridge | 189:f392fc9709a3 | 775 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 776 | |
| AnnaBridge | 189:f392fc9709a3 | 777 | #endif /* __STM32L4xx_HAL_SPI_H */ |
| AnnaBridge | 189:f392fc9709a3 | 778 | |
| AnnaBridge | 189:f392fc9709a3 | 779 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
