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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_hal_qspi.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_hal_qspi.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of QSPI HAL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_HAL_QSPI_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_HAL_QSPI_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | #if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) |
| AnnaBridge | 189:f392fc9709a3 | 48 | |
| AnnaBridge | 189:f392fc9709a3 | 49 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 50 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 51 | */ |
| AnnaBridge | 189:f392fc9709a3 | 52 | |
| AnnaBridge | 189:f392fc9709a3 | 53 | /** @addtogroup QSPI |
| AnnaBridge | 189:f392fc9709a3 | 54 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 55 | */ |
| AnnaBridge | 189:f392fc9709a3 | 56 | |
| AnnaBridge | 189:f392fc9709a3 | 57 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 58 | /** @defgroup QSPI_Exported_Types QSPI Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 59 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 60 | */ |
| AnnaBridge | 189:f392fc9709a3 | 61 | |
| AnnaBridge | 189:f392fc9709a3 | 62 | /** |
| AnnaBridge | 189:f392fc9709a3 | 63 | * @brief QSPI Init structure definition |
| AnnaBridge | 189:f392fc9709a3 | 64 | */ |
| AnnaBridge | 189:f392fc9709a3 | 65 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 66 | { |
| AnnaBridge | 189:f392fc9709a3 | 67 | uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. |
| AnnaBridge | 189:f392fc9709a3 | 68 | This parameter can be a number between 0 and 255 */ |
| AnnaBridge | 189:f392fc9709a3 | 69 | uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) |
| AnnaBridge | 189:f392fc9709a3 | 70 | This parameter can be a value between 1 and 16 */ |
| AnnaBridge | 189:f392fc9709a3 | 71 | uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to |
| AnnaBridge | 189:f392fc9709a3 | 72 | take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) |
| AnnaBridge | 189:f392fc9709a3 | 73 | This parameter can be a value of @ref QSPI_SampleShifting */ |
| AnnaBridge | 189:f392fc9709a3 | 74 | uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits |
| AnnaBridge | 189:f392fc9709a3 | 75 | required to address the flash memory. The flash capacity can be up to 4GB |
| AnnaBridge | 189:f392fc9709a3 | 76 | (addressed using 32 bits) in indirect mode, but the addressable space in |
| AnnaBridge | 189:f392fc9709a3 | 77 | memory-mapped mode is limited to 256MB |
| AnnaBridge | 189:f392fc9709a3 | 78 | This parameter can be a number between 0 and 31 */ |
| AnnaBridge | 189:f392fc9709a3 | 79 | uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number |
| AnnaBridge | 189:f392fc9709a3 | 80 | of clock cycles which the chip select must remain high between commands. |
| AnnaBridge | 189:f392fc9709a3 | 81 | This parameter can be a value of @ref QSPI_ChipSelectHighTime */ |
| AnnaBridge | 189:f392fc9709a3 | 82 | uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. |
| AnnaBridge | 189:f392fc9709a3 | 83 | This parameter can be a value of @ref QSPI_ClockMode */ |
| AnnaBridge | 189:f392fc9709a3 | 84 | #if defined(QUADSPI_CR_DFM) |
| AnnaBridge | 189:f392fc9709a3 | 85 | uint32_t FlashID; /* Specifies the Flash which will be used, |
| AnnaBridge | 189:f392fc9709a3 | 86 | This parameter can be a value of @ref QSPI_Flash_Select */ |
| AnnaBridge | 189:f392fc9709a3 | 87 | uint32_t DualFlash; /* Specifies the Dual Flash Mode State |
| AnnaBridge | 189:f392fc9709a3 | 88 | This parameter can be a value of @ref QSPI_DualFlash_Mode */ |
| AnnaBridge | 189:f392fc9709a3 | 89 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 90 | }QSPI_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 91 | |
| AnnaBridge | 189:f392fc9709a3 | 92 | /** |
| AnnaBridge | 189:f392fc9709a3 | 93 | * @brief HAL QSPI State structures definition |
| AnnaBridge | 189:f392fc9709a3 | 94 | */ |
| AnnaBridge | 189:f392fc9709a3 | 95 | typedef enum |
| AnnaBridge | 189:f392fc9709a3 | 96 | { |
| AnnaBridge | 189:f392fc9709a3 | 97 | HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */ |
| AnnaBridge | 189:f392fc9709a3 | 98 | HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */ |
| AnnaBridge | 189:f392fc9709a3 | 99 | HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */ |
| AnnaBridge | 189:f392fc9709a3 | 100 | HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 101 | HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 102 | HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 103 | HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 104 | HAL_QSPI_STATE_ABORT = 0x08, /*!< Peripheral with abort request ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 105 | HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */ |
| AnnaBridge | 189:f392fc9709a3 | 106 | }HAL_QSPI_StateTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 107 | |
| AnnaBridge | 189:f392fc9709a3 | 108 | /** |
| AnnaBridge | 189:f392fc9709a3 | 109 | * @brief QSPI Handle Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 110 | */ |
| AnnaBridge | 189:f392fc9709a3 | 111 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 112 | { |
| AnnaBridge | 189:f392fc9709a3 | 113 | QUADSPI_TypeDef *Instance; /* QSPI registers base address */ |
| AnnaBridge | 189:f392fc9709a3 | 114 | QSPI_InitTypeDef Init; /* QSPI communication parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 115 | uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ |
| AnnaBridge | 189:f392fc9709a3 | 116 | __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ |
| AnnaBridge | 189:f392fc9709a3 | 117 | __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ |
| AnnaBridge | 189:f392fc9709a3 | 118 | uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ |
| AnnaBridge | 189:f392fc9709a3 | 119 | __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ |
| AnnaBridge | 189:f392fc9709a3 | 120 | __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | __IO HAL_LockTypeDef Lock; /* Locking object */ |
| AnnaBridge | 189:f392fc9709a3 | 123 | __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ |
| AnnaBridge | 189:f392fc9709a3 | 124 | __IO uint32_t ErrorCode; /* QSPI Error code */ |
| AnnaBridge | 189:f392fc9709a3 | 125 | uint32_t Timeout; /* Timeout for the QSPI memory access */ |
| AnnaBridge | 189:f392fc9709a3 | 126 | }QSPI_HandleTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 127 | |
| AnnaBridge | 189:f392fc9709a3 | 128 | /** |
| AnnaBridge | 189:f392fc9709a3 | 129 | * @brief QSPI Command structure definition |
| AnnaBridge | 189:f392fc9709a3 | 130 | */ |
| AnnaBridge | 189:f392fc9709a3 | 131 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 132 | { |
| AnnaBridge | 189:f392fc9709a3 | 133 | uint32_t Instruction; /* Specifies the Instruction to be sent |
| AnnaBridge | 189:f392fc9709a3 | 134 | This parameter can be a value (8-bit) between 0x00 and 0xFF */ |
| AnnaBridge | 189:f392fc9709a3 | 135 | uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) |
| AnnaBridge | 189:f392fc9709a3 | 136 | This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) |
| AnnaBridge | 189:f392fc9709a3 | 138 | This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ |
| AnnaBridge | 189:f392fc9709a3 | 139 | uint32_t AddressSize; /* Specifies the Address Size |
| AnnaBridge | 189:f392fc9709a3 | 140 | This parameter can be a value of @ref QSPI_AddressSize */ |
| AnnaBridge | 189:f392fc9709a3 | 141 | uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size |
| AnnaBridge | 189:f392fc9709a3 | 142 | This parameter can be a value of @ref QSPI_AlternateBytesSize */ |
| AnnaBridge | 189:f392fc9709a3 | 143 | uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. |
| AnnaBridge | 189:f392fc9709a3 | 144 | This parameter can be a number between 0 and 31 */ |
| AnnaBridge | 189:f392fc9709a3 | 145 | uint32_t InstructionMode; /* Specifies the Instruction Mode |
| AnnaBridge | 189:f392fc9709a3 | 146 | This parameter can be a value of @ref QSPI_InstructionMode */ |
| AnnaBridge | 189:f392fc9709a3 | 147 | uint32_t AddressMode; /* Specifies the Address Mode |
| AnnaBridge | 189:f392fc9709a3 | 148 | This parameter can be a value of @ref QSPI_AddressMode */ |
| AnnaBridge | 189:f392fc9709a3 | 149 | uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode |
| AnnaBridge | 189:f392fc9709a3 | 150 | This parameter can be a value of @ref QSPI_AlternateBytesMode */ |
| AnnaBridge | 189:f392fc9709a3 | 151 | uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) |
| AnnaBridge | 189:f392fc9709a3 | 152 | This parameter can be a value of @ref QSPI_DataMode */ |
| AnnaBridge | 189:f392fc9709a3 | 153 | uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) |
| AnnaBridge | 189:f392fc9709a3 | 154 | This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length |
| AnnaBridge | 189:f392fc9709a3 | 155 | until end of memory)*/ |
| AnnaBridge | 189:f392fc9709a3 | 156 | uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase |
| AnnaBridge | 189:f392fc9709a3 | 157 | This parameter can be a value of @ref QSPI_DdrMode */ |
| AnnaBridge | 189:f392fc9709a3 | 158 | uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of |
| AnnaBridge | 189:f392fc9709a3 | 159 | system clock in DDR mode. Not available on STM32L4x6 devices but in future devices. |
| AnnaBridge | 189:f392fc9709a3 | 160 | This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ |
| AnnaBridge | 189:f392fc9709a3 | 161 | uint32_t SIOOMode; /* Specifies the send instruction only once mode |
| AnnaBridge | 189:f392fc9709a3 | 162 | This parameter can be a value of @ref QSPI_SIOOMode */ |
| AnnaBridge | 189:f392fc9709a3 | 163 | }QSPI_CommandTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 164 | |
| AnnaBridge | 189:f392fc9709a3 | 165 | /** |
| AnnaBridge | 189:f392fc9709a3 | 166 | * @brief QSPI Auto Polling mode configuration structure definition |
| AnnaBridge | 189:f392fc9709a3 | 167 | */ |
| AnnaBridge | 189:f392fc9709a3 | 168 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 169 | { |
| AnnaBridge | 189:f392fc9709a3 | 170 | uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. |
| AnnaBridge | 189:f392fc9709a3 | 171 | This parameter can be any value between 0 and 0xFFFFFFFF */ |
| AnnaBridge | 189:f392fc9709a3 | 172 | uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. |
| AnnaBridge | 189:f392fc9709a3 | 173 | This parameter can be any value between 0 and 0xFFFFFFFF */ |
| AnnaBridge | 189:f392fc9709a3 | 174 | uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. |
| AnnaBridge | 189:f392fc9709a3 | 175 | This parameter can be any value between 0 and 0xFFFF */ |
| AnnaBridge | 189:f392fc9709a3 | 176 | uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. |
| AnnaBridge | 189:f392fc9709a3 | 177 | This parameter can be any value between 1 and 4 */ |
| AnnaBridge | 189:f392fc9709a3 | 178 | uint32_t MatchMode; /* Specifies the method used for determining a match. |
| AnnaBridge | 189:f392fc9709a3 | 179 | This parameter can be a value of @ref QSPI_MatchMode */ |
| AnnaBridge | 189:f392fc9709a3 | 180 | uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. |
| AnnaBridge | 189:f392fc9709a3 | 181 | This parameter can be a value of @ref QSPI_AutomaticStop */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | }QSPI_AutoPollingTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 183 | |
| AnnaBridge | 189:f392fc9709a3 | 184 | /** |
| AnnaBridge | 189:f392fc9709a3 | 185 | * @brief QSPI Memory Mapped mode configuration structure definition |
| AnnaBridge | 189:f392fc9709a3 | 186 | */ |
| AnnaBridge | 189:f392fc9709a3 | 187 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 188 | { |
| AnnaBridge | 189:f392fc9709a3 | 189 | uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. |
| AnnaBridge | 189:f392fc9709a3 | 190 | This parameter can be any value between 0 and 0xFFFF */ |
| AnnaBridge | 189:f392fc9709a3 | 191 | uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. |
| AnnaBridge | 189:f392fc9709a3 | 192 | This parameter can be a value of @ref QSPI_TimeOutActivation */ |
| AnnaBridge | 189:f392fc9709a3 | 193 | }QSPI_MemoryMappedTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 194 | |
| AnnaBridge | 189:f392fc9709a3 | 195 | /** |
| AnnaBridge | 189:f392fc9709a3 | 196 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 197 | */ |
| AnnaBridge | 189:f392fc9709a3 | 198 | |
| AnnaBridge | 189:f392fc9709a3 | 199 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 200 | /** @defgroup QSPI_Exported_Constants QSPI Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 201 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 202 | */ |
| AnnaBridge | 189:f392fc9709a3 | 203 | |
| AnnaBridge | 189:f392fc9709a3 | 204 | /** @defgroup QSPI_ErrorCode QSPI Error Code |
| AnnaBridge | 189:f392fc9709a3 | 205 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 206 | */ |
| AnnaBridge | 189:f392fc9709a3 | 207 | #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| AnnaBridge | 189:f392fc9709a3 | 208 | #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ |
| AnnaBridge | 189:f392fc9709a3 | 209 | #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */ |
| AnnaBridge | 189:f392fc9709a3 | 210 | #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */ |
| AnnaBridge | 189:f392fc9709a3 | 211 | #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008) /*!< Invalid parameters error */ |
| AnnaBridge | 189:f392fc9709a3 | 212 | /** |
| AnnaBridge | 189:f392fc9709a3 | 213 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 214 | */ |
| AnnaBridge | 189:f392fc9709a3 | 215 | |
| AnnaBridge | 189:f392fc9709a3 | 216 | /** @defgroup QSPI_SampleShifting QSPI Sample Shifting |
| AnnaBridge | 189:f392fc9709a3 | 217 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 218 | */ |
| AnnaBridge | 189:f392fc9709a3 | 219 | #define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/ |
| AnnaBridge | 189:f392fc9709a3 | 220 | #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ |
| AnnaBridge | 189:f392fc9709a3 | 221 | /** |
| AnnaBridge | 189:f392fc9709a3 | 222 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 223 | */ |
| AnnaBridge | 189:f392fc9709a3 | 224 | |
| AnnaBridge | 189:f392fc9709a3 | 225 | /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time |
| AnnaBridge | 189:f392fc9709a3 | 226 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 227 | */ |
| AnnaBridge | 189:f392fc9709a3 | 228 | #define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/ |
| AnnaBridge | 189:f392fc9709a3 | 229 | #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ |
| AnnaBridge | 189:f392fc9709a3 | 230 | #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ |
| AnnaBridge | 189:f392fc9709a3 | 231 | #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ |
| AnnaBridge | 189:f392fc9709a3 | 232 | #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ |
| AnnaBridge | 189:f392fc9709a3 | 233 | #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ |
| AnnaBridge | 189:f392fc9709a3 | 234 | #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ |
| AnnaBridge | 189:f392fc9709a3 | 235 | #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ |
| AnnaBridge | 189:f392fc9709a3 | 236 | /** |
| AnnaBridge | 189:f392fc9709a3 | 237 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 238 | */ |
| AnnaBridge | 189:f392fc9709a3 | 239 | |
| AnnaBridge | 189:f392fc9709a3 | 240 | /** @defgroup QSPI_ClockMode QSPI Clock Mode |
| AnnaBridge | 189:f392fc9709a3 | 241 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 242 | */ |
| AnnaBridge | 189:f392fc9709a3 | 243 | #define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/ |
| AnnaBridge | 189:f392fc9709a3 | 244 | #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ |
| AnnaBridge | 189:f392fc9709a3 | 245 | /** |
| AnnaBridge | 189:f392fc9709a3 | 246 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 247 | */ |
| AnnaBridge | 189:f392fc9709a3 | 248 | |
| AnnaBridge | 189:f392fc9709a3 | 249 | #if defined(QUADSPI_CR_DFM) |
| AnnaBridge | 189:f392fc9709a3 | 250 | /** @defgroup QSPI_Flash_Select QSPI Flash Select |
| AnnaBridge | 189:f392fc9709a3 | 251 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 252 | */ |
| AnnaBridge | 189:f392fc9709a3 | 253 | #define QSPI_FLASH_ID_1 ((uint32_t)0x00000000) /*!<FLASH 1 selected*/ |
| AnnaBridge | 189:f392fc9709a3 | 254 | #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/ |
| AnnaBridge | 189:f392fc9709a3 | 255 | /** |
| AnnaBridge | 189:f392fc9709a3 | 256 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 257 | */ |
| AnnaBridge | 189:f392fc9709a3 | 258 | |
| AnnaBridge | 189:f392fc9709a3 | 259 | /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode |
| AnnaBridge | 189:f392fc9709a3 | 260 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 261 | */ |
| AnnaBridge | 189:f392fc9709a3 | 262 | #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/ |
| AnnaBridge | 189:f392fc9709a3 | 263 | #define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000) /*!<Dual-flash mode disabled*/ |
| AnnaBridge | 189:f392fc9709a3 | 264 | /** |
| AnnaBridge | 189:f392fc9709a3 | 265 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 266 | */ |
| AnnaBridge | 189:f392fc9709a3 | 267 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 268 | |
| AnnaBridge | 189:f392fc9709a3 | 269 | /** @defgroup QSPI_AddressSize QSPI Address Size |
| AnnaBridge | 189:f392fc9709a3 | 270 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 271 | */ |
| AnnaBridge | 189:f392fc9709a3 | 272 | #define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/ |
| AnnaBridge | 189:f392fc9709a3 | 273 | #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ |
| AnnaBridge | 189:f392fc9709a3 | 274 | #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ |
| AnnaBridge | 189:f392fc9709a3 | 275 | #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ |
| AnnaBridge | 189:f392fc9709a3 | 276 | /** |
| AnnaBridge | 189:f392fc9709a3 | 277 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 278 | */ |
| AnnaBridge | 189:f392fc9709a3 | 279 | |
| AnnaBridge | 189:f392fc9709a3 | 280 | /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size |
| AnnaBridge | 189:f392fc9709a3 | 281 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 282 | */ |
| AnnaBridge | 189:f392fc9709a3 | 283 | #define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/ |
| AnnaBridge | 189:f392fc9709a3 | 284 | #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ |
| AnnaBridge | 189:f392fc9709a3 | 285 | #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ |
| AnnaBridge | 189:f392fc9709a3 | 286 | #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ |
| AnnaBridge | 189:f392fc9709a3 | 287 | /** |
| AnnaBridge | 189:f392fc9709a3 | 288 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 289 | */ |
| AnnaBridge | 189:f392fc9709a3 | 290 | |
| AnnaBridge | 189:f392fc9709a3 | 291 | /** @defgroup QSPI_InstructionMode QSPI Instruction Mode |
| AnnaBridge | 189:f392fc9709a3 | 292 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 293 | */ |
| AnnaBridge | 189:f392fc9709a3 | 294 | #define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/ |
| AnnaBridge | 189:f392fc9709a3 | 295 | #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ |
| AnnaBridge | 189:f392fc9709a3 | 296 | #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ |
| AnnaBridge | 189:f392fc9709a3 | 297 | #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ |
| AnnaBridge | 189:f392fc9709a3 | 298 | /** |
| AnnaBridge | 189:f392fc9709a3 | 299 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 300 | */ |
| AnnaBridge | 189:f392fc9709a3 | 301 | |
| AnnaBridge | 189:f392fc9709a3 | 302 | /** @defgroup QSPI_AddressMode QSPI Address Mode |
| AnnaBridge | 189:f392fc9709a3 | 303 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 304 | */ |
| AnnaBridge | 189:f392fc9709a3 | 305 | #define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/ |
| AnnaBridge | 189:f392fc9709a3 | 306 | #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ |
| AnnaBridge | 189:f392fc9709a3 | 307 | #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ |
| AnnaBridge | 189:f392fc9709a3 | 308 | #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ |
| AnnaBridge | 189:f392fc9709a3 | 309 | /** |
| AnnaBridge | 189:f392fc9709a3 | 310 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 311 | */ |
| AnnaBridge | 189:f392fc9709a3 | 312 | |
| AnnaBridge | 189:f392fc9709a3 | 313 | /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode |
| AnnaBridge | 189:f392fc9709a3 | 314 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 315 | */ |
| AnnaBridge | 189:f392fc9709a3 | 316 | #define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/ |
| AnnaBridge | 189:f392fc9709a3 | 317 | #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ |
| AnnaBridge | 189:f392fc9709a3 | 318 | #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ |
| AnnaBridge | 189:f392fc9709a3 | 319 | #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ |
| AnnaBridge | 189:f392fc9709a3 | 320 | /** |
| AnnaBridge | 189:f392fc9709a3 | 321 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 322 | */ |
| AnnaBridge | 189:f392fc9709a3 | 323 | |
| AnnaBridge | 189:f392fc9709a3 | 324 | /** @defgroup QSPI_DataMode QSPI Data Mode |
| AnnaBridge | 189:f392fc9709a3 | 325 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 326 | */ |
| AnnaBridge | 189:f392fc9709a3 | 327 | #define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/ |
| AnnaBridge | 189:f392fc9709a3 | 328 | #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ |
| AnnaBridge | 189:f392fc9709a3 | 329 | #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ |
| AnnaBridge | 189:f392fc9709a3 | 330 | #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ |
| AnnaBridge | 189:f392fc9709a3 | 331 | /** |
| AnnaBridge | 189:f392fc9709a3 | 332 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 333 | */ |
| AnnaBridge | 189:f392fc9709a3 | 334 | |
| AnnaBridge | 189:f392fc9709a3 | 335 | /** @defgroup QSPI_DdrMode QSPI DDR Mode |
| AnnaBridge | 189:f392fc9709a3 | 336 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 337 | */ |
| AnnaBridge | 189:f392fc9709a3 | 338 | #define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/ |
| AnnaBridge | 189:f392fc9709a3 | 339 | #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ |
| AnnaBridge | 189:f392fc9709a3 | 340 | /** |
| AnnaBridge | 189:f392fc9709a3 | 341 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 342 | */ |
| AnnaBridge | 189:f392fc9709a3 | 343 | |
| AnnaBridge | 189:f392fc9709a3 | 344 | /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay |
| AnnaBridge | 189:f392fc9709a3 | 345 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 346 | */ |
| AnnaBridge | 189:f392fc9709a3 | 347 | #define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/ |
| AnnaBridge | 189:f392fc9709a3 | 348 | #if defined(QUADSPI_CCR_DHHC) |
| AnnaBridge | 189:f392fc9709a3 | 349 | #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/ |
| AnnaBridge | 189:f392fc9709a3 | 350 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 351 | /** |
| AnnaBridge | 189:f392fc9709a3 | 352 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 353 | */ |
| AnnaBridge | 189:f392fc9709a3 | 354 | |
| AnnaBridge | 189:f392fc9709a3 | 355 | /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode |
| AnnaBridge | 189:f392fc9709a3 | 356 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 357 | */ |
| AnnaBridge | 189:f392fc9709a3 | 358 | #define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/ |
| AnnaBridge | 189:f392fc9709a3 | 359 | #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ |
| AnnaBridge | 189:f392fc9709a3 | 360 | /** |
| AnnaBridge | 189:f392fc9709a3 | 361 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 362 | */ |
| AnnaBridge | 189:f392fc9709a3 | 363 | |
| AnnaBridge | 189:f392fc9709a3 | 364 | /** @defgroup QSPI_MatchMode QSPI Match Mode |
| AnnaBridge | 189:f392fc9709a3 | 365 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 366 | */ |
| AnnaBridge | 189:f392fc9709a3 | 367 | #define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/ |
| AnnaBridge | 189:f392fc9709a3 | 368 | #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ |
| AnnaBridge | 189:f392fc9709a3 | 369 | /** |
| AnnaBridge | 189:f392fc9709a3 | 370 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 371 | */ |
| AnnaBridge | 189:f392fc9709a3 | 372 | |
| AnnaBridge | 189:f392fc9709a3 | 373 | /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop |
| AnnaBridge | 189:f392fc9709a3 | 374 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 375 | */ |
| AnnaBridge | 189:f392fc9709a3 | 376 | #define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/ |
| AnnaBridge | 189:f392fc9709a3 | 377 | #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ |
| AnnaBridge | 189:f392fc9709a3 | 378 | /** |
| AnnaBridge | 189:f392fc9709a3 | 379 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 380 | */ |
| AnnaBridge | 189:f392fc9709a3 | 381 | |
| AnnaBridge | 189:f392fc9709a3 | 382 | /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation |
| AnnaBridge | 189:f392fc9709a3 | 383 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 384 | */ |
| AnnaBridge | 189:f392fc9709a3 | 385 | #define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/ |
| AnnaBridge | 189:f392fc9709a3 | 386 | #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ |
| AnnaBridge | 189:f392fc9709a3 | 387 | /** |
| AnnaBridge | 189:f392fc9709a3 | 388 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 389 | */ |
| AnnaBridge | 189:f392fc9709a3 | 390 | |
| AnnaBridge | 189:f392fc9709a3 | 391 | /** @defgroup QSPI_Flags QSPI Flags |
| AnnaBridge | 189:f392fc9709a3 | 392 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 393 | */ |
| AnnaBridge | 189:f392fc9709a3 | 394 | #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ |
| AnnaBridge | 189:f392fc9709a3 | 395 | #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ |
| AnnaBridge | 189:f392fc9709a3 | 396 | #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ |
| AnnaBridge | 189:f392fc9709a3 | 397 | #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ |
| AnnaBridge | 189:f392fc9709a3 | 398 | #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ |
| AnnaBridge | 189:f392fc9709a3 | 399 | #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ |
| AnnaBridge | 189:f392fc9709a3 | 400 | /** |
| AnnaBridge | 189:f392fc9709a3 | 401 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 402 | */ |
| AnnaBridge | 189:f392fc9709a3 | 403 | |
| AnnaBridge | 189:f392fc9709a3 | 404 | /** @defgroup QSPI_Interrupts QSPI Interrupts |
| AnnaBridge | 189:f392fc9709a3 | 405 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 406 | */ |
| AnnaBridge | 189:f392fc9709a3 | 407 | #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ |
| AnnaBridge | 189:f392fc9709a3 | 408 | #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ |
| AnnaBridge | 189:f392fc9709a3 | 409 | #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ |
| AnnaBridge | 189:f392fc9709a3 | 410 | #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ |
| AnnaBridge | 189:f392fc9709a3 | 411 | #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ |
| AnnaBridge | 189:f392fc9709a3 | 412 | /** |
| AnnaBridge | 189:f392fc9709a3 | 413 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 414 | */ |
| AnnaBridge | 189:f392fc9709a3 | 415 | |
| AnnaBridge | 189:f392fc9709a3 | 416 | /** @defgroup QSPI_Timeout_definition QSPI Timeout definition |
| AnnaBridge | 189:f392fc9709a3 | 417 | * @brief QSPI Timeout definition |
| AnnaBridge | 189:f392fc9709a3 | 418 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 419 | */ |
| AnnaBridge | 189:f392fc9709a3 | 420 | #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */ |
| AnnaBridge | 189:f392fc9709a3 | 421 | /** |
| AnnaBridge | 189:f392fc9709a3 | 422 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 423 | */ |
| AnnaBridge | 189:f392fc9709a3 | 424 | |
| AnnaBridge | 189:f392fc9709a3 | 425 | /** |
| AnnaBridge | 189:f392fc9709a3 | 426 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 427 | */ |
| AnnaBridge | 189:f392fc9709a3 | 428 | |
| AnnaBridge | 189:f392fc9709a3 | 429 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 430 | /** @defgroup QSPI_Exported_Macros QSPI Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 431 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 432 | */ |
| AnnaBridge | 189:f392fc9709a3 | 433 | /** @brief Reset QSPI handle state. |
| AnnaBridge | 189:f392fc9709a3 | 434 | * @param __HANDLE__ : QSPI handle. |
| AnnaBridge | 189:f392fc9709a3 | 435 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 436 | */ |
| AnnaBridge | 189:f392fc9709a3 | 437 | #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) |
| AnnaBridge | 189:f392fc9709a3 | 438 | |
| AnnaBridge | 189:f392fc9709a3 | 439 | /** @brief Enable the QSPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 440 | * @param __HANDLE__ : specifies the QSPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 441 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 442 | */ |
| AnnaBridge | 189:f392fc9709a3 | 443 | #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) |
| AnnaBridge | 189:f392fc9709a3 | 444 | |
| AnnaBridge | 189:f392fc9709a3 | 445 | /** @brief Disable the QSPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 446 | * @param __HANDLE__ : specifies the QSPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 447 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 448 | */ |
| AnnaBridge | 189:f392fc9709a3 | 449 | #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) |
| AnnaBridge | 189:f392fc9709a3 | 450 | |
| AnnaBridge | 189:f392fc9709a3 | 451 | /** @brief Enable the specified QSPI interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 452 | * @param __HANDLE__: specifies the QSPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 453 | * @param __INTERRUPT__: specifies the QSPI interrupt source to enable. |
| AnnaBridge | 189:f392fc9709a3 | 454 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 455 | * @arg QSPI_IT_TO: QSPI Timeout interrupt |
| AnnaBridge | 189:f392fc9709a3 | 456 | * @arg QSPI_IT_SM: QSPI Status match interrupt |
| AnnaBridge | 189:f392fc9709a3 | 457 | * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
| AnnaBridge | 189:f392fc9709a3 | 458 | * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
| AnnaBridge | 189:f392fc9709a3 | 459 | * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
| AnnaBridge | 189:f392fc9709a3 | 460 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 461 | */ |
| AnnaBridge | 189:f392fc9709a3 | 462 | #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 463 | |
| AnnaBridge | 189:f392fc9709a3 | 464 | |
| AnnaBridge | 189:f392fc9709a3 | 465 | /** @brief Disable the specified QSPI interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 466 | * @param __HANDLE__: specifies the QSPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 467 | * @param __INTERRUPT__: specifies the QSPI interrupt source to disable. |
| AnnaBridge | 189:f392fc9709a3 | 468 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 469 | * @arg QSPI_IT_TO: QSPI Timeout interrupt |
| AnnaBridge | 189:f392fc9709a3 | 470 | * @arg QSPI_IT_SM: QSPI Status match interrupt |
| AnnaBridge | 189:f392fc9709a3 | 471 | * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
| AnnaBridge | 189:f392fc9709a3 | 472 | * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
| AnnaBridge | 189:f392fc9709a3 | 473 | * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
| AnnaBridge | 189:f392fc9709a3 | 474 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 475 | */ |
| AnnaBridge | 189:f392fc9709a3 | 476 | #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 477 | |
| AnnaBridge | 189:f392fc9709a3 | 478 | /** @brief Check whether the specified QSPI interrupt source is enabled or not. |
| AnnaBridge | 189:f392fc9709a3 | 479 | * @param __HANDLE__: specifies the QSPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 480 | * @param __INTERRUPT__: specifies the QSPI interrupt source to check. |
| AnnaBridge | 189:f392fc9709a3 | 481 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 482 | * @arg QSPI_IT_TO: QSPI Timeout interrupt |
| AnnaBridge | 189:f392fc9709a3 | 483 | * @arg QSPI_IT_SM: QSPI Status match interrupt |
| AnnaBridge | 189:f392fc9709a3 | 484 | * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
| AnnaBridge | 189:f392fc9709a3 | 485 | * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
| AnnaBridge | 189:f392fc9709a3 | 486 | * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
| AnnaBridge | 189:f392fc9709a3 | 487 | * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
| AnnaBridge | 189:f392fc9709a3 | 488 | */ |
| AnnaBridge | 189:f392fc9709a3 | 489 | #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 490 | |
| AnnaBridge | 189:f392fc9709a3 | 491 | /** |
| AnnaBridge | 189:f392fc9709a3 | 492 | * @brief Check whether the selected QSPI flag is set or not. |
| AnnaBridge | 189:f392fc9709a3 | 493 | * @param __HANDLE__: specifies the QSPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 494 | * @param __FLAG__: specifies the QSPI flag to check. |
| AnnaBridge | 189:f392fc9709a3 | 495 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 496 | * @arg QSPI_FLAG_BUSY: QSPI Busy flag |
| AnnaBridge | 189:f392fc9709a3 | 497 | * @arg QSPI_FLAG_TO: QSPI Timeout flag |
| AnnaBridge | 189:f392fc9709a3 | 498 | * @arg QSPI_FLAG_SM: QSPI Status match flag |
| AnnaBridge | 189:f392fc9709a3 | 499 | * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag |
| AnnaBridge | 189:f392fc9709a3 | 500 | * @arg QSPI_FLAG_TC: QSPI Transfer complete flag |
| AnnaBridge | 189:f392fc9709a3 | 501 | * @arg QSPI_FLAG_TE: QSPI Transfer error flag |
| AnnaBridge | 189:f392fc9709a3 | 502 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 503 | */ |
| AnnaBridge | 189:f392fc9709a3 | 504 | #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET) |
| AnnaBridge | 189:f392fc9709a3 | 505 | |
| AnnaBridge | 189:f392fc9709a3 | 506 | /** @brief Clears the specified QSPI's flag status. |
| AnnaBridge | 189:f392fc9709a3 | 507 | * @param __HANDLE__: specifies the QSPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 508 | * @param __FLAG__: specifies the QSPI clear register flag that needs to be set |
| AnnaBridge | 189:f392fc9709a3 | 509 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 510 | * @arg QSPI_FLAG_TO: QSPI Timeout flag |
| AnnaBridge | 189:f392fc9709a3 | 511 | * @arg QSPI_FLAG_SM: QSPI Status match flag |
| AnnaBridge | 189:f392fc9709a3 | 512 | * @arg QSPI_FLAG_TC: QSPI Transfer complete flag |
| AnnaBridge | 189:f392fc9709a3 | 513 | * @arg QSPI_FLAG_TE: QSPI Transfer error flag |
| AnnaBridge | 189:f392fc9709a3 | 514 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 515 | */ |
| AnnaBridge | 189:f392fc9709a3 | 516 | #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) |
| AnnaBridge | 189:f392fc9709a3 | 517 | /** |
| AnnaBridge | 189:f392fc9709a3 | 518 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 519 | */ |
| AnnaBridge | 189:f392fc9709a3 | 520 | |
| AnnaBridge | 189:f392fc9709a3 | 521 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 522 | /** @addtogroup QSPI_Exported_Functions |
| AnnaBridge | 189:f392fc9709a3 | 523 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 524 | */ |
| AnnaBridge | 189:f392fc9709a3 | 525 | /* Initialization/de-initialization functions ********************************/ |
| AnnaBridge | 189:f392fc9709a3 | 526 | HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 527 | HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 528 | void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 529 | void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 530 | |
| AnnaBridge | 189:f392fc9709a3 | 531 | /* IO operation functions *****************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 532 | /* QSPI IRQ handler method */ |
| AnnaBridge | 189:f392fc9709a3 | 533 | void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 534 | |
| AnnaBridge | 189:f392fc9709a3 | 535 | /* QSPI indirect mode */ |
| AnnaBridge | 189:f392fc9709a3 | 536 | HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 537 | HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 538 | HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 539 | HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); |
| AnnaBridge | 189:f392fc9709a3 | 540 | HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
| AnnaBridge | 189:f392fc9709a3 | 541 | HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
| AnnaBridge | 189:f392fc9709a3 | 542 | HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
| AnnaBridge | 189:f392fc9709a3 | 543 | HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
| AnnaBridge | 189:f392fc9709a3 | 544 | |
| AnnaBridge | 189:f392fc9709a3 | 545 | /* QSPI status flag polling mode */ |
| AnnaBridge | 189:f392fc9709a3 | 546 | HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 547 | HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); |
| AnnaBridge | 189:f392fc9709a3 | 548 | |
| AnnaBridge | 189:f392fc9709a3 | 549 | /* QSPI memory-mapped mode */ |
| AnnaBridge | 189:f392fc9709a3 | 550 | HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); |
| AnnaBridge | 189:f392fc9709a3 | 551 | |
| AnnaBridge | 189:f392fc9709a3 | 552 | /* Callback functions in non-blocking modes ***********************************/ |
| AnnaBridge | 189:f392fc9709a3 | 553 | void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 554 | void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 555 | void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 556 | |
| AnnaBridge | 189:f392fc9709a3 | 557 | /* QSPI indirect mode */ |
| AnnaBridge | 189:f392fc9709a3 | 558 | void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 559 | void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 560 | void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 561 | void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 562 | void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 563 | |
| AnnaBridge | 189:f392fc9709a3 | 564 | /* QSPI status flag polling mode */ |
| AnnaBridge | 189:f392fc9709a3 | 565 | void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 566 | |
| AnnaBridge | 189:f392fc9709a3 | 567 | /* QSPI memory-mapped mode */ |
| AnnaBridge | 189:f392fc9709a3 | 568 | void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 569 | |
| AnnaBridge | 189:f392fc9709a3 | 570 | /* Peripheral Control and State functions ************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 571 | HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 572 | uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 573 | HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 574 | HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 575 | void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 576 | HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); |
| AnnaBridge | 189:f392fc9709a3 | 577 | uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); |
| AnnaBridge | 189:f392fc9709a3 | 578 | /** |
| AnnaBridge | 189:f392fc9709a3 | 579 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 580 | */ |
| AnnaBridge | 189:f392fc9709a3 | 581 | /* End of exported functions -------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 582 | |
| AnnaBridge | 189:f392fc9709a3 | 583 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 584 | /** @defgroup QSPI_Private_Macros QSPI Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 585 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 586 | */ |
| AnnaBridge | 189:f392fc9709a3 | 587 | #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF) |
| AnnaBridge | 189:f392fc9709a3 | 588 | |
| AnnaBridge | 189:f392fc9709a3 | 589 | #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16)) |
| AnnaBridge | 189:f392fc9709a3 | 590 | |
| AnnaBridge | 189:f392fc9709a3 | 591 | #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 592 | ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) |
| AnnaBridge | 189:f392fc9709a3 | 593 | |
| AnnaBridge | 189:f392fc9709a3 | 594 | #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31)) |
| AnnaBridge | 189:f392fc9709a3 | 595 | |
| AnnaBridge | 189:f392fc9709a3 | 596 | #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 597 | ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 598 | ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 599 | ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 600 | ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 601 | ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 602 | ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 603 | ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) |
| AnnaBridge | 189:f392fc9709a3 | 604 | |
| AnnaBridge | 189:f392fc9709a3 | 605 | #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ |
| AnnaBridge | 189:f392fc9709a3 | 606 | ((CLKMODE) == QSPI_CLOCK_MODE_3)) |
| AnnaBridge | 189:f392fc9709a3 | 607 | |
| AnnaBridge | 189:f392fc9709a3 | 608 | #if defined(QUADSPI_CR_DFM) |
| AnnaBridge | 189:f392fc9709a3 | 609 | #define IS_QSPI_FLASH_ID(FLASH) (((FLASH) == QSPI_FLASH_ID_1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 610 | ((FLASH) == QSPI_FLASH_ID_2)) |
| AnnaBridge | 189:f392fc9709a3 | 611 | |
| AnnaBridge | 189:f392fc9709a3 | 612 | #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 613 | ((MODE) == QSPI_DUALFLASH_DISABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 614 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 615 | |
| AnnaBridge | 189:f392fc9709a3 | 616 | #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF) |
| AnnaBridge | 189:f392fc9709a3 | 617 | |
| AnnaBridge | 189:f392fc9709a3 | 618 | #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ |
| AnnaBridge | 189:f392fc9709a3 | 619 | ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ |
| AnnaBridge | 189:f392fc9709a3 | 620 | ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ |
| AnnaBridge | 189:f392fc9709a3 | 621 | ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) |
| AnnaBridge | 189:f392fc9709a3 | 622 | |
| AnnaBridge | 189:f392fc9709a3 | 623 | #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ |
| AnnaBridge | 189:f392fc9709a3 | 624 | ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ |
| AnnaBridge | 189:f392fc9709a3 | 625 | ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ |
| AnnaBridge | 189:f392fc9709a3 | 626 | ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) |
| AnnaBridge | 189:f392fc9709a3 | 627 | |
| AnnaBridge | 189:f392fc9709a3 | 628 | #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31) |
| AnnaBridge | 189:f392fc9709a3 | 629 | |
| AnnaBridge | 189:f392fc9709a3 | 630 | #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 631 | ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 632 | ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 633 | ((MODE) == QSPI_INSTRUCTION_4_LINES)) |
| AnnaBridge | 189:f392fc9709a3 | 634 | |
| AnnaBridge | 189:f392fc9709a3 | 635 | #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 636 | ((MODE) == QSPI_ADDRESS_1_LINE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 637 | ((MODE) == QSPI_ADDRESS_2_LINES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 638 | ((MODE) == QSPI_ADDRESS_4_LINES)) |
| AnnaBridge | 189:f392fc9709a3 | 639 | |
| AnnaBridge | 189:f392fc9709a3 | 640 | #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 641 | ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 642 | ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 643 | ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) |
| AnnaBridge | 189:f392fc9709a3 | 644 | |
| AnnaBridge | 189:f392fc9709a3 | 645 | #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 646 | ((MODE) == QSPI_DATA_1_LINE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 647 | ((MODE) == QSPI_DATA_2_LINES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 648 | ((MODE) == QSPI_DATA_4_LINES)) |
| AnnaBridge | 189:f392fc9709a3 | 649 | |
| AnnaBridge | 189:f392fc9709a3 | 650 | #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 651 | ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 652 | |
| AnnaBridge | 189:f392fc9709a3 | 653 | #if defined(QUADSPI_CCR_DHHC) |
| AnnaBridge | 189:f392fc9709a3 | 654 | #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ |
| AnnaBridge | 189:f392fc9709a3 | 655 | ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) |
| AnnaBridge | 189:f392fc9709a3 | 656 | #else |
| AnnaBridge | 189:f392fc9709a3 | 657 | #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY)) |
| AnnaBridge | 189:f392fc9709a3 | 658 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 659 | |
| AnnaBridge | 189:f392fc9709a3 | 660 | #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ |
| AnnaBridge | 189:f392fc9709a3 | 661 | ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) |
| AnnaBridge | 189:f392fc9709a3 | 662 | |
| AnnaBridge | 189:f392fc9709a3 | 663 | #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) |
| AnnaBridge | 189:f392fc9709a3 | 664 | |
| AnnaBridge | 189:f392fc9709a3 | 665 | #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) |
| AnnaBridge | 189:f392fc9709a3 | 666 | |
| AnnaBridge | 189:f392fc9709a3 | 667 | #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ |
| AnnaBridge | 189:f392fc9709a3 | 668 | ((MODE) == QSPI_MATCH_MODE_OR)) |
| AnnaBridge | 189:f392fc9709a3 | 669 | |
| AnnaBridge | 189:f392fc9709a3 | 670 | #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 671 | ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 672 | |
| AnnaBridge | 189:f392fc9709a3 | 673 | #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 674 | ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 675 | |
| AnnaBridge | 189:f392fc9709a3 | 676 | #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) |
| AnnaBridge | 189:f392fc9709a3 | 677 | /** |
| AnnaBridge | 189:f392fc9709a3 | 678 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 679 | */ |
| AnnaBridge | 189:f392fc9709a3 | 680 | /* End of private macros -----------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 681 | |
| AnnaBridge | 189:f392fc9709a3 | 682 | /** |
| AnnaBridge | 189:f392fc9709a3 | 683 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 684 | */ |
| AnnaBridge | 189:f392fc9709a3 | 685 | |
| AnnaBridge | 189:f392fc9709a3 | 686 | /** |
| AnnaBridge | 189:f392fc9709a3 | 687 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 688 | */ |
| AnnaBridge | 189:f392fc9709a3 | 689 | |
| AnnaBridge | 189:f392fc9709a3 | 690 | #endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ |
| AnnaBridge | 189:f392fc9709a3 | 691 | |
| AnnaBridge | 189:f392fc9709a3 | 692 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 693 | } |
| AnnaBridge | 189:f392fc9709a3 | 694 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 695 | |
| AnnaBridge | 189:f392fc9709a3 | 696 | #endif /* __STM32L4xx_HAL_QSPI_H */ |
| AnnaBridge | 189:f392fc9709a3 | 697 | |
| AnnaBridge | 189:f392fc9709a3 | 698 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
