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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_hal_pwr_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_hal_pwr_ex.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of PWR HAL Extended module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_HAL_PWR_EX_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_HAL_PWR_EX_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | /** @addtogroup PWREx |
| AnnaBridge | 189:f392fc9709a3 | 52 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 53 | */ |
| AnnaBridge | 189:f392fc9709a3 | 54 | |
| AnnaBridge | 189:f392fc9709a3 | 55 | |
| AnnaBridge | 189:f392fc9709a3 | 56 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 57 | |
| AnnaBridge | 189:f392fc9709a3 | 58 | /** @defgroup PWREx_Exported_Types PWR Extended Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 59 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 60 | */ |
| AnnaBridge | 189:f392fc9709a3 | 61 | |
| AnnaBridge | 189:f392fc9709a3 | 62 | |
| AnnaBridge | 189:f392fc9709a3 | 63 | /** |
| AnnaBridge | 189:f392fc9709a3 | 64 | * @brief PWR PVM configuration structure definition |
| AnnaBridge | 189:f392fc9709a3 | 65 | */ |
| AnnaBridge | 189:f392fc9709a3 | 66 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 67 | { |
| AnnaBridge | 189:f392fc9709a3 | 68 | uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. |
| AnnaBridge | 189:f392fc9709a3 | 69 | This parameter can be a value of @ref PWREx_PVM_Type. |
| AnnaBridge | 189:f392fc9709a3 | 70 | @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). |
| AnnaBridge | 189:f392fc9709a3 | 71 | @if STM32L486xx |
| AnnaBridge | 189:f392fc9709a3 | 72 | @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). |
| AnnaBridge | 189:f392fc9709a3 | 73 | @endif |
| AnnaBridge | 189:f392fc9709a3 | 74 | @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. |
| AnnaBridge | 189:f392fc9709a3 | 75 | @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */ |
| AnnaBridge | 189:f392fc9709a3 | 76 | |
| AnnaBridge | 189:f392fc9709a3 | 77 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
| AnnaBridge | 189:f392fc9709a3 | 78 | This parameter can be a value of @ref PWREx_PVM_Mode. */ |
| AnnaBridge | 189:f392fc9709a3 | 79 | }PWR_PVMTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 80 | |
| AnnaBridge | 189:f392fc9709a3 | 81 | /** |
| AnnaBridge | 189:f392fc9709a3 | 82 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 83 | */ |
| AnnaBridge | 189:f392fc9709a3 | 84 | |
| AnnaBridge | 189:f392fc9709a3 | 85 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 86 | |
| AnnaBridge | 189:f392fc9709a3 | 87 | /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 88 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 89 | */ |
| AnnaBridge | 189:f392fc9709a3 | 90 | |
| AnnaBridge | 189:f392fc9709a3 | 91 | /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants |
| AnnaBridge | 189:f392fc9709a3 | 92 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 93 | */ |
| AnnaBridge | 189:f392fc9709a3 | 94 | #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */ |
| AnnaBridge | 189:f392fc9709a3 | 95 | /** |
| AnnaBridge | 189:f392fc9709a3 | 96 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 97 | */ |
| AnnaBridge | 189:f392fc9709a3 | 98 | |
| AnnaBridge | 189:f392fc9709a3 | 99 | |
| AnnaBridge | 189:f392fc9709a3 | 100 | /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins |
| AnnaBridge | 189:f392fc9709a3 | 101 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 102 | */ |
| AnnaBridge | 189:f392fc9709a3 | 103 | #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 104 | #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 105 | #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 106 | #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 107 | #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 108 | #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 109 | #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 111 | #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 112 | #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 113 | #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 114 | #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 115 | #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 116 | #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 117 | #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ |
| AnnaBridge | 189:f392fc9709a3 | 118 | /** |
| AnnaBridge | 189:f392fc9709a3 | 119 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 120 | */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | |
| AnnaBridge | 189:f392fc9709a3 | 122 | /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type |
| AnnaBridge | 189:f392fc9709a3 | 123 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 124 | */ |
| AnnaBridge | 189:f392fc9709a3 | 125 | #if defined(PWR_CR2_PVME1) |
| AnnaBridge | 189:f392fc9709a3 | 126 | #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ |
| AnnaBridge | 189:f392fc9709a3 | 127 | #endif /* PWR_CR2_PVME1 */ |
| AnnaBridge | 189:f392fc9709a3 | 128 | #if defined(PWR_CR2_PVME2) |
| AnnaBridge | 189:f392fc9709a3 | 129 | #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */ |
| AnnaBridge | 189:f392fc9709a3 | 130 | #endif /* PWR_CR2_PVME2 */ |
| AnnaBridge | 189:f392fc9709a3 | 131 | #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ |
| AnnaBridge | 189:f392fc9709a3 | 132 | #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */ |
| AnnaBridge | 189:f392fc9709a3 | 133 | /** |
| AnnaBridge | 189:f392fc9709a3 | 134 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 135 | */ |
| AnnaBridge | 189:f392fc9709a3 | 136 | |
| AnnaBridge | 189:f392fc9709a3 | 137 | /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode |
| AnnaBridge | 189:f392fc9709a3 | 138 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 139 | */ |
| AnnaBridge | 189:f392fc9709a3 | 140 | #define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ |
| AnnaBridge | 189:f392fc9709a3 | 141 | #define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ |
| AnnaBridge | 189:f392fc9709a3 | 142 | #define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ |
| AnnaBridge | 189:f392fc9709a3 | 143 | #define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 189:f392fc9709a3 | 144 | #define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ |
| AnnaBridge | 189:f392fc9709a3 | 145 | #define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ |
| AnnaBridge | 189:f392fc9709a3 | 146 | #define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 189:f392fc9709a3 | 147 | /** |
| AnnaBridge | 189:f392fc9709a3 | 148 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 149 | */ |
| AnnaBridge | 189:f392fc9709a3 | 150 | |
| AnnaBridge | 189:f392fc9709a3 | 151 | |
| AnnaBridge | 189:f392fc9709a3 | 152 | |
| AnnaBridge | 189:f392fc9709a3 | 153 | /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale |
| AnnaBridge | 189:f392fc9709a3 | 154 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 155 | */ |
| AnnaBridge | 189:f392fc9709a3 | 156 | #if defined(PWR_CR5_R1MODE) |
| AnnaBridge | 189:f392fc9709a3 | 157 | #define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000) /*!< Voltage scaling range 1 boost mode */ |
| AnnaBridge | 189:f392fc9709a3 | 158 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 159 | #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */ |
| AnnaBridge | 189:f392fc9709a3 | 160 | #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 161 | /** |
| AnnaBridge | 189:f392fc9709a3 | 162 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 163 | */ |
| AnnaBridge | 189:f392fc9709a3 | 164 | |
| AnnaBridge | 189:f392fc9709a3 | 165 | |
| AnnaBridge | 189:f392fc9709a3 | 166 | /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection |
| AnnaBridge | 189:f392fc9709a3 | 167 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 168 | */ |
| AnnaBridge | 189:f392fc9709a3 | 169 | #define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */ |
| AnnaBridge | 189:f392fc9709a3 | 170 | #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ |
| AnnaBridge | 189:f392fc9709a3 | 171 | /** |
| AnnaBridge | 189:f392fc9709a3 | 172 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 173 | */ |
| AnnaBridge | 189:f392fc9709a3 | 174 | |
| AnnaBridge | 189:f392fc9709a3 | 175 | /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging |
| AnnaBridge | 189:f392fc9709a3 | 176 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 177 | */ |
| AnnaBridge | 189:f392fc9709a3 | 178 | #define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 179 | #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE |
| AnnaBridge | 189:f392fc9709a3 | 180 | /** |
| AnnaBridge | 189:f392fc9709a3 | 181 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 182 | */ |
| AnnaBridge | 189:f392fc9709a3 | 183 | |
| AnnaBridge | 189:f392fc9709a3 | 184 | /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode |
| AnnaBridge | 189:f392fc9709a3 | 185 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 186 | */ |
| AnnaBridge | 189:f392fc9709a3 | 187 | #define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */ |
| AnnaBridge | 189:f392fc9709a3 | 188 | #define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 189 | #define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 190 | #define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 191 | #define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */ |
| AnnaBridge | 189:f392fc9709a3 | 192 | #define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */ |
| AnnaBridge | 189:f392fc9709a3 | 193 | #define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */ |
| AnnaBridge | 189:f392fc9709a3 | 194 | #define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */ |
| AnnaBridge | 189:f392fc9709a3 | 195 | #define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */ |
| AnnaBridge | 189:f392fc9709a3 | 196 | #define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */ |
| AnnaBridge | 189:f392fc9709a3 | 197 | #define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */ |
| AnnaBridge | 189:f392fc9709a3 | 198 | #define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */ |
| AnnaBridge | 189:f392fc9709a3 | 199 | #define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */ |
| AnnaBridge | 189:f392fc9709a3 | 200 | #define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */ |
| AnnaBridge | 189:f392fc9709a3 | 201 | #define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */ |
| AnnaBridge | 189:f392fc9709a3 | 202 | #define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */ |
| AnnaBridge | 189:f392fc9709a3 | 203 | /** |
| AnnaBridge | 189:f392fc9709a3 | 204 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 205 | */ |
| AnnaBridge | 189:f392fc9709a3 | 206 | |
| AnnaBridge | 189:f392fc9709a3 | 207 | /** @defgroup PWREx_GPIO GPIO port |
| AnnaBridge | 189:f392fc9709a3 | 208 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 209 | */ |
| AnnaBridge | 189:f392fc9709a3 | 210 | #define PWR_GPIO_A 0x00000000 /*!< GPIO port A */ |
| AnnaBridge | 189:f392fc9709a3 | 211 | #define PWR_GPIO_B 0x00000001 /*!< GPIO port B */ |
| AnnaBridge | 189:f392fc9709a3 | 212 | #define PWR_GPIO_C 0x00000002 /*!< GPIO port C */ |
| AnnaBridge | 189:f392fc9709a3 | 213 | #if defined(GPIOD_BASE) |
| AnnaBridge | 189:f392fc9709a3 | 214 | #define PWR_GPIO_D 0x00000003 /*!< GPIO port D */ |
| AnnaBridge | 189:f392fc9709a3 | 215 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 216 | #if defined(GPIOE_BASE) |
| AnnaBridge | 189:f392fc9709a3 | 217 | #define PWR_GPIO_E 0x00000004 /*!< GPIO port E */ |
| AnnaBridge | 189:f392fc9709a3 | 218 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 219 | #if defined(GPIOF_BASE) |
| AnnaBridge | 189:f392fc9709a3 | 220 | #define PWR_GPIO_F 0x00000005 /*!< GPIO port F */ |
| AnnaBridge | 189:f392fc9709a3 | 221 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 222 | #if defined(GPIOG_BASE) |
| AnnaBridge | 189:f392fc9709a3 | 223 | #define PWR_GPIO_G 0x00000006 /*!< GPIO port G */ |
| AnnaBridge | 189:f392fc9709a3 | 224 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 225 | #define PWR_GPIO_H 0x00000007 /*!< GPIO port H */ |
| AnnaBridge | 189:f392fc9709a3 | 226 | #if defined(GPIOI_BASE) |
| AnnaBridge | 189:f392fc9709a3 | 227 | #define PWR_GPIO_I 0x00000008 /*!< GPIO port I */ |
| AnnaBridge | 189:f392fc9709a3 | 228 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 229 | /** |
| AnnaBridge | 189:f392fc9709a3 | 230 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 231 | */ |
| AnnaBridge | 189:f392fc9709a3 | 232 | |
| AnnaBridge | 189:f392fc9709a3 | 233 | /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines |
| AnnaBridge | 189:f392fc9709a3 | 234 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 235 | */ |
| AnnaBridge | 189:f392fc9709a3 | 236 | #if defined(PWR_CR2_PVME1) |
| AnnaBridge | 189:f392fc9709a3 | 237 | #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */ |
| AnnaBridge | 189:f392fc9709a3 | 238 | #endif /* PWR_CR2_PVME1 */ |
| AnnaBridge | 189:f392fc9709a3 | 239 | #if defined(PWR_CR2_PVME2) |
| AnnaBridge | 189:f392fc9709a3 | 240 | #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */ |
| AnnaBridge | 189:f392fc9709a3 | 241 | #endif /* PWR_CR2_PVME2 */ |
| AnnaBridge | 189:f392fc9709a3 | 242 | #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */ |
| AnnaBridge | 189:f392fc9709a3 | 243 | #define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */ |
| AnnaBridge | 189:f392fc9709a3 | 244 | /** |
| AnnaBridge | 189:f392fc9709a3 | 245 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 246 | */ |
| AnnaBridge | 189:f392fc9709a3 | 247 | |
| AnnaBridge | 189:f392fc9709a3 | 248 | /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines |
| AnnaBridge | 189:f392fc9709a3 | 249 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 250 | */ |
| AnnaBridge | 189:f392fc9709a3 | 251 | #if defined(PWR_CR2_PVME1) |
| AnnaBridge | 189:f392fc9709a3 | 252 | #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */ |
| AnnaBridge | 189:f392fc9709a3 | 253 | #endif /* PWR_CR2_PVME1 */ |
| AnnaBridge | 189:f392fc9709a3 | 254 | #if defined(PWR_CR2_PVME2) |
| AnnaBridge | 189:f392fc9709a3 | 255 | #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */ |
| AnnaBridge | 189:f392fc9709a3 | 256 | #endif /* PWR_CR2_PVME2 */ |
| AnnaBridge | 189:f392fc9709a3 | 257 | #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */ |
| AnnaBridge | 189:f392fc9709a3 | 258 | #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */ |
| AnnaBridge | 189:f392fc9709a3 | 259 | /** |
| AnnaBridge | 189:f392fc9709a3 | 260 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 261 | */ |
| AnnaBridge | 189:f392fc9709a3 | 262 | |
| AnnaBridge | 189:f392fc9709a3 | 263 | /** @defgroup PWREx_Flag PWR Status Flags |
| AnnaBridge | 189:f392fc9709a3 | 264 | * Elements values convention: 0000 0000 0XXY YYYYb |
| AnnaBridge | 189:f392fc9709a3 | 265 | * - Y YYYY : Flag position in the XX register (5 bits) |
| AnnaBridge | 189:f392fc9709a3 | 266 | * - XX : Status register (2 bits) |
| AnnaBridge | 189:f392fc9709a3 | 267 | * - 01: SR1 register |
| AnnaBridge | 189:f392fc9709a3 | 268 | * - 10: SR2 register |
| AnnaBridge | 189:f392fc9709a3 | 269 | * The only exception is PWR_FLAG_WU, encompassing all |
| AnnaBridge | 189:f392fc9709a3 | 270 | * wake-up flags and set to PWR_SR1_WUF. |
| AnnaBridge | 189:f392fc9709a3 | 271 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 272 | */ |
| AnnaBridge | 189:f392fc9709a3 | 273 | #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 274 | #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 275 | #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 276 | #define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */ |
| AnnaBridge | 189:f392fc9709a3 | 277 | #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */ |
| AnnaBridge | 189:f392fc9709a3 | 278 | #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ |
| AnnaBridge | 189:f392fc9709a3 | 279 | #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */ |
| AnnaBridge | 189:f392fc9709a3 | 280 | #define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */ |
| AnnaBridge | 189:f392fc9709a3 | 281 | |
| AnnaBridge | 189:f392fc9709a3 | 282 | #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */ |
| AnnaBridge | 189:f392fc9709a3 | 283 | #define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */ |
| AnnaBridge | 189:f392fc9709a3 | 284 | #define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */ |
| AnnaBridge | 189:f392fc9709a3 | 285 | #define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */ |
| AnnaBridge | 189:f392fc9709a3 | 286 | #if defined(PWR_CR2_PVME1) |
| AnnaBridge | 189:f392fc9709a3 | 287 | #define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */ |
| AnnaBridge | 189:f392fc9709a3 | 288 | #endif /* PWR_CR2_PVME1 */ |
| AnnaBridge | 189:f392fc9709a3 | 289 | #if defined(PWR_CR2_PVME2) |
| AnnaBridge | 189:f392fc9709a3 | 290 | #define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */ |
| AnnaBridge | 189:f392fc9709a3 | 291 | #endif /* PWR_CR2_PVME2 */ |
| AnnaBridge | 189:f392fc9709a3 | 292 | #define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */ |
| AnnaBridge | 189:f392fc9709a3 | 293 | #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */ |
| AnnaBridge | 189:f392fc9709a3 | 294 | /** |
| AnnaBridge | 189:f392fc9709a3 | 295 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 296 | */ |
| AnnaBridge | 189:f392fc9709a3 | 297 | |
| AnnaBridge | 189:f392fc9709a3 | 298 | /** |
| AnnaBridge | 189:f392fc9709a3 | 299 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 300 | */ |
| AnnaBridge | 189:f392fc9709a3 | 301 | |
| AnnaBridge | 189:f392fc9709a3 | 302 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 303 | /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 304 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 305 | */ |
| AnnaBridge | 189:f392fc9709a3 | 306 | |
| AnnaBridge | 189:f392fc9709a3 | 307 | #if defined(PWR_CR2_PVME1) |
| AnnaBridge | 189:f392fc9709a3 | 308 | /** |
| AnnaBridge | 189:f392fc9709a3 | 309 | * @brief Enable the PVM1 Extended Interrupt Line. |
| AnnaBridge | 189:f392fc9709a3 | 310 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 311 | */ |
| AnnaBridge | 189:f392fc9709a3 | 312 | #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) |
| AnnaBridge | 189:f392fc9709a3 | 313 | |
| AnnaBridge | 189:f392fc9709a3 | 314 | /** |
| AnnaBridge | 189:f392fc9709a3 | 315 | * @brief Disable the PVM1 Extended Interrupt Line. |
| AnnaBridge | 189:f392fc9709a3 | 316 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 317 | */ |
| AnnaBridge | 189:f392fc9709a3 | 318 | #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) |
| AnnaBridge | 189:f392fc9709a3 | 319 | |
| AnnaBridge | 189:f392fc9709a3 | 320 | /** |
| AnnaBridge | 189:f392fc9709a3 | 321 | * @brief Enable the PVM1 Event Line. |
| AnnaBridge | 189:f392fc9709a3 | 322 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 323 | */ |
| AnnaBridge | 189:f392fc9709a3 | 324 | #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) |
| AnnaBridge | 189:f392fc9709a3 | 325 | |
| AnnaBridge | 189:f392fc9709a3 | 326 | /** |
| AnnaBridge | 189:f392fc9709a3 | 327 | * @brief Disable the PVM1 Event Line. |
| AnnaBridge | 189:f392fc9709a3 | 328 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 329 | */ |
| AnnaBridge | 189:f392fc9709a3 | 330 | #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) |
| AnnaBridge | 189:f392fc9709a3 | 331 | |
| AnnaBridge | 189:f392fc9709a3 | 332 | /** |
| AnnaBridge | 189:f392fc9709a3 | 333 | * @brief Enable the PVM1 Extended Interrupt Rising Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 334 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 335 | */ |
| AnnaBridge | 189:f392fc9709a3 | 336 | #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) |
| AnnaBridge | 189:f392fc9709a3 | 337 | |
| AnnaBridge | 189:f392fc9709a3 | 338 | /** |
| AnnaBridge | 189:f392fc9709a3 | 339 | * @brief Disable the PVM1 Extended Interrupt Rising Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 340 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 341 | */ |
| AnnaBridge | 189:f392fc9709a3 | 342 | #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) |
| AnnaBridge | 189:f392fc9709a3 | 343 | |
| AnnaBridge | 189:f392fc9709a3 | 344 | /** |
| AnnaBridge | 189:f392fc9709a3 | 345 | * @brief Enable the PVM1 Extended Interrupt Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 346 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 347 | */ |
| AnnaBridge | 189:f392fc9709a3 | 348 | #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) |
| AnnaBridge | 189:f392fc9709a3 | 349 | |
| AnnaBridge | 189:f392fc9709a3 | 350 | |
| AnnaBridge | 189:f392fc9709a3 | 351 | /** |
| AnnaBridge | 189:f392fc9709a3 | 352 | * @brief Disable the PVM1 Extended Interrupt Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 353 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 354 | */ |
| AnnaBridge | 189:f392fc9709a3 | 355 | #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) |
| AnnaBridge | 189:f392fc9709a3 | 356 | |
| AnnaBridge | 189:f392fc9709a3 | 357 | |
| AnnaBridge | 189:f392fc9709a3 | 358 | /** |
| AnnaBridge | 189:f392fc9709a3 | 359 | * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. |
| AnnaBridge | 189:f392fc9709a3 | 360 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 361 | */ |
| AnnaBridge | 189:f392fc9709a3 | 362 | #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 189:f392fc9709a3 | 363 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 364 | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 365 | __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 366 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 367 | |
| AnnaBridge | 189:f392fc9709a3 | 368 | /** |
| AnnaBridge | 189:f392fc9709a3 | 369 | * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 370 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 371 | */ |
| AnnaBridge | 189:f392fc9709a3 | 372 | #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 189:f392fc9709a3 | 373 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 374 | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 375 | __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 376 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 377 | |
| AnnaBridge | 189:f392fc9709a3 | 378 | /** |
| AnnaBridge | 189:f392fc9709a3 | 379 | * @brief Generate a Software interrupt on selected EXTI line. |
| AnnaBridge | 189:f392fc9709a3 | 380 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 381 | */ |
| AnnaBridge | 189:f392fc9709a3 | 382 | #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) |
| AnnaBridge | 189:f392fc9709a3 | 383 | |
| AnnaBridge | 189:f392fc9709a3 | 384 | /** |
| AnnaBridge | 189:f392fc9709a3 | 385 | * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. |
| AnnaBridge | 189:f392fc9709a3 | 386 | * @retval EXTI PVM1 Line Status. |
| AnnaBridge | 189:f392fc9709a3 | 387 | */ |
| AnnaBridge | 189:f392fc9709a3 | 388 | #define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1) |
| AnnaBridge | 189:f392fc9709a3 | 389 | |
| AnnaBridge | 189:f392fc9709a3 | 390 | /** |
| AnnaBridge | 189:f392fc9709a3 | 391 | * @brief Clear the PVM1 EXTI flag. |
| AnnaBridge | 189:f392fc9709a3 | 392 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 393 | */ |
| AnnaBridge | 189:f392fc9709a3 | 394 | #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1) |
| AnnaBridge | 189:f392fc9709a3 | 395 | |
| AnnaBridge | 189:f392fc9709a3 | 396 | #endif /* PWR_CR2_PVME1 */ |
| AnnaBridge | 189:f392fc9709a3 | 397 | |
| AnnaBridge | 189:f392fc9709a3 | 398 | |
| AnnaBridge | 189:f392fc9709a3 | 399 | #if defined(PWR_CR2_PVME2) |
| AnnaBridge | 189:f392fc9709a3 | 400 | /** |
| AnnaBridge | 189:f392fc9709a3 | 401 | * @brief Enable the PVM2 Extended Interrupt Line. |
| AnnaBridge | 189:f392fc9709a3 | 402 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 403 | */ |
| AnnaBridge | 189:f392fc9709a3 | 404 | #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) |
| AnnaBridge | 189:f392fc9709a3 | 405 | |
| AnnaBridge | 189:f392fc9709a3 | 406 | /** |
| AnnaBridge | 189:f392fc9709a3 | 407 | * @brief Disable the PVM2 Extended Interrupt Line. |
| AnnaBridge | 189:f392fc9709a3 | 408 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 409 | */ |
| AnnaBridge | 189:f392fc9709a3 | 410 | #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) |
| AnnaBridge | 189:f392fc9709a3 | 411 | |
| AnnaBridge | 189:f392fc9709a3 | 412 | /** |
| AnnaBridge | 189:f392fc9709a3 | 413 | * @brief Enable the PVM2 Event Line. |
| AnnaBridge | 189:f392fc9709a3 | 414 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 415 | */ |
| AnnaBridge | 189:f392fc9709a3 | 416 | #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) |
| AnnaBridge | 189:f392fc9709a3 | 417 | |
| AnnaBridge | 189:f392fc9709a3 | 418 | /** |
| AnnaBridge | 189:f392fc9709a3 | 419 | * @brief Disable the PVM2 Event Line. |
| AnnaBridge | 189:f392fc9709a3 | 420 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 421 | */ |
| AnnaBridge | 189:f392fc9709a3 | 422 | #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) |
| AnnaBridge | 189:f392fc9709a3 | 423 | |
| AnnaBridge | 189:f392fc9709a3 | 424 | /** |
| AnnaBridge | 189:f392fc9709a3 | 425 | * @brief Enable the PVM2 Extended Interrupt Rising Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 426 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 427 | */ |
| AnnaBridge | 189:f392fc9709a3 | 428 | #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) |
| AnnaBridge | 189:f392fc9709a3 | 429 | |
| AnnaBridge | 189:f392fc9709a3 | 430 | /** |
| AnnaBridge | 189:f392fc9709a3 | 431 | * @brief Disable the PVM2 Extended Interrupt Rising Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 432 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 433 | */ |
| AnnaBridge | 189:f392fc9709a3 | 434 | #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) |
| AnnaBridge | 189:f392fc9709a3 | 435 | |
| AnnaBridge | 189:f392fc9709a3 | 436 | /** |
| AnnaBridge | 189:f392fc9709a3 | 437 | * @brief Enable the PVM2 Extended Interrupt Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 438 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 439 | */ |
| AnnaBridge | 189:f392fc9709a3 | 440 | #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) |
| AnnaBridge | 189:f392fc9709a3 | 441 | |
| AnnaBridge | 189:f392fc9709a3 | 442 | |
| AnnaBridge | 189:f392fc9709a3 | 443 | /** |
| AnnaBridge | 189:f392fc9709a3 | 444 | * @brief Disable the PVM2 Extended Interrupt Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 445 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 446 | */ |
| AnnaBridge | 189:f392fc9709a3 | 447 | #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) |
| AnnaBridge | 189:f392fc9709a3 | 448 | |
| AnnaBridge | 189:f392fc9709a3 | 449 | |
| AnnaBridge | 189:f392fc9709a3 | 450 | /** |
| AnnaBridge | 189:f392fc9709a3 | 451 | * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. |
| AnnaBridge | 189:f392fc9709a3 | 452 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 453 | */ |
| AnnaBridge | 189:f392fc9709a3 | 454 | #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 189:f392fc9709a3 | 455 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 456 | __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 457 | __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 458 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 459 | |
| AnnaBridge | 189:f392fc9709a3 | 460 | /** |
| AnnaBridge | 189:f392fc9709a3 | 461 | * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 462 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 463 | */ |
| AnnaBridge | 189:f392fc9709a3 | 464 | #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 189:f392fc9709a3 | 465 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 466 | __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 467 | __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 468 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 469 | |
| AnnaBridge | 189:f392fc9709a3 | 470 | /** |
| AnnaBridge | 189:f392fc9709a3 | 471 | * @brief Generate a Software interrupt on selected EXTI line. |
| AnnaBridge | 189:f392fc9709a3 | 472 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 473 | */ |
| AnnaBridge | 189:f392fc9709a3 | 474 | #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) |
| AnnaBridge | 189:f392fc9709a3 | 475 | |
| AnnaBridge | 189:f392fc9709a3 | 476 | /** |
| AnnaBridge | 189:f392fc9709a3 | 477 | * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. |
| AnnaBridge | 189:f392fc9709a3 | 478 | * @retval EXTI PVM2 Line Status. |
| AnnaBridge | 189:f392fc9709a3 | 479 | */ |
| AnnaBridge | 189:f392fc9709a3 | 480 | #define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2) |
| AnnaBridge | 189:f392fc9709a3 | 481 | |
| AnnaBridge | 189:f392fc9709a3 | 482 | /** |
| AnnaBridge | 189:f392fc9709a3 | 483 | * @brief Clear the PVM2 EXTI flag. |
| AnnaBridge | 189:f392fc9709a3 | 484 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 485 | */ |
| AnnaBridge | 189:f392fc9709a3 | 486 | #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2) |
| AnnaBridge | 189:f392fc9709a3 | 487 | |
| AnnaBridge | 189:f392fc9709a3 | 488 | #endif /* PWR_CR2_PVME2 */ |
| AnnaBridge | 189:f392fc9709a3 | 489 | |
| AnnaBridge | 189:f392fc9709a3 | 490 | |
| AnnaBridge | 189:f392fc9709a3 | 491 | /** |
| AnnaBridge | 189:f392fc9709a3 | 492 | * @brief Enable the PVM3 Extended Interrupt Line. |
| AnnaBridge | 189:f392fc9709a3 | 493 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 494 | */ |
| AnnaBridge | 189:f392fc9709a3 | 495 | #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) |
| AnnaBridge | 189:f392fc9709a3 | 496 | |
| AnnaBridge | 189:f392fc9709a3 | 497 | /** |
| AnnaBridge | 189:f392fc9709a3 | 498 | * @brief Disable the PVM3 Extended Interrupt Line. |
| AnnaBridge | 189:f392fc9709a3 | 499 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 500 | */ |
| AnnaBridge | 189:f392fc9709a3 | 501 | #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) |
| AnnaBridge | 189:f392fc9709a3 | 502 | |
| AnnaBridge | 189:f392fc9709a3 | 503 | /** |
| AnnaBridge | 189:f392fc9709a3 | 504 | * @brief Enable the PVM3 Event Line. |
| AnnaBridge | 189:f392fc9709a3 | 505 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 506 | */ |
| AnnaBridge | 189:f392fc9709a3 | 507 | #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) |
| AnnaBridge | 189:f392fc9709a3 | 508 | |
| AnnaBridge | 189:f392fc9709a3 | 509 | /** |
| AnnaBridge | 189:f392fc9709a3 | 510 | * @brief Disable the PVM3 Event Line. |
| AnnaBridge | 189:f392fc9709a3 | 511 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 512 | */ |
| AnnaBridge | 189:f392fc9709a3 | 513 | #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) |
| AnnaBridge | 189:f392fc9709a3 | 514 | |
| AnnaBridge | 189:f392fc9709a3 | 515 | /** |
| AnnaBridge | 189:f392fc9709a3 | 516 | * @brief Enable the PVM3 Extended Interrupt Rising Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 517 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 518 | */ |
| AnnaBridge | 189:f392fc9709a3 | 519 | #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) |
| AnnaBridge | 189:f392fc9709a3 | 520 | |
| AnnaBridge | 189:f392fc9709a3 | 521 | /** |
| AnnaBridge | 189:f392fc9709a3 | 522 | * @brief Disable the PVM3 Extended Interrupt Rising Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 523 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 524 | */ |
| AnnaBridge | 189:f392fc9709a3 | 525 | #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) |
| AnnaBridge | 189:f392fc9709a3 | 526 | |
| AnnaBridge | 189:f392fc9709a3 | 527 | /** |
| AnnaBridge | 189:f392fc9709a3 | 528 | * @brief Enable the PVM3 Extended Interrupt Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 529 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 530 | */ |
| AnnaBridge | 189:f392fc9709a3 | 531 | #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) |
| AnnaBridge | 189:f392fc9709a3 | 532 | |
| AnnaBridge | 189:f392fc9709a3 | 533 | |
| AnnaBridge | 189:f392fc9709a3 | 534 | /** |
| AnnaBridge | 189:f392fc9709a3 | 535 | * @brief Disable the PVM3 Extended Interrupt Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 536 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 537 | */ |
| AnnaBridge | 189:f392fc9709a3 | 538 | #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) |
| AnnaBridge | 189:f392fc9709a3 | 539 | |
| AnnaBridge | 189:f392fc9709a3 | 540 | |
| AnnaBridge | 189:f392fc9709a3 | 541 | /** |
| AnnaBridge | 189:f392fc9709a3 | 542 | * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. |
| AnnaBridge | 189:f392fc9709a3 | 543 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 544 | */ |
| AnnaBridge | 189:f392fc9709a3 | 545 | #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 189:f392fc9709a3 | 546 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 547 | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 548 | __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 549 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 550 | |
| AnnaBridge | 189:f392fc9709a3 | 551 | /** |
| AnnaBridge | 189:f392fc9709a3 | 552 | * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 553 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 554 | */ |
| AnnaBridge | 189:f392fc9709a3 | 555 | #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 189:f392fc9709a3 | 556 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 557 | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 558 | __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 559 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 560 | |
| AnnaBridge | 189:f392fc9709a3 | 561 | /** |
| AnnaBridge | 189:f392fc9709a3 | 562 | * @brief Generate a Software interrupt on selected EXTI line. |
| AnnaBridge | 189:f392fc9709a3 | 563 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 564 | */ |
| AnnaBridge | 189:f392fc9709a3 | 565 | #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) |
| AnnaBridge | 189:f392fc9709a3 | 566 | |
| AnnaBridge | 189:f392fc9709a3 | 567 | /** |
| AnnaBridge | 189:f392fc9709a3 | 568 | * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. |
| AnnaBridge | 189:f392fc9709a3 | 569 | * @retval EXTI PVM3 Line Status. |
| AnnaBridge | 189:f392fc9709a3 | 570 | */ |
| AnnaBridge | 189:f392fc9709a3 | 571 | #define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3) |
| AnnaBridge | 189:f392fc9709a3 | 572 | |
| AnnaBridge | 189:f392fc9709a3 | 573 | /** |
| AnnaBridge | 189:f392fc9709a3 | 574 | * @brief Clear the PVM3 EXTI flag. |
| AnnaBridge | 189:f392fc9709a3 | 575 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 576 | */ |
| AnnaBridge | 189:f392fc9709a3 | 577 | #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3) |
| AnnaBridge | 189:f392fc9709a3 | 578 | |
| AnnaBridge | 189:f392fc9709a3 | 579 | |
| AnnaBridge | 189:f392fc9709a3 | 580 | |
| AnnaBridge | 189:f392fc9709a3 | 581 | |
| AnnaBridge | 189:f392fc9709a3 | 582 | /** |
| AnnaBridge | 189:f392fc9709a3 | 583 | * @brief Enable the PVM4 Extended Interrupt Line. |
| AnnaBridge | 189:f392fc9709a3 | 584 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 585 | */ |
| AnnaBridge | 189:f392fc9709a3 | 586 | #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) |
| AnnaBridge | 189:f392fc9709a3 | 587 | |
| AnnaBridge | 189:f392fc9709a3 | 588 | /** |
| AnnaBridge | 189:f392fc9709a3 | 589 | * @brief Disable the PVM4 Extended Interrupt Line. |
| AnnaBridge | 189:f392fc9709a3 | 590 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 591 | */ |
| AnnaBridge | 189:f392fc9709a3 | 592 | #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) |
| AnnaBridge | 189:f392fc9709a3 | 593 | |
| AnnaBridge | 189:f392fc9709a3 | 594 | /** |
| AnnaBridge | 189:f392fc9709a3 | 595 | * @brief Enable the PVM4 Event Line. |
| AnnaBridge | 189:f392fc9709a3 | 596 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 597 | */ |
| AnnaBridge | 189:f392fc9709a3 | 598 | #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) |
| AnnaBridge | 189:f392fc9709a3 | 599 | |
| AnnaBridge | 189:f392fc9709a3 | 600 | /** |
| AnnaBridge | 189:f392fc9709a3 | 601 | * @brief Disable the PVM4 Event Line. |
| AnnaBridge | 189:f392fc9709a3 | 602 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 603 | */ |
| AnnaBridge | 189:f392fc9709a3 | 604 | #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) |
| AnnaBridge | 189:f392fc9709a3 | 605 | |
| AnnaBridge | 189:f392fc9709a3 | 606 | /** |
| AnnaBridge | 189:f392fc9709a3 | 607 | * @brief Enable the PVM4 Extended Interrupt Rising Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 608 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 609 | */ |
| AnnaBridge | 189:f392fc9709a3 | 610 | #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) |
| AnnaBridge | 189:f392fc9709a3 | 611 | |
| AnnaBridge | 189:f392fc9709a3 | 612 | /** |
| AnnaBridge | 189:f392fc9709a3 | 613 | * @brief Disable the PVM4 Extended Interrupt Rising Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 614 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 615 | */ |
| AnnaBridge | 189:f392fc9709a3 | 616 | #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) |
| AnnaBridge | 189:f392fc9709a3 | 617 | |
| AnnaBridge | 189:f392fc9709a3 | 618 | /** |
| AnnaBridge | 189:f392fc9709a3 | 619 | * @brief Enable the PVM4 Extended Interrupt Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 620 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 621 | */ |
| AnnaBridge | 189:f392fc9709a3 | 622 | #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) |
| AnnaBridge | 189:f392fc9709a3 | 623 | |
| AnnaBridge | 189:f392fc9709a3 | 624 | |
| AnnaBridge | 189:f392fc9709a3 | 625 | /** |
| AnnaBridge | 189:f392fc9709a3 | 626 | * @brief Disable the PVM4 Extended Interrupt Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 627 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 628 | */ |
| AnnaBridge | 189:f392fc9709a3 | 629 | #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) |
| AnnaBridge | 189:f392fc9709a3 | 630 | |
| AnnaBridge | 189:f392fc9709a3 | 631 | |
| AnnaBridge | 189:f392fc9709a3 | 632 | /** |
| AnnaBridge | 189:f392fc9709a3 | 633 | * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. |
| AnnaBridge | 189:f392fc9709a3 | 634 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 635 | */ |
| AnnaBridge | 189:f392fc9709a3 | 636 | #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 189:f392fc9709a3 | 637 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 638 | __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 639 | __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 640 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 641 | |
| AnnaBridge | 189:f392fc9709a3 | 642 | /** |
| AnnaBridge | 189:f392fc9709a3 | 643 | * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 644 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 645 | */ |
| AnnaBridge | 189:f392fc9709a3 | 646 | #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 189:f392fc9709a3 | 647 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 648 | __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 649 | __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 650 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 651 | |
| AnnaBridge | 189:f392fc9709a3 | 652 | /** |
| AnnaBridge | 189:f392fc9709a3 | 653 | * @brief Generate a Software interrupt on selected EXTI line. |
| AnnaBridge | 189:f392fc9709a3 | 654 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 655 | */ |
| AnnaBridge | 189:f392fc9709a3 | 656 | #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) |
| AnnaBridge | 189:f392fc9709a3 | 657 | |
| AnnaBridge | 189:f392fc9709a3 | 658 | /** |
| AnnaBridge | 189:f392fc9709a3 | 659 | * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. |
| AnnaBridge | 189:f392fc9709a3 | 660 | * @retval EXTI PVM4 Line Status. |
| AnnaBridge | 189:f392fc9709a3 | 661 | */ |
| AnnaBridge | 189:f392fc9709a3 | 662 | #define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4) |
| AnnaBridge | 189:f392fc9709a3 | 663 | |
| AnnaBridge | 189:f392fc9709a3 | 664 | /** |
| AnnaBridge | 189:f392fc9709a3 | 665 | * @brief Clear the PVM4 EXTI flag. |
| AnnaBridge | 189:f392fc9709a3 | 666 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 667 | */ |
| AnnaBridge | 189:f392fc9709a3 | 668 | #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4) |
| AnnaBridge | 189:f392fc9709a3 | 669 | |
| AnnaBridge | 189:f392fc9709a3 | 670 | |
| AnnaBridge | 189:f392fc9709a3 | 671 | /** |
| AnnaBridge | 189:f392fc9709a3 | 672 | * @brief Configure the main internal regulator output voltage. |
| AnnaBridge | 189:f392fc9709a3 | 673 | * @param __REGULATOR__: specifies the regulator output voltage to achieve |
| AnnaBridge | 189:f392fc9709a3 | 674 | * a tradeoff between performance and power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 675 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 676 | * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, |
| AnnaBridge | 189:f392fc9709a3 | 677 | * typical output voltage at 1.2 V, |
| AnnaBridge | 189:f392fc9709a3 | 678 | * system frequency up to 80 MHz. |
| AnnaBridge | 189:f392fc9709a3 | 679 | * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, |
| AnnaBridge | 189:f392fc9709a3 | 680 | * typical output voltage at 1.0 V, |
| AnnaBridge | 189:f392fc9709a3 | 681 | * system frequency up to 26 MHz. |
| AnnaBridge | 189:f392fc9709a3 | 682 | * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check |
| AnnaBridge | 189:f392fc9709a3 | 683 | * whether or not VOSF flag is cleared when moving from range 2 to range 1. User |
| AnnaBridge | 189:f392fc9709a3 | 684 | * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. |
| AnnaBridge | 189:f392fc9709a3 | 685 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 686 | */ |
| AnnaBridge | 189:f392fc9709a3 | 687 | #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ |
| AnnaBridge | 189:f392fc9709a3 | 688 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 689 | MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ |
| AnnaBridge | 189:f392fc9709a3 | 690 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 691 | tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ |
| AnnaBridge | 189:f392fc9709a3 | 692 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 693 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 694 | |
| AnnaBridge | 189:f392fc9709a3 | 695 | /** |
| AnnaBridge | 189:f392fc9709a3 | 696 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 697 | */ |
| AnnaBridge | 189:f392fc9709a3 | 698 | |
| AnnaBridge | 189:f392fc9709a3 | 699 | /* Private macros --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 700 | /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 701 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 702 | */ |
| AnnaBridge | 189:f392fc9709a3 | 703 | |
| AnnaBridge | 189:f392fc9709a3 | 704 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 705 | ((PIN) == PWR_WAKEUP_PIN2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 706 | ((PIN) == PWR_WAKEUP_PIN3) || \ |
| AnnaBridge | 189:f392fc9709a3 | 707 | ((PIN) == PWR_WAKEUP_PIN4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 708 | ((PIN) == PWR_WAKEUP_PIN5) || \ |
| AnnaBridge | 189:f392fc9709a3 | 709 | ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ |
| AnnaBridge | 189:f392fc9709a3 | 710 | ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ |
| AnnaBridge | 189:f392fc9709a3 | 711 | ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ |
| AnnaBridge | 189:f392fc9709a3 | 712 | ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ |
| AnnaBridge | 189:f392fc9709a3 | 713 | ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ |
| AnnaBridge | 189:f392fc9709a3 | 714 | ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ |
| AnnaBridge | 189:f392fc9709a3 | 715 | ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ |
| AnnaBridge | 189:f392fc9709a3 | 716 | ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ |
| AnnaBridge | 189:f392fc9709a3 | 717 | ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ |
| AnnaBridge | 189:f392fc9709a3 | 718 | ((PIN) == PWR_WAKEUP_PIN5_LOW)) |
| AnnaBridge | 189:f392fc9709a3 | 719 | |
| AnnaBridge | 189:f392fc9709a3 | 720 | #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 721 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 722 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 723 | #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 724 | ((TYPE) == PWR_PVM_2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 725 | ((TYPE) == PWR_PVM_3) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 726 | ((TYPE) == PWR_PVM_4)) |
| AnnaBridge | 189:f392fc9709a3 | 727 | #elif defined (STM32L471xx) |
| AnnaBridge | 189:f392fc9709a3 | 728 | #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 729 | ((TYPE) == PWR_PVM_3) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 730 | ((TYPE) == PWR_PVM_4)) |
| AnnaBridge | 189:f392fc9709a3 | 731 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 732 | |
| AnnaBridge | 189:f392fc9709a3 | 733 | #if defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx) |
| AnnaBridge | 189:f392fc9709a3 | 734 | #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 735 | ((TYPE) == PWR_PVM_3) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 736 | ((TYPE) == PWR_PVM_4)) |
| AnnaBridge | 189:f392fc9709a3 | 737 | #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx) |
| AnnaBridge | 189:f392fc9709a3 | 738 | #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 739 | ((TYPE) == PWR_PVM_4)) |
| AnnaBridge | 189:f392fc9709a3 | 740 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 741 | |
| AnnaBridge | 189:f392fc9709a3 | 742 | #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 743 | ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 744 | ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 745 | ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 746 | ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 747 | ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 748 | ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) |
| AnnaBridge | 189:f392fc9709a3 | 749 | |
| AnnaBridge | 189:f392fc9709a3 | 750 | #if defined(PWR_CR5_R1MODE) |
| AnnaBridge | 189:f392fc9709a3 | 751 | #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ |
| AnnaBridge | 189:f392fc9709a3 | 752 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 753 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) |
| AnnaBridge | 189:f392fc9709a3 | 754 | #else |
| AnnaBridge | 189:f392fc9709a3 | 755 | #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 756 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) |
| AnnaBridge | 189:f392fc9709a3 | 757 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 758 | |
| AnnaBridge | 189:f392fc9709a3 | 759 | |
| AnnaBridge | 189:f392fc9709a3 | 760 | #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 761 | ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) |
| AnnaBridge | 189:f392fc9709a3 | 762 | |
| AnnaBridge | 189:f392fc9709a3 | 763 | #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 764 | ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 765 | |
| AnnaBridge | 189:f392fc9709a3 | 766 | #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) |
| AnnaBridge | 189:f392fc9709a3 | 767 | |
| AnnaBridge | 189:f392fc9709a3 | 768 | |
| AnnaBridge | 189:f392fc9709a3 | 769 | #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 770 | defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) |
| AnnaBridge | 189:f392fc9709a3 | 771 | #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 772 | ((GPIO) == PWR_GPIO_B) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 773 | ((GPIO) == PWR_GPIO_C) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 774 | ((GPIO) == PWR_GPIO_D) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 775 | ((GPIO) == PWR_GPIO_E) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 776 | ((GPIO) == PWR_GPIO_H)) |
| AnnaBridge | 189:f392fc9709a3 | 777 | #elif defined (STM32L432xx) || defined (STM32L442xx) |
| AnnaBridge | 189:f392fc9709a3 | 778 | #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 779 | ((GPIO) == PWR_GPIO_B) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 780 | ((GPIO) == PWR_GPIO_C) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 781 | ((GPIO) == PWR_GPIO_H)) |
| AnnaBridge | 189:f392fc9709a3 | 782 | #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) |
| AnnaBridge | 189:f392fc9709a3 | 783 | #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 784 | ((GPIO) == PWR_GPIO_B) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 785 | ((GPIO) == PWR_GPIO_C) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 786 | ((GPIO) == PWR_GPIO_D) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 787 | ((GPIO) == PWR_GPIO_E) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 788 | ((GPIO) == PWR_GPIO_F) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 789 | ((GPIO) == PWR_GPIO_G) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 790 | ((GPIO) == PWR_GPIO_H)) |
| AnnaBridge | 189:f392fc9709a3 | 791 | #elif defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 792 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 793 | #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 794 | ((GPIO) == PWR_GPIO_B) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 795 | ((GPIO) == PWR_GPIO_C) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 796 | ((GPIO) == PWR_GPIO_D) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 797 | ((GPIO) == PWR_GPIO_E) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 798 | ((GPIO) == PWR_GPIO_F) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 799 | ((GPIO) == PWR_GPIO_G) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 800 | ((GPIO) == PWR_GPIO_H) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 801 | ((GPIO) == PWR_GPIO_I)) |
| AnnaBridge | 189:f392fc9709a3 | 802 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 803 | |
| AnnaBridge | 189:f392fc9709a3 | 804 | |
| AnnaBridge | 189:f392fc9709a3 | 805 | /** |
| AnnaBridge | 189:f392fc9709a3 | 806 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 807 | */ |
| AnnaBridge | 189:f392fc9709a3 | 808 | |
| AnnaBridge | 189:f392fc9709a3 | 809 | |
| AnnaBridge | 189:f392fc9709a3 | 810 | /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 811 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 812 | */ |
| AnnaBridge | 189:f392fc9709a3 | 813 | |
| AnnaBridge | 189:f392fc9709a3 | 814 | /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions |
| AnnaBridge | 189:f392fc9709a3 | 815 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 816 | */ |
| AnnaBridge | 189:f392fc9709a3 | 817 | |
| AnnaBridge | 189:f392fc9709a3 | 818 | |
| AnnaBridge | 189:f392fc9709a3 | 819 | /* Peripheral Control functions **********************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 820 | uint32_t HAL_PWREx_GetVoltageRange(void); |
| AnnaBridge | 189:f392fc9709a3 | 821 | HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); |
| AnnaBridge | 189:f392fc9709a3 | 822 | void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); |
| AnnaBridge | 189:f392fc9709a3 | 823 | void HAL_PWREx_DisableBatteryCharging(void); |
| AnnaBridge | 189:f392fc9709a3 | 824 | #if defined(PWR_CR2_USV) |
| AnnaBridge | 189:f392fc9709a3 | 825 | void HAL_PWREx_EnableVddUSB(void); |
| AnnaBridge | 189:f392fc9709a3 | 826 | void HAL_PWREx_DisableVddUSB(void); |
| AnnaBridge | 189:f392fc9709a3 | 827 | #endif /* PWR_CR2_USV */ |
| AnnaBridge | 189:f392fc9709a3 | 828 | #if defined(PWR_CR2_IOSV) |
| AnnaBridge | 189:f392fc9709a3 | 829 | void HAL_PWREx_EnableVddIO2(void); |
| AnnaBridge | 189:f392fc9709a3 | 830 | void HAL_PWREx_DisableVddIO2(void); |
| AnnaBridge | 189:f392fc9709a3 | 831 | #endif /* PWR_CR2_IOSV */ |
| AnnaBridge | 189:f392fc9709a3 | 832 | void HAL_PWREx_EnableInternalWakeUpLine(void); |
| AnnaBridge | 189:f392fc9709a3 | 833 | void HAL_PWREx_DisableInternalWakeUpLine(void); |
| AnnaBridge | 189:f392fc9709a3 | 834 | HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); |
| AnnaBridge | 189:f392fc9709a3 | 835 | HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); |
| AnnaBridge | 189:f392fc9709a3 | 836 | HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); |
| AnnaBridge | 189:f392fc9709a3 | 837 | HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); |
| AnnaBridge | 189:f392fc9709a3 | 838 | void HAL_PWREx_EnablePullUpPullDownConfig(void); |
| AnnaBridge | 189:f392fc9709a3 | 839 | void HAL_PWREx_DisablePullUpPullDownConfig(void); |
| AnnaBridge | 189:f392fc9709a3 | 840 | void HAL_PWREx_EnableSRAM2ContentRetention(void); |
| AnnaBridge | 189:f392fc9709a3 | 841 | void HAL_PWREx_DisableSRAM2ContentRetention(void); |
| AnnaBridge | 189:f392fc9709a3 | 842 | #if defined(PWR_CR1_RRSTP) |
| AnnaBridge | 189:f392fc9709a3 | 843 | void HAL_PWREx_EnableSRAM3ContentRetention(void); |
| AnnaBridge | 189:f392fc9709a3 | 844 | void HAL_PWREx_DisableSRAM3ContentRetention(void); |
| AnnaBridge | 189:f392fc9709a3 | 845 | #endif /* PWR_CR1_RRSTP */ |
| AnnaBridge | 189:f392fc9709a3 | 846 | #if defined(PWR_CR3_DSIPDEN) |
| AnnaBridge | 189:f392fc9709a3 | 847 | void HAL_PWREx_EnableDSIPinsPDActivation(void); |
| AnnaBridge | 189:f392fc9709a3 | 848 | void HAL_PWREx_DisableDSIPinsPDActivation(void); |
| AnnaBridge | 189:f392fc9709a3 | 849 | #endif /* PWR_CR3_DSIPDEN */ |
| AnnaBridge | 189:f392fc9709a3 | 850 | #if defined(PWR_CR2_PVME1) |
| AnnaBridge | 189:f392fc9709a3 | 851 | void HAL_PWREx_EnablePVM1(void); |
| AnnaBridge | 189:f392fc9709a3 | 852 | void HAL_PWREx_DisablePVM1(void); |
| AnnaBridge | 189:f392fc9709a3 | 853 | #endif /* PWR_CR2_PVME1 */ |
| AnnaBridge | 189:f392fc9709a3 | 854 | #if defined(PWR_CR2_PVME2) |
| AnnaBridge | 189:f392fc9709a3 | 855 | void HAL_PWREx_EnablePVM2(void); |
| AnnaBridge | 189:f392fc9709a3 | 856 | void HAL_PWREx_DisablePVM2(void); |
| AnnaBridge | 189:f392fc9709a3 | 857 | #endif /* PWR_CR2_PVME2 */ |
| AnnaBridge | 189:f392fc9709a3 | 858 | void HAL_PWREx_EnablePVM3(void); |
| AnnaBridge | 189:f392fc9709a3 | 859 | void HAL_PWREx_DisablePVM3(void); |
| AnnaBridge | 189:f392fc9709a3 | 860 | void HAL_PWREx_EnablePVM4(void); |
| AnnaBridge | 189:f392fc9709a3 | 861 | void HAL_PWREx_DisablePVM4(void); |
| AnnaBridge | 189:f392fc9709a3 | 862 | HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); |
| AnnaBridge | 189:f392fc9709a3 | 863 | |
| AnnaBridge | 189:f392fc9709a3 | 864 | |
| AnnaBridge | 189:f392fc9709a3 | 865 | /* Low Power modes configuration functions ************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 866 | void HAL_PWREx_EnableLowPowerRunMode(void); |
| AnnaBridge | 189:f392fc9709a3 | 867 | HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); |
| AnnaBridge | 189:f392fc9709a3 | 868 | void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); |
| AnnaBridge | 189:f392fc9709a3 | 869 | void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); |
| AnnaBridge | 189:f392fc9709a3 | 870 | void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); |
| AnnaBridge | 189:f392fc9709a3 | 871 | void HAL_PWREx_EnterSHUTDOWNMode(void); |
| AnnaBridge | 189:f392fc9709a3 | 872 | |
| AnnaBridge | 189:f392fc9709a3 | 873 | void HAL_PWREx_PVD_PVM_IRQHandler(void); |
| AnnaBridge | 189:f392fc9709a3 | 874 | #if defined(PWR_CR2_PVME1) |
| AnnaBridge | 189:f392fc9709a3 | 875 | void HAL_PWREx_PVM1Callback(void); |
| AnnaBridge | 189:f392fc9709a3 | 876 | #endif /* PWR_CR2_PVME1 */ |
| AnnaBridge | 189:f392fc9709a3 | 877 | #if defined(PWR_CR2_PVME2) |
| AnnaBridge | 189:f392fc9709a3 | 878 | void HAL_PWREx_PVM2Callback(void); |
| AnnaBridge | 189:f392fc9709a3 | 879 | #endif /* PWR_CR2_PVME2 */ |
| AnnaBridge | 189:f392fc9709a3 | 880 | void HAL_PWREx_PVM3Callback(void); |
| AnnaBridge | 189:f392fc9709a3 | 881 | void HAL_PWREx_PVM4Callback(void); |
| AnnaBridge | 189:f392fc9709a3 | 882 | |
| AnnaBridge | 189:f392fc9709a3 | 883 | /** |
| AnnaBridge | 189:f392fc9709a3 | 884 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 885 | */ |
| AnnaBridge | 189:f392fc9709a3 | 886 | |
| AnnaBridge | 189:f392fc9709a3 | 887 | /** |
| AnnaBridge | 189:f392fc9709a3 | 888 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 889 | */ |
| AnnaBridge | 189:f392fc9709a3 | 890 | |
| AnnaBridge | 189:f392fc9709a3 | 891 | /** |
| AnnaBridge | 189:f392fc9709a3 | 892 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 893 | */ |
| AnnaBridge | 189:f392fc9709a3 | 894 | |
| AnnaBridge | 189:f392fc9709a3 | 895 | /** |
| AnnaBridge | 189:f392fc9709a3 | 896 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 897 | */ |
| AnnaBridge | 189:f392fc9709a3 | 898 | |
| AnnaBridge | 189:f392fc9709a3 | 899 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 900 | } |
| AnnaBridge | 189:f392fc9709a3 | 901 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 902 | |
| AnnaBridge | 189:f392fc9709a3 | 903 | |
| AnnaBridge | 189:f392fc9709a3 | 904 | #endif /* __STM32L4xx_HAL_PWR_EX_H */ |
| AnnaBridge | 189:f392fc9709a3 | 905 | |
| AnnaBridge | 189:f392fc9709a3 | 906 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
