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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_hal_lcd.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_hal_lcd.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of LCD Controller HAL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_HAL_LCD_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_HAL_LCD_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | #if defined(STM32L433xx) || defined(STM32L443xx) || defined(STM32L476xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) |
| AnnaBridge | 189:f392fc9709a3 | 45 | |
| AnnaBridge | 189:f392fc9709a3 | 46 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 47 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 48 | |
| AnnaBridge | 189:f392fc9709a3 | 49 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 50 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 51 | */ |
| AnnaBridge | 189:f392fc9709a3 | 52 | |
| AnnaBridge | 189:f392fc9709a3 | 53 | /** @addtogroup LCD |
| AnnaBridge | 189:f392fc9709a3 | 54 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 55 | */ |
| AnnaBridge | 189:f392fc9709a3 | 56 | |
| AnnaBridge | 189:f392fc9709a3 | 57 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 58 | /** @defgroup LCD_Exported_Types LCD Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 59 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 60 | */ |
| AnnaBridge | 189:f392fc9709a3 | 61 | |
| AnnaBridge | 189:f392fc9709a3 | 62 | /** |
| AnnaBridge | 189:f392fc9709a3 | 63 | * @brief LCD Init structure definition |
| AnnaBridge | 189:f392fc9709a3 | 64 | */ |
| AnnaBridge | 189:f392fc9709a3 | 65 | |
| AnnaBridge | 189:f392fc9709a3 | 66 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 67 | { |
| AnnaBridge | 189:f392fc9709a3 | 68 | uint32_t Prescaler; /*!< Configures the LCD Prescaler. |
| AnnaBridge | 189:f392fc9709a3 | 69 | This parameter can be one value of @ref LCD_Prescaler */ |
| AnnaBridge | 189:f392fc9709a3 | 70 | uint32_t Divider; /*!< Configures the LCD Divider. |
| AnnaBridge | 189:f392fc9709a3 | 71 | This parameter can be one value of @ref LCD_Divider */ |
| AnnaBridge | 189:f392fc9709a3 | 72 | uint32_t Duty; /*!< Configures the LCD Duty. |
| AnnaBridge | 189:f392fc9709a3 | 73 | This parameter can be one value of @ref LCD_Duty */ |
| AnnaBridge | 189:f392fc9709a3 | 74 | uint32_t Bias; /*!< Configures the LCD Bias. |
| AnnaBridge | 189:f392fc9709a3 | 75 | This parameter can be one value of @ref LCD_Bias */ |
| AnnaBridge | 189:f392fc9709a3 | 76 | uint32_t VoltageSource; /*!< Selects the LCD Voltage source. |
| AnnaBridge | 189:f392fc9709a3 | 77 | This parameter can be one value of @ref LCD_Voltage_Source */ |
| AnnaBridge | 189:f392fc9709a3 | 78 | uint32_t Contrast; /*!< Configures the LCD Contrast. |
| AnnaBridge | 189:f392fc9709a3 | 79 | This parameter can be one value of @ref LCD_Contrast */ |
| AnnaBridge | 189:f392fc9709a3 | 80 | uint32_t DeadTime; /*!< Configures the LCD Dead Time. |
| AnnaBridge | 189:f392fc9709a3 | 81 | This parameter can be one value of @ref LCD_DeadTime */ |
| AnnaBridge | 189:f392fc9709a3 | 82 | uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration. |
| AnnaBridge | 189:f392fc9709a3 | 83 | This parameter can be one value of @ref LCD_PulseOnDuration */ |
| AnnaBridge | 189:f392fc9709a3 | 84 | uint32_t HighDrive; /*!< Enable or disable the low resistance divider. |
| AnnaBridge | 189:f392fc9709a3 | 85 | This parameter can be one value of @ref LCD_HighDrive */ |
| AnnaBridge | 189:f392fc9709a3 | 86 | uint32_t BlinkMode; /*!< Configures the LCD Blink Mode. |
| AnnaBridge | 189:f392fc9709a3 | 87 | This parameter can be one value of @ref LCD_BlinkMode */ |
| AnnaBridge | 189:f392fc9709a3 | 88 | uint32_t BlinkFrequency; /*!< Configures the LCD Blink frequency. |
| AnnaBridge | 189:f392fc9709a3 | 89 | This parameter can be one value of @ref LCD_BlinkFrequency */ |
| AnnaBridge | 189:f392fc9709a3 | 90 | uint32_t MuxSegment; /*!< Enable or disable mux segment. |
| AnnaBridge | 189:f392fc9709a3 | 91 | This parameter can be one value of @ref LCD_MuxSegment */ |
| AnnaBridge | 189:f392fc9709a3 | 92 | } LCD_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 93 | |
| AnnaBridge | 189:f392fc9709a3 | 94 | /** |
| AnnaBridge | 189:f392fc9709a3 | 95 | * @brief HAL LCD State structures definition |
| AnnaBridge | 189:f392fc9709a3 | 96 | */ |
| AnnaBridge | 189:f392fc9709a3 | 97 | typedef enum |
| AnnaBridge | 189:f392fc9709a3 | 98 | { |
| AnnaBridge | 189:f392fc9709a3 | 99 | HAL_LCD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ |
| AnnaBridge | 189:f392fc9709a3 | 100 | HAL_LCD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ |
| AnnaBridge | 189:f392fc9709a3 | 101 | HAL_LCD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 102 | HAL_LCD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
| AnnaBridge | 189:f392fc9709a3 | 103 | HAL_LCD_STATE_ERROR = 0x04 /*!< Error */ |
| AnnaBridge | 189:f392fc9709a3 | 104 | } HAL_LCD_StateTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 105 | |
| AnnaBridge | 189:f392fc9709a3 | 106 | /** |
| AnnaBridge | 189:f392fc9709a3 | 107 | * @brief UART handle Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 108 | */ |
| AnnaBridge | 189:f392fc9709a3 | 109 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 110 | { |
| AnnaBridge | 189:f392fc9709a3 | 111 | LCD_TypeDef *Instance; /* LCD registers base address */ |
| AnnaBridge | 189:f392fc9709a3 | 112 | |
| AnnaBridge | 189:f392fc9709a3 | 113 | LCD_InitTypeDef Init; /* LCD communication parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 114 | |
| AnnaBridge | 189:f392fc9709a3 | 115 | HAL_LockTypeDef Lock; /* Locking object */ |
| AnnaBridge | 189:f392fc9709a3 | 116 | |
| AnnaBridge | 189:f392fc9709a3 | 117 | __IO HAL_LCD_StateTypeDef State; /* LCD communication state */ |
| AnnaBridge | 189:f392fc9709a3 | 118 | |
| AnnaBridge | 189:f392fc9709a3 | 119 | __IO uint32_t ErrorCode; /* LCD Error code */ |
| AnnaBridge | 189:f392fc9709a3 | 120 | |
| AnnaBridge | 189:f392fc9709a3 | 121 | }LCD_HandleTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 122 | /** |
| AnnaBridge | 189:f392fc9709a3 | 123 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 124 | */ |
| AnnaBridge | 189:f392fc9709a3 | 125 | |
| AnnaBridge | 189:f392fc9709a3 | 126 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 127 | /** @defgroup LCD_Exported_Constants LCD Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 128 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 129 | */ |
| AnnaBridge | 189:f392fc9709a3 | 130 | |
| AnnaBridge | 189:f392fc9709a3 | 131 | /** @defgroup LCD_ErrorCode LCD Error Code |
| AnnaBridge | 189:f392fc9709a3 | 132 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 133 | */ |
| AnnaBridge | 189:f392fc9709a3 | 134 | #define HAL_LCD_ERROR_NONE ((uint32_t)0x00) /*!< No error */ |
| AnnaBridge | 189:f392fc9709a3 | 135 | #define HAL_LCD_ERROR_FCRSF ((uint32_t)0x01) /*!< Synchro flag timeout error */ |
| AnnaBridge | 189:f392fc9709a3 | 136 | #define HAL_LCD_ERROR_UDR ((uint32_t)0x02) /*!< Update display request flag timeout error */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | #define HAL_LCD_ERROR_UDD ((uint32_t)0x04) /*!< Update display done flag timeout error */ |
| AnnaBridge | 189:f392fc9709a3 | 138 | #define HAL_LCD_ERROR_ENS ((uint32_t)0x08) /*!< LCD enabled status flag timeout error */ |
| AnnaBridge | 189:f392fc9709a3 | 139 | #define HAL_LCD_ERROR_RDY ((uint32_t)0x10) /*!< LCD Booster ready timeout error */ |
| AnnaBridge | 189:f392fc9709a3 | 140 | /** |
| AnnaBridge | 189:f392fc9709a3 | 141 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 142 | */ |
| AnnaBridge | 189:f392fc9709a3 | 143 | |
| AnnaBridge | 189:f392fc9709a3 | 144 | /** @defgroup LCD_Prescaler LCD Prescaler |
| AnnaBridge | 189:f392fc9709a3 | 145 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 146 | */ |
| AnnaBridge | 189:f392fc9709a3 | 147 | #define LCD_PRESCALER_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */ |
| AnnaBridge | 189:f392fc9709a3 | 148 | #define LCD_PRESCALER_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */ |
| AnnaBridge | 189:f392fc9709a3 | 149 | #define LCD_PRESCALER_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */ |
| AnnaBridge | 189:f392fc9709a3 | 150 | #define LCD_PRESCALER_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */ |
| AnnaBridge | 189:f392fc9709a3 | 151 | #define LCD_PRESCALER_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */ |
| AnnaBridge | 189:f392fc9709a3 | 152 | #define LCD_PRESCALER_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */ |
| AnnaBridge | 189:f392fc9709a3 | 153 | #define LCD_PRESCALER_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */ |
| AnnaBridge | 189:f392fc9709a3 | 154 | #define LCD_PRESCALER_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */ |
| AnnaBridge | 189:f392fc9709a3 | 155 | #define LCD_PRESCALER_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */ |
| AnnaBridge | 189:f392fc9709a3 | 156 | #define LCD_PRESCALER_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */ |
| AnnaBridge | 189:f392fc9709a3 | 157 | #define LCD_PRESCALER_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */ |
| AnnaBridge | 189:f392fc9709a3 | 158 | #define LCD_PRESCALER_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */ |
| AnnaBridge | 189:f392fc9709a3 | 159 | #define LCD_PRESCALER_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */ |
| AnnaBridge | 189:f392fc9709a3 | 160 | #define LCD_PRESCALER_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */ |
| AnnaBridge | 189:f392fc9709a3 | 161 | #define LCD_PRESCALER_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */ |
| AnnaBridge | 189:f392fc9709a3 | 162 | #define LCD_PRESCALER_32768 ((uint32_t)0x03C00000) /*!< CLKPS = LCDCLK/32768 */ |
| AnnaBridge | 189:f392fc9709a3 | 163 | /** |
| AnnaBridge | 189:f392fc9709a3 | 164 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 165 | */ |
| AnnaBridge | 189:f392fc9709a3 | 166 | |
| AnnaBridge | 189:f392fc9709a3 | 167 | /** @defgroup LCD_Divider LCD Divider |
| AnnaBridge | 189:f392fc9709a3 | 168 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 169 | */ |
| AnnaBridge | 189:f392fc9709a3 | 170 | #define LCD_DIVIDER_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */ |
| AnnaBridge | 189:f392fc9709a3 | 171 | #define LCD_DIVIDER_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */ |
| AnnaBridge | 189:f392fc9709a3 | 172 | #define LCD_DIVIDER_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */ |
| AnnaBridge | 189:f392fc9709a3 | 173 | #define LCD_DIVIDER_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */ |
| AnnaBridge | 189:f392fc9709a3 | 174 | #define LCD_DIVIDER_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */ |
| AnnaBridge | 189:f392fc9709a3 | 175 | #define LCD_DIVIDER_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */ |
| AnnaBridge | 189:f392fc9709a3 | 176 | #define LCD_DIVIDER_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */ |
| AnnaBridge | 189:f392fc9709a3 | 177 | #define LCD_DIVIDER_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */ |
| AnnaBridge | 189:f392fc9709a3 | 178 | #define LCD_DIVIDER_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */ |
| AnnaBridge | 189:f392fc9709a3 | 179 | #define LCD_DIVIDER_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */ |
| AnnaBridge | 189:f392fc9709a3 | 180 | #define LCD_DIVIDER_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */ |
| AnnaBridge | 189:f392fc9709a3 | 181 | #define LCD_DIVIDER_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | #define LCD_DIVIDER_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */ |
| AnnaBridge | 189:f392fc9709a3 | 183 | #define LCD_DIVIDER_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */ |
| AnnaBridge | 189:f392fc9709a3 | 184 | #define LCD_DIVIDER_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */ |
| AnnaBridge | 189:f392fc9709a3 | 185 | #define LCD_DIVIDER_31 ((uint32_t)0x003C0000) /*!< LCD frequency = CLKPS/31 */ |
| AnnaBridge | 189:f392fc9709a3 | 186 | /** |
| AnnaBridge | 189:f392fc9709a3 | 187 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 188 | */ |
| AnnaBridge | 189:f392fc9709a3 | 189 | |
| AnnaBridge | 189:f392fc9709a3 | 190 | |
| AnnaBridge | 189:f392fc9709a3 | 191 | /** @defgroup LCD_Duty LCD Duty |
| AnnaBridge | 189:f392fc9709a3 | 192 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 193 | */ |
| AnnaBridge | 189:f392fc9709a3 | 194 | #define LCD_DUTY_STATIC ((uint32_t)0x00000000) /*!< Static duty */ |
| AnnaBridge | 189:f392fc9709a3 | 195 | #define LCD_DUTY_1_2 (LCD_CR_DUTY_0) /*!< 1/2 duty */ |
| AnnaBridge | 189:f392fc9709a3 | 196 | #define LCD_DUTY_1_3 (LCD_CR_DUTY_1) /*!< 1/3 duty */ |
| AnnaBridge | 189:f392fc9709a3 | 197 | #define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty */ |
| AnnaBridge | 189:f392fc9709a3 | 198 | #define LCD_DUTY_1_8 (LCD_CR_DUTY_2) /*!< 1/8 duty */ |
| AnnaBridge | 189:f392fc9709a3 | 199 | /** |
| AnnaBridge | 189:f392fc9709a3 | 200 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 201 | */ |
| AnnaBridge | 189:f392fc9709a3 | 202 | |
| AnnaBridge | 189:f392fc9709a3 | 203 | |
| AnnaBridge | 189:f392fc9709a3 | 204 | /** @defgroup LCD_Bias LCD Bias |
| AnnaBridge | 189:f392fc9709a3 | 205 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 206 | */ |
| AnnaBridge | 189:f392fc9709a3 | 207 | #define LCD_BIAS_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */ |
| AnnaBridge | 189:f392fc9709a3 | 208 | #define LCD_BIAS_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */ |
| AnnaBridge | 189:f392fc9709a3 | 209 | #define LCD_BIAS_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */ |
| AnnaBridge | 189:f392fc9709a3 | 210 | /** |
| AnnaBridge | 189:f392fc9709a3 | 211 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 212 | */ |
| AnnaBridge | 189:f392fc9709a3 | 213 | |
| AnnaBridge | 189:f392fc9709a3 | 214 | /** @defgroup LCD_Voltage_Source LCD Voltage Source |
| AnnaBridge | 189:f392fc9709a3 | 215 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 216 | */ |
| AnnaBridge | 189:f392fc9709a3 | 217 | #define LCD_VOLTAGESOURCE_INTERNAL ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */ |
| AnnaBridge | 189:f392fc9709a3 | 218 | #define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL /*!< External voltage source for the LCD */ |
| AnnaBridge | 189:f392fc9709a3 | 219 | /** |
| AnnaBridge | 189:f392fc9709a3 | 220 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 221 | */ |
| AnnaBridge | 189:f392fc9709a3 | 222 | |
| AnnaBridge | 189:f392fc9709a3 | 223 | /** @defgroup LCD_Interrupts LCD Interrupts |
| AnnaBridge | 189:f392fc9709a3 | 224 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 225 | */ |
| AnnaBridge | 189:f392fc9709a3 | 226 | #define LCD_IT_SOF LCD_FCR_SOFIE |
| AnnaBridge | 189:f392fc9709a3 | 227 | #define LCD_IT_UDD LCD_FCR_UDDIE |
| AnnaBridge | 189:f392fc9709a3 | 228 | /** |
| AnnaBridge | 189:f392fc9709a3 | 229 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 230 | */ |
| AnnaBridge | 189:f392fc9709a3 | 231 | |
| AnnaBridge | 189:f392fc9709a3 | 232 | /** @defgroup LCD_PulseOnDuration LCD Pulse On Duration |
| AnnaBridge | 189:f392fc9709a3 | 233 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 234 | */ |
| AnnaBridge | 189:f392fc9709a3 | 235 | #define LCD_PULSEONDURATION_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */ |
| AnnaBridge | 189:f392fc9709a3 | 236 | #define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0) /*!< Pulse ON duration = 1/CK_PS */ |
| AnnaBridge | 189:f392fc9709a3 | 237 | #define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1) /*!< Pulse ON duration = 2/CK_PS */ |
| AnnaBridge | 189:f392fc9709a3 | 238 | #define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS */ |
| AnnaBridge | 189:f392fc9709a3 | 239 | #define LCD_PULSEONDURATION_4 (LCD_FCR_PON_2) /*!< Pulse ON duration = 4/CK_PS */ |
| AnnaBridge | 189:f392fc9709a3 | 240 | #define LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS */ |
| AnnaBridge | 189:f392fc9709a3 | 241 | #define LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS */ |
| AnnaBridge | 189:f392fc9709a3 | 242 | #define LCD_PULSEONDURATION_7 (LCD_FCR_PON) /*!< Pulse ON duration = 7/CK_PS */ |
| AnnaBridge | 189:f392fc9709a3 | 243 | /** |
| AnnaBridge | 189:f392fc9709a3 | 244 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 245 | */ |
| AnnaBridge | 189:f392fc9709a3 | 246 | |
| AnnaBridge | 189:f392fc9709a3 | 247 | |
| AnnaBridge | 189:f392fc9709a3 | 248 | /** @defgroup LCD_DeadTime LCD Dead Time |
| AnnaBridge | 189:f392fc9709a3 | 249 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 250 | */ |
| AnnaBridge | 189:f392fc9709a3 | 251 | #define LCD_DEADTIME_0 ((uint32_t)0x00000000) /*!< No dead Time */ |
| AnnaBridge | 189:f392fc9709a3 | 252 | #define LCD_DEADTIME_1 (LCD_FCR_DEAD_0) /*!< One Phase between different couple of Frame */ |
| AnnaBridge | 189:f392fc9709a3 | 253 | #define LCD_DEADTIME_2 (LCD_FCR_DEAD_1) /*!< Two Phase between different couple of Frame */ |
| AnnaBridge | 189:f392fc9709a3 | 254 | #define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */ |
| AnnaBridge | 189:f392fc9709a3 | 255 | #define LCD_DEADTIME_4 (LCD_FCR_DEAD_2) /*!< Four Phase between different couple of Frame */ |
| AnnaBridge | 189:f392fc9709a3 | 256 | #define LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame */ |
| AnnaBridge | 189:f392fc9709a3 | 257 | #define LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame */ |
| AnnaBridge | 189:f392fc9709a3 | 258 | #define LCD_DEADTIME_7 (LCD_FCR_DEAD) /*!< Seven Phase between different couple of Frame */ |
| AnnaBridge | 189:f392fc9709a3 | 259 | /** |
| AnnaBridge | 189:f392fc9709a3 | 260 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 261 | */ |
| AnnaBridge | 189:f392fc9709a3 | 262 | |
| AnnaBridge | 189:f392fc9709a3 | 263 | /** @defgroup LCD_BlinkMode LCD Blink Mode |
| AnnaBridge | 189:f392fc9709a3 | 264 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 265 | */ |
| AnnaBridge | 189:f392fc9709a3 | 266 | #define LCD_BLINKMODE_OFF ((uint32_t)0x00000000) /*!< Blink disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 267 | #define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */ |
| AnnaBridge | 189:f392fc9709a3 | 268 | #define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1) /*!< Blink enabled on SEG[0], all COM (up to |
| AnnaBridge | 189:f392fc9709a3 | 269 | 8 pixels according to the programmed duty) */ |
| AnnaBridge | 189:f392fc9709a3 | 270 | #define LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK) /*!< Blink enabled on all SEG and all COM (all pixels) */ |
| AnnaBridge | 189:f392fc9709a3 | 271 | /** |
| AnnaBridge | 189:f392fc9709a3 | 272 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 273 | */ |
| AnnaBridge | 189:f392fc9709a3 | 274 | |
| AnnaBridge | 189:f392fc9709a3 | 275 | /** @defgroup LCD_BlinkFrequency LCD Blink Frequency |
| AnnaBridge | 189:f392fc9709a3 | 276 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 277 | */ |
| AnnaBridge | 189:f392fc9709a3 | 278 | #define LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */ |
| AnnaBridge | 189:f392fc9709a3 | 279 | #define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/16 */ |
| AnnaBridge | 189:f392fc9709a3 | 280 | #define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/32 */ |
| AnnaBridge | 189:f392fc9709a3 | 281 | #define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64 */ |
| AnnaBridge | 189:f392fc9709a3 | 282 | #define LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2) /*!< The Blink frequency = fLCD/128 */ |
| AnnaBridge | 189:f392fc9709a3 | 283 | #define LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/256 */ |
| AnnaBridge | 189:f392fc9709a3 | 284 | #define LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/512 */ |
| AnnaBridge | 189:f392fc9709a3 | 285 | #define LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF) /*!< The Blink frequency = fLCD/1024 */ |
| AnnaBridge | 189:f392fc9709a3 | 286 | /** |
| AnnaBridge | 189:f392fc9709a3 | 287 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 288 | */ |
| AnnaBridge | 189:f392fc9709a3 | 289 | |
| AnnaBridge | 189:f392fc9709a3 | 290 | /** @defgroup LCD_Contrast LCD Contrast |
| AnnaBridge | 189:f392fc9709a3 | 291 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 292 | */ |
| AnnaBridge | 189:f392fc9709a3 | 293 | #define LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */ |
| AnnaBridge | 189:f392fc9709a3 | 294 | #define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0) /*!< Maximum Voltage = 2.73V */ |
| AnnaBridge | 189:f392fc9709a3 | 295 | #define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1) /*!< Maximum Voltage = 2.86V */ |
| AnnaBridge | 189:f392fc9709a3 | 296 | #define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V */ |
| AnnaBridge | 189:f392fc9709a3 | 297 | #define LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2) /*!< Maximum Voltage = 3.12V */ |
| AnnaBridge | 189:f392fc9709a3 | 298 | #define LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.26V */ |
| AnnaBridge | 189:f392fc9709a3 | 299 | #define LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.40V */ |
| AnnaBridge | 189:f392fc9709a3 | 300 | #define LCD_CONTRASTLEVEL_7 (LCD_FCR_CC) /*!< Maximum Voltage = 3.55V */ |
| AnnaBridge | 189:f392fc9709a3 | 301 | /** |
| AnnaBridge | 189:f392fc9709a3 | 302 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 303 | */ |
| AnnaBridge | 189:f392fc9709a3 | 304 | |
| AnnaBridge | 189:f392fc9709a3 | 305 | /** @defgroup LCD_RAMRegister LCD RAMRegister |
| AnnaBridge | 189:f392fc9709a3 | 306 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 307 | */ |
| AnnaBridge | 189:f392fc9709a3 | 308 | #define LCD_RAM_REGISTER0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */ |
| AnnaBridge | 189:f392fc9709a3 | 309 | #define LCD_RAM_REGISTER1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 310 | #define LCD_RAM_REGISTER2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 311 | #define LCD_RAM_REGISTER3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 312 | #define LCD_RAM_REGISTER4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */ |
| AnnaBridge | 189:f392fc9709a3 | 313 | #define LCD_RAM_REGISTER5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */ |
| AnnaBridge | 189:f392fc9709a3 | 314 | #define LCD_RAM_REGISTER6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */ |
| AnnaBridge | 189:f392fc9709a3 | 315 | #define LCD_RAM_REGISTER7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */ |
| AnnaBridge | 189:f392fc9709a3 | 316 | #define LCD_RAM_REGISTER8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */ |
| AnnaBridge | 189:f392fc9709a3 | 317 | #define LCD_RAM_REGISTER9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */ |
| AnnaBridge | 189:f392fc9709a3 | 318 | #define LCD_RAM_REGISTER10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */ |
| AnnaBridge | 189:f392fc9709a3 | 319 | #define LCD_RAM_REGISTER11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */ |
| AnnaBridge | 189:f392fc9709a3 | 320 | #define LCD_RAM_REGISTER12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */ |
| AnnaBridge | 189:f392fc9709a3 | 321 | #define LCD_RAM_REGISTER13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */ |
| AnnaBridge | 189:f392fc9709a3 | 322 | #define LCD_RAM_REGISTER14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */ |
| AnnaBridge | 189:f392fc9709a3 | 323 | #define LCD_RAM_REGISTER15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */ |
| AnnaBridge | 189:f392fc9709a3 | 324 | /** |
| AnnaBridge | 189:f392fc9709a3 | 325 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 326 | */ |
| AnnaBridge | 189:f392fc9709a3 | 327 | |
| AnnaBridge | 189:f392fc9709a3 | 328 | /** @defgroup LCD_HighDrive LCD High Drive |
| AnnaBridge | 189:f392fc9709a3 | 329 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 330 | */ |
| AnnaBridge | 189:f392fc9709a3 | 331 | |
| AnnaBridge | 189:f392fc9709a3 | 332 | #define LCD_HIGHDRIVE_DISABLE ((uint32_t)0x00000000) /*!< High drive disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 333 | #define LCD_HIGHDRIVE_ENABLE (LCD_FCR_HD) /*!< High drive enabled */ |
| AnnaBridge | 189:f392fc9709a3 | 334 | /** |
| AnnaBridge | 189:f392fc9709a3 | 335 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 336 | */ |
| AnnaBridge | 189:f392fc9709a3 | 337 | |
| AnnaBridge | 189:f392fc9709a3 | 338 | /** @defgroup LCD_MuxSegment LCD Mux Segment |
| AnnaBridge | 189:f392fc9709a3 | 339 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 340 | */ |
| AnnaBridge | 189:f392fc9709a3 | 341 | |
| AnnaBridge | 189:f392fc9709a3 | 342 | #define LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000) /*!< SEG pin multiplexing disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 343 | #define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG) /*!< SEG[31:28] are multiplexed with SEG[43:40] */ |
| AnnaBridge | 189:f392fc9709a3 | 344 | /** |
| AnnaBridge | 189:f392fc9709a3 | 345 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 346 | */ |
| AnnaBridge | 189:f392fc9709a3 | 347 | |
| AnnaBridge | 189:f392fc9709a3 | 348 | /** @defgroup LCD_Flag_Definition LCD Flags Definition |
| AnnaBridge | 189:f392fc9709a3 | 349 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 350 | */ |
| AnnaBridge | 189:f392fc9709a3 | 351 | #define LCD_FLAG_ENS LCD_SR_ENS /*!< LCD enabled status */ |
| AnnaBridge | 189:f392fc9709a3 | 352 | #define LCD_FLAG_SOF LCD_SR_SOF /*!< Start of frame flag */ |
| AnnaBridge | 189:f392fc9709a3 | 353 | #define LCD_FLAG_UDR LCD_SR_UDR /*!< Update display request */ |
| AnnaBridge | 189:f392fc9709a3 | 354 | #define LCD_FLAG_UDD LCD_SR_UDD /*!< Update display done */ |
| AnnaBridge | 189:f392fc9709a3 | 355 | #define LCD_FLAG_RDY LCD_SR_RDY /*!< Ready flag */ |
| AnnaBridge | 189:f392fc9709a3 | 356 | #define LCD_FLAG_FCRSF LCD_SR_FCRSR /*!< LCD Frame Control Register Synchronization flag */ |
| AnnaBridge | 189:f392fc9709a3 | 357 | /** |
| AnnaBridge | 189:f392fc9709a3 | 358 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 359 | */ |
| AnnaBridge | 189:f392fc9709a3 | 360 | |
| AnnaBridge | 189:f392fc9709a3 | 361 | /** |
| AnnaBridge | 189:f392fc9709a3 | 362 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 363 | */ |
| AnnaBridge | 189:f392fc9709a3 | 364 | |
| AnnaBridge | 189:f392fc9709a3 | 365 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 366 | /** @defgroup LCD_Exported_Macros LCD Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 367 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 368 | */ |
| AnnaBridge | 189:f392fc9709a3 | 369 | |
| AnnaBridge | 189:f392fc9709a3 | 370 | /** @brief Reset LCD handle state. |
| AnnaBridge | 189:f392fc9709a3 | 371 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 372 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 373 | */ |
| AnnaBridge | 189:f392fc9709a3 | 374 | #define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET) |
| AnnaBridge | 189:f392fc9709a3 | 375 | |
| AnnaBridge | 189:f392fc9709a3 | 376 | /** @brief Enable the LCD peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 377 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 378 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 379 | */ |
| AnnaBridge | 189:f392fc9709a3 | 380 | #define __HAL_LCD_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN) |
| AnnaBridge | 189:f392fc9709a3 | 381 | |
| AnnaBridge | 189:f392fc9709a3 | 382 | /** @brief Disable the LCD peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 383 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 384 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 385 | */ |
| AnnaBridge | 189:f392fc9709a3 | 386 | #define __HAL_LCD_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN) |
| AnnaBridge | 189:f392fc9709a3 | 387 | |
| AnnaBridge | 189:f392fc9709a3 | 388 | /** @brief Enable the low resistance divider. |
| AnnaBridge | 189:f392fc9709a3 | 389 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 390 | * @note Displays with high internal resistance may need a longer drive time to |
| AnnaBridge | 189:f392fc9709a3 | 391 | * achieve satisfactory contrast. This function is useful in this case if |
| AnnaBridge | 189:f392fc9709a3 | 392 | * some additional power consumption can be tolerated. |
| AnnaBridge | 189:f392fc9709a3 | 393 | * @note When this mode is enabled, the PulseOn Duration (PON) have to be |
| AnnaBridge | 189:f392fc9709a3 | 394 | * programmed to 1/CK_PS (LCD_PULSEONDURATION_1). |
| AnnaBridge | 189:f392fc9709a3 | 395 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 396 | */ |
| AnnaBridge | 189:f392fc9709a3 | 397 | #define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__) \ |
| AnnaBridge | 189:f392fc9709a3 | 398 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 399 | SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \ |
| AnnaBridge | 189:f392fc9709a3 | 400 | LCD_WaitForSynchro(__HANDLE__); \ |
| AnnaBridge | 189:f392fc9709a3 | 401 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 402 | |
| AnnaBridge | 189:f392fc9709a3 | 403 | /** @brief Disable the low resistance divider. |
| AnnaBridge | 189:f392fc9709a3 | 404 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 405 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 406 | */ |
| AnnaBridge | 189:f392fc9709a3 | 407 | #define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__) \ |
| AnnaBridge | 189:f392fc9709a3 | 408 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 409 | CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \ |
| AnnaBridge | 189:f392fc9709a3 | 410 | LCD_WaitForSynchro(__HANDLE__); \ |
| AnnaBridge | 189:f392fc9709a3 | 411 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 412 | |
| AnnaBridge | 189:f392fc9709a3 | 413 | /** @brief Enable the voltage output buffer for higher driving capability. |
| AnnaBridge | 189:f392fc9709a3 | 414 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 415 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 416 | */ |
| AnnaBridge | 189:f392fc9709a3 | 417 | #define __HAL_LCD_VOLTAGE_BUFFER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN) |
| AnnaBridge | 189:f392fc9709a3 | 418 | |
| AnnaBridge | 189:f392fc9709a3 | 419 | /** @brief Disable the voltage output buffer for higher driving capability. |
| AnnaBridge | 189:f392fc9709a3 | 420 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 421 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 422 | */ |
| AnnaBridge | 189:f392fc9709a3 | 423 | #define __HAL_LCD_VOLTAGE_BUFFER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN) |
| AnnaBridge | 189:f392fc9709a3 | 424 | |
| AnnaBridge | 189:f392fc9709a3 | 425 | /** |
| AnnaBridge | 189:f392fc9709a3 | 426 | * @brief Configure the LCD pulse on duration. |
| AnnaBridge | 189:f392fc9709a3 | 427 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 428 | * @param __DURATION__: specifies the LCD pulse on duration in terms of |
| AnnaBridge | 189:f392fc9709a3 | 429 | * CK_PS (prescaled LCD clock period) pulses. |
| AnnaBridge | 189:f392fc9709a3 | 430 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 431 | * @arg LCD_PULSEONDURATION_0: 0 pulse |
| AnnaBridge | 189:f392fc9709a3 | 432 | * @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS |
| AnnaBridge | 189:f392fc9709a3 | 433 | * @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS |
| AnnaBridge | 189:f392fc9709a3 | 434 | * @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS |
| AnnaBridge | 189:f392fc9709a3 | 435 | * @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS |
| AnnaBridge | 189:f392fc9709a3 | 436 | * @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS |
| AnnaBridge | 189:f392fc9709a3 | 437 | * @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS |
| AnnaBridge | 189:f392fc9709a3 | 438 | * @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS |
| AnnaBridge | 189:f392fc9709a3 | 439 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 440 | */ |
| AnnaBridge | 189:f392fc9709a3 | 441 | #define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__) \ |
| AnnaBridge | 189:f392fc9709a3 | 442 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 443 | MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \ |
| AnnaBridge | 189:f392fc9709a3 | 444 | LCD_WaitForSynchro(__HANDLE__); \ |
| AnnaBridge | 189:f392fc9709a3 | 445 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 446 | |
| AnnaBridge | 189:f392fc9709a3 | 447 | /** |
| AnnaBridge | 189:f392fc9709a3 | 448 | * @brief Configure the LCD dead time. |
| AnnaBridge | 189:f392fc9709a3 | 449 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 450 | * @param __DEADTIME__: specifies the LCD dead time. |
| AnnaBridge | 189:f392fc9709a3 | 451 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 452 | * @arg LCD_DEADTIME_0: No dead Time |
| AnnaBridge | 189:f392fc9709a3 | 453 | * @arg LCD_DEADTIME_1: One Phase between different couple of Frame |
| AnnaBridge | 189:f392fc9709a3 | 454 | * @arg LCD_DEADTIME_2: Two Phase between different couple of Frame |
| AnnaBridge | 189:f392fc9709a3 | 455 | * @arg LCD_DEADTIME_3: Three Phase between different couple of Frame |
| AnnaBridge | 189:f392fc9709a3 | 456 | * @arg LCD_DEADTIME_4: Four Phase between different couple of Frame |
| AnnaBridge | 189:f392fc9709a3 | 457 | * @arg LCD_DEADTIME_5: Five Phase between different couple of Frame |
| AnnaBridge | 189:f392fc9709a3 | 458 | * @arg LCD_DEADTIME_6: Six Phase between different couple of Frame |
| AnnaBridge | 189:f392fc9709a3 | 459 | * @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame |
| AnnaBridge | 189:f392fc9709a3 | 460 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 461 | */ |
| AnnaBridge | 189:f392fc9709a3 | 462 | #define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__) \ |
| AnnaBridge | 189:f392fc9709a3 | 463 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 464 | MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \ |
| AnnaBridge | 189:f392fc9709a3 | 465 | LCD_WaitForSynchro(__HANDLE__); \ |
| AnnaBridge | 189:f392fc9709a3 | 466 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 467 | |
| AnnaBridge | 189:f392fc9709a3 | 468 | /** |
| AnnaBridge | 189:f392fc9709a3 | 469 | * @brief Configure the LCD contrast. |
| AnnaBridge | 189:f392fc9709a3 | 470 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 471 | * @param __CONTRAST__: specifies the LCD Contrast. |
| AnnaBridge | 189:f392fc9709a3 | 472 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 473 | * @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V |
| AnnaBridge | 189:f392fc9709a3 | 474 | * @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V |
| AnnaBridge | 189:f392fc9709a3 | 475 | * @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V |
| AnnaBridge | 189:f392fc9709a3 | 476 | * @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V |
| AnnaBridge | 189:f392fc9709a3 | 477 | * @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V |
| AnnaBridge | 189:f392fc9709a3 | 478 | * @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V |
| AnnaBridge | 189:f392fc9709a3 | 479 | * @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V |
| AnnaBridge | 189:f392fc9709a3 | 480 | * @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V |
| AnnaBridge | 189:f392fc9709a3 | 481 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 482 | */ |
| AnnaBridge | 189:f392fc9709a3 | 483 | #define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__) \ |
| AnnaBridge | 189:f392fc9709a3 | 484 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 485 | MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \ |
| AnnaBridge | 189:f392fc9709a3 | 486 | LCD_WaitForSynchro(__HANDLE__); \ |
| AnnaBridge | 189:f392fc9709a3 | 487 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 488 | |
| AnnaBridge | 189:f392fc9709a3 | 489 | /** |
| AnnaBridge | 189:f392fc9709a3 | 490 | * @brief Configure the LCD Blink mode and Blink frequency. |
| AnnaBridge | 189:f392fc9709a3 | 491 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 492 | * @param __BLINKMODE__: specifies the LCD blink mode. |
| AnnaBridge | 189:f392fc9709a3 | 493 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 494 | * @arg LCD_BLINKMODE_OFF: Blink disabled |
| AnnaBridge | 189:f392fc9709a3 | 495 | * @arg LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel) |
| AnnaBridge | 189:f392fc9709a3 | 496 | * @arg LCD_BLINKMODE_SEG0_ALLCOM: Blink enabled on SEG[0], all COM (up to 8 |
| AnnaBridge | 189:f392fc9709a3 | 497 | * pixels according to the programmed duty) |
| AnnaBridge | 189:f392fc9709a3 | 498 | * @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM |
| AnnaBridge | 189:f392fc9709a3 | 499 | * (all pixels) |
| AnnaBridge | 189:f392fc9709a3 | 500 | * @param __BLINKFREQUENCY__: specifies the LCD blink frequency. |
| AnnaBridge | 189:f392fc9709a3 | 501 | * @arg LCD_BLINKFREQUENCY_DIV8: The Blink frequency = fLcd/8 |
| AnnaBridge | 189:f392fc9709a3 | 502 | * @arg LCD_BLINKFREQUENCY_DIV16: The Blink frequency = fLcd/16 |
| AnnaBridge | 189:f392fc9709a3 | 503 | * @arg LCD_BLINKFREQUENCY_DIV32: The Blink frequency = fLcd/32 |
| AnnaBridge | 189:f392fc9709a3 | 504 | * @arg LCD_BLINKFREQUENCY_DIV64: The Blink frequency = fLcd/64 |
| AnnaBridge | 189:f392fc9709a3 | 505 | * @arg LCD_BLINKFREQUENCY_DIV128: The Blink frequency = fLcd/128 |
| AnnaBridge | 189:f392fc9709a3 | 506 | * @arg LCD_BLINKFREQUENCY_DIV256: The Blink frequency = fLcd/256 |
| AnnaBridge | 189:f392fc9709a3 | 507 | * @arg LCD_BLINKFREQUENCY_DIV512: The Blink frequency = fLcd/512 |
| AnnaBridge | 189:f392fc9709a3 | 508 | * @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024 |
| AnnaBridge | 189:f392fc9709a3 | 509 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 510 | */ |
| AnnaBridge | 189:f392fc9709a3 | 511 | #define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__) \ |
| AnnaBridge | 189:f392fc9709a3 | 512 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 513 | MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \ |
| AnnaBridge | 189:f392fc9709a3 | 514 | LCD_WaitForSynchro(__HANDLE__); \ |
| AnnaBridge | 189:f392fc9709a3 | 515 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 516 | |
| AnnaBridge | 189:f392fc9709a3 | 517 | /** @brief Enable the specified LCD interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 518 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 519 | * @param __INTERRUPT__: specifies the LCD interrupt source to be enabled. |
| AnnaBridge | 189:f392fc9709a3 | 520 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 521 | * @arg LCD_IT_SOF: Start of Frame Interrupt |
| AnnaBridge | 189:f392fc9709a3 | 522 | * @arg LCD_IT_UDD: Update Display Done Interrupt |
| AnnaBridge | 189:f392fc9709a3 | 523 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 524 | */ |
| AnnaBridge | 189:f392fc9709a3 | 525 | #define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ |
| AnnaBridge | 189:f392fc9709a3 | 526 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 527 | SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \ |
| AnnaBridge | 189:f392fc9709a3 | 528 | LCD_WaitForSynchro(__HANDLE__); \ |
| AnnaBridge | 189:f392fc9709a3 | 529 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 530 | |
| AnnaBridge | 189:f392fc9709a3 | 531 | /** @brief Disable the specified LCD interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 532 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 533 | * @param __INTERRUPT__: specifies the LCD interrupt source to be disabled. |
| AnnaBridge | 189:f392fc9709a3 | 534 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 535 | * @arg LCD_IT_SOF: Start of Frame Interrupt |
| AnnaBridge | 189:f392fc9709a3 | 536 | * @arg LCD_IT_UDD: Update Display Done Interrupt |
| AnnaBridge | 189:f392fc9709a3 | 537 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 538 | */ |
| AnnaBridge | 189:f392fc9709a3 | 539 | #define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ |
| AnnaBridge | 189:f392fc9709a3 | 540 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 541 | CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \ |
| AnnaBridge | 189:f392fc9709a3 | 542 | LCD_WaitForSynchro(__HANDLE__); \ |
| AnnaBridge | 189:f392fc9709a3 | 543 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 544 | |
| AnnaBridge | 189:f392fc9709a3 | 545 | /** @brief Check whether the specified LCD interrupt source is enabled or not. |
| AnnaBridge | 189:f392fc9709a3 | 546 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 547 | * @param __IT__: specifies the LCD interrupt source to check. |
| AnnaBridge | 189:f392fc9709a3 | 548 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 549 | * @arg LCD_IT_SOF: Start of Frame Interrupt |
| AnnaBridge | 189:f392fc9709a3 | 550 | * @arg LCD_IT_UDD: Update Display Done Interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 551 | * @note If the device is in STOP mode (PCLK not provided) UDD will not |
| AnnaBridge | 189:f392fc9709a3 | 552 | * generate an interrupt even if UDDIE = 1. |
| AnnaBridge | 189:f392fc9709a3 | 553 | * If the display is not enabled the UDD interrupt will never occur. |
| AnnaBridge | 189:f392fc9709a3 | 554 | * @retval The state of __IT__ (TRUE or FALSE). |
| AnnaBridge | 189:f392fc9709a3 | 555 | */ |
| AnnaBridge | 189:f392fc9709a3 | 556 | #define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__)) |
| AnnaBridge | 189:f392fc9709a3 | 557 | |
| AnnaBridge | 189:f392fc9709a3 | 558 | /** @brief Check whether the specified LCD flag is set or not. |
| AnnaBridge | 189:f392fc9709a3 | 559 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 560 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 189:f392fc9709a3 | 561 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 562 | * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status. |
| AnnaBridge | 189:f392fc9709a3 | 563 | * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR |
| AnnaBridge | 189:f392fc9709a3 | 564 | * goes from 0 to 1. On deactivation it reflects the real status of |
| AnnaBridge | 189:f392fc9709a3 | 565 | * LCD so it becomes 0 at the end of the last displayed frame. |
| AnnaBridge | 189:f392fc9709a3 | 566 | * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at |
| AnnaBridge | 189:f392fc9709a3 | 567 | * the beginning of a new frame, at the same time as the display data is |
| AnnaBridge | 189:f392fc9709a3 | 568 | * updated. |
| AnnaBridge | 189:f392fc9709a3 | 569 | * @arg LCD_FLAG_UDR: Update Display Request flag. |
| AnnaBridge | 189:f392fc9709a3 | 570 | * @arg LCD_FLAG_UDD: Update Display Done flag. |
| AnnaBridge | 189:f392fc9709a3 | 571 | * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status |
| AnnaBridge | 189:f392fc9709a3 | 572 | * of the step-up converter. |
| AnnaBridge | 189:f392fc9709a3 | 573 | * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. |
| AnnaBridge | 189:f392fc9709a3 | 574 | * This flag is set by hardware each time the LCD_FCR register is updated |
| AnnaBridge | 189:f392fc9709a3 | 575 | * in the LCDCLK domain. |
| AnnaBridge | 189:f392fc9709a3 | 576 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 189:f392fc9709a3 | 577 | */ |
| AnnaBridge | 189:f392fc9709a3 | 578 | #define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 189:f392fc9709a3 | 579 | |
| AnnaBridge | 189:f392fc9709a3 | 580 | /** @brief Clear the specified LCD pending flag. |
| AnnaBridge | 189:f392fc9709a3 | 581 | * @param __HANDLE__: specifies the LCD Handle. |
| AnnaBridge | 189:f392fc9709a3 | 582 | * @param __FLAG__: specifies the flag to clear. |
| AnnaBridge | 189:f392fc9709a3 | 583 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 584 | * @arg LCD_FLAG_SOF: Start of Frame Interrupt |
| AnnaBridge | 189:f392fc9709a3 | 585 | * @arg LCD_FLAG_UDD: Update Display Done Interrupt |
| AnnaBridge | 189:f392fc9709a3 | 586 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 587 | */ |
| AnnaBridge | 189:f392fc9709a3 | 588 | #define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->CLR, (__FLAG__)) |
| AnnaBridge | 189:f392fc9709a3 | 589 | |
| AnnaBridge | 189:f392fc9709a3 | 590 | /** |
| AnnaBridge | 189:f392fc9709a3 | 591 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 592 | */ |
| AnnaBridge | 189:f392fc9709a3 | 593 | |
| AnnaBridge | 189:f392fc9709a3 | 594 | /* Exported functions ------------------------------------------------------- */ |
| AnnaBridge | 189:f392fc9709a3 | 595 | /** @addtogroup LCD_Exported_Functions |
| AnnaBridge | 189:f392fc9709a3 | 596 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 597 | */ |
| AnnaBridge | 189:f392fc9709a3 | 598 | |
| AnnaBridge | 189:f392fc9709a3 | 599 | /* Initialization/de-initialization methods **********************************/ |
| AnnaBridge | 189:f392fc9709a3 | 600 | /** @addtogroup LCD_Exported_Functions_Group1 |
| AnnaBridge | 189:f392fc9709a3 | 601 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 602 | */ |
| AnnaBridge | 189:f392fc9709a3 | 603 | HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd); |
| AnnaBridge | 189:f392fc9709a3 | 604 | HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd); |
| AnnaBridge | 189:f392fc9709a3 | 605 | void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd); |
| AnnaBridge | 189:f392fc9709a3 | 606 | void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd); |
| AnnaBridge | 189:f392fc9709a3 | 607 | /** |
| AnnaBridge | 189:f392fc9709a3 | 608 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 609 | */ |
| AnnaBridge | 189:f392fc9709a3 | 610 | |
| AnnaBridge | 189:f392fc9709a3 | 611 | /* IO operation methods *******************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 612 | /** @addtogroup LCD_Exported_Functions_Group2 |
| AnnaBridge | 189:f392fc9709a3 | 613 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 614 | */ |
| AnnaBridge | 189:f392fc9709a3 | 615 | HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data); |
| AnnaBridge | 189:f392fc9709a3 | 616 | HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd); |
| AnnaBridge | 189:f392fc9709a3 | 617 | HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd); |
| AnnaBridge | 189:f392fc9709a3 | 618 | /** |
| AnnaBridge | 189:f392fc9709a3 | 619 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 620 | */ |
| AnnaBridge | 189:f392fc9709a3 | 621 | |
| AnnaBridge | 189:f392fc9709a3 | 622 | /* Peripheral State methods **************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 623 | /** @addtogroup LCD_Exported_Functions_Group3 |
| AnnaBridge | 189:f392fc9709a3 | 624 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 625 | */ |
| AnnaBridge | 189:f392fc9709a3 | 626 | HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd); |
| AnnaBridge | 189:f392fc9709a3 | 627 | uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd); |
| AnnaBridge | 189:f392fc9709a3 | 628 | /** |
| AnnaBridge | 189:f392fc9709a3 | 629 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 630 | */ |
| AnnaBridge | 189:f392fc9709a3 | 631 | |
| AnnaBridge | 189:f392fc9709a3 | 632 | /** |
| AnnaBridge | 189:f392fc9709a3 | 633 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 634 | */ |
| AnnaBridge | 189:f392fc9709a3 | 635 | |
| AnnaBridge | 189:f392fc9709a3 | 636 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 637 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 638 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 639 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 640 | /** @defgroup LCD_Private_Macros LCD Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 641 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 642 | */ |
| AnnaBridge | 189:f392fc9709a3 | 643 | |
| AnnaBridge | 189:f392fc9709a3 | 644 | #define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 645 | ((__PRESCALER__) == LCD_PRESCALER_2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 646 | ((__PRESCALER__) == LCD_PRESCALER_4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 647 | ((__PRESCALER__) == LCD_PRESCALER_8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 648 | ((__PRESCALER__) == LCD_PRESCALER_16) || \ |
| AnnaBridge | 189:f392fc9709a3 | 649 | ((__PRESCALER__) == LCD_PRESCALER_32) || \ |
| AnnaBridge | 189:f392fc9709a3 | 650 | ((__PRESCALER__) == LCD_PRESCALER_64) || \ |
| AnnaBridge | 189:f392fc9709a3 | 651 | ((__PRESCALER__) == LCD_PRESCALER_128) || \ |
| AnnaBridge | 189:f392fc9709a3 | 652 | ((__PRESCALER__) == LCD_PRESCALER_256) || \ |
| AnnaBridge | 189:f392fc9709a3 | 653 | ((__PRESCALER__) == LCD_PRESCALER_512) || \ |
| AnnaBridge | 189:f392fc9709a3 | 654 | ((__PRESCALER__) == LCD_PRESCALER_1024) || \ |
| AnnaBridge | 189:f392fc9709a3 | 655 | ((__PRESCALER__) == LCD_PRESCALER_2048) || \ |
| AnnaBridge | 189:f392fc9709a3 | 656 | ((__PRESCALER__) == LCD_PRESCALER_4096) || \ |
| AnnaBridge | 189:f392fc9709a3 | 657 | ((__PRESCALER__) == LCD_PRESCALER_8192) || \ |
| AnnaBridge | 189:f392fc9709a3 | 658 | ((__PRESCALER__) == LCD_PRESCALER_16384) || \ |
| AnnaBridge | 189:f392fc9709a3 | 659 | ((__PRESCALER__) == LCD_PRESCALER_32768)) |
| AnnaBridge | 189:f392fc9709a3 | 660 | |
| AnnaBridge | 189:f392fc9709a3 | 661 | #define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \ |
| AnnaBridge | 189:f392fc9709a3 | 662 | ((__DIVIDER__) == LCD_DIVIDER_17) || \ |
| AnnaBridge | 189:f392fc9709a3 | 663 | ((__DIVIDER__) == LCD_DIVIDER_18) || \ |
| AnnaBridge | 189:f392fc9709a3 | 664 | ((__DIVIDER__) == LCD_DIVIDER_19) || \ |
| AnnaBridge | 189:f392fc9709a3 | 665 | ((__DIVIDER__) == LCD_DIVIDER_20) || \ |
| AnnaBridge | 189:f392fc9709a3 | 666 | ((__DIVIDER__) == LCD_DIVIDER_21) || \ |
| AnnaBridge | 189:f392fc9709a3 | 667 | ((__DIVIDER__) == LCD_DIVIDER_22) || \ |
| AnnaBridge | 189:f392fc9709a3 | 668 | ((__DIVIDER__) == LCD_DIVIDER_23) || \ |
| AnnaBridge | 189:f392fc9709a3 | 669 | ((__DIVIDER__) == LCD_DIVIDER_24) || \ |
| AnnaBridge | 189:f392fc9709a3 | 670 | ((__DIVIDER__) == LCD_DIVIDER_25) || \ |
| AnnaBridge | 189:f392fc9709a3 | 671 | ((__DIVIDER__) == LCD_DIVIDER_26) || \ |
| AnnaBridge | 189:f392fc9709a3 | 672 | ((__DIVIDER__) == LCD_DIVIDER_27) || \ |
| AnnaBridge | 189:f392fc9709a3 | 673 | ((__DIVIDER__) == LCD_DIVIDER_28) || \ |
| AnnaBridge | 189:f392fc9709a3 | 674 | ((__DIVIDER__) == LCD_DIVIDER_29) || \ |
| AnnaBridge | 189:f392fc9709a3 | 675 | ((__DIVIDER__) == LCD_DIVIDER_30) || \ |
| AnnaBridge | 189:f392fc9709a3 | 676 | ((__DIVIDER__) == LCD_DIVIDER_31)) |
| AnnaBridge | 189:f392fc9709a3 | 677 | |
| AnnaBridge | 189:f392fc9709a3 | 678 | #define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC) || \ |
| AnnaBridge | 189:f392fc9709a3 | 679 | ((__DUTY__) == LCD_DUTY_1_2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 680 | ((__DUTY__) == LCD_DUTY_1_3) || \ |
| AnnaBridge | 189:f392fc9709a3 | 681 | ((__DUTY__) == LCD_DUTY_1_4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 682 | ((__DUTY__) == LCD_DUTY_1_8)) |
| AnnaBridge | 189:f392fc9709a3 | 683 | |
| AnnaBridge | 189:f392fc9709a3 | 684 | #define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 685 | ((__BIAS__) == LCD_BIAS_1_2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 686 | ((__BIAS__) == LCD_BIAS_1_3)) |
| AnnaBridge | 189:f392fc9709a3 | 687 | |
| AnnaBridge | 189:f392fc9709a3 | 688 | #define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \ |
| AnnaBridge | 189:f392fc9709a3 | 689 | ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL)) |
| AnnaBridge | 189:f392fc9709a3 | 690 | |
| AnnaBridge | 189:f392fc9709a3 | 691 | |
| AnnaBridge | 189:f392fc9709a3 | 692 | #define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \ |
| AnnaBridge | 189:f392fc9709a3 | 693 | ((__DURATION__) == LCD_PULSEONDURATION_1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 694 | ((__DURATION__) == LCD_PULSEONDURATION_2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 695 | ((__DURATION__) == LCD_PULSEONDURATION_3) || \ |
| AnnaBridge | 189:f392fc9709a3 | 696 | ((__DURATION__) == LCD_PULSEONDURATION_4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 697 | ((__DURATION__) == LCD_PULSEONDURATION_5) || \ |
| AnnaBridge | 189:f392fc9709a3 | 698 | ((__DURATION__) == LCD_PULSEONDURATION_6) || \ |
| AnnaBridge | 189:f392fc9709a3 | 699 | ((__DURATION__) == LCD_PULSEONDURATION_7)) |
| AnnaBridge | 189:f392fc9709a3 | 700 | |
| AnnaBridge | 189:f392fc9709a3 | 701 | #define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \ |
| AnnaBridge | 189:f392fc9709a3 | 702 | ((__TIME__) == LCD_DEADTIME_1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 703 | ((__TIME__) == LCD_DEADTIME_2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 704 | ((__TIME__) == LCD_DEADTIME_3) || \ |
| AnnaBridge | 189:f392fc9709a3 | 705 | ((__TIME__) == LCD_DEADTIME_4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 706 | ((__TIME__) == LCD_DEADTIME_5) || \ |
| AnnaBridge | 189:f392fc9709a3 | 707 | ((__TIME__) == LCD_DEADTIME_6) || \ |
| AnnaBridge | 189:f392fc9709a3 | 708 | ((__TIME__) == LCD_DEADTIME_7)) |
| AnnaBridge | 189:f392fc9709a3 | 709 | |
| AnnaBridge | 189:f392fc9709a3 | 710 | #define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF) || \ |
| AnnaBridge | 189:f392fc9709a3 | 711 | ((__MODE__) == LCD_BLINKMODE_SEG0_COM0) || \ |
| AnnaBridge | 189:f392fc9709a3 | 712 | ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM) || \ |
| AnnaBridge | 189:f392fc9709a3 | 713 | ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM)) |
| AnnaBridge | 189:f392fc9709a3 | 714 | |
| AnnaBridge | 189:f392fc9709a3 | 715 | #define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 716 | ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16) || \ |
| AnnaBridge | 189:f392fc9709a3 | 717 | ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32) || \ |
| AnnaBridge | 189:f392fc9709a3 | 718 | ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64) || \ |
| AnnaBridge | 189:f392fc9709a3 | 719 | ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \ |
| AnnaBridge | 189:f392fc9709a3 | 720 | ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \ |
| AnnaBridge | 189:f392fc9709a3 | 721 | ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \ |
| AnnaBridge | 189:f392fc9709a3 | 722 | ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024)) |
| AnnaBridge | 189:f392fc9709a3 | 723 | |
| AnnaBridge | 189:f392fc9709a3 | 724 | #define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \ |
| AnnaBridge | 189:f392fc9709a3 | 725 | ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 726 | ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 727 | ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \ |
| AnnaBridge | 189:f392fc9709a3 | 728 | ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 729 | ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \ |
| AnnaBridge | 189:f392fc9709a3 | 730 | ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \ |
| AnnaBridge | 189:f392fc9709a3 | 731 | ((__CONTRAST__) == LCD_CONTRASTLEVEL_7)) |
| AnnaBridge | 189:f392fc9709a3 | 732 | |
| AnnaBridge | 189:f392fc9709a3 | 733 | #define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0) || \ |
| AnnaBridge | 189:f392fc9709a3 | 734 | ((__REGISTER__) == LCD_RAM_REGISTER1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 735 | ((__REGISTER__) == LCD_RAM_REGISTER2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 736 | ((__REGISTER__) == LCD_RAM_REGISTER3) || \ |
| AnnaBridge | 189:f392fc9709a3 | 737 | ((__REGISTER__) == LCD_RAM_REGISTER4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 738 | ((__REGISTER__) == LCD_RAM_REGISTER5) || \ |
| AnnaBridge | 189:f392fc9709a3 | 739 | ((__REGISTER__) == LCD_RAM_REGISTER6) || \ |
| AnnaBridge | 189:f392fc9709a3 | 740 | ((__REGISTER__) == LCD_RAM_REGISTER7) || \ |
| AnnaBridge | 189:f392fc9709a3 | 741 | ((__REGISTER__) == LCD_RAM_REGISTER8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 742 | ((__REGISTER__) == LCD_RAM_REGISTER9) || \ |
| AnnaBridge | 189:f392fc9709a3 | 743 | ((__REGISTER__) == LCD_RAM_REGISTER10) || \ |
| AnnaBridge | 189:f392fc9709a3 | 744 | ((__REGISTER__) == LCD_RAM_REGISTER11) || \ |
| AnnaBridge | 189:f392fc9709a3 | 745 | ((__REGISTER__) == LCD_RAM_REGISTER12) || \ |
| AnnaBridge | 189:f392fc9709a3 | 746 | ((__REGISTER__) == LCD_RAM_REGISTER13) || \ |
| AnnaBridge | 189:f392fc9709a3 | 747 | ((__REGISTER__) == LCD_RAM_REGISTER14) || \ |
| AnnaBridge | 189:f392fc9709a3 | 748 | ((__REGISTER__) == LCD_RAM_REGISTER15)) |
| AnnaBridge | 189:f392fc9709a3 | 749 | |
| AnnaBridge | 189:f392fc9709a3 | 750 | #define IS_LCD_HIGH_DRIVE(__VALUE__) (((__VALUE__) == LCD_HIGHDRIVE_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 751 | ((__VALUE__) == LCD_HIGHDRIVE_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 752 | |
| AnnaBridge | 189:f392fc9709a3 | 753 | #define IS_LCD_MUX_SEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 754 | ((__VALUE__) == LCD_MUXSEGMENT_DISABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 755 | |
| AnnaBridge | 189:f392fc9709a3 | 756 | /** |
| AnnaBridge | 189:f392fc9709a3 | 757 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 758 | */ |
| AnnaBridge | 189:f392fc9709a3 | 759 | |
| AnnaBridge | 189:f392fc9709a3 | 760 | /* Private functions ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 761 | /** @addtogroup LCD_Private_Functions |
| AnnaBridge | 189:f392fc9709a3 | 762 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 763 | */ |
| AnnaBridge | 189:f392fc9709a3 | 764 | |
| AnnaBridge | 189:f392fc9709a3 | 765 | HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd); |
| AnnaBridge | 189:f392fc9709a3 | 766 | |
| AnnaBridge | 189:f392fc9709a3 | 767 | /** |
| AnnaBridge | 189:f392fc9709a3 | 768 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 769 | */ |
| AnnaBridge | 189:f392fc9709a3 | 770 | |
| AnnaBridge | 189:f392fc9709a3 | 771 | /** |
| AnnaBridge | 189:f392fc9709a3 | 772 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 773 | */ |
| AnnaBridge | 189:f392fc9709a3 | 774 | |
| AnnaBridge | 189:f392fc9709a3 | 775 | /** |
| AnnaBridge | 189:f392fc9709a3 | 776 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 777 | */ |
| AnnaBridge | 189:f392fc9709a3 | 778 | |
| AnnaBridge | 189:f392fc9709a3 | 779 | #endif /* STM32L433xx || STM32L443xx || STM32L476xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ |
| AnnaBridge | 189:f392fc9709a3 | 780 | |
| AnnaBridge | 189:f392fc9709a3 | 781 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 782 | } |
| AnnaBridge | 189:f392fc9709a3 | 783 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 784 | |
| AnnaBridge | 189:f392fc9709a3 | 785 | #endif /* __STM32L4xx_HAL_LCD_H */ |
| AnnaBridge | 189:f392fc9709a3 | 786 | |
| AnnaBridge | 189:f392fc9709a3 | 787 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
