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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_hal_dma2d.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_hal_dma2d.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of DMA2D HAL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_HAL_DMA2D_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_HAL_DMA2D_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | #if defined(STM32L496xx) || defined(STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 45 | defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 48 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 49 | |
| AnnaBridge | 189:f392fc9709a3 | 50 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 51 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 52 | */ |
| AnnaBridge | 189:f392fc9709a3 | 53 | |
| AnnaBridge | 189:f392fc9709a3 | 54 | /** @addtogroup DMA2D DMA2D |
| AnnaBridge | 189:f392fc9709a3 | 55 | * @brief DMA2D HAL module driver |
| AnnaBridge | 189:f392fc9709a3 | 56 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 57 | */ |
| AnnaBridge | 189:f392fc9709a3 | 58 | |
| AnnaBridge | 189:f392fc9709a3 | 59 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 60 | /** @defgroup DMA2D_Exported_Types DMA2D Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 61 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 62 | */ |
| AnnaBridge | 189:f392fc9709a3 | 63 | #define MAX_DMA2D_LAYER 2U |
| AnnaBridge | 189:f392fc9709a3 | 64 | |
| AnnaBridge | 189:f392fc9709a3 | 65 | /** |
| AnnaBridge | 189:f392fc9709a3 | 66 | * @brief DMA2D color Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 67 | */ |
| AnnaBridge | 189:f392fc9709a3 | 68 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 69 | { |
| AnnaBridge | 189:f392fc9709a3 | 70 | uint32_t Blue; /*!< Configures the blue value. |
| AnnaBridge | 189:f392fc9709a3 | 71 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
| AnnaBridge | 189:f392fc9709a3 | 72 | |
| AnnaBridge | 189:f392fc9709a3 | 73 | uint32_t Green; /*!< Configures the green value. |
| AnnaBridge | 189:f392fc9709a3 | 74 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
| AnnaBridge | 189:f392fc9709a3 | 75 | |
| AnnaBridge | 189:f392fc9709a3 | 76 | uint32_t Red; /*!< Configures the red value. |
| AnnaBridge | 189:f392fc9709a3 | 77 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
| AnnaBridge | 189:f392fc9709a3 | 78 | } DMA2D_ColorTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 79 | |
| AnnaBridge | 189:f392fc9709a3 | 80 | /** |
| AnnaBridge | 189:f392fc9709a3 | 81 | * @brief DMA2D CLUT Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 82 | */ |
| AnnaBridge | 189:f392fc9709a3 | 83 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 84 | { |
| AnnaBridge | 189:f392fc9709a3 | 85 | uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ |
| AnnaBridge | 189:f392fc9709a3 | 86 | |
| AnnaBridge | 189:f392fc9709a3 | 87 | uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. |
| AnnaBridge | 189:f392fc9709a3 | 88 | This parameter can be one value of @ref DMA2D_CLUT_CM. */ |
| AnnaBridge | 189:f392fc9709a3 | 89 | |
| AnnaBridge | 189:f392fc9709a3 | 90 | uint32_t Size; /*!< Configures the DMA2D CLUT size. |
| AnnaBridge | 189:f392fc9709a3 | 91 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ |
| AnnaBridge | 189:f392fc9709a3 | 92 | } DMA2D_CLUTCfgTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 93 | |
| AnnaBridge | 189:f392fc9709a3 | 94 | /** |
| AnnaBridge | 189:f392fc9709a3 | 95 | * @brief DMA2D Init structure definition |
| AnnaBridge | 189:f392fc9709a3 | 96 | */ |
| AnnaBridge | 189:f392fc9709a3 | 97 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 98 | { |
| AnnaBridge | 189:f392fc9709a3 | 99 | uint32_t Mode; /*!< Configures the DMA2D transfer mode. |
| AnnaBridge | 189:f392fc9709a3 | 100 | This parameter can be one value of @ref DMA2D_Mode. */ |
| AnnaBridge | 189:f392fc9709a3 | 101 | |
| AnnaBridge | 189:f392fc9709a3 | 102 | uint32_t ColorMode; /*!< Configures the color format of the output image. |
| AnnaBridge | 189:f392fc9709a3 | 103 | This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ |
| AnnaBridge | 189:f392fc9709a3 | 104 | |
| AnnaBridge | 189:f392fc9709a3 | 105 | uint32_t OutputOffset; /*!< Specifies the Offset value. |
| AnnaBridge | 189:f392fc9709a3 | 106 | This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ |
| AnnaBridge | 189:f392fc9709a3 | 107 | |
| AnnaBridge | 189:f392fc9709a3 | 108 | uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. |
| AnnaBridge | 189:f392fc9709a3 | 109 | This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | |
| AnnaBridge | 189:f392fc9709a3 | 111 | uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) |
| AnnaBridge | 189:f392fc9709a3 | 112 | for the output pixel format converter. |
| AnnaBridge | 189:f392fc9709a3 | 113 | This parameter can be one value of @ref DMA2D_RB_Swap. */ |
| AnnaBridge | 189:f392fc9709a3 | 114 | |
| AnnaBridge | 189:f392fc9709a3 | 115 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 116 | uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). |
| AnnaBridge | 189:f392fc9709a3 | 117 | This parameter can be one value of @ref DMA2D_Bytes_Swap. */ |
| AnnaBridge | 189:f392fc9709a3 | 118 | |
| AnnaBridge | 189:f392fc9709a3 | 119 | uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. |
| AnnaBridge | 189:f392fc9709a3 | 120 | This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | |
| AnnaBridge | 189:f392fc9709a3 | 122 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 123 | |
| AnnaBridge | 189:f392fc9709a3 | 124 | } DMA2D_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 125 | |
| AnnaBridge | 189:f392fc9709a3 | 126 | |
| AnnaBridge | 189:f392fc9709a3 | 127 | /** |
| AnnaBridge | 189:f392fc9709a3 | 128 | * @brief DMA2D Layer structure definition |
| AnnaBridge | 189:f392fc9709a3 | 129 | */ |
| AnnaBridge | 189:f392fc9709a3 | 130 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 131 | { |
| AnnaBridge | 189:f392fc9709a3 | 132 | uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. |
| AnnaBridge | 189:f392fc9709a3 | 133 | This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ |
| AnnaBridge | 189:f392fc9709a3 | 134 | |
| AnnaBridge | 189:f392fc9709a3 | 135 | uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. |
| AnnaBridge | 189:f392fc9709a3 | 136 | This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | |
| AnnaBridge | 189:f392fc9709a3 | 138 | uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. |
| AnnaBridge | 189:f392fc9709a3 | 139 | This parameter can be one value of @ref DMA2D_Alpha_Mode. */ |
| AnnaBridge | 189:f392fc9709a3 | 140 | |
| AnnaBridge | 189:f392fc9709a3 | 141 | uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. |
| AnnaBridge | 189:f392fc9709a3 | 142 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. |
| AnnaBridge | 189:f392fc9709a3 | 143 | @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between |
| AnnaBridge | 189:f392fc9709a3 | 144 | Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where |
| AnnaBridge | 189:f392fc9709a3 | 145 | - InputAlpha[24:31] is the alpha value ALPHA[0:7] |
| AnnaBridge | 189:f392fc9709a3 | 146 | - InputAlpha[16:23] is the red value RED[0:7] |
| AnnaBridge | 189:f392fc9709a3 | 147 | - InputAlpha[8:15] is the green value GREEN[0:7] |
| AnnaBridge | 189:f392fc9709a3 | 148 | - InputAlpha[0:7] is the blue value BLUE[0:7]. */ |
| AnnaBridge | 189:f392fc9709a3 | 149 | |
| AnnaBridge | 189:f392fc9709a3 | 150 | uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. |
| AnnaBridge | 189:f392fc9709a3 | 151 | This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ |
| AnnaBridge | 189:f392fc9709a3 | 152 | |
| AnnaBridge | 189:f392fc9709a3 | 153 | uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). |
| AnnaBridge | 189:f392fc9709a3 | 154 | This parameter can be one value of @ref DMA2D_RB_Swap. */ |
| AnnaBridge | 189:f392fc9709a3 | 155 | } DMA2D_LayerCfgTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 156 | |
| AnnaBridge | 189:f392fc9709a3 | 157 | /** |
| AnnaBridge | 189:f392fc9709a3 | 158 | * @brief HAL DMA2D State structures definition |
| AnnaBridge | 189:f392fc9709a3 | 159 | */ |
| AnnaBridge | 189:f392fc9709a3 | 160 | typedef enum |
| AnnaBridge | 189:f392fc9709a3 | 161 | { |
| AnnaBridge | 189:f392fc9709a3 | 162 | HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 163 | HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
| AnnaBridge | 189:f392fc9709a3 | 164 | HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 165 | HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
| AnnaBridge | 189:f392fc9709a3 | 166 | HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ |
| AnnaBridge | 189:f392fc9709a3 | 167 | HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ |
| AnnaBridge | 189:f392fc9709a3 | 168 | }HAL_DMA2D_StateTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 169 | |
| AnnaBridge | 189:f392fc9709a3 | 170 | /** |
| AnnaBridge | 189:f392fc9709a3 | 171 | * @brief DMA2D handle Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 172 | */ |
| AnnaBridge | 189:f392fc9709a3 | 173 | typedef struct __DMA2D_HandleTypeDef |
| AnnaBridge | 189:f392fc9709a3 | 174 | { |
| AnnaBridge | 189:f392fc9709a3 | 175 | DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ |
| AnnaBridge | 189:f392fc9709a3 | 176 | |
| AnnaBridge | 189:f392fc9709a3 | 177 | DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ |
| AnnaBridge | 189:f392fc9709a3 | 178 | |
| AnnaBridge | 189:f392fc9709a3 | 179 | void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ |
| AnnaBridge | 189:f392fc9709a3 | 180 | |
| AnnaBridge | 189:f392fc9709a3 | 181 | void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | |
| AnnaBridge | 189:f392fc9709a3 | 183 | DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 184 | |
| AnnaBridge | 189:f392fc9709a3 | 185 | HAL_LockTypeDef Lock; /*!< DMA2D lock. */ |
| AnnaBridge | 189:f392fc9709a3 | 186 | |
| AnnaBridge | 189:f392fc9709a3 | 187 | __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ |
| AnnaBridge | 189:f392fc9709a3 | 188 | |
| AnnaBridge | 189:f392fc9709a3 | 189 | __IO uint32_t ErrorCode; /*!< DMA2D error code. */ |
| AnnaBridge | 189:f392fc9709a3 | 190 | } DMA2D_HandleTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 191 | /** |
| AnnaBridge | 189:f392fc9709a3 | 192 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 193 | */ |
| AnnaBridge | 189:f392fc9709a3 | 194 | |
| AnnaBridge | 189:f392fc9709a3 | 195 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 196 | /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 197 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 198 | */ |
| AnnaBridge | 189:f392fc9709a3 | 199 | |
| AnnaBridge | 189:f392fc9709a3 | 200 | /** @defgroup DMA2D_Error_Code DMA2D Error Code |
| AnnaBridge | 189:f392fc9709a3 | 201 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 202 | */ |
| AnnaBridge | 189:f392fc9709a3 | 203 | #define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
| AnnaBridge | 189:f392fc9709a3 | 204 | #define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ |
| AnnaBridge | 189:f392fc9709a3 | 205 | #define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */ |
| AnnaBridge | 189:f392fc9709a3 | 206 | #define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */ |
| AnnaBridge | 189:f392fc9709a3 | 207 | #define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ |
| AnnaBridge | 189:f392fc9709a3 | 208 | /** |
| AnnaBridge | 189:f392fc9709a3 | 209 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 210 | */ |
| AnnaBridge | 189:f392fc9709a3 | 211 | |
| AnnaBridge | 189:f392fc9709a3 | 212 | /** @defgroup DMA2D_Mode DMA2D Mode |
| AnnaBridge | 189:f392fc9709a3 | 213 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 214 | */ |
| AnnaBridge | 189:f392fc9709a3 | 215 | #define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */ |
| AnnaBridge | 189:f392fc9709a3 | 216 | #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ |
| AnnaBridge | 189:f392fc9709a3 | 217 | #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ |
| AnnaBridge | 189:f392fc9709a3 | 218 | #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ |
| AnnaBridge | 189:f392fc9709a3 | 219 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 220 | #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ |
| AnnaBridge | 189:f392fc9709a3 | 221 | #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ |
| AnnaBridge | 189:f392fc9709a3 | 222 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 223 | /** |
| AnnaBridge | 189:f392fc9709a3 | 224 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 225 | */ |
| AnnaBridge | 189:f392fc9709a3 | 226 | |
| AnnaBridge | 189:f392fc9709a3 | 227 | /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode |
| AnnaBridge | 189:f392fc9709a3 | 228 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 229 | */ |
| AnnaBridge | 189:f392fc9709a3 | 230 | #define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 231 | #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 232 | #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 233 | #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 234 | #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 235 | /** |
| AnnaBridge | 189:f392fc9709a3 | 236 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 237 | */ |
| AnnaBridge | 189:f392fc9709a3 | 238 | |
| AnnaBridge | 189:f392fc9709a3 | 239 | /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode |
| AnnaBridge | 189:f392fc9709a3 | 240 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 241 | */ |
| AnnaBridge | 189:f392fc9709a3 | 242 | #define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 243 | #define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 244 | #define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 245 | #define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 246 | #define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 247 | #define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 248 | #define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 249 | #define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 250 | #define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 251 | #define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 252 | #define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 253 | /** |
| AnnaBridge | 189:f392fc9709a3 | 254 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 255 | */ |
| AnnaBridge | 189:f392fc9709a3 | 256 | |
| AnnaBridge | 189:f392fc9709a3 | 257 | /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode |
| AnnaBridge | 189:f392fc9709a3 | 258 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 259 | */ |
| AnnaBridge | 189:f392fc9709a3 | 260 | #define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */ |
| AnnaBridge | 189:f392fc9709a3 | 261 | #define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */ |
| AnnaBridge | 189:f392fc9709a3 | 262 | #define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value |
| AnnaBridge | 189:f392fc9709a3 | 263 | with original alpha channel value */ |
| AnnaBridge | 189:f392fc9709a3 | 264 | /** |
| AnnaBridge | 189:f392fc9709a3 | 265 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 266 | */ |
| AnnaBridge | 189:f392fc9709a3 | 267 | |
| AnnaBridge | 189:f392fc9709a3 | 268 | /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion |
| AnnaBridge | 189:f392fc9709a3 | 269 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 270 | */ |
| AnnaBridge | 189:f392fc9709a3 | 271 | #define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */ |
| AnnaBridge | 189:f392fc9709a3 | 272 | #define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) /*!< Invert the alpha channel value */ |
| AnnaBridge | 189:f392fc9709a3 | 273 | /** |
| AnnaBridge | 189:f392fc9709a3 | 274 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 275 | */ |
| AnnaBridge | 189:f392fc9709a3 | 276 | |
| AnnaBridge | 189:f392fc9709a3 | 277 | /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap |
| AnnaBridge | 189:f392fc9709a3 | 278 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 279 | */ |
| AnnaBridge | 189:f392fc9709a3 | 280 | #define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) /*!< Select regular mode (RGB or ARGB) */ |
| AnnaBridge | 189:f392fc9709a3 | 281 | #define DMA2D_RB_SWAP ((uint32_t)0x00000001U) /*!< Select swap mode (BGR or ABGR) */ |
| AnnaBridge | 189:f392fc9709a3 | 282 | /** |
| AnnaBridge | 189:f392fc9709a3 | 283 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 284 | */ |
| AnnaBridge | 189:f392fc9709a3 | 285 | |
| AnnaBridge | 189:f392fc9709a3 | 286 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 287 | /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode |
| AnnaBridge | 189:f392fc9709a3 | 288 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 289 | */ |
| AnnaBridge | 189:f392fc9709a3 | 290 | #define DMA2D_LOM_PIXELS ((uint32_t)0x00000000U) /*!< Line offsets expressed in pixels */ |
| AnnaBridge | 189:f392fc9709a3 | 291 | #define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ |
| AnnaBridge | 189:f392fc9709a3 | 292 | /** |
| AnnaBridge | 189:f392fc9709a3 | 293 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 294 | */ |
| AnnaBridge | 189:f392fc9709a3 | 295 | |
| AnnaBridge | 189:f392fc9709a3 | 296 | /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap |
| AnnaBridge | 189:f392fc9709a3 | 297 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 298 | */ |
| AnnaBridge | 189:f392fc9709a3 | 299 | #define DMA2D_BYTES_REGULAR ((uint32_t)0x00000000U) /*!< Bytes in regular order in output FIFO */ |
| AnnaBridge | 189:f392fc9709a3 | 300 | #define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ |
| AnnaBridge | 189:f392fc9709a3 | 301 | /** |
| AnnaBridge | 189:f392fc9709a3 | 302 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 303 | */ |
| AnnaBridge | 189:f392fc9709a3 | 304 | |
| AnnaBridge | 189:f392fc9709a3 | 305 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 306 | |
| AnnaBridge | 189:f392fc9709a3 | 307 | /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode |
| AnnaBridge | 189:f392fc9709a3 | 308 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 309 | */ |
| AnnaBridge | 189:f392fc9709a3 | 310 | #define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 311 | #define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */ |
| AnnaBridge | 189:f392fc9709a3 | 312 | /** |
| AnnaBridge | 189:f392fc9709a3 | 313 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 314 | */ |
| AnnaBridge | 189:f392fc9709a3 | 315 | |
| AnnaBridge | 189:f392fc9709a3 | 316 | /** @defgroup DMA2D_Interrupts DMA2D Interrupts |
| AnnaBridge | 189:f392fc9709a3 | 317 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 318 | */ |
| AnnaBridge | 189:f392fc9709a3 | 319 | #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 320 | #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 321 | #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 322 | #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 323 | #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 324 | #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 325 | /** |
| AnnaBridge | 189:f392fc9709a3 | 326 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 327 | */ |
| AnnaBridge | 189:f392fc9709a3 | 328 | |
| AnnaBridge | 189:f392fc9709a3 | 329 | /** @defgroup DMA2D_Flags DMA2D Flags |
| AnnaBridge | 189:f392fc9709a3 | 330 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 331 | */ |
| AnnaBridge | 189:f392fc9709a3 | 332 | #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ |
| AnnaBridge | 189:f392fc9709a3 | 333 | #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ |
| AnnaBridge | 189:f392fc9709a3 | 334 | #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ |
| AnnaBridge | 189:f392fc9709a3 | 335 | #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ |
| AnnaBridge | 189:f392fc9709a3 | 336 | #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ |
| AnnaBridge | 189:f392fc9709a3 | 337 | #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ |
| AnnaBridge | 189:f392fc9709a3 | 338 | /** |
| AnnaBridge | 189:f392fc9709a3 | 339 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 340 | */ |
| AnnaBridge | 189:f392fc9709a3 | 341 | |
| AnnaBridge | 189:f392fc9709a3 | 342 | /** @defgroup DMA2D_Aliases DMA2D API Aliases |
| AnnaBridge | 189:f392fc9709a3 | 343 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 344 | */ |
| AnnaBridge | 189:f392fc9709a3 | 345 | #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ |
| AnnaBridge | 189:f392fc9709a3 | 346 | /** |
| AnnaBridge | 189:f392fc9709a3 | 347 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 348 | */ |
| AnnaBridge | 189:f392fc9709a3 | 349 | |
| AnnaBridge | 189:f392fc9709a3 | 350 | |
| AnnaBridge | 189:f392fc9709a3 | 351 | /** |
| AnnaBridge | 189:f392fc9709a3 | 352 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 353 | */ |
| AnnaBridge | 189:f392fc9709a3 | 354 | /* Exported macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 355 | /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 356 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 357 | */ |
| AnnaBridge | 189:f392fc9709a3 | 358 | |
| AnnaBridge | 189:f392fc9709a3 | 359 | /** @brief Reset DMA2D handle state |
| AnnaBridge | 189:f392fc9709a3 | 360 | * @param __HANDLE__: specifies the DMA2D handle. |
| AnnaBridge | 189:f392fc9709a3 | 361 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 362 | */ |
| AnnaBridge | 189:f392fc9709a3 | 363 | #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) |
| AnnaBridge | 189:f392fc9709a3 | 364 | |
| AnnaBridge | 189:f392fc9709a3 | 365 | /** |
| AnnaBridge | 189:f392fc9709a3 | 366 | * @brief Enable the DMA2D. |
| AnnaBridge | 189:f392fc9709a3 | 367 | * @param __HANDLE__: DMA2D handle |
| AnnaBridge | 189:f392fc9709a3 | 368 | * @retval None. |
| AnnaBridge | 189:f392fc9709a3 | 369 | */ |
| AnnaBridge | 189:f392fc9709a3 | 370 | #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) |
| AnnaBridge | 189:f392fc9709a3 | 371 | |
| AnnaBridge | 189:f392fc9709a3 | 372 | |
| AnnaBridge | 189:f392fc9709a3 | 373 | /* Interrupt & Flag management */ |
| AnnaBridge | 189:f392fc9709a3 | 374 | /** |
| AnnaBridge | 189:f392fc9709a3 | 375 | * @brief Get the DMA2D pending flags. |
| AnnaBridge | 189:f392fc9709a3 | 376 | * @param __HANDLE__: DMA2D handle |
| AnnaBridge | 189:f392fc9709a3 | 377 | * @param __FLAG__: flag to check. |
| AnnaBridge | 189:f392fc9709a3 | 378 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 379 | * @arg DMA2D_FLAG_CE: Configuration error flag |
| AnnaBridge | 189:f392fc9709a3 | 380 | * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag |
| AnnaBridge | 189:f392fc9709a3 | 381 | * @arg DMA2D_FLAG_CAE: CLUT access error flag |
| AnnaBridge | 189:f392fc9709a3 | 382 | * @arg DMA2D_FLAG_TW: Transfer Watermark flag |
| AnnaBridge | 189:f392fc9709a3 | 383 | * @arg DMA2D_FLAG_TC: Transfer complete flag |
| AnnaBridge | 189:f392fc9709a3 | 384 | * @arg DMA2D_FLAG_TE: Transfer error flag |
| AnnaBridge | 189:f392fc9709a3 | 385 | * @retval The state of FLAG. |
| AnnaBridge | 189:f392fc9709a3 | 386 | */ |
| AnnaBridge | 189:f392fc9709a3 | 387 | #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) |
| AnnaBridge | 189:f392fc9709a3 | 388 | |
| AnnaBridge | 189:f392fc9709a3 | 389 | /** |
| AnnaBridge | 189:f392fc9709a3 | 390 | * @brief Clear the DMA2D pending flags. |
| AnnaBridge | 189:f392fc9709a3 | 391 | * @param __HANDLE__: DMA2D handle |
| AnnaBridge | 189:f392fc9709a3 | 392 | * @param __FLAG__: specifies the flag to clear. |
| AnnaBridge | 189:f392fc9709a3 | 393 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 394 | * @arg DMA2D_FLAG_CE: Configuration error flag |
| AnnaBridge | 189:f392fc9709a3 | 395 | * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag |
| AnnaBridge | 189:f392fc9709a3 | 396 | * @arg DMA2D_FLAG_CAE: CLUT access error flag |
| AnnaBridge | 189:f392fc9709a3 | 397 | * @arg DMA2D_FLAG_TW: Transfer Watermark flag |
| AnnaBridge | 189:f392fc9709a3 | 398 | * @arg DMA2D_FLAG_TC: Transfer complete flag |
| AnnaBridge | 189:f392fc9709a3 | 399 | * @arg DMA2D_FLAG_TE: Transfer error flag |
| AnnaBridge | 189:f392fc9709a3 | 400 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 401 | */ |
| AnnaBridge | 189:f392fc9709a3 | 402 | #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) |
| AnnaBridge | 189:f392fc9709a3 | 403 | |
| AnnaBridge | 189:f392fc9709a3 | 404 | /** |
| AnnaBridge | 189:f392fc9709a3 | 405 | * @brief Enable the specified DMA2D interrupts. |
| AnnaBridge | 189:f392fc9709a3 | 406 | * @param __HANDLE__: DMA2D handle |
| AnnaBridge | 189:f392fc9709a3 | 407 | * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. |
| AnnaBridge | 189:f392fc9709a3 | 408 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 409 | * @arg DMA2D_IT_CE: Configuration error interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 410 | * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 411 | * @arg DMA2D_IT_CAE: CLUT access error interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 412 | * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 413 | * @arg DMA2D_IT_TC: Transfer complete interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 414 | * @arg DMA2D_IT_TE: Transfer error interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 415 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 416 | */ |
| AnnaBridge | 189:f392fc9709a3 | 417 | #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 418 | |
| AnnaBridge | 189:f392fc9709a3 | 419 | /** |
| AnnaBridge | 189:f392fc9709a3 | 420 | * @brief Disable the specified DMA2D interrupts. |
| AnnaBridge | 189:f392fc9709a3 | 421 | * @param __HANDLE__: DMA2D handle |
| AnnaBridge | 189:f392fc9709a3 | 422 | * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. |
| AnnaBridge | 189:f392fc9709a3 | 423 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 424 | * @arg DMA2D_IT_CE: Configuration error interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 425 | * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 426 | * @arg DMA2D_IT_CAE: CLUT access error interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 427 | * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 428 | * @arg DMA2D_IT_TC: Transfer complete interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 429 | * @arg DMA2D_IT_TE: Transfer error interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 430 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 431 | */ |
| AnnaBridge | 189:f392fc9709a3 | 432 | #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 433 | |
| AnnaBridge | 189:f392fc9709a3 | 434 | /** |
| AnnaBridge | 189:f392fc9709a3 | 435 | * @brief Check whether the specified DMA2D interrupt source is enabled or not. |
| AnnaBridge | 189:f392fc9709a3 | 436 | * @param __HANDLE__: DMA2D handle |
| AnnaBridge | 189:f392fc9709a3 | 437 | * @param __INTERRUPT__: specifies the DMA2D interrupt source to check. |
| AnnaBridge | 189:f392fc9709a3 | 438 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 439 | * @arg DMA2D_IT_CE: Configuration error interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 440 | * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 441 | * @arg DMA2D_IT_CAE: CLUT access error interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 442 | * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 443 | * @arg DMA2D_IT_TC: Transfer complete interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 444 | * @arg DMA2D_IT_TE: Transfer error interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 445 | * @retval The state of INTERRUPT source. |
| AnnaBridge | 189:f392fc9709a3 | 446 | */ |
| AnnaBridge | 189:f392fc9709a3 | 447 | #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 448 | |
| AnnaBridge | 189:f392fc9709a3 | 449 | /** |
| AnnaBridge | 189:f392fc9709a3 | 450 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 451 | */ |
| AnnaBridge | 189:f392fc9709a3 | 452 | |
| AnnaBridge | 189:f392fc9709a3 | 453 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 454 | /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 455 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 456 | */ |
| AnnaBridge | 189:f392fc9709a3 | 457 | |
| AnnaBridge | 189:f392fc9709a3 | 458 | /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 189:f392fc9709a3 | 459 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 460 | */ |
| AnnaBridge | 189:f392fc9709a3 | 461 | |
| AnnaBridge | 189:f392fc9709a3 | 462 | /* Initialization and de-initialization functions *******************************/ |
| AnnaBridge | 189:f392fc9709a3 | 463 | HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 464 | HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 465 | void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 466 | void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 467 | |
| AnnaBridge | 189:f392fc9709a3 | 468 | /** |
| AnnaBridge | 189:f392fc9709a3 | 469 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 470 | */ |
| AnnaBridge | 189:f392fc9709a3 | 471 | |
| AnnaBridge | 189:f392fc9709a3 | 472 | |
| AnnaBridge | 189:f392fc9709a3 | 473 | /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions |
| AnnaBridge | 189:f392fc9709a3 | 474 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 475 | */ |
| AnnaBridge | 189:f392fc9709a3 | 476 | |
| AnnaBridge | 189:f392fc9709a3 | 477 | /* IO operation functions *******************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 478 | HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); |
| AnnaBridge | 189:f392fc9709a3 | 479 | HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); |
| AnnaBridge | 189:f392fc9709a3 | 480 | HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); |
| AnnaBridge | 189:f392fc9709a3 | 481 | HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); |
| AnnaBridge | 189:f392fc9709a3 | 482 | HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 483 | HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 484 | HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 485 | HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
| AnnaBridge | 189:f392fc9709a3 | 486 | HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); |
| AnnaBridge | 189:f392fc9709a3 | 487 | HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); |
| AnnaBridge | 189:f392fc9709a3 | 488 | HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
| AnnaBridge | 189:f392fc9709a3 | 489 | HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
| AnnaBridge | 189:f392fc9709a3 | 490 | HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
| AnnaBridge | 189:f392fc9709a3 | 491 | HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 492 | void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 493 | void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 494 | void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 495 | |
| AnnaBridge | 189:f392fc9709a3 | 496 | /** |
| AnnaBridge | 189:f392fc9709a3 | 497 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 498 | */ |
| AnnaBridge | 189:f392fc9709a3 | 499 | |
| AnnaBridge | 189:f392fc9709a3 | 500 | /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions |
| AnnaBridge | 189:f392fc9709a3 | 501 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 502 | */ |
| AnnaBridge | 189:f392fc9709a3 | 503 | |
| AnnaBridge | 189:f392fc9709a3 | 504 | /* Peripheral Control functions *************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 505 | HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
| AnnaBridge | 189:f392fc9709a3 | 506 | HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); |
| AnnaBridge | 189:f392fc9709a3 | 507 | HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); |
| AnnaBridge | 189:f392fc9709a3 | 508 | HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 509 | HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 510 | HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); |
| AnnaBridge | 189:f392fc9709a3 | 511 | |
| AnnaBridge | 189:f392fc9709a3 | 512 | /** |
| AnnaBridge | 189:f392fc9709a3 | 513 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 514 | */ |
| AnnaBridge | 189:f392fc9709a3 | 515 | |
| AnnaBridge | 189:f392fc9709a3 | 516 | /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions |
| AnnaBridge | 189:f392fc9709a3 | 517 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 518 | */ |
| AnnaBridge | 189:f392fc9709a3 | 519 | |
| AnnaBridge | 189:f392fc9709a3 | 520 | /* Peripheral State functions ***************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 521 | HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 522 | uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); |
| AnnaBridge | 189:f392fc9709a3 | 523 | |
| AnnaBridge | 189:f392fc9709a3 | 524 | /** |
| AnnaBridge | 189:f392fc9709a3 | 525 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 526 | */ |
| AnnaBridge | 189:f392fc9709a3 | 527 | |
| AnnaBridge | 189:f392fc9709a3 | 528 | /** |
| AnnaBridge | 189:f392fc9709a3 | 529 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 530 | */ |
| AnnaBridge | 189:f392fc9709a3 | 531 | |
| AnnaBridge | 189:f392fc9709a3 | 532 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 533 | |
| AnnaBridge | 189:f392fc9709a3 | 534 | /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants |
| AnnaBridge | 189:f392fc9709a3 | 535 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 536 | */ |
| AnnaBridge | 189:f392fc9709a3 | 537 | |
| AnnaBridge | 189:f392fc9709a3 | 538 | /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark |
| AnnaBridge | 189:f392fc9709a3 | 539 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 540 | */ |
| AnnaBridge | 189:f392fc9709a3 | 541 | #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ |
| AnnaBridge | 189:f392fc9709a3 | 542 | /** |
| AnnaBridge | 189:f392fc9709a3 | 543 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 544 | */ |
| AnnaBridge | 189:f392fc9709a3 | 545 | |
| AnnaBridge | 189:f392fc9709a3 | 546 | /** @defgroup DMA2D_Color_Value DMA2D Color Value |
| AnnaBridge | 189:f392fc9709a3 | 547 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 548 | */ |
| AnnaBridge | 189:f392fc9709a3 | 549 | #define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */ |
| AnnaBridge | 189:f392fc9709a3 | 550 | /** |
| AnnaBridge | 189:f392fc9709a3 | 551 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 552 | */ |
| AnnaBridge | 189:f392fc9709a3 | 553 | |
| AnnaBridge | 189:f392fc9709a3 | 554 | /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers |
| AnnaBridge | 189:f392fc9709a3 | 555 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 556 | */ |
| AnnaBridge | 189:f392fc9709a3 | 557 | #define DMA2D_MAX_LAYER 2 /*!< DMA2D maximum number of layers */ |
| AnnaBridge | 189:f392fc9709a3 | 558 | /** |
| AnnaBridge | 189:f392fc9709a3 | 559 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 560 | */ |
| AnnaBridge | 189:f392fc9709a3 | 561 | |
| AnnaBridge | 189:f392fc9709a3 | 562 | /** @defgroup DMA2D_Offset DMA2D Offset |
| AnnaBridge | 189:f392fc9709a3 | 563 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 564 | */ |
| AnnaBridge | 189:f392fc9709a3 | 565 | #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */ |
| AnnaBridge | 189:f392fc9709a3 | 566 | /** |
| AnnaBridge | 189:f392fc9709a3 | 567 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 568 | */ |
| AnnaBridge | 189:f392fc9709a3 | 569 | |
| AnnaBridge | 189:f392fc9709a3 | 570 | /** @defgroup DMA2D_Size DMA2D Size |
| AnnaBridge | 189:f392fc9709a3 | 571 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 572 | */ |
| AnnaBridge | 189:f392fc9709a3 | 573 | #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */ |
| AnnaBridge | 189:f392fc9709a3 | 574 | #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */ |
| AnnaBridge | 189:f392fc9709a3 | 575 | /** |
| AnnaBridge | 189:f392fc9709a3 | 576 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 577 | */ |
| AnnaBridge | 189:f392fc9709a3 | 578 | |
| AnnaBridge | 189:f392fc9709a3 | 579 | /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size |
| AnnaBridge | 189:f392fc9709a3 | 580 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 581 | */ |
| AnnaBridge | 189:f392fc9709a3 | 582 | #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D CLUT size */ |
| AnnaBridge | 189:f392fc9709a3 | 583 | /** |
| AnnaBridge | 189:f392fc9709a3 | 584 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 585 | */ |
| AnnaBridge | 189:f392fc9709a3 | 586 | |
| AnnaBridge | 189:f392fc9709a3 | 587 | /** |
| AnnaBridge | 189:f392fc9709a3 | 588 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 589 | */ |
| AnnaBridge | 189:f392fc9709a3 | 590 | |
| AnnaBridge | 189:f392fc9709a3 | 591 | |
| AnnaBridge | 189:f392fc9709a3 | 592 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 593 | /** @defgroup DMA2D_Private_Macros DMA2D Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 594 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 595 | */ |
| AnnaBridge | 189:f392fc9709a3 | 596 | #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER) |
| AnnaBridge | 189:f392fc9709a3 | 597 | |
| AnnaBridge | 189:f392fc9709a3 | 598 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 599 | #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ |
| AnnaBridge | 189:f392fc9709a3 | 600 | ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ |
| AnnaBridge | 189:f392fc9709a3 | 601 | ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) |
| AnnaBridge | 189:f392fc9709a3 | 602 | #else |
| AnnaBridge | 189:f392fc9709a3 | 603 | #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ |
| AnnaBridge | 189:f392fc9709a3 | 604 | ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) |
| AnnaBridge | 189:f392fc9709a3 | 605 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 606 | |
| AnnaBridge | 189:f392fc9709a3 | 607 | #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ |
| AnnaBridge | 189:f392fc9709a3 | 608 | ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ |
| AnnaBridge | 189:f392fc9709a3 | 609 | ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) |
| AnnaBridge | 189:f392fc9709a3 | 610 | #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) |
| AnnaBridge | 189:f392fc9709a3 | 611 | #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) |
| AnnaBridge | 189:f392fc9709a3 | 612 | #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) |
| AnnaBridge | 189:f392fc9709a3 | 613 | #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) |
| AnnaBridge | 189:f392fc9709a3 | 614 | #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ |
| AnnaBridge | 189:f392fc9709a3 | 615 | ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ |
| AnnaBridge | 189:f392fc9709a3 | 616 | ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 617 | ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ |
| AnnaBridge | 189:f392fc9709a3 | 618 | ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 619 | ((INPUT_CM) == DMA2D_INPUT_A4)) |
| AnnaBridge | 189:f392fc9709a3 | 620 | #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ |
| AnnaBridge | 189:f392fc9709a3 | 621 | ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ |
| AnnaBridge | 189:f392fc9709a3 | 622 | ((AlphaMode) == DMA2D_COMBINE_ALPHA)) |
| AnnaBridge | 189:f392fc9709a3 | 623 | |
| AnnaBridge | 189:f392fc9709a3 | 624 | #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ |
| AnnaBridge | 189:f392fc9709a3 | 625 | ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) |
| AnnaBridge | 189:f392fc9709a3 | 626 | |
| AnnaBridge | 189:f392fc9709a3 | 627 | #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ |
| AnnaBridge | 189:f392fc9709a3 | 628 | ((RB_Swap) == DMA2D_RB_SWAP)) |
| AnnaBridge | 189:f392fc9709a3 | 629 | |
| AnnaBridge | 189:f392fc9709a3 | 630 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 631 | #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ |
| AnnaBridge | 189:f392fc9709a3 | 632 | ((LOM) == DMA2D_LOM_BYTES)) |
| AnnaBridge | 189:f392fc9709a3 | 633 | |
| AnnaBridge | 189:f392fc9709a3 | 634 | #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ |
| AnnaBridge | 189:f392fc9709a3 | 635 | ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) |
| AnnaBridge | 189:f392fc9709a3 | 636 | |
| AnnaBridge | 189:f392fc9709a3 | 637 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 638 | |
| AnnaBridge | 189:f392fc9709a3 | 639 | #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) |
| AnnaBridge | 189:f392fc9709a3 | 640 | #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) |
| AnnaBridge | 189:f392fc9709a3 | 641 | #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) |
| AnnaBridge | 189:f392fc9709a3 | 642 | #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 643 | ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ |
| AnnaBridge | 189:f392fc9709a3 | 644 | ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) |
| AnnaBridge | 189:f392fc9709a3 | 645 | #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 646 | ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ |
| AnnaBridge | 189:f392fc9709a3 | 647 | ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) |
| AnnaBridge | 189:f392fc9709a3 | 648 | /** |
| AnnaBridge | 189:f392fc9709a3 | 649 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 650 | */ |
| AnnaBridge | 189:f392fc9709a3 | 651 | |
| AnnaBridge | 189:f392fc9709a3 | 652 | /** |
| AnnaBridge | 189:f392fc9709a3 | 653 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 654 | */ |
| AnnaBridge | 189:f392fc9709a3 | 655 | |
| AnnaBridge | 189:f392fc9709a3 | 656 | /** |
| AnnaBridge | 189:f392fc9709a3 | 657 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 658 | */ |
| AnnaBridge | 189:f392fc9709a3 | 659 | |
| AnnaBridge | 189:f392fc9709a3 | 660 | #endif /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 661 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 662 | |
| AnnaBridge | 189:f392fc9709a3 | 663 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 664 | } |
| AnnaBridge | 189:f392fc9709a3 | 665 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 666 | |
| AnnaBridge | 189:f392fc9709a3 | 667 | #endif /* __STM32L4xx_HAL_DMA2D_H */ |
| AnnaBridge | 189:f392fc9709a3 | 668 | |
| AnnaBridge | 189:f392fc9709a3 | 669 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
