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mbed library sources. Supersedes mbed-src.

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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_hal_dma.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /**
AnnaBridge 189:f392fc9709a3 2 ******************************************************************************
AnnaBridge 189:f392fc9709a3 3 * @file stm32l4xx_hal_dma.h
AnnaBridge 189:f392fc9709a3 4 * @author MCD Application Team
AnnaBridge 189:f392fc9709a3 5 * @brief Header file of DMA HAL module.
AnnaBridge 189:f392fc9709a3 6 ******************************************************************************
AnnaBridge 189:f392fc9709a3 7 * @attention
AnnaBridge 189:f392fc9709a3 8 *
AnnaBridge 189:f392fc9709a3 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 189:f392fc9709a3 10 *
AnnaBridge 189:f392fc9709a3 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 12 * are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 189:f392fc9709a3 14 * this list of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 189:f392fc9709a3 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 189:f392fc9709a3 17 * and/or other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 189:f392fc9709a3 19 * may be used to endorse or promote products derived from this software
AnnaBridge 189:f392fc9709a3 20 * without specific prior written permission.
AnnaBridge 189:f392fc9709a3 21 *
AnnaBridge 189:f392fc9709a3 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 189:f392fc9709a3 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 189:f392fc9709a3 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 189:f392fc9709a3 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 189:f392fc9709a3 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 189:f392fc9709a3 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 189:f392fc9709a3 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 189:f392fc9709a3 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 189:f392fc9709a3 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 189:f392fc9709a3 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 32 *
AnnaBridge 189:f392fc9709a3 33 ******************************************************************************
AnnaBridge 189:f392fc9709a3 34 */
AnnaBridge 189:f392fc9709a3 35
AnnaBridge 189:f392fc9709a3 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 189:f392fc9709a3 37 #ifndef __STM32L4xx_HAL_DMA_H
AnnaBridge 189:f392fc9709a3 38 #define __STM32L4xx_HAL_DMA_H
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 41 extern "C" {
AnnaBridge 189:f392fc9709a3 42 #endif
AnnaBridge 189:f392fc9709a3 43
AnnaBridge 189:f392fc9709a3 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 45 #include "stm32l4xx_hal_def.h"
AnnaBridge 189:f392fc9709a3 46
AnnaBridge 189:f392fc9709a3 47 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 189:f392fc9709a3 48 * @{
AnnaBridge 189:f392fc9709a3 49 */
AnnaBridge 189:f392fc9709a3 50
AnnaBridge 189:f392fc9709a3 51 /** @addtogroup DMA
AnnaBridge 189:f392fc9709a3 52 * @{
AnnaBridge 189:f392fc9709a3 53 */
AnnaBridge 189:f392fc9709a3 54
AnnaBridge 189:f392fc9709a3 55 /* Exported types ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 56 /** @defgroup DMA_Exported_Types DMA Exported Types
AnnaBridge 189:f392fc9709a3 57 * @{
AnnaBridge 189:f392fc9709a3 58 */
AnnaBridge 189:f392fc9709a3 59
AnnaBridge 189:f392fc9709a3 60 /**
AnnaBridge 189:f392fc9709a3 61 * @brief DMA Configuration Structure definition
AnnaBridge 189:f392fc9709a3 62 */
AnnaBridge 189:f392fc9709a3 63 typedef struct
AnnaBridge 189:f392fc9709a3 64 {
AnnaBridge 189:f392fc9709a3 65 uint32_t Request; /*!< Specifies the request selected for the specified channel.
AnnaBridge 189:f392fc9709a3 66 This parameter can be a value of @ref DMA_request */
AnnaBridge 189:f392fc9709a3 67
AnnaBridge 189:f392fc9709a3 68 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge 189:f392fc9709a3 69 from memory to memory or from peripheral to memory.
AnnaBridge 189:f392fc9709a3 70 This parameter can be a value of @ref DMA_Data_transfer_direction */
AnnaBridge 189:f392fc9709a3 71
AnnaBridge 189:f392fc9709a3 72 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
AnnaBridge 189:f392fc9709a3 73 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
AnnaBridge 189:f392fc9709a3 74
AnnaBridge 189:f392fc9709a3 75 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
AnnaBridge 189:f392fc9709a3 76 This parameter can be a value of @ref DMA_Memory_incremented_mode */
AnnaBridge 189:f392fc9709a3 77
AnnaBridge 189:f392fc9709a3 78 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
AnnaBridge 189:f392fc9709a3 79 This parameter can be a value of @ref DMA_Peripheral_data_size */
AnnaBridge 189:f392fc9709a3 80
AnnaBridge 189:f392fc9709a3 81 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
AnnaBridge 189:f392fc9709a3 82 This parameter can be a value of @ref DMA_Memory_data_size */
AnnaBridge 189:f392fc9709a3 83
AnnaBridge 189:f392fc9709a3 84 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
AnnaBridge 189:f392fc9709a3 85 This parameter can be a value of @ref DMA_mode
AnnaBridge 189:f392fc9709a3 86 @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge 189:f392fc9709a3 87 data transfer is configured on the selected Channel */
AnnaBridge 189:f392fc9709a3 88
AnnaBridge 189:f392fc9709a3 89 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
AnnaBridge 189:f392fc9709a3 90 This parameter can be a value of @ref DMA_Priority_level */
AnnaBridge 189:f392fc9709a3 91 } DMA_InitTypeDef;
AnnaBridge 189:f392fc9709a3 92
AnnaBridge 189:f392fc9709a3 93 /**
AnnaBridge 189:f392fc9709a3 94 * @brief HAL DMA State structures definition
AnnaBridge 189:f392fc9709a3 95 */
AnnaBridge 189:f392fc9709a3 96 typedef enum
AnnaBridge 189:f392fc9709a3 97 {
AnnaBridge 189:f392fc9709a3 98 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
AnnaBridge 189:f392fc9709a3 99 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
AnnaBridge 189:f392fc9709a3 100 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
AnnaBridge 189:f392fc9709a3 101 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
AnnaBridge 189:f392fc9709a3 102 }HAL_DMA_StateTypeDef;
AnnaBridge 189:f392fc9709a3 103
AnnaBridge 189:f392fc9709a3 104 /**
AnnaBridge 189:f392fc9709a3 105 * @brief HAL DMA Error Code structure definition
AnnaBridge 189:f392fc9709a3 106 */
AnnaBridge 189:f392fc9709a3 107 typedef enum
AnnaBridge 189:f392fc9709a3 108 {
AnnaBridge 189:f392fc9709a3 109 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
AnnaBridge 189:f392fc9709a3 110 HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
AnnaBridge 189:f392fc9709a3 111 }HAL_DMA_LevelCompleteTypeDef;
AnnaBridge 189:f392fc9709a3 112
AnnaBridge 189:f392fc9709a3 113
AnnaBridge 189:f392fc9709a3 114 /**
AnnaBridge 189:f392fc9709a3 115 * @brief HAL DMA Callback ID structure definition
AnnaBridge 189:f392fc9709a3 116 */
AnnaBridge 189:f392fc9709a3 117 typedef enum
AnnaBridge 189:f392fc9709a3 118 {
AnnaBridge 189:f392fc9709a3 119 HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */
AnnaBridge 189:f392fc9709a3 120 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */
AnnaBridge 189:f392fc9709a3 121 HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */
AnnaBridge 189:f392fc9709a3 122 HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */
AnnaBridge 189:f392fc9709a3 123 HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
AnnaBridge 189:f392fc9709a3 124
AnnaBridge 189:f392fc9709a3 125 }HAL_DMA_CallbackIDTypeDef;
AnnaBridge 189:f392fc9709a3 126
AnnaBridge 189:f392fc9709a3 127 /**
AnnaBridge 189:f392fc9709a3 128 * @brief DMA handle Structure definition
AnnaBridge 189:f392fc9709a3 129 */
AnnaBridge 189:f392fc9709a3 130 typedef struct __DMA_HandleTypeDef
AnnaBridge 189:f392fc9709a3 131 {
AnnaBridge 189:f392fc9709a3 132 DMA_Channel_TypeDef *Instance; /*!< Register base address */
AnnaBridge 189:f392fc9709a3 133
AnnaBridge 189:f392fc9709a3 134 DMA_InitTypeDef Init; /*!< DMA communication parameters */
AnnaBridge 189:f392fc9709a3 135
AnnaBridge 189:f392fc9709a3 136 HAL_LockTypeDef Lock; /*!< DMA locking object */
AnnaBridge 189:f392fc9709a3 137
AnnaBridge 189:f392fc9709a3 138 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
AnnaBridge 189:f392fc9709a3 139
AnnaBridge 189:f392fc9709a3 140 void *Parent; /*!< Parent object state */
AnnaBridge 189:f392fc9709a3 141
AnnaBridge 189:f392fc9709a3 142 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
AnnaBridge 189:f392fc9709a3 143
AnnaBridge 189:f392fc9709a3 144 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
AnnaBridge 189:f392fc9709a3 145
AnnaBridge 189:f392fc9709a3 146 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
AnnaBridge 189:f392fc9709a3 147
AnnaBridge 189:f392fc9709a3 148 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
AnnaBridge 189:f392fc9709a3 149
AnnaBridge 189:f392fc9709a3 150 __IO uint32_t ErrorCode; /*!< DMA Error code */
AnnaBridge 189:f392fc9709a3 151
AnnaBridge 189:f392fc9709a3 152 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
AnnaBridge 189:f392fc9709a3 153
AnnaBridge 189:f392fc9709a3 154 uint32_t ChannelIndex; /*!< DMA Channel Index */
AnnaBridge 189:f392fc9709a3 155
AnnaBridge 189:f392fc9709a3 156 #if defined(DMAMUX1)
AnnaBridge 189:f392fc9709a3 157 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
AnnaBridge 189:f392fc9709a3 158
AnnaBridge 189:f392fc9709a3 159 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
AnnaBridge 189:f392fc9709a3 160
AnnaBridge 189:f392fc9709a3 161 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
AnnaBridge 189:f392fc9709a3 162
AnnaBridge 189:f392fc9709a3 163 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
AnnaBridge 189:f392fc9709a3 164
AnnaBridge 189:f392fc9709a3 165 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
AnnaBridge 189:f392fc9709a3 166
AnnaBridge 189:f392fc9709a3 167 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
AnnaBridge 189:f392fc9709a3 168
AnnaBridge 189:f392fc9709a3 169 #endif /* DMAMUX1 */
AnnaBridge 189:f392fc9709a3 170
AnnaBridge 189:f392fc9709a3 171 }DMA_HandleTypeDef;
AnnaBridge 189:f392fc9709a3 172 /**
AnnaBridge 189:f392fc9709a3 173 * @}
AnnaBridge 189:f392fc9709a3 174 */
AnnaBridge 189:f392fc9709a3 175
AnnaBridge 189:f392fc9709a3 176 /* Exported constants --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 177
AnnaBridge 189:f392fc9709a3 178 /** @defgroup DMA_Exported_Constants DMA Exported Constants
AnnaBridge 189:f392fc9709a3 179 * @{
AnnaBridge 189:f392fc9709a3 180 */
AnnaBridge 189:f392fc9709a3 181
AnnaBridge 189:f392fc9709a3 182 /** @defgroup DMA_Error_Code DMA Error Code
AnnaBridge 189:f392fc9709a3 183 * @{
AnnaBridge 189:f392fc9709a3 184 */
AnnaBridge 189:f392fc9709a3 185 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
AnnaBridge 189:f392fc9709a3 186 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
AnnaBridge 189:f392fc9709a3 187 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< Abort requested with no Xfer ongoing */
AnnaBridge 189:f392fc9709a3 188 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
AnnaBridge 189:f392fc9709a3 189 #define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */
AnnaBridge 189:f392fc9709a3 190 #define HAL_DMA_ERROR_SYNC ((uint32_t)0x00000200U) /*!< DMAMUX sync overrun error */
AnnaBridge 189:f392fc9709a3 191 #define HAL_DMA_ERROR_REQGEN ((uint32_t)0x00000400U) /*!< DMAMUX request generator overrun error */
AnnaBridge 189:f392fc9709a3 192
AnnaBridge 189:f392fc9709a3 193 /**
AnnaBridge 189:f392fc9709a3 194 * @}
AnnaBridge 189:f392fc9709a3 195 */
AnnaBridge 189:f392fc9709a3 196
AnnaBridge 189:f392fc9709a3 197 /** @defgroup DMA_request DMA request
AnnaBridge 189:f392fc9709a3 198 * @{
AnnaBridge 189:f392fc9709a3 199 */
AnnaBridge 189:f392fc9709a3 200 #if !defined (DMAMUX1)
AnnaBridge 189:f392fc9709a3 201
AnnaBridge 189:f392fc9709a3 202 #define DMA_REQUEST_0 ((uint32_t)0x00000000)
AnnaBridge 189:f392fc9709a3 203 #define DMA_REQUEST_1 ((uint32_t)0x00000001)
AnnaBridge 189:f392fc9709a3 204 #define DMA_REQUEST_2 ((uint32_t)0x00000002)
AnnaBridge 189:f392fc9709a3 205 #define DMA_REQUEST_3 ((uint32_t)0x00000003)
AnnaBridge 189:f392fc9709a3 206 #define DMA_REQUEST_4 ((uint32_t)0x00000004)
AnnaBridge 189:f392fc9709a3 207 #define DMA_REQUEST_5 ((uint32_t)0x00000005)
AnnaBridge 189:f392fc9709a3 208 #define DMA_REQUEST_6 ((uint32_t)0x00000006)
AnnaBridge 189:f392fc9709a3 209 #define DMA_REQUEST_7 ((uint32_t)0x00000007)
AnnaBridge 189:f392fc9709a3 210
AnnaBridge 189:f392fc9709a3 211 #endif
AnnaBridge 189:f392fc9709a3 212
AnnaBridge 189:f392fc9709a3 213 #if defined(DMAMUX1)
AnnaBridge 189:f392fc9709a3 214
AnnaBridge 189:f392fc9709a3 215 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
AnnaBridge 189:f392fc9709a3 216
AnnaBridge 189:f392fc9709a3 217 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */
AnnaBridge 189:f392fc9709a3 218 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */
AnnaBridge 189:f392fc9709a3 219 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */
AnnaBridge 189:f392fc9709a3 220 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */
AnnaBridge 189:f392fc9709a3 221
AnnaBridge 189:f392fc9709a3 222 #define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */
AnnaBridge 189:f392fc9709a3 223
AnnaBridge 189:f392fc9709a3 224 #define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */
AnnaBridge 189:f392fc9709a3 225 #define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */
AnnaBridge 189:f392fc9709a3 226
AnnaBridge 189:f392fc9709a3 227 #define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */
AnnaBridge 189:f392fc9709a3 228 #define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */
AnnaBridge 189:f392fc9709a3 229
AnnaBridge 189:f392fc9709a3 230 #define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */
AnnaBridge 189:f392fc9709a3 231 #define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */
AnnaBridge 189:f392fc9709a3 232 #define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */
AnnaBridge 189:f392fc9709a3 233 #define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */
AnnaBridge 189:f392fc9709a3 234 #define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */
AnnaBridge 189:f392fc9709a3 235 #define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */
AnnaBridge 189:f392fc9709a3 236
AnnaBridge 189:f392fc9709a3 237 #define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */
AnnaBridge 189:f392fc9709a3 238 #define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */
AnnaBridge 189:f392fc9709a3 239 #define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */
AnnaBridge 189:f392fc9709a3 240 #define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */
AnnaBridge 189:f392fc9709a3 241 #define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */
AnnaBridge 189:f392fc9709a3 242 #define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */
AnnaBridge 189:f392fc9709a3 243 #define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */
AnnaBridge 189:f392fc9709a3 244 #define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */
AnnaBridge 189:f392fc9709a3 245
AnnaBridge 189:f392fc9709a3 246 #define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */
AnnaBridge 189:f392fc9709a3 247 #define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */
AnnaBridge 189:f392fc9709a3 248 #define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */
AnnaBridge 189:f392fc9709a3 249 #define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */
AnnaBridge 189:f392fc9709a3 250 #define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */
AnnaBridge 189:f392fc9709a3 251 #define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */
AnnaBridge 189:f392fc9709a3 252
AnnaBridge 189:f392fc9709a3 253 #define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */
AnnaBridge 189:f392fc9709a3 254 #define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */
AnnaBridge 189:f392fc9709a3 255 #define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */
AnnaBridge 189:f392fc9709a3 256 #define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */
AnnaBridge 189:f392fc9709a3 257
AnnaBridge 189:f392fc9709a3 258 #define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */
AnnaBridge 189:f392fc9709a3 259 #define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */
AnnaBridge 189:f392fc9709a3 260
AnnaBridge 189:f392fc9709a3 261 #define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */
AnnaBridge 189:f392fc9709a3 262 #define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */
AnnaBridge 189:f392fc9709a3 263 #define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */
AnnaBridge 189:f392fc9709a3 264 #define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */
AnnaBridge 189:f392fc9709a3 265
AnnaBridge 189:f392fc9709a3 266 #define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */
AnnaBridge 189:f392fc9709a3 267 #define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */
AnnaBridge 189:f392fc9709a3 268
AnnaBridge 189:f392fc9709a3 269 #define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */
AnnaBridge 189:f392fc9709a3 270 #define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */
AnnaBridge 189:f392fc9709a3 271 #define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */
AnnaBridge 189:f392fc9709a3 272 #define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */
AnnaBridge 189:f392fc9709a3 273 #define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */
AnnaBridge 189:f392fc9709a3 274 #define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */
AnnaBridge 189:f392fc9709a3 275 #define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */
AnnaBridge 189:f392fc9709a3 276
AnnaBridge 189:f392fc9709a3 277 #define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */
AnnaBridge 189:f392fc9709a3 278 #define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */
AnnaBridge 189:f392fc9709a3 279 #define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */
AnnaBridge 189:f392fc9709a3 280 #define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */
AnnaBridge 189:f392fc9709a3 281 #define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */
AnnaBridge 189:f392fc9709a3 282 #define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */
AnnaBridge 189:f392fc9709a3 283 #define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */
AnnaBridge 189:f392fc9709a3 284
AnnaBridge 189:f392fc9709a3 285 #define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */
AnnaBridge 189:f392fc9709a3 286 #define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */
AnnaBridge 189:f392fc9709a3 287 #define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */
AnnaBridge 189:f392fc9709a3 288 #define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */
AnnaBridge 189:f392fc9709a3 289 #define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */
AnnaBridge 189:f392fc9709a3 290
AnnaBridge 189:f392fc9709a3 291 #define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */
AnnaBridge 189:f392fc9709a3 292 #define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */
AnnaBridge 189:f392fc9709a3 293 #define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */
AnnaBridge 189:f392fc9709a3 294 #define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */
AnnaBridge 189:f392fc9709a3 295 #define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */
AnnaBridge 189:f392fc9709a3 296 #define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */
AnnaBridge 189:f392fc9709a3 297
AnnaBridge 189:f392fc9709a3 298 #define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */
AnnaBridge 189:f392fc9709a3 299 #define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */
AnnaBridge 189:f392fc9709a3 300 #define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */
AnnaBridge 189:f392fc9709a3 301 #define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */
AnnaBridge 189:f392fc9709a3 302 #define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */
AnnaBridge 189:f392fc9709a3 303
AnnaBridge 189:f392fc9709a3 304 #define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */
AnnaBridge 189:f392fc9709a3 305 #define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */
AnnaBridge 189:f392fc9709a3 306 #define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */
AnnaBridge 189:f392fc9709a3 307 #define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */
AnnaBridge 189:f392fc9709a3 308 #define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */
AnnaBridge 189:f392fc9709a3 309 #define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */
AnnaBridge 189:f392fc9709a3 310
AnnaBridge 189:f392fc9709a3 311 #define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */
AnnaBridge 189:f392fc9709a3 312 #define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */
AnnaBridge 189:f392fc9709a3 313 #define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */
AnnaBridge 189:f392fc9709a3 314 #define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */
AnnaBridge 189:f392fc9709a3 315
AnnaBridge 189:f392fc9709a3 316 #define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */
AnnaBridge 189:f392fc9709a3 317 #define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */
AnnaBridge 189:f392fc9709a3 318 #define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */
AnnaBridge 189:f392fc9709a3 319 #define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */
AnnaBridge 189:f392fc9709a3 320
AnnaBridge 189:f392fc9709a3 321 #define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */
AnnaBridge 189:f392fc9709a3 322 #define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */
AnnaBridge 189:f392fc9709a3 323 #define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */
AnnaBridge 189:f392fc9709a3 324 #define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */
AnnaBridge 189:f392fc9709a3 325
AnnaBridge 189:f392fc9709a3 326 #define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */
AnnaBridge 189:f392fc9709a3 327
AnnaBridge 189:f392fc9709a3 328 #define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */
AnnaBridge 189:f392fc9709a3 329 #define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */
AnnaBridge 189:f392fc9709a3 330
AnnaBridge 189:f392fc9709a3 331 #define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */
AnnaBridge 189:f392fc9709a3 332
AnnaBridge 189:f392fc9709a3 333 #endif /* DMAMUX1 */
AnnaBridge 189:f392fc9709a3 334
AnnaBridge 189:f392fc9709a3 335 /**
AnnaBridge 189:f392fc9709a3 336 * @}
AnnaBridge 189:f392fc9709a3 337 */
AnnaBridge 189:f392fc9709a3 338
AnnaBridge 189:f392fc9709a3 339 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
AnnaBridge 189:f392fc9709a3 340 * @{
AnnaBridge 189:f392fc9709a3 341 */
AnnaBridge 189:f392fc9709a3 342 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
AnnaBridge 189:f392fc9709a3 343 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
AnnaBridge 189:f392fc9709a3 344 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
AnnaBridge 189:f392fc9709a3 345 /**
AnnaBridge 189:f392fc9709a3 346 * @}
AnnaBridge 189:f392fc9709a3 347 */
AnnaBridge 189:f392fc9709a3 348
AnnaBridge 189:f392fc9709a3 349 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
AnnaBridge 189:f392fc9709a3 350 * @{
AnnaBridge 189:f392fc9709a3 351 */
AnnaBridge 189:f392fc9709a3 352 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
AnnaBridge 189:f392fc9709a3 353 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
AnnaBridge 189:f392fc9709a3 354 /**
AnnaBridge 189:f392fc9709a3 355 * @}
AnnaBridge 189:f392fc9709a3 356 */
AnnaBridge 189:f392fc9709a3 357
AnnaBridge 189:f392fc9709a3 358 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
AnnaBridge 189:f392fc9709a3 359 * @{
AnnaBridge 189:f392fc9709a3 360 */
AnnaBridge 189:f392fc9709a3 361 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
AnnaBridge 189:f392fc9709a3 362 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
AnnaBridge 189:f392fc9709a3 363 /**
AnnaBridge 189:f392fc9709a3 364 * @}
AnnaBridge 189:f392fc9709a3 365 */
AnnaBridge 189:f392fc9709a3 366
AnnaBridge 189:f392fc9709a3 367 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
AnnaBridge 189:f392fc9709a3 368 * @{
AnnaBridge 189:f392fc9709a3 369 */
AnnaBridge 189:f392fc9709a3 370 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
AnnaBridge 189:f392fc9709a3 371 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
AnnaBridge 189:f392fc9709a3 372 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
AnnaBridge 189:f392fc9709a3 373 /**
AnnaBridge 189:f392fc9709a3 374 * @}
AnnaBridge 189:f392fc9709a3 375 */
AnnaBridge 189:f392fc9709a3 376
AnnaBridge 189:f392fc9709a3 377 /** @defgroup DMA_Memory_data_size DMA Memory data size
AnnaBridge 189:f392fc9709a3 378 * @{
AnnaBridge 189:f392fc9709a3 379 */
AnnaBridge 189:f392fc9709a3 380 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
AnnaBridge 189:f392fc9709a3 381 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
AnnaBridge 189:f392fc9709a3 382 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
AnnaBridge 189:f392fc9709a3 383 /**
AnnaBridge 189:f392fc9709a3 384 * @}
AnnaBridge 189:f392fc9709a3 385 */
AnnaBridge 189:f392fc9709a3 386
AnnaBridge 189:f392fc9709a3 387 /** @defgroup DMA_mode DMA mode
AnnaBridge 189:f392fc9709a3 388 * @{
AnnaBridge 189:f392fc9709a3 389 */
AnnaBridge 189:f392fc9709a3 390 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
AnnaBridge 189:f392fc9709a3 391 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
AnnaBridge 189:f392fc9709a3 392 /**
AnnaBridge 189:f392fc9709a3 393 * @}
AnnaBridge 189:f392fc9709a3 394 */
AnnaBridge 189:f392fc9709a3 395
AnnaBridge 189:f392fc9709a3 396 /** @defgroup DMA_Priority_level DMA Priority level
AnnaBridge 189:f392fc9709a3 397 * @{
AnnaBridge 189:f392fc9709a3 398 */
AnnaBridge 189:f392fc9709a3 399 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
AnnaBridge 189:f392fc9709a3 400 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
AnnaBridge 189:f392fc9709a3 401 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
AnnaBridge 189:f392fc9709a3 402 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
AnnaBridge 189:f392fc9709a3 403 /**
AnnaBridge 189:f392fc9709a3 404 * @}
AnnaBridge 189:f392fc9709a3 405 */
AnnaBridge 189:f392fc9709a3 406
AnnaBridge 189:f392fc9709a3 407
AnnaBridge 189:f392fc9709a3 408 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
AnnaBridge 189:f392fc9709a3 409 * @{
AnnaBridge 189:f392fc9709a3 410 */
AnnaBridge 189:f392fc9709a3 411 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
AnnaBridge 189:f392fc9709a3 412 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
AnnaBridge 189:f392fc9709a3 413 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
AnnaBridge 189:f392fc9709a3 414 /**
AnnaBridge 189:f392fc9709a3 415 * @}
AnnaBridge 189:f392fc9709a3 416 */
AnnaBridge 189:f392fc9709a3 417
AnnaBridge 189:f392fc9709a3 418 /** @defgroup DMA_flag_definitions DMA flag definitions
AnnaBridge 189:f392fc9709a3 419 * @{
AnnaBridge 189:f392fc9709a3 420 */
AnnaBridge 189:f392fc9709a3 421 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
AnnaBridge 189:f392fc9709a3 422 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
AnnaBridge 189:f392fc9709a3 423 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
AnnaBridge 189:f392fc9709a3 424 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
AnnaBridge 189:f392fc9709a3 425 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
AnnaBridge 189:f392fc9709a3 426 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
AnnaBridge 189:f392fc9709a3 427 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
AnnaBridge 189:f392fc9709a3 428 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
AnnaBridge 189:f392fc9709a3 429 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
AnnaBridge 189:f392fc9709a3 430 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
AnnaBridge 189:f392fc9709a3 431 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
AnnaBridge 189:f392fc9709a3 432 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
AnnaBridge 189:f392fc9709a3 433 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
AnnaBridge 189:f392fc9709a3 434 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
AnnaBridge 189:f392fc9709a3 435 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
AnnaBridge 189:f392fc9709a3 436 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
AnnaBridge 189:f392fc9709a3 437 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
AnnaBridge 189:f392fc9709a3 438 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
AnnaBridge 189:f392fc9709a3 439 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
AnnaBridge 189:f392fc9709a3 440 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
AnnaBridge 189:f392fc9709a3 441 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
AnnaBridge 189:f392fc9709a3 442 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
AnnaBridge 189:f392fc9709a3 443 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
AnnaBridge 189:f392fc9709a3 444 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
AnnaBridge 189:f392fc9709a3 445 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
AnnaBridge 189:f392fc9709a3 446 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
AnnaBridge 189:f392fc9709a3 447 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
AnnaBridge 189:f392fc9709a3 448 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
AnnaBridge 189:f392fc9709a3 449 /**
AnnaBridge 189:f392fc9709a3 450 * @}
AnnaBridge 189:f392fc9709a3 451 */
AnnaBridge 189:f392fc9709a3 452
AnnaBridge 189:f392fc9709a3 453 /**
AnnaBridge 189:f392fc9709a3 454 * @}
AnnaBridge 189:f392fc9709a3 455 */
AnnaBridge 189:f392fc9709a3 456
AnnaBridge 189:f392fc9709a3 457 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 458 /** @defgroup DMA_Exported_Macros DMA Exported Macros
AnnaBridge 189:f392fc9709a3 459 * @{
AnnaBridge 189:f392fc9709a3 460 */
AnnaBridge 189:f392fc9709a3 461
AnnaBridge 189:f392fc9709a3 462 /** @brief Reset DMA handle state.
AnnaBridge 189:f392fc9709a3 463 * @param __HANDLE__: DMA handle
AnnaBridge 189:f392fc9709a3 464 * @retval None
AnnaBridge 189:f392fc9709a3 465 */
AnnaBridge 189:f392fc9709a3 466 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
AnnaBridge 189:f392fc9709a3 467
AnnaBridge 189:f392fc9709a3 468 /**
AnnaBridge 189:f392fc9709a3 469 * @brief Enable the specified DMA Channel.
AnnaBridge 189:f392fc9709a3 470 * @param __HANDLE__: DMA handle
AnnaBridge 189:f392fc9709a3 471 * @retval None
AnnaBridge 189:f392fc9709a3 472 */
AnnaBridge 189:f392fc9709a3 473 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
AnnaBridge 189:f392fc9709a3 474
AnnaBridge 189:f392fc9709a3 475 /**
AnnaBridge 189:f392fc9709a3 476 * @brief Disable the specified DMA Channel.
AnnaBridge 189:f392fc9709a3 477 * @param __HANDLE__: DMA handle
AnnaBridge 189:f392fc9709a3 478 * @retval None
AnnaBridge 189:f392fc9709a3 479 */
AnnaBridge 189:f392fc9709a3 480 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
AnnaBridge 189:f392fc9709a3 481
AnnaBridge 189:f392fc9709a3 482
AnnaBridge 189:f392fc9709a3 483 /* Interrupt & Flag management */
AnnaBridge 189:f392fc9709a3 484
AnnaBridge 189:f392fc9709a3 485 /**
AnnaBridge 189:f392fc9709a3 486 * @brief Return the current DMA Channel transfer complete flag.
AnnaBridge 189:f392fc9709a3 487 * @param __HANDLE__: DMA handle
AnnaBridge 189:f392fc9709a3 488 * @retval The specified transfer complete flag index.
AnnaBridge 189:f392fc9709a3 489 */
AnnaBridge 189:f392fc9709a3 490
AnnaBridge 189:f392fc9709a3 491 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 492 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
AnnaBridge 189:f392fc9709a3 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
AnnaBridge 189:f392fc9709a3 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
AnnaBridge 189:f392fc9709a3 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
AnnaBridge 189:f392fc9709a3 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
AnnaBridge 189:f392fc9709a3 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
AnnaBridge 189:f392fc9709a3 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
AnnaBridge 189:f392fc9709a3 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
AnnaBridge 189:f392fc9709a3 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
AnnaBridge 189:f392fc9709a3 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
AnnaBridge 189:f392fc9709a3 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
AnnaBridge 189:f392fc9709a3 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
AnnaBridge 189:f392fc9709a3 504 DMA_FLAG_TC7)
AnnaBridge 189:f392fc9709a3 505
AnnaBridge 189:f392fc9709a3 506 /**
AnnaBridge 189:f392fc9709a3 507 * @brief Return the current DMA Channel half transfer complete flag.
AnnaBridge 189:f392fc9709a3 508 * @param __HANDLE__: DMA handle
AnnaBridge 189:f392fc9709a3 509 * @retval The specified half transfer complete flag index.
AnnaBridge 189:f392fc9709a3 510 */
AnnaBridge 189:f392fc9709a3 511 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
AnnaBridge 189:f392fc9709a3 512 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
AnnaBridge 189:f392fc9709a3 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
AnnaBridge 189:f392fc9709a3 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
AnnaBridge 189:f392fc9709a3 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
AnnaBridge 189:f392fc9709a3 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
AnnaBridge 189:f392fc9709a3 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
AnnaBridge 189:f392fc9709a3 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
AnnaBridge 189:f392fc9709a3 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
AnnaBridge 189:f392fc9709a3 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
AnnaBridge 189:f392fc9709a3 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
AnnaBridge 189:f392fc9709a3 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
AnnaBridge 189:f392fc9709a3 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
AnnaBridge 189:f392fc9709a3 524 DMA_FLAG_HT7)
AnnaBridge 189:f392fc9709a3 525
AnnaBridge 189:f392fc9709a3 526 /**
AnnaBridge 189:f392fc9709a3 527 * @brief Return the current DMA Channel transfer error flag.
AnnaBridge 189:f392fc9709a3 528 * @param __HANDLE__: DMA handle
AnnaBridge 189:f392fc9709a3 529 * @retval The specified transfer error flag index.
AnnaBridge 189:f392fc9709a3 530 */
AnnaBridge 189:f392fc9709a3 531 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
AnnaBridge 189:f392fc9709a3 532 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
AnnaBridge 189:f392fc9709a3 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
AnnaBridge 189:f392fc9709a3 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
AnnaBridge 189:f392fc9709a3 535 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
AnnaBridge 189:f392fc9709a3 536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
AnnaBridge 189:f392fc9709a3 537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
AnnaBridge 189:f392fc9709a3 538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
AnnaBridge 189:f392fc9709a3 539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
AnnaBridge 189:f392fc9709a3 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
AnnaBridge 189:f392fc9709a3 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
AnnaBridge 189:f392fc9709a3 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
AnnaBridge 189:f392fc9709a3 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
AnnaBridge 189:f392fc9709a3 544 DMA_FLAG_TE7)
AnnaBridge 189:f392fc9709a3 545
AnnaBridge 189:f392fc9709a3 546 /**
AnnaBridge 189:f392fc9709a3 547 * @brief Return the current DMA Channel Global interrupt flag.
AnnaBridge 189:f392fc9709a3 548 * @param __HANDLE__: DMA handle
AnnaBridge 189:f392fc9709a3 549 * @retval The specified transfer error flag index.
AnnaBridge 189:f392fc9709a3 550 */
AnnaBridge 189:f392fc9709a3 551 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
AnnaBridge 189:f392fc9709a3 552 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
AnnaBridge 189:f392fc9709a3 553 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
AnnaBridge 189:f392fc9709a3 554 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
AnnaBridge 189:f392fc9709a3 555 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
AnnaBridge 189:f392fc9709a3 556 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
AnnaBridge 189:f392fc9709a3 557 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
AnnaBridge 189:f392fc9709a3 558 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
AnnaBridge 189:f392fc9709a3 559 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
AnnaBridge 189:f392fc9709a3 560 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
AnnaBridge 189:f392fc9709a3 561 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
AnnaBridge 189:f392fc9709a3 562 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
AnnaBridge 189:f392fc9709a3 563 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
AnnaBridge 189:f392fc9709a3 564 DMA_ISR_GIF7)
AnnaBridge 189:f392fc9709a3 565
AnnaBridge 189:f392fc9709a3 566 /**
AnnaBridge 189:f392fc9709a3 567 * @brief Get the DMA Channel pending flags.
AnnaBridge 189:f392fc9709a3 568 * @param __HANDLE__: DMA handle
AnnaBridge 189:f392fc9709a3 569 * @param __FLAG__: Get the specified flag.
AnnaBridge 189:f392fc9709a3 570 * This parameter can be any combination of the following values:
AnnaBridge 189:f392fc9709a3 571 * @arg DMA_FLAG_TCx: Transfer complete flag
AnnaBridge 189:f392fc9709a3 572 * @arg DMA_FLAG_HTx: Half transfer complete flag
AnnaBridge 189:f392fc9709a3 573 * @arg DMA_FLAG_TEx: Transfer error flag
AnnaBridge 189:f392fc9709a3 574 * @arg DMA_FLAG_GLx: Global interrupt flag
AnnaBridge 189:f392fc9709a3 575 * Where x can be from 1 to 7 to select the DMA Channel x flag.
AnnaBridge 189:f392fc9709a3 576 * @retval The state of FLAG (SET or RESET).
AnnaBridge 189:f392fc9709a3 577 */
AnnaBridge 189:f392fc9709a3 578 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
AnnaBridge 189:f392fc9709a3 579 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
AnnaBridge 189:f392fc9709a3 580
AnnaBridge 189:f392fc9709a3 581 /**
AnnaBridge 189:f392fc9709a3 582 * @brief Clear the DMA Channel pending flags.
AnnaBridge 189:f392fc9709a3 583 * @param __HANDLE__: DMA handle
AnnaBridge 189:f392fc9709a3 584 * @param __FLAG__: specifies the flag to clear.
AnnaBridge 189:f392fc9709a3 585 * This parameter can be any combination of the following values:
AnnaBridge 189:f392fc9709a3 586 * @arg DMA_FLAG_TCx: Transfer complete flag
AnnaBridge 189:f392fc9709a3 587 * @arg DMA_FLAG_HTx: Half transfer complete flag
AnnaBridge 189:f392fc9709a3 588 * @arg DMA_FLAG_TEx: Transfer error flag
AnnaBridge 189:f392fc9709a3 589 * @arg DMA_FLAG_GLx: Global interrupt flag
AnnaBridge 189:f392fc9709a3 590 * Where x can be from 1 to 7 to select the DMA Channel x flag.
AnnaBridge 189:f392fc9709a3 591 * @retval None
AnnaBridge 189:f392fc9709a3 592 */
AnnaBridge 189:f392fc9709a3 593 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
AnnaBridge 189:f392fc9709a3 594 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
AnnaBridge 189:f392fc9709a3 595
AnnaBridge 189:f392fc9709a3 596 /**
AnnaBridge 189:f392fc9709a3 597 * @brief Enable the specified DMA Channel interrupts.
AnnaBridge 189:f392fc9709a3 598 * @param __HANDLE__: DMA handle
AnnaBridge 189:f392fc9709a3 599 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 189:f392fc9709a3 600 * This parameter can be any combination of the following values:
AnnaBridge 189:f392fc9709a3 601 * @arg DMA_IT_TC: Transfer complete interrupt mask
AnnaBridge 189:f392fc9709a3 602 * @arg DMA_IT_HT: Half transfer complete interrupt mask
AnnaBridge 189:f392fc9709a3 603 * @arg DMA_IT_TE: Transfer error interrupt mask
AnnaBridge 189:f392fc9709a3 604 * @retval None
AnnaBridge 189:f392fc9709a3 605 */
AnnaBridge 189:f392fc9709a3 606 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
AnnaBridge 189:f392fc9709a3 607
AnnaBridge 189:f392fc9709a3 608 /**
AnnaBridge 189:f392fc9709a3 609 * @brief Disable the specified DMA Channel interrupts.
AnnaBridge 189:f392fc9709a3 610 * @param __HANDLE__: DMA handle
AnnaBridge 189:f392fc9709a3 611 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 189:f392fc9709a3 612 * This parameter can be any combination of the following values:
AnnaBridge 189:f392fc9709a3 613 * @arg DMA_IT_TC: Transfer complete interrupt mask
AnnaBridge 189:f392fc9709a3 614 * @arg DMA_IT_HT: Half transfer complete interrupt mask
AnnaBridge 189:f392fc9709a3 615 * @arg DMA_IT_TE: Transfer error interrupt mask
AnnaBridge 189:f392fc9709a3 616 * @retval None
AnnaBridge 189:f392fc9709a3 617 */
AnnaBridge 189:f392fc9709a3 618 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
AnnaBridge 189:f392fc9709a3 619
AnnaBridge 189:f392fc9709a3 620 /**
AnnaBridge 189:f392fc9709a3 621 * @brief Check whether the specified DMA Channel interrupt is enabled or not.
AnnaBridge 189:f392fc9709a3 622 * @param __HANDLE__: DMA handle
AnnaBridge 189:f392fc9709a3 623 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
AnnaBridge 189:f392fc9709a3 624 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 625 * @arg DMA_IT_TC: Transfer complete interrupt mask
AnnaBridge 189:f392fc9709a3 626 * @arg DMA_IT_HT: Half transfer complete interrupt mask
AnnaBridge 189:f392fc9709a3 627 * @arg DMA_IT_TE: Transfer error interrupt mask
AnnaBridge 189:f392fc9709a3 628 * @retval The state of DMA_IT (SET or RESET).
AnnaBridge 189:f392fc9709a3 629 */
AnnaBridge 189:f392fc9709a3 630 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
AnnaBridge 189:f392fc9709a3 631
AnnaBridge 189:f392fc9709a3 632 /**
AnnaBridge 189:f392fc9709a3 633 * @brief Return the number of remaining data units in the current DMA Channel transfer.
AnnaBridge 189:f392fc9709a3 634 * @param __HANDLE__: DMA handle
AnnaBridge 189:f392fc9709a3 635 * @retval The number of remaining data units in the current DMA Channel transfer.
AnnaBridge 189:f392fc9709a3 636 */
AnnaBridge 189:f392fc9709a3 637 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
AnnaBridge 189:f392fc9709a3 638
AnnaBridge 189:f392fc9709a3 639 /**
AnnaBridge 189:f392fc9709a3 640 * @}
AnnaBridge 189:f392fc9709a3 641 */
AnnaBridge 189:f392fc9709a3 642
AnnaBridge 189:f392fc9709a3 643 #if defined(DMAMUX1)
AnnaBridge 189:f392fc9709a3 644 /* Include DMA HAL Extension module */
AnnaBridge 189:f392fc9709a3 645 #include "stm32l4xx_hal_dma_ex.h"
AnnaBridge 189:f392fc9709a3 646 #endif /* DMAMUX1 */
AnnaBridge 189:f392fc9709a3 647
AnnaBridge 189:f392fc9709a3 648 /* Exported functions --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 649
AnnaBridge 189:f392fc9709a3 650 /** @addtogroup DMA_Exported_Functions
AnnaBridge 189:f392fc9709a3 651 * @{
AnnaBridge 189:f392fc9709a3 652 */
AnnaBridge 189:f392fc9709a3 653
AnnaBridge 189:f392fc9709a3 654 /** @addtogroup DMA_Exported_Functions_Group1
AnnaBridge 189:f392fc9709a3 655 * @{
AnnaBridge 189:f392fc9709a3 656 */
AnnaBridge 189:f392fc9709a3 657 /* Initialization and de-initialization functions *****************************/
AnnaBridge 189:f392fc9709a3 658 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
AnnaBridge 189:f392fc9709a3 659 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
AnnaBridge 189:f392fc9709a3 660 /**
AnnaBridge 189:f392fc9709a3 661 * @}
AnnaBridge 189:f392fc9709a3 662 */
AnnaBridge 189:f392fc9709a3 663
AnnaBridge 189:f392fc9709a3 664 /** @addtogroup DMA_Exported_Functions_Group2
AnnaBridge 189:f392fc9709a3 665 * @{
AnnaBridge 189:f392fc9709a3 666 */
AnnaBridge 189:f392fc9709a3 667 /* IO operation functions *****************************************************/
AnnaBridge 189:f392fc9709a3 668 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 189:f392fc9709a3 669 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 189:f392fc9709a3 670 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
AnnaBridge 189:f392fc9709a3 671 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
AnnaBridge 189:f392fc9709a3 672 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
AnnaBridge 189:f392fc9709a3 673 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
AnnaBridge 189:f392fc9709a3 674 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
AnnaBridge 189:f392fc9709a3 675 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
AnnaBridge 189:f392fc9709a3 676
AnnaBridge 189:f392fc9709a3 677 /**
AnnaBridge 189:f392fc9709a3 678 * @}
AnnaBridge 189:f392fc9709a3 679 */
AnnaBridge 189:f392fc9709a3 680
AnnaBridge 189:f392fc9709a3 681 /** @addtogroup DMA_Exported_Functions_Group3
AnnaBridge 189:f392fc9709a3 682 * @{
AnnaBridge 189:f392fc9709a3 683 */
AnnaBridge 189:f392fc9709a3 684 /* Peripheral State and Error functions ***************************************/
AnnaBridge 189:f392fc9709a3 685 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
AnnaBridge 189:f392fc9709a3 686 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
AnnaBridge 189:f392fc9709a3 687 /**
AnnaBridge 189:f392fc9709a3 688 * @}
AnnaBridge 189:f392fc9709a3 689 */
AnnaBridge 189:f392fc9709a3 690
AnnaBridge 189:f392fc9709a3 691 /**
AnnaBridge 189:f392fc9709a3 692 * @}
AnnaBridge 189:f392fc9709a3 693 */
AnnaBridge 189:f392fc9709a3 694
AnnaBridge 189:f392fc9709a3 695 /* Private macros ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 696 /** @defgroup DMA_Private_Macros DMA Private Macros
AnnaBridge 189:f392fc9709a3 697 * @{
AnnaBridge 189:f392fc9709a3 698 */
AnnaBridge 189:f392fc9709a3 699
AnnaBridge 189:f392fc9709a3 700 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
AnnaBridge 189:f392fc9709a3 701 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
AnnaBridge 189:f392fc9709a3 702 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
AnnaBridge 189:f392fc9709a3 703
AnnaBridge 189:f392fc9709a3 704 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
AnnaBridge 189:f392fc9709a3 705
AnnaBridge 189:f392fc9709a3 706 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
AnnaBridge 189:f392fc9709a3 707 ((STATE) == DMA_PINC_DISABLE))
AnnaBridge 189:f392fc9709a3 708
AnnaBridge 189:f392fc9709a3 709 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
AnnaBridge 189:f392fc9709a3 710 ((STATE) == DMA_MINC_DISABLE))
AnnaBridge 189:f392fc9709a3 711
AnnaBridge 189:f392fc9709a3 712 #if !defined (DMAMUX1)
AnnaBridge 189:f392fc9709a3 713
AnnaBridge 189:f392fc9709a3 714 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
AnnaBridge 189:f392fc9709a3 715 ((REQUEST) == DMA_REQUEST_1) || \
AnnaBridge 189:f392fc9709a3 716 ((REQUEST) == DMA_REQUEST_2) || \
AnnaBridge 189:f392fc9709a3 717 ((REQUEST) == DMA_REQUEST_3) || \
AnnaBridge 189:f392fc9709a3 718 ((REQUEST) == DMA_REQUEST_4) || \
AnnaBridge 189:f392fc9709a3 719 ((REQUEST) == DMA_REQUEST_5) || \
AnnaBridge 189:f392fc9709a3 720 ((REQUEST) == DMA_REQUEST_6) || \
AnnaBridge 189:f392fc9709a3 721 ((REQUEST) == DMA_REQUEST_7))
AnnaBridge 189:f392fc9709a3 722 #endif
AnnaBridge 189:f392fc9709a3 723
AnnaBridge 189:f392fc9709a3 724 #if defined(DMAMUX1)
AnnaBridge 189:f392fc9709a3 725
AnnaBridge 189:f392fc9709a3 726 #define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN)
AnnaBridge 189:f392fc9709a3 727
AnnaBridge 189:f392fc9709a3 728 #endif /* DMAMUX1 */
AnnaBridge 189:f392fc9709a3 729
AnnaBridge 189:f392fc9709a3 730 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
AnnaBridge 189:f392fc9709a3 731 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
AnnaBridge 189:f392fc9709a3 732 ((SIZE) == DMA_PDATAALIGN_WORD))
AnnaBridge 189:f392fc9709a3 733
AnnaBridge 189:f392fc9709a3 734 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
AnnaBridge 189:f392fc9709a3 735 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
AnnaBridge 189:f392fc9709a3 736 ((SIZE) == DMA_MDATAALIGN_WORD ))
AnnaBridge 189:f392fc9709a3 737
AnnaBridge 189:f392fc9709a3 738 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
AnnaBridge 189:f392fc9709a3 739 ((MODE) == DMA_CIRCULAR))
AnnaBridge 189:f392fc9709a3 740
AnnaBridge 189:f392fc9709a3 741 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
AnnaBridge 189:f392fc9709a3 742 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
AnnaBridge 189:f392fc9709a3 743 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
AnnaBridge 189:f392fc9709a3 744 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
AnnaBridge 189:f392fc9709a3 745
AnnaBridge 189:f392fc9709a3 746 /**
AnnaBridge 189:f392fc9709a3 747 * @}
AnnaBridge 189:f392fc9709a3 748 */
AnnaBridge 189:f392fc9709a3 749
AnnaBridge 189:f392fc9709a3 750 /* Private functions ---------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 751
AnnaBridge 189:f392fc9709a3 752 /**
AnnaBridge 189:f392fc9709a3 753 * @}
AnnaBridge 189:f392fc9709a3 754 */
AnnaBridge 189:f392fc9709a3 755
AnnaBridge 189:f392fc9709a3 756 /**
AnnaBridge 189:f392fc9709a3 757 * @}
AnnaBridge 189:f392fc9709a3 758 */
AnnaBridge 189:f392fc9709a3 759
AnnaBridge 189:f392fc9709a3 760 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 761 }
AnnaBridge 189:f392fc9709a3 762 #endif
AnnaBridge 189:f392fc9709a3 763
AnnaBridge 189:f392fc9709a3 764 #endif /* __STM32L4xx_HAL_DMA_H */
AnnaBridge 189:f392fc9709a3 765
AnnaBridge 189:f392fc9709a3 766 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/