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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_hal_dac.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_hal_dac.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of DAC HAL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_HAL_DAC_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_HAL_DAC_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | |
| AnnaBridge | 189:f392fc9709a3 | 45 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 46 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 47 | |
| AnnaBridge | 189:f392fc9709a3 | 48 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 49 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 50 | */ |
| AnnaBridge | 189:f392fc9709a3 | 51 | |
| AnnaBridge | 189:f392fc9709a3 | 52 | /** @addtogroup DAC |
| AnnaBridge | 189:f392fc9709a3 | 53 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 54 | */ |
| AnnaBridge | 189:f392fc9709a3 | 55 | |
| AnnaBridge | 189:f392fc9709a3 | 56 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 57 | |
| AnnaBridge | 189:f392fc9709a3 | 58 | /** @defgroup DAC_Exported_Types DAC Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 59 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 60 | */ |
| AnnaBridge | 189:f392fc9709a3 | 61 | |
| AnnaBridge | 189:f392fc9709a3 | 62 | /** |
| AnnaBridge | 189:f392fc9709a3 | 63 | * @brief HAL State structures definition |
| AnnaBridge | 189:f392fc9709a3 | 64 | */ |
| AnnaBridge | 189:f392fc9709a3 | 65 | typedef enum |
| AnnaBridge | 189:f392fc9709a3 | 66 | { |
| AnnaBridge | 189:f392fc9709a3 | 67 | HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 68 | HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */ |
| AnnaBridge | 189:f392fc9709a3 | 69 | HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 70 | HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ |
| AnnaBridge | 189:f392fc9709a3 | 71 | HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ |
| AnnaBridge | 189:f392fc9709a3 | 72 | |
| AnnaBridge | 189:f392fc9709a3 | 73 | }HAL_DAC_StateTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 74 | |
| AnnaBridge | 189:f392fc9709a3 | 75 | /** |
| AnnaBridge | 189:f392fc9709a3 | 76 | * @brief DAC handle Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 77 | */ |
| AnnaBridge | 189:f392fc9709a3 | 78 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 79 | { |
| AnnaBridge | 189:f392fc9709a3 | 80 | DAC_TypeDef *Instance; /*!< Register base address */ |
| AnnaBridge | 189:f392fc9709a3 | 81 | |
| AnnaBridge | 189:f392fc9709a3 | 82 | __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ |
| AnnaBridge | 189:f392fc9709a3 | 83 | |
| AnnaBridge | 189:f392fc9709a3 | 84 | HAL_LockTypeDef Lock; /*!< DAC locking object */ |
| AnnaBridge | 189:f392fc9709a3 | 85 | |
| AnnaBridge | 189:f392fc9709a3 | 86 | DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 87 | |
| AnnaBridge | 189:f392fc9709a3 | 88 | DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 89 | |
| AnnaBridge | 189:f392fc9709a3 | 90 | __IO uint32_t ErrorCode; /*!< DAC Error code */ |
| AnnaBridge | 189:f392fc9709a3 | 91 | |
| AnnaBridge | 189:f392fc9709a3 | 92 | }DAC_HandleTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 93 | |
| AnnaBridge | 189:f392fc9709a3 | 94 | /** |
| AnnaBridge | 189:f392fc9709a3 | 95 | * @brief DAC Configuration sample and hold Channel structure definition |
| AnnaBridge | 189:f392fc9709a3 | 96 | */ |
| AnnaBridge | 189:f392fc9709a3 | 97 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 98 | { |
| AnnaBridge | 189:f392fc9709a3 | 99 | uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. |
| AnnaBridge | 189:f392fc9709a3 | 100 | This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. |
| AnnaBridge | 189:f392fc9709a3 | 101 | This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ |
| AnnaBridge | 189:f392fc9709a3 | 102 | |
| AnnaBridge | 189:f392fc9709a3 | 103 | uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel |
| AnnaBridge | 189:f392fc9709a3 | 104 | This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. |
| AnnaBridge | 189:f392fc9709a3 | 105 | This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ |
| AnnaBridge | 189:f392fc9709a3 | 106 | |
| AnnaBridge | 189:f392fc9709a3 | 107 | uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel |
| AnnaBridge | 189:f392fc9709a3 | 108 | This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. |
| AnnaBridge | 189:f392fc9709a3 | 109 | This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | } |
| AnnaBridge | 189:f392fc9709a3 | 111 | DAC_SampleAndHoldConfTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 112 | |
| AnnaBridge | 189:f392fc9709a3 | 113 | /** |
| AnnaBridge | 189:f392fc9709a3 | 114 | * @brief DAC Configuration regular Channel structure definition |
| AnnaBridge | 189:f392fc9709a3 | 115 | */ |
| AnnaBridge | 189:f392fc9709a3 | 116 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 117 | { |
| AnnaBridge | 189:f392fc9709a3 | 118 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 119 | uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode |
| AnnaBridge | 189:f392fc9709a3 | 120 | This parameter can be a value of @ref DAC_HighFrequency */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | |
| AnnaBridge | 189:f392fc9709a3 | 123 | uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. |
| AnnaBridge | 189:f392fc9709a3 | 124 | This parameter can be a value of @ref DAC_SampleAndHold */ |
| AnnaBridge | 189:f392fc9709a3 | 125 | |
| AnnaBridge | 189:f392fc9709a3 | 126 | uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. |
| AnnaBridge | 189:f392fc9709a3 | 127 | This parameter can be a value of @ref DAC_trigger_selection */ |
| AnnaBridge | 189:f392fc9709a3 | 128 | |
| AnnaBridge | 189:f392fc9709a3 | 129 | uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. |
| AnnaBridge | 189:f392fc9709a3 | 130 | This parameter can be a value of @ref DAC_output_buffer */ |
| AnnaBridge | 189:f392fc9709a3 | 131 | |
| AnnaBridge | 189:f392fc9709a3 | 132 | uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . |
| AnnaBridge | 189:f392fc9709a3 | 133 | This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ |
| AnnaBridge | 189:f392fc9709a3 | 134 | |
| AnnaBridge | 189:f392fc9709a3 | 135 | uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode |
| AnnaBridge | 189:f392fc9709a3 | 136 | This parameter must be a value of @ref DAC_UserTrimming |
| AnnaBridge | 189:f392fc9709a3 | 137 | DAC_UserTrimming is either factory or user trimming */ |
| AnnaBridge | 189:f392fc9709a3 | 138 | |
| AnnaBridge | 189:f392fc9709a3 | 139 | uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value |
| AnnaBridge | 189:f392fc9709a3 | 140 | i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. |
| AnnaBridge | 189:f392fc9709a3 | 141 | This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ |
| AnnaBridge | 189:f392fc9709a3 | 142 | |
| AnnaBridge | 189:f392fc9709a3 | 143 | DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ |
| AnnaBridge | 189:f392fc9709a3 | 144 | |
| AnnaBridge | 189:f392fc9709a3 | 145 | }DAC_ChannelConfTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 146 | |
| AnnaBridge | 189:f392fc9709a3 | 147 | /** |
| AnnaBridge | 189:f392fc9709a3 | 148 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 149 | */ |
| AnnaBridge | 189:f392fc9709a3 | 150 | |
| AnnaBridge | 189:f392fc9709a3 | 151 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 152 | |
| AnnaBridge | 189:f392fc9709a3 | 153 | /** @defgroup DAC_Exported_Constants DAC Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 154 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 155 | */ |
| AnnaBridge | 189:f392fc9709a3 | 156 | |
| AnnaBridge | 189:f392fc9709a3 | 157 | /** @defgroup DAC_Error_Code DAC Error Code |
| AnnaBridge | 189:f392fc9709a3 | 158 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 159 | */ |
| AnnaBridge | 189:f392fc9709a3 | 160 | #define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ |
| AnnaBridge | 189:f392fc9709a3 | 161 | #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */ |
| AnnaBridge | 189:f392fc9709a3 | 162 | #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */ |
| AnnaBridge | 189:f392fc9709a3 | 163 | #define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ |
| AnnaBridge | 189:f392fc9709a3 | 164 | #define HAL_DAC_ERROR_TIMEOUT 0x08 /*!< Timeout error */ |
| AnnaBridge | 189:f392fc9709a3 | 165 | /** |
| AnnaBridge | 189:f392fc9709a3 | 166 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 167 | */ |
| AnnaBridge | 189:f392fc9709a3 | 168 | |
| AnnaBridge | 189:f392fc9709a3 | 169 | /** @defgroup DAC_trigger_selection DAC trigger selection |
| AnnaBridge | 189:f392fc9709a3 | 170 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 171 | */ |
| AnnaBridge | 189:f392fc9709a3 | 172 | |
| AnnaBridge | 189:f392fc9709a3 | 173 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) |
| AnnaBridge | 189:f392fc9709a3 | 174 | #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register |
| AnnaBridge | 189:f392fc9709a3 | 175 | has been loaded, and not by external trigger */ |
| AnnaBridge | 189:f392fc9709a3 | 176 | #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 177 | #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 178 | #define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 179 | #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 180 | #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 181 | #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | |
| AnnaBridge | 189:f392fc9709a3 | 183 | #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) |
| AnnaBridge | 189:f392fc9709a3 | 184 | #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register |
| AnnaBridge | 189:f392fc9709a3 | 185 | has been loaded, and not by external trigger */ |
| AnnaBridge | 189:f392fc9709a3 | 186 | #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 187 | #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 188 | #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 189 | #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 190 | #endif /* STM32L451xx STM32L452xx STM32L462xx */ |
| AnnaBridge | 189:f392fc9709a3 | 191 | |
| AnnaBridge | 189:f392fc9709a3 | 192 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) |
| AnnaBridge | 189:f392fc9709a3 | 193 | #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register |
| AnnaBridge | 189:f392fc9709a3 | 194 | has been loaded, and not by external trigger */ |
| AnnaBridge | 189:f392fc9709a3 | 195 | #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 196 | #define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 197 | #define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 198 | #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 199 | #define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 200 | #define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 201 | #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 202 | #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 203 | #endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx*/ |
| AnnaBridge | 189:f392fc9709a3 | 204 | |
| AnnaBridge | 189:f392fc9709a3 | 205 | |
| AnnaBridge | 189:f392fc9709a3 | 206 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 207 | #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register |
| AnnaBridge | 189:f392fc9709a3 | 208 | has been loaded, and not by external trigger */ |
| AnnaBridge | 189:f392fc9709a3 | 209 | #define DAC_TRIGGER_T1_TRGO ((uint32_t) (DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 210 | #define DAC_TRIGGER_T2_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 211 | #define DAC_TRIGGER_T4_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 212 | #define DAC_TRIGGER_T5_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 213 | #define DAC_TRIGGER_T6_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 214 | #define DAC_TRIGGER_T7_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 215 | #define DAC_TRIGGER_T8_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 216 | #define DAC_TRIGGER_T15_TRGO ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 217 | #define DAC_TRIGGER_LPTIM1_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 218 | #define DAC_TRIGGER_LPTIM2_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 219 | #define DAC_TRIGGER_EXT_IT9 ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 220 | #define DAC_TRIGGER_SOFTWARE ((uint32_t) (DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ |
| AnnaBridge | 189:f392fc9709a3 | 221 | |
| AnnaBridge | 189:f392fc9709a3 | 222 | #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 223 | |
| AnnaBridge | 189:f392fc9709a3 | 224 | |
| AnnaBridge | 189:f392fc9709a3 | 225 | /** |
| AnnaBridge | 189:f392fc9709a3 | 226 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 227 | */ |
| AnnaBridge | 189:f392fc9709a3 | 228 | |
| AnnaBridge | 189:f392fc9709a3 | 229 | /** @defgroup DAC_output_buffer DAC output buffer |
| AnnaBridge | 189:f392fc9709a3 | 230 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 231 | */ |
| AnnaBridge | 189:f392fc9709a3 | 232 | #define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 233 | #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_MCR_MODE1_1) |
| AnnaBridge | 189:f392fc9709a3 | 234 | |
| AnnaBridge | 189:f392fc9709a3 | 235 | /** |
| AnnaBridge | 189:f392fc9709a3 | 236 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 237 | */ |
| AnnaBridge | 189:f392fc9709a3 | 238 | |
| AnnaBridge | 189:f392fc9709a3 | 239 | /** @defgroup DAC_Channel_selection DAC Channel selection |
| AnnaBridge | 189:f392fc9709a3 | 240 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 241 | */ |
| AnnaBridge | 189:f392fc9709a3 | 242 | #define DAC_CHANNEL_1 ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 243 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 244 | defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 245 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 246 | #define DAC_CHANNEL_2 ((uint32_t)0x00000010) |
| AnnaBridge | 189:f392fc9709a3 | 247 | #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ |
| AnnaBridge | 189:f392fc9709a3 | 248 | /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ |
| AnnaBridge | 189:f392fc9709a3 | 249 | /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 250 | |
| AnnaBridge | 189:f392fc9709a3 | 251 | /** |
| AnnaBridge | 189:f392fc9709a3 | 252 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 253 | */ |
| AnnaBridge | 189:f392fc9709a3 | 254 | |
| AnnaBridge | 189:f392fc9709a3 | 255 | /** @defgroup DAC_data_alignment DAC data alignment |
| AnnaBridge | 189:f392fc9709a3 | 256 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 257 | */ |
| AnnaBridge | 189:f392fc9709a3 | 258 | #define DAC_ALIGN_12B_R ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 259 | #define DAC_ALIGN_12B_L ((uint32_t)0x00000004) |
| AnnaBridge | 189:f392fc9709a3 | 260 | #define DAC_ALIGN_8B_R ((uint32_t)0x00000008) |
| AnnaBridge | 189:f392fc9709a3 | 261 | |
| AnnaBridge | 189:f392fc9709a3 | 262 | /** |
| AnnaBridge | 189:f392fc9709a3 | 263 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 264 | */ |
| AnnaBridge | 189:f392fc9709a3 | 265 | |
| AnnaBridge | 189:f392fc9709a3 | 266 | /** @defgroup DAC_flags_definition DAC flags definition |
| AnnaBridge | 189:f392fc9709a3 | 267 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 268 | */ |
| AnnaBridge | 189:f392fc9709a3 | 269 | #define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) |
| AnnaBridge | 189:f392fc9709a3 | 270 | #define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) |
| AnnaBridge | 189:f392fc9709a3 | 271 | |
| AnnaBridge | 189:f392fc9709a3 | 272 | /** |
| AnnaBridge | 189:f392fc9709a3 | 273 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 274 | */ |
| AnnaBridge | 189:f392fc9709a3 | 275 | |
| AnnaBridge | 189:f392fc9709a3 | 276 | /** @defgroup DAC_IT_definition DAC IT definition |
| AnnaBridge | 189:f392fc9709a3 | 277 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 278 | */ |
| AnnaBridge | 189:f392fc9709a3 | 279 | #define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) |
| AnnaBridge | 189:f392fc9709a3 | 280 | #define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) |
| AnnaBridge | 189:f392fc9709a3 | 281 | |
| AnnaBridge | 189:f392fc9709a3 | 282 | /** |
| AnnaBridge | 189:f392fc9709a3 | 283 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 284 | */ |
| AnnaBridge | 189:f392fc9709a3 | 285 | |
| AnnaBridge | 189:f392fc9709a3 | 286 | /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral |
| AnnaBridge | 189:f392fc9709a3 | 287 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 288 | */ |
| AnnaBridge | 189:f392fc9709a3 | 289 | #define DAC_CHIPCONNECT_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 290 | #define DAC_CHIPCONNECT_ENABLE ((uint32_t)DAC_MCR_MODE1_0) |
| AnnaBridge | 189:f392fc9709a3 | 291 | |
| AnnaBridge | 189:f392fc9709a3 | 292 | /** |
| AnnaBridge | 189:f392fc9709a3 | 293 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 294 | */ |
| AnnaBridge | 189:f392fc9709a3 | 295 | |
| AnnaBridge | 189:f392fc9709a3 | 296 | /** @defgroup DAC_UserTrimming DAC User Trimming |
| AnnaBridge | 189:f392fc9709a3 | 297 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 298 | */ |
| AnnaBridge | 189:f392fc9709a3 | 299 | |
| AnnaBridge | 189:f392fc9709a3 | 300 | #define DAC_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */ |
| AnnaBridge | 189:f392fc9709a3 | 301 | #define DAC_TRIMMING_USER ((uint32_t)0x00000001) /*!< User trimming */ |
| AnnaBridge | 189:f392fc9709a3 | 302 | |
| AnnaBridge | 189:f392fc9709a3 | 303 | /** |
| AnnaBridge | 189:f392fc9709a3 | 304 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 305 | */ |
| AnnaBridge | 189:f392fc9709a3 | 306 | |
| AnnaBridge | 189:f392fc9709a3 | 307 | /** @defgroup DAC_SampleAndHold DAC power mode |
| AnnaBridge | 189:f392fc9709a3 | 308 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 309 | */ |
| AnnaBridge | 189:f392fc9709a3 | 310 | #define DAC_SAMPLEANDHOLD_DISABLE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 311 | #define DAC_SAMPLEANDHOLD_ENABLE ((uint32_t)DAC_MCR_MODE1_2) |
| AnnaBridge | 189:f392fc9709a3 | 312 | |
| AnnaBridge | 189:f392fc9709a3 | 313 | /** |
| AnnaBridge | 189:f392fc9709a3 | 314 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 315 | */ |
| AnnaBridge | 189:f392fc9709a3 | 316 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 317 | /** @defgroup DAC_HighFrequency DAC high frequency interface mode |
| AnnaBridge | 189:f392fc9709a3 | 318 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 319 | */ |
| AnnaBridge | 189:f392fc9709a3 | 320 | #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE ((uint32_t)0x00000000) /*!< High frequency interface mode disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 321 | #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ ((uint32_t)DAC_CR_HFSEL) /*!< High frequency interface mode enabled */ |
| AnnaBridge | 189:f392fc9709a3 | 322 | #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC ((uint32_t)0x00000002) /*!< High frequency interface mode automatic */ |
| AnnaBridge | 189:f392fc9709a3 | 323 | |
| AnnaBridge | 189:f392fc9709a3 | 324 | /** |
| AnnaBridge | 189:f392fc9709a3 | 325 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 326 | */ |
| AnnaBridge | 189:f392fc9709a3 | 327 | #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 328 | |
| AnnaBridge | 189:f392fc9709a3 | 329 | /** |
| AnnaBridge | 189:f392fc9709a3 | 330 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 331 | */ |
| AnnaBridge | 189:f392fc9709a3 | 332 | |
| AnnaBridge | 189:f392fc9709a3 | 333 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 334 | |
| AnnaBridge | 189:f392fc9709a3 | 335 | /** @defgroup DAC_Exported_Macros DAC Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 336 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 337 | */ |
| AnnaBridge | 189:f392fc9709a3 | 338 | |
| AnnaBridge | 189:f392fc9709a3 | 339 | /** @brief Reset DAC handle state. |
| AnnaBridge | 189:f392fc9709a3 | 340 | * @param __HANDLE__: specifies the DAC handle. |
| AnnaBridge | 189:f392fc9709a3 | 341 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 342 | */ |
| AnnaBridge | 189:f392fc9709a3 | 343 | #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) |
| AnnaBridge | 189:f392fc9709a3 | 344 | |
| AnnaBridge | 189:f392fc9709a3 | 345 | /** @brief Enable the DAC channel. |
| AnnaBridge | 189:f392fc9709a3 | 346 | * @param __HANDLE__: specifies the DAC handle. |
| AnnaBridge | 189:f392fc9709a3 | 347 | * @param __DAC_Channel__: specifies the DAC channel |
| AnnaBridge | 189:f392fc9709a3 | 348 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 349 | */ |
| AnnaBridge | 189:f392fc9709a3 | 350 | #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ |
| AnnaBridge | 189:f392fc9709a3 | 351 | ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__))) |
| AnnaBridge | 189:f392fc9709a3 | 352 | |
| AnnaBridge | 189:f392fc9709a3 | 353 | /** @brief Disable the DAC channel. |
| AnnaBridge | 189:f392fc9709a3 | 354 | * @param __HANDLE__: specifies the DAC handle |
| AnnaBridge | 189:f392fc9709a3 | 355 | * @param __DAC_Channel__: specifies the DAC channel. |
| AnnaBridge | 189:f392fc9709a3 | 356 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 357 | */ |
| AnnaBridge | 189:f392fc9709a3 | 358 | #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ |
| AnnaBridge | 189:f392fc9709a3 | 359 | ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) |
| AnnaBridge | 189:f392fc9709a3 | 360 | |
| AnnaBridge | 189:f392fc9709a3 | 361 | /** @brief Set DHR12R1 alignment. |
| AnnaBridge | 189:f392fc9709a3 | 362 | * @param __ALIGNMENT__: specifies the DAC alignment |
| AnnaBridge | 189:f392fc9709a3 | 363 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 364 | */ |
| AnnaBridge | 189:f392fc9709a3 | 365 | #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__)) |
| AnnaBridge | 189:f392fc9709a3 | 366 | |
| AnnaBridge | 189:f392fc9709a3 | 367 | /** @brief Set DHR12R2 alignment. |
| AnnaBridge | 189:f392fc9709a3 | 368 | * @param __ALIGNMENT__: specifies the DAC alignment |
| AnnaBridge | 189:f392fc9709a3 | 369 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 370 | */ |
| AnnaBridge | 189:f392fc9709a3 | 371 | #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__)) |
| AnnaBridge | 189:f392fc9709a3 | 372 | |
| AnnaBridge | 189:f392fc9709a3 | 373 | /** @brief Set DHR12RD alignment. |
| AnnaBridge | 189:f392fc9709a3 | 374 | * @param __ALIGNMENT__: specifies the DAC alignment |
| AnnaBridge | 189:f392fc9709a3 | 375 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 376 | */ |
| AnnaBridge | 189:f392fc9709a3 | 377 | #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__)) |
| AnnaBridge | 189:f392fc9709a3 | 378 | |
| AnnaBridge | 189:f392fc9709a3 | 379 | /** @brief Enable the DAC interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 380 | * @param __HANDLE__: specifies the DAC handle |
| AnnaBridge | 189:f392fc9709a3 | 381 | * @param __INTERRUPT__: specifies the DAC interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 382 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 383 | * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt |
| AnnaBridge | 189:f392fc9709a3 | 384 | * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt |
| AnnaBridge | 189:f392fc9709a3 | 385 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 386 | */ |
| AnnaBridge | 189:f392fc9709a3 | 387 | #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 388 | |
| AnnaBridge | 189:f392fc9709a3 | 389 | /** @brief Disable the DAC interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 390 | * @param __HANDLE__: specifies the DAC handle |
| AnnaBridge | 189:f392fc9709a3 | 391 | * @param __INTERRUPT__: specifies the DAC interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 392 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 393 | * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt |
| AnnaBridge | 189:f392fc9709a3 | 394 | * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt |
| AnnaBridge | 189:f392fc9709a3 | 395 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 396 | */ |
| AnnaBridge | 189:f392fc9709a3 | 397 | #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 398 | |
| AnnaBridge | 189:f392fc9709a3 | 399 | /** @brief Check whether the specified DAC interrupt source is enabled or not. |
| AnnaBridge | 189:f392fc9709a3 | 400 | * @param __HANDLE__: DAC handle |
| AnnaBridge | 189:f392fc9709a3 | 401 | * @param __INTERRUPT__: DAC interrupt source to check |
| AnnaBridge | 189:f392fc9709a3 | 402 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 403 | * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt |
| AnnaBridge | 189:f392fc9709a3 | 404 | * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt |
| AnnaBridge | 189:f392fc9709a3 | 405 | * @retval State of interruption (SET or RESET) |
| AnnaBridge | 189:f392fc9709a3 | 406 | */ |
| AnnaBridge | 189:f392fc9709a3 | 407 | #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 408 | |
| AnnaBridge | 189:f392fc9709a3 | 409 | /** @brief Get the selected DAC's flag status. |
| AnnaBridge | 189:f392fc9709a3 | 410 | * @param __HANDLE__: specifies the DAC handle. |
| AnnaBridge | 189:f392fc9709a3 | 411 | * @param __FLAG__: specifies the DAC flag to get. |
| AnnaBridge | 189:f392fc9709a3 | 412 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 413 | * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag |
| AnnaBridge | 189:f392fc9709a3 | 414 | * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag |
| AnnaBridge | 189:f392fc9709a3 | 415 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 416 | */ |
| AnnaBridge | 189:f392fc9709a3 | 417 | #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 189:f392fc9709a3 | 418 | |
| AnnaBridge | 189:f392fc9709a3 | 419 | /** @brief Clear the DAC's flag. |
| AnnaBridge | 189:f392fc9709a3 | 420 | * @param __HANDLE__: specifies the DAC handle. |
| AnnaBridge | 189:f392fc9709a3 | 421 | * @param __FLAG__: specifies the DAC flag to clear. |
| AnnaBridge | 189:f392fc9709a3 | 422 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 423 | * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag |
| AnnaBridge | 189:f392fc9709a3 | 424 | * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag |
| AnnaBridge | 189:f392fc9709a3 | 425 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 426 | */ |
| AnnaBridge | 189:f392fc9709a3 | 427 | #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) |
| AnnaBridge | 189:f392fc9709a3 | 428 | |
| AnnaBridge | 189:f392fc9709a3 | 429 | /** |
| AnnaBridge | 189:f392fc9709a3 | 430 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 431 | */ |
| AnnaBridge | 189:f392fc9709a3 | 432 | |
| AnnaBridge | 189:f392fc9709a3 | 433 | /* Private macro -------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 434 | |
| AnnaBridge | 189:f392fc9709a3 | 435 | /** @defgroup DAC_Private_Macros DAC Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 436 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 437 | */ |
| AnnaBridge | 189:f392fc9709a3 | 438 | #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 439 | ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 440 | |
| AnnaBridge | 189:f392fc9709a3 | 441 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 442 | defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 443 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 444 | #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 445 | ((CHANNEL) == DAC_CHANNEL_2)) |
| AnnaBridge | 189:f392fc9709a3 | 446 | #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ |
| AnnaBridge | 189:f392fc9709a3 | 447 | /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ |
| AnnaBridge | 189:f392fc9709a3 | 448 | /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 449 | |
| AnnaBridge | 189:f392fc9709a3 | 450 | #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) |
| AnnaBridge | 189:f392fc9709a3 | 451 | #define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1) |
| AnnaBridge | 189:f392fc9709a3 | 452 | #endif /* STM32L451xx STM32L452xx STM32L462xx */ |
| AnnaBridge | 189:f392fc9709a3 | 453 | |
| AnnaBridge | 189:f392fc9709a3 | 454 | #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ |
| AnnaBridge | 189:f392fc9709a3 | 455 | ((ALIGN) == DAC_ALIGN_12B_L) || \ |
| AnnaBridge | 189:f392fc9709a3 | 456 | ((ALIGN) == DAC_ALIGN_8B_R)) |
| AnnaBridge | 189:f392fc9709a3 | 457 | |
| AnnaBridge | 189:f392fc9709a3 | 458 | #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) |
| AnnaBridge | 189:f392fc9709a3 | 459 | |
| AnnaBridge | 189:f392fc9709a3 | 460 | #define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FF) |
| AnnaBridge | 189:f392fc9709a3 | 461 | |
| AnnaBridge | 189:f392fc9709a3 | 462 | /** |
| AnnaBridge | 189:f392fc9709a3 | 463 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 464 | */ |
| AnnaBridge | 189:f392fc9709a3 | 465 | |
| AnnaBridge | 189:f392fc9709a3 | 466 | /* Include DAC HAL Extended module */ |
| AnnaBridge | 189:f392fc9709a3 | 467 | #include "stm32l4xx_hal_dac_ex.h" |
| AnnaBridge | 189:f392fc9709a3 | 468 | |
| AnnaBridge | 189:f392fc9709a3 | 469 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 470 | |
| AnnaBridge | 189:f392fc9709a3 | 471 | /** @addtogroup DAC_Exported_Functions |
| AnnaBridge | 189:f392fc9709a3 | 472 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 473 | */ |
| AnnaBridge | 189:f392fc9709a3 | 474 | |
| AnnaBridge | 189:f392fc9709a3 | 475 | /** @addtogroup DAC_Exported_Functions_Group1 |
| AnnaBridge | 189:f392fc9709a3 | 476 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 477 | */ |
| AnnaBridge | 189:f392fc9709a3 | 478 | /* Initialization and de-initialization functions *****************************/ |
| AnnaBridge | 189:f392fc9709a3 | 479 | HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 189:f392fc9709a3 | 480 | HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 189:f392fc9709a3 | 481 | void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 189:f392fc9709a3 | 482 | void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 189:f392fc9709a3 | 483 | |
| AnnaBridge | 189:f392fc9709a3 | 484 | /** |
| AnnaBridge | 189:f392fc9709a3 | 485 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 486 | */ |
| AnnaBridge | 189:f392fc9709a3 | 487 | |
| AnnaBridge | 189:f392fc9709a3 | 488 | /** @addtogroup DAC_Exported_Functions_Group2 |
| AnnaBridge | 189:f392fc9709a3 | 489 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 490 | */ |
| AnnaBridge | 189:f392fc9709a3 | 491 | /* IO operation functions *****************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 492 | HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 493 | HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 494 | HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment); |
| AnnaBridge | 189:f392fc9709a3 | 495 | HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 496 | |
| AnnaBridge | 189:f392fc9709a3 | 497 | void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 189:f392fc9709a3 | 498 | |
| AnnaBridge | 189:f392fc9709a3 | 499 | HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); |
| AnnaBridge | 189:f392fc9709a3 | 500 | |
| AnnaBridge | 189:f392fc9709a3 | 501 | void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 189:f392fc9709a3 | 502 | void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 189:f392fc9709a3 | 503 | void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); |
| AnnaBridge | 189:f392fc9709a3 | 504 | void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); |
| AnnaBridge | 189:f392fc9709a3 | 505 | /** |
| AnnaBridge | 189:f392fc9709a3 | 506 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 507 | */ |
| AnnaBridge | 189:f392fc9709a3 | 508 | |
| AnnaBridge | 189:f392fc9709a3 | 509 | /** @addtogroup DAC_Exported_Functions_Group3 |
| AnnaBridge | 189:f392fc9709a3 | 510 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 511 | */ |
| AnnaBridge | 189:f392fc9709a3 | 512 | /* Peripheral Control functions ***********************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 513 | uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 514 | |
| AnnaBridge | 189:f392fc9709a3 | 515 | HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 516 | /** |
| AnnaBridge | 189:f392fc9709a3 | 517 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 518 | */ |
| AnnaBridge | 189:f392fc9709a3 | 519 | |
| AnnaBridge | 189:f392fc9709a3 | 520 | /** @addtogroup DAC_Exported_Functions_Group4 |
| AnnaBridge | 189:f392fc9709a3 | 521 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 522 | */ |
| AnnaBridge | 189:f392fc9709a3 | 523 | /* Peripheral State and Error functions ***************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 524 | HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); |
| AnnaBridge | 189:f392fc9709a3 | 525 | uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); |
| AnnaBridge | 189:f392fc9709a3 | 526 | |
| AnnaBridge | 189:f392fc9709a3 | 527 | /** |
| AnnaBridge | 189:f392fc9709a3 | 528 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 529 | */ |
| AnnaBridge | 189:f392fc9709a3 | 530 | |
| AnnaBridge | 189:f392fc9709a3 | 531 | /** |
| AnnaBridge | 189:f392fc9709a3 | 532 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 533 | */ |
| AnnaBridge | 189:f392fc9709a3 | 534 | |
| AnnaBridge | 189:f392fc9709a3 | 535 | /** |
| AnnaBridge | 189:f392fc9709a3 | 536 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 537 | */ |
| AnnaBridge | 189:f392fc9709a3 | 538 | |
| AnnaBridge | 189:f392fc9709a3 | 539 | /** |
| AnnaBridge | 189:f392fc9709a3 | 540 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 541 | */ |
| AnnaBridge | 189:f392fc9709a3 | 542 | |
| AnnaBridge | 189:f392fc9709a3 | 543 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 544 | } |
| AnnaBridge | 189:f392fc9709a3 | 545 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 546 | |
| AnnaBridge | 189:f392fc9709a3 | 547 | |
| AnnaBridge | 189:f392fc9709a3 | 548 | #endif /*__STM32L4xx_HAL_DAC_H */ |
| AnnaBridge | 189:f392fc9709a3 | 549 | |
| AnnaBridge | 189:f392fc9709a3 | 550 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| AnnaBridge | 189:f392fc9709a3 | 551 |
