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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_ARM_STD/stm32l4xx_ll_tim.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_ll_tim.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of TIM LL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_LL_TIM_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_LL_TIM_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l4xx.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32L4xx_LL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7) |
| AnnaBridge | 189:f392fc9709a3 | 52 | |
| AnnaBridge | 189:f392fc9709a3 | 53 | /** @defgroup TIM_LL TIM |
| AnnaBridge | 189:f392fc9709a3 | 54 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 55 | */ |
| AnnaBridge | 189:f392fc9709a3 | 56 | |
| AnnaBridge | 189:f392fc9709a3 | 57 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 58 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 59 | /** @defgroup TIM_LL_Private_Variables TIM Private Variables |
| AnnaBridge | 189:f392fc9709a3 | 60 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 61 | */ |
| AnnaBridge | 189:f392fc9709a3 | 62 | static const uint8_t OFFSET_TAB_CCMRx[] = |
| AnnaBridge | 189:f392fc9709a3 | 63 | { |
| AnnaBridge | 189:f392fc9709a3 | 64 | 0x00U, /* 0: TIMx_CH1 */ |
| AnnaBridge | 189:f392fc9709a3 | 65 | 0x00U, /* 1: TIMx_CH1N */ |
| AnnaBridge | 189:f392fc9709a3 | 66 | 0x00U, /* 2: TIMx_CH2 */ |
| AnnaBridge | 189:f392fc9709a3 | 67 | 0x00U, /* 3: TIMx_CH2N */ |
| AnnaBridge | 189:f392fc9709a3 | 68 | 0x04U, /* 4: TIMx_CH3 */ |
| AnnaBridge | 189:f392fc9709a3 | 69 | 0x04U, /* 5: TIMx_CH3N */ |
| AnnaBridge | 189:f392fc9709a3 | 70 | 0x04U, /* 6: TIMx_CH4 */ |
| AnnaBridge | 189:f392fc9709a3 | 71 | 0x3CU, /* 7: TIMx_CH5 */ |
| AnnaBridge | 189:f392fc9709a3 | 72 | 0x3CU /* 8: TIMx_CH6 */ |
| AnnaBridge | 189:f392fc9709a3 | 73 | }; |
| AnnaBridge | 189:f392fc9709a3 | 74 | |
| AnnaBridge | 189:f392fc9709a3 | 75 | static const uint8_t SHIFT_TAB_OCxx[] = |
| AnnaBridge | 189:f392fc9709a3 | 76 | { |
| AnnaBridge | 189:f392fc9709a3 | 77 | 0U, /* 0: OC1M, OC1FE, OC1PE */ |
| AnnaBridge | 189:f392fc9709a3 | 78 | 0U, /* 1: - NA */ |
| AnnaBridge | 189:f392fc9709a3 | 79 | 8U, /* 2: OC2M, OC2FE, OC2PE */ |
| AnnaBridge | 189:f392fc9709a3 | 80 | 0U, /* 3: - NA */ |
| AnnaBridge | 189:f392fc9709a3 | 81 | 0U, /* 4: OC3M, OC3FE, OC3PE */ |
| AnnaBridge | 189:f392fc9709a3 | 82 | 0U, /* 5: - NA */ |
| AnnaBridge | 189:f392fc9709a3 | 83 | 8U, /* 6: OC4M, OC4FE, OC4PE */ |
| AnnaBridge | 189:f392fc9709a3 | 84 | 0U, /* 7: OC5M, OC5FE, OC5PE */ |
| AnnaBridge | 189:f392fc9709a3 | 85 | 8U /* 8: OC6M, OC6FE, OC6PE */ |
| AnnaBridge | 189:f392fc9709a3 | 86 | }; |
| AnnaBridge | 189:f392fc9709a3 | 87 | |
| AnnaBridge | 189:f392fc9709a3 | 88 | static const uint8_t SHIFT_TAB_ICxx[] = |
| AnnaBridge | 189:f392fc9709a3 | 89 | { |
| AnnaBridge | 189:f392fc9709a3 | 90 | 0U, /* 0: CC1S, IC1PSC, IC1F */ |
| AnnaBridge | 189:f392fc9709a3 | 91 | 0U, /* 1: - NA */ |
| AnnaBridge | 189:f392fc9709a3 | 92 | 8U, /* 2: CC2S, IC2PSC, IC2F */ |
| AnnaBridge | 189:f392fc9709a3 | 93 | 0U, /* 3: - NA */ |
| AnnaBridge | 189:f392fc9709a3 | 94 | 0U, /* 4: CC3S, IC3PSC, IC3F */ |
| AnnaBridge | 189:f392fc9709a3 | 95 | 0U, /* 5: - NA */ |
| AnnaBridge | 189:f392fc9709a3 | 96 | 8U, /* 6: CC4S, IC4PSC, IC4F */ |
| AnnaBridge | 189:f392fc9709a3 | 97 | 0U, /* 7: - NA */ |
| AnnaBridge | 189:f392fc9709a3 | 98 | 0U /* 8: - NA */ |
| AnnaBridge | 189:f392fc9709a3 | 99 | }; |
| AnnaBridge | 189:f392fc9709a3 | 100 | |
| AnnaBridge | 189:f392fc9709a3 | 101 | static const uint8_t SHIFT_TAB_CCxP[] = |
| AnnaBridge | 189:f392fc9709a3 | 102 | { |
| AnnaBridge | 189:f392fc9709a3 | 103 | 0U, /* 0: CC1P */ |
| AnnaBridge | 189:f392fc9709a3 | 104 | 2U, /* 1: CC1NP */ |
| AnnaBridge | 189:f392fc9709a3 | 105 | 4U, /* 2: CC2P */ |
| AnnaBridge | 189:f392fc9709a3 | 106 | 6U, /* 3: CC2NP */ |
| AnnaBridge | 189:f392fc9709a3 | 107 | 8U, /* 4: CC3P */ |
| AnnaBridge | 189:f392fc9709a3 | 108 | 10U, /* 5: CC3NP */ |
| AnnaBridge | 189:f392fc9709a3 | 109 | 12U, /* 6: CC4P */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | 16U, /* 7: CC5P */ |
| AnnaBridge | 189:f392fc9709a3 | 111 | 20U /* 8: CC6P */ |
| AnnaBridge | 189:f392fc9709a3 | 112 | }; |
| AnnaBridge | 189:f392fc9709a3 | 113 | |
| AnnaBridge | 189:f392fc9709a3 | 114 | static const uint8_t SHIFT_TAB_OISx[] = |
| AnnaBridge | 189:f392fc9709a3 | 115 | { |
| AnnaBridge | 189:f392fc9709a3 | 116 | 0U, /* 0: OIS1 */ |
| AnnaBridge | 189:f392fc9709a3 | 117 | 1U, /* 1: OIS1N */ |
| AnnaBridge | 189:f392fc9709a3 | 118 | 2U, /* 2: OIS2 */ |
| AnnaBridge | 189:f392fc9709a3 | 119 | 3U, /* 3: OIS2N */ |
| AnnaBridge | 189:f392fc9709a3 | 120 | 4U, /* 4: OIS3 */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | 5U, /* 5: OIS3N */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | 6U, /* 6: OIS4 */ |
| AnnaBridge | 189:f392fc9709a3 | 123 | 8U, /* 7: OIS5 */ |
| AnnaBridge | 189:f392fc9709a3 | 124 | 10U /* 8: OIS6 */ |
| AnnaBridge | 189:f392fc9709a3 | 125 | }; |
| AnnaBridge | 189:f392fc9709a3 | 126 | /** |
| AnnaBridge | 189:f392fc9709a3 | 127 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 128 | */ |
| AnnaBridge | 189:f392fc9709a3 | 129 | |
| AnnaBridge | 189:f392fc9709a3 | 130 | |
| AnnaBridge | 189:f392fc9709a3 | 131 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 132 | /** @defgroup TIM_LL_Private_Constants TIM Private Constants |
| AnnaBridge | 189:f392fc9709a3 | 133 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 134 | */ |
| AnnaBridge | 189:f392fc9709a3 | 135 | |
| AnnaBridge | 189:f392fc9709a3 | 136 | /* Defines used for the bit position in the register and perform offsets */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | #define TIM_POSITION_BRK_SOURCE POSITION_VAL(Source) |
| AnnaBridge | 189:f392fc9709a3 | 138 | |
| AnnaBridge | 189:f392fc9709a3 | 139 | /* Generic bit definitions for TIMx_OR2 register */ |
| AnnaBridge | 189:f392fc9709a3 | 140 | #define TIMx_OR2_BKINE TIM1_OR2_BKINE /*!< BRK BKIN input enable */ |
| AnnaBridge | 189:f392fc9709a3 | 141 | #define TIMx_OR2_BKCOMP1E TIM1_OR2_BKCMP1E /*!< BRK COMP1 enable */ |
| AnnaBridge | 189:f392fc9709a3 | 142 | #define TIMx_OR2_BKCOMP2E TIM1_OR2_BKCMP2E /*!< BRK COMP2 enable */ |
| AnnaBridge | 189:f392fc9709a3 | 143 | #if defined(DFSDM1_Channel0) |
| AnnaBridge | 189:f392fc9709a3 | 144 | #define TIMx_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E /*!< BRK DFSDM1_BREAK[0] enable */ |
| AnnaBridge | 189:f392fc9709a3 | 145 | #endif /* DFSDM1_Channel0 */ |
| AnnaBridge | 189:f392fc9709a3 | 146 | #define TIMx_OR2_BKINP TIM1_OR2_BKINP /*!< BRK BKIN input polarity */ |
| AnnaBridge | 189:f392fc9709a3 | 147 | #define TIMx_OR2_BKCOMP1P TIM1_OR2_BKCMP1P /*!< BRK COMP1 input polarity */ |
| AnnaBridge | 189:f392fc9709a3 | 148 | #define TIMx_OR2_BKCOMP2P TIM1_OR2_BKCMP2P /*!< BRK COMP2 input polarity */ |
| AnnaBridge | 189:f392fc9709a3 | 149 | #define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /*!< TIMx ETR source selection */ |
| AnnaBridge | 189:f392fc9709a3 | 150 | |
| AnnaBridge | 189:f392fc9709a3 | 151 | /* Generic bit definitions for TIMx_OR3 register */ |
| AnnaBridge | 189:f392fc9709a3 | 152 | #define TIMx_OR3_BK2INE TIM1_OR3_BK2INE /*!< BRK2 BKIN2 input enable */ |
| AnnaBridge | 189:f392fc9709a3 | 153 | #define TIMx_OR3_BK2COMP1E TIM1_OR3_BK2CMP1E /*!< BRK2 COMP1 enable */ |
| AnnaBridge | 189:f392fc9709a3 | 154 | #define TIMx_OR3_BK2COMP2E TIM1_OR3_BK2CMP2E /*!< BRK2 COMP2 enable */ |
| AnnaBridge | 189:f392fc9709a3 | 155 | #if defined(DFSDM1_Channel0) |
| AnnaBridge | 189:f392fc9709a3 | 156 | #define TIMx_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E /*!< BRK2 DFSDM1_BREAK[1] enable */ |
| AnnaBridge | 189:f392fc9709a3 | 157 | #endif /* DFSDM1_Channel0 */ |
| AnnaBridge | 189:f392fc9709a3 | 158 | #define TIMx_OR3_BK2INP TIM1_OR3_BK2INP /*!< BRK2 BKIN2 input polarity */ |
| AnnaBridge | 189:f392fc9709a3 | 159 | #define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P /*!< BRK2 COMP1 input polarity */ |
| AnnaBridge | 189:f392fc9709a3 | 160 | #define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P /*!< BRK2 COMP2 input polarity */ |
| AnnaBridge | 189:f392fc9709a3 | 161 | |
| AnnaBridge | 189:f392fc9709a3 | 162 | /* Remap mask definitions */ |
| AnnaBridge | 189:f392fc9709a3 | 163 | #define TIMx_OR1_RMP_SHIFT 16U |
| AnnaBridge | 189:f392fc9709a3 | 164 | #define TIMx_OR1_RMP_MASK 0x0000FFFFU |
| AnnaBridge | 189:f392fc9709a3 | 165 | #if defined(ADC3) |
| AnnaBridge | 189:f392fc9709a3 | 166 | #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) |
| AnnaBridge | 189:f392fc9709a3 | 167 | #else |
| AnnaBridge | 189:f392fc9709a3 | 168 | #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) |
| AnnaBridge | 189:f392fc9709a3 | 169 | #endif /* ADC3 */ |
| AnnaBridge | 189:f392fc9709a3 | 170 | #define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT) |
| AnnaBridge | 189:f392fc9709a3 | 171 | #define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) |
| AnnaBridge | 189:f392fc9709a3 | 172 | #if defined(ADC2) && defined(ADC3) |
| AnnaBridge | 189:f392fc9709a3 | 173 | #define TIM8_OR1_RMP_MASK ((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) |
| AnnaBridge | 189:f392fc9709a3 | 174 | #else |
| AnnaBridge | 189:f392fc9709a3 | 175 | #define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) |
| AnnaBridge | 189:f392fc9709a3 | 176 | #endif /* ADC2 & ADC3 */ |
| AnnaBridge | 189:f392fc9709a3 | 177 | #define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) |
| AnnaBridge | 189:f392fc9709a3 | 178 | #define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) |
| AnnaBridge | 189:f392fc9709a3 | 179 | #define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) |
| AnnaBridge | 189:f392fc9709a3 | 180 | |
| AnnaBridge | 189:f392fc9709a3 | 181 | /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | #define DT_DELAY_1 ((uint8_t)0x7F) |
| AnnaBridge | 189:f392fc9709a3 | 183 | #define DT_DELAY_2 ((uint8_t)0x3F) |
| AnnaBridge | 189:f392fc9709a3 | 184 | #define DT_DELAY_3 ((uint8_t)0x1F) |
| AnnaBridge | 189:f392fc9709a3 | 185 | #define DT_DELAY_4 ((uint8_t)0x1F) |
| AnnaBridge | 189:f392fc9709a3 | 186 | |
| AnnaBridge | 189:f392fc9709a3 | 187 | /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ |
| AnnaBridge | 189:f392fc9709a3 | 188 | #define DT_RANGE_1 ((uint8_t)0x00) |
| AnnaBridge | 189:f392fc9709a3 | 189 | #define DT_RANGE_2 ((uint8_t)0x80) |
| AnnaBridge | 189:f392fc9709a3 | 190 | #define DT_RANGE_3 ((uint8_t)0xC0) |
| AnnaBridge | 189:f392fc9709a3 | 191 | #define DT_RANGE_4 ((uint8_t)0xE0) |
| AnnaBridge | 189:f392fc9709a3 | 192 | |
| AnnaBridge | 189:f392fc9709a3 | 193 | /** Legacy definitions for compatibility purpose |
| AnnaBridge | 189:f392fc9709a3 | 194 | @cond 0 |
| AnnaBridge | 189:f392fc9709a3 | 195 | */ |
| AnnaBridge | 189:f392fc9709a3 | 196 | #if defined(DFSDM1_Channel0) |
| AnnaBridge | 189:f392fc9709a3 | 197 | #define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E |
| AnnaBridge | 189:f392fc9709a3 | 198 | #define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E |
| AnnaBridge | 189:f392fc9709a3 | 199 | #endif /* DFSDM1_Channel0 */ |
| AnnaBridge | 189:f392fc9709a3 | 200 | /** |
| AnnaBridge | 189:f392fc9709a3 | 201 | @endcond |
| AnnaBridge | 189:f392fc9709a3 | 202 | */ |
| AnnaBridge | 189:f392fc9709a3 | 203 | |
| AnnaBridge | 189:f392fc9709a3 | 204 | /** |
| AnnaBridge | 189:f392fc9709a3 | 205 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 206 | */ |
| AnnaBridge | 189:f392fc9709a3 | 207 | |
| AnnaBridge | 189:f392fc9709a3 | 208 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 209 | /** @defgroup TIM_LL_Private_Macros TIM Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 210 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 211 | */ |
| AnnaBridge | 189:f392fc9709a3 | 212 | /** @brief Convert channel id into channel index. |
| AnnaBridge | 189:f392fc9709a3 | 213 | * @param __CHANNEL__ This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 214 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 215 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| AnnaBridge | 189:f392fc9709a3 | 216 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 217 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| AnnaBridge | 189:f392fc9709a3 | 218 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 219 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| AnnaBridge | 189:f392fc9709a3 | 220 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 221 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 222 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 223 | * @retval none |
| AnnaBridge | 189:f392fc9709a3 | 224 | */ |
| AnnaBridge | 189:f392fc9709a3 | 225 | #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ |
| AnnaBridge | 189:f392fc9709a3 | 226 | (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ |
| AnnaBridge | 189:f392fc9709a3 | 227 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ |
| AnnaBridge | 189:f392fc9709a3 | 228 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ |
| AnnaBridge | 189:f392fc9709a3 | 229 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ |
| AnnaBridge | 189:f392fc9709a3 | 230 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ |
| AnnaBridge | 189:f392fc9709a3 | 231 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ |
| AnnaBridge | 189:f392fc9709a3 | 232 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ |
| AnnaBridge | 189:f392fc9709a3 | 233 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) |
| AnnaBridge | 189:f392fc9709a3 | 234 | |
| AnnaBridge | 189:f392fc9709a3 | 235 | /** @brief Calculate the deadtime sampling period(in ps). |
| AnnaBridge | 189:f392fc9709a3 | 236 | * @param __TIMCLK__ timer input clock frequency (in Hz). |
| AnnaBridge | 189:f392fc9709a3 | 237 | * @param __CKD__ This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 238 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 239 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 240 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 241 | * @retval none |
| AnnaBridge | 189:f392fc9709a3 | 242 | */ |
| AnnaBridge | 189:f392fc9709a3 | 243 | #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ |
| AnnaBridge | 189:f392fc9709a3 | 244 | (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ |
| AnnaBridge | 189:f392fc9709a3 | 245 | ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ |
| AnnaBridge | 189:f392fc9709a3 | 246 | ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) |
| AnnaBridge | 189:f392fc9709a3 | 247 | /** |
| AnnaBridge | 189:f392fc9709a3 | 248 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 249 | */ |
| AnnaBridge | 189:f392fc9709a3 | 250 | |
| AnnaBridge | 189:f392fc9709a3 | 251 | |
| AnnaBridge | 189:f392fc9709a3 | 252 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 253 | #if defined(USE_FULL_LL_DRIVER) |
| AnnaBridge | 189:f392fc9709a3 | 254 | /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure |
| AnnaBridge | 189:f392fc9709a3 | 255 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 256 | */ |
| AnnaBridge | 189:f392fc9709a3 | 257 | |
| AnnaBridge | 189:f392fc9709a3 | 258 | /** |
| AnnaBridge | 189:f392fc9709a3 | 259 | * @brief TIM Time Base configuration structure definition. |
| AnnaBridge | 189:f392fc9709a3 | 260 | */ |
| AnnaBridge | 189:f392fc9709a3 | 261 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 262 | { |
| AnnaBridge | 189:f392fc9709a3 | 263 | uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
| AnnaBridge | 189:f392fc9709a3 | 264 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 265 | |
| AnnaBridge | 189:f392fc9709a3 | 266 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ |
| AnnaBridge | 189:f392fc9709a3 | 267 | |
| AnnaBridge | 189:f392fc9709a3 | 268 | uint32_t CounterMode; /*!< Specifies the counter mode. |
| AnnaBridge | 189:f392fc9709a3 | 269 | This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. |
| AnnaBridge | 189:f392fc9709a3 | 270 | |
| AnnaBridge | 189:f392fc9709a3 | 271 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ |
| AnnaBridge | 189:f392fc9709a3 | 272 | |
| AnnaBridge | 189:f392fc9709a3 | 273 | uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active |
| AnnaBridge | 189:f392fc9709a3 | 274 | Auto-Reload Register at the next update event. |
| AnnaBridge | 189:f392fc9709a3 | 275 | This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 276 | Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 277 | |
| AnnaBridge | 189:f392fc9709a3 | 278 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ |
| AnnaBridge | 189:f392fc9709a3 | 279 | |
| AnnaBridge | 189:f392fc9709a3 | 280 | uint32_t ClockDivision; /*!< Specifies the clock division. |
| AnnaBridge | 189:f392fc9709a3 | 281 | This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. |
| AnnaBridge | 189:f392fc9709a3 | 282 | |
| AnnaBridge | 189:f392fc9709a3 | 283 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ |
| AnnaBridge | 189:f392fc9709a3 | 284 | |
| AnnaBridge | 189:f392fc9709a3 | 285 | uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
| AnnaBridge | 189:f392fc9709a3 | 286 | reaches zero, an update event is generated and counting restarts |
| AnnaBridge | 189:f392fc9709a3 | 287 | from the RCR value (N). |
| AnnaBridge | 189:f392fc9709a3 | 288 | This means in PWM mode that (N+1) corresponds to: |
| AnnaBridge | 189:f392fc9709a3 | 289 | - the number of PWM periods in edge-aligned mode |
| AnnaBridge | 189:f392fc9709a3 | 290 | - the number of half PWM period in center-aligned mode |
| AnnaBridge | 189:f392fc9709a3 | 291 | This parameter must be a number between 0x00 and 0xFF. |
| AnnaBridge | 189:f392fc9709a3 | 292 | |
| AnnaBridge | 189:f392fc9709a3 | 293 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ |
| AnnaBridge | 189:f392fc9709a3 | 294 | } LL_TIM_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 295 | |
| AnnaBridge | 189:f392fc9709a3 | 296 | /** |
| AnnaBridge | 189:f392fc9709a3 | 297 | * @brief TIM Output Compare configuration structure definition. |
| AnnaBridge | 189:f392fc9709a3 | 298 | */ |
| AnnaBridge | 189:f392fc9709a3 | 299 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 300 | { |
| AnnaBridge | 189:f392fc9709a3 | 301 | uint32_t OCMode; /*!< Specifies the output mode. |
| AnnaBridge | 189:f392fc9709a3 | 302 | This parameter can be a value of @ref TIM_LL_EC_OCMODE. |
| AnnaBridge | 189:f392fc9709a3 | 303 | |
| AnnaBridge | 189:f392fc9709a3 | 304 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ |
| AnnaBridge | 189:f392fc9709a3 | 305 | |
| AnnaBridge | 189:f392fc9709a3 | 306 | uint32_t OCState; /*!< Specifies the TIM Output Compare state. |
| AnnaBridge | 189:f392fc9709a3 | 307 | This parameter can be a value of @ref TIM_LL_EC_OCSTATE. |
| AnnaBridge | 189:f392fc9709a3 | 308 | |
| AnnaBridge | 189:f392fc9709a3 | 309 | This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ |
| AnnaBridge | 189:f392fc9709a3 | 310 | |
| AnnaBridge | 189:f392fc9709a3 | 311 | uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. |
| AnnaBridge | 189:f392fc9709a3 | 312 | This parameter can be a value of @ref TIM_LL_EC_OCSTATE. |
| AnnaBridge | 189:f392fc9709a3 | 313 | |
| AnnaBridge | 189:f392fc9709a3 | 314 | This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ |
| AnnaBridge | 189:f392fc9709a3 | 315 | |
| AnnaBridge | 189:f392fc9709a3 | 316 | uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. |
| AnnaBridge | 189:f392fc9709a3 | 317 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 318 | |
| AnnaBridge | 189:f392fc9709a3 | 319 | This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ |
| AnnaBridge | 189:f392fc9709a3 | 320 | |
| AnnaBridge | 189:f392fc9709a3 | 321 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
| AnnaBridge | 189:f392fc9709a3 | 322 | This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. |
| AnnaBridge | 189:f392fc9709a3 | 323 | |
| AnnaBridge | 189:f392fc9709a3 | 324 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ |
| AnnaBridge | 189:f392fc9709a3 | 325 | |
| AnnaBridge | 189:f392fc9709a3 | 326 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
| AnnaBridge | 189:f392fc9709a3 | 327 | This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. |
| AnnaBridge | 189:f392fc9709a3 | 328 | |
| AnnaBridge | 189:f392fc9709a3 | 329 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ |
| AnnaBridge | 189:f392fc9709a3 | 330 | |
| AnnaBridge | 189:f392fc9709a3 | 331 | |
| AnnaBridge | 189:f392fc9709a3 | 332 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
| AnnaBridge | 189:f392fc9709a3 | 333 | This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. |
| AnnaBridge | 189:f392fc9709a3 | 334 | |
| AnnaBridge | 189:f392fc9709a3 | 335 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ |
| AnnaBridge | 189:f392fc9709a3 | 336 | |
| AnnaBridge | 189:f392fc9709a3 | 337 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
| AnnaBridge | 189:f392fc9709a3 | 338 | This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. |
| AnnaBridge | 189:f392fc9709a3 | 339 | |
| AnnaBridge | 189:f392fc9709a3 | 340 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ |
| AnnaBridge | 189:f392fc9709a3 | 341 | } LL_TIM_OC_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 342 | |
| AnnaBridge | 189:f392fc9709a3 | 343 | /** |
| AnnaBridge | 189:f392fc9709a3 | 344 | * @brief TIM Input Capture configuration structure definition. |
| AnnaBridge | 189:f392fc9709a3 | 345 | */ |
| AnnaBridge | 189:f392fc9709a3 | 346 | |
| AnnaBridge | 189:f392fc9709a3 | 347 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 348 | { |
| AnnaBridge | 189:f392fc9709a3 | 349 | |
| AnnaBridge | 189:f392fc9709a3 | 350 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
| AnnaBridge | 189:f392fc9709a3 | 351 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
| AnnaBridge | 189:f392fc9709a3 | 352 | |
| AnnaBridge | 189:f392fc9709a3 | 353 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
| AnnaBridge | 189:f392fc9709a3 | 354 | |
| AnnaBridge | 189:f392fc9709a3 | 355 | uint32_t ICActiveInput; /*!< Specifies the input. |
| AnnaBridge | 189:f392fc9709a3 | 356 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
| AnnaBridge | 189:f392fc9709a3 | 357 | |
| AnnaBridge | 189:f392fc9709a3 | 358 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ |
| AnnaBridge | 189:f392fc9709a3 | 359 | |
| AnnaBridge | 189:f392fc9709a3 | 360 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
| AnnaBridge | 189:f392fc9709a3 | 361 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
| AnnaBridge | 189:f392fc9709a3 | 362 | |
| AnnaBridge | 189:f392fc9709a3 | 363 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
| AnnaBridge | 189:f392fc9709a3 | 364 | |
| AnnaBridge | 189:f392fc9709a3 | 365 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
| AnnaBridge | 189:f392fc9709a3 | 366 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
| AnnaBridge | 189:f392fc9709a3 | 367 | |
| AnnaBridge | 189:f392fc9709a3 | 368 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
| AnnaBridge | 189:f392fc9709a3 | 369 | } LL_TIM_IC_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 370 | |
| AnnaBridge | 189:f392fc9709a3 | 371 | |
| AnnaBridge | 189:f392fc9709a3 | 372 | /** |
| AnnaBridge | 189:f392fc9709a3 | 373 | * @brief TIM Encoder interface configuration structure definition. |
| AnnaBridge | 189:f392fc9709a3 | 374 | */ |
| AnnaBridge | 189:f392fc9709a3 | 375 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 376 | { |
| AnnaBridge | 189:f392fc9709a3 | 377 | uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). |
| AnnaBridge | 189:f392fc9709a3 | 378 | This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. |
| AnnaBridge | 189:f392fc9709a3 | 379 | |
| AnnaBridge | 189:f392fc9709a3 | 380 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ |
| AnnaBridge | 189:f392fc9709a3 | 381 | |
| AnnaBridge | 189:f392fc9709a3 | 382 | uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. |
| AnnaBridge | 189:f392fc9709a3 | 383 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
| AnnaBridge | 189:f392fc9709a3 | 384 | |
| AnnaBridge | 189:f392fc9709a3 | 385 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
| AnnaBridge | 189:f392fc9709a3 | 386 | |
| AnnaBridge | 189:f392fc9709a3 | 387 | uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source |
| AnnaBridge | 189:f392fc9709a3 | 388 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
| AnnaBridge | 189:f392fc9709a3 | 389 | |
| AnnaBridge | 189:f392fc9709a3 | 390 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ |
| AnnaBridge | 189:f392fc9709a3 | 391 | |
| AnnaBridge | 189:f392fc9709a3 | 392 | uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. |
| AnnaBridge | 189:f392fc9709a3 | 393 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
| AnnaBridge | 189:f392fc9709a3 | 394 | |
| AnnaBridge | 189:f392fc9709a3 | 395 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
| AnnaBridge | 189:f392fc9709a3 | 396 | |
| AnnaBridge | 189:f392fc9709a3 | 397 | uint32_t IC1Filter; /*!< Specifies the TI1 input filter. |
| AnnaBridge | 189:f392fc9709a3 | 398 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
| AnnaBridge | 189:f392fc9709a3 | 399 | |
| AnnaBridge | 189:f392fc9709a3 | 400 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
| AnnaBridge | 189:f392fc9709a3 | 401 | |
| AnnaBridge | 189:f392fc9709a3 | 402 | uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. |
| AnnaBridge | 189:f392fc9709a3 | 403 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
| AnnaBridge | 189:f392fc9709a3 | 404 | |
| AnnaBridge | 189:f392fc9709a3 | 405 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
| AnnaBridge | 189:f392fc9709a3 | 406 | |
| AnnaBridge | 189:f392fc9709a3 | 407 | uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source |
| AnnaBridge | 189:f392fc9709a3 | 408 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
| AnnaBridge | 189:f392fc9709a3 | 409 | |
| AnnaBridge | 189:f392fc9709a3 | 410 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ |
| AnnaBridge | 189:f392fc9709a3 | 411 | |
| AnnaBridge | 189:f392fc9709a3 | 412 | uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. |
| AnnaBridge | 189:f392fc9709a3 | 413 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
| AnnaBridge | 189:f392fc9709a3 | 414 | |
| AnnaBridge | 189:f392fc9709a3 | 415 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
| AnnaBridge | 189:f392fc9709a3 | 416 | |
| AnnaBridge | 189:f392fc9709a3 | 417 | uint32_t IC2Filter; /*!< Specifies the TI2 input filter. |
| AnnaBridge | 189:f392fc9709a3 | 418 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
| AnnaBridge | 189:f392fc9709a3 | 419 | |
| AnnaBridge | 189:f392fc9709a3 | 420 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
| AnnaBridge | 189:f392fc9709a3 | 421 | |
| AnnaBridge | 189:f392fc9709a3 | 422 | } LL_TIM_ENCODER_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 423 | |
| AnnaBridge | 189:f392fc9709a3 | 424 | /** |
| AnnaBridge | 189:f392fc9709a3 | 425 | * @brief TIM Hall sensor interface configuration structure definition. |
| AnnaBridge | 189:f392fc9709a3 | 426 | */ |
| AnnaBridge | 189:f392fc9709a3 | 427 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 428 | { |
| AnnaBridge | 189:f392fc9709a3 | 429 | |
| AnnaBridge | 189:f392fc9709a3 | 430 | uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. |
| AnnaBridge | 189:f392fc9709a3 | 431 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
| AnnaBridge | 189:f392fc9709a3 | 432 | |
| AnnaBridge | 189:f392fc9709a3 | 433 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
| AnnaBridge | 189:f392fc9709a3 | 434 | |
| AnnaBridge | 189:f392fc9709a3 | 435 | uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. |
| AnnaBridge | 189:f392fc9709a3 | 436 | Prescaler must be set to get a maximum counter period longer than the |
| AnnaBridge | 189:f392fc9709a3 | 437 | time interval between 2 consecutive changes on the Hall inputs. |
| AnnaBridge | 189:f392fc9709a3 | 438 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
| AnnaBridge | 189:f392fc9709a3 | 439 | |
| AnnaBridge | 189:f392fc9709a3 | 440 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
| AnnaBridge | 189:f392fc9709a3 | 441 | |
| AnnaBridge | 189:f392fc9709a3 | 442 | uint32_t IC1Filter; /*!< Specifies the TI1 input filter. |
| AnnaBridge | 189:f392fc9709a3 | 443 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
| AnnaBridge | 189:f392fc9709a3 | 444 | |
| AnnaBridge | 189:f392fc9709a3 | 445 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
| AnnaBridge | 189:f392fc9709a3 | 446 | |
| AnnaBridge | 189:f392fc9709a3 | 447 | uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. |
| AnnaBridge | 189:f392fc9709a3 | 448 | A positive pulse (TRGO event) is generated with a programmable delay every time |
| AnnaBridge | 189:f392fc9709a3 | 449 | a change occurs on the Hall inputs. |
| AnnaBridge | 189:f392fc9709a3 | 450 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 451 | |
| AnnaBridge | 189:f392fc9709a3 | 452 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ |
| AnnaBridge | 189:f392fc9709a3 | 453 | } LL_TIM_HALLSENSOR_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 454 | |
| AnnaBridge | 189:f392fc9709a3 | 455 | /** |
| AnnaBridge | 189:f392fc9709a3 | 456 | * @brief BDTR (Break and Dead Time) structure definition |
| AnnaBridge | 189:f392fc9709a3 | 457 | */ |
| AnnaBridge | 189:f392fc9709a3 | 458 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 459 | { |
| AnnaBridge | 189:f392fc9709a3 | 460 | uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. |
| AnnaBridge | 189:f392fc9709a3 | 461 | This parameter can be a value of @ref TIM_LL_EC_OSSR |
| AnnaBridge | 189:f392fc9709a3 | 462 | |
| AnnaBridge | 189:f392fc9709a3 | 463 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() |
| AnnaBridge | 189:f392fc9709a3 | 464 | |
| AnnaBridge | 189:f392fc9709a3 | 465 | @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ |
| AnnaBridge | 189:f392fc9709a3 | 466 | |
| AnnaBridge | 189:f392fc9709a3 | 467 | uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. |
| AnnaBridge | 189:f392fc9709a3 | 468 | This parameter can be a value of @ref TIM_LL_EC_OSSI |
| AnnaBridge | 189:f392fc9709a3 | 469 | |
| AnnaBridge | 189:f392fc9709a3 | 470 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() |
| AnnaBridge | 189:f392fc9709a3 | 471 | |
| AnnaBridge | 189:f392fc9709a3 | 472 | @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ |
| AnnaBridge | 189:f392fc9709a3 | 473 | |
| AnnaBridge | 189:f392fc9709a3 | 474 | uint32_t LockLevel; /*!< Specifies the LOCK level parameters. |
| AnnaBridge | 189:f392fc9709a3 | 475 | This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL |
| AnnaBridge | 189:f392fc9709a3 | 476 | |
| AnnaBridge | 189:f392fc9709a3 | 477 | @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register |
| AnnaBridge | 189:f392fc9709a3 | 478 | has been written, their content is frozen until the next reset.*/ |
| AnnaBridge | 189:f392fc9709a3 | 479 | |
| AnnaBridge | 189:f392fc9709a3 | 480 | uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the |
| AnnaBridge | 189:f392fc9709a3 | 481 | switching-on of the outputs. |
| AnnaBridge | 189:f392fc9709a3 | 482 | This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
| AnnaBridge | 189:f392fc9709a3 | 483 | |
| AnnaBridge | 189:f392fc9709a3 | 484 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() |
| AnnaBridge | 189:f392fc9709a3 | 485 | |
| AnnaBridge | 189:f392fc9709a3 | 486 | @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ |
| AnnaBridge | 189:f392fc9709a3 | 487 | |
| AnnaBridge | 189:f392fc9709a3 | 488 | uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. |
| AnnaBridge | 189:f392fc9709a3 | 489 | This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE |
| AnnaBridge | 189:f392fc9709a3 | 490 | |
| AnnaBridge | 189:f392fc9709a3 | 491 | This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() |
| AnnaBridge | 189:f392fc9709a3 | 492 | |
| AnnaBridge | 189:f392fc9709a3 | 493 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
| AnnaBridge | 189:f392fc9709a3 | 494 | |
| AnnaBridge | 189:f392fc9709a3 | 495 | uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. |
| AnnaBridge | 189:f392fc9709a3 | 496 | This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY |
| AnnaBridge | 189:f392fc9709a3 | 497 | |
| AnnaBridge | 189:f392fc9709a3 | 498 | This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() |
| AnnaBridge | 189:f392fc9709a3 | 499 | |
| AnnaBridge | 189:f392fc9709a3 | 500 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
| AnnaBridge | 189:f392fc9709a3 | 501 | |
| AnnaBridge | 189:f392fc9709a3 | 502 | uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. |
| AnnaBridge | 189:f392fc9709a3 | 503 | This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER |
| AnnaBridge | 189:f392fc9709a3 | 504 | |
| AnnaBridge | 189:f392fc9709a3 | 505 | This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() |
| AnnaBridge | 189:f392fc9709a3 | 506 | |
| AnnaBridge | 189:f392fc9709a3 | 507 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
| AnnaBridge | 189:f392fc9709a3 | 508 | |
| AnnaBridge | 189:f392fc9709a3 | 509 | uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. |
| AnnaBridge | 189:f392fc9709a3 | 510 | This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE |
| AnnaBridge | 189:f392fc9709a3 | 511 | |
| AnnaBridge | 189:f392fc9709a3 | 512 | This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() |
| AnnaBridge | 189:f392fc9709a3 | 513 | |
| AnnaBridge | 189:f392fc9709a3 | 514 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
| AnnaBridge | 189:f392fc9709a3 | 515 | |
| AnnaBridge | 189:f392fc9709a3 | 516 | uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. |
| AnnaBridge | 189:f392fc9709a3 | 517 | This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY |
| AnnaBridge | 189:f392fc9709a3 | 518 | |
| AnnaBridge | 189:f392fc9709a3 | 519 | This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() |
| AnnaBridge | 189:f392fc9709a3 | 520 | |
| AnnaBridge | 189:f392fc9709a3 | 521 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
| AnnaBridge | 189:f392fc9709a3 | 522 | |
| AnnaBridge | 189:f392fc9709a3 | 523 | uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. |
| AnnaBridge | 189:f392fc9709a3 | 524 | This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER |
| AnnaBridge | 189:f392fc9709a3 | 525 | |
| AnnaBridge | 189:f392fc9709a3 | 526 | This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() |
| AnnaBridge | 189:f392fc9709a3 | 527 | |
| AnnaBridge | 189:f392fc9709a3 | 528 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
| AnnaBridge | 189:f392fc9709a3 | 529 | |
| AnnaBridge | 189:f392fc9709a3 | 530 | uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. |
| AnnaBridge | 189:f392fc9709a3 | 531 | This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE |
| AnnaBridge | 189:f392fc9709a3 | 532 | |
| AnnaBridge | 189:f392fc9709a3 | 533 | This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() |
| AnnaBridge | 189:f392fc9709a3 | 534 | |
| AnnaBridge | 189:f392fc9709a3 | 535 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
| AnnaBridge | 189:f392fc9709a3 | 536 | } LL_TIM_BDTR_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 537 | |
| AnnaBridge | 189:f392fc9709a3 | 538 | /** |
| AnnaBridge | 189:f392fc9709a3 | 539 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 540 | */ |
| AnnaBridge | 189:f392fc9709a3 | 541 | #endif /* USE_FULL_LL_DRIVER */ |
| AnnaBridge | 189:f392fc9709a3 | 542 | |
| AnnaBridge | 189:f392fc9709a3 | 543 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 544 | /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 545 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 546 | */ |
| AnnaBridge | 189:f392fc9709a3 | 547 | |
| AnnaBridge | 189:f392fc9709a3 | 548 | /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines |
| AnnaBridge | 189:f392fc9709a3 | 549 | * @brief Flags defines which can be used with LL_TIM_ReadReg function. |
| AnnaBridge | 189:f392fc9709a3 | 550 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 551 | */ |
| AnnaBridge | 189:f392fc9709a3 | 552 | #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ |
| AnnaBridge | 189:f392fc9709a3 | 553 | #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ |
| AnnaBridge | 189:f392fc9709a3 | 554 | #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ |
| AnnaBridge | 189:f392fc9709a3 | 555 | #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ |
| AnnaBridge | 189:f392fc9709a3 | 556 | #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ |
| AnnaBridge | 189:f392fc9709a3 | 557 | #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ |
| AnnaBridge | 189:f392fc9709a3 | 558 | #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ |
| AnnaBridge | 189:f392fc9709a3 | 559 | #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ |
| AnnaBridge | 189:f392fc9709a3 | 560 | #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ |
| AnnaBridge | 189:f392fc9709a3 | 561 | #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ |
| AnnaBridge | 189:f392fc9709a3 | 562 | #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ |
| AnnaBridge | 189:f392fc9709a3 | 563 | #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ |
| AnnaBridge | 189:f392fc9709a3 | 564 | #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ |
| AnnaBridge | 189:f392fc9709a3 | 565 | #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ |
| AnnaBridge | 189:f392fc9709a3 | 566 | #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ |
| AnnaBridge | 189:f392fc9709a3 | 567 | #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ |
| AnnaBridge | 189:f392fc9709a3 | 568 | /** |
| AnnaBridge | 189:f392fc9709a3 | 569 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 570 | */ |
| AnnaBridge | 189:f392fc9709a3 | 571 | |
| AnnaBridge | 189:f392fc9709a3 | 572 | #if defined(USE_FULL_LL_DRIVER) |
| AnnaBridge | 189:f392fc9709a3 | 573 | /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable |
| AnnaBridge | 189:f392fc9709a3 | 574 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 575 | */ |
| AnnaBridge | 189:f392fc9709a3 | 576 | #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 577 | #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ |
| AnnaBridge | 189:f392fc9709a3 | 578 | /** |
| AnnaBridge | 189:f392fc9709a3 | 579 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 580 | */ |
| AnnaBridge | 189:f392fc9709a3 | 581 | |
| AnnaBridge | 189:f392fc9709a3 | 582 | /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable |
| AnnaBridge | 189:f392fc9709a3 | 583 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 584 | */ |
| AnnaBridge | 189:f392fc9709a3 | 585 | #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 586 | #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ |
| AnnaBridge | 189:f392fc9709a3 | 587 | /** |
| AnnaBridge | 189:f392fc9709a3 | 588 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 589 | */ |
| AnnaBridge | 189:f392fc9709a3 | 590 | |
| AnnaBridge | 189:f392fc9709a3 | 591 | /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable |
| AnnaBridge | 189:f392fc9709a3 | 592 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 593 | */ |
| AnnaBridge | 189:f392fc9709a3 | 594 | #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ |
| AnnaBridge | 189:f392fc9709a3 | 595 | #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ |
| AnnaBridge | 189:f392fc9709a3 | 596 | /** |
| AnnaBridge | 189:f392fc9709a3 | 597 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 598 | */ |
| AnnaBridge | 189:f392fc9709a3 | 599 | #endif /* USE_FULL_LL_DRIVER */ |
| AnnaBridge | 189:f392fc9709a3 | 600 | |
| AnnaBridge | 189:f392fc9709a3 | 601 | /** @defgroup TIM_LL_EC_IT IT Defines |
| AnnaBridge | 189:f392fc9709a3 | 602 | * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. |
| AnnaBridge | 189:f392fc9709a3 | 603 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 604 | */ |
| AnnaBridge | 189:f392fc9709a3 | 605 | #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 606 | #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 607 | #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 608 | #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 609 | #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 610 | #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 611 | #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 612 | #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 613 | /** |
| AnnaBridge | 189:f392fc9709a3 | 614 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 615 | */ |
| AnnaBridge | 189:f392fc9709a3 | 616 | |
| AnnaBridge | 189:f392fc9709a3 | 617 | /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source |
| AnnaBridge | 189:f392fc9709a3 | 618 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 619 | */ |
| AnnaBridge | 189:f392fc9709a3 | 620 | #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ |
| AnnaBridge | 189:f392fc9709a3 | 621 | #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ |
| AnnaBridge | 189:f392fc9709a3 | 622 | /** |
| AnnaBridge | 189:f392fc9709a3 | 623 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 624 | */ |
| AnnaBridge | 189:f392fc9709a3 | 625 | |
| AnnaBridge | 189:f392fc9709a3 | 626 | /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode |
| AnnaBridge | 189:f392fc9709a3 | 627 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 628 | */ |
| AnnaBridge | 189:f392fc9709a3 | 629 | #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ |
| AnnaBridge | 189:f392fc9709a3 | 630 | #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ |
| AnnaBridge | 189:f392fc9709a3 | 631 | /** |
| AnnaBridge | 189:f392fc9709a3 | 632 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 633 | */ |
| AnnaBridge | 189:f392fc9709a3 | 634 | |
| AnnaBridge | 189:f392fc9709a3 | 635 | /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode |
| AnnaBridge | 189:f392fc9709a3 | 636 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 637 | */ |
| AnnaBridge | 189:f392fc9709a3 | 638 | #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */ |
| AnnaBridge | 189:f392fc9709a3 | 639 | #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ |
| AnnaBridge | 189:f392fc9709a3 | 640 | #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ |
| AnnaBridge | 189:f392fc9709a3 | 641 | #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ |
| AnnaBridge | 189:f392fc9709a3 | 642 | #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ |
| AnnaBridge | 189:f392fc9709a3 | 643 | /** |
| AnnaBridge | 189:f392fc9709a3 | 644 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 645 | */ |
| AnnaBridge | 189:f392fc9709a3 | 646 | |
| AnnaBridge | 189:f392fc9709a3 | 647 | /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division |
| AnnaBridge | 189:f392fc9709a3 | 648 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 649 | */ |
| AnnaBridge | 189:f392fc9709a3 | 650 | #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ |
| AnnaBridge | 189:f392fc9709a3 | 651 | #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ |
| AnnaBridge | 189:f392fc9709a3 | 652 | #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ |
| AnnaBridge | 189:f392fc9709a3 | 653 | /** |
| AnnaBridge | 189:f392fc9709a3 | 654 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 655 | */ |
| AnnaBridge | 189:f392fc9709a3 | 656 | |
| AnnaBridge | 189:f392fc9709a3 | 657 | /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction |
| AnnaBridge | 189:f392fc9709a3 | 658 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 659 | */ |
| AnnaBridge | 189:f392fc9709a3 | 660 | #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ |
| AnnaBridge | 189:f392fc9709a3 | 661 | #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ |
| AnnaBridge | 189:f392fc9709a3 | 662 | /** |
| AnnaBridge | 189:f392fc9709a3 | 663 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 664 | */ |
| AnnaBridge | 189:f392fc9709a3 | 665 | |
| AnnaBridge | 189:f392fc9709a3 | 666 | /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source |
| AnnaBridge | 189:f392fc9709a3 | 667 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 668 | */ |
| AnnaBridge | 189:f392fc9709a3 | 669 | #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ |
| AnnaBridge | 189:f392fc9709a3 | 670 | #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ |
| AnnaBridge | 189:f392fc9709a3 | 671 | /** |
| AnnaBridge | 189:f392fc9709a3 | 672 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 673 | */ |
| AnnaBridge | 189:f392fc9709a3 | 674 | |
| AnnaBridge | 189:f392fc9709a3 | 675 | /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request |
| AnnaBridge | 189:f392fc9709a3 | 676 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 677 | */ |
| AnnaBridge | 189:f392fc9709a3 | 678 | #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ |
| AnnaBridge | 189:f392fc9709a3 | 679 | #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ |
| AnnaBridge | 189:f392fc9709a3 | 680 | /** |
| AnnaBridge | 189:f392fc9709a3 | 681 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 682 | */ |
| AnnaBridge | 189:f392fc9709a3 | 683 | |
| AnnaBridge | 189:f392fc9709a3 | 684 | /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level |
| AnnaBridge | 189:f392fc9709a3 | 685 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 686 | */ |
| AnnaBridge | 189:f392fc9709a3 | 687 | #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ |
| AnnaBridge | 189:f392fc9709a3 | 688 | #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 689 | #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 690 | #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 691 | /** |
| AnnaBridge | 189:f392fc9709a3 | 692 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 693 | */ |
| AnnaBridge | 189:f392fc9709a3 | 694 | |
| AnnaBridge | 189:f392fc9709a3 | 695 | /** @defgroup TIM_LL_EC_CHANNEL Channel |
| AnnaBridge | 189:f392fc9709a3 | 696 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 697 | */ |
| AnnaBridge | 189:f392fc9709a3 | 698 | #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 699 | #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 700 | #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 701 | #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 702 | #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 703 | #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 704 | #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ |
| AnnaBridge | 189:f392fc9709a3 | 705 | #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ |
| AnnaBridge | 189:f392fc9709a3 | 706 | #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ |
| AnnaBridge | 189:f392fc9709a3 | 707 | /** |
| AnnaBridge | 189:f392fc9709a3 | 708 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 709 | */ |
| AnnaBridge | 189:f392fc9709a3 | 710 | |
| AnnaBridge | 189:f392fc9709a3 | 711 | #if defined(USE_FULL_LL_DRIVER) |
| AnnaBridge | 189:f392fc9709a3 | 712 | /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State |
| AnnaBridge | 189:f392fc9709a3 | 713 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 714 | */ |
| AnnaBridge | 189:f392fc9709a3 | 715 | #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ |
| AnnaBridge | 189:f392fc9709a3 | 716 | #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ |
| AnnaBridge | 189:f392fc9709a3 | 717 | /** |
| AnnaBridge | 189:f392fc9709a3 | 718 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 719 | */ |
| AnnaBridge | 189:f392fc9709a3 | 720 | #endif /* USE_FULL_LL_DRIVER */ |
| AnnaBridge | 189:f392fc9709a3 | 721 | |
| AnnaBridge | 189:f392fc9709a3 | 722 | /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode |
| AnnaBridge | 189:f392fc9709a3 | 723 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 724 | */ |
| AnnaBridge | 189:f392fc9709a3 | 725 | #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ |
| AnnaBridge | 189:f392fc9709a3 | 726 | #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ |
| AnnaBridge | 189:f392fc9709a3 | 727 | #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ |
| AnnaBridge | 189:f392fc9709a3 | 728 | #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ |
| AnnaBridge | 189:f392fc9709a3 | 729 | #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/ |
| AnnaBridge | 189:f392fc9709a3 | 730 | #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ |
| AnnaBridge | 189:f392fc9709a3 | 731 | #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ |
| AnnaBridge | 189:f392fc9709a3 | 732 | #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ |
| AnnaBridge | 189:f392fc9709a3 | 733 | #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/ |
| AnnaBridge | 189:f392fc9709a3 | 734 | #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/ |
| AnnaBridge | 189:f392fc9709a3 | 735 | #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/ |
| AnnaBridge | 189:f392fc9709a3 | 736 | #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/ |
| AnnaBridge | 189:f392fc9709a3 | 737 | #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/ |
| AnnaBridge | 189:f392fc9709a3 | 738 | #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/ |
| AnnaBridge | 189:f392fc9709a3 | 739 | /** |
| AnnaBridge | 189:f392fc9709a3 | 740 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 741 | */ |
| AnnaBridge | 189:f392fc9709a3 | 742 | |
| AnnaBridge | 189:f392fc9709a3 | 743 | /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity |
| AnnaBridge | 189:f392fc9709a3 | 744 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 745 | */ |
| AnnaBridge | 189:f392fc9709a3 | 746 | #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ |
| AnnaBridge | 189:f392fc9709a3 | 747 | #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ |
| AnnaBridge | 189:f392fc9709a3 | 748 | /** |
| AnnaBridge | 189:f392fc9709a3 | 749 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 750 | */ |
| AnnaBridge | 189:f392fc9709a3 | 751 | |
| AnnaBridge | 189:f392fc9709a3 | 752 | /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State |
| AnnaBridge | 189:f392fc9709a3 | 753 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 754 | */ |
| AnnaBridge | 189:f392fc9709a3 | 755 | #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/ |
| AnnaBridge | 189:f392fc9709a3 | 756 | #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/ |
| AnnaBridge | 189:f392fc9709a3 | 757 | /** |
| AnnaBridge | 189:f392fc9709a3 | 758 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 759 | */ |
| AnnaBridge | 189:f392fc9709a3 | 760 | |
| AnnaBridge | 189:f392fc9709a3 | 761 | /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5 |
| AnnaBridge | 189:f392fc9709a3 | 762 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 763 | */ |
| AnnaBridge | 189:f392fc9709a3 | 764 | #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ |
| AnnaBridge | 189:f392fc9709a3 | 765 | #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ |
| AnnaBridge | 189:f392fc9709a3 | 766 | #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ |
| AnnaBridge | 189:f392fc9709a3 | 767 | #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ |
| AnnaBridge | 189:f392fc9709a3 | 768 | /** |
| AnnaBridge | 189:f392fc9709a3 | 769 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 770 | */ |
| AnnaBridge | 189:f392fc9709a3 | 771 | |
| AnnaBridge | 189:f392fc9709a3 | 772 | /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection |
| AnnaBridge | 189:f392fc9709a3 | 773 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 774 | */ |
| AnnaBridge | 189:f392fc9709a3 | 775 | #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ |
| AnnaBridge | 189:f392fc9709a3 | 776 | #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ |
| AnnaBridge | 189:f392fc9709a3 | 777 | #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ |
| AnnaBridge | 189:f392fc9709a3 | 778 | /** |
| AnnaBridge | 189:f392fc9709a3 | 779 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 780 | */ |
| AnnaBridge | 189:f392fc9709a3 | 781 | |
| AnnaBridge | 189:f392fc9709a3 | 782 | /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler |
| AnnaBridge | 189:f392fc9709a3 | 783 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 784 | */ |
| AnnaBridge | 189:f392fc9709a3 | 785 | #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ |
| AnnaBridge | 189:f392fc9709a3 | 786 | #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ |
| AnnaBridge | 189:f392fc9709a3 | 787 | #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ |
| AnnaBridge | 189:f392fc9709a3 | 788 | #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ |
| AnnaBridge | 189:f392fc9709a3 | 789 | /** |
| AnnaBridge | 189:f392fc9709a3 | 790 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 791 | */ |
| AnnaBridge | 189:f392fc9709a3 | 792 | |
| AnnaBridge | 189:f392fc9709a3 | 793 | /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter |
| AnnaBridge | 189:f392fc9709a3 | 794 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 795 | */ |
| AnnaBridge | 189:f392fc9709a3 | 796 | #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
| AnnaBridge | 189:f392fc9709a3 | 797 | #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ |
| AnnaBridge | 189:f392fc9709a3 | 798 | #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ |
| AnnaBridge | 189:f392fc9709a3 | 799 | #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 800 | #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 801 | #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 802 | #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 803 | #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 804 | #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 805 | #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 806 | #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ |
| AnnaBridge | 189:f392fc9709a3 | 807 | #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 808 | #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 809 | #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ |
| AnnaBridge | 189:f392fc9709a3 | 810 | #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 811 | #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 812 | /** |
| AnnaBridge | 189:f392fc9709a3 | 813 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 814 | */ |
| AnnaBridge | 189:f392fc9709a3 | 815 | |
| AnnaBridge | 189:f392fc9709a3 | 816 | /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity |
| AnnaBridge | 189:f392fc9709a3 | 817 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 818 | */ |
| AnnaBridge | 189:f392fc9709a3 | 819 | #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ |
| AnnaBridge | 189:f392fc9709a3 | 820 | #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ |
| AnnaBridge | 189:f392fc9709a3 | 821 | #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ |
| AnnaBridge | 189:f392fc9709a3 | 822 | /** |
| AnnaBridge | 189:f392fc9709a3 | 823 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 824 | */ |
| AnnaBridge | 189:f392fc9709a3 | 825 | |
| AnnaBridge | 189:f392fc9709a3 | 826 | /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source |
| AnnaBridge | 189:f392fc9709a3 | 827 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 828 | */ |
| AnnaBridge | 189:f392fc9709a3 | 829 | #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ |
| AnnaBridge | 189:f392fc9709a3 | 830 | #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/ |
| AnnaBridge | 189:f392fc9709a3 | 831 | #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ |
| AnnaBridge | 189:f392fc9709a3 | 832 | /** |
| AnnaBridge | 189:f392fc9709a3 | 833 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 834 | */ |
| AnnaBridge | 189:f392fc9709a3 | 835 | |
| AnnaBridge | 189:f392fc9709a3 | 836 | /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode |
| AnnaBridge | 189:f392fc9709a3 | 837 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 838 | */ |
| AnnaBridge | 189:f392fc9709a3 | 839 | #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ |
| AnnaBridge | 189:f392fc9709a3 | 840 | #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ |
| AnnaBridge | 189:f392fc9709a3 | 841 | #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */ |
| AnnaBridge | 189:f392fc9709a3 | 842 | /** |
| AnnaBridge | 189:f392fc9709a3 | 843 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 844 | */ |
| AnnaBridge | 189:f392fc9709a3 | 845 | |
| AnnaBridge | 189:f392fc9709a3 | 846 | /** @defgroup TIM_LL_EC_TRGO Trigger Output |
| AnnaBridge | 189:f392fc9709a3 | 847 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 848 | */ |
| AnnaBridge | 189:f392fc9709a3 | 849 | #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */ |
| AnnaBridge | 189:f392fc9709a3 | 850 | #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ |
| AnnaBridge | 189:f392fc9709a3 | 851 | #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ |
| AnnaBridge | 189:f392fc9709a3 | 852 | #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ |
| AnnaBridge | 189:f392fc9709a3 | 853 | #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ |
| AnnaBridge | 189:f392fc9709a3 | 854 | #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ |
| AnnaBridge | 189:f392fc9709a3 | 855 | #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ |
| AnnaBridge | 189:f392fc9709a3 | 856 | #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ |
| AnnaBridge | 189:f392fc9709a3 | 857 | /** |
| AnnaBridge | 189:f392fc9709a3 | 858 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 859 | */ |
| AnnaBridge | 189:f392fc9709a3 | 860 | |
| AnnaBridge | 189:f392fc9709a3 | 861 | /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2 |
| AnnaBridge | 189:f392fc9709a3 | 862 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 863 | */ |
| AnnaBridge | 189:f392fc9709a3 | 864 | #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 865 | #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 866 | #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 867 | #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 868 | #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 869 | #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 870 | #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 871 | #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 872 | #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 873 | #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 874 | #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 875 | #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 876 | #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 877 | #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 878 | #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 879 | #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 880 | /** |
| AnnaBridge | 189:f392fc9709a3 | 881 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 882 | */ |
| AnnaBridge | 189:f392fc9709a3 | 883 | |
| AnnaBridge | 189:f392fc9709a3 | 884 | /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode |
| AnnaBridge | 189:f392fc9709a3 | 885 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 886 | */ |
| AnnaBridge | 189:f392fc9709a3 | 887 | #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 888 | #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ |
| AnnaBridge | 189:f392fc9709a3 | 889 | #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ |
| AnnaBridge | 189:f392fc9709a3 | 890 | #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ |
| AnnaBridge | 189:f392fc9709a3 | 891 | #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */ |
| AnnaBridge | 189:f392fc9709a3 | 892 | /** |
| AnnaBridge | 189:f392fc9709a3 | 893 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 894 | */ |
| AnnaBridge | 189:f392fc9709a3 | 895 | |
| AnnaBridge | 189:f392fc9709a3 | 896 | /** @defgroup TIM_LL_EC_TS Trigger Selection |
| AnnaBridge | 189:f392fc9709a3 | 897 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 898 | */ |
| AnnaBridge | 189:f392fc9709a3 | 899 | #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ |
| AnnaBridge | 189:f392fc9709a3 | 900 | #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ |
| AnnaBridge | 189:f392fc9709a3 | 901 | #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ |
| AnnaBridge | 189:f392fc9709a3 | 902 | #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ |
| AnnaBridge | 189:f392fc9709a3 | 903 | #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ |
| AnnaBridge | 189:f392fc9709a3 | 904 | #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ |
| AnnaBridge | 189:f392fc9709a3 | 905 | #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ |
| AnnaBridge | 189:f392fc9709a3 | 906 | #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ |
| AnnaBridge | 189:f392fc9709a3 | 907 | /** |
| AnnaBridge | 189:f392fc9709a3 | 908 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 909 | */ |
| AnnaBridge | 189:f392fc9709a3 | 910 | |
| AnnaBridge | 189:f392fc9709a3 | 911 | /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity |
| AnnaBridge | 189:f392fc9709a3 | 912 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 913 | */ |
| AnnaBridge | 189:f392fc9709a3 | 914 | #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */ |
| AnnaBridge | 189:f392fc9709a3 | 915 | #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ |
| AnnaBridge | 189:f392fc9709a3 | 916 | /** |
| AnnaBridge | 189:f392fc9709a3 | 917 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 918 | */ |
| AnnaBridge | 189:f392fc9709a3 | 919 | |
| AnnaBridge | 189:f392fc9709a3 | 920 | /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler |
| AnnaBridge | 189:f392fc9709a3 | 921 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 922 | */ |
| AnnaBridge | 189:f392fc9709a3 | 923 | #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */ |
| AnnaBridge | 189:f392fc9709a3 | 924 | #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 925 | #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ |
| AnnaBridge | 189:f392fc9709a3 | 926 | #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ |
| AnnaBridge | 189:f392fc9709a3 | 927 | /** |
| AnnaBridge | 189:f392fc9709a3 | 928 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 929 | */ |
| AnnaBridge | 189:f392fc9709a3 | 930 | |
| AnnaBridge | 189:f392fc9709a3 | 931 | /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter |
| AnnaBridge | 189:f392fc9709a3 | 932 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 933 | */ |
| AnnaBridge | 189:f392fc9709a3 | 934 | #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
| AnnaBridge | 189:f392fc9709a3 | 935 | #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ |
| AnnaBridge | 189:f392fc9709a3 | 936 | #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ |
| AnnaBridge | 189:f392fc9709a3 | 937 | #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 938 | #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 939 | #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 940 | #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 941 | #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 942 | #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 943 | #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ |
| AnnaBridge | 189:f392fc9709a3 | 944 | #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 945 | #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 946 | #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ |
| AnnaBridge | 189:f392fc9709a3 | 947 | #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ |
| AnnaBridge | 189:f392fc9709a3 | 948 | #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 949 | #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 950 | /** |
| AnnaBridge | 189:f392fc9709a3 | 951 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 952 | */ |
| AnnaBridge | 189:f392fc9709a3 | 953 | |
| AnnaBridge | 189:f392fc9709a3 | 954 | /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source |
| AnnaBridge | 189:f392fc9709a3 | 955 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 956 | */ |
| AnnaBridge | 189:f392fc9709a3 | 957 | #define LL_TIM_ETRSOURCE_LEGACY 0x00000000U /*!< ETR legacy mode */ |
| AnnaBridge | 189:f392fc9709a3 | 958 | #define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0 /*!< COMP1 output connected to ETR input */ |
| AnnaBridge | 189:f392fc9709a3 | 959 | #define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /*!< COMP2 output connected to ETR input */ |
| AnnaBridge | 189:f392fc9709a3 | 960 | /** |
| AnnaBridge | 189:f392fc9709a3 | 961 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 962 | */ |
| AnnaBridge | 189:f392fc9709a3 | 963 | |
| AnnaBridge | 189:f392fc9709a3 | 964 | /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity |
| AnnaBridge | 189:f392fc9709a3 | 965 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 966 | */ |
| AnnaBridge | 189:f392fc9709a3 | 967 | #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ |
| AnnaBridge | 189:f392fc9709a3 | 968 | #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ |
| AnnaBridge | 189:f392fc9709a3 | 969 | /** |
| AnnaBridge | 189:f392fc9709a3 | 970 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 971 | */ |
| AnnaBridge | 189:f392fc9709a3 | 972 | |
| AnnaBridge | 189:f392fc9709a3 | 973 | /** @defgroup TIM_LL_EC_BREAK_FILTER break filter |
| AnnaBridge | 189:f392fc9709a3 | 974 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 975 | */ |
| AnnaBridge | 189:f392fc9709a3 | 976 | #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ |
| AnnaBridge | 189:f392fc9709a3 | 977 | #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */ |
| AnnaBridge | 189:f392fc9709a3 | 978 | #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */ |
| AnnaBridge | 189:f392fc9709a3 | 979 | #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 980 | #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 981 | #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 982 | #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 983 | #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 984 | #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 985 | #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 986 | #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */ |
| AnnaBridge | 189:f392fc9709a3 | 987 | #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 988 | #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 989 | #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */ |
| AnnaBridge | 189:f392fc9709a3 | 990 | #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 991 | #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 992 | /** |
| AnnaBridge | 189:f392fc9709a3 | 993 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 994 | */ |
| AnnaBridge | 189:f392fc9709a3 | 995 | |
| AnnaBridge | 189:f392fc9709a3 | 996 | /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY |
| AnnaBridge | 189:f392fc9709a3 | 997 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 998 | */ |
| AnnaBridge | 189:f392fc9709a3 | 999 | #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ |
| AnnaBridge | 189:f392fc9709a3 | 1000 | #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ |
| AnnaBridge | 189:f392fc9709a3 | 1001 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1002 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1003 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1004 | |
| AnnaBridge | 189:f392fc9709a3 | 1005 | /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER |
| AnnaBridge | 189:f392fc9709a3 | 1006 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1007 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1008 | #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ |
| AnnaBridge | 189:f392fc9709a3 | 1009 | #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */ |
| AnnaBridge | 189:f392fc9709a3 | 1010 | #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */ |
| AnnaBridge | 189:f392fc9709a3 | 1011 | #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 1012 | #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 1013 | #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 1014 | #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 1015 | #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 1016 | #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 1017 | #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 1018 | #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */ |
| AnnaBridge | 189:f392fc9709a3 | 1019 | #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 1020 | #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 1021 | #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */ |
| AnnaBridge | 189:f392fc9709a3 | 1022 | #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */ |
| AnnaBridge | 189:f392fc9709a3 | 1023 | #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */ |
| AnnaBridge | 189:f392fc9709a3 | 1024 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1025 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1026 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1027 | |
| AnnaBridge | 189:f392fc9709a3 | 1028 | /** @defgroup TIM_LL_EC_OSSI OSSI |
| AnnaBridge | 189:f392fc9709a3 | 1029 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1030 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1031 | #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 1032 | #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */ |
| AnnaBridge | 189:f392fc9709a3 | 1033 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1034 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1035 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1036 | |
| AnnaBridge | 189:f392fc9709a3 | 1037 | /** @defgroup TIM_LL_EC_OSSR OSSR |
| AnnaBridge | 189:f392fc9709a3 | 1038 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1039 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1040 | #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 1041 | #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */ |
| AnnaBridge | 189:f392fc9709a3 | 1042 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1043 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1044 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1045 | |
| AnnaBridge | 189:f392fc9709a3 | 1046 | /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT |
| AnnaBridge | 189:f392fc9709a3 | 1047 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1048 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1049 | #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */ |
| AnnaBridge | 189:f392fc9709a3 | 1050 | #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */ |
| AnnaBridge | 189:f392fc9709a3 | 1051 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1052 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1053 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1054 | |
| AnnaBridge | 189:f392fc9709a3 | 1055 | /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE |
| AnnaBridge | 189:f392fc9709a3 | 1056 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1057 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1058 | #define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /*!< BKIN input from AF controller */ |
| AnnaBridge | 189:f392fc9709a3 | 1059 | #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /*!< internal signal: COMP1 output */ |
| AnnaBridge | 189:f392fc9709a3 | 1060 | #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /*!< internal signal: COMP2 output */ |
| AnnaBridge | 189:f392fc9709a3 | 1061 | #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */ |
| AnnaBridge | 189:f392fc9709a3 | 1062 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1063 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1064 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1065 | |
| AnnaBridge | 189:f392fc9709a3 | 1066 | /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY |
| AnnaBridge | 189:f392fc9709a3 | 1067 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1068 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1069 | #define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /*!< BRK BKIN input is active low */ |
| AnnaBridge | 189:f392fc9709a3 | 1070 | #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */ |
| AnnaBridge | 189:f392fc9709a3 | 1071 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1072 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1073 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1074 | |
| AnnaBridge | 189:f392fc9709a3 | 1075 | /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address |
| AnnaBridge | 189:f392fc9709a3 | 1076 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1077 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1078 | #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1079 | #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1080 | #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1081 | #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1082 | #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1083 | #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1084 | #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1085 | #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1086 | #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1087 | #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1088 | #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1089 | #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1090 | #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1091 | #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1092 | #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1093 | #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1094 | #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1095 | #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1096 | #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1097 | #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1098 | #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1099 | #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR1 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1100 | #define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_OR2 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1101 | #define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_OR3 register is the DMA base address for DMA burst */ |
| AnnaBridge | 189:f392fc9709a3 | 1102 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1103 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1104 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1105 | |
| AnnaBridge | 189:f392fc9709a3 | 1106 | /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length |
| AnnaBridge | 189:f392fc9709a3 | 1107 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1108 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1109 | #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1110 | #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1111 | #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1112 | #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1113 | #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1114 | #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1115 | #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1116 | #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1117 | #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1118 | #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1119 | #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1120 | #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1121 | #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1122 | #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1123 | #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1124 | #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1125 | #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1126 | #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ |
| AnnaBridge | 189:f392fc9709a3 | 1127 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1128 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1129 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1130 | |
| AnnaBridge | 189:f392fc9709a3 | 1131 | /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap |
| AnnaBridge | 189:f392fc9709a3 | 1132 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1133 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1134 | #define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */ |
| AnnaBridge | 189:f392fc9709a3 | 1135 | #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 1136 | #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 1137 | #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 1138 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1139 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1140 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1141 | |
| AnnaBridge | 189:f392fc9709a3 | 1142 | #if defined(ADC3) |
| AnnaBridge | 189:f392fc9709a3 | 1143 | /** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 External Trigger ADC3 Remap |
| AnnaBridge | 189:f392fc9709a3 | 1144 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1145 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1146 | #define LL_TIM_TIM1_ETR_ADC3_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC3 analog watchdog x*/ |
| AnnaBridge | 189:f392fc9709a3 | 1147 | #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 1148 | #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 1149 | #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 1150 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1151 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1152 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1153 | #endif /* ADC3 */ |
| AnnaBridge | 189:f392fc9709a3 | 1154 | |
| AnnaBridge | 189:f392fc9709a3 | 1155 | /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap |
| AnnaBridge | 189:f392fc9709a3 | 1156 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1157 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1158 | #define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR1_RMP_MASK /*!< TIM1 input capture 1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 1159 | #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1 input capture 1 is connected to COMP1 output */ |
| AnnaBridge | 189:f392fc9709a3 | 1160 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1161 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1162 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1163 | |
| AnnaBridge | 189:f392fc9709a3 | 1164 | /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap |
| AnnaBridge | 189:f392fc9709a3 | 1165 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1166 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1167 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 1168 | #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR1_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */ |
| AnnaBridge | 189:f392fc9709a3 | 1169 | #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */ |
| AnnaBridge | 189:f392fc9709a3 | 1170 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 1171 | /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 1172 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 1173 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) |
| AnnaBridge | 189:f392fc9709a3 | 1174 | #define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */ |
| AnnaBridge | 189:f392fc9709a3 | 1175 | #define LL_TIM_TIM2_ITR1_RMP_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */ |
| AnnaBridge | 189:f392fc9709a3 | 1176 | #endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 1177 | /* STM32L451xx || STM32L452xx || STM32L462xx */ |
| AnnaBridge | 189:f392fc9709a3 | 1178 | #define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2_ETR is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 1179 | #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ETR is connected to LSE */ |
| AnnaBridge | 189:f392fc9709a3 | 1180 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1181 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1182 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1183 | |
| AnnaBridge | 189:f392fc9709a3 | 1184 | /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap |
| AnnaBridge | 189:f392fc9709a3 | 1185 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1186 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1187 | #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 1188 | #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 1189 | #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 1190 | #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 1191 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1192 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1193 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1194 | |
| AnnaBridge | 189:f392fc9709a3 | 1195 | #if defined(TIM3) |
| AnnaBridge | 189:f392fc9709a3 | 1196 | /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap |
| AnnaBridge | 189:f392fc9709a3 | 1197 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1198 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1199 | #define LL_TIM_TIM3_TI1_RMP_GPIO TIM3_OR1_RMP_MASK /*!< TIM3 input capture 1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 1200 | #define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP1_OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 1201 | #define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP2_OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 1202 | #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 1203 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1204 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1205 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1206 | #endif /* TIM3 */ |
| AnnaBridge | 189:f392fc9709a3 | 1207 | |
| AnnaBridge | 189:f392fc9709a3 | 1208 | #if defined(TIM8) |
| AnnaBridge | 189:f392fc9709a3 | 1209 | /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap |
| AnnaBridge | 189:f392fc9709a3 | 1210 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1211 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1212 | #define LL_TIM_TIM8_ETR_ADC2_RMP_NC TIM8_OR1_RMP_MASK /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */ |
| AnnaBridge | 189:f392fc9709a3 | 1213 | #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */ |
| AnnaBridge | 189:f392fc9709a3 | 1214 | #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 1215 | #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 1216 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1217 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1218 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1219 | |
| AnnaBridge | 189:f392fc9709a3 | 1220 | /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap |
| AnnaBridge | 189:f392fc9709a3 | 1221 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1222 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1223 | #define LL_TIM_TIM8_ETR_ADC3_RMP_NC TIM8_OR1_RMP_MASK /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */ |
| AnnaBridge | 189:f392fc9709a3 | 1224 | #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 1225 | #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 1226 | #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 1227 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1228 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1229 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1230 | |
| AnnaBridge | 189:f392fc9709a3 | 1231 | /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap |
| AnnaBridge | 189:f392fc9709a3 | 1232 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1233 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1234 | #define LL_TIM_TIM8_TI1_RMP_GPIO TIM8_OR1_RMP_MASK /*!< TIM8 input capture 1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 1235 | #define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8 input capture 1 is connected to COMP2 output */ |
| AnnaBridge | 189:f392fc9709a3 | 1236 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1237 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1238 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1239 | #endif /* TIM8 */ |
| AnnaBridge | 189:f392fc9709a3 | 1240 | |
| AnnaBridge | 189:f392fc9709a3 | 1241 | /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap |
| AnnaBridge | 189:f392fc9709a3 | 1242 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1243 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1244 | #define LL_TIM_TIM15_TI1_RMP_GPIO TIM15_OR1_RMP_MASK /*!< TIM15 input capture 1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 1245 | #define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK) /*!< TIM15 input capture 1 is connected to LSE */ |
| AnnaBridge | 189:f392fc9709a3 | 1246 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1247 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1248 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1249 | |
| AnnaBridge | 189:f392fc9709a3 | 1250 | /** @defgroup TIM_LL_EC_TIM15_ENCODERMODE TIM15 ENCODERMODE |
| AnnaBridge | 189:f392fc9709a3 | 1251 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1252 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1253 | #define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION TIM15_OR1_RMP_MASK /*!< No redirection*/ |
| AnnaBridge | 189:f392fc9709a3 | 1254 | #define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ |
| AnnaBridge | 189:f392fc9709a3 | 1255 | #define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y*/ |
| AnnaBridge | 189:f392fc9709a3 | 1256 | #define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ |
| AnnaBridge | 189:f392fc9709a3 | 1257 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1258 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1259 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1260 | |
| AnnaBridge | 189:f392fc9709a3 | 1261 | /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap |
| AnnaBridge | 189:f392fc9709a3 | 1262 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1263 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1264 | #define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR1_RMP_MASK /*!< TIM16 input capture 1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 1265 | #define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSI */ |
| AnnaBridge | 189:f392fc9709a3 | 1266 | #define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSE */ |
| AnnaBridge | 189:f392fc9709a3 | 1267 | #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 1268 | #if defined TIM16_OR1_TI1_RMP_2 |
| AnnaBridge | 189:f392fc9709a3 | 1269 | #define LL_TIM_TIM16_TI1_RMP_MSI (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MSI */ |
| AnnaBridge | 189:f392fc9709a3 | 1270 | #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 */ |
| AnnaBridge | 189:f392fc9709a3 | 1271 | #define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */ |
| AnnaBridge | 189:f392fc9709a3 | 1272 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 1273 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1274 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1275 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1276 | |
| AnnaBridge | 189:f392fc9709a3 | 1277 | #if defined(TIM17) |
| AnnaBridge | 189:f392fc9709a3 | 1278 | /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap |
| AnnaBridge | 189:f392fc9709a3 | 1279 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1280 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1281 | #define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR1_RMP_MASK /*!< TIM17 input capture 1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 1282 | #define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MSI */ |
| AnnaBridge | 189:f392fc9709a3 | 1283 | #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to HSE/32 */ |
| AnnaBridge | 189:f392fc9709a3 | 1284 | #define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MCO */ |
| AnnaBridge | 189:f392fc9709a3 | 1285 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1286 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1287 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1288 | #endif /* TIM17 */ |
| AnnaBridge | 189:f392fc9709a3 | 1289 | |
| AnnaBridge | 189:f392fc9709a3 | 1290 | /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection |
| AnnaBridge | 189:f392fc9709a3 | 1291 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1292 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1293 | #define LL_TIM_OCREF_CLR_INT_NC 0x00000000U /*!< OCREF_CLR_INT is not connected */ |
| AnnaBridge | 189:f392fc9709a3 | 1294 | #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */ |
| AnnaBridge | 189:f392fc9709a3 | 1295 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1296 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1297 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1298 | |
| AnnaBridge | 189:f392fc9709a3 | 1299 | /** Legacy definitions for compatibility purpose |
| AnnaBridge | 189:f392fc9709a3 | 1300 | @cond 0 |
| AnnaBridge | 189:f392fc9709a3 | 1301 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1302 | #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK |
| AnnaBridge | 189:f392fc9709a3 | 1303 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1304 | @endcond |
| AnnaBridge | 189:f392fc9709a3 | 1305 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1306 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1307 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1308 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1309 | |
| AnnaBridge | 189:f392fc9709a3 | 1310 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 1311 | /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 1312 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1313 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1314 | |
| AnnaBridge | 189:f392fc9709a3 | 1315 | /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros |
| AnnaBridge | 189:f392fc9709a3 | 1316 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1317 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1318 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1319 | * @brief Write a value in TIM register. |
| AnnaBridge | 189:f392fc9709a3 | 1320 | * @param __INSTANCE__ TIM Instance |
| AnnaBridge | 189:f392fc9709a3 | 1321 | * @param __REG__ Register to be written |
| AnnaBridge | 189:f392fc9709a3 | 1322 | * @param __VALUE__ Value to be written in the register |
| AnnaBridge | 189:f392fc9709a3 | 1323 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1324 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1325 | #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
| AnnaBridge | 189:f392fc9709a3 | 1326 | |
| AnnaBridge | 189:f392fc9709a3 | 1327 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1328 | * @brief Read a value in TIM register. |
| AnnaBridge | 189:f392fc9709a3 | 1329 | * @param __INSTANCE__ TIM Instance |
| AnnaBridge | 189:f392fc9709a3 | 1330 | * @param __REG__ Register to be read |
| AnnaBridge | 189:f392fc9709a3 | 1331 | * @retval Register value |
| AnnaBridge | 189:f392fc9709a3 | 1332 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1333 | #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
| AnnaBridge | 189:f392fc9709a3 | 1334 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1335 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1336 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1337 | |
| AnnaBridge | 189:f392fc9709a3 | 1338 | /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros |
| AnnaBridge | 189:f392fc9709a3 | 1339 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1340 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1341 | |
| AnnaBridge | 189:f392fc9709a3 | 1342 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1343 | * @brief HELPER macro retrieving the UIFCPY flag from the counter value. |
| AnnaBridge | 189:f392fc9709a3 | 1344 | * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); |
| AnnaBridge | 189:f392fc9709a3 | 1345 | * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied |
| AnnaBridge | 189:f392fc9709a3 | 1346 | * to TIMx_CNT register bit 31) |
| AnnaBridge | 189:f392fc9709a3 | 1347 | * @param __CNT__ Counter value |
| AnnaBridge | 189:f392fc9709a3 | 1348 | * @retval UIF status bit |
| AnnaBridge | 189:f392fc9709a3 | 1349 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1350 | #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ |
| AnnaBridge | 189:f392fc9709a3 | 1351 | (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) |
| AnnaBridge | 189:f392fc9709a3 | 1352 | |
| AnnaBridge | 189:f392fc9709a3 | 1353 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1354 | * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. |
| AnnaBridge | 189:f392fc9709a3 | 1355 | * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); |
| AnnaBridge | 189:f392fc9709a3 | 1356 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
| AnnaBridge | 189:f392fc9709a3 | 1357 | * @param __CKD__ This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1358 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 1359 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 1360 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 1361 | * @param __DT__ deadtime duration (in ns) |
| AnnaBridge | 189:f392fc9709a3 | 1362 | * @retval DTG[0:7] |
| AnnaBridge | 189:f392fc9709a3 | 1363 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1364 | #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ |
| AnnaBridge | 189:f392fc9709a3 | 1365 | ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ |
| AnnaBridge | 189:f392fc9709a3 | 1366 | (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ |
| AnnaBridge | 189:f392fc9709a3 | 1367 | (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ |
| AnnaBridge | 189:f392fc9709a3 | 1368 | (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ |
| AnnaBridge | 189:f392fc9709a3 | 1369 | 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1370 | |
| AnnaBridge | 189:f392fc9709a3 | 1371 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1372 | * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. |
| AnnaBridge | 189:f392fc9709a3 | 1373 | * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); |
| AnnaBridge | 189:f392fc9709a3 | 1374 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
| AnnaBridge | 189:f392fc9709a3 | 1375 | * @param __CNTCLK__ counter clock frequency (in Hz) |
| AnnaBridge | 189:f392fc9709a3 | 1376 | * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 1377 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1378 | #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ |
| AnnaBridge | 189:f392fc9709a3 | 1379 | ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U |
| AnnaBridge | 189:f392fc9709a3 | 1380 | |
| AnnaBridge | 189:f392fc9709a3 | 1381 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1382 | * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. |
| AnnaBridge | 189:f392fc9709a3 | 1383 | * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); |
| AnnaBridge | 189:f392fc9709a3 | 1384 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
| AnnaBridge | 189:f392fc9709a3 | 1385 | * @param __PSC__ prescaler |
| AnnaBridge | 189:f392fc9709a3 | 1386 | * @param __FREQ__ output signal frequency (in Hz) |
| AnnaBridge | 189:f392fc9709a3 | 1387 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 1388 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1389 | #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ |
| AnnaBridge | 189:f392fc9709a3 | 1390 | (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U |
| AnnaBridge | 189:f392fc9709a3 | 1391 | |
| AnnaBridge | 189:f392fc9709a3 | 1392 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1393 | * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. |
| AnnaBridge | 189:f392fc9709a3 | 1394 | * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); |
| AnnaBridge | 189:f392fc9709a3 | 1395 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
| AnnaBridge | 189:f392fc9709a3 | 1396 | * @param __PSC__ prescaler |
| AnnaBridge | 189:f392fc9709a3 | 1397 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
| AnnaBridge | 189:f392fc9709a3 | 1398 | * @retval Compare value (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 1399 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1400 | #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ |
| AnnaBridge | 189:f392fc9709a3 | 1401 | ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ |
| AnnaBridge | 189:f392fc9709a3 | 1402 | / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) |
| AnnaBridge | 189:f392fc9709a3 | 1403 | |
| AnnaBridge | 189:f392fc9709a3 | 1404 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1405 | * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). |
| AnnaBridge | 189:f392fc9709a3 | 1406 | * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); |
| AnnaBridge | 189:f392fc9709a3 | 1407 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
| AnnaBridge | 189:f392fc9709a3 | 1408 | * @param __PSC__ prescaler |
| AnnaBridge | 189:f392fc9709a3 | 1409 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
| AnnaBridge | 189:f392fc9709a3 | 1410 | * @param __PULSE__ pulse duration (in us) |
| AnnaBridge | 189:f392fc9709a3 | 1411 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 1412 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1413 | #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ |
| AnnaBridge | 189:f392fc9709a3 | 1414 | ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ |
| AnnaBridge | 189:f392fc9709a3 | 1415 | + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) |
| AnnaBridge | 189:f392fc9709a3 | 1416 | |
| AnnaBridge | 189:f392fc9709a3 | 1417 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1418 | * @brief HELPER macro retrieving the ratio of the input capture prescaler |
| AnnaBridge | 189:f392fc9709a3 | 1419 | * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); |
| AnnaBridge | 189:f392fc9709a3 | 1420 | * @param __ICPSC__ This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1421 | * @arg @ref LL_TIM_ICPSC_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 1422 | * @arg @ref LL_TIM_ICPSC_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 1423 | * @arg @ref LL_TIM_ICPSC_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 1424 | * @arg @ref LL_TIM_ICPSC_DIV8 |
| AnnaBridge | 189:f392fc9709a3 | 1425 | * @retval Input capture prescaler ratio (1, 2, 4 or 8) |
| AnnaBridge | 189:f392fc9709a3 | 1426 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1427 | #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ |
| AnnaBridge | 189:f392fc9709a3 | 1428 | ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) |
| AnnaBridge | 189:f392fc9709a3 | 1429 | |
| AnnaBridge | 189:f392fc9709a3 | 1430 | |
| AnnaBridge | 189:f392fc9709a3 | 1431 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1432 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1433 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1434 | |
| AnnaBridge | 189:f392fc9709a3 | 1435 | |
| AnnaBridge | 189:f392fc9709a3 | 1436 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1437 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1438 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1439 | |
| AnnaBridge | 189:f392fc9709a3 | 1440 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 1441 | /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 1442 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1443 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1444 | |
| AnnaBridge | 189:f392fc9709a3 | 1445 | /** @defgroup TIM_LL_EF_Time_Base Time Base configuration |
| AnnaBridge | 189:f392fc9709a3 | 1446 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1447 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1448 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1449 | * @brief Enable timer counter. |
| AnnaBridge | 189:f392fc9709a3 | 1450 | * @rmtoll CR1 CEN LL_TIM_EnableCounter |
| AnnaBridge | 189:f392fc9709a3 | 1451 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1452 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1453 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1454 | __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1455 | { |
| AnnaBridge | 189:f392fc9709a3 | 1456 | SET_BIT(TIMx->CR1, TIM_CR1_CEN); |
| AnnaBridge | 189:f392fc9709a3 | 1457 | } |
| AnnaBridge | 189:f392fc9709a3 | 1458 | |
| AnnaBridge | 189:f392fc9709a3 | 1459 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1460 | * @brief Disable timer counter. |
| AnnaBridge | 189:f392fc9709a3 | 1461 | * @rmtoll CR1 CEN LL_TIM_DisableCounter |
| AnnaBridge | 189:f392fc9709a3 | 1462 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1463 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1464 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1465 | __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1466 | { |
| AnnaBridge | 189:f392fc9709a3 | 1467 | CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); |
| AnnaBridge | 189:f392fc9709a3 | 1468 | } |
| AnnaBridge | 189:f392fc9709a3 | 1469 | |
| AnnaBridge | 189:f392fc9709a3 | 1470 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1471 | * @brief Indicates whether the timer counter is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 1472 | * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter |
| AnnaBridge | 189:f392fc9709a3 | 1473 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1474 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1475 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1476 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1477 | { |
| AnnaBridge | 189:f392fc9709a3 | 1478 | return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)); |
| AnnaBridge | 189:f392fc9709a3 | 1479 | } |
| AnnaBridge | 189:f392fc9709a3 | 1480 | |
| AnnaBridge | 189:f392fc9709a3 | 1481 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1482 | * @brief Enable update event generation. |
| AnnaBridge | 189:f392fc9709a3 | 1483 | * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent |
| AnnaBridge | 189:f392fc9709a3 | 1484 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1485 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1486 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1487 | __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1488 | { |
| AnnaBridge | 189:f392fc9709a3 | 1489 | CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); |
| AnnaBridge | 189:f392fc9709a3 | 1490 | } |
| AnnaBridge | 189:f392fc9709a3 | 1491 | |
| AnnaBridge | 189:f392fc9709a3 | 1492 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1493 | * @brief Disable update event generation. |
| AnnaBridge | 189:f392fc9709a3 | 1494 | * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent |
| AnnaBridge | 189:f392fc9709a3 | 1495 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1496 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1497 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1498 | __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1499 | { |
| AnnaBridge | 189:f392fc9709a3 | 1500 | SET_BIT(TIMx->CR1, TIM_CR1_UDIS); |
| AnnaBridge | 189:f392fc9709a3 | 1501 | } |
| AnnaBridge | 189:f392fc9709a3 | 1502 | |
| AnnaBridge | 189:f392fc9709a3 | 1503 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1504 | * @brief Indicates whether update event generation is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 1505 | * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent |
| AnnaBridge | 189:f392fc9709a3 | 1506 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1507 | * @retval Inverted state of bit (0 or 1). |
| AnnaBridge | 189:f392fc9709a3 | 1508 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1509 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1510 | { |
| AnnaBridge | 189:f392fc9709a3 | 1511 | return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET); |
| AnnaBridge | 189:f392fc9709a3 | 1512 | } |
| AnnaBridge | 189:f392fc9709a3 | 1513 | |
| AnnaBridge | 189:f392fc9709a3 | 1514 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1515 | * @brief Set update event source |
| AnnaBridge | 189:f392fc9709a3 | 1516 | * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events |
| AnnaBridge | 189:f392fc9709a3 | 1517 | * generate an update interrupt or DMA request if enabled: |
| AnnaBridge | 189:f392fc9709a3 | 1518 | * - Counter overflow/underflow |
| AnnaBridge | 189:f392fc9709a3 | 1519 | * - Setting the UG bit |
| AnnaBridge | 189:f392fc9709a3 | 1520 | * - Update generation through the slave mode controller |
| AnnaBridge | 189:f392fc9709a3 | 1521 | * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter |
| AnnaBridge | 189:f392fc9709a3 | 1522 | * overflow/underflow generates an update interrupt or DMA request if enabled. |
| AnnaBridge | 189:f392fc9709a3 | 1523 | * @rmtoll CR1 URS LL_TIM_SetUpdateSource |
| AnnaBridge | 189:f392fc9709a3 | 1524 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1525 | * @param UpdateSource This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1526 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
| AnnaBridge | 189:f392fc9709a3 | 1527 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
| AnnaBridge | 189:f392fc9709a3 | 1528 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1529 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1530 | __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) |
| AnnaBridge | 189:f392fc9709a3 | 1531 | { |
| AnnaBridge | 189:f392fc9709a3 | 1532 | MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); |
| AnnaBridge | 189:f392fc9709a3 | 1533 | } |
| AnnaBridge | 189:f392fc9709a3 | 1534 | |
| AnnaBridge | 189:f392fc9709a3 | 1535 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1536 | * @brief Get actual event update source |
| AnnaBridge | 189:f392fc9709a3 | 1537 | * @rmtoll CR1 URS LL_TIM_GetUpdateSource |
| AnnaBridge | 189:f392fc9709a3 | 1538 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1539 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1540 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
| AnnaBridge | 189:f392fc9709a3 | 1541 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
| AnnaBridge | 189:f392fc9709a3 | 1542 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1543 | __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1544 | { |
| AnnaBridge | 189:f392fc9709a3 | 1545 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); |
| AnnaBridge | 189:f392fc9709a3 | 1546 | } |
| AnnaBridge | 189:f392fc9709a3 | 1547 | |
| AnnaBridge | 189:f392fc9709a3 | 1548 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1549 | * @brief Set one pulse mode (one shot v.s. repetitive). |
| AnnaBridge | 189:f392fc9709a3 | 1550 | * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode |
| AnnaBridge | 189:f392fc9709a3 | 1551 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1552 | * @param OnePulseMode This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1553 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
| AnnaBridge | 189:f392fc9709a3 | 1554 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
| AnnaBridge | 189:f392fc9709a3 | 1555 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1556 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1557 | __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) |
| AnnaBridge | 189:f392fc9709a3 | 1558 | { |
| AnnaBridge | 189:f392fc9709a3 | 1559 | MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); |
| AnnaBridge | 189:f392fc9709a3 | 1560 | } |
| AnnaBridge | 189:f392fc9709a3 | 1561 | |
| AnnaBridge | 189:f392fc9709a3 | 1562 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1563 | * @brief Get actual one pulse mode. |
| AnnaBridge | 189:f392fc9709a3 | 1564 | * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode |
| AnnaBridge | 189:f392fc9709a3 | 1565 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1566 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1567 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
| AnnaBridge | 189:f392fc9709a3 | 1568 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
| AnnaBridge | 189:f392fc9709a3 | 1569 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1570 | __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1571 | { |
| AnnaBridge | 189:f392fc9709a3 | 1572 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); |
| AnnaBridge | 189:f392fc9709a3 | 1573 | } |
| AnnaBridge | 189:f392fc9709a3 | 1574 | |
| AnnaBridge | 189:f392fc9709a3 | 1575 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1576 | * @brief Set the timer counter counting mode. |
| AnnaBridge | 189:f392fc9709a3 | 1577 | * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
| AnnaBridge | 189:f392fc9709a3 | 1578 | * check whether or not the counter mode selection feature is supported |
| AnnaBridge | 189:f392fc9709a3 | 1579 | * by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 1580 | * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) |
| AnnaBridge | 189:f392fc9709a3 | 1581 | * requires a timer reset to avoid unexpected direction |
| AnnaBridge | 189:f392fc9709a3 | 1582 | * due to DIR bit readonly in center aligned mode. |
| AnnaBridge | 189:f392fc9709a3 | 1583 | * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n |
| AnnaBridge | 189:f392fc9709a3 | 1584 | * CR1 CMS LL_TIM_SetCounterMode |
| AnnaBridge | 189:f392fc9709a3 | 1585 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1586 | * @param CounterMode This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1587 | * @arg @ref LL_TIM_COUNTERMODE_UP |
| AnnaBridge | 189:f392fc9709a3 | 1588 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
| AnnaBridge | 189:f392fc9709a3 | 1589 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
| AnnaBridge | 189:f392fc9709a3 | 1590 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
| AnnaBridge | 189:f392fc9709a3 | 1591 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
| AnnaBridge | 189:f392fc9709a3 | 1592 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1593 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1594 | __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) |
| AnnaBridge | 189:f392fc9709a3 | 1595 | { |
| AnnaBridge | 189:f392fc9709a3 | 1596 | MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode); |
| AnnaBridge | 189:f392fc9709a3 | 1597 | } |
| AnnaBridge | 189:f392fc9709a3 | 1598 | |
| AnnaBridge | 189:f392fc9709a3 | 1599 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1600 | * @brief Get actual counter mode. |
| AnnaBridge | 189:f392fc9709a3 | 1601 | * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
| AnnaBridge | 189:f392fc9709a3 | 1602 | * check whether or not the counter mode selection feature is supported |
| AnnaBridge | 189:f392fc9709a3 | 1603 | * by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 1604 | * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n |
| AnnaBridge | 189:f392fc9709a3 | 1605 | * CR1 CMS LL_TIM_GetCounterMode |
| AnnaBridge | 189:f392fc9709a3 | 1606 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1607 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1608 | * @arg @ref LL_TIM_COUNTERMODE_UP |
| AnnaBridge | 189:f392fc9709a3 | 1609 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
| AnnaBridge | 189:f392fc9709a3 | 1610 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
| AnnaBridge | 189:f392fc9709a3 | 1611 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
| AnnaBridge | 189:f392fc9709a3 | 1612 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
| AnnaBridge | 189:f392fc9709a3 | 1613 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1614 | __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1615 | { |
| AnnaBridge | 189:f392fc9709a3 | 1616 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); |
| AnnaBridge | 189:f392fc9709a3 | 1617 | } |
| AnnaBridge | 189:f392fc9709a3 | 1618 | |
| AnnaBridge | 189:f392fc9709a3 | 1619 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1620 | * @brief Enable auto-reload (ARR) preload. |
| AnnaBridge | 189:f392fc9709a3 | 1621 | * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload |
| AnnaBridge | 189:f392fc9709a3 | 1622 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1623 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1624 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1625 | __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1626 | { |
| AnnaBridge | 189:f392fc9709a3 | 1627 | SET_BIT(TIMx->CR1, TIM_CR1_ARPE); |
| AnnaBridge | 189:f392fc9709a3 | 1628 | } |
| AnnaBridge | 189:f392fc9709a3 | 1629 | |
| AnnaBridge | 189:f392fc9709a3 | 1630 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1631 | * @brief Disable auto-reload (ARR) preload. |
| AnnaBridge | 189:f392fc9709a3 | 1632 | * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload |
| AnnaBridge | 189:f392fc9709a3 | 1633 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1634 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1635 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1636 | __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1637 | { |
| AnnaBridge | 189:f392fc9709a3 | 1638 | CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); |
| AnnaBridge | 189:f392fc9709a3 | 1639 | } |
| AnnaBridge | 189:f392fc9709a3 | 1640 | |
| AnnaBridge | 189:f392fc9709a3 | 1641 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1642 | * @brief Indicates whether auto-reload (ARR) preload is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 1643 | * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload |
| AnnaBridge | 189:f392fc9709a3 | 1644 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1645 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1646 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1647 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1648 | { |
| AnnaBridge | 189:f392fc9709a3 | 1649 | return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)); |
| AnnaBridge | 189:f392fc9709a3 | 1650 | } |
| AnnaBridge | 189:f392fc9709a3 | 1651 | |
| AnnaBridge | 189:f392fc9709a3 | 1652 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1653 | * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. |
| AnnaBridge | 189:f392fc9709a3 | 1654 | * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 1655 | * whether or not the clock division feature is supported by the timer |
| AnnaBridge | 189:f392fc9709a3 | 1656 | * instance. |
| AnnaBridge | 189:f392fc9709a3 | 1657 | * @rmtoll CR1 CKD LL_TIM_SetClockDivision |
| AnnaBridge | 189:f392fc9709a3 | 1658 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1659 | * @param ClockDivision This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1660 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 1661 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 1662 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 1663 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1664 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1665 | __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) |
| AnnaBridge | 189:f392fc9709a3 | 1666 | { |
| AnnaBridge | 189:f392fc9709a3 | 1667 | MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); |
| AnnaBridge | 189:f392fc9709a3 | 1668 | } |
| AnnaBridge | 189:f392fc9709a3 | 1669 | |
| AnnaBridge | 189:f392fc9709a3 | 1670 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1671 | * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. |
| AnnaBridge | 189:f392fc9709a3 | 1672 | * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 1673 | * whether or not the clock division feature is supported by the timer |
| AnnaBridge | 189:f392fc9709a3 | 1674 | * instance. |
| AnnaBridge | 189:f392fc9709a3 | 1675 | * @rmtoll CR1 CKD LL_TIM_GetClockDivision |
| AnnaBridge | 189:f392fc9709a3 | 1676 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1677 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1678 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 1679 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 1680 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 1681 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1682 | __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1683 | { |
| AnnaBridge | 189:f392fc9709a3 | 1684 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); |
| AnnaBridge | 189:f392fc9709a3 | 1685 | } |
| AnnaBridge | 189:f392fc9709a3 | 1686 | |
| AnnaBridge | 189:f392fc9709a3 | 1687 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1688 | * @brief Set the counter value. |
| AnnaBridge | 189:f392fc9709a3 | 1689 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 1690 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 1691 | * @rmtoll CNT CNT LL_TIM_SetCounter |
| AnnaBridge | 189:f392fc9709a3 | 1692 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1693 | * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) |
| AnnaBridge | 189:f392fc9709a3 | 1694 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1695 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1696 | __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) |
| AnnaBridge | 189:f392fc9709a3 | 1697 | { |
| AnnaBridge | 189:f392fc9709a3 | 1698 | WRITE_REG(TIMx->CNT, Counter); |
| AnnaBridge | 189:f392fc9709a3 | 1699 | } |
| AnnaBridge | 189:f392fc9709a3 | 1700 | |
| AnnaBridge | 189:f392fc9709a3 | 1701 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1702 | * @brief Get the counter value. |
| AnnaBridge | 189:f392fc9709a3 | 1703 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 1704 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 1705 | * @rmtoll CNT CNT LL_TIM_GetCounter |
| AnnaBridge | 189:f392fc9709a3 | 1706 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1707 | * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) |
| AnnaBridge | 189:f392fc9709a3 | 1708 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1709 | __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1710 | { |
| AnnaBridge | 189:f392fc9709a3 | 1711 | return (uint32_t)(READ_REG(TIMx->CNT)); |
| AnnaBridge | 189:f392fc9709a3 | 1712 | } |
| AnnaBridge | 189:f392fc9709a3 | 1713 | |
| AnnaBridge | 189:f392fc9709a3 | 1714 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1715 | * @brief Get the current direction of the counter |
| AnnaBridge | 189:f392fc9709a3 | 1716 | * @rmtoll CR1 DIR LL_TIM_GetDirection |
| AnnaBridge | 189:f392fc9709a3 | 1717 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1718 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1719 | * @arg @ref LL_TIM_COUNTERDIRECTION_UP |
| AnnaBridge | 189:f392fc9709a3 | 1720 | * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN |
| AnnaBridge | 189:f392fc9709a3 | 1721 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1722 | __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1723 | { |
| AnnaBridge | 189:f392fc9709a3 | 1724 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); |
| AnnaBridge | 189:f392fc9709a3 | 1725 | } |
| AnnaBridge | 189:f392fc9709a3 | 1726 | |
| AnnaBridge | 189:f392fc9709a3 | 1727 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1728 | * @brief Set the prescaler value. |
| AnnaBridge | 189:f392fc9709a3 | 1729 | * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). |
| AnnaBridge | 189:f392fc9709a3 | 1730 | * @note The prescaler can be changed on the fly as this control register is buffered. The new |
| AnnaBridge | 189:f392fc9709a3 | 1731 | * prescaler ratio is taken into account at the next update event. |
| AnnaBridge | 189:f392fc9709a3 | 1732 | * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter |
| AnnaBridge | 189:f392fc9709a3 | 1733 | * @rmtoll PSC PSC LL_TIM_SetPrescaler |
| AnnaBridge | 189:f392fc9709a3 | 1734 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1735 | * @param Prescaler between Min_Data=0 and Max_Data=65535 |
| AnnaBridge | 189:f392fc9709a3 | 1736 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1737 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1738 | __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) |
| AnnaBridge | 189:f392fc9709a3 | 1739 | { |
| AnnaBridge | 189:f392fc9709a3 | 1740 | WRITE_REG(TIMx->PSC, Prescaler); |
| AnnaBridge | 189:f392fc9709a3 | 1741 | } |
| AnnaBridge | 189:f392fc9709a3 | 1742 | |
| AnnaBridge | 189:f392fc9709a3 | 1743 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1744 | * @brief Get the prescaler value. |
| AnnaBridge | 189:f392fc9709a3 | 1745 | * @rmtoll PSC PSC LL_TIM_GetPrescaler |
| AnnaBridge | 189:f392fc9709a3 | 1746 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1747 | * @retval Prescaler value between Min_Data=0 and Max_Data=65535 |
| AnnaBridge | 189:f392fc9709a3 | 1748 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1749 | __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1750 | { |
| AnnaBridge | 189:f392fc9709a3 | 1751 | return (uint32_t)(READ_REG(TIMx->PSC)); |
| AnnaBridge | 189:f392fc9709a3 | 1752 | } |
| AnnaBridge | 189:f392fc9709a3 | 1753 | |
| AnnaBridge | 189:f392fc9709a3 | 1754 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1755 | * @brief Set the auto-reload value. |
| AnnaBridge | 189:f392fc9709a3 | 1756 | * @note The counter is blocked while the auto-reload value is null. |
| AnnaBridge | 189:f392fc9709a3 | 1757 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 1758 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 1759 | * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter |
| AnnaBridge | 189:f392fc9709a3 | 1760 | * @rmtoll ARR ARR LL_TIM_SetAutoReload |
| AnnaBridge | 189:f392fc9709a3 | 1761 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1762 | * @param AutoReload between Min_Data=0 and Max_Data=65535 |
| AnnaBridge | 189:f392fc9709a3 | 1763 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1764 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1765 | __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) |
| AnnaBridge | 189:f392fc9709a3 | 1766 | { |
| AnnaBridge | 189:f392fc9709a3 | 1767 | WRITE_REG(TIMx->ARR, AutoReload); |
| AnnaBridge | 189:f392fc9709a3 | 1768 | } |
| AnnaBridge | 189:f392fc9709a3 | 1769 | |
| AnnaBridge | 189:f392fc9709a3 | 1770 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1771 | * @brief Get the auto-reload value. |
| AnnaBridge | 189:f392fc9709a3 | 1772 | * @rmtoll ARR ARR LL_TIM_GetAutoReload |
| AnnaBridge | 189:f392fc9709a3 | 1773 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 1774 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 1775 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1776 | * @retval Auto-reload value |
| AnnaBridge | 189:f392fc9709a3 | 1777 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1778 | __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1779 | { |
| AnnaBridge | 189:f392fc9709a3 | 1780 | return (uint32_t)(READ_REG(TIMx->ARR)); |
| AnnaBridge | 189:f392fc9709a3 | 1781 | } |
| AnnaBridge | 189:f392fc9709a3 | 1782 | |
| AnnaBridge | 189:f392fc9709a3 | 1783 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1784 | * @brief Set the repetition counter value. |
| AnnaBridge | 189:f392fc9709a3 | 1785 | * @note For advanced timer instances RepetitionCounter can be up to 65535. |
| AnnaBridge | 189:f392fc9709a3 | 1786 | * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 1787 | * whether or not a timer instance supports a repetition counter. |
| AnnaBridge | 189:f392fc9709a3 | 1788 | * @rmtoll RCR REP LL_TIM_SetRepetitionCounter |
| AnnaBridge | 189:f392fc9709a3 | 1789 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1790 | * @param RepetitionCounter between Min_Data=0 and Max_Data=255 |
| AnnaBridge | 189:f392fc9709a3 | 1791 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1792 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1793 | __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) |
| AnnaBridge | 189:f392fc9709a3 | 1794 | { |
| AnnaBridge | 189:f392fc9709a3 | 1795 | WRITE_REG(TIMx->RCR, RepetitionCounter); |
| AnnaBridge | 189:f392fc9709a3 | 1796 | } |
| AnnaBridge | 189:f392fc9709a3 | 1797 | |
| AnnaBridge | 189:f392fc9709a3 | 1798 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1799 | * @brief Get the repetition counter value. |
| AnnaBridge | 189:f392fc9709a3 | 1800 | * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 1801 | * whether or not a timer instance supports a repetition counter. |
| AnnaBridge | 189:f392fc9709a3 | 1802 | * @rmtoll RCR REP LL_TIM_GetRepetitionCounter |
| AnnaBridge | 189:f392fc9709a3 | 1803 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1804 | * @retval Repetition counter value |
| AnnaBridge | 189:f392fc9709a3 | 1805 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1806 | __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1807 | { |
| AnnaBridge | 189:f392fc9709a3 | 1808 | return (uint32_t)(READ_REG(TIMx->RCR)); |
| AnnaBridge | 189:f392fc9709a3 | 1809 | } |
| AnnaBridge | 189:f392fc9709a3 | 1810 | |
| AnnaBridge | 189:f392fc9709a3 | 1811 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1812 | * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). |
| AnnaBridge | 189:f392fc9709a3 | 1813 | * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. |
| AnnaBridge | 189:f392fc9709a3 | 1814 | * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap |
| AnnaBridge | 189:f392fc9709a3 | 1815 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1816 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1817 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1818 | __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1819 | { |
| AnnaBridge | 189:f392fc9709a3 | 1820 | SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); |
| AnnaBridge | 189:f392fc9709a3 | 1821 | } |
| AnnaBridge | 189:f392fc9709a3 | 1822 | |
| AnnaBridge | 189:f392fc9709a3 | 1823 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1824 | * @brief Disable update interrupt flag (UIF) remapping. |
| AnnaBridge | 189:f392fc9709a3 | 1825 | * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap |
| AnnaBridge | 189:f392fc9709a3 | 1826 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1827 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1828 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1829 | __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1830 | { |
| AnnaBridge | 189:f392fc9709a3 | 1831 | CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); |
| AnnaBridge | 189:f392fc9709a3 | 1832 | } |
| AnnaBridge | 189:f392fc9709a3 | 1833 | |
| AnnaBridge | 189:f392fc9709a3 | 1834 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1835 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1836 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1837 | |
| AnnaBridge | 189:f392fc9709a3 | 1838 | /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration |
| AnnaBridge | 189:f392fc9709a3 | 1839 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1840 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1841 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1842 | * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. |
| AnnaBridge | 189:f392fc9709a3 | 1843 | * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, |
| AnnaBridge | 189:f392fc9709a3 | 1844 | * they are updated only when a commutation event (COM) occurs. |
| AnnaBridge | 189:f392fc9709a3 | 1845 | * @note Only on channels that have a complementary output. |
| AnnaBridge | 189:f392fc9709a3 | 1846 | * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 1847 | * whether or not a timer instance is able to generate a commutation event. |
| AnnaBridge | 189:f392fc9709a3 | 1848 | * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload |
| AnnaBridge | 189:f392fc9709a3 | 1849 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1850 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1851 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1852 | __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1853 | { |
| AnnaBridge | 189:f392fc9709a3 | 1854 | SET_BIT(TIMx->CR2, TIM_CR2_CCPC); |
| AnnaBridge | 189:f392fc9709a3 | 1855 | } |
| AnnaBridge | 189:f392fc9709a3 | 1856 | |
| AnnaBridge | 189:f392fc9709a3 | 1857 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1858 | * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. |
| AnnaBridge | 189:f392fc9709a3 | 1859 | * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 1860 | * whether or not a timer instance is able to generate a commutation event. |
| AnnaBridge | 189:f392fc9709a3 | 1861 | * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload |
| AnnaBridge | 189:f392fc9709a3 | 1862 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1863 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1864 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1865 | __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1866 | { |
| AnnaBridge | 189:f392fc9709a3 | 1867 | CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); |
| AnnaBridge | 189:f392fc9709a3 | 1868 | } |
| AnnaBridge | 189:f392fc9709a3 | 1869 | |
| AnnaBridge | 189:f392fc9709a3 | 1870 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1871 | * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). |
| AnnaBridge | 189:f392fc9709a3 | 1872 | * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 1873 | * whether or not a timer instance is able to generate a commutation event. |
| AnnaBridge | 189:f392fc9709a3 | 1874 | * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate |
| AnnaBridge | 189:f392fc9709a3 | 1875 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1876 | * @param CCUpdateSource This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1877 | * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY |
| AnnaBridge | 189:f392fc9709a3 | 1878 | * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI |
| AnnaBridge | 189:f392fc9709a3 | 1879 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1880 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1881 | __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) |
| AnnaBridge | 189:f392fc9709a3 | 1882 | { |
| AnnaBridge | 189:f392fc9709a3 | 1883 | MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); |
| AnnaBridge | 189:f392fc9709a3 | 1884 | } |
| AnnaBridge | 189:f392fc9709a3 | 1885 | |
| AnnaBridge | 189:f392fc9709a3 | 1886 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1887 | * @brief Set the trigger of the capture/compare DMA request. |
| AnnaBridge | 189:f392fc9709a3 | 1888 | * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger |
| AnnaBridge | 189:f392fc9709a3 | 1889 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1890 | * @param DMAReqTrigger This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1891 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
| AnnaBridge | 189:f392fc9709a3 | 1892 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
| AnnaBridge | 189:f392fc9709a3 | 1893 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1894 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1895 | __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) |
| AnnaBridge | 189:f392fc9709a3 | 1896 | { |
| AnnaBridge | 189:f392fc9709a3 | 1897 | MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); |
| AnnaBridge | 189:f392fc9709a3 | 1898 | } |
| AnnaBridge | 189:f392fc9709a3 | 1899 | |
| AnnaBridge | 189:f392fc9709a3 | 1900 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1901 | * @brief Get actual trigger of the capture/compare DMA request. |
| AnnaBridge | 189:f392fc9709a3 | 1902 | * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger |
| AnnaBridge | 189:f392fc9709a3 | 1903 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1904 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1905 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
| AnnaBridge | 189:f392fc9709a3 | 1906 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
| AnnaBridge | 189:f392fc9709a3 | 1907 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1908 | __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 1909 | { |
| AnnaBridge | 189:f392fc9709a3 | 1910 | return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); |
| AnnaBridge | 189:f392fc9709a3 | 1911 | } |
| AnnaBridge | 189:f392fc9709a3 | 1912 | |
| AnnaBridge | 189:f392fc9709a3 | 1913 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1914 | * @brief Set the lock level to freeze the |
| AnnaBridge | 189:f392fc9709a3 | 1915 | * configuration of several capture/compare parameters. |
| AnnaBridge | 189:f392fc9709a3 | 1916 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 1917 | * the lock mechanism is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 1918 | * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel |
| AnnaBridge | 189:f392fc9709a3 | 1919 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1920 | * @param LockLevel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1921 | * @arg @ref LL_TIM_LOCKLEVEL_OFF |
| AnnaBridge | 189:f392fc9709a3 | 1922 | * @arg @ref LL_TIM_LOCKLEVEL_1 |
| AnnaBridge | 189:f392fc9709a3 | 1923 | * @arg @ref LL_TIM_LOCKLEVEL_2 |
| AnnaBridge | 189:f392fc9709a3 | 1924 | * @arg @ref LL_TIM_LOCKLEVEL_3 |
| AnnaBridge | 189:f392fc9709a3 | 1925 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1926 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1927 | __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) |
| AnnaBridge | 189:f392fc9709a3 | 1928 | { |
| AnnaBridge | 189:f392fc9709a3 | 1929 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); |
| AnnaBridge | 189:f392fc9709a3 | 1930 | } |
| AnnaBridge | 189:f392fc9709a3 | 1931 | |
| AnnaBridge | 189:f392fc9709a3 | 1932 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1933 | * @brief Enable capture/compare channels. |
| AnnaBridge | 189:f392fc9709a3 | 1934 | * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1935 | * CCER CC1NE LL_TIM_CC_EnableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1936 | * CCER CC2E LL_TIM_CC_EnableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1937 | * CCER CC2NE LL_TIM_CC_EnableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1938 | * CCER CC3E LL_TIM_CC_EnableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1939 | * CCER CC3NE LL_TIM_CC_EnableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1940 | * CCER CC4E LL_TIM_CC_EnableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1941 | * CCER CC5E LL_TIM_CC_EnableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1942 | * CCER CC6E LL_TIM_CC_EnableChannel |
| AnnaBridge | 189:f392fc9709a3 | 1943 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1944 | * @param Channels This parameter can be a combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1945 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 1946 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| AnnaBridge | 189:f392fc9709a3 | 1947 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 1948 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| AnnaBridge | 189:f392fc9709a3 | 1949 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 1950 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| AnnaBridge | 189:f392fc9709a3 | 1951 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 1952 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 1953 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 1954 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1955 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1956 | __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
| AnnaBridge | 189:f392fc9709a3 | 1957 | { |
| AnnaBridge | 189:f392fc9709a3 | 1958 | SET_BIT(TIMx->CCER, Channels); |
| AnnaBridge | 189:f392fc9709a3 | 1959 | } |
| AnnaBridge | 189:f392fc9709a3 | 1960 | |
| AnnaBridge | 189:f392fc9709a3 | 1961 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1962 | * @brief Disable capture/compare channels. |
| AnnaBridge | 189:f392fc9709a3 | 1963 | * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1964 | * CCER CC1NE LL_TIM_CC_DisableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1965 | * CCER CC2E LL_TIM_CC_DisableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1966 | * CCER CC2NE LL_TIM_CC_DisableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1967 | * CCER CC3E LL_TIM_CC_DisableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1968 | * CCER CC3NE LL_TIM_CC_DisableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1969 | * CCER CC4E LL_TIM_CC_DisableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1970 | * CCER CC5E LL_TIM_CC_DisableChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1971 | * CCER CC6E LL_TIM_CC_DisableChannel |
| AnnaBridge | 189:f392fc9709a3 | 1972 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 1973 | * @param Channels This parameter can be a combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1974 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 1975 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| AnnaBridge | 189:f392fc9709a3 | 1976 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 1977 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| AnnaBridge | 189:f392fc9709a3 | 1978 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 1979 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| AnnaBridge | 189:f392fc9709a3 | 1980 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 1981 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 1982 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 1983 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1984 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1985 | __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
| AnnaBridge | 189:f392fc9709a3 | 1986 | { |
| AnnaBridge | 189:f392fc9709a3 | 1987 | CLEAR_BIT(TIMx->CCER, Channels); |
| AnnaBridge | 189:f392fc9709a3 | 1988 | } |
| AnnaBridge | 189:f392fc9709a3 | 1989 | |
| AnnaBridge | 189:f392fc9709a3 | 1990 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1991 | * @brief Indicate whether channel(s) is(are) enabled. |
| AnnaBridge | 189:f392fc9709a3 | 1992 | * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1993 | * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1994 | * CCER CC2E LL_TIM_CC_IsEnabledChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1995 | * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1996 | * CCER CC3E LL_TIM_CC_IsEnabledChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1997 | * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1998 | * CCER CC4E LL_TIM_CC_IsEnabledChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 1999 | * CCER CC5E LL_TIM_CC_IsEnabledChannel\n |
| AnnaBridge | 189:f392fc9709a3 | 2000 | * CCER CC6E LL_TIM_CC_IsEnabledChannel |
| AnnaBridge | 189:f392fc9709a3 | 2001 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2002 | * @param Channels This parameter can be a combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2003 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2004 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| AnnaBridge | 189:f392fc9709a3 | 2005 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2006 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| AnnaBridge | 189:f392fc9709a3 | 2007 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2008 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| AnnaBridge | 189:f392fc9709a3 | 2009 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2010 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2011 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2012 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 2013 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2014 | __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
| AnnaBridge | 189:f392fc9709a3 | 2015 | { |
| AnnaBridge | 189:f392fc9709a3 | 2016 | return (READ_BIT(TIMx->CCER, Channels) == (Channels)); |
| AnnaBridge | 189:f392fc9709a3 | 2017 | } |
| AnnaBridge | 189:f392fc9709a3 | 2018 | |
| AnnaBridge | 189:f392fc9709a3 | 2019 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2020 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 2021 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2022 | |
| AnnaBridge | 189:f392fc9709a3 | 2023 | /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration |
| AnnaBridge | 189:f392fc9709a3 | 2024 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 2025 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2026 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2027 | * @brief Configure an output channel. |
| AnnaBridge | 189:f392fc9709a3 | 2028 | * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2029 | * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2030 | * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2031 | * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2032 | * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2033 | * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2034 | * CCER CC1P LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2035 | * CCER CC2P LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2036 | * CCER CC3P LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2037 | * CCER CC4P LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2038 | * CCER CC5P LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2039 | * CCER CC6P LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2040 | * CR2 OIS1 LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2041 | * CR2 OIS2 LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2042 | * CR2 OIS3 LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2043 | * CR2 OIS4 LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2044 | * CR2 OIS5 LL_TIM_OC_ConfigOutput\n |
| AnnaBridge | 189:f392fc9709a3 | 2045 | * CR2 OIS6 LL_TIM_OC_ConfigOutput |
| AnnaBridge | 189:f392fc9709a3 | 2046 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2047 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2048 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2049 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2050 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2051 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2052 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2053 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2054 | * @param Configuration This parameter must be a combination of all the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2055 | * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW |
| AnnaBridge | 189:f392fc9709a3 | 2056 | * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH |
| AnnaBridge | 189:f392fc9709a3 | 2057 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2058 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2059 | __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
| AnnaBridge | 189:f392fc9709a3 | 2060 | { |
| AnnaBridge | 189:f392fc9709a3 | 2061 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2062 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2063 | CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2064 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), |
| AnnaBridge | 189:f392fc9709a3 | 2065 | (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2066 | MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), |
| AnnaBridge | 189:f392fc9709a3 | 2067 | (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2068 | } |
| AnnaBridge | 189:f392fc9709a3 | 2069 | |
| AnnaBridge | 189:f392fc9709a3 | 2070 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2071 | * @brief Define the behavior of the output reference signal OCxREF from which |
| AnnaBridge | 189:f392fc9709a3 | 2072 | * OCx and OCxN (when relevant) are derived. |
| AnnaBridge | 189:f392fc9709a3 | 2073 | * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n |
| AnnaBridge | 189:f392fc9709a3 | 2074 | * CCMR1 OC2M LL_TIM_OC_SetMode\n |
| AnnaBridge | 189:f392fc9709a3 | 2075 | * CCMR2 OC3M LL_TIM_OC_SetMode\n |
| AnnaBridge | 189:f392fc9709a3 | 2076 | * CCMR2 OC4M LL_TIM_OC_SetMode\n |
| AnnaBridge | 189:f392fc9709a3 | 2077 | * CCMR3 OC5M LL_TIM_OC_SetMode\n |
| AnnaBridge | 189:f392fc9709a3 | 2078 | * CCMR3 OC6M LL_TIM_OC_SetMode |
| AnnaBridge | 189:f392fc9709a3 | 2079 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2080 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2081 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2082 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2083 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2084 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2085 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2086 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2087 | * @param Mode This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2088 | * @arg @ref LL_TIM_OCMODE_FROZEN |
| AnnaBridge | 189:f392fc9709a3 | 2089 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
| AnnaBridge | 189:f392fc9709a3 | 2090 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
| AnnaBridge | 189:f392fc9709a3 | 2091 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
| AnnaBridge | 189:f392fc9709a3 | 2092 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
| AnnaBridge | 189:f392fc9709a3 | 2093 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
| AnnaBridge | 189:f392fc9709a3 | 2094 | * @arg @ref LL_TIM_OCMODE_PWM1 |
| AnnaBridge | 189:f392fc9709a3 | 2095 | * @arg @ref LL_TIM_OCMODE_PWM2 |
| AnnaBridge | 189:f392fc9709a3 | 2096 | * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 |
| AnnaBridge | 189:f392fc9709a3 | 2097 | * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 |
| AnnaBridge | 189:f392fc9709a3 | 2098 | * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 |
| AnnaBridge | 189:f392fc9709a3 | 2099 | * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 |
| AnnaBridge | 189:f392fc9709a3 | 2100 | * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 |
| AnnaBridge | 189:f392fc9709a3 | 2101 | * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 |
| AnnaBridge | 189:f392fc9709a3 | 2102 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2103 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2104 | __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) |
| AnnaBridge | 189:f392fc9709a3 | 2105 | { |
| AnnaBridge | 189:f392fc9709a3 | 2106 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2107 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2108 | MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2109 | } |
| AnnaBridge | 189:f392fc9709a3 | 2110 | |
| AnnaBridge | 189:f392fc9709a3 | 2111 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2112 | * @brief Get the output compare mode of an output channel. |
| AnnaBridge | 189:f392fc9709a3 | 2113 | * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n |
| AnnaBridge | 189:f392fc9709a3 | 2114 | * CCMR1 OC2M LL_TIM_OC_GetMode\n |
| AnnaBridge | 189:f392fc9709a3 | 2115 | * CCMR2 OC3M LL_TIM_OC_GetMode\n |
| AnnaBridge | 189:f392fc9709a3 | 2116 | * CCMR2 OC4M LL_TIM_OC_GetMode\n |
| AnnaBridge | 189:f392fc9709a3 | 2117 | * CCMR3 OC5M LL_TIM_OC_GetMode\n |
| AnnaBridge | 189:f392fc9709a3 | 2118 | * CCMR3 OC6M LL_TIM_OC_GetMode |
| AnnaBridge | 189:f392fc9709a3 | 2119 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2120 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2121 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2122 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2123 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2124 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2125 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2126 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2127 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2128 | * @arg @ref LL_TIM_OCMODE_FROZEN |
| AnnaBridge | 189:f392fc9709a3 | 2129 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
| AnnaBridge | 189:f392fc9709a3 | 2130 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
| AnnaBridge | 189:f392fc9709a3 | 2131 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
| AnnaBridge | 189:f392fc9709a3 | 2132 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
| AnnaBridge | 189:f392fc9709a3 | 2133 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
| AnnaBridge | 189:f392fc9709a3 | 2134 | * @arg @ref LL_TIM_OCMODE_PWM1 |
| AnnaBridge | 189:f392fc9709a3 | 2135 | * @arg @ref LL_TIM_OCMODE_PWM2 |
| AnnaBridge | 189:f392fc9709a3 | 2136 | * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 |
| AnnaBridge | 189:f392fc9709a3 | 2137 | * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 |
| AnnaBridge | 189:f392fc9709a3 | 2138 | * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 |
| AnnaBridge | 189:f392fc9709a3 | 2139 | * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 |
| AnnaBridge | 189:f392fc9709a3 | 2140 | * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 |
| AnnaBridge | 189:f392fc9709a3 | 2141 | * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 |
| AnnaBridge | 189:f392fc9709a3 | 2142 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2143 | __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2144 | { |
| AnnaBridge | 189:f392fc9709a3 | 2145 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2146 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2147 | return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2148 | } |
| AnnaBridge | 189:f392fc9709a3 | 2149 | |
| AnnaBridge | 189:f392fc9709a3 | 2150 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2151 | * @brief Set the polarity of an output channel. |
| AnnaBridge | 189:f392fc9709a3 | 2152 | * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2153 | * CCER CC1NP LL_TIM_OC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2154 | * CCER CC2P LL_TIM_OC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2155 | * CCER CC2NP LL_TIM_OC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2156 | * CCER CC3P LL_TIM_OC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2157 | * CCER CC3NP LL_TIM_OC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2158 | * CCER CC4P LL_TIM_OC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2159 | * CCER CC5P LL_TIM_OC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2160 | * CCER CC6P LL_TIM_OC_SetPolarity |
| AnnaBridge | 189:f392fc9709a3 | 2161 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2162 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2163 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2164 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| AnnaBridge | 189:f392fc9709a3 | 2165 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2166 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| AnnaBridge | 189:f392fc9709a3 | 2167 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2168 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| AnnaBridge | 189:f392fc9709a3 | 2169 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2170 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2171 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2172 | * @param Polarity This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2173 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
| AnnaBridge | 189:f392fc9709a3 | 2174 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
| AnnaBridge | 189:f392fc9709a3 | 2175 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2176 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2177 | __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) |
| AnnaBridge | 189:f392fc9709a3 | 2178 | { |
| AnnaBridge | 189:f392fc9709a3 | 2179 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2180 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2181 | } |
| AnnaBridge | 189:f392fc9709a3 | 2182 | |
| AnnaBridge | 189:f392fc9709a3 | 2183 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2184 | * @brief Get the polarity of an output channel. |
| AnnaBridge | 189:f392fc9709a3 | 2185 | * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2186 | * CCER CC1NP LL_TIM_OC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2187 | * CCER CC2P LL_TIM_OC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2188 | * CCER CC2NP LL_TIM_OC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2189 | * CCER CC3P LL_TIM_OC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2190 | * CCER CC3NP LL_TIM_OC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2191 | * CCER CC4P LL_TIM_OC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2192 | * CCER CC5P LL_TIM_OC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2193 | * CCER CC6P LL_TIM_OC_GetPolarity |
| AnnaBridge | 189:f392fc9709a3 | 2194 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2195 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2196 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2197 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| AnnaBridge | 189:f392fc9709a3 | 2198 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2199 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| AnnaBridge | 189:f392fc9709a3 | 2200 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2201 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| AnnaBridge | 189:f392fc9709a3 | 2202 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2203 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2204 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2205 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2206 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
| AnnaBridge | 189:f392fc9709a3 | 2207 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
| AnnaBridge | 189:f392fc9709a3 | 2208 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2209 | __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2210 | { |
| AnnaBridge | 189:f392fc9709a3 | 2211 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2212 | return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2213 | } |
| AnnaBridge | 189:f392fc9709a3 | 2214 | |
| AnnaBridge | 189:f392fc9709a3 | 2215 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2216 | * @brief Set the IDLE state of an output channel |
| AnnaBridge | 189:f392fc9709a3 | 2217 | * @note This function is significant only for the timer instances |
| AnnaBridge | 189:f392fc9709a3 | 2218 | * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 2219 | * can be used to check whether or not a timer instance provides |
| AnnaBridge | 189:f392fc9709a3 | 2220 | * a break input. |
| AnnaBridge | 189:f392fc9709a3 | 2221 | * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2222 | * CR2 OIS2N LL_TIM_OC_SetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2223 | * CR2 OIS2 LL_TIM_OC_SetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2224 | * CR2 OIS2N LL_TIM_OC_SetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2225 | * CR2 OIS3 LL_TIM_OC_SetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2226 | * CR2 OIS3N LL_TIM_OC_SetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2227 | * CR2 OIS4 LL_TIM_OC_SetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2228 | * CR2 OIS5 LL_TIM_OC_SetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2229 | * CR2 OIS6 LL_TIM_OC_SetIdleState |
| AnnaBridge | 189:f392fc9709a3 | 2230 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2231 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2232 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2233 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| AnnaBridge | 189:f392fc9709a3 | 2234 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2235 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| AnnaBridge | 189:f392fc9709a3 | 2236 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2237 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| AnnaBridge | 189:f392fc9709a3 | 2238 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2239 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2240 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2241 | * @param IdleState This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2242 | * @arg @ref LL_TIM_OCIDLESTATE_LOW |
| AnnaBridge | 189:f392fc9709a3 | 2243 | * @arg @ref LL_TIM_OCIDLESTATE_HIGH |
| AnnaBridge | 189:f392fc9709a3 | 2244 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2245 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2246 | __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) |
| AnnaBridge | 189:f392fc9709a3 | 2247 | { |
| AnnaBridge | 189:f392fc9709a3 | 2248 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2249 | MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2250 | } |
| AnnaBridge | 189:f392fc9709a3 | 2251 | |
| AnnaBridge | 189:f392fc9709a3 | 2252 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2253 | * @brief Get the IDLE state of an output channel |
| AnnaBridge | 189:f392fc9709a3 | 2254 | * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2255 | * CR2 OIS2N LL_TIM_OC_GetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2256 | * CR2 OIS2 LL_TIM_OC_GetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2257 | * CR2 OIS2N LL_TIM_OC_GetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2258 | * CR2 OIS3 LL_TIM_OC_GetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2259 | * CR2 OIS3N LL_TIM_OC_GetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2260 | * CR2 OIS4 LL_TIM_OC_GetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2261 | * CR2 OIS5 LL_TIM_OC_GetIdleState\n |
| AnnaBridge | 189:f392fc9709a3 | 2262 | * CR2 OIS6 LL_TIM_OC_GetIdleState |
| AnnaBridge | 189:f392fc9709a3 | 2263 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2264 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2265 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2266 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| AnnaBridge | 189:f392fc9709a3 | 2267 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2268 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| AnnaBridge | 189:f392fc9709a3 | 2269 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2270 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| AnnaBridge | 189:f392fc9709a3 | 2271 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2272 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2273 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2274 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2275 | * @arg @ref LL_TIM_OCIDLESTATE_LOW |
| AnnaBridge | 189:f392fc9709a3 | 2276 | * @arg @ref LL_TIM_OCIDLESTATE_HIGH |
| AnnaBridge | 189:f392fc9709a3 | 2277 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2278 | __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2279 | { |
| AnnaBridge | 189:f392fc9709a3 | 2280 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2281 | return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2282 | } |
| AnnaBridge | 189:f392fc9709a3 | 2283 | |
| AnnaBridge | 189:f392fc9709a3 | 2284 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2285 | * @brief Enable fast mode for the output channel. |
| AnnaBridge | 189:f392fc9709a3 | 2286 | * @note Acts only if the channel is configured in PWM1 or PWM2 mode. |
| AnnaBridge | 189:f392fc9709a3 | 2287 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2288 | * CCMR1 OC2FE LL_TIM_OC_EnableFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2289 | * CCMR2 OC3FE LL_TIM_OC_EnableFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2290 | * CCMR2 OC4FE LL_TIM_OC_EnableFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2291 | * CCMR3 OC5FE LL_TIM_OC_EnableFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2292 | * CCMR3 OC6FE LL_TIM_OC_EnableFast |
| AnnaBridge | 189:f392fc9709a3 | 2293 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2294 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2295 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2296 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2297 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2298 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2299 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2300 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2301 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2302 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2303 | __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2304 | { |
| AnnaBridge | 189:f392fc9709a3 | 2305 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2306 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2307 | SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2308 | |
| AnnaBridge | 189:f392fc9709a3 | 2309 | } |
| AnnaBridge | 189:f392fc9709a3 | 2310 | |
| AnnaBridge | 189:f392fc9709a3 | 2311 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2312 | * @brief Disable fast mode for the output channel. |
| AnnaBridge | 189:f392fc9709a3 | 2313 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2314 | * CCMR1 OC2FE LL_TIM_OC_DisableFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2315 | * CCMR2 OC3FE LL_TIM_OC_DisableFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2316 | * CCMR2 OC4FE LL_TIM_OC_DisableFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2317 | * CCMR3 OC5FE LL_TIM_OC_DisableFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2318 | * CCMR3 OC6FE LL_TIM_OC_DisableFast |
| AnnaBridge | 189:f392fc9709a3 | 2319 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2320 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2321 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2322 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2323 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2324 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2325 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2326 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2327 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2328 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2329 | __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2330 | { |
| AnnaBridge | 189:f392fc9709a3 | 2331 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2332 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2333 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2334 | |
| AnnaBridge | 189:f392fc9709a3 | 2335 | } |
| AnnaBridge | 189:f392fc9709a3 | 2336 | |
| AnnaBridge | 189:f392fc9709a3 | 2337 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2338 | * @brief Indicates whether fast mode is enabled for the output channel. |
| AnnaBridge | 189:f392fc9709a3 | 2339 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2340 | * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2341 | * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2342 | * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2343 | * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n |
| AnnaBridge | 189:f392fc9709a3 | 2344 | * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast |
| AnnaBridge | 189:f392fc9709a3 | 2345 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2346 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2347 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2348 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2349 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2350 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2351 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2352 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2353 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 2354 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2355 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2356 | { |
| AnnaBridge | 189:f392fc9709a3 | 2357 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2358 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2359 | register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; |
| AnnaBridge | 189:f392fc9709a3 | 2360 | return (READ_BIT(*pReg, bitfield) == bitfield); |
| AnnaBridge | 189:f392fc9709a3 | 2361 | } |
| AnnaBridge | 189:f392fc9709a3 | 2362 | |
| AnnaBridge | 189:f392fc9709a3 | 2363 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2364 | * @brief Enable compare register (TIMx_CCRx) preload for the output channel. |
| AnnaBridge | 189:f392fc9709a3 | 2365 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2366 | * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2367 | * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2368 | * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2369 | * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2370 | * CCMR3 OC6PE LL_TIM_OC_EnablePreload |
| AnnaBridge | 189:f392fc9709a3 | 2371 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2372 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2373 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2374 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2375 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2376 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2377 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2378 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2379 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2380 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2381 | __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2382 | { |
| AnnaBridge | 189:f392fc9709a3 | 2383 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2384 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2385 | SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2386 | } |
| AnnaBridge | 189:f392fc9709a3 | 2387 | |
| AnnaBridge | 189:f392fc9709a3 | 2388 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2389 | * @brief Disable compare register (TIMx_CCRx) preload for the output channel. |
| AnnaBridge | 189:f392fc9709a3 | 2390 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2391 | * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2392 | * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2393 | * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2394 | * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2395 | * CCMR3 OC6PE LL_TIM_OC_DisablePreload |
| AnnaBridge | 189:f392fc9709a3 | 2396 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2397 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2398 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2399 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2400 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2401 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2402 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2403 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2404 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2405 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2406 | __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2407 | { |
| AnnaBridge | 189:f392fc9709a3 | 2408 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2409 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2410 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2411 | } |
| AnnaBridge | 189:f392fc9709a3 | 2412 | |
| AnnaBridge | 189:f392fc9709a3 | 2413 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2414 | * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. |
| AnnaBridge | 189:f392fc9709a3 | 2415 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2416 | * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2417 | * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2418 | * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2419 | * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n |
| AnnaBridge | 189:f392fc9709a3 | 2420 | * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload |
| AnnaBridge | 189:f392fc9709a3 | 2421 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2422 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2423 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2424 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2425 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2426 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2427 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2428 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2429 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 2430 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2431 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2432 | { |
| AnnaBridge | 189:f392fc9709a3 | 2433 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2434 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2435 | register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; |
| AnnaBridge | 189:f392fc9709a3 | 2436 | return (READ_BIT(*pReg, bitfield) == bitfield); |
| AnnaBridge | 189:f392fc9709a3 | 2437 | } |
| AnnaBridge | 189:f392fc9709a3 | 2438 | |
| AnnaBridge | 189:f392fc9709a3 | 2439 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2440 | * @brief Enable clearing the output channel on an external event. |
| AnnaBridge | 189:f392fc9709a3 | 2441 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
| AnnaBridge | 189:f392fc9709a3 | 2442 | * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
| AnnaBridge | 189:f392fc9709a3 | 2443 | * or not a timer instance can clear the OCxREF signal on an external event. |
| AnnaBridge | 189:f392fc9709a3 | 2444 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2445 | * CCMR1 OC2CE LL_TIM_OC_EnableClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2446 | * CCMR2 OC3CE LL_TIM_OC_EnableClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2447 | * CCMR2 OC4CE LL_TIM_OC_EnableClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2448 | * CCMR3 OC5CE LL_TIM_OC_EnableClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2449 | * CCMR3 OC6CE LL_TIM_OC_EnableClear |
| AnnaBridge | 189:f392fc9709a3 | 2450 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2451 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2452 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2453 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2454 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2455 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2456 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2457 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2458 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2459 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2460 | __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2461 | { |
| AnnaBridge | 189:f392fc9709a3 | 2462 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2463 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2464 | SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2465 | } |
| AnnaBridge | 189:f392fc9709a3 | 2466 | |
| AnnaBridge | 189:f392fc9709a3 | 2467 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2468 | * @brief Disable clearing the output channel on an external event. |
| AnnaBridge | 189:f392fc9709a3 | 2469 | * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
| AnnaBridge | 189:f392fc9709a3 | 2470 | * or not a timer instance can clear the OCxREF signal on an external event. |
| AnnaBridge | 189:f392fc9709a3 | 2471 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2472 | * CCMR1 OC2CE LL_TIM_OC_DisableClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2473 | * CCMR2 OC3CE LL_TIM_OC_DisableClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2474 | * CCMR2 OC4CE LL_TIM_OC_DisableClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2475 | * CCMR3 OC5CE LL_TIM_OC_DisableClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2476 | * CCMR3 OC6CE LL_TIM_OC_DisableClear |
| AnnaBridge | 189:f392fc9709a3 | 2477 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2478 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2479 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2480 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2481 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2482 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2483 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2484 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2485 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2486 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2487 | __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2488 | { |
| AnnaBridge | 189:f392fc9709a3 | 2489 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2490 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2491 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2492 | } |
| AnnaBridge | 189:f392fc9709a3 | 2493 | |
| AnnaBridge | 189:f392fc9709a3 | 2494 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2495 | * @brief Indicates clearing the output channel on an external event is enabled for the output channel. |
| AnnaBridge | 189:f392fc9709a3 | 2496 | * @note This function enables clearing the output channel on an external event. |
| AnnaBridge | 189:f392fc9709a3 | 2497 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
| AnnaBridge | 189:f392fc9709a3 | 2498 | * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
| AnnaBridge | 189:f392fc9709a3 | 2499 | * or not a timer instance can clear the OCxREF signal on an external event. |
| AnnaBridge | 189:f392fc9709a3 | 2500 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2501 | * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2502 | * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2503 | * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2504 | * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n |
| AnnaBridge | 189:f392fc9709a3 | 2505 | * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear |
| AnnaBridge | 189:f392fc9709a3 | 2506 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2507 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2508 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2509 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2510 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2511 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2512 | * @arg @ref LL_TIM_CHANNEL_CH5 |
| AnnaBridge | 189:f392fc9709a3 | 2513 | * @arg @ref LL_TIM_CHANNEL_CH6 |
| AnnaBridge | 189:f392fc9709a3 | 2514 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 2515 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2516 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2517 | { |
| AnnaBridge | 189:f392fc9709a3 | 2518 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2519 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2520 | register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; |
| AnnaBridge | 189:f392fc9709a3 | 2521 | return (READ_BIT(*pReg, bitfield) == bitfield); |
| AnnaBridge | 189:f392fc9709a3 | 2522 | } |
| AnnaBridge | 189:f392fc9709a3 | 2523 | |
| AnnaBridge | 189:f392fc9709a3 | 2524 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2525 | * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). |
| AnnaBridge | 189:f392fc9709a3 | 2526 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 2527 | * dead-time insertion feature is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 2528 | * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter |
| AnnaBridge | 189:f392fc9709a3 | 2529 | * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime |
| AnnaBridge | 189:f392fc9709a3 | 2530 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2531 | * @param DeadTime between Min_Data=0 and Max_Data=255 |
| AnnaBridge | 189:f392fc9709a3 | 2532 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2533 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2534 | __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) |
| AnnaBridge | 189:f392fc9709a3 | 2535 | { |
| AnnaBridge | 189:f392fc9709a3 | 2536 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); |
| AnnaBridge | 189:f392fc9709a3 | 2537 | } |
| AnnaBridge | 189:f392fc9709a3 | 2538 | |
| AnnaBridge | 189:f392fc9709a3 | 2539 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2540 | * @brief Set compare value for output channel 1 (TIMx_CCR1). |
| AnnaBridge | 189:f392fc9709a3 | 2541 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 2542 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 2543 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 2544 | * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 2545 | * output channel 1 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 2546 | * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 |
| AnnaBridge | 189:f392fc9709a3 | 2547 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2548 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| AnnaBridge | 189:f392fc9709a3 | 2549 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2550 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2551 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| AnnaBridge | 189:f392fc9709a3 | 2552 | { |
| AnnaBridge | 189:f392fc9709a3 | 2553 | WRITE_REG(TIMx->CCR1, CompareValue); |
| AnnaBridge | 189:f392fc9709a3 | 2554 | } |
| AnnaBridge | 189:f392fc9709a3 | 2555 | |
| AnnaBridge | 189:f392fc9709a3 | 2556 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2557 | * @brief Set compare value for output channel 2 (TIMx_CCR2). |
| AnnaBridge | 189:f392fc9709a3 | 2558 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 2559 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 2560 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 2561 | * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 2562 | * output channel 2 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 2563 | * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 |
| AnnaBridge | 189:f392fc9709a3 | 2564 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2565 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| AnnaBridge | 189:f392fc9709a3 | 2566 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2567 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2568 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| AnnaBridge | 189:f392fc9709a3 | 2569 | { |
| AnnaBridge | 189:f392fc9709a3 | 2570 | WRITE_REG(TIMx->CCR2, CompareValue); |
| AnnaBridge | 189:f392fc9709a3 | 2571 | } |
| AnnaBridge | 189:f392fc9709a3 | 2572 | |
| AnnaBridge | 189:f392fc9709a3 | 2573 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2574 | * @brief Set compare value for output channel 3 (TIMx_CCR3). |
| AnnaBridge | 189:f392fc9709a3 | 2575 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 2576 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 2577 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 2578 | * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 2579 | * output channel is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 2580 | * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 |
| AnnaBridge | 189:f392fc9709a3 | 2581 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2582 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| AnnaBridge | 189:f392fc9709a3 | 2583 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2584 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2585 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| AnnaBridge | 189:f392fc9709a3 | 2586 | { |
| AnnaBridge | 189:f392fc9709a3 | 2587 | WRITE_REG(TIMx->CCR3, CompareValue); |
| AnnaBridge | 189:f392fc9709a3 | 2588 | } |
| AnnaBridge | 189:f392fc9709a3 | 2589 | |
| AnnaBridge | 189:f392fc9709a3 | 2590 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2591 | * @brief Set compare value for output channel 4 (TIMx_CCR4). |
| AnnaBridge | 189:f392fc9709a3 | 2592 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 2593 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 2594 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 2595 | * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 2596 | * output channel 4 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 2597 | * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 |
| AnnaBridge | 189:f392fc9709a3 | 2598 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2599 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| AnnaBridge | 189:f392fc9709a3 | 2600 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2601 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2602 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| AnnaBridge | 189:f392fc9709a3 | 2603 | { |
| AnnaBridge | 189:f392fc9709a3 | 2604 | WRITE_REG(TIMx->CCR4, CompareValue); |
| AnnaBridge | 189:f392fc9709a3 | 2605 | } |
| AnnaBridge | 189:f392fc9709a3 | 2606 | |
| AnnaBridge | 189:f392fc9709a3 | 2607 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2608 | * @brief Set compare value for output channel 5 (TIMx_CCR5). |
| AnnaBridge | 189:f392fc9709a3 | 2609 | * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 2610 | * output channel 5 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 2611 | * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 |
| AnnaBridge | 189:f392fc9709a3 | 2612 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2613 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| AnnaBridge | 189:f392fc9709a3 | 2614 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2615 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2616 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| AnnaBridge | 189:f392fc9709a3 | 2617 | { |
| AnnaBridge | 189:f392fc9709a3 | 2618 | WRITE_REG(TIMx->CCR5, CompareValue); |
| AnnaBridge | 189:f392fc9709a3 | 2619 | } |
| AnnaBridge | 189:f392fc9709a3 | 2620 | |
| AnnaBridge | 189:f392fc9709a3 | 2621 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2622 | * @brief Set compare value for output channel 6 (TIMx_CCR6). |
| AnnaBridge | 189:f392fc9709a3 | 2623 | * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 2624 | * output channel 6 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 2625 | * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 |
| AnnaBridge | 189:f392fc9709a3 | 2626 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2627 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| AnnaBridge | 189:f392fc9709a3 | 2628 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2629 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2630 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| AnnaBridge | 189:f392fc9709a3 | 2631 | { |
| AnnaBridge | 189:f392fc9709a3 | 2632 | WRITE_REG(TIMx->CCR6, CompareValue); |
| AnnaBridge | 189:f392fc9709a3 | 2633 | } |
| AnnaBridge | 189:f392fc9709a3 | 2634 | |
| AnnaBridge | 189:f392fc9709a3 | 2635 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2636 | * @brief Get compare value (TIMx_CCR1) set for output channel 1. |
| AnnaBridge | 189:f392fc9709a3 | 2637 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 2638 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 2639 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 2640 | * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 2641 | * output channel 1 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 2642 | * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 |
| AnnaBridge | 189:f392fc9709a3 | 2643 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2644 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 2645 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2646 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 2647 | { |
| AnnaBridge | 189:f392fc9709a3 | 2648 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
| AnnaBridge | 189:f392fc9709a3 | 2649 | } |
| AnnaBridge | 189:f392fc9709a3 | 2650 | |
| AnnaBridge | 189:f392fc9709a3 | 2651 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2652 | * @brief Get compare value (TIMx_CCR2) set for output channel 2. |
| AnnaBridge | 189:f392fc9709a3 | 2653 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 2654 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 2655 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 2656 | * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 2657 | * output channel 2 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 2658 | * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 |
| AnnaBridge | 189:f392fc9709a3 | 2659 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2660 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 2661 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2662 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 2663 | { |
| AnnaBridge | 189:f392fc9709a3 | 2664 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
| AnnaBridge | 189:f392fc9709a3 | 2665 | } |
| AnnaBridge | 189:f392fc9709a3 | 2666 | |
| AnnaBridge | 189:f392fc9709a3 | 2667 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2668 | * @brief Get compare value (TIMx_CCR3) set for output channel 3. |
| AnnaBridge | 189:f392fc9709a3 | 2669 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 2670 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 2671 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 2672 | * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 2673 | * output channel 3 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 2674 | * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 |
| AnnaBridge | 189:f392fc9709a3 | 2675 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2676 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 2677 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2678 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 2679 | { |
| AnnaBridge | 189:f392fc9709a3 | 2680 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
| AnnaBridge | 189:f392fc9709a3 | 2681 | } |
| AnnaBridge | 189:f392fc9709a3 | 2682 | |
| AnnaBridge | 189:f392fc9709a3 | 2683 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2684 | * @brief Get compare value (TIMx_CCR4) set for output channel 4. |
| AnnaBridge | 189:f392fc9709a3 | 2685 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 2686 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 2687 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 2688 | * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 2689 | * output channel 4 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 2690 | * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 |
| AnnaBridge | 189:f392fc9709a3 | 2691 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2692 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 2693 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2694 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 2695 | { |
| AnnaBridge | 189:f392fc9709a3 | 2696 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
| AnnaBridge | 189:f392fc9709a3 | 2697 | } |
| AnnaBridge | 189:f392fc9709a3 | 2698 | |
| AnnaBridge | 189:f392fc9709a3 | 2699 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2700 | * @brief Get compare value (TIMx_CCR5) set for output channel 5. |
| AnnaBridge | 189:f392fc9709a3 | 2701 | * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 2702 | * output channel 5 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 2703 | * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 |
| AnnaBridge | 189:f392fc9709a3 | 2704 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2705 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 2706 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2707 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 2708 | { |
| AnnaBridge | 189:f392fc9709a3 | 2709 | return (uint32_t)(READ_REG(TIMx->CCR5)); |
| AnnaBridge | 189:f392fc9709a3 | 2710 | } |
| AnnaBridge | 189:f392fc9709a3 | 2711 | |
| AnnaBridge | 189:f392fc9709a3 | 2712 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2713 | * @brief Get compare value (TIMx_CCR6) set for output channel 6. |
| AnnaBridge | 189:f392fc9709a3 | 2714 | * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 2715 | * output channel 6 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 2716 | * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 |
| AnnaBridge | 189:f392fc9709a3 | 2717 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2718 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 2719 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2720 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 2721 | { |
| AnnaBridge | 189:f392fc9709a3 | 2722 | return (uint32_t)(READ_REG(TIMx->CCR6)); |
| AnnaBridge | 189:f392fc9709a3 | 2723 | } |
| AnnaBridge | 189:f392fc9709a3 | 2724 | |
| AnnaBridge | 189:f392fc9709a3 | 2725 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2726 | * @brief Select on which reference signal the OC5REF is combined to. |
| AnnaBridge | 189:f392fc9709a3 | 2727 | * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 2728 | * whether or not a timer instance supports the combined 3-phase PWM mode. |
| AnnaBridge | 189:f392fc9709a3 | 2729 | * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n |
| AnnaBridge | 189:f392fc9709a3 | 2730 | * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n |
| AnnaBridge | 189:f392fc9709a3 | 2731 | * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels |
| AnnaBridge | 189:f392fc9709a3 | 2732 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2733 | * @param GroupCH5 This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2734 | * @arg @ref LL_TIM_GROUPCH5_NONE |
| AnnaBridge | 189:f392fc9709a3 | 2735 | * @arg @ref LL_TIM_GROUPCH5_OC1REFC |
| AnnaBridge | 189:f392fc9709a3 | 2736 | * @arg @ref LL_TIM_GROUPCH5_OC2REFC |
| AnnaBridge | 189:f392fc9709a3 | 2737 | * @arg @ref LL_TIM_GROUPCH5_OC3REFC |
| AnnaBridge | 189:f392fc9709a3 | 2738 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2739 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2740 | __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) |
| AnnaBridge | 189:f392fc9709a3 | 2741 | { |
| AnnaBridge | 189:f392fc9709a3 | 2742 | MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5); |
| AnnaBridge | 189:f392fc9709a3 | 2743 | } |
| AnnaBridge | 189:f392fc9709a3 | 2744 | |
| AnnaBridge | 189:f392fc9709a3 | 2745 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2746 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 2747 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2748 | |
| AnnaBridge | 189:f392fc9709a3 | 2749 | /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration |
| AnnaBridge | 189:f392fc9709a3 | 2750 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 2751 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2752 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2753 | * @brief Configure input channel. |
| AnnaBridge | 189:f392fc9709a3 | 2754 | * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2755 | * CCMR1 IC1PSC LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2756 | * CCMR1 IC1F LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2757 | * CCMR1 CC2S LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2758 | * CCMR1 IC2PSC LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2759 | * CCMR1 IC2F LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2760 | * CCMR2 CC3S LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2761 | * CCMR2 IC3PSC LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2762 | * CCMR2 IC3F LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2763 | * CCMR2 CC4S LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2764 | * CCMR2 IC4PSC LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2765 | * CCMR2 IC4F LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2766 | * CCER CC1P LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2767 | * CCER CC1NP LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2768 | * CCER CC2P LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2769 | * CCER CC2NP LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2770 | * CCER CC3P LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2771 | * CCER CC3NP LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2772 | * CCER CC4P LL_TIM_IC_Config\n |
| AnnaBridge | 189:f392fc9709a3 | 2773 | * CCER CC4NP LL_TIM_IC_Config |
| AnnaBridge | 189:f392fc9709a3 | 2774 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2775 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2776 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2777 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2778 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2779 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2780 | * @param Configuration This parameter must be a combination of all the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2781 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC |
| AnnaBridge | 189:f392fc9709a3 | 2782 | * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 |
| AnnaBridge | 189:f392fc9709a3 | 2783 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 |
| AnnaBridge | 189:f392fc9709a3 | 2784 | * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE |
| AnnaBridge | 189:f392fc9709a3 | 2785 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2786 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2787 | __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
| AnnaBridge | 189:f392fc9709a3 | 2788 | { |
| AnnaBridge | 189:f392fc9709a3 | 2789 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2790 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2791 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), |
| AnnaBridge | 189:f392fc9709a3 | 2792 | ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2793 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
| AnnaBridge | 189:f392fc9709a3 | 2794 | (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2795 | } |
| AnnaBridge | 189:f392fc9709a3 | 2796 | |
| AnnaBridge | 189:f392fc9709a3 | 2797 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2798 | * @brief Set the active input. |
| AnnaBridge | 189:f392fc9709a3 | 2799 | * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n |
| AnnaBridge | 189:f392fc9709a3 | 2800 | * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n |
| AnnaBridge | 189:f392fc9709a3 | 2801 | * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n |
| AnnaBridge | 189:f392fc9709a3 | 2802 | * CCMR2 CC4S LL_TIM_IC_SetActiveInput |
| AnnaBridge | 189:f392fc9709a3 | 2803 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2804 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2805 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2806 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2807 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2808 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2809 | * @param ICActiveInput This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2810 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
| AnnaBridge | 189:f392fc9709a3 | 2811 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
| AnnaBridge | 189:f392fc9709a3 | 2812 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
| AnnaBridge | 189:f392fc9709a3 | 2813 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2814 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2815 | __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) |
| AnnaBridge | 189:f392fc9709a3 | 2816 | { |
| AnnaBridge | 189:f392fc9709a3 | 2817 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2818 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2819 | MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2820 | } |
| AnnaBridge | 189:f392fc9709a3 | 2821 | |
| AnnaBridge | 189:f392fc9709a3 | 2822 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2823 | * @brief Get the current active input. |
| AnnaBridge | 189:f392fc9709a3 | 2824 | * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n |
| AnnaBridge | 189:f392fc9709a3 | 2825 | * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n |
| AnnaBridge | 189:f392fc9709a3 | 2826 | * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n |
| AnnaBridge | 189:f392fc9709a3 | 2827 | * CCMR2 CC4S LL_TIM_IC_GetActiveInput |
| AnnaBridge | 189:f392fc9709a3 | 2828 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2829 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2830 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2831 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2832 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2833 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2834 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2835 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
| AnnaBridge | 189:f392fc9709a3 | 2836 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
| AnnaBridge | 189:f392fc9709a3 | 2837 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
| AnnaBridge | 189:f392fc9709a3 | 2838 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2839 | __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2840 | { |
| AnnaBridge | 189:f392fc9709a3 | 2841 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2842 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2843 | return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
| AnnaBridge | 189:f392fc9709a3 | 2844 | } |
| AnnaBridge | 189:f392fc9709a3 | 2845 | |
| AnnaBridge | 189:f392fc9709a3 | 2846 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2847 | * @brief Set the prescaler of input channel. |
| AnnaBridge | 189:f392fc9709a3 | 2848 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n |
| AnnaBridge | 189:f392fc9709a3 | 2849 | * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n |
| AnnaBridge | 189:f392fc9709a3 | 2850 | * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n |
| AnnaBridge | 189:f392fc9709a3 | 2851 | * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler |
| AnnaBridge | 189:f392fc9709a3 | 2852 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2853 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2854 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2855 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2856 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2857 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2858 | * @param ICPrescaler This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2859 | * @arg @ref LL_TIM_ICPSC_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 2860 | * @arg @ref LL_TIM_ICPSC_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 2861 | * @arg @ref LL_TIM_ICPSC_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 2862 | * @arg @ref LL_TIM_ICPSC_DIV8 |
| AnnaBridge | 189:f392fc9709a3 | 2863 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2864 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2865 | __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) |
| AnnaBridge | 189:f392fc9709a3 | 2866 | { |
| AnnaBridge | 189:f392fc9709a3 | 2867 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2868 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2869 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2870 | } |
| AnnaBridge | 189:f392fc9709a3 | 2871 | |
| AnnaBridge | 189:f392fc9709a3 | 2872 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2873 | * @brief Get the current prescaler value acting on an input channel. |
| AnnaBridge | 189:f392fc9709a3 | 2874 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n |
| AnnaBridge | 189:f392fc9709a3 | 2875 | * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n |
| AnnaBridge | 189:f392fc9709a3 | 2876 | * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n |
| AnnaBridge | 189:f392fc9709a3 | 2877 | * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler |
| AnnaBridge | 189:f392fc9709a3 | 2878 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2879 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2880 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2881 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2882 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2883 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2884 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2885 | * @arg @ref LL_TIM_ICPSC_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 2886 | * @arg @ref LL_TIM_ICPSC_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 2887 | * @arg @ref LL_TIM_ICPSC_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 2888 | * @arg @ref LL_TIM_ICPSC_DIV8 |
| AnnaBridge | 189:f392fc9709a3 | 2889 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2890 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2891 | { |
| AnnaBridge | 189:f392fc9709a3 | 2892 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2893 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2894 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
| AnnaBridge | 189:f392fc9709a3 | 2895 | } |
| AnnaBridge | 189:f392fc9709a3 | 2896 | |
| AnnaBridge | 189:f392fc9709a3 | 2897 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2898 | * @brief Set the input filter duration. |
| AnnaBridge | 189:f392fc9709a3 | 2899 | * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n |
| AnnaBridge | 189:f392fc9709a3 | 2900 | * CCMR1 IC2F LL_TIM_IC_SetFilter\n |
| AnnaBridge | 189:f392fc9709a3 | 2901 | * CCMR2 IC3F LL_TIM_IC_SetFilter\n |
| AnnaBridge | 189:f392fc9709a3 | 2902 | * CCMR2 IC4F LL_TIM_IC_SetFilter |
| AnnaBridge | 189:f392fc9709a3 | 2903 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2904 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2905 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2906 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2907 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2908 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2909 | * @param ICFilter This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2910 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
| AnnaBridge | 189:f392fc9709a3 | 2911 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
| AnnaBridge | 189:f392fc9709a3 | 2912 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
| AnnaBridge | 189:f392fc9709a3 | 2913 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
| AnnaBridge | 189:f392fc9709a3 | 2914 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
| AnnaBridge | 189:f392fc9709a3 | 2915 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
| AnnaBridge | 189:f392fc9709a3 | 2916 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
| AnnaBridge | 189:f392fc9709a3 | 2917 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
| AnnaBridge | 189:f392fc9709a3 | 2918 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
| AnnaBridge | 189:f392fc9709a3 | 2919 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
| AnnaBridge | 189:f392fc9709a3 | 2920 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
| AnnaBridge | 189:f392fc9709a3 | 2921 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
| AnnaBridge | 189:f392fc9709a3 | 2922 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
| AnnaBridge | 189:f392fc9709a3 | 2923 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
| AnnaBridge | 189:f392fc9709a3 | 2924 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
| AnnaBridge | 189:f392fc9709a3 | 2925 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
| AnnaBridge | 189:f392fc9709a3 | 2926 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2927 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2928 | __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) |
| AnnaBridge | 189:f392fc9709a3 | 2929 | { |
| AnnaBridge | 189:f392fc9709a3 | 2930 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2931 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2932 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2933 | } |
| AnnaBridge | 189:f392fc9709a3 | 2934 | |
| AnnaBridge | 189:f392fc9709a3 | 2935 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2936 | * @brief Get the input filter duration. |
| AnnaBridge | 189:f392fc9709a3 | 2937 | * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n |
| AnnaBridge | 189:f392fc9709a3 | 2938 | * CCMR1 IC2F LL_TIM_IC_GetFilter\n |
| AnnaBridge | 189:f392fc9709a3 | 2939 | * CCMR2 IC3F LL_TIM_IC_GetFilter\n |
| AnnaBridge | 189:f392fc9709a3 | 2940 | * CCMR2 IC4F LL_TIM_IC_GetFilter |
| AnnaBridge | 189:f392fc9709a3 | 2941 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2942 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2943 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2944 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2945 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2946 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2947 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2948 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
| AnnaBridge | 189:f392fc9709a3 | 2949 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
| AnnaBridge | 189:f392fc9709a3 | 2950 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
| AnnaBridge | 189:f392fc9709a3 | 2951 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
| AnnaBridge | 189:f392fc9709a3 | 2952 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
| AnnaBridge | 189:f392fc9709a3 | 2953 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
| AnnaBridge | 189:f392fc9709a3 | 2954 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
| AnnaBridge | 189:f392fc9709a3 | 2955 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
| AnnaBridge | 189:f392fc9709a3 | 2956 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
| AnnaBridge | 189:f392fc9709a3 | 2957 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
| AnnaBridge | 189:f392fc9709a3 | 2958 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
| AnnaBridge | 189:f392fc9709a3 | 2959 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
| AnnaBridge | 189:f392fc9709a3 | 2960 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
| AnnaBridge | 189:f392fc9709a3 | 2961 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
| AnnaBridge | 189:f392fc9709a3 | 2962 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
| AnnaBridge | 189:f392fc9709a3 | 2963 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
| AnnaBridge | 189:f392fc9709a3 | 2964 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2965 | __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 2966 | { |
| AnnaBridge | 189:f392fc9709a3 | 2967 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2968 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| AnnaBridge | 189:f392fc9709a3 | 2969 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
| AnnaBridge | 189:f392fc9709a3 | 2970 | } |
| AnnaBridge | 189:f392fc9709a3 | 2971 | |
| AnnaBridge | 189:f392fc9709a3 | 2972 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2973 | * @brief Set the input channel polarity. |
| AnnaBridge | 189:f392fc9709a3 | 2974 | * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2975 | * CCER CC1NP LL_TIM_IC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2976 | * CCER CC2P LL_TIM_IC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2977 | * CCER CC2NP LL_TIM_IC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2978 | * CCER CC3P LL_TIM_IC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2979 | * CCER CC3NP LL_TIM_IC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2980 | * CCER CC4P LL_TIM_IC_SetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 2981 | * CCER CC4NP LL_TIM_IC_SetPolarity |
| AnnaBridge | 189:f392fc9709a3 | 2982 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 2983 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2984 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 2985 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 2986 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 2987 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 2988 | * @param ICPolarity This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2989 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
| AnnaBridge | 189:f392fc9709a3 | 2990 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
| AnnaBridge | 189:f392fc9709a3 | 2991 | * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE |
| AnnaBridge | 189:f392fc9709a3 | 2992 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2993 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2994 | __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) |
| AnnaBridge | 189:f392fc9709a3 | 2995 | { |
| AnnaBridge | 189:f392fc9709a3 | 2996 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 2997 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
| AnnaBridge | 189:f392fc9709a3 | 2998 | ICPolarity << SHIFT_TAB_CCxP[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 2999 | } |
| AnnaBridge | 189:f392fc9709a3 | 3000 | |
| AnnaBridge | 189:f392fc9709a3 | 3001 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3002 | * @brief Get the current input channel polarity. |
| AnnaBridge | 189:f392fc9709a3 | 3003 | * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 3004 | * CCER CC1NP LL_TIM_IC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 3005 | * CCER CC2P LL_TIM_IC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 3006 | * CCER CC2NP LL_TIM_IC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 3007 | * CCER CC3P LL_TIM_IC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 3008 | * CCER CC3NP LL_TIM_IC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 3009 | * CCER CC4P LL_TIM_IC_GetPolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 3010 | * CCER CC4NP LL_TIM_IC_GetPolarity |
| AnnaBridge | 189:f392fc9709a3 | 3011 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3012 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3013 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| AnnaBridge | 189:f392fc9709a3 | 3014 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| AnnaBridge | 189:f392fc9709a3 | 3015 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| AnnaBridge | 189:f392fc9709a3 | 3016 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| AnnaBridge | 189:f392fc9709a3 | 3017 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3018 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
| AnnaBridge | 189:f392fc9709a3 | 3019 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
| AnnaBridge | 189:f392fc9709a3 | 3020 | * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE |
| AnnaBridge | 189:f392fc9709a3 | 3021 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3022 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) |
| AnnaBridge | 189:f392fc9709a3 | 3023 | { |
| AnnaBridge | 189:f392fc9709a3 | 3024 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| AnnaBridge | 189:f392fc9709a3 | 3025 | return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> |
| AnnaBridge | 189:f392fc9709a3 | 3026 | SHIFT_TAB_CCxP[iChannel]); |
| AnnaBridge | 189:f392fc9709a3 | 3027 | } |
| AnnaBridge | 189:f392fc9709a3 | 3028 | |
| AnnaBridge | 189:f392fc9709a3 | 3029 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3030 | * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). |
| AnnaBridge | 189:f392fc9709a3 | 3031 | * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3032 | * a timer instance provides an XOR input. |
| AnnaBridge | 189:f392fc9709a3 | 3033 | * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination |
| AnnaBridge | 189:f392fc9709a3 | 3034 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3035 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3036 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3037 | __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3038 | { |
| AnnaBridge | 189:f392fc9709a3 | 3039 | SET_BIT(TIMx->CR2, TIM_CR2_TI1S); |
| AnnaBridge | 189:f392fc9709a3 | 3040 | } |
| AnnaBridge | 189:f392fc9709a3 | 3041 | |
| AnnaBridge | 189:f392fc9709a3 | 3042 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3043 | * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. |
| AnnaBridge | 189:f392fc9709a3 | 3044 | * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3045 | * a timer instance provides an XOR input. |
| AnnaBridge | 189:f392fc9709a3 | 3046 | * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination |
| AnnaBridge | 189:f392fc9709a3 | 3047 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3048 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3049 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3050 | __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3051 | { |
| AnnaBridge | 189:f392fc9709a3 | 3052 | CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); |
| AnnaBridge | 189:f392fc9709a3 | 3053 | } |
| AnnaBridge | 189:f392fc9709a3 | 3054 | |
| AnnaBridge | 189:f392fc9709a3 | 3055 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3056 | * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. |
| AnnaBridge | 189:f392fc9709a3 | 3057 | * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3058 | * a timer instance provides an XOR input. |
| AnnaBridge | 189:f392fc9709a3 | 3059 | * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination |
| AnnaBridge | 189:f392fc9709a3 | 3060 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3061 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 3062 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3063 | __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3064 | { |
| AnnaBridge | 189:f392fc9709a3 | 3065 | return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)); |
| AnnaBridge | 189:f392fc9709a3 | 3066 | } |
| AnnaBridge | 189:f392fc9709a3 | 3067 | |
| AnnaBridge | 189:f392fc9709a3 | 3068 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3069 | * @brief Get captured value for input channel 1. |
| AnnaBridge | 189:f392fc9709a3 | 3070 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 3071 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 3072 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 3073 | * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3074 | * input channel 1 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 3075 | * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 |
| AnnaBridge | 189:f392fc9709a3 | 3076 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3077 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 3078 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3079 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3080 | { |
| AnnaBridge | 189:f392fc9709a3 | 3081 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
| AnnaBridge | 189:f392fc9709a3 | 3082 | } |
| AnnaBridge | 189:f392fc9709a3 | 3083 | |
| AnnaBridge | 189:f392fc9709a3 | 3084 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3085 | * @brief Get captured value for input channel 2. |
| AnnaBridge | 189:f392fc9709a3 | 3086 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 3087 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 3088 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 3089 | * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3090 | * input channel 2 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 3091 | * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 |
| AnnaBridge | 189:f392fc9709a3 | 3092 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3093 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 3094 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3095 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3096 | { |
| AnnaBridge | 189:f392fc9709a3 | 3097 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
| AnnaBridge | 189:f392fc9709a3 | 3098 | } |
| AnnaBridge | 189:f392fc9709a3 | 3099 | |
| AnnaBridge | 189:f392fc9709a3 | 3100 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3101 | * @brief Get captured value for input channel 3. |
| AnnaBridge | 189:f392fc9709a3 | 3102 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 3103 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 3104 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 3105 | * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3106 | * input channel 3 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 3107 | * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 |
| AnnaBridge | 189:f392fc9709a3 | 3108 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3109 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 3110 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3111 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3112 | { |
| AnnaBridge | 189:f392fc9709a3 | 3113 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
| AnnaBridge | 189:f392fc9709a3 | 3114 | } |
| AnnaBridge | 189:f392fc9709a3 | 3115 | |
| AnnaBridge | 189:f392fc9709a3 | 3116 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3117 | * @brief Get captured value for input channel 4. |
| AnnaBridge | 189:f392fc9709a3 | 3118 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
| AnnaBridge | 189:f392fc9709a3 | 3119 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 3120 | * whether or not a timer instance supports a 32 bits counter. |
| AnnaBridge | 189:f392fc9709a3 | 3121 | * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3122 | * input channel 4 is supported by a timer instance. |
| AnnaBridge | 189:f392fc9709a3 | 3123 | * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 |
| AnnaBridge | 189:f392fc9709a3 | 3124 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3125 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
| AnnaBridge | 189:f392fc9709a3 | 3126 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3127 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3128 | { |
| AnnaBridge | 189:f392fc9709a3 | 3129 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
| AnnaBridge | 189:f392fc9709a3 | 3130 | } |
| AnnaBridge | 189:f392fc9709a3 | 3131 | |
| AnnaBridge | 189:f392fc9709a3 | 3132 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3133 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3134 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3135 | |
| AnnaBridge | 189:f392fc9709a3 | 3136 | /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection |
| AnnaBridge | 189:f392fc9709a3 | 3137 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3138 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3139 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3140 | * @brief Enable external clock mode 2. |
| AnnaBridge | 189:f392fc9709a3 | 3141 | * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. |
| AnnaBridge | 189:f392fc9709a3 | 3142 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 3143 | * whether or not a timer instance supports external clock mode2. |
| AnnaBridge | 189:f392fc9709a3 | 3144 | * @rmtoll SMCR ECE LL_TIM_EnableExternalClock |
| AnnaBridge | 189:f392fc9709a3 | 3145 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3146 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3147 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3148 | __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3149 | { |
| AnnaBridge | 189:f392fc9709a3 | 3150 | SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
| AnnaBridge | 189:f392fc9709a3 | 3151 | } |
| AnnaBridge | 189:f392fc9709a3 | 3152 | |
| AnnaBridge | 189:f392fc9709a3 | 3153 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3154 | * @brief Disable external clock mode 2. |
| AnnaBridge | 189:f392fc9709a3 | 3155 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 3156 | * whether or not a timer instance supports external clock mode2. |
| AnnaBridge | 189:f392fc9709a3 | 3157 | * @rmtoll SMCR ECE LL_TIM_DisableExternalClock |
| AnnaBridge | 189:f392fc9709a3 | 3158 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3159 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3160 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3161 | __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3162 | { |
| AnnaBridge | 189:f392fc9709a3 | 3163 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
| AnnaBridge | 189:f392fc9709a3 | 3164 | } |
| AnnaBridge | 189:f392fc9709a3 | 3165 | |
| AnnaBridge | 189:f392fc9709a3 | 3166 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3167 | * @brief Indicate whether external clock mode 2 is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 3168 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 3169 | * whether or not a timer instance supports external clock mode2. |
| AnnaBridge | 189:f392fc9709a3 | 3170 | * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock |
| AnnaBridge | 189:f392fc9709a3 | 3171 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3172 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 3173 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3174 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3175 | { |
| AnnaBridge | 189:f392fc9709a3 | 3176 | return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)); |
| AnnaBridge | 189:f392fc9709a3 | 3177 | } |
| AnnaBridge | 189:f392fc9709a3 | 3178 | |
| AnnaBridge | 189:f392fc9709a3 | 3179 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3180 | * @brief Set the clock source of the counter clock. |
| AnnaBridge | 189:f392fc9709a3 | 3181 | * @note when selected clock source is external clock mode 1, the timer input |
| AnnaBridge | 189:f392fc9709a3 | 3182 | * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() |
| AnnaBridge | 189:f392fc9709a3 | 3183 | * function. This timer input must be configured by calling |
| AnnaBridge | 189:f392fc9709a3 | 3184 | * the @ref LL_TIM_IC_Config() function. |
| AnnaBridge | 189:f392fc9709a3 | 3185 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 3186 | * whether or not a timer instance supports external clock mode1. |
| AnnaBridge | 189:f392fc9709a3 | 3187 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 3188 | * whether or not a timer instance supports external clock mode2. |
| AnnaBridge | 189:f392fc9709a3 | 3189 | * @rmtoll SMCR SMS LL_TIM_SetClockSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3190 | * SMCR ECE LL_TIM_SetClockSource |
| AnnaBridge | 189:f392fc9709a3 | 3191 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3192 | * @param ClockSource This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3193 | * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL |
| AnnaBridge | 189:f392fc9709a3 | 3194 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 |
| AnnaBridge | 189:f392fc9709a3 | 3195 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 |
| AnnaBridge | 189:f392fc9709a3 | 3196 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3197 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3198 | __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) |
| AnnaBridge | 189:f392fc9709a3 | 3199 | { |
| AnnaBridge | 189:f392fc9709a3 | 3200 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); |
| AnnaBridge | 189:f392fc9709a3 | 3201 | } |
| AnnaBridge | 189:f392fc9709a3 | 3202 | |
| AnnaBridge | 189:f392fc9709a3 | 3203 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3204 | * @brief Set the encoder interface mode. |
| AnnaBridge | 189:f392fc9709a3 | 3205 | * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 3206 | * whether or not a timer instance supports the encoder mode. |
| AnnaBridge | 189:f392fc9709a3 | 3207 | * @rmtoll SMCR SMS LL_TIM_SetEncoderMode |
| AnnaBridge | 189:f392fc9709a3 | 3208 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3209 | * @param EncoderMode This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3210 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 |
| AnnaBridge | 189:f392fc9709a3 | 3211 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 |
| AnnaBridge | 189:f392fc9709a3 | 3212 | * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 |
| AnnaBridge | 189:f392fc9709a3 | 3213 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3214 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3215 | __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) |
| AnnaBridge | 189:f392fc9709a3 | 3216 | { |
| AnnaBridge | 189:f392fc9709a3 | 3217 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); |
| AnnaBridge | 189:f392fc9709a3 | 3218 | } |
| AnnaBridge | 189:f392fc9709a3 | 3219 | |
| AnnaBridge | 189:f392fc9709a3 | 3220 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3221 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3222 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3223 | |
| AnnaBridge | 189:f392fc9709a3 | 3224 | /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration |
| AnnaBridge | 189:f392fc9709a3 | 3225 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3226 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3227 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3228 | * @brief Set the trigger output (TRGO) used for timer synchronization . |
| AnnaBridge | 189:f392fc9709a3 | 3229 | * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 3230 | * whether or not a timer instance can operate as a master timer. |
| AnnaBridge | 189:f392fc9709a3 | 3231 | * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput |
| AnnaBridge | 189:f392fc9709a3 | 3232 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3233 | * @param TimerSynchronization This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3234 | * @arg @ref LL_TIM_TRGO_RESET |
| AnnaBridge | 189:f392fc9709a3 | 3235 | * @arg @ref LL_TIM_TRGO_ENABLE |
| AnnaBridge | 189:f392fc9709a3 | 3236 | * @arg @ref LL_TIM_TRGO_UPDATE |
| AnnaBridge | 189:f392fc9709a3 | 3237 | * @arg @ref LL_TIM_TRGO_CC1IF |
| AnnaBridge | 189:f392fc9709a3 | 3238 | * @arg @ref LL_TIM_TRGO_OC1REF |
| AnnaBridge | 189:f392fc9709a3 | 3239 | * @arg @ref LL_TIM_TRGO_OC2REF |
| AnnaBridge | 189:f392fc9709a3 | 3240 | * @arg @ref LL_TIM_TRGO_OC3REF |
| AnnaBridge | 189:f392fc9709a3 | 3241 | * @arg @ref LL_TIM_TRGO_OC4REF |
| AnnaBridge | 189:f392fc9709a3 | 3242 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3243 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3244 | __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) |
| AnnaBridge | 189:f392fc9709a3 | 3245 | { |
| AnnaBridge | 189:f392fc9709a3 | 3246 | MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); |
| AnnaBridge | 189:f392fc9709a3 | 3247 | } |
| AnnaBridge | 189:f392fc9709a3 | 3248 | |
| AnnaBridge | 189:f392fc9709a3 | 3249 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3250 | * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . |
| AnnaBridge | 189:f392fc9709a3 | 3251 | * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check |
| AnnaBridge | 189:f392fc9709a3 | 3252 | * whether or not a timer instance can be used for ADC synchronization. |
| AnnaBridge | 189:f392fc9709a3 | 3253 | * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 |
| AnnaBridge | 189:f392fc9709a3 | 3254 | * @param TIMx Timer Instance |
| AnnaBridge | 189:f392fc9709a3 | 3255 | * @param ADCSynchronization This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3256 | * @arg @ref LL_TIM_TRGO2_RESET |
| AnnaBridge | 189:f392fc9709a3 | 3257 | * @arg @ref LL_TIM_TRGO2_ENABLE |
| AnnaBridge | 189:f392fc9709a3 | 3258 | * @arg @ref LL_TIM_TRGO2_UPDATE |
| AnnaBridge | 189:f392fc9709a3 | 3259 | * @arg @ref LL_TIM_TRGO2_CC1F |
| AnnaBridge | 189:f392fc9709a3 | 3260 | * @arg @ref LL_TIM_TRGO2_OC1 |
| AnnaBridge | 189:f392fc9709a3 | 3261 | * @arg @ref LL_TIM_TRGO2_OC2 |
| AnnaBridge | 189:f392fc9709a3 | 3262 | * @arg @ref LL_TIM_TRGO2_OC3 |
| AnnaBridge | 189:f392fc9709a3 | 3263 | * @arg @ref LL_TIM_TRGO2_OC4 |
| AnnaBridge | 189:f392fc9709a3 | 3264 | * @arg @ref LL_TIM_TRGO2_OC5 |
| AnnaBridge | 189:f392fc9709a3 | 3265 | * @arg @ref LL_TIM_TRGO2_OC6 |
| AnnaBridge | 189:f392fc9709a3 | 3266 | * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING |
| AnnaBridge | 189:f392fc9709a3 | 3267 | * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING |
| AnnaBridge | 189:f392fc9709a3 | 3268 | * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING |
| AnnaBridge | 189:f392fc9709a3 | 3269 | * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING |
| AnnaBridge | 189:f392fc9709a3 | 3270 | * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING |
| AnnaBridge | 189:f392fc9709a3 | 3271 | * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING |
| AnnaBridge | 189:f392fc9709a3 | 3272 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3273 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3274 | __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) |
| AnnaBridge | 189:f392fc9709a3 | 3275 | { |
| AnnaBridge | 189:f392fc9709a3 | 3276 | MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); |
| AnnaBridge | 189:f392fc9709a3 | 3277 | } |
| AnnaBridge | 189:f392fc9709a3 | 3278 | |
| AnnaBridge | 189:f392fc9709a3 | 3279 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3280 | * @brief Set the synchronization mode of a slave timer. |
| AnnaBridge | 189:f392fc9709a3 | 3281 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3282 | * a timer instance can operate as a slave timer. |
| AnnaBridge | 189:f392fc9709a3 | 3283 | * @rmtoll SMCR SMS LL_TIM_SetSlaveMode |
| AnnaBridge | 189:f392fc9709a3 | 3284 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3285 | * @param SlaveMode This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3286 | * @arg @ref LL_TIM_SLAVEMODE_DISABLED |
| AnnaBridge | 189:f392fc9709a3 | 3287 | * @arg @ref LL_TIM_SLAVEMODE_RESET |
| AnnaBridge | 189:f392fc9709a3 | 3288 | * @arg @ref LL_TIM_SLAVEMODE_GATED |
| AnnaBridge | 189:f392fc9709a3 | 3289 | * @arg @ref LL_TIM_SLAVEMODE_TRIGGER |
| AnnaBridge | 189:f392fc9709a3 | 3290 | * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER |
| AnnaBridge | 189:f392fc9709a3 | 3291 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3292 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3293 | __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) |
| AnnaBridge | 189:f392fc9709a3 | 3294 | { |
| AnnaBridge | 189:f392fc9709a3 | 3295 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); |
| AnnaBridge | 189:f392fc9709a3 | 3296 | } |
| AnnaBridge | 189:f392fc9709a3 | 3297 | |
| AnnaBridge | 189:f392fc9709a3 | 3298 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3299 | * @brief Set the selects the trigger input to be used to synchronize the counter. |
| AnnaBridge | 189:f392fc9709a3 | 3300 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3301 | * a timer instance can operate as a slave timer. |
| AnnaBridge | 189:f392fc9709a3 | 3302 | * @rmtoll SMCR TS LL_TIM_SetTriggerInput |
| AnnaBridge | 189:f392fc9709a3 | 3303 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3304 | * @param TriggerInput This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3305 | * @arg @ref LL_TIM_TS_ITR0 |
| AnnaBridge | 189:f392fc9709a3 | 3306 | * @arg @ref LL_TIM_TS_ITR1 |
| AnnaBridge | 189:f392fc9709a3 | 3307 | * @arg @ref LL_TIM_TS_ITR2 |
| AnnaBridge | 189:f392fc9709a3 | 3308 | * @arg @ref LL_TIM_TS_ITR3 |
| AnnaBridge | 189:f392fc9709a3 | 3309 | * @arg @ref LL_TIM_TS_TI1F_ED |
| AnnaBridge | 189:f392fc9709a3 | 3310 | * @arg @ref LL_TIM_TS_TI1FP1 |
| AnnaBridge | 189:f392fc9709a3 | 3311 | * @arg @ref LL_TIM_TS_TI2FP2 |
| AnnaBridge | 189:f392fc9709a3 | 3312 | * @arg @ref LL_TIM_TS_ETRF |
| AnnaBridge | 189:f392fc9709a3 | 3313 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3314 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3315 | __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) |
| AnnaBridge | 189:f392fc9709a3 | 3316 | { |
| AnnaBridge | 189:f392fc9709a3 | 3317 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); |
| AnnaBridge | 189:f392fc9709a3 | 3318 | } |
| AnnaBridge | 189:f392fc9709a3 | 3319 | |
| AnnaBridge | 189:f392fc9709a3 | 3320 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3321 | * @brief Enable the Master/Slave mode. |
| AnnaBridge | 189:f392fc9709a3 | 3322 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3323 | * a timer instance can operate as a slave timer. |
| AnnaBridge | 189:f392fc9709a3 | 3324 | * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode |
| AnnaBridge | 189:f392fc9709a3 | 3325 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3326 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3327 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3328 | __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3329 | { |
| AnnaBridge | 189:f392fc9709a3 | 3330 | SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
| AnnaBridge | 189:f392fc9709a3 | 3331 | } |
| AnnaBridge | 189:f392fc9709a3 | 3332 | |
| AnnaBridge | 189:f392fc9709a3 | 3333 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3334 | * @brief Disable the Master/Slave mode. |
| AnnaBridge | 189:f392fc9709a3 | 3335 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3336 | * a timer instance can operate as a slave timer. |
| AnnaBridge | 189:f392fc9709a3 | 3337 | * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode |
| AnnaBridge | 189:f392fc9709a3 | 3338 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3339 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3340 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3341 | __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3342 | { |
| AnnaBridge | 189:f392fc9709a3 | 3343 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
| AnnaBridge | 189:f392fc9709a3 | 3344 | } |
| AnnaBridge | 189:f392fc9709a3 | 3345 | |
| AnnaBridge | 189:f392fc9709a3 | 3346 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3347 | * @brief Indicates whether the Master/Slave mode is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 3348 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3349 | * a timer instance can operate as a slave timer. |
| AnnaBridge | 189:f392fc9709a3 | 3350 | * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode |
| AnnaBridge | 189:f392fc9709a3 | 3351 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3352 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 3353 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3354 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3355 | { |
| AnnaBridge | 189:f392fc9709a3 | 3356 | return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)); |
| AnnaBridge | 189:f392fc9709a3 | 3357 | } |
| AnnaBridge | 189:f392fc9709a3 | 3358 | |
| AnnaBridge | 189:f392fc9709a3 | 3359 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3360 | * @brief Configure the external trigger (ETR) input. |
| AnnaBridge | 189:f392fc9709a3 | 3361 | * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3362 | * a timer instance provides an external trigger input. |
| AnnaBridge | 189:f392fc9709a3 | 3363 | * @rmtoll SMCR ETP LL_TIM_ConfigETR\n |
| AnnaBridge | 189:f392fc9709a3 | 3364 | * SMCR ETPS LL_TIM_ConfigETR\n |
| AnnaBridge | 189:f392fc9709a3 | 3365 | * SMCR ETF LL_TIM_ConfigETR |
| AnnaBridge | 189:f392fc9709a3 | 3366 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3367 | * @param ETRPolarity This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3368 | * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED |
| AnnaBridge | 189:f392fc9709a3 | 3369 | * @arg @ref LL_TIM_ETR_POLARITY_INVERTED |
| AnnaBridge | 189:f392fc9709a3 | 3370 | * @param ETRPrescaler This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3371 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 3372 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 3373 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 3374 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 |
| AnnaBridge | 189:f392fc9709a3 | 3375 | * @param ETRFilter This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3376 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1 |
| AnnaBridge | 189:f392fc9709a3 | 3377 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 |
| AnnaBridge | 189:f392fc9709a3 | 3378 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 |
| AnnaBridge | 189:f392fc9709a3 | 3379 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3380 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3381 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3382 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3383 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3384 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3385 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3386 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 |
| AnnaBridge | 189:f392fc9709a3 | 3387 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3388 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3389 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 |
| AnnaBridge | 189:f392fc9709a3 | 3390 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3391 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3392 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3393 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3394 | __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, |
| AnnaBridge | 189:f392fc9709a3 | 3395 | uint32_t ETRFilter) |
| AnnaBridge | 189:f392fc9709a3 | 3396 | { |
| AnnaBridge | 189:f392fc9709a3 | 3397 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); |
| AnnaBridge | 189:f392fc9709a3 | 3398 | } |
| AnnaBridge | 189:f392fc9709a3 | 3399 | |
| AnnaBridge | 189:f392fc9709a3 | 3400 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3401 | * @brief Select the external trigger (ETR) input source. |
| AnnaBridge | 189:f392fc9709a3 | 3402 | * @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or |
| AnnaBridge | 189:f392fc9709a3 | 3403 | * not a timer instance supports ETR source selection. |
| AnnaBridge | 189:f392fc9709a3 | 3404 | * @rmtoll OR2 ETRSEL LL_TIM_SetETRSource |
| AnnaBridge | 189:f392fc9709a3 | 3405 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3406 | * @param ETRSource This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3407 | * @arg @ref LL_TIM_ETRSOURCE_LEGACY |
| AnnaBridge | 189:f392fc9709a3 | 3408 | * @arg @ref LL_TIM_ETRSOURCE_COMP1 |
| AnnaBridge | 189:f392fc9709a3 | 3409 | * @arg @ref LL_TIM_ETRSOURCE_COMP2 |
| AnnaBridge | 189:f392fc9709a3 | 3410 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3411 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3412 | __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) |
| AnnaBridge | 189:f392fc9709a3 | 3413 | { |
| AnnaBridge | 189:f392fc9709a3 | 3414 | |
| AnnaBridge | 189:f392fc9709a3 | 3415 | MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource); |
| AnnaBridge | 189:f392fc9709a3 | 3416 | } |
| AnnaBridge | 189:f392fc9709a3 | 3417 | |
| AnnaBridge | 189:f392fc9709a3 | 3418 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3419 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3420 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3421 | |
| AnnaBridge | 189:f392fc9709a3 | 3422 | /** @defgroup TIM_LL_EF_Break_Function Break function configuration |
| AnnaBridge | 189:f392fc9709a3 | 3423 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3424 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3425 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3426 | * @brief Enable the break function. |
| AnnaBridge | 189:f392fc9709a3 | 3427 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3428 | * a timer instance provides a break input. |
| AnnaBridge | 189:f392fc9709a3 | 3429 | * @rmtoll BDTR BKE LL_TIM_EnableBRK |
| AnnaBridge | 189:f392fc9709a3 | 3430 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3431 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3432 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3433 | __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3434 | { |
| AnnaBridge | 189:f392fc9709a3 | 3435 | SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); |
| AnnaBridge | 189:f392fc9709a3 | 3436 | } |
| AnnaBridge | 189:f392fc9709a3 | 3437 | |
| AnnaBridge | 189:f392fc9709a3 | 3438 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3439 | * @brief Disable the break function. |
| AnnaBridge | 189:f392fc9709a3 | 3440 | * @rmtoll BDTR BKE LL_TIM_DisableBRK |
| AnnaBridge | 189:f392fc9709a3 | 3441 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3442 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3443 | * a timer instance provides a break input. |
| AnnaBridge | 189:f392fc9709a3 | 3444 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3445 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3446 | __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3447 | { |
| AnnaBridge | 189:f392fc9709a3 | 3448 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); |
| AnnaBridge | 189:f392fc9709a3 | 3449 | } |
| AnnaBridge | 189:f392fc9709a3 | 3450 | |
| AnnaBridge | 189:f392fc9709a3 | 3451 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3452 | * @brief Configure the break input. |
| AnnaBridge | 189:f392fc9709a3 | 3453 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3454 | * a timer instance provides a break input. |
| AnnaBridge | 189:f392fc9709a3 | 3455 | * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n |
| AnnaBridge | 189:f392fc9709a3 | 3456 | * BDTR BKF LL_TIM_ConfigBRK |
| AnnaBridge | 189:f392fc9709a3 | 3457 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3458 | * @param BreakPolarity This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3459 | * @arg @ref LL_TIM_BREAK_POLARITY_LOW |
| AnnaBridge | 189:f392fc9709a3 | 3460 | * @arg @ref LL_TIM_BREAK_POLARITY_HIGH |
| AnnaBridge | 189:f392fc9709a3 | 3461 | * @param BreakFilter This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3462 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 |
| AnnaBridge | 189:f392fc9709a3 | 3463 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 |
| AnnaBridge | 189:f392fc9709a3 | 3464 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 |
| AnnaBridge | 189:f392fc9709a3 | 3465 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3466 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3467 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3468 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3469 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3470 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3471 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3472 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 |
| AnnaBridge | 189:f392fc9709a3 | 3473 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3474 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3475 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 |
| AnnaBridge | 189:f392fc9709a3 | 3476 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3477 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3478 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3479 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3480 | __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter) |
| AnnaBridge | 189:f392fc9709a3 | 3481 | { |
| AnnaBridge | 189:f392fc9709a3 | 3482 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); |
| AnnaBridge | 189:f392fc9709a3 | 3483 | } |
| AnnaBridge | 189:f392fc9709a3 | 3484 | |
| AnnaBridge | 189:f392fc9709a3 | 3485 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3486 | * @brief Enable the break 2 function. |
| AnnaBridge | 189:f392fc9709a3 | 3487 | * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3488 | * a timer instance provides a second break input. |
| AnnaBridge | 189:f392fc9709a3 | 3489 | * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 |
| AnnaBridge | 189:f392fc9709a3 | 3490 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3491 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3492 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3493 | __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3494 | { |
| AnnaBridge | 189:f392fc9709a3 | 3495 | SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); |
| AnnaBridge | 189:f392fc9709a3 | 3496 | } |
| AnnaBridge | 189:f392fc9709a3 | 3497 | |
| AnnaBridge | 189:f392fc9709a3 | 3498 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3499 | * @brief Disable the break 2 function. |
| AnnaBridge | 189:f392fc9709a3 | 3500 | * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3501 | * a timer instance provides a second break input. |
| AnnaBridge | 189:f392fc9709a3 | 3502 | * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 |
| AnnaBridge | 189:f392fc9709a3 | 3503 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3504 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3505 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3506 | __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3507 | { |
| AnnaBridge | 189:f392fc9709a3 | 3508 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); |
| AnnaBridge | 189:f392fc9709a3 | 3509 | } |
| AnnaBridge | 189:f392fc9709a3 | 3510 | |
| AnnaBridge | 189:f392fc9709a3 | 3511 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3512 | * @brief Configure the break 2 input. |
| AnnaBridge | 189:f392fc9709a3 | 3513 | * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3514 | * a timer instance provides a second break input. |
| AnnaBridge | 189:f392fc9709a3 | 3515 | * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n |
| AnnaBridge | 189:f392fc9709a3 | 3516 | * BDTR BK2F LL_TIM_ConfigBRK2 |
| AnnaBridge | 189:f392fc9709a3 | 3517 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3518 | * @param Break2Polarity This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3519 | * @arg @ref LL_TIM_BREAK2_POLARITY_LOW |
| AnnaBridge | 189:f392fc9709a3 | 3520 | * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH |
| AnnaBridge | 189:f392fc9709a3 | 3521 | * @param Break2Filter This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3522 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 |
| AnnaBridge | 189:f392fc9709a3 | 3523 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 |
| AnnaBridge | 189:f392fc9709a3 | 3524 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 |
| AnnaBridge | 189:f392fc9709a3 | 3525 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3526 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3527 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3528 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3529 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3530 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3531 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3532 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 |
| AnnaBridge | 189:f392fc9709a3 | 3533 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3534 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3535 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 |
| AnnaBridge | 189:f392fc9709a3 | 3536 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 |
| AnnaBridge | 189:f392fc9709a3 | 3537 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 |
| AnnaBridge | 189:f392fc9709a3 | 3538 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3539 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3540 | __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) |
| AnnaBridge | 189:f392fc9709a3 | 3541 | { |
| AnnaBridge | 189:f392fc9709a3 | 3542 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); |
| AnnaBridge | 189:f392fc9709a3 | 3543 | } |
| AnnaBridge | 189:f392fc9709a3 | 3544 | |
| AnnaBridge | 189:f392fc9709a3 | 3545 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3546 | * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. |
| AnnaBridge | 189:f392fc9709a3 | 3547 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3548 | * a timer instance provides a break input. |
| AnnaBridge | 189:f392fc9709a3 | 3549 | * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n |
| AnnaBridge | 189:f392fc9709a3 | 3550 | * BDTR OSSR LL_TIM_SetOffStates |
| AnnaBridge | 189:f392fc9709a3 | 3551 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3552 | * @param OffStateIdle This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3553 | * @arg @ref LL_TIM_OSSI_DISABLE |
| AnnaBridge | 189:f392fc9709a3 | 3554 | * @arg @ref LL_TIM_OSSI_ENABLE |
| AnnaBridge | 189:f392fc9709a3 | 3555 | * @param OffStateRun This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3556 | * @arg @ref LL_TIM_OSSR_DISABLE |
| AnnaBridge | 189:f392fc9709a3 | 3557 | * @arg @ref LL_TIM_OSSR_ENABLE |
| AnnaBridge | 189:f392fc9709a3 | 3558 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3559 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3560 | __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) |
| AnnaBridge | 189:f392fc9709a3 | 3561 | { |
| AnnaBridge | 189:f392fc9709a3 | 3562 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); |
| AnnaBridge | 189:f392fc9709a3 | 3563 | } |
| AnnaBridge | 189:f392fc9709a3 | 3564 | |
| AnnaBridge | 189:f392fc9709a3 | 3565 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3566 | * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). |
| AnnaBridge | 189:f392fc9709a3 | 3567 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3568 | * a timer instance provides a break input. |
| AnnaBridge | 189:f392fc9709a3 | 3569 | * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput |
| AnnaBridge | 189:f392fc9709a3 | 3570 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3571 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3572 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3573 | __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3574 | { |
| AnnaBridge | 189:f392fc9709a3 | 3575 | SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); |
| AnnaBridge | 189:f392fc9709a3 | 3576 | } |
| AnnaBridge | 189:f392fc9709a3 | 3577 | |
| AnnaBridge | 189:f392fc9709a3 | 3578 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3579 | * @brief Disable automatic output (MOE can be set only by software). |
| AnnaBridge | 189:f392fc9709a3 | 3580 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3581 | * a timer instance provides a break input. |
| AnnaBridge | 189:f392fc9709a3 | 3582 | * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput |
| AnnaBridge | 189:f392fc9709a3 | 3583 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3584 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3585 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3586 | __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3587 | { |
| AnnaBridge | 189:f392fc9709a3 | 3588 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); |
| AnnaBridge | 189:f392fc9709a3 | 3589 | } |
| AnnaBridge | 189:f392fc9709a3 | 3590 | |
| AnnaBridge | 189:f392fc9709a3 | 3591 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3592 | * @brief Indicate whether automatic output is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 3593 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3594 | * a timer instance provides a break input. |
| AnnaBridge | 189:f392fc9709a3 | 3595 | * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput |
| AnnaBridge | 189:f392fc9709a3 | 3596 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3597 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 3598 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3599 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3600 | { |
| AnnaBridge | 189:f392fc9709a3 | 3601 | return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)); |
| AnnaBridge | 189:f392fc9709a3 | 3602 | } |
| AnnaBridge | 189:f392fc9709a3 | 3603 | |
| AnnaBridge | 189:f392fc9709a3 | 3604 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3605 | * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). |
| AnnaBridge | 189:f392fc9709a3 | 3606 | * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by |
| AnnaBridge | 189:f392fc9709a3 | 3607 | * software and is reset in case of break or break2 event |
| AnnaBridge | 189:f392fc9709a3 | 3608 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3609 | * a timer instance provides a break input. |
| AnnaBridge | 189:f392fc9709a3 | 3610 | * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs |
| AnnaBridge | 189:f392fc9709a3 | 3611 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3612 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3613 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3614 | __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3615 | { |
| AnnaBridge | 189:f392fc9709a3 | 3616 | SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); |
| AnnaBridge | 189:f392fc9709a3 | 3617 | } |
| AnnaBridge | 189:f392fc9709a3 | 3618 | |
| AnnaBridge | 189:f392fc9709a3 | 3619 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3620 | * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). |
| AnnaBridge | 189:f392fc9709a3 | 3621 | * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by |
| AnnaBridge | 189:f392fc9709a3 | 3622 | * software and is reset in case of break or break2 event. |
| AnnaBridge | 189:f392fc9709a3 | 3623 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3624 | * a timer instance provides a break input. |
| AnnaBridge | 189:f392fc9709a3 | 3625 | * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs |
| AnnaBridge | 189:f392fc9709a3 | 3626 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3627 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3628 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3629 | __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3630 | { |
| AnnaBridge | 189:f392fc9709a3 | 3631 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); |
| AnnaBridge | 189:f392fc9709a3 | 3632 | } |
| AnnaBridge | 189:f392fc9709a3 | 3633 | |
| AnnaBridge | 189:f392fc9709a3 | 3634 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3635 | * @brief Indicates whether outputs are enabled. |
| AnnaBridge | 189:f392fc9709a3 | 3636 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3637 | * a timer instance provides a break input. |
| AnnaBridge | 189:f392fc9709a3 | 3638 | * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs |
| AnnaBridge | 189:f392fc9709a3 | 3639 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3640 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 3641 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3642 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 3643 | { |
| AnnaBridge | 189:f392fc9709a3 | 3644 | return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)); |
| AnnaBridge | 189:f392fc9709a3 | 3645 | } |
| AnnaBridge | 189:f392fc9709a3 | 3646 | |
| AnnaBridge | 189:f392fc9709a3 | 3647 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3648 | * @brief Enable the signals connected to the designated timer break input. |
| AnnaBridge | 189:f392fc9709a3 | 3649 | * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether |
| AnnaBridge | 189:f392fc9709a3 | 3650 | * or not a timer instance allows for break input selection. |
| AnnaBridge | 189:f392fc9709a3 | 3651 | * @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3652 | * OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3653 | * OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3654 | * OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3655 | * OR3 BK2INE LL_TIM_EnableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3656 | * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3657 | * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3658 | * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource |
| AnnaBridge | 189:f392fc9709a3 | 3659 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3660 | * @param BreakInput This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3661 | * @arg @ref LL_TIM_BREAK_INPUT_BKIN |
| AnnaBridge | 189:f392fc9709a3 | 3662 | * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 |
| AnnaBridge | 189:f392fc9709a3 | 3663 | * @param Source This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3664 | * @arg @ref LL_TIM_BKIN_SOURCE_BKIN |
| AnnaBridge | 189:f392fc9709a3 | 3665 | * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 |
| AnnaBridge | 189:f392fc9709a3 | 3666 | * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 |
| AnnaBridge | 189:f392fc9709a3 | 3667 | * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK |
| AnnaBridge | 189:f392fc9709a3 | 3668 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3669 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3670 | __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) |
| AnnaBridge | 189:f392fc9709a3 | 3671 | { |
| AnnaBridge | 189:f392fc9709a3 | 3672 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); |
| AnnaBridge | 189:f392fc9709a3 | 3673 | SET_BIT(*pReg , Source); |
| AnnaBridge | 189:f392fc9709a3 | 3674 | } |
| AnnaBridge | 189:f392fc9709a3 | 3675 | |
| AnnaBridge | 189:f392fc9709a3 | 3676 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3677 | * @brief Disable the signals connected to the designated timer break input. |
| AnnaBridge | 189:f392fc9709a3 | 3678 | * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether |
| AnnaBridge | 189:f392fc9709a3 | 3679 | * or not a timer instance allows for break input selection. |
| AnnaBridge | 189:f392fc9709a3 | 3680 | * @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3681 | * OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3682 | * OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3683 | * OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3684 | * OR3 BK2INE LL_TIM_DisableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3685 | * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3686 | * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n |
| AnnaBridge | 189:f392fc9709a3 | 3687 | * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource |
| AnnaBridge | 189:f392fc9709a3 | 3688 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3689 | * @param BreakInput This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3690 | * @arg @ref LL_TIM_BREAK_INPUT_BKIN |
| AnnaBridge | 189:f392fc9709a3 | 3691 | * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 |
| AnnaBridge | 189:f392fc9709a3 | 3692 | * @param Source This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3693 | * @arg @ref LL_TIM_BKIN_SOURCE_BKIN |
| AnnaBridge | 189:f392fc9709a3 | 3694 | * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 |
| AnnaBridge | 189:f392fc9709a3 | 3695 | * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 |
| AnnaBridge | 189:f392fc9709a3 | 3696 | * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK |
| AnnaBridge | 189:f392fc9709a3 | 3697 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3698 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3699 | __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) |
| AnnaBridge | 189:f392fc9709a3 | 3700 | { |
| AnnaBridge | 189:f392fc9709a3 | 3701 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); |
| AnnaBridge | 189:f392fc9709a3 | 3702 | CLEAR_BIT(*pReg, Source); |
| AnnaBridge | 189:f392fc9709a3 | 3703 | } |
| AnnaBridge | 189:f392fc9709a3 | 3704 | |
| AnnaBridge | 189:f392fc9709a3 | 3705 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3706 | * @brief Set the polarity of the break signal for the timer break input. |
| AnnaBridge | 189:f392fc9709a3 | 3707 | * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether |
| AnnaBridge | 189:f392fc9709a3 | 3708 | * or not a timer instance allows for break input selection. |
| AnnaBridge | 189:f392fc9709a3 | 3709 | * @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 3710 | * OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 3711 | * OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 3712 | * OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 3713 | * OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n |
| AnnaBridge | 189:f392fc9709a3 | 3714 | * OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity |
| AnnaBridge | 189:f392fc9709a3 | 3715 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3716 | * @param BreakInput This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3717 | * @arg @ref LL_TIM_BREAK_INPUT_BKIN |
| AnnaBridge | 189:f392fc9709a3 | 3718 | * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 |
| AnnaBridge | 189:f392fc9709a3 | 3719 | * @param Source This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3720 | * @arg @ref LL_TIM_BKIN_SOURCE_BKIN |
| AnnaBridge | 189:f392fc9709a3 | 3721 | * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 |
| AnnaBridge | 189:f392fc9709a3 | 3722 | * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 |
| AnnaBridge | 189:f392fc9709a3 | 3723 | * @param Polarity This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3724 | * @arg @ref LL_TIM_BKIN_POLARITY_LOW |
| AnnaBridge | 189:f392fc9709a3 | 3725 | * @arg @ref LL_TIM_BKIN_POLARITY_HIGH |
| AnnaBridge | 189:f392fc9709a3 | 3726 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3727 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3728 | __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, |
| AnnaBridge | 189:f392fc9709a3 | 3729 | uint32_t Polarity) |
| AnnaBridge | 189:f392fc9709a3 | 3730 | { |
| AnnaBridge | 189:f392fc9709a3 | 3731 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); |
| AnnaBridge | 189:f392fc9709a3 | 3732 | MODIFY_REG(*pReg, (TIMx_OR2_BKINP << (TIM_POSITION_BRK_SOURCE)) , (Polarity << (TIM_POSITION_BRK_SOURCE))); |
| AnnaBridge | 189:f392fc9709a3 | 3733 | } |
| AnnaBridge | 189:f392fc9709a3 | 3734 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3735 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3736 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3737 | |
| AnnaBridge | 189:f392fc9709a3 | 3738 | /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration |
| AnnaBridge | 189:f392fc9709a3 | 3739 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3740 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3741 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3742 | * @brief Configures the timer DMA burst feature. |
| AnnaBridge | 189:f392fc9709a3 | 3743 | * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or |
| AnnaBridge | 189:f392fc9709a3 | 3744 | * not a timer instance supports the DMA burst mode. |
| AnnaBridge | 189:f392fc9709a3 | 3745 | * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n |
| AnnaBridge | 189:f392fc9709a3 | 3746 | * DCR DBA LL_TIM_ConfigDMABurst |
| AnnaBridge | 189:f392fc9709a3 | 3747 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3748 | * @param DMABurstBaseAddress This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3749 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 |
| AnnaBridge | 189:f392fc9709a3 | 3750 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 |
| AnnaBridge | 189:f392fc9709a3 | 3751 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR |
| AnnaBridge | 189:f392fc9709a3 | 3752 | * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER |
| AnnaBridge | 189:f392fc9709a3 | 3753 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SR |
| AnnaBridge | 189:f392fc9709a3 | 3754 | * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR |
| AnnaBridge | 189:f392fc9709a3 | 3755 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 |
| AnnaBridge | 189:f392fc9709a3 | 3756 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 |
| AnnaBridge | 189:f392fc9709a3 | 3757 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER |
| AnnaBridge | 189:f392fc9709a3 | 3758 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT |
| AnnaBridge | 189:f392fc9709a3 | 3759 | * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC |
| AnnaBridge | 189:f392fc9709a3 | 3760 | * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR |
| AnnaBridge | 189:f392fc9709a3 | 3761 | * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR |
| AnnaBridge | 189:f392fc9709a3 | 3762 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 |
| AnnaBridge | 189:f392fc9709a3 | 3763 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 |
| AnnaBridge | 189:f392fc9709a3 | 3764 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 |
| AnnaBridge | 189:f392fc9709a3 | 3765 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 |
| AnnaBridge | 189:f392fc9709a3 | 3766 | * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR |
| AnnaBridge | 189:f392fc9709a3 | 3767 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 |
| AnnaBridge | 189:f392fc9709a3 | 3768 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 |
| AnnaBridge | 189:f392fc9709a3 | 3769 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 |
| AnnaBridge | 189:f392fc9709a3 | 3770 | * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1 |
| AnnaBridge | 189:f392fc9709a3 | 3771 | * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2 |
| AnnaBridge | 189:f392fc9709a3 | 3772 | * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3 |
| AnnaBridge | 189:f392fc9709a3 | 3773 | * @param DMABurstLength This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3774 | * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER |
| AnnaBridge | 189:f392fc9709a3 | 3775 | * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3776 | * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3777 | * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3778 | * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3779 | * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3780 | * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3781 | * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3782 | * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3783 | * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3784 | * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3785 | * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3786 | * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3787 | * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3788 | * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3789 | * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3790 | * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3791 | * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS |
| AnnaBridge | 189:f392fc9709a3 | 3792 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3793 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3794 | __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) |
| AnnaBridge | 189:f392fc9709a3 | 3795 | { |
| AnnaBridge | 189:f392fc9709a3 | 3796 | MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); |
| AnnaBridge | 189:f392fc9709a3 | 3797 | } |
| AnnaBridge | 189:f392fc9709a3 | 3798 | |
| AnnaBridge | 189:f392fc9709a3 | 3799 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3800 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3801 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3802 | |
| AnnaBridge | 189:f392fc9709a3 | 3803 | /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping |
| AnnaBridge | 189:f392fc9709a3 | 3804 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3805 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3806 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3807 | * @brief Remap TIM inputs (input channel, internal/external triggers). |
| AnnaBridge | 189:f392fc9709a3 | 3808 | * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not |
| AnnaBridge | 189:f392fc9709a3 | 3809 | * a some timer inputs can be remapped. |
| AnnaBridge | 189:f392fc9709a3 | 3810 | @if STM32L486xx |
| AnnaBridge | 189:f392fc9709a3 | 3811 | * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3812 | * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3813 | * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3814 | * TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3815 | * TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3816 | * TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3817 | * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3818 | * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3819 | * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3820 | * TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3821 | * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3822 | * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3823 | * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3824 | * TIM17_OR1 TI1_RMP LL_TIM_SetRemap |
| AnnaBridge | 189:f392fc9709a3 | 3825 | @endif |
| AnnaBridge | 189:f392fc9709a3 | 3826 | @if STM32L443xx |
| AnnaBridge | 189:f392fc9709a3 | 3827 | * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3828 | * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3829 | * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3830 | * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3831 | * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3832 | * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3833 | * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3834 | * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3835 | * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n |
| AnnaBridge | 189:f392fc9709a3 | 3836 | @endif |
| AnnaBridge | 189:f392fc9709a3 | 3837 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 3838 | * @param Remap Remap param depends on the TIMx. Description available only |
| AnnaBridge | 189:f392fc9709a3 | 3839 | * in CHM version of the User Manual (not in .pdf). |
| AnnaBridge | 189:f392fc9709a3 | 3840 | * Otherwise see Reference Manual description of OR registers. |
| AnnaBridge | 189:f392fc9709a3 | 3841 | * |
| AnnaBridge | 189:f392fc9709a3 | 3842 | * Below description summarizes "Timer Instance" and "Remap" param combinations: |
| AnnaBridge | 189:f392fc9709a3 | 3843 | * |
| AnnaBridge | 189:f392fc9709a3 | 3844 | @if STM32L486xx |
| AnnaBridge | 189:f392fc9709a3 | 3845 | * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where |
| AnnaBridge | 189:f392fc9709a3 | 3846 | * |
| AnnaBridge | 189:f392fc9709a3 | 3847 | * . . ADC1_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3848 | * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC |
| AnnaBridge | 189:f392fc9709a3 | 3849 | * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 |
| AnnaBridge | 189:f392fc9709a3 | 3850 | * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 |
| AnnaBridge | 189:f392fc9709a3 | 3851 | * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 |
| AnnaBridge | 189:f392fc9709a3 | 3852 | * |
| AnnaBridge | 189:f392fc9709a3 | 3853 | * . . ADC3_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3854 | * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC |
| AnnaBridge | 189:f392fc9709a3 | 3855 | * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 |
| AnnaBridge | 189:f392fc9709a3 | 3856 | * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 |
| AnnaBridge | 189:f392fc9709a3 | 3857 | * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 |
| AnnaBridge | 189:f392fc9709a3 | 3858 | * |
| AnnaBridge | 189:f392fc9709a3 | 3859 | * . . TI1_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3860 | * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 3861 | * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 |
| AnnaBridge | 189:f392fc9709a3 | 3862 | * |
| AnnaBridge | 189:f392fc9709a3 | 3863 | * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where |
| AnnaBridge | 189:f392fc9709a3 | 3864 | * |
| AnnaBridge | 189:f392fc9709a3 | 3865 | * ITR1_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3866 | * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO |
| AnnaBridge | 189:f392fc9709a3 | 3867 | * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF |
| AnnaBridge | 189:f392fc9709a3 | 3868 | * |
| AnnaBridge | 189:f392fc9709a3 | 3869 | * . . ETR1_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3870 | * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 3871 | * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE |
| AnnaBridge | 189:f392fc9709a3 | 3872 | * |
| AnnaBridge | 189:f392fc9709a3 | 3873 | * . . TI4_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3874 | * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 3875 | * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 |
| AnnaBridge | 189:f392fc9709a3 | 3876 | * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 |
| AnnaBridge | 189:f392fc9709a3 | 3877 | * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 |
| AnnaBridge | 189:f392fc9709a3 | 3878 | * |
| AnnaBridge | 189:f392fc9709a3 | 3879 | * TIM3: one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3880 | * |
| AnnaBridge | 189:f392fc9709a3 | 3881 | * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 3882 | * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1 |
| AnnaBridge | 189:f392fc9709a3 | 3883 | * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2 |
| AnnaBridge | 189:f392fc9709a3 | 3884 | * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 |
| AnnaBridge | 189:f392fc9709a3 | 3885 | * |
| AnnaBridge | 189:f392fc9709a3 | 3886 | * TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where |
| AnnaBridge | 189:f392fc9709a3 | 3887 | * |
| AnnaBridge | 189:f392fc9709a3 | 3888 | * . . ADC1_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3889 | * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC |
| AnnaBridge | 189:f392fc9709a3 | 3890 | * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 |
| AnnaBridge | 189:f392fc9709a3 | 3891 | * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 |
| AnnaBridge | 189:f392fc9709a3 | 3892 | * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 |
| AnnaBridge | 189:f392fc9709a3 | 3893 | * |
| AnnaBridge | 189:f392fc9709a3 | 3894 | * . . ADC3_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3895 | * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC |
| AnnaBridge | 189:f392fc9709a3 | 3896 | * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 |
| AnnaBridge | 189:f392fc9709a3 | 3897 | * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 |
| AnnaBridge | 189:f392fc9709a3 | 3898 | * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 |
| AnnaBridge | 189:f392fc9709a3 | 3899 | * |
| AnnaBridge | 189:f392fc9709a3 | 3900 | * . . TI1_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3901 | * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 3902 | * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2 |
| AnnaBridge | 189:f392fc9709a3 | 3903 | * |
| AnnaBridge | 189:f392fc9709a3 | 3904 | * TIM15: any combination of TI1_RMP, ENCODER_MODE where |
| AnnaBridge | 189:f392fc9709a3 | 3905 | * |
| AnnaBridge | 189:f392fc9709a3 | 3906 | * . . TI1_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3907 | * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 3908 | * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE |
| AnnaBridge | 189:f392fc9709a3 | 3909 | * |
| AnnaBridge | 189:f392fc9709a3 | 3910 | * . . ENCODER_MODE can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3911 | * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION |
| AnnaBridge | 189:f392fc9709a3 | 3912 | * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2 |
| AnnaBridge | 189:f392fc9709a3 | 3913 | * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3 |
| AnnaBridge | 189:f392fc9709a3 | 3914 | * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4 |
| AnnaBridge | 189:f392fc9709a3 | 3915 | * |
| AnnaBridge | 189:f392fc9709a3 | 3916 | * TIM16: one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3917 | * |
| AnnaBridge | 189:f392fc9709a3 | 3918 | * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 3919 | * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI |
| AnnaBridge | 189:f392fc9709a3 | 3920 | * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE |
| AnnaBridge | 189:f392fc9709a3 | 3921 | * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC |
| AnnaBridge | 189:f392fc9709a3 | 3922 | * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI |
| AnnaBridge | 189:f392fc9709a3 | 3923 | * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32 |
| AnnaBridge | 189:f392fc9709a3 | 3924 | * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO |
| AnnaBridge | 189:f392fc9709a3 | 3925 | * |
| AnnaBridge | 189:f392fc9709a3 | 3926 | * TIM17: one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3927 | * |
| AnnaBridge | 189:f392fc9709a3 | 3928 | * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 3929 | * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI |
| AnnaBridge | 189:f392fc9709a3 | 3930 | * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32 |
| AnnaBridge | 189:f392fc9709a3 | 3931 | * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO |
| AnnaBridge | 189:f392fc9709a3 | 3932 | @endif |
| AnnaBridge | 189:f392fc9709a3 | 3933 | @if STM32L443xx |
| AnnaBridge | 189:f392fc9709a3 | 3934 | * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where |
| AnnaBridge | 189:f392fc9709a3 | 3935 | * |
| AnnaBridge | 189:f392fc9709a3 | 3936 | * . . ADC1_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3937 | * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC |
| AnnaBridge | 189:f392fc9709a3 | 3938 | * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 |
| AnnaBridge | 189:f392fc9709a3 | 3939 | * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 |
| AnnaBridge | 189:f392fc9709a3 | 3940 | * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 |
| AnnaBridge | 189:f392fc9709a3 | 3941 | * |
| AnnaBridge | 189:f392fc9709a3 | 3942 | * . . TI1_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3943 | * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 3944 | * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 |
| AnnaBridge | 189:f392fc9709a3 | 3945 | * |
| AnnaBridge | 189:f392fc9709a3 | 3946 | * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where |
| AnnaBridge | 189:f392fc9709a3 | 3947 | * |
| AnnaBridge | 189:f392fc9709a3 | 3948 | * ITR1_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3949 | * @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE |
| AnnaBridge | 189:f392fc9709a3 | 3950 | * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF |
| AnnaBridge | 189:f392fc9709a3 | 3951 | * |
| AnnaBridge | 189:f392fc9709a3 | 3952 | * . . ETR1_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3953 | * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 3954 | * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE |
| AnnaBridge | 189:f392fc9709a3 | 3955 | * |
| AnnaBridge | 189:f392fc9709a3 | 3956 | * . . TI4_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3957 | * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 3958 | * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 |
| AnnaBridge | 189:f392fc9709a3 | 3959 | * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 |
| AnnaBridge | 189:f392fc9709a3 | 3960 | * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 |
| AnnaBridge | 189:f392fc9709a3 | 3961 | * |
| AnnaBridge | 189:f392fc9709a3 | 3962 | * TIM15: any combination of TI1_RMP, ENCODER_MODE where |
| AnnaBridge | 189:f392fc9709a3 | 3963 | * |
| AnnaBridge | 189:f392fc9709a3 | 3964 | * . . TI1_RMP can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3965 | * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 3966 | * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE |
| AnnaBridge | 189:f392fc9709a3 | 3967 | * |
| AnnaBridge | 189:f392fc9709a3 | 3968 | * . . ENCODER_MODE can be one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3969 | * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION |
| AnnaBridge | 189:f392fc9709a3 | 3970 | * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2 |
| AnnaBridge | 189:f392fc9709a3 | 3971 | * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3 |
| AnnaBridge | 189:f392fc9709a3 | 3972 | * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4 |
| AnnaBridge | 189:f392fc9709a3 | 3973 | * |
| AnnaBridge | 189:f392fc9709a3 | 3974 | * TIM16: one of the following values |
| AnnaBridge | 189:f392fc9709a3 | 3975 | * |
| AnnaBridge | 189:f392fc9709a3 | 3976 | * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 3977 | * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI |
| AnnaBridge | 189:f392fc9709a3 | 3978 | * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE |
| AnnaBridge | 189:f392fc9709a3 | 3979 | * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC |
| AnnaBridge | 189:f392fc9709a3 | 3980 | * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI |
| AnnaBridge | 189:f392fc9709a3 | 3981 | * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32 |
| AnnaBridge | 189:f392fc9709a3 | 3982 | * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO |
| AnnaBridge | 189:f392fc9709a3 | 3983 | @endif |
| AnnaBridge | 189:f392fc9709a3 | 3984 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3985 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3986 | __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) |
| AnnaBridge | 189:f392fc9709a3 | 3987 | { |
| AnnaBridge | 189:f392fc9709a3 | 3988 | MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK)); |
| AnnaBridge | 189:f392fc9709a3 | 3989 | } |
| AnnaBridge | 189:f392fc9709a3 | 3990 | |
| AnnaBridge | 189:f392fc9709a3 | 3991 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3992 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3993 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3994 | |
| AnnaBridge | 189:f392fc9709a3 | 3995 | /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management |
| AnnaBridge | 189:f392fc9709a3 | 3996 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3997 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3998 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3999 | * @brief Set the OCREF clear input source |
| AnnaBridge | 189:f392fc9709a3 | 4000 | * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT |
| AnnaBridge | 189:f392fc9709a3 | 4001 | * @note This function can only be used in Output compare and PWM modes. |
| AnnaBridge | 189:f392fc9709a3 | 4002 | * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource |
| AnnaBridge | 189:f392fc9709a3 | 4003 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4004 | * @param OCRefClearInputSource This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 4005 | * @arg @ref LL_TIM_OCREF_CLR_INT_NC |
| AnnaBridge | 189:f392fc9709a3 | 4006 | * @arg @ref LL_TIM_OCREF_CLR_INT_ETR |
| AnnaBridge | 189:f392fc9709a3 | 4007 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4008 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4009 | __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) |
| AnnaBridge | 189:f392fc9709a3 | 4010 | { |
| AnnaBridge | 189:f392fc9709a3 | 4011 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); |
| AnnaBridge | 189:f392fc9709a3 | 4012 | } |
| AnnaBridge | 189:f392fc9709a3 | 4013 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4014 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 4015 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4016 | |
| AnnaBridge | 189:f392fc9709a3 | 4017 | /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management |
| AnnaBridge | 189:f392fc9709a3 | 4018 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 4019 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4020 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4021 | * @brief Clear the update interrupt flag (UIF). |
| AnnaBridge | 189:f392fc9709a3 | 4022 | * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE |
| AnnaBridge | 189:f392fc9709a3 | 4023 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4024 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4025 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4026 | __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4027 | { |
| AnnaBridge | 189:f392fc9709a3 | 4028 | WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); |
| AnnaBridge | 189:f392fc9709a3 | 4029 | } |
| AnnaBridge | 189:f392fc9709a3 | 4030 | |
| AnnaBridge | 189:f392fc9709a3 | 4031 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4032 | * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4033 | * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE |
| AnnaBridge | 189:f392fc9709a3 | 4034 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4035 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4036 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4037 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4038 | { |
| AnnaBridge | 189:f392fc9709a3 | 4039 | return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); |
| AnnaBridge | 189:f392fc9709a3 | 4040 | } |
| AnnaBridge | 189:f392fc9709a3 | 4041 | |
| AnnaBridge | 189:f392fc9709a3 | 4042 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4043 | * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). |
| AnnaBridge | 189:f392fc9709a3 | 4044 | * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 |
| AnnaBridge | 189:f392fc9709a3 | 4045 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4046 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4047 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4048 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4049 | { |
| AnnaBridge | 189:f392fc9709a3 | 4050 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4051 | } |
| AnnaBridge | 189:f392fc9709a3 | 4052 | |
| AnnaBridge | 189:f392fc9709a3 | 4053 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4054 | * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4055 | * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 |
| AnnaBridge | 189:f392fc9709a3 | 4056 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4057 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4058 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4059 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4060 | { |
| AnnaBridge | 189:f392fc9709a3 | 4061 | return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4062 | } |
| AnnaBridge | 189:f392fc9709a3 | 4063 | |
| AnnaBridge | 189:f392fc9709a3 | 4064 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4065 | * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). |
| AnnaBridge | 189:f392fc9709a3 | 4066 | * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 |
| AnnaBridge | 189:f392fc9709a3 | 4067 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4068 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4069 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4070 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4071 | { |
| AnnaBridge | 189:f392fc9709a3 | 4072 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4073 | } |
| AnnaBridge | 189:f392fc9709a3 | 4074 | |
| AnnaBridge | 189:f392fc9709a3 | 4075 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4076 | * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4077 | * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 |
| AnnaBridge | 189:f392fc9709a3 | 4078 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4079 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4080 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4081 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4082 | { |
| AnnaBridge | 189:f392fc9709a3 | 4083 | return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4084 | } |
| AnnaBridge | 189:f392fc9709a3 | 4085 | |
| AnnaBridge | 189:f392fc9709a3 | 4086 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4087 | * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). |
| AnnaBridge | 189:f392fc9709a3 | 4088 | * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 |
| AnnaBridge | 189:f392fc9709a3 | 4089 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4090 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4091 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4092 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4093 | { |
| AnnaBridge | 189:f392fc9709a3 | 4094 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4095 | } |
| AnnaBridge | 189:f392fc9709a3 | 4096 | |
| AnnaBridge | 189:f392fc9709a3 | 4097 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4098 | * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4099 | * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 |
| AnnaBridge | 189:f392fc9709a3 | 4100 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4101 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4102 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4103 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4104 | { |
| AnnaBridge | 189:f392fc9709a3 | 4105 | return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4106 | } |
| AnnaBridge | 189:f392fc9709a3 | 4107 | |
| AnnaBridge | 189:f392fc9709a3 | 4108 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4109 | * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). |
| AnnaBridge | 189:f392fc9709a3 | 4110 | * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 |
| AnnaBridge | 189:f392fc9709a3 | 4111 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4112 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4113 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4114 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4115 | { |
| AnnaBridge | 189:f392fc9709a3 | 4116 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4117 | } |
| AnnaBridge | 189:f392fc9709a3 | 4118 | |
| AnnaBridge | 189:f392fc9709a3 | 4119 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4120 | * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4121 | * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 |
| AnnaBridge | 189:f392fc9709a3 | 4122 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4123 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4124 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4125 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4126 | { |
| AnnaBridge | 189:f392fc9709a3 | 4127 | return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4128 | } |
| AnnaBridge | 189:f392fc9709a3 | 4129 | |
| AnnaBridge | 189:f392fc9709a3 | 4130 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4131 | * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). |
| AnnaBridge | 189:f392fc9709a3 | 4132 | * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 |
| AnnaBridge | 189:f392fc9709a3 | 4133 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4134 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4135 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4136 | __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4137 | { |
| AnnaBridge | 189:f392fc9709a3 | 4138 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4139 | } |
| AnnaBridge | 189:f392fc9709a3 | 4140 | |
| AnnaBridge | 189:f392fc9709a3 | 4141 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4142 | * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4143 | * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 |
| AnnaBridge | 189:f392fc9709a3 | 4144 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4145 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4146 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4147 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4148 | { |
| AnnaBridge | 189:f392fc9709a3 | 4149 | return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4150 | } |
| AnnaBridge | 189:f392fc9709a3 | 4151 | |
| AnnaBridge | 189:f392fc9709a3 | 4152 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4153 | * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). |
| AnnaBridge | 189:f392fc9709a3 | 4154 | * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 |
| AnnaBridge | 189:f392fc9709a3 | 4155 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4156 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4157 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4158 | __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4159 | { |
| AnnaBridge | 189:f392fc9709a3 | 4160 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4161 | } |
| AnnaBridge | 189:f392fc9709a3 | 4162 | |
| AnnaBridge | 189:f392fc9709a3 | 4163 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4164 | * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4165 | * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 |
| AnnaBridge | 189:f392fc9709a3 | 4166 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4167 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4168 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4169 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4170 | { |
| AnnaBridge | 189:f392fc9709a3 | 4171 | return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4172 | } |
| AnnaBridge | 189:f392fc9709a3 | 4173 | |
| AnnaBridge | 189:f392fc9709a3 | 4174 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4175 | * @brief Clear the commutation interrupt flag (COMIF). |
| AnnaBridge | 189:f392fc9709a3 | 4176 | * @rmtoll SR COMIF LL_TIM_ClearFlag_COM |
| AnnaBridge | 189:f392fc9709a3 | 4177 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4178 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4179 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4180 | __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4181 | { |
| AnnaBridge | 189:f392fc9709a3 | 4182 | WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); |
| AnnaBridge | 189:f392fc9709a3 | 4183 | } |
| AnnaBridge | 189:f392fc9709a3 | 4184 | |
| AnnaBridge | 189:f392fc9709a3 | 4185 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4186 | * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4187 | * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM |
| AnnaBridge | 189:f392fc9709a3 | 4188 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4189 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4190 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4191 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4192 | { |
| AnnaBridge | 189:f392fc9709a3 | 4193 | return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)); |
| AnnaBridge | 189:f392fc9709a3 | 4194 | } |
| AnnaBridge | 189:f392fc9709a3 | 4195 | |
| AnnaBridge | 189:f392fc9709a3 | 4196 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4197 | * @brief Clear the trigger interrupt flag (TIF). |
| AnnaBridge | 189:f392fc9709a3 | 4198 | * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG |
| AnnaBridge | 189:f392fc9709a3 | 4199 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4200 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4201 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4202 | __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4203 | { |
| AnnaBridge | 189:f392fc9709a3 | 4204 | WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); |
| AnnaBridge | 189:f392fc9709a3 | 4205 | } |
| AnnaBridge | 189:f392fc9709a3 | 4206 | |
| AnnaBridge | 189:f392fc9709a3 | 4207 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4208 | * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4209 | * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG |
| AnnaBridge | 189:f392fc9709a3 | 4210 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4211 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4212 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4213 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4214 | { |
| AnnaBridge | 189:f392fc9709a3 | 4215 | return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)); |
| AnnaBridge | 189:f392fc9709a3 | 4216 | } |
| AnnaBridge | 189:f392fc9709a3 | 4217 | |
| AnnaBridge | 189:f392fc9709a3 | 4218 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4219 | * @brief Clear the break interrupt flag (BIF). |
| AnnaBridge | 189:f392fc9709a3 | 4220 | * @rmtoll SR BIF LL_TIM_ClearFlag_BRK |
| AnnaBridge | 189:f392fc9709a3 | 4221 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4222 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4223 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4224 | __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4225 | { |
| AnnaBridge | 189:f392fc9709a3 | 4226 | WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); |
| AnnaBridge | 189:f392fc9709a3 | 4227 | } |
| AnnaBridge | 189:f392fc9709a3 | 4228 | |
| AnnaBridge | 189:f392fc9709a3 | 4229 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4230 | * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4231 | * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK |
| AnnaBridge | 189:f392fc9709a3 | 4232 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4233 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4234 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4235 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4236 | { |
| AnnaBridge | 189:f392fc9709a3 | 4237 | return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)); |
| AnnaBridge | 189:f392fc9709a3 | 4238 | } |
| AnnaBridge | 189:f392fc9709a3 | 4239 | |
| AnnaBridge | 189:f392fc9709a3 | 4240 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4241 | * @brief Clear the break 2 interrupt flag (B2IF). |
| AnnaBridge | 189:f392fc9709a3 | 4242 | * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 |
| AnnaBridge | 189:f392fc9709a3 | 4243 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4244 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4245 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4246 | __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4247 | { |
| AnnaBridge | 189:f392fc9709a3 | 4248 | WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4249 | } |
| AnnaBridge | 189:f392fc9709a3 | 4250 | |
| AnnaBridge | 189:f392fc9709a3 | 4251 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4252 | * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4253 | * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 |
| AnnaBridge | 189:f392fc9709a3 | 4254 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4255 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4256 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4257 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4258 | { |
| AnnaBridge | 189:f392fc9709a3 | 4259 | return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)); |
| AnnaBridge | 189:f392fc9709a3 | 4260 | } |
| AnnaBridge | 189:f392fc9709a3 | 4261 | |
| AnnaBridge | 189:f392fc9709a3 | 4262 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4263 | * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). |
| AnnaBridge | 189:f392fc9709a3 | 4264 | * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR |
| AnnaBridge | 189:f392fc9709a3 | 4265 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4266 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4267 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4268 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4269 | { |
| AnnaBridge | 189:f392fc9709a3 | 4270 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); |
| AnnaBridge | 189:f392fc9709a3 | 4271 | } |
| AnnaBridge | 189:f392fc9709a3 | 4272 | |
| AnnaBridge | 189:f392fc9709a3 | 4273 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4274 | * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4275 | * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR |
| AnnaBridge | 189:f392fc9709a3 | 4276 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4277 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4278 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4279 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4280 | { |
| AnnaBridge | 189:f392fc9709a3 | 4281 | return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)); |
| AnnaBridge | 189:f392fc9709a3 | 4282 | } |
| AnnaBridge | 189:f392fc9709a3 | 4283 | |
| AnnaBridge | 189:f392fc9709a3 | 4284 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4285 | * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). |
| AnnaBridge | 189:f392fc9709a3 | 4286 | * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR |
| AnnaBridge | 189:f392fc9709a3 | 4287 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4288 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4289 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4290 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4291 | { |
| AnnaBridge | 189:f392fc9709a3 | 4292 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); |
| AnnaBridge | 189:f392fc9709a3 | 4293 | } |
| AnnaBridge | 189:f392fc9709a3 | 4294 | |
| AnnaBridge | 189:f392fc9709a3 | 4295 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4296 | * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4297 | * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR |
| AnnaBridge | 189:f392fc9709a3 | 4298 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4299 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4300 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4301 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4302 | { |
| AnnaBridge | 189:f392fc9709a3 | 4303 | return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)); |
| AnnaBridge | 189:f392fc9709a3 | 4304 | } |
| AnnaBridge | 189:f392fc9709a3 | 4305 | |
| AnnaBridge | 189:f392fc9709a3 | 4306 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4307 | * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). |
| AnnaBridge | 189:f392fc9709a3 | 4308 | * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR |
| AnnaBridge | 189:f392fc9709a3 | 4309 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4310 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4311 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4312 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4313 | { |
| AnnaBridge | 189:f392fc9709a3 | 4314 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); |
| AnnaBridge | 189:f392fc9709a3 | 4315 | } |
| AnnaBridge | 189:f392fc9709a3 | 4316 | |
| AnnaBridge | 189:f392fc9709a3 | 4317 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4318 | * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4319 | * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR |
| AnnaBridge | 189:f392fc9709a3 | 4320 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4321 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4322 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4323 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4324 | { |
| AnnaBridge | 189:f392fc9709a3 | 4325 | return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)); |
| AnnaBridge | 189:f392fc9709a3 | 4326 | } |
| AnnaBridge | 189:f392fc9709a3 | 4327 | |
| AnnaBridge | 189:f392fc9709a3 | 4328 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4329 | * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). |
| AnnaBridge | 189:f392fc9709a3 | 4330 | * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR |
| AnnaBridge | 189:f392fc9709a3 | 4331 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4332 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4333 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4334 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4335 | { |
| AnnaBridge | 189:f392fc9709a3 | 4336 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); |
| AnnaBridge | 189:f392fc9709a3 | 4337 | } |
| AnnaBridge | 189:f392fc9709a3 | 4338 | |
| AnnaBridge | 189:f392fc9709a3 | 4339 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4340 | * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4341 | * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR |
| AnnaBridge | 189:f392fc9709a3 | 4342 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4343 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4344 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4345 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4346 | { |
| AnnaBridge | 189:f392fc9709a3 | 4347 | return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)); |
| AnnaBridge | 189:f392fc9709a3 | 4348 | } |
| AnnaBridge | 189:f392fc9709a3 | 4349 | |
| AnnaBridge | 189:f392fc9709a3 | 4350 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4351 | * @brief Clear the system break interrupt flag (SBIF). |
| AnnaBridge | 189:f392fc9709a3 | 4352 | * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK |
| AnnaBridge | 189:f392fc9709a3 | 4353 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4354 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4355 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4356 | __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4357 | { |
| AnnaBridge | 189:f392fc9709a3 | 4358 | WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); |
| AnnaBridge | 189:f392fc9709a3 | 4359 | } |
| AnnaBridge | 189:f392fc9709a3 | 4360 | |
| AnnaBridge | 189:f392fc9709a3 | 4361 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4362 | * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). |
| AnnaBridge | 189:f392fc9709a3 | 4363 | * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK |
| AnnaBridge | 189:f392fc9709a3 | 4364 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4365 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4366 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4367 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4368 | { |
| AnnaBridge | 189:f392fc9709a3 | 4369 | return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)); |
| AnnaBridge | 189:f392fc9709a3 | 4370 | } |
| AnnaBridge | 189:f392fc9709a3 | 4371 | |
| AnnaBridge | 189:f392fc9709a3 | 4372 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4373 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 4374 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4375 | |
| AnnaBridge | 189:f392fc9709a3 | 4376 | /** @defgroup TIM_LL_EF_IT_Management IT-Management |
| AnnaBridge | 189:f392fc9709a3 | 4377 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 4378 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4379 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4380 | * @brief Enable update interrupt (UIE). |
| AnnaBridge | 189:f392fc9709a3 | 4381 | * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE |
| AnnaBridge | 189:f392fc9709a3 | 4382 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4383 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4384 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4385 | __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4386 | { |
| AnnaBridge | 189:f392fc9709a3 | 4387 | SET_BIT(TIMx->DIER, TIM_DIER_UIE); |
| AnnaBridge | 189:f392fc9709a3 | 4388 | } |
| AnnaBridge | 189:f392fc9709a3 | 4389 | |
| AnnaBridge | 189:f392fc9709a3 | 4390 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4391 | * @brief Disable update interrupt (UIE). |
| AnnaBridge | 189:f392fc9709a3 | 4392 | * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE |
| AnnaBridge | 189:f392fc9709a3 | 4393 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4394 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4395 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4396 | __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4397 | { |
| AnnaBridge | 189:f392fc9709a3 | 4398 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); |
| AnnaBridge | 189:f392fc9709a3 | 4399 | } |
| AnnaBridge | 189:f392fc9709a3 | 4400 | |
| AnnaBridge | 189:f392fc9709a3 | 4401 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4402 | * @brief Indicates whether the update interrupt (UIE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4403 | * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE |
| AnnaBridge | 189:f392fc9709a3 | 4404 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4405 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4406 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4407 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4408 | { |
| AnnaBridge | 189:f392fc9709a3 | 4409 | return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)); |
| AnnaBridge | 189:f392fc9709a3 | 4410 | } |
| AnnaBridge | 189:f392fc9709a3 | 4411 | |
| AnnaBridge | 189:f392fc9709a3 | 4412 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4413 | * @brief Enable capture/compare 1 interrupt (CC1IE). |
| AnnaBridge | 189:f392fc9709a3 | 4414 | * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 |
| AnnaBridge | 189:f392fc9709a3 | 4415 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4416 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4417 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4418 | __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4419 | { |
| AnnaBridge | 189:f392fc9709a3 | 4420 | SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
| AnnaBridge | 189:f392fc9709a3 | 4421 | } |
| AnnaBridge | 189:f392fc9709a3 | 4422 | |
| AnnaBridge | 189:f392fc9709a3 | 4423 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4424 | * @brief Disable capture/compare 1 interrupt (CC1IE). |
| AnnaBridge | 189:f392fc9709a3 | 4425 | * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 |
| AnnaBridge | 189:f392fc9709a3 | 4426 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4427 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4428 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4429 | __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4430 | { |
| AnnaBridge | 189:f392fc9709a3 | 4431 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
| AnnaBridge | 189:f392fc9709a3 | 4432 | } |
| AnnaBridge | 189:f392fc9709a3 | 4433 | |
| AnnaBridge | 189:f392fc9709a3 | 4434 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4435 | * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4436 | * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 |
| AnnaBridge | 189:f392fc9709a3 | 4437 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4438 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4439 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4440 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4441 | { |
| AnnaBridge | 189:f392fc9709a3 | 4442 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)); |
| AnnaBridge | 189:f392fc9709a3 | 4443 | } |
| AnnaBridge | 189:f392fc9709a3 | 4444 | |
| AnnaBridge | 189:f392fc9709a3 | 4445 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4446 | * @brief Enable capture/compare 2 interrupt (CC2IE). |
| AnnaBridge | 189:f392fc9709a3 | 4447 | * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 |
| AnnaBridge | 189:f392fc9709a3 | 4448 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4449 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4450 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4451 | __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4452 | { |
| AnnaBridge | 189:f392fc9709a3 | 4453 | SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
| AnnaBridge | 189:f392fc9709a3 | 4454 | } |
| AnnaBridge | 189:f392fc9709a3 | 4455 | |
| AnnaBridge | 189:f392fc9709a3 | 4456 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4457 | * @brief Disable capture/compare 2 interrupt (CC2IE). |
| AnnaBridge | 189:f392fc9709a3 | 4458 | * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 |
| AnnaBridge | 189:f392fc9709a3 | 4459 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4460 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4461 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4462 | __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4463 | { |
| AnnaBridge | 189:f392fc9709a3 | 4464 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
| AnnaBridge | 189:f392fc9709a3 | 4465 | } |
| AnnaBridge | 189:f392fc9709a3 | 4466 | |
| AnnaBridge | 189:f392fc9709a3 | 4467 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4468 | * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4469 | * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 |
| AnnaBridge | 189:f392fc9709a3 | 4470 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4471 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4472 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4473 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4474 | { |
| AnnaBridge | 189:f392fc9709a3 | 4475 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)); |
| AnnaBridge | 189:f392fc9709a3 | 4476 | } |
| AnnaBridge | 189:f392fc9709a3 | 4477 | |
| AnnaBridge | 189:f392fc9709a3 | 4478 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4479 | * @brief Enable capture/compare 3 interrupt (CC3IE). |
| AnnaBridge | 189:f392fc9709a3 | 4480 | * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 |
| AnnaBridge | 189:f392fc9709a3 | 4481 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4482 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4483 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4484 | __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4485 | { |
| AnnaBridge | 189:f392fc9709a3 | 4486 | SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
| AnnaBridge | 189:f392fc9709a3 | 4487 | } |
| AnnaBridge | 189:f392fc9709a3 | 4488 | |
| AnnaBridge | 189:f392fc9709a3 | 4489 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4490 | * @brief Disable capture/compare 3 interrupt (CC3IE). |
| AnnaBridge | 189:f392fc9709a3 | 4491 | * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 |
| AnnaBridge | 189:f392fc9709a3 | 4492 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4493 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4494 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4495 | __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4496 | { |
| AnnaBridge | 189:f392fc9709a3 | 4497 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
| AnnaBridge | 189:f392fc9709a3 | 4498 | } |
| AnnaBridge | 189:f392fc9709a3 | 4499 | |
| AnnaBridge | 189:f392fc9709a3 | 4500 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4501 | * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4502 | * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 |
| AnnaBridge | 189:f392fc9709a3 | 4503 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4504 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4505 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4506 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4507 | { |
| AnnaBridge | 189:f392fc9709a3 | 4508 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)); |
| AnnaBridge | 189:f392fc9709a3 | 4509 | } |
| AnnaBridge | 189:f392fc9709a3 | 4510 | |
| AnnaBridge | 189:f392fc9709a3 | 4511 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4512 | * @brief Enable capture/compare 4 interrupt (CC4IE). |
| AnnaBridge | 189:f392fc9709a3 | 4513 | * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 |
| AnnaBridge | 189:f392fc9709a3 | 4514 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4515 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4516 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4517 | __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4518 | { |
| AnnaBridge | 189:f392fc9709a3 | 4519 | SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
| AnnaBridge | 189:f392fc9709a3 | 4520 | } |
| AnnaBridge | 189:f392fc9709a3 | 4521 | |
| AnnaBridge | 189:f392fc9709a3 | 4522 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4523 | * @brief Disable capture/compare 4 interrupt (CC4IE). |
| AnnaBridge | 189:f392fc9709a3 | 4524 | * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 |
| AnnaBridge | 189:f392fc9709a3 | 4525 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4526 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4527 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4528 | __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4529 | { |
| AnnaBridge | 189:f392fc9709a3 | 4530 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
| AnnaBridge | 189:f392fc9709a3 | 4531 | } |
| AnnaBridge | 189:f392fc9709a3 | 4532 | |
| AnnaBridge | 189:f392fc9709a3 | 4533 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4534 | * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4535 | * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 |
| AnnaBridge | 189:f392fc9709a3 | 4536 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4537 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4538 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4539 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4540 | { |
| AnnaBridge | 189:f392fc9709a3 | 4541 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)); |
| AnnaBridge | 189:f392fc9709a3 | 4542 | } |
| AnnaBridge | 189:f392fc9709a3 | 4543 | |
| AnnaBridge | 189:f392fc9709a3 | 4544 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4545 | * @brief Enable commutation interrupt (COMIE). |
| AnnaBridge | 189:f392fc9709a3 | 4546 | * @rmtoll DIER COMIE LL_TIM_EnableIT_COM |
| AnnaBridge | 189:f392fc9709a3 | 4547 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4548 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4549 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4550 | __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4551 | { |
| AnnaBridge | 189:f392fc9709a3 | 4552 | SET_BIT(TIMx->DIER, TIM_DIER_COMIE); |
| AnnaBridge | 189:f392fc9709a3 | 4553 | } |
| AnnaBridge | 189:f392fc9709a3 | 4554 | |
| AnnaBridge | 189:f392fc9709a3 | 4555 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4556 | * @brief Disable commutation interrupt (COMIE). |
| AnnaBridge | 189:f392fc9709a3 | 4557 | * @rmtoll DIER COMIE LL_TIM_DisableIT_COM |
| AnnaBridge | 189:f392fc9709a3 | 4558 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4559 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4560 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4561 | __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4562 | { |
| AnnaBridge | 189:f392fc9709a3 | 4563 | CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); |
| AnnaBridge | 189:f392fc9709a3 | 4564 | } |
| AnnaBridge | 189:f392fc9709a3 | 4565 | |
| AnnaBridge | 189:f392fc9709a3 | 4566 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4567 | * @brief Indicates whether the commutation interrupt (COMIE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4568 | * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM |
| AnnaBridge | 189:f392fc9709a3 | 4569 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4570 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4571 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4572 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4573 | { |
| AnnaBridge | 189:f392fc9709a3 | 4574 | return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)); |
| AnnaBridge | 189:f392fc9709a3 | 4575 | } |
| AnnaBridge | 189:f392fc9709a3 | 4576 | |
| AnnaBridge | 189:f392fc9709a3 | 4577 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4578 | * @brief Enable trigger interrupt (TIE). |
| AnnaBridge | 189:f392fc9709a3 | 4579 | * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG |
| AnnaBridge | 189:f392fc9709a3 | 4580 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4581 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4582 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4583 | __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4584 | { |
| AnnaBridge | 189:f392fc9709a3 | 4585 | SET_BIT(TIMx->DIER, TIM_DIER_TIE); |
| AnnaBridge | 189:f392fc9709a3 | 4586 | } |
| AnnaBridge | 189:f392fc9709a3 | 4587 | |
| AnnaBridge | 189:f392fc9709a3 | 4588 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4589 | * @brief Disable trigger interrupt (TIE). |
| AnnaBridge | 189:f392fc9709a3 | 4590 | * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG |
| AnnaBridge | 189:f392fc9709a3 | 4591 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4592 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4593 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4594 | __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4595 | { |
| AnnaBridge | 189:f392fc9709a3 | 4596 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); |
| AnnaBridge | 189:f392fc9709a3 | 4597 | } |
| AnnaBridge | 189:f392fc9709a3 | 4598 | |
| AnnaBridge | 189:f392fc9709a3 | 4599 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4600 | * @brief Indicates whether the trigger interrupt (TIE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4601 | * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG |
| AnnaBridge | 189:f392fc9709a3 | 4602 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4603 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4604 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4605 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4606 | { |
| AnnaBridge | 189:f392fc9709a3 | 4607 | return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)); |
| AnnaBridge | 189:f392fc9709a3 | 4608 | } |
| AnnaBridge | 189:f392fc9709a3 | 4609 | |
| AnnaBridge | 189:f392fc9709a3 | 4610 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4611 | * @brief Enable break interrupt (BIE). |
| AnnaBridge | 189:f392fc9709a3 | 4612 | * @rmtoll DIER BIE LL_TIM_EnableIT_BRK |
| AnnaBridge | 189:f392fc9709a3 | 4613 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4614 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4615 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4616 | __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4617 | { |
| AnnaBridge | 189:f392fc9709a3 | 4618 | SET_BIT(TIMx->DIER, TIM_DIER_BIE); |
| AnnaBridge | 189:f392fc9709a3 | 4619 | } |
| AnnaBridge | 189:f392fc9709a3 | 4620 | |
| AnnaBridge | 189:f392fc9709a3 | 4621 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4622 | * @brief Disable break interrupt (BIE). |
| AnnaBridge | 189:f392fc9709a3 | 4623 | * @rmtoll DIER BIE LL_TIM_DisableIT_BRK |
| AnnaBridge | 189:f392fc9709a3 | 4624 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4625 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4626 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4627 | __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4628 | { |
| AnnaBridge | 189:f392fc9709a3 | 4629 | CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); |
| AnnaBridge | 189:f392fc9709a3 | 4630 | } |
| AnnaBridge | 189:f392fc9709a3 | 4631 | |
| AnnaBridge | 189:f392fc9709a3 | 4632 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4633 | * @brief Indicates whether the break interrupt (BIE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4634 | * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK |
| AnnaBridge | 189:f392fc9709a3 | 4635 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4636 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4637 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4638 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4639 | { |
| AnnaBridge | 189:f392fc9709a3 | 4640 | return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)); |
| AnnaBridge | 189:f392fc9709a3 | 4641 | } |
| AnnaBridge | 189:f392fc9709a3 | 4642 | |
| AnnaBridge | 189:f392fc9709a3 | 4643 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4644 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 4645 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4646 | |
| AnnaBridge | 189:f392fc9709a3 | 4647 | /** @defgroup TIM_LL_EF_DMA_Management DMA-Management |
| AnnaBridge | 189:f392fc9709a3 | 4648 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 4649 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4650 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4651 | * @brief Enable update DMA request (UDE). |
| AnnaBridge | 189:f392fc9709a3 | 4652 | * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE |
| AnnaBridge | 189:f392fc9709a3 | 4653 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4654 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4655 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4656 | __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4657 | { |
| AnnaBridge | 189:f392fc9709a3 | 4658 | SET_BIT(TIMx->DIER, TIM_DIER_UDE); |
| AnnaBridge | 189:f392fc9709a3 | 4659 | } |
| AnnaBridge | 189:f392fc9709a3 | 4660 | |
| AnnaBridge | 189:f392fc9709a3 | 4661 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4662 | * @brief Disable update DMA request (UDE). |
| AnnaBridge | 189:f392fc9709a3 | 4663 | * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE |
| AnnaBridge | 189:f392fc9709a3 | 4664 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4665 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4666 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4667 | __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4668 | { |
| AnnaBridge | 189:f392fc9709a3 | 4669 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); |
| AnnaBridge | 189:f392fc9709a3 | 4670 | } |
| AnnaBridge | 189:f392fc9709a3 | 4671 | |
| AnnaBridge | 189:f392fc9709a3 | 4672 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4673 | * @brief Indicates whether the update DMA request (UDE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4674 | * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE |
| AnnaBridge | 189:f392fc9709a3 | 4675 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4676 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4677 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4678 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4679 | { |
| AnnaBridge | 189:f392fc9709a3 | 4680 | return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)); |
| AnnaBridge | 189:f392fc9709a3 | 4681 | } |
| AnnaBridge | 189:f392fc9709a3 | 4682 | |
| AnnaBridge | 189:f392fc9709a3 | 4683 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4684 | * @brief Enable capture/compare 1 DMA request (CC1DE). |
| AnnaBridge | 189:f392fc9709a3 | 4685 | * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 |
| AnnaBridge | 189:f392fc9709a3 | 4686 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4687 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4688 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4689 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4690 | { |
| AnnaBridge | 189:f392fc9709a3 | 4691 | SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
| AnnaBridge | 189:f392fc9709a3 | 4692 | } |
| AnnaBridge | 189:f392fc9709a3 | 4693 | |
| AnnaBridge | 189:f392fc9709a3 | 4694 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4695 | * @brief Disable capture/compare 1 DMA request (CC1DE). |
| AnnaBridge | 189:f392fc9709a3 | 4696 | * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 |
| AnnaBridge | 189:f392fc9709a3 | 4697 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4698 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4699 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4700 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4701 | { |
| AnnaBridge | 189:f392fc9709a3 | 4702 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
| AnnaBridge | 189:f392fc9709a3 | 4703 | } |
| AnnaBridge | 189:f392fc9709a3 | 4704 | |
| AnnaBridge | 189:f392fc9709a3 | 4705 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4706 | * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4707 | * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 |
| AnnaBridge | 189:f392fc9709a3 | 4708 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4709 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4710 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4711 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4712 | { |
| AnnaBridge | 189:f392fc9709a3 | 4713 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)); |
| AnnaBridge | 189:f392fc9709a3 | 4714 | } |
| AnnaBridge | 189:f392fc9709a3 | 4715 | |
| AnnaBridge | 189:f392fc9709a3 | 4716 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4717 | * @brief Enable capture/compare 2 DMA request (CC2DE). |
| AnnaBridge | 189:f392fc9709a3 | 4718 | * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 |
| AnnaBridge | 189:f392fc9709a3 | 4719 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4720 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4721 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4722 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4723 | { |
| AnnaBridge | 189:f392fc9709a3 | 4724 | SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
| AnnaBridge | 189:f392fc9709a3 | 4725 | } |
| AnnaBridge | 189:f392fc9709a3 | 4726 | |
| AnnaBridge | 189:f392fc9709a3 | 4727 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4728 | * @brief Disable capture/compare 2 DMA request (CC2DE). |
| AnnaBridge | 189:f392fc9709a3 | 4729 | * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 |
| AnnaBridge | 189:f392fc9709a3 | 4730 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4731 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4732 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4733 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4734 | { |
| AnnaBridge | 189:f392fc9709a3 | 4735 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
| AnnaBridge | 189:f392fc9709a3 | 4736 | } |
| AnnaBridge | 189:f392fc9709a3 | 4737 | |
| AnnaBridge | 189:f392fc9709a3 | 4738 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4739 | * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4740 | * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 |
| AnnaBridge | 189:f392fc9709a3 | 4741 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4742 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4743 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4744 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4745 | { |
| AnnaBridge | 189:f392fc9709a3 | 4746 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)); |
| AnnaBridge | 189:f392fc9709a3 | 4747 | } |
| AnnaBridge | 189:f392fc9709a3 | 4748 | |
| AnnaBridge | 189:f392fc9709a3 | 4749 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4750 | * @brief Enable capture/compare 3 DMA request (CC3DE). |
| AnnaBridge | 189:f392fc9709a3 | 4751 | * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 |
| AnnaBridge | 189:f392fc9709a3 | 4752 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4753 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4754 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4755 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4756 | { |
| AnnaBridge | 189:f392fc9709a3 | 4757 | SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
| AnnaBridge | 189:f392fc9709a3 | 4758 | } |
| AnnaBridge | 189:f392fc9709a3 | 4759 | |
| AnnaBridge | 189:f392fc9709a3 | 4760 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4761 | * @brief Disable capture/compare 3 DMA request (CC3DE). |
| AnnaBridge | 189:f392fc9709a3 | 4762 | * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 |
| AnnaBridge | 189:f392fc9709a3 | 4763 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4764 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4765 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4766 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4767 | { |
| AnnaBridge | 189:f392fc9709a3 | 4768 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
| AnnaBridge | 189:f392fc9709a3 | 4769 | } |
| AnnaBridge | 189:f392fc9709a3 | 4770 | |
| AnnaBridge | 189:f392fc9709a3 | 4771 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4772 | * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4773 | * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 |
| AnnaBridge | 189:f392fc9709a3 | 4774 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4775 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4776 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4777 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4778 | { |
| AnnaBridge | 189:f392fc9709a3 | 4779 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)); |
| AnnaBridge | 189:f392fc9709a3 | 4780 | } |
| AnnaBridge | 189:f392fc9709a3 | 4781 | |
| AnnaBridge | 189:f392fc9709a3 | 4782 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4783 | * @brief Enable capture/compare 4 DMA request (CC4DE). |
| AnnaBridge | 189:f392fc9709a3 | 4784 | * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 |
| AnnaBridge | 189:f392fc9709a3 | 4785 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4786 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4787 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4788 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4789 | { |
| AnnaBridge | 189:f392fc9709a3 | 4790 | SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
| AnnaBridge | 189:f392fc9709a3 | 4791 | } |
| AnnaBridge | 189:f392fc9709a3 | 4792 | |
| AnnaBridge | 189:f392fc9709a3 | 4793 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4794 | * @brief Disable capture/compare 4 DMA request (CC4DE). |
| AnnaBridge | 189:f392fc9709a3 | 4795 | * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 |
| AnnaBridge | 189:f392fc9709a3 | 4796 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4797 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4798 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4799 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4800 | { |
| AnnaBridge | 189:f392fc9709a3 | 4801 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
| AnnaBridge | 189:f392fc9709a3 | 4802 | } |
| AnnaBridge | 189:f392fc9709a3 | 4803 | |
| AnnaBridge | 189:f392fc9709a3 | 4804 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4805 | * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4806 | * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 |
| AnnaBridge | 189:f392fc9709a3 | 4807 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4808 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4809 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4810 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4811 | { |
| AnnaBridge | 189:f392fc9709a3 | 4812 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)); |
| AnnaBridge | 189:f392fc9709a3 | 4813 | } |
| AnnaBridge | 189:f392fc9709a3 | 4814 | |
| AnnaBridge | 189:f392fc9709a3 | 4815 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4816 | * @brief Enable commutation DMA request (COMDE). |
| AnnaBridge | 189:f392fc9709a3 | 4817 | * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM |
| AnnaBridge | 189:f392fc9709a3 | 4818 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4819 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4820 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4821 | __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4822 | { |
| AnnaBridge | 189:f392fc9709a3 | 4823 | SET_BIT(TIMx->DIER, TIM_DIER_COMDE); |
| AnnaBridge | 189:f392fc9709a3 | 4824 | } |
| AnnaBridge | 189:f392fc9709a3 | 4825 | |
| AnnaBridge | 189:f392fc9709a3 | 4826 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4827 | * @brief Disable commutation DMA request (COMDE). |
| AnnaBridge | 189:f392fc9709a3 | 4828 | * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM |
| AnnaBridge | 189:f392fc9709a3 | 4829 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4830 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4831 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4832 | __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4833 | { |
| AnnaBridge | 189:f392fc9709a3 | 4834 | CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); |
| AnnaBridge | 189:f392fc9709a3 | 4835 | } |
| AnnaBridge | 189:f392fc9709a3 | 4836 | |
| AnnaBridge | 189:f392fc9709a3 | 4837 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4838 | * @brief Indicates whether the commutation DMA request (COMDE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4839 | * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM |
| AnnaBridge | 189:f392fc9709a3 | 4840 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4841 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4842 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4843 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4844 | { |
| AnnaBridge | 189:f392fc9709a3 | 4845 | return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)); |
| AnnaBridge | 189:f392fc9709a3 | 4846 | } |
| AnnaBridge | 189:f392fc9709a3 | 4847 | |
| AnnaBridge | 189:f392fc9709a3 | 4848 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4849 | * @brief Enable trigger interrupt (TDE). |
| AnnaBridge | 189:f392fc9709a3 | 4850 | * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG |
| AnnaBridge | 189:f392fc9709a3 | 4851 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4852 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4853 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4854 | __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4855 | { |
| AnnaBridge | 189:f392fc9709a3 | 4856 | SET_BIT(TIMx->DIER, TIM_DIER_TDE); |
| AnnaBridge | 189:f392fc9709a3 | 4857 | } |
| AnnaBridge | 189:f392fc9709a3 | 4858 | |
| AnnaBridge | 189:f392fc9709a3 | 4859 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4860 | * @brief Disable trigger interrupt (TDE). |
| AnnaBridge | 189:f392fc9709a3 | 4861 | * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG |
| AnnaBridge | 189:f392fc9709a3 | 4862 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4863 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4864 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4865 | __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4866 | { |
| AnnaBridge | 189:f392fc9709a3 | 4867 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); |
| AnnaBridge | 189:f392fc9709a3 | 4868 | } |
| AnnaBridge | 189:f392fc9709a3 | 4869 | |
| AnnaBridge | 189:f392fc9709a3 | 4870 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4871 | * @brief Indicates whether the trigger interrupt (TDE) is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 4872 | * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG |
| AnnaBridge | 189:f392fc9709a3 | 4873 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4874 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 4875 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4876 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4877 | { |
| AnnaBridge | 189:f392fc9709a3 | 4878 | return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)); |
| AnnaBridge | 189:f392fc9709a3 | 4879 | } |
| AnnaBridge | 189:f392fc9709a3 | 4880 | |
| AnnaBridge | 189:f392fc9709a3 | 4881 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4882 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 4883 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4884 | |
| AnnaBridge | 189:f392fc9709a3 | 4885 | /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management |
| AnnaBridge | 189:f392fc9709a3 | 4886 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 4887 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4888 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4889 | * @brief Generate an update event. |
| AnnaBridge | 189:f392fc9709a3 | 4890 | * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE |
| AnnaBridge | 189:f392fc9709a3 | 4891 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4892 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4893 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4894 | __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4895 | { |
| AnnaBridge | 189:f392fc9709a3 | 4896 | SET_BIT(TIMx->EGR, TIM_EGR_UG); |
| AnnaBridge | 189:f392fc9709a3 | 4897 | } |
| AnnaBridge | 189:f392fc9709a3 | 4898 | |
| AnnaBridge | 189:f392fc9709a3 | 4899 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4900 | * @brief Generate Capture/Compare 1 event. |
| AnnaBridge | 189:f392fc9709a3 | 4901 | * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 |
| AnnaBridge | 189:f392fc9709a3 | 4902 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4903 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4904 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4905 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4906 | { |
| AnnaBridge | 189:f392fc9709a3 | 4907 | SET_BIT(TIMx->EGR, TIM_EGR_CC1G); |
| AnnaBridge | 189:f392fc9709a3 | 4908 | } |
| AnnaBridge | 189:f392fc9709a3 | 4909 | |
| AnnaBridge | 189:f392fc9709a3 | 4910 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4911 | * @brief Generate Capture/Compare 2 event. |
| AnnaBridge | 189:f392fc9709a3 | 4912 | * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 |
| AnnaBridge | 189:f392fc9709a3 | 4913 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4914 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4915 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4916 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4917 | { |
| AnnaBridge | 189:f392fc9709a3 | 4918 | SET_BIT(TIMx->EGR, TIM_EGR_CC2G); |
| AnnaBridge | 189:f392fc9709a3 | 4919 | } |
| AnnaBridge | 189:f392fc9709a3 | 4920 | |
| AnnaBridge | 189:f392fc9709a3 | 4921 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4922 | * @brief Generate Capture/Compare 3 event. |
| AnnaBridge | 189:f392fc9709a3 | 4923 | * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 |
| AnnaBridge | 189:f392fc9709a3 | 4924 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4925 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4926 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4927 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4928 | { |
| AnnaBridge | 189:f392fc9709a3 | 4929 | SET_BIT(TIMx->EGR, TIM_EGR_CC3G); |
| AnnaBridge | 189:f392fc9709a3 | 4930 | } |
| AnnaBridge | 189:f392fc9709a3 | 4931 | |
| AnnaBridge | 189:f392fc9709a3 | 4932 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4933 | * @brief Generate Capture/Compare 4 event. |
| AnnaBridge | 189:f392fc9709a3 | 4934 | * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 |
| AnnaBridge | 189:f392fc9709a3 | 4935 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4936 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4937 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4938 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4939 | { |
| AnnaBridge | 189:f392fc9709a3 | 4940 | SET_BIT(TIMx->EGR, TIM_EGR_CC4G); |
| AnnaBridge | 189:f392fc9709a3 | 4941 | } |
| AnnaBridge | 189:f392fc9709a3 | 4942 | |
| AnnaBridge | 189:f392fc9709a3 | 4943 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4944 | * @brief Generate commutation event. |
| AnnaBridge | 189:f392fc9709a3 | 4945 | * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM |
| AnnaBridge | 189:f392fc9709a3 | 4946 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4947 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4948 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4949 | __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4950 | { |
| AnnaBridge | 189:f392fc9709a3 | 4951 | SET_BIT(TIMx->EGR, TIM_EGR_COMG); |
| AnnaBridge | 189:f392fc9709a3 | 4952 | } |
| AnnaBridge | 189:f392fc9709a3 | 4953 | |
| AnnaBridge | 189:f392fc9709a3 | 4954 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4955 | * @brief Generate trigger event. |
| AnnaBridge | 189:f392fc9709a3 | 4956 | * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG |
| AnnaBridge | 189:f392fc9709a3 | 4957 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4958 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4959 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4960 | __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4961 | { |
| AnnaBridge | 189:f392fc9709a3 | 4962 | SET_BIT(TIMx->EGR, TIM_EGR_TG); |
| AnnaBridge | 189:f392fc9709a3 | 4963 | } |
| AnnaBridge | 189:f392fc9709a3 | 4964 | |
| AnnaBridge | 189:f392fc9709a3 | 4965 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4966 | * @brief Generate break event. |
| AnnaBridge | 189:f392fc9709a3 | 4967 | * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK |
| AnnaBridge | 189:f392fc9709a3 | 4968 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4969 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4970 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4971 | __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4972 | { |
| AnnaBridge | 189:f392fc9709a3 | 4973 | SET_BIT(TIMx->EGR, TIM_EGR_BG); |
| AnnaBridge | 189:f392fc9709a3 | 4974 | } |
| AnnaBridge | 189:f392fc9709a3 | 4975 | |
| AnnaBridge | 189:f392fc9709a3 | 4976 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4977 | * @brief Generate break 2 event. |
| AnnaBridge | 189:f392fc9709a3 | 4978 | * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 |
| AnnaBridge | 189:f392fc9709a3 | 4979 | * @param TIMx Timer instance |
| AnnaBridge | 189:f392fc9709a3 | 4980 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 4981 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4982 | __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) |
| AnnaBridge | 189:f392fc9709a3 | 4983 | { |
| AnnaBridge | 189:f392fc9709a3 | 4984 | SET_BIT(TIMx->EGR, TIM_EGR_B2G); |
| AnnaBridge | 189:f392fc9709a3 | 4985 | } |
| AnnaBridge | 189:f392fc9709a3 | 4986 | |
| AnnaBridge | 189:f392fc9709a3 | 4987 | /** |
| AnnaBridge | 189:f392fc9709a3 | 4988 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 4989 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4990 | |
| AnnaBridge | 189:f392fc9709a3 | 4991 | #if defined(USE_FULL_LL_DRIVER) |
| AnnaBridge | 189:f392fc9709a3 | 4992 | /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions |
| AnnaBridge | 189:f392fc9709a3 | 4993 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 4994 | */ |
| AnnaBridge | 189:f392fc9709a3 | 4995 | |
| AnnaBridge | 189:f392fc9709a3 | 4996 | ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); |
| AnnaBridge | 189:f392fc9709a3 | 4997 | void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 4998 | ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 4999 | void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 5000 | ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 5001 | void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 5002 | ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 5003 | void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 5004 | ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 5005 | void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 5006 | ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 5007 | void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 5008 | ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 5009 | /** |
| AnnaBridge | 189:f392fc9709a3 | 5010 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 5011 | */ |
| AnnaBridge | 189:f392fc9709a3 | 5012 | #endif /* USE_FULL_LL_DRIVER */ |
| AnnaBridge | 189:f392fc9709a3 | 5013 | |
| AnnaBridge | 189:f392fc9709a3 | 5014 | /** |
| AnnaBridge | 189:f392fc9709a3 | 5015 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 5016 | */ |
| AnnaBridge | 189:f392fc9709a3 | 5017 | |
| AnnaBridge | 189:f392fc9709a3 | 5018 | /** |
| AnnaBridge | 189:f392fc9709a3 | 5019 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 5020 | */ |
| AnnaBridge | 189:f392fc9709a3 | 5021 | |
| AnnaBridge | 189:f392fc9709a3 | 5022 | #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */ |
| AnnaBridge | 189:f392fc9709a3 | 5023 | |
| AnnaBridge | 189:f392fc9709a3 | 5024 | /** |
| AnnaBridge | 189:f392fc9709a3 | 5025 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 5026 | */ |
| AnnaBridge | 189:f392fc9709a3 | 5027 | |
| AnnaBridge | 189:f392fc9709a3 | 5028 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 5029 | } |
| AnnaBridge | 189:f392fc9709a3 | 5030 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 5031 | |
| AnnaBridge | 189:f392fc9709a3 | 5032 | #endif /* __STM32L4xx_LL_TIM_H */ |
| AnnaBridge | 189:f392fc9709a3 | 5033 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
