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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_ARM_STD/stm32l4xx_ll_swpmi.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_ll_swpmi.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of SWPMI LL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_LL_SWPMI_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_LL_SWPMI_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l4xx.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32L4xx_LL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | #if defined (SWPMI1) |
| AnnaBridge | 189:f392fc9709a3 | 52 | |
| AnnaBridge | 189:f392fc9709a3 | 53 | /** @defgroup SWPMI_LL SWPMI |
| AnnaBridge | 189:f392fc9709a3 | 54 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 55 | */ |
| AnnaBridge | 189:f392fc9709a3 | 56 | |
| AnnaBridge | 189:f392fc9709a3 | 57 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 58 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 59 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 60 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 61 | #if defined(USE_FULL_LL_DRIVER) |
| AnnaBridge | 189:f392fc9709a3 | 62 | /** @defgroup SWPMI_LL_Private_Macros SWPMI Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 63 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 64 | */ |
| AnnaBridge | 189:f392fc9709a3 | 65 | /** |
| AnnaBridge | 189:f392fc9709a3 | 66 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 67 | */ |
| AnnaBridge | 189:f392fc9709a3 | 68 | #endif /*USE_FULL_LL_DRIVER*/ |
| AnnaBridge | 189:f392fc9709a3 | 69 | |
| AnnaBridge | 189:f392fc9709a3 | 70 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 71 | #if defined(USE_FULL_LL_DRIVER) |
| AnnaBridge | 189:f392fc9709a3 | 72 | /** @defgroup SWPMI_LL_ES_INIT SWPMI Exported Init structure |
| AnnaBridge | 189:f392fc9709a3 | 73 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 74 | */ |
| AnnaBridge | 189:f392fc9709a3 | 75 | |
| AnnaBridge | 189:f392fc9709a3 | 76 | /** |
| AnnaBridge | 189:f392fc9709a3 | 77 | * @brief SWPMI Init structures definition |
| AnnaBridge | 189:f392fc9709a3 | 78 | */ |
| AnnaBridge | 189:f392fc9709a3 | 79 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 80 | { |
| AnnaBridge | 189:f392fc9709a3 | 81 | uint32_t VoltageClass; /*!< Specifies the SWP Voltage Class. |
| AnnaBridge | 189:f392fc9709a3 | 82 | This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS |
| AnnaBridge | 189:f392fc9709a3 | 83 | |
| AnnaBridge | 189:f392fc9709a3 | 84 | This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */ |
| AnnaBridge | 189:f392fc9709a3 | 85 | |
| AnnaBridge | 189:f392fc9709a3 | 86 | uint32_t BitRatePrescaler; /*!< Specifies the SWPMI bitrate prescaler. |
| AnnaBridge | 189:f392fc9709a3 | 87 | This parameter must be a number between Min_Data=0 and Max_Data=63. |
| AnnaBridge | 189:f392fc9709a3 | 88 | |
| AnnaBridge | 189:f392fc9709a3 | 89 | The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER |
| AnnaBridge | 189:f392fc9709a3 | 90 | |
| AnnaBridge | 189:f392fc9709a3 | 91 | This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */ |
| AnnaBridge | 189:f392fc9709a3 | 92 | |
| AnnaBridge | 189:f392fc9709a3 | 93 | uint32_t TxBufferingMode; /*!< Specifies the transmission buffering mode. |
| AnnaBridge | 189:f392fc9709a3 | 94 | This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX |
| AnnaBridge | 189:f392fc9709a3 | 95 | |
| AnnaBridge | 189:f392fc9709a3 | 96 | This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */ |
| AnnaBridge | 189:f392fc9709a3 | 97 | |
| AnnaBridge | 189:f392fc9709a3 | 98 | uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode. |
| AnnaBridge | 189:f392fc9709a3 | 99 | This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX |
| AnnaBridge | 189:f392fc9709a3 | 100 | |
| AnnaBridge | 189:f392fc9709a3 | 101 | This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */ |
| AnnaBridge | 189:f392fc9709a3 | 102 | } LL_SWPMI_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 103 | |
| AnnaBridge | 189:f392fc9709a3 | 104 | /** |
| AnnaBridge | 189:f392fc9709a3 | 105 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 106 | */ |
| AnnaBridge | 189:f392fc9709a3 | 107 | #endif /* USE_FULL_LL_DRIVER */ |
| AnnaBridge | 189:f392fc9709a3 | 108 | |
| AnnaBridge | 189:f392fc9709a3 | 109 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 110 | /** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 111 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 112 | */ |
| AnnaBridge | 189:f392fc9709a3 | 113 | |
| AnnaBridge | 189:f392fc9709a3 | 114 | /** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines |
| AnnaBridge | 189:f392fc9709a3 | 115 | * @brief Flags defines which can be used with LL_SWPMI_WriteReg function |
| AnnaBridge | 189:f392fc9709a3 | 116 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 117 | */ |
| AnnaBridge | 189:f392fc9709a3 | 118 | #define LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF /*!< Clear receive buffer full flag */ |
| AnnaBridge | 189:f392fc9709a3 | 119 | #define LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF /*!< Clear transmit buffer empty flag */ |
| AnnaBridge | 189:f392fc9709a3 | 120 | #define LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF /*!< Clear receive CRC error flag */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | #define LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF /*!< Clear receive overrun error flag */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | #define LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF /*!< Clear transmit underrun error flag */ |
| AnnaBridge | 189:f392fc9709a3 | 123 | #define LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF /*!< Clear transfer complete flag */ |
| AnnaBridge | 189:f392fc9709a3 | 124 | #define LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF /*!< Clear slave resume flag */ |
| AnnaBridge | 189:f392fc9709a3 | 125 | /** |
| AnnaBridge | 189:f392fc9709a3 | 126 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 127 | */ |
| AnnaBridge | 189:f392fc9709a3 | 128 | |
| AnnaBridge | 189:f392fc9709a3 | 129 | /** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines |
| AnnaBridge | 189:f392fc9709a3 | 130 | * @brief Flags defines which can be used with LL_SWPMI_ReadReg function |
| AnnaBridge | 189:f392fc9709a3 | 131 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 132 | */ |
| AnnaBridge | 189:f392fc9709a3 | 133 | #define LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF /*!< Receive buffer full flag */ |
| AnnaBridge | 189:f392fc9709a3 | 134 | #define LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF /*!< Transmit buffer empty flag */ |
| AnnaBridge | 189:f392fc9709a3 | 135 | #define LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF /*!< Receive CRC error flag */ |
| AnnaBridge | 189:f392fc9709a3 | 136 | #define LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF /*!< Receive overrun error flag */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | #define LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF /*!< Transmit underrun error flag */ |
| AnnaBridge | 189:f392fc9709a3 | 138 | #define LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE /*!< Receive data register not empty */ |
| AnnaBridge | 189:f392fc9709a3 | 139 | #define LL_SWPMI_ISR_TXE SWPMI_ISR_TXE /*!< Transmit data register empty */ |
| AnnaBridge | 189:f392fc9709a3 | 140 | #define LL_SWPMI_ISR_TCF SWPMI_ISR_TCF /*!< Transfer complete flag */ |
| AnnaBridge | 189:f392fc9709a3 | 141 | #define LL_SWPMI_ISR_SRF SWPMI_ISR_SRF /*!< Slave resume flag */ |
| AnnaBridge | 189:f392fc9709a3 | 142 | #define LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP /*!< SUSPEND flag */ |
| AnnaBridge | 189:f392fc9709a3 | 143 | #define LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF /*!< DEACTIVATED flag */ |
| AnnaBridge | 189:f392fc9709a3 | 144 | /** |
| AnnaBridge | 189:f392fc9709a3 | 145 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 146 | */ |
| AnnaBridge | 189:f392fc9709a3 | 147 | |
| AnnaBridge | 189:f392fc9709a3 | 148 | /** @defgroup SWPMI_LL_EC_IT IT Defines |
| AnnaBridge | 189:f392fc9709a3 | 149 | * @brief IT defines which can be used with LL_SWPMI_ReadReg and LL_SWPMI_WriteReg functions |
| AnnaBridge | 189:f392fc9709a3 | 150 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 151 | */ |
| AnnaBridge | 189:f392fc9709a3 | 152 | #define LL_SWPMI_IER_SRIE SWPMI_IER_SRIE /*!< Slave resume interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 153 | #define LL_SWPMI_IER_TCIE SWPMI_IER_TCIE /*!< Transmit complete interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 154 | #define LL_SWPMI_IER_TIE SWPMI_IER_TIE /*!< Transmit interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 155 | #define LL_SWPMI_IER_RIE SWPMI_IER_RIE /*!< Receive interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 156 | #define LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE /*!< Transmit underrun error interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 157 | #define LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE /*!< Receive overrun error interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 158 | #define LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE /*!< Receive CRC error interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 159 | #define LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE /*!< Transmit buffer empty interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 160 | #define LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE /*!< Receive buffer full interrupt enable */ |
| AnnaBridge | 189:f392fc9709a3 | 161 | /** |
| AnnaBridge | 189:f392fc9709a3 | 162 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 163 | */ |
| AnnaBridge | 189:f392fc9709a3 | 164 | |
| AnnaBridge | 189:f392fc9709a3 | 165 | /** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX |
| AnnaBridge | 189:f392fc9709a3 | 166 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 167 | */ |
| AnnaBridge | 189:f392fc9709a3 | 168 | #define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for reception */ |
| AnnaBridge | 189:f392fc9709a3 | 169 | #define LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE /*!< Multi software buffermode for reception */ |
| AnnaBridge | 189:f392fc9709a3 | 170 | /** |
| AnnaBridge | 189:f392fc9709a3 | 171 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 172 | */ |
| AnnaBridge | 189:f392fc9709a3 | 173 | |
| AnnaBridge | 189:f392fc9709a3 | 174 | /** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX |
| AnnaBridge | 189:f392fc9709a3 | 175 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 176 | */ |
| AnnaBridge | 189:f392fc9709a3 | 177 | #define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for transmission */ |
| AnnaBridge | 189:f392fc9709a3 | 178 | #define LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE /*!< Multi software buffermode for transmission */ |
| AnnaBridge | 189:f392fc9709a3 | 179 | /** |
| AnnaBridge | 189:f392fc9709a3 | 180 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 181 | */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | |
| AnnaBridge | 189:f392fc9709a3 | 183 | /** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS |
| AnnaBridge | 189:f392fc9709a3 | 184 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 185 | */ |
| AnnaBridge | 189:f392fc9709a3 | 186 | #define LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000) /*!< SWPMI_IO uses directly VDD voltage to operate in class C */ |
| AnnaBridge | 189:f392fc9709a3 | 187 | #define LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS /*!< SWPMI_IO uses an internal voltage regulator to operate in class B */ |
| AnnaBridge | 189:f392fc9709a3 | 188 | /** |
| AnnaBridge | 189:f392fc9709a3 | 189 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 190 | */ |
| AnnaBridge | 189:f392fc9709a3 | 191 | |
| AnnaBridge | 189:f392fc9709a3 | 192 | /** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data |
| AnnaBridge | 189:f392fc9709a3 | 193 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 194 | */ |
| AnnaBridge | 189:f392fc9709a3 | 195 | #define LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0 /*!< Get address of data register used for transmission */ |
| AnnaBridge | 189:f392fc9709a3 | 196 | #define LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1 /*!< Get address of data register used for reception */ |
| AnnaBridge | 189:f392fc9709a3 | 197 | /** |
| AnnaBridge | 189:f392fc9709a3 | 198 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 199 | */ |
| AnnaBridge | 189:f392fc9709a3 | 200 | |
| AnnaBridge | 189:f392fc9709a3 | 201 | /** |
| AnnaBridge | 189:f392fc9709a3 | 202 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 203 | */ |
| AnnaBridge | 189:f392fc9709a3 | 204 | |
| AnnaBridge | 189:f392fc9709a3 | 205 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 206 | /** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 207 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 208 | */ |
| AnnaBridge | 189:f392fc9709a3 | 209 | |
| AnnaBridge | 189:f392fc9709a3 | 210 | /** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros |
| AnnaBridge | 189:f392fc9709a3 | 211 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 212 | */ |
| AnnaBridge | 189:f392fc9709a3 | 213 | |
| AnnaBridge | 189:f392fc9709a3 | 214 | /** |
| AnnaBridge | 189:f392fc9709a3 | 215 | * @brief Write a value in SWPMI register |
| AnnaBridge | 189:f392fc9709a3 | 216 | * @param __INSTANCE__ SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 217 | * @param __REG__ Register to be written |
| AnnaBridge | 189:f392fc9709a3 | 218 | * @param __VALUE__ Value to be written in the register |
| AnnaBridge | 189:f392fc9709a3 | 219 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 220 | */ |
| AnnaBridge | 189:f392fc9709a3 | 221 | #define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
| AnnaBridge | 189:f392fc9709a3 | 222 | |
| AnnaBridge | 189:f392fc9709a3 | 223 | /** |
| AnnaBridge | 189:f392fc9709a3 | 224 | * @brief Read a value in SWPMI register |
| AnnaBridge | 189:f392fc9709a3 | 225 | * @param __INSTANCE__ SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 226 | * @param __REG__ Register to be read |
| AnnaBridge | 189:f392fc9709a3 | 227 | * @retval Register value |
| AnnaBridge | 189:f392fc9709a3 | 228 | */ |
| AnnaBridge | 189:f392fc9709a3 | 229 | #define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
| AnnaBridge | 189:f392fc9709a3 | 230 | /** |
| AnnaBridge | 189:f392fc9709a3 | 231 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 232 | */ |
| AnnaBridge | 189:f392fc9709a3 | 233 | |
| AnnaBridge | 189:f392fc9709a3 | 234 | /** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros |
| AnnaBridge | 189:f392fc9709a3 | 235 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 236 | */ |
| AnnaBridge | 189:f392fc9709a3 | 237 | |
| AnnaBridge | 189:f392fc9709a3 | 238 | /** |
| AnnaBridge | 189:f392fc9709a3 | 239 | * @brief Helper macro to calculate bit rate value to set in BRR register (@ref LL_SWPMI_SetBitRatePrescaler function) |
| AnnaBridge | 189:f392fc9709a3 | 240 | * @note ex: @ref __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000); |
| AnnaBridge | 189:f392fc9709a3 | 241 | * @param __FSWP__ Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s) |
| AnnaBridge | 189:f392fc9709a3 | 242 | * @param __FSWPCLK__ PCLK or HSI frequency (in Hz) |
| AnnaBridge | 189:f392fc9709a3 | 243 | * @retval Bitrate prescaler (BRR register) |
| AnnaBridge | 189:f392fc9709a3 | 244 | */ |
| AnnaBridge | 189:f392fc9709a3 | 245 | #define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__) ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1)) |
| AnnaBridge | 189:f392fc9709a3 | 246 | |
| AnnaBridge | 189:f392fc9709a3 | 247 | /** |
| AnnaBridge | 189:f392fc9709a3 | 248 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 249 | */ |
| AnnaBridge | 189:f392fc9709a3 | 250 | |
| AnnaBridge | 189:f392fc9709a3 | 251 | /** |
| AnnaBridge | 189:f392fc9709a3 | 252 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 253 | */ |
| AnnaBridge | 189:f392fc9709a3 | 254 | |
| AnnaBridge | 189:f392fc9709a3 | 255 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 256 | /** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 257 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 258 | */ |
| AnnaBridge | 189:f392fc9709a3 | 259 | |
| AnnaBridge | 189:f392fc9709a3 | 260 | /** @defgroup SWPMI_LL_EF_Configuration Configuration |
| AnnaBridge | 189:f392fc9709a3 | 261 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 262 | */ |
| AnnaBridge | 189:f392fc9709a3 | 263 | |
| AnnaBridge | 189:f392fc9709a3 | 264 | /** |
| AnnaBridge | 189:f392fc9709a3 | 265 | * @brief Set Reception buffering mode |
| AnnaBridge | 189:f392fc9709a3 | 266 | * @note If Multi software buffer mode is chosen, RXDMA bits must also be set. |
| AnnaBridge | 189:f392fc9709a3 | 267 | * @rmtoll CR RXMODE LL_SWPMI_SetReceptionMode |
| AnnaBridge | 189:f392fc9709a3 | 268 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 269 | * @param RxBufferingMode This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 270 | * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE |
| AnnaBridge | 189:f392fc9709a3 | 271 | * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI |
| AnnaBridge | 189:f392fc9709a3 | 272 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 273 | */ |
| AnnaBridge | 189:f392fc9709a3 | 274 | __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode) |
| AnnaBridge | 189:f392fc9709a3 | 275 | { |
| AnnaBridge | 189:f392fc9709a3 | 276 | MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode); |
| AnnaBridge | 189:f392fc9709a3 | 277 | } |
| AnnaBridge | 189:f392fc9709a3 | 278 | |
| AnnaBridge | 189:f392fc9709a3 | 279 | /** |
| AnnaBridge | 189:f392fc9709a3 | 280 | * @brief Get Reception buffering mode |
| AnnaBridge | 189:f392fc9709a3 | 281 | * @rmtoll CR RXMODE LL_SWPMI_GetReceptionMode |
| AnnaBridge | 189:f392fc9709a3 | 282 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 283 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 284 | * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE |
| AnnaBridge | 189:f392fc9709a3 | 285 | * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI |
| AnnaBridge | 189:f392fc9709a3 | 286 | */ |
| AnnaBridge | 189:f392fc9709a3 | 287 | __STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 288 | { |
| AnnaBridge | 189:f392fc9709a3 | 289 | return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE)); |
| AnnaBridge | 189:f392fc9709a3 | 290 | } |
| AnnaBridge | 189:f392fc9709a3 | 291 | |
| AnnaBridge | 189:f392fc9709a3 | 292 | /** |
| AnnaBridge | 189:f392fc9709a3 | 293 | * @brief Set Transmission buffering mode |
| AnnaBridge | 189:f392fc9709a3 | 294 | * @note If Multi software buffer mode is chosen, TXDMA bits must also be set. |
| AnnaBridge | 189:f392fc9709a3 | 295 | * @rmtoll CR TXMODE LL_SWPMI_SetTransmissionMode |
| AnnaBridge | 189:f392fc9709a3 | 296 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 297 | * @param TxBufferingMode This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 298 | * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE |
| AnnaBridge | 189:f392fc9709a3 | 299 | * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI |
| AnnaBridge | 189:f392fc9709a3 | 300 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 301 | */ |
| AnnaBridge | 189:f392fc9709a3 | 302 | __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode) |
| AnnaBridge | 189:f392fc9709a3 | 303 | { |
| AnnaBridge | 189:f392fc9709a3 | 304 | MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode); |
| AnnaBridge | 189:f392fc9709a3 | 305 | } |
| AnnaBridge | 189:f392fc9709a3 | 306 | |
| AnnaBridge | 189:f392fc9709a3 | 307 | /** |
| AnnaBridge | 189:f392fc9709a3 | 308 | * @brief Get Transmission buffering mode |
| AnnaBridge | 189:f392fc9709a3 | 309 | * @rmtoll CR TXMODE LL_SWPMI_GetTransmissionMode |
| AnnaBridge | 189:f392fc9709a3 | 310 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 311 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 312 | * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE |
| AnnaBridge | 189:f392fc9709a3 | 313 | * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI |
| AnnaBridge | 189:f392fc9709a3 | 314 | */ |
| AnnaBridge | 189:f392fc9709a3 | 315 | __STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 316 | { |
| AnnaBridge | 189:f392fc9709a3 | 317 | return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE)); |
| AnnaBridge | 189:f392fc9709a3 | 318 | } |
| AnnaBridge | 189:f392fc9709a3 | 319 | |
| AnnaBridge | 189:f392fc9709a3 | 320 | /** |
| AnnaBridge | 189:f392fc9709a3 | 321 | * @brief Enable loopback mode |
| AnnaBridge | 189:f392fc9709a3 | 322 | * @rmtoll CR LPBK LL_SWPMI_EnableLoopback |
| AnnaBridge | 189:f392fc9709a3 | 323 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 324 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 325 | */ |
| AnnaBridge | 189:f392fc9709a3 | 326 | __STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 327 | { |
| AnnaBridge | 189:f392fc9709a3 | 328 | SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK); |
| AnnaBridge | 189:f392fc9709a3 | 329 | } |
| AnnaBridge | 189:f392fc9709a3 | 330 | |
| AnnaBridge | 189:f392fc9709a3 | 331 | /** |
| AnnaBridge | 189:f392fc9709a3 | 332 | * @brief Disable loopback mode |
| AnnaBridge | 189:f392fc9709a3 | 333 | * @rmtoll CR LPBK LL_SWPMI_DisableLoopback |
| AnnaBridge | 189:f392fc9709a3 | 334 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 335 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 336 | */ |
| AnnaBridge | 189:f392fc9709a3 | 337 | __STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 338 | { |
| AnnaBridge | 189:f392fc9709a3 | 339 | CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK); |
| AnnaBridge | 189:f392fc9709a3 | 340 | } |
| AnnaBridge | 189:f392fc9709a3 | 341 | |
| AnnaBridge | 189:f392fc9709a3 | 342 | /** |
| AnnaBridge | 189:f392fc9709a3 | 343 | * @brief Activate Single wire protocol bus (SUSPENDED or ACTIVATED state) |
| AnnaBridge | 189:f392fc9709a3 | 344 | * @note SWP bus stays in the ACTIVATED state as long as there is a communication |
| AnnaBridge | 189:f392fc9709a3 | 345 | * with the slave, either in transmission or in reception. The SWP bus switches back |
| AnnaBridge | 189:f392fc9709a3 | 346 | * to the SUSPENDED state as soon as there is no more transmission or reception |
| AnnaBridge | 189:f392fc9709a3 | 347 | * activity, after 7 idle bits. |
| AnnaBridge | 189:f392fc9709a3 | 348 | * @rmtoll CR SWPACT LL_SWPMI_Activate |
| AnnaBridge | 189:f392fc9709a3 | 349 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 350 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 351 | */ |
| AnnaBridge | 189:f392fc9709a3 | 352 | __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 353 | { |
| AnnaBridge | 189:f392fc9709a3 | 354 | /* In order to activate SWP again, the software must clear DEACT bit*/ |
| AnnaBridge | 189:f392fc9709a3 | 355 | CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT); |
| AnnaBridge | 189:f392fc9709a3 | 356 | |
| AnnaBridge | 189:f392fc9709a3 | 357 | /* Set SWACT bit */ |
| AnnaBridge | 189:f392fc9709a3 | 358 | SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT); |
| AnnaBridge | 189:f392fc9709a3 | 359 | } |
| AnnaBridge | 189:f392fc9709a3 | 360 | |
| AnnaBridge | 189:f392fc9709a3 | 361 | /** |
| AnnaBridge | 189:f392fc9709a3 | 362 | * @brief Check if Single wire protocol bus is in ACTIVATED state. |
| AnnaBridge | 189:f392fc9709a3 | 363 | * @rmtoll CR SWPACT LL_SWPMI_Activate |
| AnnaBridge | 189:f392fc9709a3 | 364 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 365 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 366 | */ |
| AnnaBridge | 189:f392fc9709a3 | 367 | __STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 368 | { |
| AnnaBridge | 189:f392fc9709a3 | 369 | return (READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)); |
| AnnaBridge | 189:f392fc9709a3 | 370 | } |
| AnnaBridge | 189:f392fc9709a3 | 371 | |
| AnnaBridge | 189:f392fc9709a3 | 372 | /** |
| AnnaBridge | 189:f392fc9709a3 | 373 | * @brief Deactivate immediately Single wire protocol bus (immediate transition to |
| AnnaBridge | 189:f392fc9709a3 | 374 | * DEACTIVATED state) |
| AnnaBridge | 189:f392fc9709a3 | 375 | * @rmtoll CR SWPACT LL_SWPMI_Deactivate |
| AnnaBridge | 189:f392fc9709a3 | 376 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 377 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 378 | */ |
| AnnaBridge | 189:f392fc9709a3 | 379 | __STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 380 | { |
| AnnaBridge | 189:f392fc9709a3 | 381 | CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT); |
| AnnaBridge | 189:f392fc9709a3 | 382 | } |
| AnnaBridge | 189:f392fc9709a3 | 383 | |
| AnnaBridge | 189:f392fc9709a3 | 384 | /** |
| AnnaBridge | 189:f392fc9709a3 | 385 | * @brief Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED |
| AnnaBridge | 189:f392fc9709a3 | 386 | * state if no resume from slave) |
| AnnaBridge | 189:f392fc9709a3 | 387 | * @rmtoll CR DEACT LL_SWPMI_RequestDeactivation |
| AnnaBridge | 189:f392fc9709a3 | 388 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 389 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 390 | */ |
| AnnaBridge | 189:f392fc9709a3 | 391 | __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 392 | { |
| AnnaBridge | 189:f392fc9709a3 | 393 | SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT); |
| AnnaBridge | 189:f392fc9709a3 | 394 | } |
| AnnaBridge | 189:f392fc9709a3 | 395 | |
| AnnaBridge | 189:f392fc9709a3 | 396 | /** |
| AnnaBridge | 189:f392fc9709a3 | 397 | * @brief Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4) |
| AnnaBridge | 189:f392fc9709a3 | 398 | * @rmtoll BRR BR LL_SWPMI_SetBitRatePrescaler |
| AnnaBridge | 189:f392fc9709a3 | 399 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 400 | * @param BitRatePrescaler A number between Min_Data=0 and Max_Data=63 |
| AnnaBridge | 189:f392fc9709a3 | 401 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 402 | */ |
| AnnaBridge | 189:f392fc9709a3 | 403 | __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler) |
| AnnaBridge | 189:f392fc9709a3 | 404 | { |
| AnnaBridge | 189:f392fc9709a3 | 405 | WRITE_REG(SWPMIx->BRR, BitRatePrescaler); |
| AnnaBridge | 189:f392fc9709a3 | 406 | } |
| AnnaBridge | 189:f392fc9709a3 | 407 | |
| AnnaBridge | 189:f392fc9709a3 | 408 | /** |
| AnnaBridge | 189:f392fc9709a3 | 409 | * @brief Get Bitrate prescaler |
| AnnaBridge | 189:f392fc9709a3 | 410 | * @rmtoll BRR BR LL_SWPMI_GetBitRatePrescaler |
| AnnaBridge | 189:f392fc9709a3 | 411 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 412 | * @retval A number between Min_Data=0 and Max_Data=63 |
| AnnaBridge | 189:f392fc9709a3 | 413 | */ |
| AnnaBridge | 189:f392fc9709a3 | 414 | __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 415 | { |
| AnnaBridge | 189:f392fc9709a3 | 416 | return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR)); |
| AnnaBridge | 189:f392fc9709a3 | 417 | } |
| AnnaBridge | 189:f392fc9709a3 | 418 | |
| AnnaBridge | 189:f392fc9709a3 | 419 | /** |
| AnnaBridge | 189:f392fc9709a3 | 420 | * @brief Set SWP Voltage Class |
| AnnaBridge | 189:f392fc9709a3 | 421 | * @rmtoll OR CLASS LL_SWPMI_SetVoltageClass |
| AnnaBridge | 189:f392fc9709a3 | 422 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 423 | * @param VoltageClass This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 424 | * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C |
| AnnaBridge | 189:f392fc9709a3 | 425 | * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B |
| AnnaBridge | 189:f392fc9709a3 | 426 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 427 | */ |
| AnnaBridge | 189:f392fc9709a3 | 428 | __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass) |
| AnnaBridge | 189:f392fc9709a3 | 429 | { |
| AnnaBridge | 189:f392fc9709a3 | 430 | MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass); |
| AnnaBridge | 189:f392fc9709a3 | 431 | } |
| AnnaBridge | 189:f392fc9709a3 | 432 | |
| AnnaBridge | 189:f392fc9709a3 | 433 | /** |
| AnnaBridge | 189:f392fc9709a3 | 434 | * @brief Get SWP Voltage Class |
| AnnaBridge | 189:f392fc9709a3 | 435 | * @rmtoll OR CLASS LL_SWPMI_GetVoltageClass |
| AnnaBridge | 189:f392fc9709a3 | 436 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 437 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 438 | * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C |
| AnnaBridge | 189:f392fc9709a3 | 439 | * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B |
| AnnaBridge | 189:f392fc9709a3 | 440 | */ |
| AnnaBridge | 189:f392fc9709a3 | 441 | __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 442 | { |
| AnnaBridge | 189:f392fc9709a3 | 443 | return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS)); |
| AnnaBridge | 189:f392fc9709a3 | 444 | } |
| AnnaBridge | 189:f392fc9709a3 | 445 | |
| AnnaBridge | 189:f392fc9709a3 | 446 | /** |
| AnnaBridge | 189:f392fc9709a3 | 447 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 448 | */ |
| AnnaBridge | 189:f392fc9709a3 | 449 | |
| AnnaBridge | 189:f392fc9709a3 | 450 | /** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management |
| AnnaBridge | 189:f392fc9709a3 | 451 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 452 | */ |
| AnnaBridge | 189:f392fc9709a3 | 453 | |
| AnnaBridge | 189:f392fc9709a3 | 454 | /** |
| AnnaBridge | 189:f392fc9709a3 | 455 | * @brief Check if the last word of the frame under reception has arrived in SWPMI_RDR. |
| AnnaBridge | 189:f392fc9709a3 | 456 | * @rmtoll ISR RXBFF LL_SWPMI_IsActiveFlag_RXBF |
| AnnaBridge | 189:f392fc9709a3 | 457 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 458 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 459 | */ |
| AnnaBridge | 189:f392fc9709a3 | 460 | __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 461 | { |
| AnnaBridge | 189:f392fc9709a3 | 462 | return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)); |
| AnnaBridge | 189:f392fc9709a3 | 463 | } |
| AnnaBridge | 189:f392fc9709a3 | 464 | |
| AnnaBridge | 189:f392fc9709a3 | 465 | /** |
| AnnaBridge | 189:f392fc9709a3 | 466 | * @brief Check if Frame transmission buffer has been emptied |
| AnnaBridge | 189:f392fc9709a3 | 467 | * @rmtoll ISR TXBEF LL_SWPMI_IsActiveFlag_TXBE |
| AnnaBridge | 189:f392fc9709a3 | 468 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 469 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 470 | */ |
| AnnaBridge | 189:f392fc9709a3 | 471 | __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 472 | { |
| AnnaBridge | 189:f392fc9709a3 | 473 | return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)); |
| AnnaBridge | 189:f392fc9709a3 | 474 | } |
| AnnaBridge | 189:f392fc9709a3 | 475 | |
| AnnaBridge | 189:f392fc9709a3 | 476 | /** |
| AnnaBridge | 189:f392fc9709a3 | 477 | * @brief Check if CRC error in reception has been detected |
| AnnaBridge | 189:f392fc9709a3 | 478 | * @rmtoll ISR RXBERF LL_SWPMI_IsActiveFlag_RXBER |
| AnnaBridge | 189:f392fc9709a3 | 479 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 480 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 481 | */ |
| AnnaBridge | 189:f392fc9709a3 | 482 | __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 483 | { |
| AnnaBridge | 189:f392fc9709a3 | 484 | return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)); |
| AnnaBridge | 189:f392fc9709a3 | 485 | } |
| AnnaBridge | 189:f392fc9709a3 | 486 | |
| AnnaBridge | 189:f392fc9709a3 | 487 | /** |
| AnnaBridge | 189:f392fc9709a3 | 488 | * @brief Check if Overrun in reception has been detected |
| AnnaBridge | 189:f392fc9709a3 | 489 | * @rmtoll ISR RXOVRF LL_SWPMI_IsActiveFlag_RXOVR |
| AnnaBridge | 189:f392fc9709a3 | 490 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 491 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 492 | */ |
| AnnaBridge | 189:f392fc9709a3 | 493 | __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 494 | { |
| AnnaBridge | 189:f392fc9709a3 | 495 | return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)); |
| AnnaBridge | 189:f392fc9709a3 | 496 | } |
| AnnaBridge | 189:f392fc9709a3 | 497 | |
| AnnaBridge | 189:f392fc9709a3 | 498 | /** |
| AnnaBridge | 189:f392fc9709a3 | 499 | * @brief Check if underrun error in transmission has been detected |
| AnnaBridge | 189:f392fc9709a3 | 500 | * @rmtoll ISR TXUNRF LL_SWPMI_IsActiveFlag_TXUNR |
| AnnaBridge | 189:f392fc9709a3 | 501 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 502 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 503 | */ |
| AnnaBridge | 189:f392fc9709a3 | 504 | __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 505 | { |
| AnnaBridge | 189:f392fc9709a3 | 506 | return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)); |
| AnnaBridge | 189:f392fc9709a3 | 507 | } |
| AnnaBridge | 189:f392fc9709a3 | 508 | |
| AnnaBridge | 189:f392fc9709a3 | 509 | /** |
| AnnaBridge | 189:f392fc9709a3 | 510 | * @brief Check if Receive data register not empty (it means that Received data is ready |
| AnnaBridge | 189:f392fc9709a3 | 511 | * to be read in the SWPMI_RDR register) |
| AnnaBridge | 189:f392fc9709a3 | 512 | * @rmtoll ISR RXNE LL_SWPMI_IsActiveFlag_RXNE |
| AnnaBridge | 189:f392fc9709a3 | 513 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 514 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 515 | */ |
| AnnaBridge | 189:f392fc9709a3 | 516 | __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 517 | { |
| AnnaBridge | 189:f392fc9709a3 | 518 | return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)); |
| AnnaBridge | 189:f392fc9709a3 | 519 | } |
| AnnaBridge | 189:f392fc9709a3 | 520 | |
| AnnaBridge | 189:f392fc9709a3 | 521 | /** |
| AnnaBridge | 189:f392fc9709a3 | 522 | * @brief Check if Transmit data register is empty (it means that Data written in transmit |
| AnnaBridge | 189:f392fc9709a3 | 523 | * data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again) |
| AnnaBridge | 189:f392fc9709a3 | 524 | * @rmtoll ISR TXE LL_SWPMI_IsActiveFlag_TXE |
| AnnaBridge | 189:f392fc9709a3 | 525 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 526 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 527 | */ |
| AnnaBridge | 189:f392fc9709a3 | 528 | __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 529 | { |
| AnnaBridge | 189:f392fc9709a3 | 530 | return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)); |
| AnnaBridge | 189:f392fc9709a3 | 531 | } |
| AnnaBridge | 189:f392fc9709a3 | 532 | |
| AnnaBridge | 189:f392fc9709a3 | 533 | /** |
| AnnaBridge | 189:f392fc9709a3 | 534 | * @brief Check if Both transmission and reception are completed and SWP is switched to |
| AnnaBridge | 189:f392fc9709a3 | 535 | * the SUSPENDED state |
| AnnaBridge | 189:f392fc9709a3 | 536 | * @rmtoll ISR TCF LL_SWPMI_IsActiveFlag_TC |
| AnnaBridge | 189:f392fc9709a3 | 537 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 538 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 539 | */ |
| AnnaBridge | 189:f392fc9709a3 | 540 | __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 541 | { |
| AnnaBridge | 189:f392fc9709a3 | 542 | return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)); |
| AnnaBridge | 189:f392fc9709a3 | 543 | } |
| AnnaBridge | 189:f392fc9709a3 | 544 | |
| AnnaBridge | 189:f392fc9709a3 | 545 | /** |
| AnnaBridge | 189:f392fc9709a3 | 546 | * @brief Check if a Resume by slave state has been detected during the SWP bus SUSPENDED |
| AnnaBridge | 189:f392fc9709a3 | 547 | * state |
| AnnaBridge | 189:f392fc9709a3 | 548 | * @rmtoll ISR SRF LL_SWPMI_IsActiveFlag_SR |
| AnnaBridge | 189:f392fc9709a3 | 549 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 550 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 551 | */ |
| AnnaBridge | 189:f392fc9709a3 | 552 | __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 553 | { |
| AnnaBridge | 189:f392fc9709a3 | 554 | return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)); |
| AnnaBridge | 189:f392fc9709a3 | 555 | } |
| AnnaBridge | 189:f392fc9709a3 | 556 | |
| AnnaBridge | 189:f392fc9709a3 | 557 | /** |
| AnnaBridge | 189:f392fc9709a3 | 558 | * @brief Check if SWP bus is in SUSPENDED or DEACTIVATED state |
| AnnaBridge | 189:f392fc9709a3 | 559 | * @rmtoll ISR SUSP LL_SWPMI_IsActiveFlag_SUSP |
| AnnaBridge | 189:f392fc9709a3 | 560 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 561 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 562 | */ |
| AnnaBridge | 189:f392fc9709a3 | 563 | __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 564 | { |
| AnnaBridge | 189:f392fc9709a3 | 565 | return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)); |
| AnnaBridge | 189:f392fc9709a3 | 566 | } |
| AnnaBridge | 189:f392fc9709a3 | 567 | |
| AnnaBridge | 189:f392fc9709a3 | 568 | /** |
| AnnaBridge | 189:f392fc9709a3 | 569 | * @brief Check if SWP bus is in DEACTIVATED state |
| AnnaBridge | 189:f392fc9709a3 | 570 | * @rmtoll ISR DEACTF LL_SWPMI_IsActiveFlag_DEACT |
| AnnaBridge | 189:f392fc9709a3 | 571 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 572 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 573 | */ |
| AnnaBridge | 189:f392fc9709a3 | 574 | __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 575 | { |
| AnnaBridge | 189:f392fc9709a3 | 576 | return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)); |
| AnnaBridge | 189:f392fc9709a3 | 577 | } |
| AnnaBridge | 189:f392fc9709a3 | 578 | |
| AnnaBridge | 189:f392fc9709a3 | 579 | /** |
| AnnaBridge | 189:f392fc9709a3 | 580 | * @brief Clear receive buffer full flag |
| AnnaBridge | 189:f392fc9709a3 | 581 | * @rmtoll ICR CRXBFF LL_SWPMI_ClearFlag_RXBF |
| AnnaBridge | 189:f392fc9709a3 | 582 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 583 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 584 | */ |
| AnnaBridge | 189:f392fc9709a3 | 585 | __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 586 | { |
| AnnaBridge | 189:f392fc9709a3 | 587 | WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF); |
| AnnaBridge | 189:f392fc9709a3 | 588 | } |
| AnnaBridge | 189:f392fc9709a3 | 589 | |
| AnnaBridge | 189:f392fc9709a3 | 590 | /** |
| AnnaBridge | 189:f392fc9709a3 | 591 | * @brief Clear transmit buffer empty flag |
| AnnaBridge | 189:f392fc9709a3 | 592 | * @rmtoll ICR CTXBEF LL_SWPMI_ClearFlag_TXBE |
| AnnaBridge | 189:f392fc9709a3 | 593 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 594 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 595 | */ |
| AnnaBridge | 189:f392fc9709a3 | 596 | __STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 597 | { |
| AnnaBridge | 189:f392fc9709a3 | 598 | WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF); |
| AnnaBridge | 189:f392fc9709a3 | 599 | } |
| AnnaBridge | 189:f392fc9709a3 | 600 | |
| AnnaBridge | 189:f392fc9709a3 | 601 | /** |
| AnnaBridge | 189:f392fc9709a3 | 602 | * @brief Clear receive CRC error flag |
| AnnaBridge | 189:f392fc9709a3 | 603 | * @rmtoll ICR CRXBERF LL_SWPMI_ClearFlag_RXBER |
| AnnaBridge | 189:f392fc9709a3 | 604 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 605 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 606 | */ |
| AnnaBridge | 189:f392fc9709a3 | 607 | __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 608 | { |
| AnnaBridge | 189:f392fc9709a3 | 609 | WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF); |
| AnnaBridge | 189:f392fc9709a3 | 610 | } |
| AnnaBridge | 189:f392fc9709a3 | 611 | |
| AnnaBridge | 189:f392fc9709a3 | 612 | /** |
| AnnaBridge | 189:f392fc9709a3 | 613 | * @brief Clear receive overrun error flag |
| AnnaBridge | 189:f392fc9709a3 | 614 | * @rmtoll ICR CRXOVRF LL_SWPMI_ClearFlag_RXOVR |
| AnnaBridge | 189:f392fc9709a3 | 615 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 616 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 617 | */ |
| AnnaBridge | 189:f392fc9709a3 | 618 | __STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 619 | { |
| AnnaBridge | 189:f392fc9709a3 | 620 | WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF); |
| AnnaBridge | 189:f392fc9709a3 | 621 | } |
| AnnaBridge | 189:f392fc9709a3 | 622 | |
| AnnaBridge | 189:f392fc9709a3 | 623 | /** |
| AnnaBridge | 189:f392fc9709a3 | 624 | * @brief Clear transmit underrun error flag |
| AnnaBridge | 189:f392fc9709a3 | 625 | * @rmtoll ICR CTXUNRF LL_SWPMI_ClearFlag_TXUNR |
| AnnaBridge | 189:f392fc9709a3 | 626 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 627 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 628 | */ |
| AnnaBridge | 189:f392fc9709a3 | 629 | __STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 630 | { |
| AnnaBridge | 189:f392fc9709a3 | 631 | WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF); |
| AnnaBridge | 189:f392fc9709a3 | 632 | } |
| AnnaBridge | 189:f392fc9709a3 | 633 | |
| AnnaBridge | 189:f392fc9709a3 | 634 | /** |
| AnnaBridge | 189:f392fc9709a3 | 635 | * @brief Clear transfer complete flag |
| AnnaBridge | 189:f392fc9709a3 | 636 | * @rmtoll ICR CTCF LL_SWPMI_ClearFlag_TC |
| AnnaBridge | 189:f392fc9709a3 | 637 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 638 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 639 | */ |
| AnnaBridge | 189:f392fc9709a3 | 640 | __STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 641 | { |
| AnnaBridge | 189:f392fc9709a3 | 642 | WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF); |
| AnnaBridge | 189:f392fc9709a3 | 643 | } |
| AnnaBridge | 189:f392fc9709a3 | 644 | |
| AnnaBridge | 189:f392fc9709a3 | 645 | /** |
| AnnaBridge | 189:f392fc9709a3 | 646 | * @brief Clear slave resume flag |
| AnnaBridge | 189:f392fc9709a3 | 647 | * @rmtoll ICR CSRF LL_SWPMI_ClearFlag_SR |
| AnnaBridge | 189:f392fc9709a3 | 648 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 649 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 650 | */ |
| AnnaBridge | 189:f392fc9709a3 | 651 | __STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 652 | { |
| AnnaBridge | 189:f392fc9709a3 | 653 | WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF); |
| AnnaBridge | 189:f392fc9709a3 | 654 | } |
| AnnaBridge | 189:f392fc9709a3 | 655 | |
| AnnaBridge | 189:f392fc9709a3 | 656 | /** |
| AnnaBridge | 189:f392fc9709a3 | 657 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 658 | */ |
| AnnaBridge | 189:f392fc9709a3 | 659 | |
| AnnaBridge | 189:f392fc9709a3 | 660 | /** @defgroup SWPMI_LL_EF_IT_Management IT_Management |
| AnnaBridge | 189:f392fc9709a3 | 661 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 662 | */ |
| AnnaBridge | 189:f392fc9709a3 | 663 | |
| AnnaBridge | 189:f392fc9709a3 | 664 | /** |
| AnnaBridge | 189:f392fc9709a3 | 665 | * @brief Enable Slave resume interrupt |
| AnnaBridge | 189:f392fc9709a3 | 666 | * @rmtoll IER SRIE LL_SWPMI_EnableIT_SR |
| AnnaBridge | 189:f392fc9709a3 | 667 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 668 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 669 | */ |
| AnnaBridge | 189:f392fc9709a3 | 670 | __STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 671 | { |
| AnnaBridge | 189:f392fc9709a3 | 672 | SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE); |
| AnnaBridge | 189:f392fc9709a3 | 673 | } |
| AnnaBridge | 189:f392fc9709a3 | 674 | |
| AnnaBridge | 189:f392fc9709a3 | 675 | /** |
| AnnaBridge | 189:f392fc9709a3 | 676 | * @brief Enable Transmit complete interrupt |
| AnnaBridge | 189:f392fc9709a3 | 677 | * @rmtoll IER TCIE LL_SWPMI_EnableIT_TC |
| AnnaBridge | 189:f392fc9709a3 | 678 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 679 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 680 | */ |
| AnnaBridge | 189:f392fc9709a3 | 681 | __STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 682 | { |
| AnnaBridge | 189:f392fc9709a3 | 683 | SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE); |
| AnnaBridge | 189:f392fc9709a3 | 684 | } |
| AnnaBridge | 189:f392fc9709a3 | 685 | |
| AnnaBridge | 189:f392fc9709a3 | 686 | /** |
| AnnaBridge | 189:f392fc9709a3 | 687 | * @brief Enable Transmit interrupt |
| AnnaBridge | 189:f392fc9709a3 | 688 | * @rmtoll IER TIE LL_SWPMI_EnableIT_TX |
| AnnaBridge | 189:f392fc9709a3 | 689 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 690 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 691 | */ |
| AnnaBridge | 189:f392fc9709a3 | 692 | __STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 693 | { |
| AnnaBridge | 189:f392fc9709a3 | 694 | SET_BIT(SWPMIx->IER, SWPMI_IER_TIE); |
| AnnaBridge | 189:f392fc9709a3 | 695 | } |
| AnnaBridge | 189:f392fc9709a3 | 696 | |
| AnnaBridge | 189:f392fc9709a3 | 697 | /** |
| AnnaBridge | 189:f392fc9709a3 | 698 | * @brief Enable Receive interrupt |
| AnnaBridge | 189:f392fc9709a3 | 699 | * @rmtoll IER RIE LL_SWPMI_EnableIT_RX |
| AnnaBridge | 189:f392fc9709a3 | 700 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 701 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 702 | */ |
| AnnaBridge | 189:f392fc9709a3 | 703 | __STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 704 | { |
| AnnaBridge | 189:f392fc9709a3 | 705 | SET_BIT(SWPMIx->IER, SWPMI_IER_RIE); |
| AnnaBridge | 189:f392fc9709a3 | 706 | } |
| AnnaBridge | 189:f392fc9709a3 | 707 | |
| AnnaBridge | 189:f392fc9709a3 | 708 | /** |
| AnnaBridge | 189:f392fc9709a3 | 709 | * @brief Enable Transmit underrun error interrupt |
| AnnaBridge | 189:f392fc9709a3 | 710 | * @rmtoll IER TXUNRIE LL_SWPMI_EnableIT_TXUNR |
| AnnaBridge | 189:f392fc9709a3 | 711 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 712 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 713 | */ |
| AnnaBridge | 189:f392fc9709a3 | 714 | __STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 715 | { |
| AnnaBridge | 189:f392fc9709a3 | 716 | SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE); |
| AnnaBridge | 189:f392fc9709a3 | 717 | } |
| AnnaBridge | 189:f392fc9709a3 | 718 | |
| AnnaBridge | 189:f392fc9709a3 | 719 | /** |
| AnnaBridge | 189:f392fc9709a3 | 720 | * @brief Enable Receive overrun error interrupt |
| AnnaBridge | 189:f392fc9709a3 | 721 | * @rmtoll IER RXOVRIE LL_SWPMI_EnableIT_RXOVR |
| AnnaBridge | 189:f392fc9709a3 | 722 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 723 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 724 | */ |
| AnnaBridge | 189:f392fc9709a3 | 725 | __STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 726 | { |
| AnnaBridge | 189:f392fc9709a3 | 727 | SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE); |
| AnnaBridge | 189:f392fc9709a3 | 728 | } |
| AnnaBridge | 189:f392fc9709a3 | 729 | |
| AnnaBridge | 189:f392fc9709a3 | 730 | /** |
| AnnaBridge | 189:f392fc9709a3 | 731 | * @brief Enable Receive CRC error interrupt |
| AnnaBridge | 189:f392fc9709a3 | 732 | * @rmtoll IER RXBERIE LL_SWPMI_EnableIT_RXBER |
| AnnaBridge | 189:f392fc9709a3 | 733 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 734 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 735 | */ |
| AnnaBridge | 189:f392fc9709a3 | 736 | __STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 737 | { |
| AnnaBridge | 189:f392fc9709a3 | 738 | SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE); |
| AnnaBridge | 189:f392fc9709a3 | 739 | } |
| AnnaBridge | 189:f392fc9709a3 | 740 | |
| AnnaBridge | 189:f392fc9709a3 | 741 | /** |
| AnnaBridge | 189:f392fc9709a3 | 742 | * @brief Enable Transmit buffer empty interrupt |
| AnnaBridge | 189:f392fc9709a3 | 743 | * @rmtoll IER TXBEIE LL_SWPMI_EnableIT_TXBE |
| AnnaBridge | 189:f392fc9709a3 | 744 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 745 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 746 | */ |
| AnnaBridge | 189:f392fc9709a3 | 747 | __STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 748 | { |
| AnnaBridge | 189:f392fc9709a3 | 749 | SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE); |
| AnnaBridge | 189:f392fc9709a3 | 750 | } |
| AnnaBridge | 189:f392fc9709a3 | 751 | |
| AnnaBridge | 189:f392fc9709a3 | 752 | /** |
| AnnaBridge | 189:f392fc9709a3 | 753 | * @brief Enable Receive buffer full interrupt |
| AnnaBridge | 189:f392fc9709a3 | 754 | * @rmtoll IER RXBFIE LL_SWPMI_EnableIT_RXBF |
| AnnaBridge | 189:f392fc9709a3 | 755 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 756 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 757 | */ |
| AnnaBridge | 189:f392fc9709a3 | 758 | __STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 759 | { |
| AnnaBridge | 189:f392fc9709a3 | 760 | SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE); |
| AnnaBridge | 189:f392fc9709a3 | 761 | } |
| AnnaBridge | 189:f392fc9709a3 | 762 | |
| AnnaBridge | 189:f392fc9709a3 | 763 | /** |
| AnnaBridge | 189:f392fc9709a3 | 764 | * @brief Disable Slave resume interrupt |
| AnnaBridge | 189:f392fc9709a3 | 765 | * @rmtoll IER SRIE LL_SWPMI_DisableIT_SR |
| AnnaBridge | 189:f392fc9709a3 | 766 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 767 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 768 | */ |
| AnnaBridge | 189:f392fc9709a3 | 769 | __STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 770 | { |
| AnnaBridge | 189:f392fc9709a3 | 771 | CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE); |
| AnnaBridge | 189:f392fc9709a3 | 772 | } |
| AnnaBridge | 189:f392fc9709a3 | 773 | |
| AnnaBridge | 189:f392fc9709a3 | 774 | /** |
| AnnaBridge | 189:f392fc9709a3 | 775 | * @brief Disable Transmit complete interrupt |
| AnnaBridge | 189:f392fc9709a3 | 776 | * @rmtoll IER TCIE LL_SWPMI_DisableIT_TC |
| AnnaBridge | 189:f392fc9709a3 | 777 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 778 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 779 | */ |
| AnnaBridge | 189:f392fc9709a3 | 780 | __STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 781 | { |
| AnnaBridge | 189:f392fc9709a3 | 782 | CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE); |
| AnnaBridge | 189:f392fc9709a3 | 783 | } |
| AnnaBridge | 189:f392fc9709a3 | 784 | |
| AnnaBridge | 189:f392fc9709a3 | 785 | /** |
| AnnaBridge | 189:f392fc9709a3 | 786 | * @brief Disable Transmit interrupt |
| AnnaBridge | 189:f392fc9709a3 | 787 | * @rmtoll IER TIE LL_SWPMI_DisableIT_TX |
| AnnaBridge | 189:f392fc9709a3 | 788 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 789 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 790 | */ |
| AnnaBridge | 189:f392fc9709a3 | 791 | __STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 792 | { |
| AnnaBridge | 189:f392fc9709a3 | 793 | CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE); |
| AnnaBridge | 189:f392fc9709a3 | 794 | } |
| AnnaBridge | 189:f392fc9709a3 | 795 | |
| AnnaBridge | 189:f392fc9709a3 | 796 | /** |
| AnnaBridge | 189:f392fc9709a3 | 797 | * @brief Disable Receive interrupt |
| AnnaBridge | 189:f392fc9709a3 | 798 | * @rmtoll IER RIE LL_SWPMI_DisableIT_RX |
| AnnaBridge | 189:f392fc9709a3 | 799 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 800 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 801 | */ |
| AnnaBridge | 189:f392fc9709a3 | 802 | __STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 803 | { |
| AnnaBridge | 189:f392fc9709a3 | 804 | CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE); |
| AnnaBridge | 189:f392fc9709a3 | 805 | } |
| AnnaBridge | 189:f392fc9709a3 | 806 | |
| AnnaBridge | 189:f392fc9709a3 | 807 | /** |
| AnnaBridge | 189:f392fc9709a3 | 808 | * @brief Disable Transmit underrun error interrupt |
| AnnaBridge | 189:f392fc9709a3 | 809 | * @rmtoll IER TXUNRIE LL_SWPMI_DisableIT_TXUNR |
| AnnaBridge | 189:f392fc9709a3 | 810 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 811 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 812 | */ |
| AnnaBridge | 189:f392fc9709a3 | 813 | __STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 814 | { |
| AnnaBridge | 189:f392fc9709a3 | 815 | CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE); |
| AnnaBridge | 189:f392fc9709a3 | 816 | } |
| AnnaBridge | 189:f392fc9709a3 | 817 | |
| AnnaBridge | 189:f392fc9709a3 | 818 | /** |
| AnnaBridge | 189:f392fc9709a3 | 819 | * @brief Disable Receive overrun error interrupt |
| AnnaBridge | 189:f392fc9709a3 | 820 | * @rmtoll IER RXOVRIE LL_SWPMI_DisableIT_RXOVR |
| AnnaBridge | 189:f392fc9709a3 | 821 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 822 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 823 | */ |
| AnnaBridge | 189:f392fc9709a3 | 824 | __STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 825 | { |
| AnnaBridge | 189:f392fc9709a3 | 826 | CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE); |
| AnnaBridge | 189:f392fc9709a3 | 827 | } |
| AnnaBridge | 189:f392fc9709a3 | 828 | |
| AnnaBridge | 189:f392fc9709a3 | 829 | /** |
| AnnaBridge | 189:f392fc9709a3 | 830 | * @brief Disable Receive CRC error interrupt |
| AnnaBridge | 189:f392fc9709a3 | 831 | * @rmtoll IER RXBERIE LL_SWPMI_DisableIT_RXBER |
| AnnaBridge | 189:f392fc9709a3 | 832 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 833 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 834 | */ |
| AnnaBridge | 189:f392fc9709a3 | 835 | __STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 836 | { |
| AnnaBridge | 189:f392fc9709a3 | 837 | CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE); |
| AnnaBridge | 189:f392fc9709a3 | 838 | } |
| AnnaBridge | 189:f392fc9709a3 | 839 | |
| AnnaBridge | 189:f392fc9709a3 | 840 | /** |
| AnnaBridge | 189:f392fc9709a3 | 841 | * @brief Disable Transmit buffer empty interrupt |
| AnnaBridge | 189:f392fc9709a3 | 842 | * @rmtoll IER TXBEIE LL_SWPMI_DisableIT_TXBE |
| AnnaBridge | 189:f392fc9709a3 | 843 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 844 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 845 | */ |
| AnnaBridge | 189:f392fc9709a3 | 846 | __STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 847 | { |
| AnnaBridge | 189:f392fc9709a3 | 848 | CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE); |
| AnnaBridge | 189:f392fc9709a3 | 849 | } |
| AnnaBridge | 189:f392fc9709a3 | 850 | |
| AnnaBridge | 189:f392fc9709a3 | 851 | /** |
| AnnaBridge | 189:f392fc9709a3 | 852 | * @brief Disable Receive buffer full interrupt |
| AnnaBridge | 189:f392fc9709a3 | 853 | * @rmtoll IER RXBFIE LL_SWPMI_DisableIT_RXBF |
| AnnaBridge | 189:f392fc9709a3 | 854 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 855 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 856 | */ |
| AnnaBridge | 189:f392fc9709a3 | 857 | __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 858 | { |
| AnnaBridge | 189:f392fc9709a3 | 859 | CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE); |
| AnnaBridge | 189:f392fc9709a3 | 860 | } |
| AnnaBridge | 189:f392fc9709a3 | 861 | |
| AnnaBridge | 189:f392fc9709a3 | 862 | /** |
| AnnaBridge | 189:f392fc9709a3 | 863 | * @brief Check if Slave resume interrupt is enabled |
| AnnaBridge | 189:f392fc9709a3 | 864 | * @rmtoll IER SRIE LL_SWPMI_IsEnabledIT_SR |
| AnnaBridge | 189:f392fc9709a3 | 865 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 866 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 867 | */ |
| AnnaBridge | 189:f392fc9709a3 | 868 | __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 869 | { |
| AnnaBridge | 189:f392fc9709a3 | 870 | return (READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)); |
| AnnaBridge | 189:f392fc9709a3 | 871 | } |
| AnnaBridge | 189:f392fc9709a3 | 872 | |
| AnnaBridge | 189:f392fc9709a3 | 873 | /** |
| AnnaBridge | 189:f392fc9709a3 | 874 | * @brief Check if Transmit complete interrupt is enabled |
| AnnaBridge | 189:f392fc9709a3 | 875 | * @rmtoll IER TCIE LL_SWPMI_IsEnabledIT_TC |
| AnnaBridge | 189:f392fc9709a3 | 876 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 877 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 878 | */ |
| AnnaBridge | 189:f392fc9709a3 | 879 | __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 880 | { |
| AnnaBridge | 189:f392fc9709a3 | 881 | return (READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)); |
| AnnaBridge | 189:f392fc9709a3 | 882 | } |
| AnnaBridge | 189:f392fc9709a3 | 883 | |
| AnnaBridge | 189:f392fc9709a3 | 884 | /** |
| AnnaBridge | 189:f392fc9709a3 | 885 | * @brief Check if Transmit interrupt is enabled |
| AnnaBridge | 189:f392fc9709a3 | 886 | * @rmtoll IER TIE LL_SWPMI_IsEnabledIT_TX |
| AnnaBridge | 189:f392fc9709a3 | 887 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 888 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 889 | */ |
| AnnaBridge | 189:f392fc9709a3 | 890 | __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 891 | { |
| AnnaBridge | 189:f392fc9709a3 | 892 | return (READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)); |
| AnnaBridge | 189:f392fc9709a3 | 893 | } |
| AnnaBridge | 189:f392fc9709a3 | 894 | |
| AnnaBridge | 189:f392fc9709a3 | 895 | /** |
| AnnaBridge | 189:f392fc9709a3 | 896 | * @brief Check if Receive interrupt is enabled |
| AnnaBridge | 189:f392fc9709a3 | 897 | * @rmtoll IER RIE LL_SWPMI_IsEnabledIT_RX |
| AnnaBridge | 189:f392fc9709a3 | 898 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 899 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 900 | */ |
| AnnaBridge | 189:f392fc9709a3 | 901 | __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 902 | { |
| AnnaBridge | 189:f392fc9709a3 | 903 | return (READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)); |
| AnnaBridge | 189:f392fc9709a3 | 904 | } |
| AnnaBridge | 189:f392fc9709a3 | 905 | |
| AnnaBridge | 189:f392fc9709a3 | 906 | /** |
| AnnaBridge | 189:f392fc9709a3 | 907 | * @brief Check if Transmit underrun error interrupt is enabled |
| AnnaBridge | 189:f392fc9709a3 | 908 | * @rmtoll IER TXUNRIE LL_SWPMI_IsEnabledIT_TXUNR |
| AnnaBridge | 189:f392fc9709a3 | 909 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 910 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 911 | */ |
| AnnaBridge | 189:f392fc9709a3 | 912 | __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 913 | { |
| AnnaBridge | 189:f392fc9709a3 | 914 | return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)); |
| AnnaBridge | 189:f392fc9709a3 | 915 | } |
| AnnaBridge | 189:f392fc9709a3 | 916 | |
| AnnaBridge | 189:f392fc9709a3 | 917 | /** |
| AnnaBridge | 189:f392fc9709a3 | 918 | * @brief Check if Receive overrun error interrupt is enabled |
| AnnaBridge | 189:f392fc9709a3 | 919 | * @rmtoll IER RXOVRIE LL_SWPMI_IsEnabledIT_RXOVR |
| AnnaBridge | 189:f392fc9709a3 | 920 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 921 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 922 | */ |
| AnnaBridge | 189:f392fc9709a3 | 923 | __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 924 | { |
| AnnaBridge | 189:f392fc9709a3 | 925 | return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)); |
| AnnaBridge | 189:f392fc9709a3 | 926 | } |
| AnnaBridge | 189:f392fc9709a3 | 927 | |
| AnnaBridge | 189:f392fc9709a3 | 928 | /** |
| AnnaBridge | 189:f392fc9709a3 | 929 | * @brief Check if Receive CRC error interrupt is enabled |
| AnnaBridge | 189:f392fc9709a3 | 930 | * @rmtoll IER RXBERIE LL_SWPMI_IsEnabledIT_RXBER |
| AnnaBridge | 189:f392fc9709a3 | 931 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 932 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 933 | */ |
| AnnaBridge | 189:f392fc9709a3 | 934 | __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 935 | { |
| AnnaBridge | 189:f392fc9709a3 | 936 | return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)); |
| AnnaBridge | 189:f392fc9709a3 | 937 | } |
| AnnaBridge | 189:f392fc9709a3 | 938 | |
| AnnaBridge | 189:f392fc9709a3 | 939 | /** |
| AnnaBridge | 189:f392fc9709a3 | 940 | * @brief Check if Transmit buffer empty interrupt is enabled |
| AnnaBridge | 189:f392fc9709a3 | 941 | * @rmtoll IER TXBEIE LL_SWPMI_IsEnabledIT_TXBE |
| AnnaBridge | 189:f392fc9709a3 | 942 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 943 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 944 | */ |
| AnnaBridge | 189:f392fc9709a3 | 945 | __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 946 | { |
| AnnaBridge | 189:f392fc9709a3 | 947 | return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)); |
| AnnaBridge | 189:f392fc9709a3 | 948 | } |
| AnnaBridge | 189:f392fc9709a3 | 949 | |
| AnnaBridge | 189:f392fc9709a3 | 950 | /** |
| AnnaBridge | 189:f392fc9709a3 | 951 | * @brief Check if Receive buffer full interrupt is enabled |
| AnnaBridge | 189:f392fc9709a3 | 952 | * @rmtoll IER RXBFIE LL_SWPMI_IsEnabledIT_RXBF |
| AnnaBridge | 189:f392fc9709a3 | 953 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 954 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 955 | */ |
| AnnaBridge | 189:f392fc9709a3 | 956 | __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 957 | { |
| AnnaBridge | 189:f392fc9709a3 | 958 | return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)); |
| AnnaBridge | 189:f392fc9709a3 | 959 | } |
| AnnaBridge | 189:f392fc9709a3 | 960 | |
| AnnaBridge | 189:f392fc9709a3 | 961 | /** |
| AnnaBridge | 189:f392fc9709a3 | 962 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 963 | */ |
| AnnaBridge | 189:f392fc9709a3 | 964 | |
| AnnaBridge | 189:f392fc9709a3 | 965 | /** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management |
| AnnaBridge | 189:f392fc9709a3 | 966 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 967 | */ |
| AnnaBridge | 189:f392fc9709a3 | 968 | |
| AnnaBridge | 189:f392fc9709a3 | 969 | /** |
| AnnaBridge | 189:f392fc9709a3 | 970 | * @brief Enable DMA mode for reception |
| AnnaBridge | 189:f392fc9709a3 | 971 | * @rmtoll CR RXDMA LL_SWPMI_EnableDMAReq_RX |
| AnnaBridge | 189:f392fc9709a3 | 972 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 973 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 974 | */ |
| AnnaBridge | 189:f392fc9709a3 | 975 | __STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 976 | { |
| AnnaBridge | 189:f392fc9709a3 | 977 | SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA); |
| AnnaBridge | 189:f392fc9709a3 | 978 | } |
| AnnaBridge | 189:f392fc9709a3 | 979 | |
| AnnaBridge | 189:f392fc9709a3 | 980 | /** |
| AnnaBridge | 189:f392fc9709a3 | 981 | * @brief Disable DMA mode for reception |
| AnnaBridge | 189:f392fc9709a3 | 982 | * @rmtoll CR RXDMA LL_SWPMI_DisableDMAReq_RX |
| AnnaBridge | 189:f392fc9709a3 | 983 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 984 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 985 | */ |
| AnnaBridge | 189:f392fc9709a3 | 986 | __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 987 | { |
| AnnaBridge | 189:f392fc9709a3 | 988 | CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA); |
| AnnaBridge | 189:f392fc9709a3 | 989 | } |
| AnnaBridge | 189:f392fc9709a3 | 990 | |
| AnnaBridge | 189:f392fc9709a3 | 991 | /** |
| AnnaBridge | 189:f392fc9709a3 | 992 | * @brief Check if DMA mode for reception is enabled |
| AnnaBridge | 189:f392fc9709a3 | 993 | * @rmtoll CR RXDMA LL_SWPMI_IsEnabledDMAReq_RX |
| AnnaBridge | 189:f392fc9709a3 | 994 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 995 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 996 | */ |
| AnnaBridge | 189:f392fc9709a3 | 997 | __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 998 | { |
| AnnaBridge | 189:f392fc9709a3 | 999 | return (READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)); |
| AnnaBridge | 189:f392fc9709a3 | 1000 | } |
| AnnaBridge | 189:f392fc9709a3 | 1001 | |
| AnnaBridge | 189:f392fc9709a3 | 1002 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1003 | * @brief Enable DMA mode for transmission |
| AnnaBridge | 189:f392fc9709a3 | 1004 | * @rmtoll CR TXDMA LL_SWPMI_EnableDMAReq_TX |
| AnnaBridge | 189:f392fc9709a3 | 1005 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 1006 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1007 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1008 | __STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 1009 | { |
| AnnaBridge | 189:f392fc9709a3 | 1010 | SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA); |
| AnnaBridge | 189:f392fc9709a3 | 1011 | } |
| AnnaBridge | 189:f392fc9709a3 | 1012 | |
| AnnaBridge | 189:f392fc9709a3 | 1013 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1014 | * @brief Disable DMA mode for transmission |
| AnnaBridge | 189:f392fc9709a3 | 1015 | * @rmtoll CR TXDMA LL_SWPMI_DisableDMAReq_TX |
| AnnaBridge | 189:f392fc9709a3 | 1016 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 1017 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1018 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1019 | __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 1020 | { |
| AnnaBridge | 189:f392fc9709a3 | 1021 | CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA); |
| AnnaBridge | 189:f392fc9709a3 | 1022 | } |
| AnnaBridge | 189:f392fc9709a3 | 1023 | |
| AnnaBridge | 189:f392fc9709a3 | 1024 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1025 | * @brief Check if DMA mode for transmission is enabled |
| AnnaBridge | 189:f392fc9709a3 | 1026 | * @rmtoll CR TXDMA LL_SWPMI_IsEnabledDMAReq_TX |
| AnnaBridge | 189:f392fc9709a3 | 1027 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 1028 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1029 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1030 | __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 1031 | { |
| AnnaBridge | 189:f392fc9709a3 | 1032 | return (READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)); |
| AnnaBridge | 189:f392fc9709a3 | 1033 | } |
| AnnaBridge | 189:f392fc9709a3 | 1034 | |
| AnnaBridge | 189:f392fc9709a3 | 1035 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1036 | * @brief Get the data register address used for DMA transfer |
| AnnaBridge | 189:f392fc9709a3 | 1037 | * @rmtoll TDR TD LL_SWPMI_DMA_GetRegAddr\n |
| AnnaBridge | 189:f392fc9709a3 | 1038 | * RDR RD LL_SWPMI_DMA_GetRegAddr |
| AnnaBridge | 189:f392fc9709a3 | 1039 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 1040 | * @param Direction This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1041 | * @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT |
| AnnaBridge | 189:f392fc9709a3 | 1042 | * @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE |
| AnnaBridge | 189:f392fc9709a3 | 1043 | * @retval Address of data register |
| AnnaBridge | 189:f392fc9709a3 | 1044 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1045 | __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction) |
| AnnaBridge | 189:f392fc9709a3 | 1046 | { |
| AnnaBridge | 189:f392fc9709a3 | 1047 | register uint32_t data_reg_addr = 0; |
| AnnaBridge | 189:f392fc9709a3 | 1048 | |
| AnnaBridge | 189:f392fc9709a3 | 1049 | if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT) |
| AnnaBridge | 189:f392fc9709a3 | 1050 | { |
| AnnaBridge | 189:f392fc9709a3 | 1051 | /* return address of TDR register */ |
| AnnaBridge | 189:f392fc9709a3 | 1052 | data_reg_addr = (uint32_t)&(SWPMIx->TDR); |
| AnnaBridge | 189:f392fc9709a3 | 1053 | } |
| AnnaBridge | 189:f392fc9709a3 | 1054 | else |
| AnnaBridge | 189:f392fc9709a3 | 1055 | { |
| AnnaBridge | 189:f392fc9709a3 | 1056 | /* return address of RDR register */ |
| AnnaBridge | 189:f392fc9709a3 | 1057 | data_reg_addr = (uint32_t)&(SWPMIx->RDR); |
| AnnaBridge | 189:f392fc9709a3 | 1058 | } |
| AnnaBridge | 189:f392fc9709a3 | 1059 | |
| AnnaBridge | 189:f392fc9709a3 | 1060 | return data_reg_addr; |
| AnnaBridge | 189:f392fc9709a3 | 1061 | } |
| AnnaBridge | 189:f392fc9709a3 | 1062 | |
| AnnaBridge | 189:f392fc9709a3 | 1063 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1064 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1065 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1066 | |
| AnnaBridge | 189:f392fc9709a3 | 1067 | /** @defgroup SWPMI_LL_EF_Data_Management Data_Management |
| AnnaBridge | 189:f392fc9709a3 | 1068 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1069 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1070 | |
| AnnaBridge | 189:f392fc9709a3 | 1071 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1072 | * @brief Retrieve number of data bytes present in payload of received frame |
| AnnaBridge | 189:f392fc9709a3 | 1073 | * @rmtoll RFL RFL LL_SWPMI_GetReceiveFrameLength |
| AnnaBridge | 189:f392fc9709a3 | 1074 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 1075 | * @retval Value between Min_Data=0x00 and Max_Data=0x1F |
| AnnaBridge | 189:f392fc9709a3 | 1076 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1077 | __STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 1078 | { |
| AnnaBridge | 189:f392fc9709a3 | 1079 | return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL)); |
| AnnaBridge | 189:f392fc9709a3 | 1080 | } |
| AnnaBridge | 189:f392fc9709a3 | 1081 | |
| AnnaBridge | 189:f392fc9709a3 | 1082 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1083 | * @brief Transmit Data Register |
| AnnaBridge | 189:f392fc9709a3 | 1084 | * @rmtoll TDR TD LL_SWPMI_TransmitData32 |
| AnnaBridge | 189:f392fc9709a3 | 1085 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 1086 | * @param TxData Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF |
| AnnaBridge | 189:f392fc9709a3 | 1087 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1088 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1089 | __STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData) |
| AnnaBridge | 189:f392fc9709a3 | 1090 | { |
| AnnaBridge | 189:f392fc9709a3 | 1091 | WRITE_REG(SWPMIx->TDR, TxData); |
| AnnaBridge | 189:f392fc9709a3 | 1092 | } |
| AnnaBridge | 189:f392fc9709a3 | 1093 | |
| AnnaBridge | 189:f392fc9709a3 | 1094 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1095 | * @brief Receive Data Register |
| AnnaBridge | 189:f392fc9709a3 | 1096 | * @rmtoll RDR RD LL_SWPMI_ReceiveData32 |
| AnnaBridge | 189:f392fc9709a3 | 1097 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 1098 | * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF |
| AnnaBridge | 189:f392fc9709a3 | 1099 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1100 | __STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 1101 | { |
| AnnaBridge | 189:f392fc9709a3 | 1102 | return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD)); |
| AnnaBridge | 189:f392fc9709a3 | 1103 | } |
| AnnaBridge | 189:f392fc9709a3 | 1104 | |
| AnnaBridge | 189:f392fc9709a3 | 1105 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1106 | * @brief Enable SWP Transceiver Bypass |
| AnnaBridge | 189:f392fc9709a3 | 1107 | * @note The external interface for SWPMI is SWPMI_IO |
| AnnaBridge | 189:f392fc9709a3 | 1108 | * (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs) |
| AnnaBridge | 189:f392fc9709a3 | 1109 | * @rmtoll OR TBYP LL_SWPMI_EnableTXBypass |
| AnnaBridge | 189:f392fc9709a3 | 1110 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 1111 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1112 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1113 | __STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 1114 | { |
| AnnaBridge | 189:f392fc9709a3 | 1115 | CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP); |
| AnnaBridge | 189:f392fc9709a3 | 1116 | } |
| AnnaBridge | 189:f392fc9709a3 | 1117 | |
| AnnaBridge | 189:f392fc9709a3 | 1118 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1119 | * @brief Disable SWP Transceiver Bypass |
| AnnaBridge | 189:f392fc9709a3 | 1120 | * @note SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate |
| AnnaBridge | 189:f392fc9709a3 | 1121 | * function on GPIOs. This configuration is selected to connect an external transceiver |
| AnnaBridge | 189:f392fc9709a3 | 1122 | * @rmtoll OR TBYP LL_SWPMI_DisableTXBypass |
| AnnaBridge | 189:f392fc9709a3 | 1123 | * @param SWPMIx SWPMI Instance |
| AnnaBridge | 189:f392fc9709a3 | 1124 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1125 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1126 | __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx) |
| AnnaBridge | 189:f392fc9709a3 | 1127 | { |
| AnnaBridge | 189:f392fc9709a3 | 1128 | SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP); |
| AnnaBridge | 189:f392fc9709a3 | 1129 | } |
| AnnaBridge | 189:f392fc9709a3 | 1130 | |
| AnnaBridge | 189:f392fc9709a3 | 1131 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1132 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1133 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1134 | |
| AnnaBridge | 189:f392fc9709a3 | 1135 | #if defined(USE_FULL_LL_DRIVER) |
| AnnaBridge | 189:f392fc9709a3 | 1136 | /** @defgroup SWPMI_LL_EF_Init Initialization and de-initialization functions |
| AnnaBridge | 189:f392fc9709a3 | 1137 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1138 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1139 | |
| AnnaBridge | 189:f392fc9709a3 | 1140 | ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx); |
| AnnaBridge | 189:f392fc9709a3 | 1141 | ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 1142 | void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 1143 | |
| AnnaBridge | 189:f392fc9709a3 | 1144 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1145 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1146 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1147 | #endif /*USE_FULL_LL_DRIVER*/ |
| AnnaBridge | 189:f392fc9709a3 | 1148 | |
| AnnaBridge | 189:f392fc9709a3 | 1149 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1150 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1151 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1152 | |
| AnnaBridge | 189:f392fc9709a3 | 1153 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1154 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1155 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1156 | |
| AnnaBridge | 189:f392fc9709a3 | 1157 | #endif /* defined (SWPMI1) */ |
| AnnaBridge | 189:f392fc9709a3 | 1158 | |
| AnnaBridge | 189:f392fc9709a3 | 1159 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1160 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1161 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1162 | |
| AnnaBridge | 189:f392fc9709a3 | 1163 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 1164 | } |
| AnnaBridge | 189:f392fc9709a3 | 1165 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 1166 | |
| AnnaBridge | 189:f392fc9709a3 | 1167 | #endif /* __STM32L4xx_LL_SWPMI_H */ |
| AnnaBridge | 189:f392fc9709a3 | 1168 | |
| AnnaBridge | 189:f392fc9709a3 | 1169 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
