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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_ARM_STD/stm32l4xx_ll_pwr.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_ll_pwr.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of PWR LL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_LL_PWR_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_LL_PWR_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l4xx.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32L4xx_LL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | #if defined(PWR) |
| AnnaBridge | 189:f392fc9709a3 | 52 | |
| AnnaBridge | 189:f392fc9709a3 | 53 | /** @defgroup PWR_LL PWR |
| AnnaBridge | 189:f392fc9709a3 | 54 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 55 | */ |
| AnnaBridge | 189:f392fc9709a3 | 56 | |
| AnnaBridge | 189:f392fc9709a3 | 57 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 58 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 59 | |
| AnnaBridge | 189:f392fc9709a3 | 60 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 61 | |
| AnnaBridge | 189:f392fc9709a3 | 62 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 63 | |
| AnnaBridge | 189:f392fc9709a3 | 64 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 65 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 66 | /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 67 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 68 | */ |
| AnnaBridge | 189:f392fc9709a3 | 69 | |
| AnnaBridge | 189:f392fc9709a3 | 70 | /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines |
| AnnaBridge | 189:f392fc9709a3 | 71 | * @brief Flags defines which can be used with LL_PWR_WriteReg function |
| AnnaBridge | 189:f392fc9709a3 | 72 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 73 | */ |
| AnnaBridge | 189:f392fc9709a3 | 74 | #define LL_PWR_SCR_CSBF PWR_SCR_CSBF |
| AnnaBridge | 189:f392fc9709a3 | 75 | #define LL_PWR_SCR_CWUF PWR_SCR_CWUF |
| AnnaBridge | 189:f392fc9709a3 | 76 | #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5 |
| AnnaBridge | 189:f392fc9709a3 | 77 | #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4 |
| AnnaBridge | 189:f392fc9709a3 | 78 | #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3 |
| AnnaBridge | 189:f392fc9709a3 | 79 | #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2 |
| AnnaBridge | 189:f392fc9709a3 | 80 | #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 |
| AnnaBridge | 189:f392fc9709a3 | 81 | /** |
| AnnaBridge | 189:f392fc9709a3 | 82 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 83 | */ |
| AnnaBridge | 189:f392fc9709a3 | 84 | |
| AnnaBridge | 189:f392fc9709a3 | 85 | /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines |
| AnnaBridge | 189:f392fc9709a3 | 86 | * @brief Flags defines which can be used with LL_PWR_ReadReg function |
| AnnaBridge | 189:f392fc9709a3 | 87 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 88 | */ |
| AnnaBridge | 189:f392fc9709a3 | 89 | #define LL_PWR_SR1_WUFI PWR_SR1_WUFI |
| AnnaBridge | 189:f392fc9709a3 | 90 | #define LL_PWR_SR1_SBF PWR_SR1_SBF |
| AnnaBridge | 189:f392fc9709a3 | 91 | #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5 |
| AnnaBridge | 189:f392fc9709a3 | 92 | #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 |
| AnnaBridge | 189:f392fc9709a3 | 93 | #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3 |
| AnnaBridge | 189:f392fc9709a3 | 94 | #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2 |
| AnnaBridge | 189:f392fc9709a3 | 95 | #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1 |
| AnnaBridge | 189:f392fc9709a3 | 96 | #if defined(PWR_SR2_PVMO4) |
| AnnaBridge | 189:f392fc9709a3 | 97 | #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4 |
| AnnaBridge | 189:f392fc9709a3 | 98 | #endif /* PWR_SR2_PVMO4 */ |
| AnnaBridge | 189:f392fc9709a3 | 99 | #if defined(PWR_SR2_PVMO3) |
| AnnaBridge | 189:f392fc9709a3 | 100 | #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3 |
| AnnaBridge | 189:f392fc9709a3 | 101 | #endif /* PWR_SR2_PVMO3 */ |
| AnnaBridge | 189:f392fc9709a3 | 102 | #if defined(PWR_SR2_PVMO2) |
| AnnaBridge | 189:f392fc9709a3 | 103 | #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2 |
| AnnaBridge | 189:f392fc9709a3 | 104 | #endif /* PWR_SR2_PVMO2 */ |
| AnnaBridge | 189:f392fc9709a3 | 105 | #if defined(PWR_SR2_PVMO1) |
| AnnaBridge | 189:f392fc9709a3 | 106 | #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1 |
| AnnaBridge | 189:f392fc9709a3 | 107 | #endif /* PWR_SR2_PVMO1 */ |
| AnnaBridge | 189:f392fc9709a3 | 108 | #define LL_PWR_SR2_PVDO PWR_SR2_PVDO |
| AnnaBridge | 189:f392fc9709a3 | 109 | #define LL_PWR_SR2_VOSF PWR_SR2_VOSF |
| AnnaBridge | 189:f392fc9709a3 | 110 | #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF |
| AnnaBridge | 189:f392fc9709a3 | 111 | #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS |
| AnnaBridge | 189:f392fc9709a3 | 112 | /** |
| AnnaBridge | 189:f392fc9709a3 | 113 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 114 | */ |
| AnnaBridge | 189:f392fc9709a3 | 115 | |
| AnnaBridge | 189:f392fc9709a3 | 116 | /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE |
| AnnaBridge | 189:f392fc9709a3 | 117 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 118 | */ |
| AnnaBridge | 189:f392fc9709a3 | 119 | #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) |
| AnnaBridge | 189:f392fc9709a3 | 120 | #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) |
| AnnaBridge | 189:f392fc9709a3 | 121 | /** |
| AnnaBridge | 189:f392fc9709a3 | 122 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 123 | */ |
| AnnaBridge | 189:f392fc9709a3 | 124 | |
| AnnaBridge | 189:f392fc9709a3 | 125 | /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR |
| AnnaBridge | 189:f392fc9709a3 | 126 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 127 | */ |
| AnnaBridge | 189:f392fc9709a3 | 128 | #define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0) |
| AnnaBridge | 189:f392fc9709a3 | 129 | #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1) |
| AnnaBridge | 189:f392fc9709a3 | 130 | #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2) |
| AnnaBridge | 189:f392fc9709a3 | 131 | #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY) |
| AnnaBridge | 189:f392fc9709a3 | 132 | #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN) |
| AnnaBridge | 189:f392fc9709a3 | 133 | /** |
| AnnaBridge | 189:f392fc9709a3 | 134 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 135 | */ |
| AnnaBridge | 189:f392fc9709a3 | 136 | |
| AnnaBridge | 189:f392fc9709a3 | 137 | /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring |
| AnnaBridge | 189:f392fc9709a3 | 138 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 139 | */ |
| AnnaBridge | 189:f392fc9709a3 | 140 | #if defined(PWR_CR2_PVME1) |
| AnnaBridge | 189:f392fc9709a3 | 141 | #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */ |
| AnnaBridge | 189:f392fc9709a3 | 142 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 143 | #if defined(PWR_CR2_PVME2) |
| AnnaBridge | 189:f392fc9709a3 | 144 | #define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */ |
| AnnaBridge | 189:f392fc9709a3 | 145 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 146 | #if defined(PWR_CR2_PVME3) |
| AnnaBridge | 189:f392fc9709a3 | 147 | #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */ |
| AnnaBridge | 189:f392fc9709a3 | 148 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 149 | #if defined(PWR_CR2_PVME4) |
| AnnaBridge | 189:f392fc9709a3 | 150 | #define LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */ |
| AnnaBridge | 189:f392fc9709a3 | 151 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 152 | /** |
| AnnaBridge | 189:f392fc9709a3 | 153 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 154 | */ |
| AnnaBridge | 189:f392fc9709a3 | 155 | |
| AnnaBridge | 189:f392fc9709a3 | 156 | /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL |
| AnnaBridge | 189:f392fc9709a3 | 157 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 158 | */ |
| AnnaBridge | 189:f392fc9709a3 | 159 | #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */ |
| AnnaBridge | 189:f392fc9709a3 | 160 | #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */ |
| AnnaBridge | 189:f392fc9709a3 | 161 | #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */ |
| AnnaBridge | 189:f392fc9709a3 | 162 | #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */ |
| AnnaBridge | 189:f392fc9709a3 | 163 | #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */ |
| AnnaBridge | 189:f392fc9709a3 | 164 | #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */ |
| AnnaBridge | 189:f392fc9709a3 | 165 | #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */ |
| AnnaBridge | 189:f392fc9709a3 | 166 | #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */ |
| AnnaBridge | 189:f392fc9709a3 | 167 | /** |
| AnnaBridge | 189:f392fc9709a3 | 168 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 169 | */ |
| AnnaBridge | 189:f392fc9709a3 | 170 | |
| AnnaBridge | 189:f392fc9709a3 | 171 | /** @defgroup PWR_LL_EC_WAKEUP WAKEUP |
| AnnaBridge | 189:f392fc9709a3 | 172 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 173 | */ |
| AnnaBridge | 189:f392fc9709a3 | 174 | #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1) |
| AnnaBridge | 189:f392fc9709a3 | 175 | #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2) |
| AnnaBridge | 189:f392fc9709a3 | 176 | #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3) |
| AnnaBridge | 189:f392fc9709a3 | 177 | #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4) |
| AnnaBridge | 189:f392fc9709a3 | 178 | #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5) |
| AnnaBridge | 189:f392fc9709a3 | 179 | /** |
| AnnaBridge | 189:f392fc9709a3 | 180 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 181 | */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | |
| AnnaBridge | 189:f392fc9709a3 | 183 | /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR |
| AnnaBridge | 189:f392fc9709a3 | 184 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 185 | */ |
| AnnaBridge | 189:f392fc9709a3 | 186 | #define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 187 | #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS) |
| AnnaBridge | 189:f392fc9709a3 | 188 | /** |
| AnnaBridge | 189:f392fc9709a3 | 189 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 190 | */ |
| AnnaBridge | 189:f392fc9709a3 | 191 | |
| AnnaBridge | 189:f392fc9709a3 | 192 | /** @defgroup PWR_LL_EC_GPIO GPIO |
| AnnaBridge | 189:f392fc9709a3 | 193 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 194 | */ |
| AnnaBridge | 189:f392fc9709a3 | 195 | #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA))) |
| AnnaBridge | 189:f392fc9709a3 | 196 | #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB))) |
| AnnaBridge | 189:f392fc9709a3 | 197 | #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC))) |
| AnnaBridge | 189:f392fc9709a3 | 198 | #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD))) |
| AnnaBridge | 189:f392fc9709a3 | 199 | #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE))) |
| AnnaBridge | 189:f392fc9709a3 | 200 | #if defined(GPIOF) |
| AnnaBridge | 189:f392fc9709a3 | 201 | #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF))) |
| AnnaBridge | 189:f392fc9709a3 | 202 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 203 | #if defined(GPIOG) |
| AnnaBridge | 189:f392fc9709a3 | 204 | #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG))) |
| AnnaBridge | 189:f392fc9709a3 | 205 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 206 | #if defined(GPIOH) |
| AnnaBridge | 189:f392fc9709a3 | 207 | #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH))) |
| AnnaBridge | 189:f392fc9709a3 | 208 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 209 | #if defined(GPIOI) |
| AnnaBridge | 189:f392fc9709a3 | 210 | #define LL_PWR_GPIO_I ((uint32_t)(&(PWR->PUCRI))) |
| AnnaBridge | 189:f392fc9709a3 | 211 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 212 | /** |
| AnnaBridge | 189:f392fc9709a3 | 213 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 214 | */ |
| AnnaBridge | 189:f392fc9709a3 | 215 | |
| AnnaBridge | 189:f392fc9709a3 | 216 | /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT |
| AnnaBridge | 189:f392fc9709a3 | 217 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 218 | */ |
| AnnaBridge | 189:f392fc9709a3 | 219 | #define LL_PWR_GPIO_BIT_0 (0x00000001U) |
| AnnaBridge | 189:f392fc9709a3 | 220 | #define LL_PWR_GPIO_BIT_1 (0x00000002U) |
| AnnaBridge | 189:f392fc9709a3 | 221 | #define LL_PWR_GPIO_BIT_2 (0x00000004U) |
| AnnaBridge | 189:f392fc9709a3 | 222 | #define LL_PWR_GPIO_BIT_3 (0x00000008U) |
| AnnaBridge | 189:f392fc9709a3 | 223 | #define LL_PWR_GPIO_BIT_4 (0x00000010U) |
| AnnaBridge | 189:f392fc9709a3 | 224 | #define LL_PWR_GPIO_BIT_5 (0x00000020U) |
| AnnaBridge | 189:f392fc9709a3 | 225 | #define LL_PWR_GPIO_BIT_6 (0x00000040U) |
| AnnaBridge | 189:f392fc9709a3 | 226 | #define LL_PWR_GPIO_BIT_7 (0x00000080U) |
| AnnaBridge | 189:f392fc9709a3 | 227 | #define LL_PWR_GPIO_BIT_8 (0x00000100U) |
| AnnaBridge | 189:f392fc9709a3 | 228 | #define LL_PWR_GPIO_BIT_9 (0x00000200U) |
| AnnaBridge | 189:f392fc9709a3 | 229 | #define LL_PWR_GPIO_BIT_10 (0x00000400U) |
| AnnaBridge | 189:f392fc9709a3 | 230 | #define LL_PWR_GPIO_BIT_11 (0x00000800U) |
| AnnaBridge | 189:f392fc9709a3 | 231 | #define LL_PWR_GPIO_BIT_12 (0x00001000U) |
| AnnaBridge | 189:f392fc9709a3 | 232 | #define LL_PWR_GPIO_BIT_13 (0x00002000U) |
| AnnaBridge | 189:f392fc9709a3 | 233 | #define LL_PWR_GPIO_BIT_14 (0x00004000U) |
| AnnaBridge | 189:f392fc9709a3 | 234 | #define LL_PWR_GPIO_BIT_15 (0x00008000U) |
| AnnaBridge | 189:f392fc9709a3 | 235 | /** |
| AnnaBridge | 189:f392fc9709a3 | 236 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 237 | */ |
| AnnaBridge | 189:f392fc9709a3 | 238 | |
| AnnaBridge | 189:f392fc9709a3 | 239 | /** |
| AnnaBridge | 189:f392fc9709a3 | 240 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 241 | */ |
| AnnaBridge | 189:f392fc9709a3 | 242 | |
| AnnaBridge | 189:f392fc9709a3 | 243 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 244 | /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 245 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 246 | */ |
| AnnaBridge | 189:f392fc9709a3 | 247 | |
| AnnaBridge | 189:f392fc9709a3 | 248 | /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros |
| AnnaBridge | 189:f392fc9709a3 | 249 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 250 | */ |
| AnnaBridge | 189:f392fc9709a3 | 251 | |
| AnnaBridge | 189:f392fc9709a3 | 252 | /** |
| AnnaBridge | 189:f392fc9709a3 | 253 | * @brief Write a value in PWR register |
| AnnaBridge | 189:f392fc9709a3 | 254 | * @param __REG__ Register to be written |
| AnnaBridge | 189:f392fc9709a3 | 255 | * @param __VALUE__ Value to be written in the register |
| AnnaBridge | 189:f392fc9709a3 | 256 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 257 | */ |
| AnnaBridge | 189:f392fc9709a3 | 258 | #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) |
| AnnaBridge | 189:f392fc9709a3 | 259 | |
| AnnaBridge | 189:f392fc9709a3 | 260 | /** |
| AnnaBridge | 189:f392fc9709a3 | 261 | * @brief Read a value in PWR register |
| AnnaBridge | 189:f392fc9709a3 | 262 | * @param __REG__ Register to be read |
| AnnaBridge | 189:f392fc9709a3 | 263 | * @retval Register value |
| AnnaBridge | 189:f392fc9709a3 | 264 | */ |
| AnnaBridge | 189:f392fc9709a3 | 265 | #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) |
| AnnaBridge | 189:f392fc9709a3 | 266 | /** |
| AnnaBridge | 189:f392fc9709a3 | 267 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 268 | */ |
| AnnaBridge | 189:f392fc9709a3 | 269 | |
| AnnaBridge | 189:f392fc9709a3 | 270 | /** |
| AnnaBridge | 189:f392fc9709a3 | 271 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 272 | */ |
| AnnaBridge | 189:f392fc9709a3 | 273 | |
| AnnaBridge | 189:f392fc9709a3 | 274 | |
| AnnaBridge | 189:f392fc9709a3 | 275 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 276 | /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 277 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 278 | */ |
| AnnaBridge | 189:f392fc9709a3 | 279 | |
| AnnaBridge | 189:f392fc9709a3 | 280 | /** @defgroup PWR_LL_EF_Configuration Configuration |
| AnnaBridge | 189:f392fc9709a3 | 281 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 282 | */ |
| AnnaBridge | 189:f392fc9709a3 | 283 | |
| AnnaBridge | 189:f392fc9709a3 | 284 | /** |
| AnnaBridge | 189:f392fc9709a3 | 285 | * @brief Switch the regulator from main mode to low-power mode |
| AnnaBridge | 189:f392fc9709a3 | 286 | * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode |
| AnnaBridge | 189:f392fc9709a3 | 287 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 288 | */ |
| AnnaBridge | 189:f392fc9709a3 | 289 | __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 290 | { |
| AnnaBridge | 189:f392fc9709a3 | 291 | SET_BIT(PWR->CR1, PWR_CR1_LPR); |
| AnnaBridge | 189:f392fc9709a3 | 292 | } |
| AnnaBridge | 189:f392fc9709a3 | 293 | |
| AnnaBridge | 189:f392fc9709a3 | 294 | /** |
| AnnaBridge | 189:f392fc9709a3 | 295 | * @brief Switch the regulator from low-power mode to main mode |
| AnnaBridge | 189:f392fc9709a3 | 296 | * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode |
| AnnaBridge | 189:f392fc9709a3 | 297 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 298 | */ |
| AnnaBridge | 189:f392fc9709a3 | 299 | __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 300 | { |
| AnnaBridge | 189:f392fc9709a3 | 301 | CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); |
| AnnaBridge | 189:f392fc9709a3 | 302 | } |
| AnnaBridge | 189:f392fc9709a3 | 303 | |
| AnnaBridge | 189:f392fc9709a3 | 304 | /** |
| AnnaBridge | 189:f392fc9709a3 | 305 | * @brief Switch from run main mode to run low-power mode. |
| AnnaBridge | 189:f392fc9709a3 | 306 | * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode |
| AnnaBridge | 189:f392fc9709a3 | 307 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 308 | */ |
| AnnaBridge | 189:f392fc9709a3 | 309 | __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 310 | { |
| AnnaBridge | 189:f392fc9709a3 | 311 | LL_PWR_EnableLowPowerRunMode(); |
| AnnaBridge | 189:f392fc9709a3 | 312 | } |
| AnnaBridge | 189:f392fc9709a3 | 313 | |
| AnnaBridge | 189:f392fc9709a3 | 314 | /** |
| AnnaBridge | 189:f392fc9709a3 | 315 | * @brief Switch from run main mode to low-power mode. |
| AnnaBridge | 189:f392fc9709a3 | 316 | * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode |
| AnnaBridge | 189:f392fc9709a3 | 317 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 318 | */ |
| AnnaBridge | 189:f392fc9709a3 | 319 | __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 320 | { |
| AnnaBridge | 189:f392fc9709a3 | 321 | LL_PWR_DisableLowPowerRunMode(); |
| AnnaBridge | 189:f392fc9709a3 | 322 | } |
| AnnaBridge | 189:f392fc9709a3 | 323 | |
| AnnaBridge | 189:f392fc9709a3 | 324 | /** |
| AnnaBridge | 189:f392fc9709a3 | 325 | * @brief Check if the regulator is in low-power mode |
| AnnaBridge | 189:f392fc9709a3 | 326 | * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode |
| AnnaBridge | 189:f392fc9709a3 | 327 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 328 | */ |
| AnnaBridge | 189:f392fc9709a3 | 329 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 330 | { |
| AnnaBridge | 189:f392fc9709a3 | 331 | return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)); |
| AnnaBridge | 189:f392fc9709a3 | 332 | } |
| AnnaBridge | 189:f392fc9709a3 | 333 | |
| AnnaBridge | 189:f392fc9709a3 | 334 | /** |
| AnnaBridge | 189:f392fc9709a3 | 335 | * @brief Set the main internal regulator output voltage |
| AnnaBridge | 189:f392fc9709a3 | 336 | * @note This configuration may be completed with LL_PWR_EnableRange1BoostMode() on STM32L4Rx/STM32L4Sx devices. |
| AnnaBridge | 189:f392fc9709a3 | 337 | * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling |
| AnnaBridge | 189:f392fc9709a3 | 338 | * @param VoltageScaling This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 339 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 |
| AnnaBridge | 189:f392fc9709a3 | 340 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 |
| AnnaBridge | 189:f392fc9709a3 | 341 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 342 | */ |
| AnnaBridge | 189:f392fc9709a3 | 343 | __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) |
| AnnaBridge | 189:f392fc9709a3 | 344 | { |
| AnnaBridge | 189:f392fc9709a3 | 345 | MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); |
| AnnaBridge | 189:f392fc9709a3 | 346 | } |
| AnnaBridge | 189:f392fc9709a3 | 347 | |
| AnnaBridge | 189:f392fc9709a3 | 348 | /** |
| AnnaBridge | 189:f392fc9709a3 | 349 | * @brief Get the main internal regulator output voltage |
| AnnaBridge | 189:f392fc9709a3 | 350 | * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling |
| AnnaBridge | 189:f392fc9709a3 | 351 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 352 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 |
| AnnaBridge | 189:f392fc9709a3 | 353 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 |
| AnnaBridge | 189:f392fc9709a3 | 354 | */ |
| AnnaBridge | 189:f392fc9709a3 | 355 | __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) |
| AnnaBridge | 189:f392fc9709a3 | 356 | { |
| AnnaBridge | 189:f392fc9709a3 | 357 | return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); |
| AnnaBridge | 189:f392fc9709a3 | 358 | } |
| AnnaBridge | 189:f392fc9709a3 | 359 | |
| AnnaBridge | 189:f392fc9709a3 | 360 | #if defined(PWR_CR5_R1MODE) |
| AnnaBridge | 189:f392fc9709a3 | 361 | /** |
| AnnaBridge | 189:f392fc9709a3 | 362 | * @brief Enable main regulator voltage range 1 boost mode |
| AnnaBridge | 189:f392fc9709a3 | 363 | * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode |
| AnnaBridge | 189:f392fc9709a3 | 364 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 365 | */ |
| AnnaBridge | 189:f392fc9709a3 | 366 | __STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 367 | { |
| AnnaBridge | 189:f392fc9709a3 | 368 | CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); |
| AnnaBridge | 189:f392fc9709a3 | 369 | } |
| AnnaBridge | 189:f392fc9709a3 | 370 | |
| AnnaBridge | 189:f392fc9709a3 | 371 | /** |
| AnnaBridge | 189:f392fc9709a3 | 372 | * @brief Disable main regulator voltage range 1 boost mode |
| AnnaBridge | 189:f392fc9709a3 | 373 | * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode |
| AnnaBridge | 189:f392fc9709a3 | 374 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 375 | */ |
| AnnaBridge | 189:f392fc9709a3 | 376 | __STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 377 | { |
| AnnaBridge | 189:f392fc9709a3 | 378 | SET_BIT(PWR->CR5, PWR_CR5_R1MODE); |
| AnnaBridge | 189:f392fc9709a3 | 379 | } |
| AnnaBridge | 189:f392fc9709a3 | 380 | |
| AnnaBridge | 189:f392fc9709a3 | 381 | /** |
| AnnaBridge | 189:f392fc9709a3 | 382 | * @brief Check if the main regulator voltage range 1 boost mode is enabled |
| AnnaBridge | 189:f392fc9709a3 | 383 | * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode |
| AnnaBridge | 189:f392fc9709a3 | 384 | * @retval Inverted state of bit (0 or 1). |
| AnnaBridge | 189:f392fc9709a3 | 385 | */ |
| AnnaBridge | 189:f392fc9709a3 | 386 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 387 | { |
| AnnaBridge | 189:f392fc9709a3 | 388 | return (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == RESET); |
| AnnaBridge | 189:f392fc9709a3 | 389 | } |
| AnnaBridge | 189:f392fc9709a3 | 390 | #endif /* PWR_CR5_R1MODE */ |
| AnnaBridge | 189:f392fc9709a3 | 391 | |
| AnnaBridge | 189:f392fc9709a3 | 392 | /** |
| AnnaBridge | 189:f392fc9709a3 | 393 | * @brief Enable access to the backup domain |
| AnnaBridge | 189:f392fc9709a3 | 394 | * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess |
| AnnaBridge | 189:f392fc9709a3 | 395 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 396 | */ |
| AnnaBridge | 189:f392fc9709a3 | 397 | __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) |
| AnnaBridge | 189:f392fc9709a3 | 398 | { |
| AnnaBridge | 189:f392fc9709a3 | 399 | SET_BIT(PWR->CR1, PWR_CR1_DBP); |
| AnnaBridge | 189:f392fc9709a3 | 400 | } |
| AnnaBridge | 189:f392fc9709a3 | 401 | |
| AnnaBridge | 189:f392fc9709a3 | 402 | /** |
| AnnaBridge | 189:f392fc9709a3 | 403 | * @brief Disable access to the backup domain |
| AnnaBridge | 189:f392fc9709a3 | 404 | * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess |
| AnnaBridge | 189:f392fc9709a3 | 405 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 406 | */ |
| AnnaBridge | 189:f392fc9709a3 | 407 | __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) |
| AnnaBridge | 189:f392fc9709a3 | 408 | { |
| AnnaBridge | 189:f392fc9709a3 | 409 | CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); |
| AnnaBridge | 189:f392fc9709a3 | 410 | } |
| AnnaBridge | 189:f392fc9709a3 | 411 | |
| AnnaBridge | 189:f392fc9709a3 | 412 | /** |
| AnnaBridge | 189:f392fc9709a3 | 413 | * @brief Check if the backup domain is enabled |
| AnnaBridge | 189:f392fc9709a3 | 414 | * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess |
| AnnaBridge | 189:f392fc9709a3 | 415 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 416 | */ |
| AnnaBridge | 189:f392fc9709a3 | 417 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) |
| AnnaBridge | 189:f392fc9709a3 | 418 | { |
| AnnaBridge | 189:f392fc9709a3 | 419 | return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)); |
| AnnaBridge | 189:f392fc9709a3 | 420 | } |
| AnnaBridge | 189:f392fc9709a3 | 421 | |
| AnnaBridge | 189:f392fc9709a3 | 422 | /** |
| AnnaBridge | 189:f392fc9709a3 | 423 | * @brief Set Low-Power mode |
| AnnaBridge | 189:f392fc9709a3 | 424 | * @rmtoll CR1 LPMS LL_PWR_SetPowerMode |
| AnnaBridge | 189:f392fc9709a3 | 425 | * @param LowPowerMode This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 426 | * @arg @ref LL_PWR_MODE_STOP0 |
| AnnaBridge | 189:f392fc9709a3 | 427 | * @arg @ref LL_PWR_MODE_STOP1 |
| AnnaBridge | 189:f392fc9709a3 | 428 | * @arg @ref LL_PWR_MODE_STOP2 |
| AnnaBridge | 189:f392fc9709a3 | 429 | * @arg @ref LL_PWR_MODE_STANDBY |
| AnnaBridge | 189:f392fc9709a3 | 430 | * @arg @ref LL_PWR_MODE_SHUTDOWN |
| AnnaBridge | 189:f392fc9709a3 | 431 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 432 | */ |
| AnnaBridge | 189:f392fc9709a3 | 433 | __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) |
| AnnaBridge | 189:f392fc9709a3 | 434 | { |
| AnnaBridge | 189:f392fc9709a3 | 435 | MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); |
| AnnaBridge | 189:f392fc9709a3 | 436 | } |
| AnnaBridge | 189:f392fc9709a3 | 437 | |
| AnnaBridge | 189:f392fc9709a3 | 438 | /** |
| AnnaBridge | 189:f392fc9709a3 | 439 | * @brief Get Low-Power mode |
| AnnaBridge | 189:f392fc9709a3 | 440 | * @rmtoll CR1 LPMS LL_PWR_GetPowerMode |
| AnnaBridge | 189:f392fc9709a3 | 441 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 442 | * @arg @ref LL_PWR_MODE_STOP0 |
| AnnaBridge | 189:f392fc9709a3 | 443 | * @arg @ref LL_PWR_MODE_STOP1 |
| AnnaBridge | 189:f392fc9709a3 | 444 | * @arg @ref LL_PWR_MODE_STOP2 |
| AnnaBridge | 189:f392fc9709a3 | 445 | * @arg @ref LL_PWR_MODE_STANDBY |
| AnnaBridge | 189:f392fc9709a3 | 446 | * @arg @ref LL_PWR_MODE_SHUTDOWN |
| AnnaBridge | 189:f392fc9709a3 | 447 | */ |
| AnnaBridge | 189:f392fc9709a3 | 448 | __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 449 | { |
| AnnaBridge | 189:f392fc9709a3 | 450 | return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); |
| AnnaBridge | 189:f392fc9709a3 | 451 | } |
| AnnaBridge | 189:f392fc9709a3 | 452 | |
| AnnaBridge | 189:f392fc9709a3 | 453 | #if defined(PWR_CR1_RRSTP) |
| AnnaBridge | 189:f392fc9709a3 | 454 | /** |
| AnnaBridge | 189:f392fc9709a3 | 455 | * @brief Enable SRAM3 content retention in Stop mode |
| AnnaBridge | 189:f392fc9709a3 | 456 | * @rmtoll CR1 RRSTP LL_PWR_EnableSRAM3Retention |
| AnnaBridge | 189:f392fc9709a3 | 457 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 458 | */ |
| AnnaBridge | 189:f392fc9709a3 | 459 | __STATIC_INLINE void LL_PWR_EnableSRAM3Retention(void) |
| AnnaBridge | 189:f392fc9709a3 | 460 | { |
| AnnaBridge | 189:f392fc9709a3 | 461 | SET_BIT(PWR->CR1, PWR_CR1_RRSTP); |
| AnnaBridge | 189:f392fc9709a3 | 462 | } |
| AnnaBridge | 189:f392fc9709a3 | 463 | |
| AnnaBridge | 189:f392fc9709a3 | 464 | /** |
| AnnaBridge | 189:f392fc9709a3 | 465 | * @brief Disable SRAM3 content retention in Stop mode |
| AnnaBridge | 189:f392fc9709a3 | 466 | * @rmtoll CR1 RRSTP LL_PWR_DisableSRAM3Retention |
| AnnaBridge | 189:f392fc9709a3 | 467 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 468 | */ |
| AnnaBridge | 189:f392fc9709a3 | 469 | __STATIC_INLINE void LL_PWR_DisableSRAM3Retention(void) |
| AnnaBridge | 189:f392fc9709a3 | 470 | { |
| AnnaBridge | 189:f392fc9709a3 | 471 | CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP); |
| AnnaBridge | 189:f392fc9709a3 | 472 | } |
| AnnaBridge | 189:f392fc9709a3 | 473 | |
| AnnaBridge | 189:f392fc9709a3 | 474 | /** |
| AnnaBridge | 189:f392fc9709a3 | 475 | * @brief Check if SRAM3 content retention in Stop mode is enabled |
| AnnaBridge | 189:f392fc9709a3 | 476 | * @rmtoll CR1 RRSTP LL_PWR_IsEnabledSRAM3Retention |
| AnnaBridge | 189:f392fc9709a3 | 477 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 478 | */ |
| AnnaBridge | 189:f392fc9709a3 | 479 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM3Retention(void) |
| AnnaBridge | 189:f392fc9709a3 | 480 | { |
| AnnaBridge | 189:f392fc9709a3 | 481 | return (READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP)); |
| AnnaBridge | 189:f392fc9709a3 | 482 | } |
| AnnaBridge | 189:f392fc9709a3 | 483 | #endif /* PWR_CR1_RRSTP */ |
| AnnaBridge | 189:f392fc9709a3 | 484 | |
| AnnaBridge | 189:f392fc9709a3 | 485 | #if defined(PWR_CR3_DSIPDEN) |
| AnnaBridge | 189:f392fc9709a3 | 486 | /** |
| AnnaBridge | 189:f392fc9709a3 | 487 | * @brief Enable pull-down activation on DSI pins |
| AnnaBridge | 189:f392fc9709a3 | 488 | * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPinsPDActivation |
| AnnaBridge | 189:f392fc9709a3 | 489 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 490 | */ |
| AnnaBridge | 189:f392fc9709a3 | 491 | __STATIC_INLINE void LL_PWR_EnableDSIPinsPDActivation(void) |
| AnnaBridge | 189:f392fc9709a3 | 492 | { |
| AnnaBridge | 189:f392fc9709a3 | 493 | SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); |
| AnnaBridge | 189:f392fc9709a3 | 494 | } |
| AnnaBridge | 189:f392fc9709a3 | 495 | |
| AnnaBridge | 189:f392fc9709a3 | 496 | /** |
| AnnaBridge | 189:f392fc9709a3 | 497 | * @brief Disable pull-down activation on DSI pins |
| AnnaBridge | 189:f392fc9709a3 | 498 | * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPinsPDActivation |
| AnnaBridge | 189:f392fc9709a3 | 499 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 500 | */ |
| AnnaBridge | 189:f392fc9709a3 | 501 | __STATIC_INLINE void LL_PWR_DisableDSIPinsPDActivation(void) |
| AnnaBridge | 189:f392fc9709a3 | 502 | { |
| AnnaBridge | 189:f392fc9709a3 | 503 | CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); |
| AnnaBridge | 189:f392fc9709a3 | 504 | } |
| AnnaBridge | 189:f392fc9709a3 | 505 | |
| AnnaBridge | 189:f392fc9709a3 | 506 | /** |
| AnnaBridge | 189:f392fc9709a3 | 507 | * @brief Check if pull-down activation on DSI pins is enabled |
| AnnaBridge | 189:f392fc9709a3 | 508 | * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPinsPDActivation |
| AnnaBridge | 189:f392fc9709a3 | 509 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 510 | */ |
| AnnaBridge | 189:f392fc9709a3 | 511 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPinsPDActivation(void) |
| AnnaBridge | 189:f392fc9709a3 | 512 | { |
| AnnaBridge | 189:f392fc9709a3 | 513 | return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)); |
| AnnaBridge | 189:f392fc9709a3 | 514 | } |
| AnnaBridge | 189:f392fc9709a3 | 515 | #endif /* PWR_CR3_DSIPDEN */ |
| AnnaBridge | 189:f392fc9709a3 | 516 | |
| AnnaBridge | 189:f392fc9709a3 | 517 | #if defined(PWR_CR2_PVME1) |
| AnnaBridge | 189:f392fc9709a3 | 518 | /** |
| AnnaBridge | 189:f392fc9709a3 | 519 | * @brief Enable VDDUSB supply |
| AnnaBridge | 189:f392fc9709a3 | 520 | * @rmtoll CR2 USV LL_PWR_EnableVddUSB |
| AnnaBridge | 189:f392fc9709a3 | 521 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 522 | */ |
| AnnaBridge | 189:f392fc9709a3 | 523 | __STATIC_INLINE void LL_PWR_EnableVddUSB(void) |
| AnnaBridge | 189:f392fc9709a3 | 524 | { |
| AnnaBridge | 189:f392fc9709a3 | 525 | SET_BIT(PWR->CR2, PWR_CR2_USV); |
| AnnaBridge | 189:f392fc9709a3 | 526 | } |
| AnnaBridge | 189:f392fc9709a3 | 527 | |
| AnnaBridge | 189:f392fc9709a3 | 528 | /** |
| AnnaBridge | 189:f392fc9709a3 | 529 | * @brief Disable VDDUSB supply |
| AnnaBridge | 189:f392fc9709a3 | 530 | * @rmtoll CR2 USV LL_PWR_DisableVddUSB |
| AnnaBridge | 189:f392fc9709a3 | 531 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 532 | */ |
| AnnaBridge | 189:f392fc9709a3 | 533 | __STATIC_INLINE void LL_PWR_DisableVddUSB(void) |
| AnnaBridge | 189:f392fc9709a3 | 534 | { |
| AnnaBridge | 189:f392fc9709a3 | 535 | CLEAR_BIT(PWR->CR2, PWR_CR2_USV); |
| AnnaBridge | 189:f392fc9709a3 | 536 | } |
| AnnaBridge | 189:f392fc9709a3 | 537 | |
| AnnaBridge | 189:f392fc9709a3 | 538 | /** |
| AnnaBridge | 189:f392fc9709a3 | 539 | * @brief Check if VDDUSB supply is enabled |
| AnnaBridge | 189:f392fc9709a3 | 540 | * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB |
| AnnaBridge | 189:f392fc9709a3 | 541 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 542 | */ |
| AnnaBridge | 189:f392fc9709a3 | 543 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) |
| AnnaBridge | 189:f392fc9709a3 | 544 | { |
| AnnaBridge | 189:f392fc9709a3 | 545 | return (READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)); |
| AnnaBridge | 189:f392fc9709a3 | 546 | } |
| AnnaBridge | 189:f392fc9709a3 | 547 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 548 | |
| AnnaBridge | 189:f392fc9709a3 | 549 | #if defined(PWR_CR2_IOSV) |
| AnnaBridge | 189:f392fc9709a3 | 550 | /** |
| AnnaBridge | 189:f392fc9709a3 | 551 | * @brief Enable VDDIO2 supply |
| AnnaBridge | 189:f392fc9709a3 | 552 | * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2 |
| AnnaBridge | 189:f392fc9709a3 | 553 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 554 | */ |
| AnnaBridge | 189:f392fc9709a3 | 555 | __STATIC_INLINE void LL_PWR_EnableVddIO2(void) |
| AnnaBridge | 189:f392fc9709a3 | 556 | { |
| AnnaBridge | 189:f392fc9709a3 | 557 | SET_BIT(PWR->CR2, PWR_CR2_IOSV); |
| AnnaBridge | 189:f392fc9709a3 | 558 | } |
| AnnaBridge | 189:f392fc9709a3 | 559 | |
| AnnaBridge | 189:f392fc9709a3 | 560 | /** |
| AnnaBridge | 189:f392fc9709a3 | 561 | * @brief Disable VDDIO2 supply |
| AnnaBridge | 189:f392fc9709a3 | 562 | * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2 |
| AnnaBridge | 189:f392fc9709a3 | 563 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 564 | */ |
| AnnaBridge | 189:f392fc9709a3 | 565 | __STATIC_INLINE void LL_PWR_DisableVddIO2(void) |
| AnnaBridge | 189:f392fc9709a3 | 566 | { |
| AnnaBridge | 189:f392fc9709a3 | 567 | CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); |
| AnnaBridge | 189:f392fc9709a3 | 568 | } |
| AnnaBridge | 189:f392fc9709a3 | 569 | |
| AnnaBridge | 189:f392fc9709a3 | 570 | /** |
| AnnaBridge | 189:f392fc9709a3 | 571 | * @brief Check if VDDIO2 supply is enabled |
| AnnaBridge | 189:f392fc9709a3 | 572 | * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2 |
| AnnaBridge | 189:f392fc9709a3 | 573 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 574 | */ |
| AnnaBridge | 189:f392fc9709a3 | 575 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) |
| AnnaBridge | 189:f392fc9709a3 | 576 | { |
| AnnaBridge | 189:f392fc9709a3 | 577 | return (READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)); |
| AnnaBridge | 189:f392fc9709a3 | 578 | } |
| AnnaBridge | 189:f392fc9709a3 | 579 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 580 | |
| AnnaBridge | 189:f392fc9709a3 | 581 | /** |
| AnnaBridge | 189:f392fc9709a3 | 582 | * @brief Enable the Power Voltage Monitoring on a peripheral |
| AnnaBridge | 189:f392fc9709a3 | 583 | * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n |
| AnnaBridge | 189:f392fc9709a3 | 584 | * CR2 PVME2 LL_PWR_EnablePVM\n |
| AnnaBridge | 189:f392fc9709a3 | 585 | * CR2 PVME3 LL_PWR_EnablePVM\n |
| AnnaBridge | 189:f392fc9709a3 | 586 | * CR2 PVME4 LL_PWR_EnablePVM |
| AnnaBridge | 189:f392fc9709a3 | 587 | * @param PeriphVoltage This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 588 | * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) |
| AnnaBridge | 189:f392fc9709a3 | 589 | * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) |
| AnnaBridge | 189:f392fc9709a3 | 590 | * @arg @ref LL_PWR_PVM_VDDA_1_62V |
| AnnaBridge | 189:f392fc9709a3 | 591 | * @arg @ref LL_PWR_PVM_VDDA_2_2V |
| AnnaBridge | 189:f392fc9709a3 | 592 | * |
| AnnaBridge | 189:f392fc9709a3 | 593 | * (*) value not defined in all devices |
| AnnaBridge | 189:f392fc9709a3 | 594 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 595 | */ |
| AnnaBridge | 189:f392fc9709a3 | 596 | __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) |
| AnnaBridge | 189:f392fc9709a3 | 597 | { |
| AnnaBridge | 189:f392fc9709a3 | 598 | SET_BIT(PWR->CR2, PeriphVoltage); |
| AnnaBridge | 189:f392fc9709a3 | 599 | } |
| AnnaBridge | 189:f392fc9709a3 | 600 | |
| AnnaBridge | 189:f392fc9709a3 | 601 | /** |
| AnnaBridge | 189:f392fc9709a3 | 602 | * @brief Disable the Power Voltage Monitoring on a peripheral |
| AnnaBridge | 189:f392fc9709a3 | 603 | * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n |
| AnnaBridge | 189:f392fc9709a3 | 604 | * CR2 PVME2 LL_PWR_DisablePVM\n |
| AnnaBridge | 189:f392fc9709a3 | 605 | * CR2 PVME3 LL_PWR_DisablePVM\n |
| AnnaBridge | 189:f392fc9709a3 | 606 | * CR2 PVME4 LL_PWR_DisablePVM |
| AnnaBridge | 189:f392fc9709a3 | 607 | * @param PeriphVoltage This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 608 | * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) |
| AnnaBridge | 189:f392fc9709a3 | 609 | * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) |
| AnnaBridge | 189:f392fc9709a3 | 610 | * @arg @ref LL_PWR_PVM_VDDA_1_62V |
| AnnaBridge | 189:f392fc9709a3 | 611 | * @arg @ref LL_PWR_PVM_VDDA_2_2V |
| AnnaBridge | 189:f392fc9709a3 | 612 | * |
| AnnaBridge | 189:f392fc9709a3 | 613 | * (*) value not defined in all devices |
| AnnaBridge | 189:f392fc9709a3 | 614 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 615 | */ |
| AnnaBridge | 189:f392fc9709a3 | 616 | __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) |
| AnnaBridge | 189:f392fc9709a3 | 617 | { |
| AnnaBridge | 189:f392fc9709a3 | 618 | CLEAR_BIT(PWR->CR2, PeriphVoltage); |
| AnnaBridge | 189:f392fc9709a3 | 619 | } |
| AnnaBridge | 189:f392fc9709a3 | 620 | |
| AnnaBridge | 189:f392fc9709a3 | 621 | /** |
| AnnaBridge | 189:f392fc9709a3 | 622 | * @brief Check if Power Voltage Monitoring is enabled on a peripheral |
| AnnaBridge | 189:f392fc9709a3 | 623 | * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n |
| AnnaBridge | 189:f392fc9709a3 | 624 | * CR2 PVME2 LL_PWR_IsEnabledPVM\n |
| AnnaBridge | 189:f392fc9709a3 | 625 | * CR2 PVME3 LL_PWR_IsEnabledPVM\n |
| AnnaBridge | 189:f392fc9709a3 | 626 | * CR2 PVME4 LL_PWR_IsEnabledPVM |
| AnnaBridge | 189:f392fc9709a3 | 627 | * @param PeriphVoltage This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 628 | * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) |
| AnnaBridge | 189:f392fc9709a3 | 629 | * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) |
| AnnaBridge | 189:f392fc9709a3 | 630 | * @arg @ref LL_PWR_PVM_VDDA_1_62V |
| AnnaBridge | 189:f392fc9709a3 | 631 | * @arg @ref LL_PWR_PVM_VDDA_2_2V |
| AnnaBridge | 189:f392fc9709a3 | 632 | * |
| AnnaBridge | 189:f392fc9709a3 | 633 | * (*) value not defined in all devices |
| AnnaBridge | 189:f392fc9709a3 | 634 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 635 | */ |
| AnnaBridge | 189:f392fc9709a3 | 636 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) |
| AnnaBridge | 189:f392fc9709a3 | 637 | { |
| AnnaBridge | 189:f392fc9709a3 | 638 | return (READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)); |
| AnnaBridge | 189:f392fc9709a3 | 639 | } |
| AnnaBridge | 189:f392fc9709a3 | 640 | |
| AnnaBridge | 189:f392fc9709a3 | 641 | /** |
| AnnaBridge | 189:f392fc9709a3 | 642 | * @brief Configure the voltage threshold detected by the Power Voltage Detector |
| AnnaBridge | 189:f392fc9709a3 | 643 | * @rmtoll CR2 PLS LL_PWR_SetPVDLevel |
| AnnaBridge | 189:f392fc9709a3 | 644 | * @param PVDLevel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 645 | * @arg @ref LL_PWR_PVDLEVEL_0 |
| AnnaBridge | 189:f392fc9709a3 | 646 | * @arg @ref LL_PWR_PVDLEVEL_1 |
| AnnaBridge | 189:f392fc9709a3 | 647 | * @arg @ref LL_PWR_PVDLEVEL_2 |
| AnnaBridge | 189:f392fc9709a3 | 648 | * @arg @ref LL_PWR_PVDLEVEL_3 |
| AnnaBridge | 189:f392fc9709a3 | 649 | * @arg @ref LL_PWR_PVDLEVEL_4 |
| AnnaBridge | 189:f392fc9709a3 | 650 | * @arg @ref LL_PWR_PVDLEVEL_5 |
| AnnaBridge | 189:f392fc9709a3 | 651 | * @arg @ref LL_PWR_PVDLEVEL_6 |
| AnnaBridge | 189:f392fc9709a3 | 652 | * @arg @ref LL_PWR_PVDLEVEL_7 |
| AnnaBridge | 189:f392fc9709a3 | 653 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 654 | */ |
| AnnaBridge | 189:f392fc9709a3 | 655 | __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) |
| AnnaBridge | 189:f392fc9709a3 | 656 | { |
| AnnaBridge | 189:f392fc9709a3 | 657 | MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel); |
| AnnaBridge | 189:f392fc9709a3 | 658 | } |
| AnnaBridge | 189:f392fc9709a3 | 659 | |
| AnnaBridge | 189:f392fc9709a3 | 660 | /** |
| AnnaBridge | 189:f392fc9709a3 | 661 | * @brief Get the voltage threshold detection |
| AnnaBridge | 189:f392fc9709a3 | 662 | * @rmtoll CR2 PLS LL_PWR_GetPVDLevel |
| AnnaBridge | 189:f392fc9709a3 | 663 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 664 | * @arg @ref LL_PWR_PVDLEVEL_0 |
| AnnaBridge | 189:f392fc9709a3 | 665 | * @arg @ref LL_PWR_PVDLEVEL_1 |
| AnnaBridge | 189:f392fc9709a3 | 666 | * @arg @ref LL_PWR_PVDLEVEL_2 |
| AnnaBridge | 189:f392fc9709a3 | 667 | * @arg @ref LL_PWR_PVDLEVEL_3 |
| AnnaBridge | 189:f392fc9709a3 | 668 | * @arg @ref LL_PWR_PVDLEVEL_4 |
| AnnaBridge | 189:f392fc9709a3 | 669 | * @arg @ref LL_PWR_PVDLEVEL_5 |
| AnnaBridge | 189:f392fc9709a3 | 670 | * @arg @ref LL_PWR_PVDLEVEL_6 |
| AnnaBridge | 189:f392fc9709a3 | 671 | * @arg @ref LL_PWR_PVDLEVEL_7 |
| AnnaBridge | 189:f392fc9709a3 | 672 | */ |
| AnnaBridge | 189:f392fc9709a3 | 673 | __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) |
| AnnaBridge | 189:f392fc9709a3 | 674 | { |
| AnnaBridge | 189:f392fc9709a3 | 675 | return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS)); |
| AnnaBridge | 189:f392fc9709a3 | 676 | } |
| AnnaBridge | 189:f392fc9709a3 | 677 | |
| AnnaBridge | 189:f392fc9709a3 | 678 | /** |
| AnnaBridge | 189:f392fc9709a3 | 679 | * @brief Enable Power Voltage Detector |
| AnnaBridge | 189:f392fc9709a3 | 680 | * @rmtoll CR2 PVDE LL_PWR_EnablePVD |
| AnnaBridge | 189:f392fc9709a3 | 681 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 682 | */ |
| AnnaBridge | 189:f392fc9709a3 | 683 | __STATIC_INLINE void LL_PWR_EnablePVD(void) |
| AnnaBridge | 189:f392fc9709a3 | 684 | { |
| AnnaBridge | 189:f392fc9709a3 | 685 | SET_BIT(PWR->CR2, PWR_CR2_PVDE); |
| AnnaBridge | 189:f392fc9709a3 | 686 | } |
| AnnaBridge | 189:f392fc9709a3 | 687 | |
| AnnaBridge | 189:f392fc9709a3 | 688 | /** |
| AnnaBridge | 189:f392fc9709a3 | 689 | * @brief Disable Power Voltage Detector |
| AnnaBridge | 189:f392fc9709a3 | 690 | * @rmtoll CR2 PVDE LL_PWR_DisablePVD |
| AnnaBridge | 189:f392fc9709a3 | 691 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 692 | */ |
| AnnaBridge | 189:f392fc9709a3 | 693 | __STATIC_INLINE void LL_PWR_DisablePVD(void) |
| AnnaBridge | 189:f392fc9709a3 | 694 | { |
| AnnaBridge | 189:f392fc9709a3 | 695 | CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); |
| AnnaBridge | 189:f392fc9709a3 | 696 | } |
| AnnaBridge | 189:f392fc9709a3 | 697 | |
| AnnaBridge | 189:f392fc9709a3 | 698 | /** |
| AnnaBridge | 189:f392fc9709a3 | 699 | * @brief Check if Power Voltage Detector is enabled |
| AnnaBridge | 189:f392fc9709a3 | 700 | * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD |
| AnnaBridge | 189:f392fc9709a3 | 701 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 702 | */ |
| AnnaBridge | 189:f392fc9709a3 | 703 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) |
| AnnaBridge | 189:f392fc9709a3 | 704 | { |
| AnnaBridge | 189:f392fc9709a3 | 705 | return (READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)); |
| AnnaBridge | 189:f392fc9709a3 | 706 | } |
| AnnaBridge | 189:f392fc9709a3 | 707 | |
| AnnaBridge | 189:f392fc9709a3 | 708 | /** |
| AnnaBridge | 189:f392fc9709a3 | 709 | * @brief Enable Internal Wake-up line |
| AnnaBridge | 189:f392fc9709a3 | 710 | * @rmtoll CR3 EIWF LL_PWR_EnableInternWU |
| AnnaBridge | 189:f392fc9709a3 | 711 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 712 | */ |
| AnnaBridge | 189:f392fc9709a3 | 713 | __STATIC_INLINE void LL_PWR_EnableInternWU(void) |
| AnnaBridge | 189:f392fc9709a3 | 714 | { |
| AnnaBridge | 189:f392fc9709a3 | 715 | SET_BIT(PWR->CR3, PWR_CR3_EIWF); |
| AnnaBridge | 189:f392fc9709a3 | 716 | } |
| AnnaBridge | 189:f392fc9709a3 | 717 | |
| AnnaBridge | 189:f392fc9709a3 | 718 | /** |
| AnnaBridge | 189:f392fc9709a3 | 719 | * @brief Disable Internal Wake-up line |
| AnnaBridge | 189:f392fc9709a3 | 720 | * @rmtoll CR3 EIWF LL_PWR_DisableInternWU |
| AnnaBridge | 189:f392fc9709a3 | 721 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 722 | */ |
| AnnaBridge | 189:f392fc9709a3 | 723 | __STATIC_INLINE void LL_PWR_DisableInternWU(void) |
| AnnaBridge | 189:f392fc9709a3 | 724 | { |
| AnnaBridge | 189:f392fc9709a3 | 725 | CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); |
| AnnaBridge | 189:f392fc9709a3 | 726 | } |
| AnnaBridge | 189:f392fc9709a3 | 727 | |
| AnnaBridge | 189:f392fc9709a3 | 728 | /** |
| AnnaBridge | 189:f392fc9709a3 | 729 | * @brief Check if Internal Wake-up line is enabled |
| AnnaBridge | 189:f392fc9709a3 | 730 | * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU |
| AnnaBridge | 189:f392fc9709a3 | 731 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 732 | */ |
| AnnaBridge | 189:f392fc9709a3 | 733 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) |
| AnnaBridge | 189:f392fc9709a3 | 734 | { |
| AnnaBridge | 189:f392fc9709a3 | 735 | return (READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)); |
| AnnaBridge | 189:f392fc9709a3 | 736 | } |
| AnnaBridge | 189:f392fc9709a3 | 737 | |
| AnnaBridge | 189:f392fc9709a3 | 738 | /** |
| AnnaBridge | 189:f392fc9709a3 | 739 | * @brief Enable pull-up and pull-down configuration |
| AnnaBridge | 189:f392fc9709a3 | 740 | * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg |
| AnnaBridge | 189:f392fc9709a3 | 741 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 742 | */ |
| AnnaBridge | 189:f392fc9709a3 | 743 | __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void) |
| AnnaBridge | 189:f392fc9709a3 | 744 | { |
| AnnaBridge | 189:f392fc9709a3 | 745 | SET_BIT(PWR->CR3, PWR_CR3_APC); |
| AnnaBridge | 189:f392fc9709a3 | 746 | } |
| AnnaBridge | 189:f392fc9709a3 | 747 | |
| AnnaBridge | 189:f392fc9709a3 | 748 | /** |
| AnnaBridge | 189:f392fc9709a3 | 749 | * @brief Disable pull-up and pull-down configuration |
| AnnaBridge | 189:f392fc9709a3 | 750 | * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg |
| AnnaBridge | 189:f392fc9709a3 | 751 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 752 | */ |
| AnnaBridge | 189:f392fc9709a3 | 753 | __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) |
| AnnaBridge | 189:f392fc9709a3 | 754 | { |
| AnnaBridge | 189:f392fc9709a3 | 755 | CLEAR_BIT(PWR->CR3, PWR_CR3_APC); |
| AnnaBridge | 189:f392fc9709a3 | 756 | } |
| AnnaBridge | 189:f392fc9709a3 | 757 | |
| AnnaBridge | 189:f392fc9709a3 | 758 | /** |
| AnnaBridge | 189:f392fc9709a3 | 759 | * @brief Check if pull-up and pull-down configuration is enabled |
| AnnaBridge | 189:f392fc9709a3 | 760 | * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg |
| AnnaBridge | 189:f392fc9709a3 | 761 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 762 | */ |
| AnnaBridge | 189:f392fc9709a3 | 763 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) |
| AnnaBridge | 189:f392fc9709a3 | 764 | { |
| AnnaBridge | 189:f392fc9709a3 | 765 | return (READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)); |
| AnnaBridge | 189:f392fc9709a3 | 766 | } |
| AnnaBridge | 189:f392fc9709a3 | 767 | |
| AnnaBridge | 189:f392fc9709a3 | 768 | #if defined(PWR_CR3_DSIPDEN) |
| AnnaBridge | 189:f392fc9709a3 | 769 | /** |
| AnnaBridge | 189:f392fc9709a3 | 770 | * @brief Enable pull-down activation on DSI pins |
| AnnaBridge | 189:f392fc9709a3 | 771 | * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPullDown |
| AnnaBridge | 189:f392fc9709a3 | 772 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 773 | */ |
| AnnaBridge | 189:f392fc9709a3 | 774 | __STATIC_INLINE void LL_PWR_EnableDSIPullDown(void) |
| AnnaBridge | 189:f392fc9709a3 | 775 | { |
| AnnaBridge | 189:f392fc9709a3 | 776 | SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); |
| AnnaBridge | 189:f392fc9709a3 | 777 | } |
| AnnaBridge | 189:f392fc9709a3 | 778 | |
| AnnaBridge | 189:f392fc9709a3 | 779 | /** |
| AnnaBridge | 189:f392fc9709a3 | 780 | * @brief Disable pull-down activation on DSI pins |
| AnnaBridge | 189:f392fc9709a3 | 781 | * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPullDown |
| AnnaBridge | 189:f392fc9709a3 | 782 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 783 | */ |
| AnnaBridge | 189:f392fc9709a3 | 784 | __STATIC_INLINE void LL_PWR_DisableDSIPullDown(void) |
| AnnaBridge | 189:f392fc9709a3 | 785 | { |
| AnnaBridge | 189:f392fc9709a3 | 786 | CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); |
| AnnaBridge | 189:f392fc9709a3 | 787 | } |
| AnnaBridge | 189:f392fc9709a3 | 788 | |
| AnnaBridge | 189:f392fc9709a3 | 789 | /** |
| AnnaBridge | 189:f392fc9709a3 | 790 | * @brief Check if pull-down activation on DSI pins is enabled |
| AnnaBridge | 189:f392fc9709a3 | 791 | * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPullDown |
| AnnaBridge | 189:f392fc9709a3 | 792 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 793 | */ |
| AnnaBridge | 189:f392fc9709a3 | 794 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPullDown(void) |
| AnnaBridge | 189:f392fc9709a3 | 795 | { |
| AnnaBridge | 189:f392fc9709a3 | 796 | return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)); |
| AnnaBridge | 189:f392fc9709a3 | 797 | } |
| AnnaBridge | 189:f392fc9709a3 | 798 | #endif /* PWR_CR3_DSIPDEN */ |
| AnnaBridge | 189:f392fc9709a3 | 799 | |
| AnnaBridge | 189:f392fc9709a3 | 800 | /** |
| AnnaBridge | 189:f392fc9709a3 | 801 | * @brief Enable SRAM2 content retention in Standby mode |
| AnnaBridge | 189:f392fc9709a3 | 802 | * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention |
| AnnaBridge | 189:f392fc9709a3 | 803 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 804 | */ |
| AnnaBridge | 189:f392fc9709a3 | 805 | __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void) |
| AnnaBridge | 189:f392fc9709a3 | 806 | { |
| AnnaBridge | 189:f392fc9709a3 | 807 | SET_BIT(PWR->CR3, PWR_CR3_RRS); |
| AnnaBridge | 189:f392fc9709a3 | 808 | } |
| AnnaBridge | 189:f392fc9709a3 | 809 | |
| AnnaBridge | 189:f392fc9709a3 | 810 | /** |
| AnnaBridge | 189:f392fc9709a3 | 811 | * @brief Disable SRAM2 content retention in Standby mode |
| AnnaBridge | 189:f392fc9709a3 | 812 | * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention |
| AnnaBridge | 189:f392fc9709a3 | 813 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 814 | */ |
| AnnaBridge | 189:f392fc9709a3 | 815 | __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) |
| AnnaBridge | 189:f392fc9709a3 | 816 | { |
| AnnaBridge | 189:f392fc9709a3 | 817 | CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); |
| AnnaBridge | 189:f392fc9709a3 | 818 | } |
| AnnaBridge | 189:f392fc9709a3 | 819 | |
| AnnaBridge | 189:f392fc9709a3 | 820 | /** |
| AnnaBridge | 189:f392fc9709a3 | 821 | * @brief Check if SRAM2 content retention in Standby mode is enabled |
| AnnaBridge | 189:f392fc9709a3 | 822 | * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention |
| AnnaBridge | 189:f392fc9709a3 | 823 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 824 | */ |
| AnnaBridge | 189:f392fc9709a3 | 825 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) |
| AnnaBridge | 189:f392fc9709a3 | 826 | { |
| AnnaBridge | 189:f392fc9709a3 | 827 | return (READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)); |
| AnnaBridge | 189:f392fc9709a3 | 828 | } |
| AnnaBridge | 189:f392fc9709a3 | 829 | |
| AnnaBridge | 189:f392fc9709a3 | 830 | /** |
| AnnaBridge | 189:f392fc9709a3 | 831 | * @brief Enable the WakeUp PINx functionality |
| AnnaBridge | 189:f392fc9709a3 | 832 | * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 833 | * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 834 | * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 835 | * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 836 | * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 837 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 838 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 189:f392fc9709a3 | 839 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
| AnnaBridge | 189:f392fc9709a3 | 840 | * @arg @ref LL_PWR_WAKEUP_PIN3 |
| AnnaBridge | 189:f392fc9709a3 | 841 | * @arg @ref LL_PWR_WAKEUP_PIN4 |
| AnnaBridge | 189:f392fc9709a3 | 842 | * @arg @ref LL_PWR_WAKEUP_PIN5 |
| AnnaBridge | 189:f392fc9709a3 | 843 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 844 | */ |
| AnnaBridge | 189:f392fc9709a3 | 845 | __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) |
| AnnaBridge | 189:f392fc9709a3 | 846 | { |
| AnnaBridge | 189:f392fc9709a3 | 847 | SET_BIT(PWR->CR3, WakeUpPin); |
| AnnaBridge | 189:f392fc9709a3 | 848 | } |
| AnnaBridge | 189:f392fc9709a3 | 849 | |
| AnnaBridge | 189:f392fc9709a3 | 850 | /** |
| AnnaBridge | 189:f392fc9709a3 | 851 | * @brief Disable the WakeUp PINx functionality |
| AnnaBridge | 189:f392fc9709a3 | 852 | * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 853 | * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 854 | * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 855 | * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 856 | * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 857 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 858 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 189:f392fc9709a3 | 859 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
| AnnaBridge | 189:f392fc9709a3 | 860 | * @arg @ref LL_PWR_WAKEUP_PIN3 |
| AnnaBridge | 189:f392fc9709a3 | 861 | * @arg @ref LL_PWR_WAKEUP_PIN4 |
| AnnaBridge | 189:f392fc9709a3 | 862 | * @arg @ref LL_PWR_WAKEUP_PIN5 |
| AnnaBridge | 189:f392fc9709a3 | 863 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 864 | */ |
| AnnaBridge | 189:f392fc9709a3 | 865 | __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) |
| AnnaBridge | 189:f392fc9709a3 | 866 | { |
| AnnaBridge | 189:f392fc9709a3 | 867 | CLEAR_BIT(PWR->CR3, WakeUpPin); |
| AnnaBridge | 189:f392fc9709a3 | 868 | } |
| AnnaBridge | 189:f392fc9709a3 | 869 | |
| AnnaBridge | 189:f392fc9709a3 | 870 | /** |
| AnnaBridge | 189:f392fc9709a3 | 871 | * @brief Check if the WakeUp PINx functionality is enabled |
| AnnaBridge | 189:f392fc9709a3 | 872 | * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 873 | * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 874 | * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 875 | * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 876 | * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 877 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 878 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 189:f392fc9709a3 | 879 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
| AnnaBridge | 189:f392fc9709a3 | 880 | * @arg @ref LL_PWR_WAKEUP_PIN3 |
| AnnaBridge | 189:f392fc9709a3 | 881 | * @arg @ref LL_PWR_WAKEUP_PIN4 |
| AnnaBridge | 189:f392fc9709a3 | 882 | * @arg @ref LL_PWR_WAKEUP_PIN5 |
| AnnaBridge | 189:f392fc9709a3 | 883 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 884 | */ |
| AnnaBridge | 189:f392fc9709a3 | 885 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) |
| AnnaBridge | 189:f392fc9709a3 | 886 | { |
| AnnaBridge | 189:f392fc9709a3 | 887 | return (READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)); |
| AnnaBridge | 189:f392fc9709a3 | 888 | } |
| AnnaBridge | 189:f392fc9709a3 | 889 | |
| AnnaBridge | 189:f392fc9709a3 | 890 | /** |
| AnnaBridge | 189:f392fc9709a3 | 891 | * @brief Set the resistor impedance |
| AnnaBridge | 189:f392fc9709a3 | 892 | * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor |
| AnnaBridge | 189:f392fc9709a3 | 893 | * @param Resistor This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 894 | * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K |
| AnnaBridge | 189:f392fc9709a3 | 895 | * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K |
| AnnaBridge | 189:f392fc9709a3 | 896 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 897 | */ |
| AnnaBridge | 189:f392fc9709a3 | 898 | __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) |
| AnnaBridge | 189:f392fc9709a3 | 899 | { |
| AnnaBridge | 189:f392fc9709a3 | 900 | MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor); |
| AnnaBridge | 189:f392fc9709a3 | 901 | } |
| AnnaBridge | 189:f392fc9709a3 | 902 | |
| AnnaBridge | 189:f392fc9709a3 | 903 | /** |
| AnnaBridge | 189:f392fc9709a3 | 904 | * @brief Get the resistor impedance |
| AnnaBridge | 189:f392fc9709a3 | 905 | * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor |
| AnnaBridge | 189:f392fc9709a3 | 906 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 907 | * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K |
| AnnaBridge | 189:f392fc9709a3 | 908 | * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K |
| AnnaBridge | 189:f392fc9709a3 | 909 | */ |
| AnnaBridge | 189:f392fc9709a3 | 910 | __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) |
| AnnaBridge | 189:f392fc9709a3 | 911 | { |
| AnnaBridge | 189:f392fc9709a3 | 912 | return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS)); |
| AnnaBridge | 189:f392fc9709a3 | 913 | } |
| AnnaBridge | 189:f392fc9709a3 | 914 | |
| AnnaBridge | 189:f392fc9709a3 | 915 | /** |
| AnnaBridge | 189:f392fc9709a3 | 916 | * @brief Enable battery charging |
| AnnaBridge | 189:f392fc9709a3 | 917 | * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging |
| AnnaBridge | 189:f392fc9709a3 | 918 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 919 | */ |
| AnnaBridge | 189:f392fc9709a3 | 920 | __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) |
| AnnaBridge | 189:f392fc9709a3 | 921 | { |
| AnnaBridge | 189:f392fc9709a3 | 922 | SET_BIT(PWR->CR4, PWR_CR4_VBE); |
| AnnaBridge | 189:f392fc9709a3 | 923 | } |
| AnnaBridge | 189:f392fc9709a3 | 924 | |
| AnnaBridge | 189:f392fc9709a3 | 925 | /** |
| AnnaBridge | 189:f392fc9709a3 | 926 | * @brief Disable battery charging |
| AnnaBridge | 189:f392fc9709a3 | 927 | * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging |
| AnnaBridge | 189:f392fc9709a3 | 928 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 929 | */ |
| AnnaBridge | 189:f392fc9709a3 | 930 | __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) |
| AnnaBridge | 189:f392fc9709a3 | 931 | { |
| AnnaBridge | 189:f392fc9709a3 | 932 | CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); |
| AnnaBridge | 189:f392fc9709a3 | 933 | } |
| AnnaBridge | 189:f392fc9709a3 | 934 | |
| AnnaBridge | 189:f392fc9709a3 | 935 | /** |
| AnnaBridge | 189:f392fc9709a3 | 936 | * @brief Check if battery charging is enabled |
| AnnaBridge | 189:f392fc9709a3 | 937 | * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging |
| AnnaBridge | 189:f392fc9709a3 | 938 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 939 | */ |
| AnnaBridge | 189:f392fc9709a3 | 940 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) |
| AnnaBridge | 189:f392fc9709a3 | 941 | { |
| AnnaBridge | 189:f392fc9709a3 | 942 | return (READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)); |
| AnnaBridge | 189:f392fc9709a3 | 943 | } |
| AnnaBridge | 189:f392fc9709a3 | 944 | |
| AnnaBridge | 189:f392fc9709a3 | 945 | /** |
| AnnaBridge | 189:f392fc9709a3 | 946 | * @brief Set the Wake-Up pin polarity low for the event detection |
| AnnaBridge | 189:f392fc9709a3 | 947 | * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n |
| AnnaBridge | 189:f392fc9709a3 | 948 | * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n |
| AnnaBridge | 189:f392fc9709a3 | 949 | * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n |
| AnnaBridge | 189:f392fc9709a3 | 950 | * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n |
| AnnaBridge | 189:f392fc9709a3 | 951 | * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow |
| AnnaBridge | 189:f392fc9709a3 | 952 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 953 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 189:f392fc9709a3 | 954 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
| AnnaBridge | 189:f392fc9709a3 | 955 | * @arg @ref LL_PWR_WAKEUP_PIN3 |
| AnnaBridge | 189:f392fc9709a3 | 956 | * @arg @ref LL_PWR_WAKEUP_PIN4 |
| AnnaBridge | 189:f392fc9709a3 | 957 | * @arg @ref LL_PWR_WAKEUP_PIN5 |
| AnnaBridge | 189:f392fc9709a3 | 958 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 959 | */ |
| AnnaBridge | 189:f392fc9709a3 | 960 | __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) |
| AnnaBridge | 189:f392fc9709a3 | 961 | { |
| AnnaBridge | 189:f392fc9709a3 | 962 | SET_BIT(PWR->CR4, WakeUpPin); |
| AnnaBridge | 189:f392fc9709a3 | 963 | } |
| AnnaBridge | 189:f392fc9709a3 | 964 | |
| AnnaBridge | 189:f392fc9709a3 | 965 | /** |
| AnnaBridge | 189:f392fc9709a3 | 966 | * @brief Set the Wake-Up pin polarity high for the event detection |
| AnnaBridge | 189:f392fc9709a3 | 967 | * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n |
| AnnaBridge | 189:f392fc9709a3 | 968 | * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n |
| AnnaBridge | 189:f392fc9709a3 | 969 | * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n |
| AnnaBridge | 189:f392fc9709a3 | 970 | * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n |
| AnnaBridge | 189:f392fc9709a3 | 971 | * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh |
| AnnaBridge | 189:f392fc9709a3 | 972 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 973 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 189:f392fc9709a3 | 974 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
| AnnaBridge | 189:f392fc9709a3 | 975 | * @arg @ref LL_PWR_WAKEUP_PIN3 |
| AnnaBridge | 189:f392fc9709a3 | 976 | * @arg @ref LL_PWR_WAKEUP_PIN4 |
| AnnaBridge | 189:f392fc9709a3 | 977 | * @arg @ref LL_PWR_WAKEUP_PIN5 |
| AnnaBridge | 189:f392fc9709a3 | 978 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 979 | */ |
| AnnaBridge | 189:f392fc9709a3 | 980 | __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) |
| AnnaBridge | 189:f392fc9709a3 | 981 | { |
| AnnaBridge | 189:f392fc9709a3 | 982 | CLEAR_BIT(PWR->CR4, WakeUpPin); |
| AnnaBridge | 189:f392fc9709a3 | 983 | } |
| AnnaBridge | 189:f392fc9709a3 | 984 | |
| AnnaBridge | 189:f392fc9709a3 | 985 | /** |
| AnnaBridge | 189:f392fc9709a3 | 986 | * @brief Get the Wake-Up pin polarity for the event detection |
| AnnaBridge | 189:f392fc9709a3 | 987 | * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n |
| AnnaBridge | 189:f392fc9709a3 | 988 | * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n |
| AnnaBridge | 189:f392fc9709a3 | 989 | * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n |
| AnnaBridge | 189:f392fc9709a3 | 990 | * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n |
| AnnaBridge | 189:f392fc9709a3 | 991 | * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow |
| AnnaBridge | 189:f392fc9709a3 | 992 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 993 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 189:f392fc9709a3 | 994 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
| AnnaBridge | 189:f392fc9709a3 | 995 | * @arg @ref LL_PWR_WAKEUP_PIN3 |
| AnnaBridge | 189:f392fc9709a3 | 996 | * @arg @ref LL_PWR_WAKEUP_PIN4 |
| AnnaBridge | 189:f392fc9709a3 | 997 | * @arg @ref LL_PWR_WAKEUP_PIN5 |
| AnnaBridge | 189:f392fc9709a3 | 998 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 999 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1000 | __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) |
| AnnaBridge | 189:f392fc9709a3 | 1001 | { |
| AnnaBridge | 189:f392fc9709a3 | 1002 | return (READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)); |
| AnnaBridge | 189:f392fc9709a3 | 1003 | } |
| AnnaBridge | 189:f392fc9709a3 | 1004 | |
| AnnaBridge | 189:f392fc9709a3 | 1005 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1006 | * @brief Enable GPIO pull-up state in Standby and Shutdown modes |
| AnnaBridge | 189:f392fc9709a3 | 1007 | * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1008 | * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1009 | * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1010 | * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1011 | * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1012 | * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1013 | * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1014 | * PUCRH PU0-15 LL_PWR_EnableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1015 | * PUCRI PU0-11 LL_PWR_EnableGPIOPullUp |
| AnnaBridge | 189:f392fc9709a3 | 1016 | * @param GPIO This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1017 | * @arg @ref LL_PWR_GPIO_A |
| AnnaBridge | 189:f392fc9709a3 | 1018 | * @arg @ref LL_PWR_GPIO_B |
| AnnaBridge | 189:f392fc9709a3 | 1019 | * @arg @ref LL_PWR_GPIO_C |
| AnnaBridge | 189:f392fc9709a3 | 1020 | * @arg @ref LL_PWR_GPIO_D |
| AnnaBridge | 189:f392fc9709a3 | 1021 | * @arg @ref LL_PWR_GPIO_E |
| AnnaBridge | 189:f392fc9709a3 | 1022 | * @arg @ref LL_PWR_GPIO_F (*) |
| AnnaBridge | 189:f392fc9709a3 | 1023 | * @arg @ref LL_PWR_GPIO_G (*) |
| AnnaBridge | 189:f392fc9709a3 | 1024 | * @arg @ref LL_PWR_GPIO_H |
| AnnaBridge | 189:f392fc9709a3 | 1025 | * @arg @ref LL_PWR_GPIO_I (*) |
| AnnaBridge | 189:f392fc9709a3 | 1026 | * |
| AnnaBridge | 189:f392fc9709a3 | 1027 | * (*) value not defined in all devices |
| AnnaBridge | 189:f392fc9709a3 | 1028 | * @param GPIONumber This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1029 | * @arg @ref LL_PWR_GPIO_BIT_0 |
| AnnaBridge | 189:f392fc9709a3 | 1030 | * @arg @ref LL_PWR_GPIO_BIT_1 |
| AnnaBridge | 189:f392fc9709a3 | 1031 | * @arg @ref LL_PWR_GPIO_BIT_2 |
| AnnaBridge | 189:f392fc9709a3 | 1032 | * @arg @ref LL_PWR_GPIO_BIT_3 |
| AnnaBridge | 189:f392fc9709a3 | 1033 | * @arg @ref LL_PWR_GPIO_BIT_4 |
| AnnaBridge | 189:f392fc9709a3 | 1034 | * @arg @ref LL_PWR_GPIO_BIT_5 |
| AnnaBridge | 189:f392fc9709a3 | 1035 | * @arg @ref LL_PWR_GPIO_BIT_6 |
| AnnaBridge | 189:f392fc9709a3 | 1036 | * @arg @ref LL_PWR_GPIO_BIT_7 |
| AnnaBridge | 189:f392fc9709a3 | 1037 | * @arg @ref LL_PWR_GPIO_BIT_8 |
| AnnaBridge | 189:f392fc9709a3 | 1038 | * @arg @ref LL_PWR_GPIO_BIT_9 |
| AnnaBridge | 189:f392fc9709a3 | 1039 | * @arg @ref LL_PWR_GPIO_BIT_10 |
| AnnaBridge | 189:f392fc9709a3 | 1040 | * @arg @ref LL_PWR_GPIO_BIT_11 |
| AnnaBridge | 189:f392fc9709a3 | 1041 | * @arg @ref LL_PWR_GPIO_BIT_12 |
| AnnaBridge | 189:f392fc9709a3 | 1042 | * @arg @ref LL_PWR_GPIO_BIT_13 |
| AnnaBridge | 189:f392fc9709a3 | 1043 | * @arg @ref LL_PWR_GPIO_BIT_14 |
| AnnaBridge | 189:f392fc9709a3 | 1044 | * @arg @ref LL_PWR_GPIO_BIT_15 |
| AnnaBridge | 189:f392fc9709a3 | 1045 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1046 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1047 | __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) |
| AnnaBridge | 189:f392fc9709a3 | 1048 | { |
| AnnaBridge | 189:f392fc9709a3 | 1049 | SET_BIT(*((uint32_t *)GPIO), GPIONumber); |
| AnnaBridge | 189:f392fc9709a3 | 1050 | } |
| AnnaBridge | 189:f392fc9709a3 | 1051 | |
| AnnaBridge | 189:f392fc9709a3 | 1052 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1053 | * @brief Disable GPIO pull-up state in Standby and Shutdown modes |
| AnnaBridge | 189:f392fc9709a3 | 1054 | * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1055 | * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1056 | * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1057 | * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1058 | * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1059 | * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1060 | * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1061 | * PUCRH PU0-15 LL_PWR_DisableGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1062 | * PUCRI PU0-11 LL_PWR_DisableGPIOPullUp |
| AnnaBridge | 189:f392fc9709a3 | 1063 | * @param GPIO This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1064 | * @arg @ref LL_PWR_GPIO_A |
| AnnaBridge | 189:f392fc9709a3 | 1065 | * @arg @ref LL_PWR_GPIO_B |
| AnnaBridge | 189:f392fc9709a3 | 1066 | * @arg @ref LL_PWR_GPIO_C |
| AnnaBridge | 189:f392fc9709a3 | 1067 | * @arg @ref LL_PWR_GPIO_D |
| AnnaBridge | 189:f392fc9709a3 | 1068 | * @arg @ref LL_PWR_GPIO_E |
| AnnaBridge | 189:f392fc9709a3 | 1069 | * @arg @ref LL_PWR_GPIO_F (*) |
| AnnaBridge | 189:f392fc9709a3 | 1070 | * @arg @ref LL_PWR_GPIO_G (*) |
| AnnaBridge | 189:f392fc9709a3 | 1071 | * @arg @ref LL_PWR_GPIO_H |
| AnnaBridge | 189:f392fc9709a3 | 1072 | * @arg @ref LL_PWR_GPIO_I (*) |
| AnnaBridge | 189:f392fc9709a3 | 1073 | * |
| AnnaBridge | 189:f392fc9709a3 | 1074 | * (*) value not defined in all devices |
| AnnaBridge | 189:f392fc9709a3 | 1075 | * @param GPIONumber This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1076 | * @arg @ref LL_PWR_GPIO_BIT_0 |
| AnnaBridge | 189:f392fc9709a3 | 1077 | * @arg @ref LL_PWR_GPIO_BIT_1 |
| AnnaBridge | 189:f392fc9709a3 | 1078 | * @arg @ref LL_PWR_GPIO_BIT_2 |
| AnnaBridge | 189:f392fc9709a3 | 1079 | * @arg @ref LL_PWR_GPIO_BIT_3 |
| AnnaBridge | 189:f392fc9709a3 | 1080 | * @arg @ref LL_PWR_GPIO_BIT_4 |
| AnnaBridge | 189:f392fc9709a3 | 1081 | * @arg @ref LL_PWR_GPIO_BIT_5 |
| AnnaBridge | 189:f392fc9709a3 | 1082 | * @arg @ref LL_PWR_GPIO_BIT_6 |
| AnnaBridge | 189:f392fc9709a3 | 1083 | * @arg @ref LL_PWR_GPIO_BIT_7 |
| AnnaBridge | 189:f392fc9709a3 | 1084 | * @arg @ref LL_PWR_GPIO_BIT_8 |
| AnnaBridge | 189:f392fc9709a3 | 1085 | * @arg @ref LL_PWR_GPIO_BIT_9 |
| AnnaBridge | 189:f392fc9709a3 | 1086 | * @arg @ref LL_PWR_GPIO_BIT_10 |
| AnnaBridge | 189:f392fc9709a3 | 1087 | * @arg @ref LL_PWR_GPIO_BIT_11 |
| AnnaBridge | 189:f392fc9709a3 | 1088 | * @arg @ref LL_PWR_GPIO_BIT_12 |
| AnnaBridge | 189:f392fc9709a3 | 1089 | * @arg @ref LL_PWR_GPIO_BIT_13 |
| AnnaBridge | 189:f392fc9709a3 | 1090 | * @arg @ref LL_PWR_GPIO_BIT_14 |
| AnnaBridge | 189:f392fc9709a3 | 1091 | * @arg @ref LL_PWR_GPIO_BIT_15 |
| AnnaBridge | 189:f392fc9709a3 | 1092 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1093 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1094 | __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) |
| AnnaBridge | 189:f392fc9709a3 | 1095 | { |
| AnnaBridge | 189:f392fc9709a3 | 1096 | CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber); |
| AnnaBridge | 189:f392fc9709a3 | 1097 | } |
| AnnaBridge | 189:f392fc9709a3 | 1098 | |
| AnnaBridge | 189:f392fc9709a3 | 1099 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1100 | * @brief Check if GPIO pull-up state is enabled |
| AnnaBridge | 189:f392fc9709a3 | 1101 | * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1102 | * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1103 | * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1104 | * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1105 | * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1106 | * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1107 | * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1108 | * PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
| AnnaBridge | 189:f392fc9709a3 | 1109 | * PUCRI PU0-11 LL_PWR_IsEnabledGPIOPullUp |
| AnnaBridge | 189:f392fc9709a3 | 1110 | * @param GPIO This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1111 | * @arg @ref LL_PWR_GPIO_A |
| AnnaBridge | 189:f392fc9709a3 | 1112 | * @arg @ref LL_PWR_GPIO_B |
| AnnaBridge | 189:f392fc9709a3 | 1113 | * @arg @ref LL_PWR_GPIO_C |
| AnnaBridge | 189:f392fc9709a3 | 1114 | * @arg @ref LL_PWR_GPIO_D |
| AnnaBridge | 189:f392fc9709a3 | 1115 | * @arg @ref LL_PWR_GPIO_E |
| AnnaBridge | 189:f392fc9709a3 | 1116 | * @arg @ref LL_PWR_GPIO_F (*) |
| AnnaBridge | 189:f392fc9709a3 | 1117 | * @arg @ref LL_PWR_GPIO_G (*) |
| AnnaBridge | 189:f392fc9709a3 | 1118 | * @arg @ref LL_PWR_GPIO_H |
| AnnaBridge | 189:f392fc9709a3 | 1119 | * @arg @ref LL_PWR_GPIO_I (*) |
| AnnaBridge | 189:f392fc9709a3 | 1120 | * |
| AnnaBridge | 189:f392fc9709a3 | 1121 | * (*) value not defined in all devices |
| AnnaBridge | 189:f392fc9709a3 | 1122 | * @param GPIONumber This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1123 | * @arg @ref LL_PWR_GPIO_BIT_0 |
| AnnaBridge | 189:f392fc9709a3 | 1124 | * @arg @ref LL_PWR_GPIO_BIT_1 |
| AnnaBridge | 189:f392fc9709a3 | 1125 | * @arg @ref LL_PWR_GPIO_BIT_2 |
| AnnaBridge | 189:f392fc9709a3 | 1126 | * @arg @ref LL_PWR_GPIO_BIT_3 |
| AnnaBridge | 189:f392fc9709a3 | 1127 | * @arg @ref LL_PWR_GPIO_BIT_4 |
| AnnaBridge | 189:f392fc9709a3 | 1128 | * @arg @ref LL_PWR_GPIO_BIT_5 |
| AnnaBridge | 189:f392fc9709a3 | 1129 | * @arg @ref LL_PWR_GPIO_BIT_6 |
| AnnaBridge | 189:f392fc9709a3 | 1130 | * @arg @ref LL_PWR_GPIO_BIT_7 |
| AnnaBridge | 189:f392fc9709a3 | 1131 | * @arg @ref LL_PWR_GPIO_BIT_8 |
| AnnaBridge | 189:f392fc9709a3 | 1132 | * @arg @ref LL_PWR_GPIO_BIT_9 |
| AnnaBridge | 189:f392fc9709a3 | 1133 | * @arg @ref LL_PWR_GPIO_BIT_10 |
| AnnaBridge | 189:f392fc9709a3 | 1134 | * @arg @ref LL_PWR_GPIO_BIT_11 |
| AnnaBridge | 189:f392fc9709a3 | 1135 | * @arg @ref LL_PWR_GPIO_BIT_12 |
| AnnaBridge | 189:f392fc9709a3 | 1136 | * @arg @ref LL_PWR_GPIO_BIT_13 |
| AnnaBridge | 189:f392fc9709a3 | 1137 | * @arg @ref LL_PWR_GPIO_BIT_14 |
| AnnaBridge | 189:f392fc9709a3 | 1138 | * @arg @ref LL_PWR_GPIO_BIT_15 |
| AnnaBridge | 189:f392fc9709a3 | 1139 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1140 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1141 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) |
| AnnaBridge | 189:f392fc9709a3 | 1142 | { |
| AnnaBridge | 189:f392fc9709a3 | 1143 | return (READ_BIT(*((uint32_t *)(GPIO)), GPIONumber) == (GPIONumber)); |
| AnnaBridge | 189:f392fc9709a3 | 1144 | } |
| AnnaBridge | 189:f392fc9709a3 | 1145 | |
| AnnaBridge | 189:f392fc9709a3 | 1146 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1147 | * @brief Enable GPIO pull-down state in Standby and Shutdown modes |
| AnnaBridge | 189:f392fc9709a3 | 1148 | * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1149 | * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1150 | * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1151 | * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1152 | * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1153 | * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1154 | * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1155 | * PDCRH PD0-15 LL_PWR_EnableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1156 | * PDCRI PD0-11 LL_PWR_EnableGPIOPullDown |
| AnnaBridge | 189:f392fc9709a3 | 1157 | * @param GPIO This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1158 | * @arg @ref LL_PWR_GPIO_A |
| AnnaBridge | 189:f392fc9709a3 | 1159 | * @arg @ref LL_PWR_GPIO_B |
| AnnaBridge | 189:f392fc9709a3 | 1160 | * @arg @ref LL_PWR_GPIO_C |
| AnnaBridge | 189:f392fc9709a3 | 1161 | * @arg @ref LL_PWR_GPIO_D |
| AnnaBridge | 189:f392fc9709a3 | 1162 | * @arg @ref LL_PWR_GPIO_E |
| AnnaBridge | 189:f392fc9709a3 | 1163 | * @arg @ref LL_PWR_GPIO_F (*) |
| AnnaBridge | 189:f392fc9709a3 | 1164 | * @arg @ref LL_PWR_GPIO_G (*) |
| AnnaBridge | 189:f392fc9709a3 | 1165 | * @arg @ref LL_PWR_GPIO_H |
| AnnaBridge | 189:f392fc9709a3 | 1166 | * @arg @ref LL_PWR_GPIO_I (*) |
| AnnaBridge | 189:f392fc9709a3 | 1167 | * |
| AnnaBridge | 189:f392fc9709a3 | 1168 | * (*) value not defined in all devices |
| AnnaBridge | 189:f392fc9709a3 | 1169 | * @param GPIONumber This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1170 | * @arg @ref LL_PWR_GPIO_BIT_0 |
| AnnaBridge | 189:f392fc9709a3 | 1171 | * @arg @ref LL_PWR_GPIO_BIT_1 |
| AnnaBridge | 189:f392fc9709a3 | 1172 | * @arg @ref LL_PWR_GPIO_BIT_2 |
| AnnaBridge | 189:f392fc9709a3 | 1173 | * @arg @ref LL_PWR_GPIO_BIT_3 |
| AnnaBridge | 189:f392fc9709a3 | 1174 | * @arg @ref LL_PWR_GPIO_BIT_4 |
| AnnaBridge | 189:f392fc9709a3 | 1175 | * @arg @ref LL_PWR_GPIO_BIT_5 |
| AnnaBridge | 189:f392fc9709a3 | 1176 | * @arg @ref LL_PWR_GPIO_BIT_6 |
| AnnaBridge | 189:f392fc9709a3 | 1177 | * @arg @ref LL_PWR_GPIO_BIT_7 |
| AnnaBridge | 189:f392fc9709a3 | 1178 | * @arg @ref LL_PWR_GPIO_BIT_8 |
| AnnaBridge | 189:f392fc9709a3 | 1179 | * @arg @ref LL_PWR_GPIO_BIT_9 |
| AnnaBridge | 189:f392fc9709a3 | 1180 | * @arg @ref LL_PWR_GPIO_BIT_10 |
| AnnaBridge | 189:f392fc9709a3 | 1181 | * @arg @ref LL_PWR_GPIO_BIT_11 |
| AnnaBridge | 189:f392fc9709a3 | 1182 | * @arg @ref LL_PWR_GPIO_BIT_12 |
| AnnaBridge | 189:f392fc9709a3 | 1183 | * @arg @ref LL_PWR_GPIO_BIT_13 |
| AnnaBridge | 189:f392fc9709a3 | 1184 | * @arg @ref LL_PWR_GPIO_BIT_14 |
| AnnaBridge | 189:f392fc9709a3 | 1185 | * @arg @ref LL_PWR_GPIO_BIT_15 |
| AnnaBridge | 189:f392fc9709a3 | 1186 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1187 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1188 | __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) |
| AnnaBridge | 189:f392fc9709a3 | 1189 | { |
| AnnaBridge | 189:f392fc9709a3 | 1190 | register uint32_t temp = (uint32_t)(GPIO) + 4; |
| AnnaBridge | 189:f392fc9709a3 | 1191 | SET_BIT(*((uint32_t *)(temp)), GPIONumber); |
| AnnaBridge | 189:f392fc9709a3 | 1192 | } |
| AnnaBridge | 189:f392fc9709a3 | 1193 | |
| AnnaBridge | 189:f392fc9709a3 | 1194 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1195 | * @brief Disable GPIO pull-down state in Standby and Shutdown modes |
| AnnaBridge | 189:f392fc9709a3 | 1196 | * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1197 | * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1198 | * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1199 | * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1200 | * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1201 | * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1202 | * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1203 | * PDCRH PD0-15 LL_PWR_DisableGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1204 | * PDCRI PD0-11 LL_PWR_DisableGPIOPullDown |
| AnnaBridge | 189:f392fc9709a3 | 1205 | * @param GPIO This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1206 | * @arg @ref LL_PWR_GPIO_A |
| AnnaBridge | 189:f392fc9709a3 | 1207 | * @arg @ref LL_PWR_GPIO_B |
| AnnaBridge | 189:f392fc9709a3 | 1208 | * @arg @ref LL_PWR_GPIO_C |
| AnnaBridge | 189:f392fc9709a3 | 1209 | * @arg @ref LL_PWR_GPIO_D |
| AnnaBridge | 189:f392fc9709a3 | 1210 | * @arg @ref LL_PWR_GPIO_E |
| AnnaBridge | 189:f392fc9709a3 | 1211 | * @arg @ref LL_PWR_GPIO_F (*) |
| AnnaBridge | 189:f392fc9709a3 | 1212 | * @arg @ref LL_PWR_GPIO_G (*) |
| AnnaBridge | 189:f392fc9709a3 | 1213 | * @arg @ref LL_PWR_GPIO_H |
| AnnaBridge | 189:f392fc9709a3 | 1214 | * @arg @ref LL_PWR_GPIO_I (*) |
| AnnaBridge | 189:f392fc9709a3 | 1215 | * |
| AnnaBridge | 189:f392fc9709a3 | 1216 | * (*) value not defined in all devices |
| AnnaBridge | 189:f392fc9709a3 | 1217 | * @param GPIONumber This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1218 | * @arg @ref LL_PWR_GPIO_BIT_0 |
| AnnaBridge | 189:f392fc9709a3 | 1219 | * @arg @ref LL_PWR_GPIO_BIT_1 |
| AnnaBridge | 189:f392fc9709a3 | 1220 | * @arg @ref LL_PWR_GPIO_BIT_2 |
| AnnaBridge | 189:f392fc9709a3 | 1221 | * @arg @ref LL_PWR_GPIO_BIT_3 |
| AnnaBridge | 189:f392fc9709a3 | 1222 | * @arg @ref LL_PWR_GPIO_BIT_4 |
| AnnaBridge | 189:f392fc9709a3 | 1223 | * @arg @ref LL_PWR_GPIO_BIT_5 |
| AnnaBridge | 189:f392fc9709a3 | 1224 | * @arg @ref LL_PWR_GPIO_BIT_6 |
| AnnaBridge | 189:f392fc9709a3 | 1225 | * @arg @ref LL_PWR_GPIO_BIT_7 |
| AnnaBridge | 189:f392fc9709a3 | 1226 | * @arg @ref LL_PWR_GPIO_BIT_8 |
| AnnaBridge | 189:f392fc9709a3 | 1227 | * @arg @ref LL_PWR_GPIO_BIT_9 |
| AnnaBridge | 189:f392fc9709a3 | 1228 | * @arg @ref LL_PWR_GPIO_BIT_10 |
| AnnaBridge | 189:f392fc9709a3 | 1229 | * @arg @ref LL_PWR_GPIO_BIT_11 |
| AnnaBridge | 189:f392fc9709a3 | 1230 | * @arg @ref LL_PWR_GPIO_BIT_12 |
| AnnaBridge | 189:f392fc9709a3 | 1231 | * @arg @ref LL_PWR_GPIO_BIT_13 |
| AnnaBridge | 189:f392fc9709a3 | 1232 | * @arg @ref LL_PWR_GPIO_BIT_14 |
| AnnaBridge | 189:f392fc9709a3 | 1233 | * @arg @ref LL_PWR_GPIO_BIT_15 |
| AnnaBridge | 189:f392fc9709a3 | 1234 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1235 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1236 | __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) |
| AnnaBridge | 189:f392fc9709a3 | 1237 | { |
| AnnaBridge | 189:f392fc9709a3 | 1238 | register uint32_t temp = (uint32_t)(GPIO) + 4; |
| AnnaBridge | 189:f392fc9709a3 | 1239 | CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber); |
| AnnaBridge | 189:f392fc9709a3 | 1240 | } |
| AnnaBridge | 189:f392fc9709a3 | 1241 | |
| AnnaBridge | 189:f392fc9709a3 | 1242 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1243 | * @brief Check if GPIO pull-down state is enabled |
| AnnaBridge | 189:f392fc9709a3 | 1244 | * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1245 | * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1246 | * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1247 | * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1248 | * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1249 | * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1250 | * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1251 | * PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
| AnnaBridge | 189:f392fc9709a3 | 1252 | * PDCRI PD0-11 LL_PWR_IsEnabledGPIOPullDown |
| AnnaBridge | 189:f392fc9709a3 | 1253 | * @param GPIO This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1254 | * @arg @ref LL_PWR_GPIO_A |
| AnnaBridge | 189:f392fc9709a3 | 1255 | * @arg @ref LL_PWR_GPIO_B |
| AnnaBridge | 189:f392fc9709a3 | 1256 | * @arg @ref LL_PWR_GPIO_C |
| AnnaBridge | 189:f392fc9709a3 | 1257 | * @arg @ref LL_PWR_GPIO_D |
| AnnaBridge | 189:f392fc9709a3 | 1258 | * @arg @ref LL_PWR_GPIO_E |
| AnnaBridge | 189:f392fc9709a3 | 1259 | * @arg @ref LL_PWR_GPIO_F (*) |
| AnnaBridge | 189:f392fc9709a3 | 1260 | * @arg @ref LL_PWR_GPIO_G (*) |
| AnnaBridge | 189:f392fc9709a3 | 1261 | * @arg @ref LL_PWR_GPIO_H |
| AnnaBridge | 189:f392fc9709a3 | 1262 | * @arg @ref LL_PWR_GPIO_I (*) |
| AnnaBridge | 189:f392fc9709a3 | 1263 | * |
| AnnaBridge | 189:f392fc9709a3 | 1264 | * (*) value not defined in all devices |
| AnnaBridge | 189:f392fc9709a3 | 1265 | * @param GPIONumber This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 1266 | * @arg @ref LL_PWR_GPIO_BIT_0 |
| AnnaBridge | 189:f392fc9709a3 | 1267 | * @arg @ref LL_PWR_GPIO_BIT_1 |
| AnnaBridge | 189:f392fc9709a3 | 1268 | * @arg @ref LL_PWR_GPIO_BIT_2 |
| AnnaBridge | 189:f392fc9709a3 | 1269 | * @arg @ref LL_PWR_GPIO_BIT_3 |
| AnnaBridge | 189:f392fc9709a3 | 1270 | * @arg @ref LL_PWR_GPIO_BIT_4 |
| AnnaBridge | 189:f392fc9709a3 | 1271 | * @arg @ref LL_PWR_GPIO_BIT_5 |
| AnnaBridge | 189:f392fc9709a3 | 1272 | * @arg @ref LL_PWR_GPIO_BIT_6 |
| AnnaBridge | 189:f392fc9709a3 | 1273 | * @arg @ref LL_PWR_GPIO_BIT_7 |
| AnnaBridge | 189:f392fc9709a3 | 1274 | * @arg @ref LL_PWR_GPIO_BIT_8 |
| AnnaBridge | 189:f392fc9709a3 | 1275 | * @arg @ref LL_PWR_GPIO_BIT_9 |
| AnnaBridge | 189:f392fc9709a3 | 1276 | * @arg @ref LL_PWR_GPIO_BIT_10 |
| AnnaBridge | 189:f392fc9709a3 | 1277 | * @arg @ref LL_PWR_GPIO_BIT_11 |
| AnnaBridge | 189:f392fc9709a3 | 1278 | * @arg @ref LL_PWR_GPIO_BIT_12 |
| AnnaBridge | 189:f392fc9709a3 | 1279 | * @arg @ref LL_PWR_GPIO_BIT_13 |
| AnnaBridge | 189:f392fc9709a3 | 1280 | * @arg @ref LL_PWR_GPIO_BIT_14 |
| AnnaBridge | 189:f392fc9709a3 | 1281 | * @arg @ref LL_PWR_GPIO_BIT_15 |
| AnnaBridge | 189:f392fc9709a3 | 1282 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1283 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1284 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) |
| AnnaBridge | 189:f392fc9709a3 | 1285 | { |
| AnnaBridge | 189:f392fc9709a3 | 1286 | register uint32_t temp = (uint32_t)(GPIO) + 4; |
| AnnaBridge | 189:f392fc9709a3 | 1287 | return (READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber)); |
| AnnaBridge | 189:f392fc9709a3 | 1288 | } |
| AnnaBridge | 189:f392fc9709a3 | 1289 | |
| AnnaBridge | 189:f392fc9709a3 | 1290 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1291 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1292 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1293 | |
| AnnaBridge | 189:f392fc9709a3 | 1294 | /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management |
| AnnaBridge | 189:f392fc9709a3 | 1295 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1296 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1297 | |
| AnnaBridge | 189:f392fc9709a3 | 1298 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1299 | * @brief Get Internal Wake-up line Flag |
| AnnaBridge | 189:f392fc9709a3 | 1300 | * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU |
| AnnaBridge | 189:f392fc9709a3 | 1301 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1302 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1303 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) |
| AnnaBridge | 189:f392fc9709a3 | 1304 | { |
| AnnaBridge | 189:f392fc9709a3 | 1305 | return (READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)); |
| AnnaBridge | 189:f392fc9709a3 | 1306 | } |
| AnnaBridge | 189:f392fc9709a3 | 1307 | |
| AnnaBridge | 189:f392fc9709a3 | 1308 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1309 | * @brief Get Stand-By Flag |
| AnnaBridge | 189:f392fc9709a3 | 1310 | * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB |
| AnnaBridge | 189:f392fc9709a3 | 1311 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1312 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1313 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) |
| AnnaBridge | 189:f392fc9709a3 | 1314 | { |
| AnnaBridge | 189:f392fc9709a3 | 1315 | return (READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)); |
| AnnaBridge | 189:f392fc9709a3 | 1316 | } |
| AnnaBridge | 189:f392fc9709a3 | 1317 | |
| AnnaBridge | 189:f392fc9709a3 | 1318 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1319 | * @brief Get Wake-up Flag 5 |
| AnnaBridge | 189:f392fc9709a3 | 1320 | * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5 |
| AnnaBridge | 189:f392fc9709a3 | 1321 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1322 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1323 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) |
| AnnaBridge | 189:f392fc9709a3 | 1324 | { |
| AnnaBridge | 189:f392fc9709a3 | 1325 | return (READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)); |
| AnnaBridge | 189:f392fc9709a3 | 1326 | } |
| AnnaBridge | 189:f392fc9709a3 | 1327 | |
| AnnaBridge | 189:f392fc9709a3 | 1328 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1329 | * @brief Get Wake-up Flag 4 |
| AnnaBridge | 189:f392fc9709a3 | 1330 | * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4 |
| AnnaBridge | 189:f392fc9709a3 | 1331 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1332 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1333 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) |
| AnnaBridge | 189:f392fc9709a3 | 1334 | { |
| AnnaBridge | 189:f392fc9709a3 | 1335 | return (READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)); |
| AnnaBridge | 189:f392fc9709a3 | 1336 | } |
| AnnaBridge | 189:f392fc9709a3 | 1337 | |
| AnnaBridge | 189:f392fc9709a3 | 1338 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1339 | * @brief Get Wake-up Flag 3 |
| AnnaBridge | 189:f392fc9709a3 | 1340 | * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3 |
| AnnaBridge | 189:f392fc9709a3 | 1341 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1342 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1343 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) |
| AnnaBridge | 189:f392fc9709a3 | 1344 | { |
| AnnaBridge | 189:f392fc9709a3 | 1345 | return (READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)); |
| AnnaBridge | 189:f392fc9709a3 | 1346 | } |
| AnnaBridge | 189:f392fc9709a3 | 1347 | |
| AnnaBridge | 189:f392fc9709a3 | 1348 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1349 | * @brief Get Wake-up Flag 2 |
| AnnaBridge | 189:f392fc9709a3 | 1350 | * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2 |
| AnnaBridge | 189:f392fc9709a3 | 1351 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1352 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1353 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) |
| AnnaBridge | 189:f392fc9709a3 | 1354 | { |
| AnnaBridge | 189:f392fc9709a3 | 1355 | return (READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)); |
| AnnaBridge | 189:f392fc9709a3 | 1356 | } |
| AnnaBridge | 189:f392fc9709a3 | 1357 | |
| AnnaBridge | 189:f392fc9709a3 | 1358 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1359 | * @brief Get Wake-up Flag 1 |
| AnnaBridge | 189:f392fc9709a3 | 1360 | * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1 |
| AnnaBridge | 189:f392fc9709a3 | 1361 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1362 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1363 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) |
| AnnaBridge | 189:f392fc9709a3 | 1364 | { |
| AnnaBridge | 189:f392fc9709a3 | 1365 | return (READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)); |
| AnnaBridge | 189:f392fc9709a3 | 1366 | } |
| AnnaBridge | 189:f392fc9709a3 | 1367 | |
| AnnaBridge | 189:f392fc9709a3 | 1368 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1369 | * @brief Clear Stand-By Flag |
| AnnaBridge | 189:f392fc9709a3 | 1370 | * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB |
| AnnaBridge | 189:f392fc9709a3 | 1371 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1372 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1373 | __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) |
| AnnaBridge | 189:f392fc9709a3 | 1374 | { |
| AnnaBridge | 189:f392fc9709a3 | 1375 | WRITE_REG(PWR->SCR, PWR_SCR_CSBF); |
| AnnaBridge | 189:f392fc9709a3 | 1376 | } |
| AnnaBridge | 189:f392fc9709a3 | 1377 | |
| AnnaBridge | 189:f392fc9709a3 | 1378 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1379 | * @brief Clear Wake-up Flags |
| AnnaBridge | 189:f392fc9709a3 | 1380 | * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU |
| AnnaBridge | 189:f392fc9709a3 | 1381 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1382 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1383 | __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) |
| AnnaBridge | 189:f392fc9709a3 | 1384 | { |
| AnnaBridge | 189:f392fc9709a3 | 1385 | WRITE_REG(PWR->SCR, PWR_SCR_CWUF); |
| AnnaBridge | 189:f392fc9709a3 | 1386 | } |
| AnnaBridge | 189:f392fc9709a3 | 1387 | |
| AnnaBridge | 189:f392fc9709a3 | 1388 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1389 | * @brief Clear Wake-up Flag 5 |
| AnnaBridge | 189:f392fc9709a3 | 1390 | * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5 |
| AnnaBridge | 189:f392fc9709a3 | 1391 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1392 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1393 | __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) |
| AnnaBridge | 189:f392fc9709a3 | 1394 | { |
| AnnaBridge | 189:f392fc9709a3 | 1395 | WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); |
| AnnaBridge | 189:f392fc9709a3 | 1396 | } |
| AnnaBridge | 189:f392fc9709a3 | 1397 | |
| AnnaBridge | 189:f392fc9709a3 | 1398 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1399 | * @brief Clear Wake-up Flag 4 |
| AnnaBridge | 189:f392fc9709a3 | 1400 | * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4 |
| AnnaBridge | 189:f392fc9709a3 | 1401 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1402 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1403 | __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) |
| AnnaBridge | 189:f392fc9709a3 | 1404 | { |
| AnnaBridge | 189:f392fc9709a3 | 1405 | WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); |
| AnnaBridge | 189:f392fc9709a3 | 1406 | } |
| AnnaBridge | 189:f392fc9709a3 | 1407 | |
| AnnaBridge | 189:f392fc9709a3 | 1408 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1409 | * @brief Clear Wake-up Flag 3 |
| AnnaBridge | 189:f392fc9709a3 | 1410 | * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3 |
| AnnaBridge | 189:f392fc9709a3 | 1411 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1412 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1413 | __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) |
| AnnaBridge | 189:f392fc9709a3 | 1414 | { |
| AnnaBridge | 189:f392fc9709a3 | 1415 | WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); |
| AnnaBridge | 189:f392fc9709a3 | 1416 | } |
| AnnaBridge | 189:f392fc9709a3 | 1417 | |
| AnnaBridge | 189:f392fc9709a3 | 1418 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1419 | * @brief Clear Wake-up Flag 2 |
| AnnaBridge | 189:f392fc9709a3 | 1420 | * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2 |
| AnnaBridge | 189:f392fc9709a3 | 1421 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1422 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1423 | __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) |
| AnnaBridge | 189:f392fc9709a3 | 1424 | { |
| AnnaBridge | 189:f392fc9709a3 | 1425 | WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); |
| AnnaBridge | 189:f392fc9709a3 | 1426 | } |
| AnnaBridge | 189:f392fc9709a3 | 1427 | |
| AnnaBridge | 189:f392fc9709a3 | 1428 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1429 | * @brief Clear Wake-up Flag 1 |
| AnnaBridge | 189:f392fc9709a3 | 1430 | * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1 |
| AnnaBridge | 189:f392fc9709a3 | 1431 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 1432 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1433 | __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) |
| AnnaBridge | 189:f392fc9709a3 | 1434 | { |
| AnnaBridge | 189:f392fc9709a3 | 1435 | WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); |
| AnnaBridge | 189:f392fc9709a3 | 1436 | } |
| AnnaBridge | 189:f392fc9709a3 | 1437 | |
| AnnaBridge | 189:f392fc9709a3 | 1438 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1439 | * @brief Indicate whether VDDA voltage is below or above PVM4 threshold |
| AnnaBridge | 189:f392fc9709a3 | 1440 | * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4 |
| AnnaBridge | 189:f392fc9709a3 | 1441 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1442 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1443 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void) |
| AnnaBridge | 189:f392fc9709a3 | 1444 | { |
| AnnaBridge | 189:f392fc9709a3 | 1445 | return (READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)); |
| AnnaBridge | 189:f392fc9709a3 | 1446 | } |
| AnnaBridge | 189:f392fc9709a3 | 1447 | |
| AnnaBridge | 189:f392fc9709a3 | 1448 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1449 | * @brief Indicate whether VDDA voltage is below or above PVM3 threshold |
| AnnaBridge | 189:f392fc9709a3 | 1450 | * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3 |
| AnnaBridge | 189:f392fc9709a3 | 1451 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1452 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1453 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void) |
| AnnaBridge | 189:f392fc9709a3 | 1454 | { |
| AnnaBridge | 189:f392fc9709a3 | 1455 | return (READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)); |
| AnnaBridge | 189:f392fc9709a3 | 1456 | } |
| AnnaBridge | 189:f392fc9709a3 | 1457 | |
| AnnaBridge | 189:f392fc9709a3 | 1458 | #if defined(PWR_SR2_PVMO2) |
| AnnaBridge | 189:f392fc9709a3 | 1459 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1460 | * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold |
| AnnaBridge | 189:f392fc9709a3 | 1461 | * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2 |
| AnnaBridge | 189:f392fc9709a3 | 1462 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1463 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1464 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void) |
| AnnaBridge | 189:f392fc9709a3 | 1465 | { |
| AnnaBridge | 189:f392fc9709a3 | 1466 | return (READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)); |
| AnnaBridge | 189:f392fc9709a3 | 1467 | } |
| AnnaBridge | 189:f392fc9709a3 | 1468 | #endif /* PWR_SR2_PVMO2 */ |
| AnnaBridge | 189:f392fc9709a3 | 1469 | |
| AnnaBridge | 189:f392fc9709a3 | 1470 | #if defined(PWR_SR2_PVMO1) |
| AnnaBridge | 189:f392fc9709a3 | 1471 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1472 | * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold |
| AnnaBridge | 189:f392fc9709a3 | 1473 | * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1 |
| AnnaBridge | 189:f392fc9709a3 | 1474 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1475 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1476 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void) |
| AnnaBridge | 189:f392fc9709a3 | 1477 | { |
| AnnaBridge | 189:f392fc9709a3 | 1478 | return (READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)); |
| AnnaBridge | 189:f392fc9709a3 | 1479 | } |
| AnnaBridge | 189:f392fc9709a3 | 1480 | #endif /* PWR_SR2_PVMO1 */ |
| AnnaBridge | 189:f392fc9709a3 | 1481 | |
| AnnaBridge | 189:f392fc9709a3 | 1482 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1483 | * @brief Indicate whether VDD voltage is below or above the selected PVD threshold |
| AnnaBridge | 189:f392fc9709a3 | 1484 | * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO |
| AnnaBridge | 189:f392fc9709a3 | 1485 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1486 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1487 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) |
| AnnaBridge | 189:f392fc9709a3 | 1488 | { |
| AnnaBridge | 189:f392fc9709a3 | 1489 | return (READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)); |
| AnnaBridge | 189:f392fc9709a3 | 1490 | } |
| AnnaBridge | 189:f392fc9709a3 | 1491 | |
| AnnaBridge | 189:f392fc9709a3 | 1492 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1493 | * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level |
| AnnaBridge | 189:f392fc9709a3 | 1494 | * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS |
| AnnaBridge | 189:f392fc9709a3 | 1495 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1496 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1497 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) |
| AnnaBridge | 189:f392fc9709a3 | 1498 | { |
| AnnaBridge | 189:f392fc9709a3 | 1499 | return (READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)); |
| AnnaBridge | 189:f392fc9709a3 | 1500 | } |
| AnnaBridge | 189:f392fc9709a3 | 1501 | |
| AnnaBridge | 189:f392fc9709a3 | 1502 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1503 | * @brief Indicate whether the regulator is ready in main mode or is in low-power mode |
| AnnaBridge | 189:f392fc9709a3 | 1504 | * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. |
| AnnaBridge | 189:f392fc9709a3 | 1505 | * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF |
| AnnaBridge | 189:f392fc9709a3 | 1506 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1507 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1508 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) |
| AnnaBridge | 189:f392fc9709a3 | 1509 | { |
| AnnaBridge | 189:f392fc9709a3 | 1510 | return (READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)); |
| AnnaBridge | 189:f392fc9709a3 | 1511 | } |
| AnnaBridge | 189:f392fc9709a3 | 1512 | |
| AnnaBridge | 189:f392fc9709a3 | 1513 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1514 | * @brief Indicate whether or not the low-power regulator is ready |
| AnnaBridge | 189:f392fc9709a3 | 1515 | * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS |
| AnnaBridge | 189:f392fc9709a3 | 1516 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 1517 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1518 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void) |
| AnnaBridge | 189:f392fc9709a3 | 1519 | { |
| AnnaBridge | 189:f392fc9709a3 | 1520 | return (READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)); |
| AnnaBridge | 189:f392fc9709a3 | 1521 | } |
| AnnaBridge | 189:f392fc9709a3 | 1522 | |
| AnnaBridge | 189:f392fc9709a3 | 1523 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1524 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1525 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1526 | |
| AnnaBridge | 189:f392fc9709a3 | 1527 | #if defined(USE_FULL_LL_DRIVER) |
| AnnaBridge | 189:f392fc9709a3 | 1528 | /** @defgroup PWR_LL_EF_Init De-initialization function |
| AnnaBridge | 189:f392fc9709a3 | 1529 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1530 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1531 | ErrorStatus LL_PWR_DeInit(void); |
| AnnaBridge | 189:f392fc9709a3 | 1532 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1533 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1534 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1535 | #endif /* USE_FULL_LL_DRIVER */ |
| AnnaBridge | 189:f392fc9709a3 | 1536 | |
| AnnaBridge | 189:f392fc9709a3 | 1537 | /** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name |
| AnnaBridge | 189:f392fc9709a3 | 1538 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 1539 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1540 | /* Old functions name kept for legacy purpose, to be replaced by the */ |
| AnnaBridge | 189:f392fc9709a3 | 1541 | /* current functions name. */ |
| AnnaBridge | 189:f392fc9709a3 | 1542 | #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS |
| AnnaBridge | 189:f392fc9709a3 | 1543 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1544 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1545 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1546 | |
| AnnaBridge | 189:f392fc9709a3 | 1547 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1548 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1549 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1550 | |
| AnnaBridge | 189:f392fc9709a3 | 1551 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1552 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1553 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1554 | |
| AnnaBridge | 189:f392fc9709a3 | 1555 | #endif /* defined(PWR) */ |
| AnnaBridge | 189:f392fc9709a3 | 1556 | |
| AnnaBridge | 189:f392fc9709a3 | 1557 | /** |
| AnnaBridge | 189:f392fc9709a3 | 1558 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 1559 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1560 | |
| AnnaBridge | 189:f392fc9709a3 | 1561 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 1562 | } |
| AnnaBridge | 189:f392fc9709a3 | 1563 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 1564 | |
| AnnaBridge | 189:f392fc9709a3 | 1565 | #endif /* __STM32L4xx_LL_PWR_H */ |
| AnnaBridge | 189:f392fc9709a3 | 1566 | |
| AnnaBridge | 189:f392fc9709a3 | 1567 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
