mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_ARM_STD/stm32l4xx_ll_lpuart.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l4xx_ll_lpuart.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of LPUART LL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L4xx_LL_LPUART_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L4xx_LL_LPUART_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	45	#include "stm32l4xx.h"
AnnaBridge	189:f392fc9709a3	46
AnnaBridge	189:f392fc9709a3	47	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	189:f392fc9709a3	48	* @{
AnnaBridge	189:f392fc9709a3	49	*/
AnnaBridge	189:f392fc9709a3	50
AnnaBridge	189:f392fc9709a3	51	#if defined (LPUART1)
AnnaBridge	189:f392fc9709a3	52
AnnaBridge	189:f392fc9709a3	53	/** @defgroup LPUART_LL LPUART
AnnaBridge	189:f392fc9709a3	54	* @{
AnnaBridge	189:f392fc9709a3	55	*/
AnnaBridge	189:f392fc9709a3	56
AnnaBridge	189:f392fc9709a3	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	59	#if defined(USART_PRESC_PRESCALER)
AnnaBridge	189:f392fc9709a3	60	/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
AnnaBridge	189:f392fc9709a3	61	* @{
AnnaBridge	189:f392fc9709a3	62	*/
AnnaBridge	189:f392fc9709a3	63	/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
AnnaBridge	189:f392fc9709a3	64	static const uint16_t LPUART_PRESCALER_TAB[] =
AnnaBridge	189:f392fc9709a3	65	{
AnnaBridge	189:f392fc9709a3	66	(uint16_t)1,
AnnaBridge	189:f392fc9709a3	67	(uint16_t)2,
AnnaBridge	189:f392fc9709a3	68	(uint16_t)4,
AnnaBridge	189:f392fc9709a3	69	(uint16_t)6,
AnnaBridge	189:f392fc9709a3	70	(uint16_t)8,
AnnaBridge	189:f392fc9709a3	71	(uint16_t)10,
AnnaBridge	189:f392fc9709a3	72	(uint16_t)12,
AnnaBridge	189:f392fc9709a3	73	(uint16_t)16,
AnnaBridge	189:f392fc9709a3	74	(uint16_t)32,
AnnaBridge	189:f392fc9709a3	75	(uint16_t)64,
AnnaBridge	189:f392fc9709a3	76	(uint16_t)128,
AnnaBridge	189:f392fc9709a3	77	(uint16_t)256
AnnaBridge	189:f392fc9709a3	78	};
AnnaBridge	189:f392fc9709a3	79	/**
AnnaBridge	189:f392fc9709a3	80	* @}
AnnaBridge	189:f392fc9709a3	81	*/
AnnaBridge	189:f392fc9709a3	82	#endif
AnnaBridge	189:f392fc9709a3	83
AnnaBridge	189:f392fc9709a3	84	/* Private constants ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	85	/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
AnnaBridge	189:f392fc9709a3	86	* @{
AnnaBridge	189:f392fc9709a3	87	*/
AnnaBridge	189:f392fc9709a3	88	/* Defines used in Baud Rate related macros and corresponding register setting computation */
AnnaBridge	189:f392fc9709a3	89	#define LPUART_LPUARTDIV_FREQ_MUL 256U
AnnaBridge	189:f392fc9709a3	90	#define LPUART_BRR_MASK 0x000FFFFFU
AnnaBridge	189:f392fc9709a3	91	#define LPUART_BRR_MIN_VALUE 0x00000300U
AnnaBridge	189:f392fc9709a3	92	/**
AnnaBridge	189:f392fc9709a3	93	* @}
AnnaBridge	189:f392fc9709a3	94	*/
AnnaBridge	189:f392fc9709a3	95
AnnaBridge	189:f392fc9709a3	96
AnnaBridge	189:f392fc9709a3	97	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	98	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	99	/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
AnnaBridge	189:f392fc9709a3	100	* @{
AnnaBridge	189:f392fc9709a3	101	*/
AnnaBridge	189:f392fc9709a3	102	/**
AnnaBridge	189:f392fc9709a3	103	* @}
AnnaBridge	189:f392fc9709a3	104	*/
AnnaBridge	189:f392fc9709a3	105	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	189:f392fc9709a3	106
AnnaBridge	189:f392fc9709a3	107	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	108	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	109	/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
AnnaBridge	189:f392fc9709a3	110	* @{
AnnaBridge	189:f392fc9709a3	111	*/
AnnaBridge	189:f392fc9709a3	112
AnnaBridge	189:f392fc9709a3	113	/**
AnnaBridge	189:f392fc9709a3	114	* @brief LL LPUART Init Structure definition
AnnaBridge	189:f392fc9709a3	115	*/
AnnaBridge	189:f392fc9709a3	116	typedef struct
AnnaBridge	189:f392fc9709a3	117	{
AnnaBridge	189:f392fc9709a3	118	#if defined(USART_PRESC_PRESCALER)
AnnaBridge	189:f392fc9709a3	119	uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
AnnaBridge	189:f392fc9709a3	120	This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
AnnaBridge	189:f392fc9709a3	121
AnnaBridge	189:f392fc9709a3	122	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/
AnnaBridge	189:f392fc9709a3	123
AnnaBridge	189:f392fc9709a3	124	#endif
AnnaBridge	189:f392fc9709a3	125	uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
AnnaBridge	189:f392fc9709a3	126
AnnaBridge	189:f392fc9709a3	127	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
AnnaBridge	189:f392fc9709a3	128
AnnaBridge	189:f392fc9709a3	129	uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
AnnaBridge	189:f392fc9709a3	130	This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
AnnaBridge	189:f392fc9709a3	131
AnnaBridge	189:f392fc9709a3	132	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
AnnaBridge	189:f392fc9709a3	133
AnnaBridge	189:f392fc9709a3	134	uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
AnnaBridge	189:f392fc9709a3	135	This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
AnnaBridge	189:f392fc9709a3	136
AnnaBridge	189:f392fc9709a3	137	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
AnnaBridge	189:f392fc9709a3	138
AnnaBridge	189:f392fc9709a3	139	uint32_t Parity; /*!< Specifies the parity mode.
AnnaBridge	189:f392fc9709a3	140	This parameter can be a value of @ref LPUART_LL_EC_PARITY.
AnnaBridge	189:f392fc9709a3	141
AnnaBridge	189:f392fc9709a3	142	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
AnnaBridge	189:f392fc9709a3	143
AnnaBridge	189:f392fc9709a3	144	uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
AnnaBridge	189:f392fc9709a3	145	This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
AnnaBridge	189:f392fc9709a3	146
AnnaBridge	189:f392fc9709a3	147	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
AnnaBridge	189:f392fc9709a3	148
AnnaBridge	189:f392fc9709a3	149	uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
AnnaBridge	189:f392fc9709a3	150	This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
AnnaBridge	189:f392fc9709a3	151
AnnaBridge	189:f392fc9709a3	152	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
AnnaBridge	189:f392fc9709a3	153
AnnaBridge	189:f392fc9709a3	154	} LL_LPUART_InitTypeDef;
AnnaBridge	189:f392fc9709a3	155
AnnaBridge	189:f392fc9709a3	156	/**
AnnaBridge	189:f392fc9709a3	157	* @}
AnnaBridge	189:f392fc9709a3	158	*/
AnnaBridge	189:f392fc9709a3	159	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	160
AnnaBridge	189:f392fc9709a3	161	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	162	/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
AnnaBridge	189:f392fc9709a3	163	* @{
AnnaBridge	189:f392fc9709a3	164	*/
AnnaBridge	189:f392fc9709a3	165
AnnaBridge	189:f392fc9709a3	166	/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	189:f392fc9709a3	167	* @brief Flags defines which can be used with LL_LPUART_WriteReg function
AnnaBridge	189:f392fc9709a3	168	* @{
AnnaBridge	189:f392fc9709a3	169	*/
AnnaBridge	189:f392fc9709a3	170	#define LL_LPUART_ICR_PECF USART_ICR_PECF /!< Parity error flag /
AnnaBridge	189:f392fc9709a3	171	#define LL_LPUART_ICR_FECF USART_ICR_FECF /!< Framing error flag /
AnnaBridge	189:f392fc9709a3	172	#define LL_LPUART_ICR_NCF USART_ICR_NCF /!< Noise detected flag /
AnnaBridge	189:f392fc9709a3	173	#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /!< Overrun error flag /
AnnaBridge	189:f392fc9709a3	174	#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /!< Idle line detected flag /
AnnaBridge	189:f392fc9709a3	175	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	176	#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /!< TX FIFO Empty Clear flag /
AnnaBridge	189:f392fc9709a3	177	#endif
AnnaBridge	189:f392fc9709a3	178	#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /!< Transmission complete flag /
AnnaBridge	189:f392fc9709a3	179	#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /!< CTS flag /
AnnaBridge	189:f392fc9709a3	180	#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /!< Character match flag /
AnnaBridge	189:f392fc9709a3	181	#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /!< Wakeup from Stop mode flag /
AnnaBridge	189:f392fc9709a3	182	/**
AnnaBridge	189:f392fc9709a3	183	* @}
AnnaBridge	189:f392fc9709a3	184	*/
AnnaBridge	189:f392fc9709a3	185
AnnaBridge	189:f392fc9709a3	186	/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	189:f392fc9709a3	187	* @brief Flags defines which can be used with LL_LPUART_ReadReg function
AnnaBridge	189:f392fc9709a3	188	* @{
AnnaBridge	189:f392fc9709a3	189	*/
AnnaBridge	189:f392fc9709a3	190	#define LL_LPUART_ISR_PE USART_ISR_PE /!< Parity error flag /
AnnaBridge	189:f392fc9709a3	191	#define LL_LPUART_ISR_FE USART_ISR_FE /!< Framing error flag /
AnnaBridge	189:f392fc9709a3	192	#define LL_LPUART_ISR_NE USART_ISR_NE /!< Noise detected flag /
AnnaBridge	189:f392fc9709a3	193	#define LL_LPUART_ISR_ORE USART_ISR_ORE /!< Overrun error flag /
AnnaBridge	189:f392fc9709a3	194	#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /!< Idle line detected flag /
AnnaBridge	189:f392fc9709a3	195	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	196	#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /!< Read data register or RX FIFO not empty flag /
AnnaBridge	189:f392fc9709a3	197	#else
AnnaBridge	189:f392fc9709a3	198	#define LL_LPUART_ISR_RXNE USART_ISR_RXNE /!< Read data register not empty flag /
AnnaBridge	189:f392fc9709a3	199	#endif
AnnaBridge	189:f392fc9709a3	200	#define LL_LPUART_ISR_TC USART_ISR_TC /!< Transmission complete flag /
AnnaBridge	189:f392fc9709a3	201	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	202	#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /!< Transmit data register empty or TX FIFO Not Full flag/
AnnaBridge	189:f392fc9709a3	203	#else
AnnaBridge	189:f392fc9709a3	204	#define LL_LPUART_ISR_TXE USART_ISR_TXE /!< Transmit data register empty flag /
AnnaBridge	189:f392fc9709a3	205	#endif
AnnaBridge	189:f392fc9709a3	206	#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /!< CTS interrupt flag /
AnnaBridge	189:f392fc9709a3	207	#define LL_LPUART_ISR_CTS USART_ISR_CTS /!< CTS flag /
AnnaBridge	189:f392fc9709a3	208	#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /!< Busy flag /
AnnaBridge	189:f392fc9709a3	209	#define LL_LPUART_ISR_CMF USART_ISR_CMF /!< Character match flag /
AnnaBridge	189:f392fc9709a3	210	#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /!< Send break flag /
AnnaBridge	189:f392fc9709a3	211	#define LL_LPUART_ISR_RWU USART_ISR_RWU /!< Receiver wakeup from Mute mode flag /
AnnaBridge	189:f392fc9709a3	212	#define LL_LPUART_ISR_WUF USART_ISR_WUF /!< Wakeup from Stop mode flag /
AnnaBridge	189:f392fc9709a3	213	#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /!< Transmit enable acknowledge flag /
AnnaBridge	189:f392fc9709a3	214	#define LL_LPUART_ISR_REACK USART_ISR_REACK /!< Receive enable acknowledge flag /
AnnaBridge	189:f392fc9709a3	215	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	216	#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /!< TX FIFO empty flag /
AnnaBridge	189:f392fc9709a3	217	#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /!< RX FIFO full flag /
AnnaBridge	189:f392fc9709a3	218	#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /!< RX FIFO threshold flag /
AnnaBridge	189:f392fc9709a3	219	#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /!< TX FIFO threshold flag /
AnnaBridge	189:f392fc9709a3	220	#endif
AnnaBridge	189:f392fc9709a3	221	/**
AnnaBridge	189:f392fc9709a3	222	* @}
AnnaBridge	189:f392fc9709a3	223	*/
AnnaBridge	189:f392fc9709a3	224
AnnaBridge	189:f392fc9709a3	225	/** @defgroup LPUART_LL_EC_IT IT Defines
AnnaBridge	189:f392fc9709a3	226	* @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
AnnaBridge	189:f392fc9709a3	227	* @{
AnnaBridge	189:f392fc9709a3	228	*/
AnnaBridge	189:f392fc9709a3	229	#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /!< IDLE interrupt enable /
AnnaBridge	189:f392fc9709a3	230	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	231	#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /!< Read data register and RXFIFO not empty interrupt enable /
AnnaBridge	189:f392fc9709a3	232	#else
AnnaBridge	189:f392fc9709a3	233	#define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /!< Read data register not empty interrupt enable /
AnnaBridge	189:f392fc9709a3	234	#endif
AnnaBridge	189:f392fc9709a3	235	#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /!< Transmission complete interrupt enable /
AnnaBridge	189:f392fc9709a3	236	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	237	#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /!< Transmit data register empty and TX FIFO not full interrupt enable /
AnnaBridge	189:f392fc9709a3	238	#else
AnnaBridge	189:f392fc9709a3	239	#define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /!< Transmit data register empty interrupt enable /
AnnaBridge	189:f392fc9709a3	240	#endif
AnnaBridge	189:f392fc9709a3	241	#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /!< Parity error /
AnnaBridge	189:f392fc9709a3	242	#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /!< Character match interrupt enable /
AnnaBridge	189:f392fc9709a3	243	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	244	#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /!< TX FIFO empty interrupt enable /
AnnaBridge	189:f392fc9709a3	245	#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /!< RX FIFO full interrupt enable /
AnnaBridge	189:f392fc9709a3	246	#endif
AnnaBridge	189:f392fc9709a3	247	#define LL_LPUART_CR3_EIE USART_CR3_EIE /!< Error interrupt enable /
AnnaBridge	189:f392fc9709a3	248	#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /!< CTS interrupt enable /
AnnaBridge	189:f392fc9709a3	249	#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /!< Wakeup from Stop mode interrupt enable /
AnnaBridge	189:f392fc9709a3	250	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	251	#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /!< TX FIFO threshold interrupt enable /
AnnaBridge	189:f392fc9709a3	252	#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /!< RX FIFO threshold interrupt enable /
AnnaBridge	189:f392fc9709a3	253	#endif
AnnaBridge	189:f392fc9709a3	254	/**
AnnaBridge	189:f392fc9709a3	255	* @}
AnnaBridge	189:f392fc9709a3	256	*/
AnnaBridge	189:f392fc9709a3	257	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	258
AnnaBridge	189:f392fc9709a3	259	/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
AnnaBridge	189:f392fc9709a3	260	* @{
AnnaBridge	189:f392fc9709a3	261	*/
AnnaBridge	189:f392fc9709a3	262	#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /!< FIFO reaches 1/8 of its depth /
AnnaBridge	189:f392fc9709a3	263	#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /!< FIFO reaches 1/4 of its depth /
AnnaBridge	189:f392fc9709a3	264	#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /!< FIFO reaches 1/2 of its depth /
AnnaBridge	189:f392fc9709a3	265	#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /!< FIFO reaches 3/4 of its depth /
AnnaBridge	189:f392fc9709a3	266	#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /!< FIFO reaches 7/8 of its depth /
AnnaBridge	189:f392fc9709a3	267	#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /!< FIFO becomes empty for TX and full for RX /
AnnaBridge	189:f392fc9709a3	268	/**
AnnaBridge	189:f392fc9709a3	269	* @}
AnnaBridge	189:f392fc9709a3	270	*/
AnnaBridge	189:f392fc9709a3	271	#endif
AnnaBridge	189:f392fc9709a3	272
AnnaBridge	189:f392fc9709a3	273	/** @defgroup LPUART_LL_EC_DIRECTION Direction
AnnaBridge	189:f392fc9709a3	274	* @{
AnnaBridge	189:f392fc9709a3	275	*/
AnnaBridge	189:f392fc9709a3	276	#define LL_LPUART_DIRECTION_NONE 0x00000000U /!< Transmitter and Receiver are disabled /
AnnaBridge	189:f392fc9709a3	277	#define LL_LPUART_DIRECTION_RX USART_CR1_RE /!< Transmitter is disabled and Receiver is enabled /
AnnaBridge	189:f392fc9709a3	278	#define LL_LPUART_DIRECTION_TX USART_CR1_TE /!< Transmitter is enabled and Receiver is disabled /
AnnaBridge	189:f392fc9709a3	279	#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE \|USART_CR1_RE) /!< Transmitter and Receiver are enabled /
AnnaBridge	189:f392fc9709a3	280	/**
AnnaBridge	189:f392fc9709a3	281	* @}
AnnaBridge	189:f392fc9709a3	282	*/
AnnaBridge	189:f392fc9709a3	283
AnnaBridge	189:f392fc9709a3	284	/** @defgroup LPUART_LL_EC_PARITY Parity Control
AnnaBridge	189:f392fc9709a3	285	* @{
AnnaBridge	189:f392fc9709a3	286	*/
AnnaBridge	189:f392fc9709a3	287	#define LL_LPUART_PARITY_NONE 0x00000000U /!< Parity control disabled /
AnnaBridge	189:f392fc9709a3	288	#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /!< Parity control enabled and Even Parity is selected /
AnnaBridge	189:f392fc9709a3	289	#define LL_LPUART_PARITY_ODD (USART_CR1_PCE \| USART_CR1_PS) /!< Parity control enabled and Odd Parity is selected /
AnnaBridge	189:f392fc9709a3	290	/**
AnnaBridge	189:f392fc9709a3	291	* @}
AnnaBridge	189:f392fc9709a3	292	*/
AnnaBridge	189:f392fc9709a3	293
AnnaBridge	189:f392fc9709a3	294	/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
AnnaBridge	189:f392fc9709a3	295	* @{
AnnaBridge	189:f392fc9709a3	296	*/
AnnaBridge	189:f392fc9709a3	297	#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /!< LPUART wake up from Mute mode on Idle Line /
AnnaBridge	189:f392fc9709a3	298	#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /!< LPUART wake up from Mute mode on Address Mark /
AnnaBridge	189:f392fc9709a3	299	/**
AnnaBridge	189:f392fc9709a3	300	* @}
AnnaBridge	189:f392fc9709a3	301	*/
AnnaBridge	189:f392fc9709a3	302
AnnaBridge	189:f392fc9709a3	303	/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
AnnaBridge	189:f392fc9709a3	304	* @{
AnnaBridge	189:f392fc9709a3	305	*/
AnnaBridge	189:f392fc9709a3	306	#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /!< 7 bits word length : Start bit, 7 data bits, n stop bits /
AnnaBridge	189:f392fc9709a3	307	#define LL_LPUART_DATAWIDTH_8B 0x00000000U /!< 8 bits word length : Start bit, 8 data bits, n stop bits /
AnnaBridge	189:f392fc9709a3	308	#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /!< 9 bits word length : Start bit, 9 data bits, n stop bits /
AnnaBridge	189:f392fc9709a3	309	/**
AnnaBridge	189:f392fc9709a3	310	* @}
AnnaBridge	189:f392fc9709a3	311	*/
AnnaBridge	189:f392fc9709a3	312	#if defined(USART_PRESC_PRESCALER)
AnnaBridge	189:f392fc9709a3	313
AnnaBridge	189:f392fc9709a3	314	/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
AnnaBridge	189:f392fc9709a3	315	* @{
AnnaBridge	189:f392fc9709a3	316	*/
AnnaBridge	189:f392fc9709a3	317	#define LL_LPUART_PRESCALER_DIV1 0x00000000U /!< Input clock not devided /
AnnaBridge	189:f392fc9709a3	318	#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /!< Input clock devided by 2 /
AnnaBridge	189:f392fc9709a3	319	#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /!< Input clock devided by 4 /
AnnaBridge	189:f392fc9709a3	320	#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 \| USART_PRESC_PRESCALER_0) /!< Input clock devided by 6 /
AnnaBridge	189:f392fc9709a3	321	#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /!< Input clock devided by 8 /
AnnaBridge	189:f392fc9709a3	322	#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 \| USART_PRESC_PRESCALER_0) /!< Input clock devided by 10 /
AnnaBridge	189:f392fc9709a3	323	#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 \| USART_PRESC_PRESCALER_1) /!< Input clock devided by 12 /
AnnaBridge	189:f392fc9709a3	324	#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 \| USART_PRESC_PRESCALER_1 \| USART_PRESC_PRESCALER_0) /!< Input clock devided by 16 /
AnnaBridge	189:f392fc9709a3	325	#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /!< Input clock devided by 32 /
AnnaBridge	189:f392fc9709a3	326	#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 \| USART_PRESC_PRESCALER_0) /!< Input clock devided by 64 /
AnnaBridge	189:f392fc9709a3	327	#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 \| USART_PRESC_PRESCALER_1) /!< Input clock devided by 128 /
AnnaBridge	189:f392fc9709a3	328	#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 \| USART_PRESC_PRESCALER_1 \| USART_PRESC_PRESCALER_0) /!< Input clock devided by 256 /
AnnaBridge	189:f392fc9709a3	329	/**
AnnaBridge	189:f392fc9709a3	330	* @}
AnnaBridge	189:f392fc9709a3	331	*/
AnnaBridge	189:f392fc9709a3	332	#endif
AnnaBridge	189:f392fc9709a3	333
AnnaBridge	189:f392fc9709a3	334	/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
AnnaBridge	189:f392fc9709a3	335	* @{
AnnaBridge	189:f392fc9709a3	336	*/
AnnaBridge	189:f392fc9709a3	337	#define LL_LPUART_STOPBITS_1 0x00000000U /!< 1 stop bit /
AnnaBridge	189:f392fc9709a3	338	#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /!< 2 stop bits /
AnnaBridge	189:f392fc9709a3	339	/**
AnnaBridge	189:f392fc9709a3	340	* @}
AnnaBridge	189:f392fc9709a3	341	*/
AnnaBridge	189:f392fc9709a3	342
AnnaBridge	189:f392fc9709a3	343	/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
AnnaBridge	189:f392fc9709a3	344	* @{
AnnaBridge	189:f392fc9709a3	345	*/
AnnaBridge	189:f392fc9709a3	346	#define LL_LPUART_TXRX_STANDARD 0x00000000U /!< TX/RX pins are used as defined in standard pinout /
AnnaBridge	189:f392fc9709a3	347	#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /!< TX and RX pins functions are swapped. /
AnnaBridge	189:f392fc9709a3	348	/**
AnnaBridge	189:f392fc9709a3	349	* @}
AnnaBridge	189:f392fc9709a3	350	*/
AnnaBridge	189:f392fc9709a3	351
AnnaBridge	189:f392fc9709a3	352	/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
AnnaBridge	189:f392fc9709a3	353	* @{
AnnaBridge	189:f392fc9709a3	354	*/
AnnaBridge	189:f392fc9709a3	355	#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /!< RX pin signal works using the standard logic levels /
AnnaBridge	189:f392fc9709a3	356	#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /!< RX pin signal values are inverted. /
AnnaBridge	189:f392fc9709a3	357	/**
AnnaBridge	189:f392fc9709a3	358	* @}
AnnaBridge	189:f392fc9709a3	359	*/
AnnaBridge	189:f392fc9709a3	360
AnnaBridge	189:f392fc9709a3	361	/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
AnnaBridge	189:f392fc9709a3	362	* @{
AnnaBridge	189:f392fc9709a3	363	*/
AnnaBridge	189:f392fc9709a3	364	#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /!< TX pin signal works using the standard logic levels /
AnnaBridge	189:f392fc9709a3	365	#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /!< TX pin signal values are inverted. /
AnnaBridge	189:f392fc9709a3	366	/**
AnnaBridge	189:f392fc9709a3	367	* @}
AnnaBridge	189:f392fc9709a3	368	*/
AnnaBridge	189:f392fc9709a3	369
AnnaBridge	189:f392fc9709a3	370	/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
AnnaBridge	189:f392fc9709a3	371	* @{
AnnaBridge	189:f392fc9709a3	372	*/
AnnaBridge	189:f392fc9709a3	373	#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) /
AnnaBridge	189:f392fc9709a3	374	#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. /
AnnaBridge	189:f392fc9709a3	375	/**
AnnaBridge	189:f392fc9709a3	376	* @}
AnnaBridge	189:f392fc9709a3	377	*/
AnnaBridge	189:f392fc9709a3	378
AnnaBridge	189:f392fc9709a3	379	/** @defgroup LPUART_LL_EC_BITORDER Bit Order
AnnaBridge	189:f392fc9709a3	380	* @{
AnnaBridge	189:f392fc9709a3	381	*/
AnnaBridge	189:f392fc9709a3	382	#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /!< data is transmitted/received with data bit 0 first, following the start bit /
AnnaBridge	189:f392fc9709a3	383	#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /!< data is transmitted/received with the MSB first, following the start bit /
AnnaBridge	189:f392fc9709a3	384	/**
AnnaBridge	189:f392fc9709a3	385	* @}
AnnaBridge	189:f392fc9709a3	386	*/
AnnaBridge	189:f392fc9709a3	387
AnnaBridge	189:f392fc9709a3	388	/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
AnnaBridge	189:f392fc9709a3	389	* @{
AnnaBridge	189:f392fc9709a3	390	*/
AnnaBridge	189:f392fc9709a3	391	#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /!< 4-bit address detection method selected /
AnnaBridge	189:f392fc9709a3	392	#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /!< 7-bit address detection (in 8-bit data mode) method selected /
AnnaBridge	189:f392fc9709a3	393	/**
AnnaBridge	189:f392fc9709a3	394	* @}
AnnaBridge	189:f392fc9709a3	395	*/
AnnaBridge	189:f392fc9709a3	396
AnnaBridge	189:f392fc9709a3	397	/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
AnnaBridge	189:f392fc9709a3	398	* @{
AnnaBridge	189:f392fc9709a3	399	*/
AnnaBridge	189:f392fc9709a3	400	#define LL_LPUART_HWCONTROL_NONE 0x00000000U /!< CTS and RTS hardware flow control disabled /
AnnaBridge	189:f392fc9709a3	401	#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /!< RTS output enabled, data is only requested when there is space in the receive buffer /
AnnaBridge	189:f392fc9709a3	402	#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) /
AnnaBridge	189:f392fc9709a3	403	#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE \| USART_CR3_CTSE) /!< CTS and RTS hardware flow control enabled /
AnnaBridge	189:f392fc9709a3	404	/**
AnnaBridge	189:f392fc9709a3	405	* @}
AnnaBridge	189:f392fc9709a3	406	*/
AnnaBridge	189:f392fc9709a3	407
AnnaBridge	189:f392fc9709a3	408	/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
AnnaBridge	189:f392fc9709a3	409	* @{
AnnaBridge	189:f392fc9709a3	410	*/
AnnaBridge	189:f392fc9709a3	411	#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /!< Wake up active on address match /
AnnaBridge	189:f392fc9709a3	412	#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /!< Wake up active on Start bit detection /
AnnaBridge	189:f392fc9709a3	413	#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 \| USART_CR3_WUS_1) /!< Wake up active on RXNE /
AnnaBridge	189:f392fc9709a3	414	/**
AnnaBridge	189:f392fc9709a3	415	* @}
AnnaBridge	189:f392fc9709a3	416	*/
AnnaBridge	189:f392fc9709a3	417
AnnaBridge	189:f392fc9709a3	418	/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
AnnaBridge	189:f392fc9709a3	419	* @{
AnnaBridge	189:f392fc9709a3	420	*/
AnnaBridge	189:f392fc9709a3	421	#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /!< DE signal is active high /
AnnaBridge	189:f392fc9709a3	422	#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /!< DE signal is active low /
AnnaBridge	189:f392fc9709a3	423	/**
AnnaBridge	189:f392fc9709a3	424	* @}
AnnaBridge	189:f392fc9709a3	425	*/
AnnaBridge	189:f392fc9709a3	426
AnnaBridge	189:f392fc9709a3	427	/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
AnnaBridge	189:f392fc9709a3	428	* @{
AnnaBridge	189:f392fc9709a3	429	*/
AnnaBridge	189:f392fc9709a3	430	#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /!< Get address of data register used for transmission /
AnnaBridge	189:f392fc9709a3	431	#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /!< Get address of data register used for reception /
AnnaBridge	189:f392fc9709a3	432	/**
AnnaBridge	189:f392fc9709a3	433	* @}
AnnaBridge	189:f392fc9709a3	434	*/
AnnaBridge	189:f392fc9709a3	435
AnnaBridge	189:f392fc9709a3	436	/**
AnnaBridge	189:f392fc9709a3	437	* @}
AnnaBridge	189:f392fc9709a3	438	*/
AnnaBridge	189:f392fc9709a3	439
AnnaBridge	189:f392fc9709a3	440	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	441	/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
AnnaBridge	189:f392fc9709a3	442	* @{
AnnaBridge	189:f392fc9709a3	443	*/
AnnaBridge	189:f392fc9709a3	444
AnnaBridge	189:f392fc9709a3	445	/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	189:f392fc9709a3	446	* @{
AnnaBridge	189:f392fc9709a3	447	*/
AnnaBridge	189:f392fc9709a3	448
AnnaBridge	189:f392fc9709a3	449	/**
AnnaBridge	189:f392fc9709a3	450	* @brief Write a value in LPUART register
AnnaBridge	189:f392fc9709a3	451	* @param __INSTANCE__ LPUART Instance
AnnaBridge	189:f392fc9709a3	452	* @param __REG__ Register to be written
AnnaBridge	189:f392fc9709a3	453	* @param __VALUE__ Value to be written in the register
AnnaBridge	189:f392fc9709a3	454	* @retval None
AnnaBridge	189:f392fc9709a3	455	*/
AnnaBridge	189:f392fc9709a3	456	#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	189:f392fc9709a3	457
AnnaBridge	189:f392fc9709a3	458	/**
AnnaBridge	189:f392fc9709a3	459	* @brief Read a value in LPUART register
AnnaBridge	189:f392fc9709a3	460	* @param __INSTANCE__ LPUART Instance
AnnaBridge	189:f392fc9709a3	461	* @param __REG__ Register to be read
AnnaBridge	189:f392fc9709a3	462	* @retval Register value
AnnaBridge	189:f392fc9709a3	463	*/
AnnaBridge	189:f392fc9709a3	464	#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	189:f392fc9709a3	465	/**
AnnaBridge	189:f392fc9709a3	466	* @}
AnnaBridge	189:f392fc9709a3	467	*/
AnnaBridge	189:f392fc9709a3	468
AnnaBridge	189:f392fc9709a3	469	/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
AnnaBridge	189:f392fc9709a3	470	* @{
AnnaBridge	189:f392fc9709a3	471	*/
AnnaBridge	189:f392fc9709a3	472
AnnaBridge	189:f392fc9709a3	473	/**
AnnaBridge	189:f392fc9709a3	474	* @brief Compute LPUARTDIV value according to Peripheral Clock and
AnnaBridge	189:f392fc9709a3	475	* expected Baud Rate (20-bit value of LPUARTDIV is returned)
AnnaBridge	189:f392fc9709a3	476	* @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
AnnaBridge	189:f392fc9709a3	477	@if USART_PRESC_PRESCALER
AnnaBridge	189:f392fc9709a3	478	* @param __PRESCALER__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	479	* @arg @ref LL_LPUART_PRESCALER_DIV1
AnnaBridge	189:f392fc9709a3	480	* @arg @ref LL_LPUART_PRESCALER_DIV2
AnnaBridge	189:f392fc9709a3	481	* @arg @ref LL_LPUART_PRESCALER_DIV4
AnnaBridge	189:f392fc9709a3	482	* @arg @ref LL_LPUART_PRESCALER_DIV6
AnnaBridge	189:f392fc9709a3	483	* @arg @ref LL_LPUART_PRESCALER_DIV8
AnnaBridge	189:f392fc9709a3	484	* @arg @ref LL_LPUART_PRESCALER_DIV10
AnnaBridge	189:f392fc9709a3	485	* @arg @ref LL_LPUART_PRESCALER_DIV12
AnnaBridge	189:f392fc9709a3	486	* @arg @ref LL_LPUART_PRESCALER_DIV16
AnnaBridge	189:f392fc9709a3	487	* @arg @ref LL_LPUART_PRESCALER_DIV32
AnnaBridge	189:f392fc9709a3	488	* @arg @ref LL_LPUART_PRESCALER_DIV64
AnnaBridge	189:f392fc9709a3	489	* @arg @ref LL_LPUART_PRESCALER_DIV128
AnnaBridge	189:f392fc9709a3	490	* @arg @ref LL_LPUART_PRESCALER_DIV256
AnnaBridge	189:f392fc9709a3	491	* @param __PRESCALER__ Prescaler value
AnnaBridge	189:f392fc9709a3	492	@endif
AnnaBridge	189:f392fc9709a3	493	* @param __BAUDRATE__ Baud Rate value to achieve
AnnaBridge	189:f392fc9709a3	494	* @retval LPUARTDIV value to be used for BRR register filling
AnnaBridge	189:f392fc9709a3	495	*/
AnnaBridge	189:f392fc9709a3	496	#if defined(USART_PRESC_PRESCALER)
AnnaBridge	189:f392fc9709a3	497	#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(__PRESCALER__)]))*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)
AnnaBridge	189:f392fc9709a3	498	#else
AnnaBridge	189:f392fc9709a3	499	#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)
AnnaBridge	189:f392fc9709a3	500	#endif
AnnaBridge	189:f392fc9709a3	501
AnnaBridge	189:f392fc9709a3	502	/**
AnnaBridge	189:f392fc9709a3	503	* @}
AnnaBridge	189:f392fc9709a3	504	*/
AnnaBridge	189:f392fc9709a3	505
AnnaBridge	189:f392fc9709a3	506	/**
AnnaBridge	189:f392fc9709a3	507	* @}
AnnaBridge	189:f392fc9709a3	508	*/
AnnaBridge	189:f392fc9709a3	509
AnnaBridge	189:f392fc9709a3	510	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	511	/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
AnnaBridge	189:f392fc9709a3	512	* @{
AnnaBridge	189:f392fc9709a3	513	*/
AnnaBridge	189:f392fc9709a3	514
AnnaBridge	189:f392fc9709a3	515	/** @defgroup LPUART_LL_EF_Configuration Configuration functions
AnnaBridge	189:f392fc9709a3	516	* @{
AnnaBridge	189:f392fc9709a3	517	*/
AnnaBridge	189:f392fc9709a3	518
AnnaBridge	189:f392fc9709a3	519	/**
AnnaBridge	189:f392fc9709a3	520	* @brief LPUART Enable
AnnaBridge	189:f392fc9709a3	521	* @rmtoll CR1 UE LL_LPUART_Enable
AnnaBridge	189:f392fc9709a3	522	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	523	* @retval None
AnnaBridge	189:f392fc9709a3	524	*/
AnnaBridge	189:f392fc9709a3	525	__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	526	{
AnnaBridge	189:f392fc9709a3	527	SET_BIT(LPUARTx->CR1, USART_CR1_UE);
AnnaBridge	189:f392fc9709a3	528	}
AnnaBridge	189:f392fc9709a3	529
AnnaBridge	189:f392fc9709a3	530	/**
AnnaBridge	189:f392fc9709a3	531	* @brief LPUART Disable
AnnaBridge	189:f392fc9709a3	532	* @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
AnnaBridge	189:f392fc9709a3	533	* and current operations are discarded. The configuration of the LPUART is kept, but all the status
AnnaBridge	189:f392fc9709a3	534	* flags, in the LPUARTx_ISR are set to their default values.
AnnaBridge	189:f392fc9709a3	535	* @note In order to go into low-power mode without generating errors on the line,
AnnaBridge	189:f392fc9709a3	536	* the TE bit must be reset before and the software must wait
AnnaBridge	189:f392fc9709a3	537	* for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
AnnaBridge	189:f392fc9709a3	538	* The DMA requests are also reset when UE = 0 so the DMA channel must
AnnaBridge	189:f392fc9709a3	539	* be disabled before resetting the UE bit.
AnnaBridge	189:f392fc9709a3	540	* @rmtoll CR1 UE LL_LPUART_Disable
AnnaBridge	189:f392fc9709a3	541	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	542	* @retval None
AnnaBridge	189:f392fc9709a3	543	*/
AnnaBridge	189:f392fc9709a3	544	__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	545	{
AnnaBridge	189:f392fc9709a3	546	CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
AnnaBridge	189:f392fc9709a3	547	}
AnnaBridge	189:f392fc9709a3	548
AnnaBridge	189:f392fc9709a3	549	/**
AnnaBridge	189:f392fc9709a3	550	* @brief Indicate if LPUART is enabled
AnnaBridge	189:f392fc9709a3	551	* @rmtoll CR1 UE LL_LPUART_IsEnabled
AnnaBridge	189:f392fc9709a3	552	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	553	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	554	*/
AnnaBridge	189:f392fc9709a3	555	__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	556	{
AnnaBridge	189:f392fc9709a3	557	return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
AnnaBridge	189:f392fc9709a3	558	}
AnnaBridge	189:f392fc9709a3	559
AnnaBridge	189:f392fc9709a3	560	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	561	/**
AnnaBridge	189:f392fc9709a3	562	* @brief FIFO Mode Enable
AnnaBridge	189:f392fc9709a3	563	* @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
AnnaBridge	189:f392fc9709a3	564	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	565	* @retval None
AnnaBridge	189:f392fc9709a3	566	*/
AnnaBridge	189:f392fc9709a3	567	__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	568	{
AnnaBridge	189:f392fc9709a3	569	SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
AnnaBridge	189:f392fc9709a3	570	}
AnnaBridge	189:f392fc9709a3	571
AnnaBridge	189:f392fc9709a3	572	/**
AnnaBridge	189:f392fc9709a3	573	* @brief FIFO Mode Disable
AnnaBridge	189:f392fc9709a3	574	* @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
AnnaBridge	189:f392fc9709a3	575	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	576	* @retval None
AnnaBridge	189:f392fc9709a3	577	*/
AnnaBridge	189:f392fc9709a3	578	__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	579	{
AnnaBridge	189:f392fc9709a3	580	CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
AnnaBridge	189:f392fc9709a3	581	}
AnnaBridge	189:f392fc9709a3	582
AnnaBridge	189:f392fc9709a3	583	/**
AnnaBridge	189:f392fc9709a3	584	* @brief Indicate if FIFO Mode is enabled
AnnaBridge	189:f392fc9709a3	585	* @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
AnnaBridge	189:f392fc9709a3	586	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	587	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	588	*/
AnnaBridge	189:f392fc9709a3	589	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	590	{
AnnaBridge	189:f392fc9709a3	591	return (READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN));
AnnaBridge	189:f392fc9709a3	592	}
AnnaBridge	189:f392fc9709a3	593
AnnaBridge	189:f392fc9709a3	594	/**
AnnaBridge	189:f392fc9709a3	595	* @brief Configure TX FIFO Threshold
AnnaBridge	189:f392fc9709a3	596	* @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
AnnaBridge	189:f392fc9709a3	597	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	598	* @param Threshold This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	599	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
AnnaBridge	189:f392fc9709a3	600	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
AnnaBridge	189:f392fc9709a3	601	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
AnnaBridge	189:f392fc9709a3	602	* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
AnnaBridge	189:f392fc9709a3	603	* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
AnnaBridge	189:f392fc9709a3	604	* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
AnnaBridge	189:f392fc9709a3	605	* @retval None
AnnaBridge	189:f392fc9709a3	606	*/
AnnaBridge	189:f392fc9709a3	607	__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
AnnaBridge	189:f392fc9709a3	608	{
AnnaBridge	189:f392fc9709a3	609	MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
AnnaBridge	189:f392fc9709a3	610	}
AnnaBridge	189:f392fc9709a3	611
AnnaBridge	189:f392fc9709a3	612	/**
AnnaBridge	189:f392fc9709a3	613	* @brief Return TX FIFO Threshold Configuration
AnnaBridge	189:f392fc9709a3	614	* @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
AnnaBridge	189:f392fc9709a3	615	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	616	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	617	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
AnnaBridge	189:f392fc9709a3	618	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
AnnaBridge	189:f392fc9709a3	619	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
AnnaBridge	189:f392fc9709a3	620	* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
AnnaBridge	189:f392fc9709a3	621	* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
AnnaBridge	189:f392fc9709a3	622	* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
AnnaBridge	189:f392fc9709a3	623	*/
AnnaBridge	189:f392fc9709a3	624	__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	625	{
AnnaBridge	189:f392fc9709a3	626	return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
AnnaBridge	189:f392fc9709a3	627	}
AnnaBridge	189:f392fc9709a3	628
AnnaBridge	189:f392fc9709a3	629	/**
AnnaBridge	189:f392fc9709a3	630	* @brief Configure RX FIFO Threshold
AnnaBridge	189:f392fc9709a3	631	* @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
AnnaBridge	189:f392fc9709a3	632	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	633	* @param Threshold This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	634	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
AnnaBridge	189:f392fc9709a3	635	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
AnnaBridge	189:f392fc9709a3	636	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
AnnaBridge	189:f392fc9709a3	637	* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
AnnaBridge	189:f392fc9709a3	638	* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
AnnaBridge	189:f392fc9709a3	639	* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
AnnaBridge	189:f392fc9709a3	640	* @retval None
AnnaBridge	189:f392fc9709a3	641	*/
AnnaBridge	189:f392fc9709a3	642	__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
AnnaBridge	189:f392fc9709a3	643	{
AnnaBridge	189:f392fc9709a3	644	MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
AnnaBridge	189:f392fc9709a3	645	}
AnnaBridge	189:f392fc9709a3	646
AnnaBridge	189:f392fc9709a3	647	/**
AnnaBridge	189:f392fc9709a3	648	* @brief Return RX FIFO Threshold Configuration
AnnaBridge	189:f392fc9709a3	649	* @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
AnnaBridge	189:f392fc9709a3	650	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	651	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	652	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
AnnaBridge	189:f392fc9709a3	653	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
AnnaBridge	189:f392fc9709a3	654	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
AnnaBridge	189:f392fc9709a3	655	* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
AnnaBridge	189:f392fc9709a3	656	* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
AnnaBridge	189:f392fc9709a3	657	* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
AnnaBridge	189:f392fc9709a3	658	*/
AnnaBridge	189:f392fc9709a3	659	__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	660	{
AnnaBridge	189:f392fc9709a3	661	return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
AnnaBridge	189:f392fc9709a3	662	}
AnnaBridge	189:f392fc9709a3	663
AnnaBridge	189:f392fc9709a3	664	/**
AnnaBridge	189:f392fc9709a3	665	* @brief Configure TX and RX FIFOs Threshold
AnnaBridge	189:f392fc9709a3	666	* @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
AnnaBridge	189:f392fc9709a3	667	* CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
AnnaBridge	189:f392fc9709a3	668	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	669	* @param TXThreshold This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	670	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
AnnaBridge	189:f392fc9709a3	671	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
AnnaBridge	189:f392fc9709a3	672	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
AnnaBridge	189:f392fc9709a3	673	* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
AnnaBridge	189:f392fc9709a3	674	* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
AnnaBridge	189:f392fc9709a3	675	* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
AnnaBridge	189:f392fc9709a3	676	* @param RXThreshold This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	677	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
AnnaBridge	189:f392fc9709a3	678	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
AnnaBridge	189:f392fc9709a3	679	* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
AnnaBridge	189:f392fc9709a3	680	* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
AnnaBridge	189:f392fc9709a3	681	* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
AnnaBridge	189:f392fc9709a3	682	* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
AnnaBridge	189:f392fc9709a3	683	* @retval None
AnnaBridge	189:f392fc9709a3	684	*/
AnnaBridge	189:f392fc9709a3	685	__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
AnnaBridge	189:f392fc9709a3	686	{
AnnaBridge	189:f392fc9709a3	687	MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG \| USART_CR3_RXFTCFG, TXThreshold << USART_CR3_TXFTCFG_Pos \| RXThreshold << USART_CR3_RXFTCFG_Pos);
AnnaBridge	189:f392fc9709a3	688	}
AnnaBridge	189:f392fc9709a3	689	#endif
AnnaBridge	189:f392fc9709a3	690
AnnaBridge	189:f392fc9709a3	691	/**
AnnaBridge	189:f392fc9709a3	692	* @brief LPUART enabled in STOP Mode
AnnaBridge	189:f392fc9709a3	693	* @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
AnnaBridge	189:f392fc9709a3	694	* LPUART clock selection is HSI or LSE in RCC.
AnnaBridge	189:f392fc9709a3	695	* @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
AnnaBridge	189:f392fc9709a3	696	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	697	* @retval None
AnnaBridge	189:f392fc9709a3	698	*/
AnnaBridge	189:f392fc9709a3	699	__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	700	{
AnnaBridge	189:f392fc9709a3	701	SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
AnnaBridge	189:f392fc9709a3	702	}
AnnaBridge	189:f392fc9709a3	703
AnnaBridge	189:f392fc9709a3	704	/**
AnnaBridge	189:f392fc9709a3	705	* @brief LPUART disabled in STOP Mode
AnnaBridge	189:f392fc9709a3	706	* @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
AnnaBridge	189:f392fc9709a3	707	* @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
AnnaBridge	189:f392fc9709a3	708	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	709	* @retval None
AnnaBridge	189:f392fc9709a3	710	*/
AnnaBridge	189:f392fc9709a3	711	__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	712	{
AnnaBridge	189:f392fc9709a3	713	CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
AnnaBridge	189:f392fc9709a3	714	}
AnnaBridge	189:f392fc9709a3	715
AnnaBridge	189:f392fc9709a3	716	/**
AnnaBridge	189:f392fc9709a3	717	* @brief Indicate if LPUART is enabled in STOP Mode
AnnaBridge	189:f392fc9709a3	718	* (able to wake up MCU from Stop mode or not)
AnnaBridge	189:f392fc9709a3	719	* @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
AnnaBridge	189:f392fc9709a3	720	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	721	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	722	*/
AnnaBridge	189:f392fc9709a3	723	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	724	{
AnnaBridge	189:f392fc9709a3	725	return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
AnnaBridge	189:f392fc9709a3	726	}
AnnaBridge	189:f392fc9709a3	727
AnnaBridge	189:f392fc9709a3	728	/**
AnnaBridge	189:f392fc9709a3	729	* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
AnnaBridge	189:f392fc9709a3	730	* @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
AnnaBridge	189:f392fc9709a3	731	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	732	* @retval None
AnnaBridge	189:f392fc9709a3	733	*/
AnnaBridge	189:f392fc9709a3	734	__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	735	{
AnnaBridge	189:f392fc9709a3	736	SET_BIT(LPUARTx->CR1, USART_CR1_RE);
AnnaBridge	189:f392fc9709a3	737	}
AnnaBridge	189:f392fc9709a3	738
AnnaBridge	189:f392fc9709a3	739	/**
AnnaBridge	189:f392fc9709a3	740	* @brief Receiver Disable
AnnaBridge	189:f392fc9709a3	741	* @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
AnnaBridge	189:f392fc9709a3	742	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	743	* @retval None
AnnaBridge	189:f392fc9709a3	744	*/
AnnaBridge	189:f392fc9709a3	745	__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	746	{
AnnaBridge	189:f392fc9709a3	747	CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
AnnaBridge	189:f392fc9709a3	748	}
AnnaBridge	189:f392fc9709a3	749
AnnaBridge	189:f392fc9709a3	750	/**
AnnaBridge	189:f392fc9709a3	751	* @brief Transmitter Enable
AnnaBridge	189:f392fc9709a3	752	* @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
AnnaBridge	189:f392fc9709a3	753	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	754	* @retval None
AnnaBridge	189:f392fc9709a3	755	*/
AnnaBridge	189:f392fc9709a3	756	__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	757	{
AnnaBridge	189:f392fc9709a3	758	SET_BIT(LPUARTx->CR1, USART_CR1_TE);
AnnaBridge	189:f392fc9709a3	759	}
AnnaBridge	189:f392fc9709a3	760
AnnaBridge	189:f392fc9709a3	761	/**
AnnaBridge	189:f392fc9709a3	762	* @brief Transmitter Disable
AnnaBridge	189:f392fc9709a3	763	* @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
AnnaBridge	189:f392fc9709a3	764	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	765	* @retval None
AnnaBridge	189:f392fc9709a3	766	*/
AnnaBridge	189:f392fc9709a3	767	__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	768	{
AnnaBridge	189:f392fc9709a3	769	CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
AnnaBridge	189:f392fc9709a3	770	}
AnnaBridge	189:f392fc9709a3	771
AnnaBridge	189:f392fc9709a3	772	/**
AnnaBridge	189:f392fc9709a3	773	* @brief Configure simultaneously enabled/disabled states
AnnaBridge	189:f392fc9709a3	774	* of Transmitter and Receiver
AnnaBridge	189:f392fc9709a3	775	* @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
AnnaBridge	189:f392fc9709a3	776	* CR1 TE LL_LPUART_SetTransferDirection
AnnaBridge	189:f392fc9709a3	777	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	778	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	779	* @arg @ref LL_LPUART_DIRECTION_NONE
AnnaBridge	189:f392fc9709a3	780	* @arg @ref LL_LPUART_DIRECTION_RX
AnnaBridge	189:f392fc9709a3	781	* @arg @ref LL_LPUART_DIRECTION_TX
AnnaBridge	189:f392fc9709a3	782	* @arg @ref LL_LPUART_DIRECTION_TX_RX
AnnaBridge	189:f392fc9709a3	783	* @retval None
AnnaBridge	189:f392fc9709a3	784	*/
AnnaBridge	189:f392fc9709a3	785	__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
AnnaBridge	189:f392fc9709a3	786	{
AnnaBridge	189:f392fc9709a3	787	MODIFY_REG(LPUARTx->CR1, USART_CR1_RE \| USART_CR1_TE, TransferDirection);
AnnaBridge	189:f392fc9709a3	788	}
AnnaBridge	189:f392fc9709a3	789
AnnaBridge	189:f392fc9709a3	790	/**
AnnaBridge	189:f392fc9709a3	791	* @brief Return enabled/disabled states of Transmitter and Receiver
AnnaBridge	189:f392fc9709a3	792	* @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
AnnaBridge	189:f392fc9709a3	793	* CR1 TE LL_LPUART_GetTransferDirection
AnnaBridge	189:f392fc9709a3	794	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	795	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	796	* @arg @ref LL_LPUART_DIRECTION_NONE
AnnaBridge	189:f392fc9709a3	797	* @arg @ref LL_LPUART_DIRECTION_RX
AnnaBridge	189:f392fc9709a3	798	* @arg @ref LL_LPUART_DIRECTION_TX
AnnaBridge	189:f392fc9709a3	799	* @arg @ref LL_LPUART_DIRECTION_TX_RX
AnnaBridge	189:f392fc9709a3	800	*/
AnnaBridge	189:f392fc9709a3	801	__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	802	{
AnnaBridge	189:f392fc9709a3	803	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE \| USART_CR1_TE));
AnnaBridge	189:f392fc9709a3	804	}
AnnaBridge	189:f392fc9709a3	805
AnnaBridge	189:f392fc9709a3	806	/**
AnnaBridge	189:f392fc9709a3	807	* @brief Configure Parity (enabled/disabled and parity mode if enabled)
AnnaBridge	189:f392fc9709a3	808	* @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
AnnaBridge	189:f392fc9709a3	809	* When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
AnnaBridge	189:f392fc9709a3	810	* (depending on data width) and parity is checked on the received data.
AnnaBridge	189:f392fc9709a3	811	* @rmtoll CR1 PS LL_LPUART_SetParity\n
AnnaBridge	189:f392fc9709a3	812	* CR1 PCE LL_LPUART_SetParity
AnnaBridge	189:f392fc9709a3	813	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	814	* @param Parity This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	815	* @arg @ref LL_LPUART_PARITY_NONE
AnnaBridge	189:f392fc9709a3	816	* @arg @ref LL_LPUART_PARITY_EVEN
AnnaBridge	189:f392fc9709a3	817	* @arg @ref LL_LPUART_PARITY_ODD
AnnaBridge	189:f392fc9709a3	818	* @retval None
AnnaBridge	189:f392fc9709a3	819	*/
AnnaBridge	189:f392fc9709a3	820	__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
AnnaBridge	189:f392fc9709a3	821	{
AnnaBridge	189:f392fc9709a3	822	MODIFY_REG(LPUARTx->CR1, USART_CR1_PS \| USART_CR1_PCE, Parity);
AnnaBridge	189:f392fc9709a3	823	}
AnnaBridge	189:f392fc9709a3	824
AnnaBridge	189:f392fc9709a3	825	/**
AnnaBridge	189:f392fc9709a3	826	* @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
AnnaBridge	189:f392fc9709a3	827	* @rmtoll CR1 PS LL_LPUART_GetParity\n
AnnaBridge	189:f392fc9709a3	828	* CR1 PCE LL_LPUART_GetParity
AnnaBridge	189:f392fc9709a3	829	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	830	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	831	* @arg @ref LL_LPUART_PARITY_NONE
AnnaBridge	189:f392fc9709a3	832	* @arg @ref LL_LPUART_PARITY_EVEN
AnnaBridge	189:f392fc9709a3	833	* @arg @ref LL_LPUART_PARITY_ODD
AnnaBridge	189:f392fc9709a3	834	*/
AnnaBridge	189:f392fc9709a3	835	__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	836	{
AnnaBridge	189:f392fc9709a3	837	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS \| USART_CR1_PCE));
AnnaBridge	189:f392fc9709a3	838	}
AnnaBridge	189:f392fc9709a3	839
AnnaBridge	189:f392fc9709a3	840	/**
AnnaBridge	189:f392fc9709a3	841	* @brief Set Receiver Wake Up method from Mute mode.
AnnaBridge	189:f392fc9709a3	842	* @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
AnnaBridge	189:f392fc9709a3	843	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	844	* @param Method This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	845	* @arg @ref LL_LPUART_WAKEUP_IDLELINE
AnnaBridge	189:f392fc9709a3	846	* @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
AnnaBridge	189:f392fc9709a3	847	* @retval None
AnnaBridge	189:f392fc9709a3	848	*/
AnnaBridge	189:f392fc9709a3	849	__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
AnnaBridge	189:f392fc9709a3	850	{
AnnaBridge	189:f392fc9709a3	851	MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
AnnaBridge	189:f392fc9709a3	852	}
AnnaBridge	189:f392fc9709a3	853
AnnaBridge	189:f392fc9709a3	854	/**
AnnaBridge	189:f392fc9709a3	855	* @brief Return Receiver Wake Up method from Mute mode
AnnaBridge	189:f392fc9709a3	856	* @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
AnnaBridge	189:f392fc9709a3	857	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	858	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	859	* @arg @ref LL_LPUART_WAKEUP_IDLELINE
AnnaBridge	189:f392fc9709a3	860	* @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
AnnaBridge	189:f392fc9709a3	861	*/
AnnaBridge	189:f392fc9709a3	862	__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	863	{
AnnaBridge	189:f392fc9709a3	864	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
AnnaBridge	189:f392fc9709a3	865	}
AnnaBridge	189:f392fc9709a3	866
AnnaBridge	189:f392fc9709a3	867	/**
AnnaBridge	189:f392fc9709a3	868	* @brief Set Word length (nb of data bits, excluding start and stop bits)
AnnaBridge	189:f392fc9709a3	869	* @rmtoll CR1 M LL_LPUART_SetDataWidth
AnnaBridge	189:f392fc9709a3	870	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	871	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	872	* @arg @ref LL_LPUART_DATAWIDTH_7B
AnnaBridge	189:f392fc9709a3	873	* @arg @ref LL_LPUART_DATAWIDTH_8B
AnnaBridge	189:f392fc9709a3	874	* @arg @ref LL_LPUART_DATAWIDTH_9B
AnnaBridge	189:f392fc9709a3	875	* @retval None
AnnaBridge	189:f392fc9709a3	876	*/
AnnaBridge	189:f392fc9709a3	877	__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
AnnaBridge	189:f392fc9709a3	878	{
AnnaBridge	189:f392fc9709a3	879	MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
AnnaBridge	189:f392fc9709a3	880	}
AnnaBridge	189:f392fc9709a3	881
AnnaBridge	189:f392fc9709a3	882	/**
AnnaBridge	189:f392fc9709a3	883	* @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
AnnaBridge	189:f392fc9709a3	884	* @rmtoll CR1 M LL_LPUART_GetDataWidth
AnnaBridge	189:f392fc9709a3	885	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	886	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	887	* @arg @ref LL_LPUART_DATAWIDTH_7B
AnnaBridge	189:f392fc9709a3	888	* @arg @ref LL_LPUART_DATAWIDTH_8B
AnnaBridge	189:f392fc9709a3	889	* @arg @ref LL_LPUART_DATAWIDTH_9B
AnnaBridge	189:f392fc9709a3	890	*/
AnnaBridge	189:f392fc9709a3	891	__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	892	{
AnnaBridge	189:f392fc9709a3	893	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
AnnaBridge	189:f392fc9709a3	894	}
AnnaBridge	189:f392fc9709a3	895
AnnaBridge	189:f392fc9709a3	896	/**
AnnaBridge	189:f392fc9709a3	897	* @brief Allow switch between Mute Mode and Active mode
AnnaBridge	189:f392fc9709a3	898	* @rmtoll CR1 MME LL_LPUART_EnableMuteMode
AnnaBridge	189:f392fc9709a3	899	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	900	* @retval None
AnnaBridge	189:f392fc9709a3	901	*/
AnnaBridge	189:f392fc9709a3	902	__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	903	{
AnnaBridge	189:f392fc9709a3	904	SET_BIT(LPUARTx->CR1, USART_CR1_MME);
AnnaBridge	189:f392fc9709a3	905	}
AnnaBridge	189:f392fc9709a3	906
AnnaBridge	189:f392fc9709a3	907	/**
AnnaBridge	189:f392fc9709a3	908	* @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
AnnaBridge	189:f392fc9709a3	909	* @rmtoll CR1 MME LL_LPUART_DisableMuteMode
AnnaBridge	189:f392fc9709a3	910	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	911	* @retval None
AnnaBridge	189:f392fc9709a3	912	*/
AnnaBridge	189:f392fc9709a3	913	__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	914	{
AnnaBridge	189:f392fc9709a3	915	CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
AnnaBridge	189:f392fc9709a3	916	}
AnnaBridge	189:f392fc9709a3	917
AnnaBridge	189:f392fc9709a3	918	/**
AnnaBridge	189:f392fc9709a3	919	* @brief Indicate if switch between Mute Mode and Active mode is allowed
AnnaBridge	189:f392fc9709a3	920	* @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
AnnaBridge	189:f392fc9709a3	921	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	922	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	923	*/
AnnaBridge	189:f392fc9709a3	924	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	925	{
AnnaBridge	189:f392fc9709a3	926	return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
AnnaBridge	189:f392fc9709a3	927	}
AnnaBridge	189:f392fc9709a3	928
AnnaBridge	189:f392fc9709a3	929	#if defined(USART_PRESC_PRESCALER)
AnnaBridge	189:f392fc9709a3	930	/**
AnnaBridge	189:f392fc9709a3	931	* @brief Configure Clock source prescaler for baudrate generator and oversampling
AnnaBridge	189:f392fc9709a3	932	* @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
AnnaBridge	189:f392fc9709a3	933	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	934	* @param PrescalerValue This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	935	* @arg @ref LL_LPUART_PRESCALER_DIV1
AnnaBridge	189:f392fc9709a3	936	* @arg @ref LL_LPUART_PRESCALER_DIV2
AnnaBridge	189:f392fc9709a3	937	* @arg @ref LL_LPUART_PRESCALER_DIV4
AnnaBridge	189:f392fc9709a3	938	* @arg @ref LL_LPUART_PRESCALER_DIV6
AnnaBridge	189:f392fc9709a3	939	* @arg @ref LL_LPUART_PRESCALER_DIV8
AnnaBridge	189:f392fc9709a3	940	* @arg @ref LL_LPUART_PRESCALER_DIV10
AnnaBridge	189:f392fc9709a3	941	* @arg @ref LL_LPUART_PRESCALER_DIV12
AnnaBridge	189:f392fc9709a3	942	* @arg @ref LL_LPUART_PRESCALER_DIV16
AnnaBridge	189:f392fc9709a3	943	* @arg @ref LL_LPUART_PRESCALER_DIV32
AnnaBridge	189:f392fc9709a3	944	* @arg @ref LL_LPUART_PRESCALER_DIV64
AnnaBridge	189:f392fc9709a3	945	* @arg @ref LL_LPUART_PRESCALER_DIV128
AnnaBridge	189:f392fc9709a3	946	* @arg @ref LL_LPUART_PRESCALER_DIV256
AnnaBridge	189:f392fc9709a3	947	* @retval None
AnnaBridge	189:f392fc9709a3	948	*/
AnnaBridge	189:f392fc9709a3	949	__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
AnnaBridge	189:f392fc9709a3	950	{
AnnaBridge	189:f392fc9709a3	951	MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, PrescalerValue);
AnnaBridge	189:f392fc9709a3	952	}
AnnaBridge	189:f392fc9709a3	953
AnnaBridge	189:f392fc9709a3	954	/**
AnnaBridge	189:f392fc9709a3	955	* @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
AnnaBridge	189:f392fc9709a3	956	* @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
AnnaBridge	189:f392fc9709a3	957	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	958	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	959	* @arg @ref LL_LPUART_PRESCALER_DIV1
AnnaBridge	189:f392fc9709a3	960	* @arg @ref LL_LPUART_PRESCALER_DIV2
AnnaBridge	189:f392fc9709a3	961	* @arg @ref LL_LPUART_PRESCALER_DIV4
AnnaBridge	189:f392fc9709a3	962	* @arg @ref LL_LPUART_PRESCALER_DIV6
AnnaBridge	189:f392fc9709a3	963	* @arg @ref LL_LPUART_PRESCALER_DIV8
AnnaBridge	189:f392fc9709a3	964	* @arg @ref LL_LPUART_PRESCALER_DIV10
AnnaBridge	189:f392fc9709a3	965	* @arg @ref LL_LPUART_PRESCALER_DIV12
AnnaBridge	189:f392fc9709a3	966	* @arg @ref LL_LPUART_PRESCALER_DIV16
AnnaBridge	189:f392fc9709a3	967	* @arg @ref LL_LPUART_PRESCALER_DIV32
AnnaBridge	189:f392fc9709a3	968	* @arg @ref LL_LPUART_PRESCALER_DIV64
AnnaBridge	189:f392fc9709a3	969	* @arg @ref LL_LPUART_PRESCALER_DIV128
AnnaBridge	189:f392fc9709a3	970	* @arg @ref LL_LPUART_PRESCALER_DIV256
AnnaBridge	189:f392fc9709a3	971	*/
AnnaBridge	189:f392fc9709a3	972	__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	973	{
AnnaBridge	189:f392fc9709a3	974	return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
AnnaBridge	189:f392fc9709a3	975	}
AnnaBridge	189:f392fc9709a3	976	#endif
AnnaBridge	189:f392fc9709a3	977
AnnaBridge	189:f392fc9709a3	978	/**
AnnaBridge	189:f392fc9709a3	979	* @brief Set the length of the stop bits
AnnaBridge	189:f392fc9709a3	980	* @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
AnnaBridge	189:f392fc9709a3	981	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	982	* @param StopBits This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	983	* @arg @ref LL_LPUART_STOPBITS_1
AnnaBridge	189:f392fc9709a3	984	* @arg @ref LL_LPUART_STOPBITS_2
AnnaBridge	189:f392fc9709a3	985	* @retval None
AnnaBridge	189:f392fc9709a3	986	*/
AnnaBridge	189:f392fc9709a3	987	__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
AnnaBridge	189:f392fc9709a3	988	{
AnnaBridge	189:f392fc9709a3	989	MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
AnnaBridge	189:f392fc9709a3	990	}
AnnaBridge	189:f392fc9709a3	991
AnnaBridge	189:f392fc9709a3	992	/**
AnnaBridge	189:f392fc9709a3	993	* @brief Retrieve the length of the stop bits
AnnaBridge	189:f392fc9709a3	994	* @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
AnnaBridge	189:f392fc9709a3	995	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	996	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	997	* @arg @ref LL_LPUART_STOPBITS_1
AnnaBridge	189:f392fc9709a3	998	* @arg @ref LL_LPUART_STOPBITS_2
AnnaBridge	189:f392fc9709a3	999	*/
AnnaBridge	189:f392fc9709a3	1000	__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1001	{
AnnaBridge	189:f392fc9709a3	1002	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
AnnaBridge	189:f392fc9709a3	1003	}
AnnaBridge	189:f392fc9709a3	1004
AnnaBridge	189:f392fc9709a3	1005	/**
AnnaBridge	189:f392fc9709a3	1006	* @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
AnnaBridge	189:f392fc9709a3	1007	* @note Call of this function is equivalent to following function call sequence :
AnnaBridge	189:f392fc9709a3	1008	* - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
AnnaBridge	189:f392fc9709a3	1009	* - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
AnnaBridge	189:f392fc9709a3	1010	* - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
AnnaBridge	189:f392fc9709a3	1011	* @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
AnnaBridge	189:f392fc9709a3	1012	* CR1 PCE LL_LPUART_ConfigCharacter\n
AnnaBridge	189:f392fc9709a3	1013	* CR1 M LL_LPUART_ConfigCharacter\n
AnnaBridge	189:f392fc9709a3	1014	* CR2 STOP LL_LPUART_ConfigCharacter
AnnaBridge	189:f392fc9709a3	1015	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1016	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1017	* @arg @ref LL_LPUART_DATAWIDTH_7B
AnnaBridge	189:f392fc9709a3	1018	* @arg @ref LL_LPUART_DATAWIDTH_8B
AnnaBridge	189:f392fc9709a3	1019	* @arg @ref LL_LPUART_DATAWIDTH_9B
AnnaBridge	189:f392fc9709a3	1020	* @param Parity This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1021	* @arg @ref LL_LPUART_PARITY_NONE
AnnaBridge	189:f392fc9709a3	1022	* @arg @ref LL_LPUART_PARITY_EVEN
AnnaBridge	189:f392fc9709a3	1023	* @arg @ref LL_LPUART_PARITY_ODD
AnnaBridge	189:f392fc9709a3	1024	* @param StopBits This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1025	* @arg @ref LL_LPUART_STOPBITS_1
AnnaBridge	189:f392fc9709a3	1026	* @arg @ref LL_LPUART_STOPBITS_2
AnnaBridge	189:f392fc9709a3	1027	* @retval None
AnnaBridge	189:f392fc9709a3	1028	*/
AnnaBridge	189:f392fc9709a3	1029	__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
AnnaBridge	189:f392fc9709a3	1030	uint32_t StopBits)
AnnaBridge	189:f392fc9709a3	1031	{
AnnaBridge	189:f392fc9709a3	1032	MODIFY_REG(LPUARTx->CR1, USART_CR1_PS \| USART_CR1_PCE \| USART_CR1_M, Parity \| DataWidth);
AnnaBridge	189:f392fc9709a3	1033	MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
AnnaBridge	189:f392fc9709a3	1034	}
AnnaBridge	189:f392fc9709a3	1035
AnnaBridge	189:f392fc9709a3	1036	/**
AnnaBridge	189:f392fc9709a3	1037	* @brief Configure TX/RX pins swapping setting.
AnnaBridge	189:f392fc9709a3	1038	* @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
AnnaBridge	189:f392fc9709a3	1039	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1040	* @param SwapConfig This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1041	* @arg @ref LL_LPUART_TXRX_STANDARD
AnnaBridge	189:f392fc9709a3	1042	* @arg @ref LL_LPUART_TXRX_SWAPPED
AnnaBridge	189:f392fc9709a3	1043	* @retval None
AnnaBridge	189:f392fc9709a3	1044	*/
AnnaBridge	189:f392fc9709a3	1045	__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
AnnaBridge	189:f392fc9709a3	1046	{
AnnaBridge	189:f392fc9709a3	1047	MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
AnnaBridge	189:f392fc9709a3	1048	}
AnnaBridge	189:f392fc9709a3	1049
AnnaBridge	189:f392fc9709a3	1050	/**
AnnaBridge	189:f392fc9709a3	1051	* @brief Retrieve TX/RX pins swapping configuration.
AnnaBridge	189:f392fc9709a3	1052	* @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
AnnaBridge	189:f392fc9709a3	1053	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1054	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1055	* @arg @ref LL_LPUART_TXRX_STANDARD
AnnaBridge	189:f392fc9709a3	1056	* @arg @ref LL_LPUART_TXRX_SWAPPED
AnnaBridge	189:f392fc9709a3	1057	*/
AnnaBridge	189:f392fc9709a3	1058	__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1059	{
AnnaBridge	189:f392fc9709a3	1060	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
AnnaBridge	189:f392fc9709a3	1061	}
AnnaBridge	189:f392fc9709a3	1062
AnnaBridge	189:f392fc9709a3	1063	/**
AnnaBridge	189:f392fc9709a3	1064	* @brief Configure RX pin active level logic
AnnaBridge	189:f392fc9709a3	1065	* @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
AnnaBridge	189:f392fc9709a3	1066	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1067	* @param PinInvMethod This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1068	* @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
AnnaBridge	189:f392fc9709a3	1069	* @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
AnnaBridge	189:f392fc9709a3	1070	* @retval None
AnnaBridge	189:f392fc9709a3	1071	*/
AnnaBridge	189:f392fc9709a3	1072	__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
AnnaBridge	189:f392fc9709a3	1073	{
AnnaBridge	189:f392fc9709a3	1074	MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
AnnaBridge	189:f392fc9709a3	1075	}
AnnaBridge	189:f392fc9709a3	1076
AnnaBridge	189:f392fc9709a3	1077	/**
AnnaBridge	189:f392fc9709a3	1078	* @brief Retrieve RX pin active level logic configuration
AnnaBridge	189:f392fc9709a3	1079	* @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
AnnaBridge	189:f392fc9709a3	1080	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1081	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1082	* @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
AnnaBridge	189:f392fc9709a3	1083	* @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
AnnaBridge	189:f392fc9709a3	1084	*/
AnnaBridge	189:f392fc9709a3	1085	__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1086	{
AnnaBridge	189:f392fc9709a3	1087	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
AnnaBridge	189:f392fc9709a3	1088	}
AnnaBridge	189:f392fc9709a3	1089
AnnaBridge	189:f392fc9709a3	1090	/**
AnnaBridge	189:f392fc9709a3	1091	* @brief Configure TX pin active level logic
AnnaBridge	189:f392fc9709a3	1092	* @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
AnnaBridge	189:f392fc9709a3	1093	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1094	* @param PinInvMethod This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1095	* @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
AnnaBridge	189:f392fc9709a3	1096	* @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
AnnaBridge	189:f392fc9709a3	1097	* @retval None
AnnaBridge	189:f392fc9709a3	1098	*/
AnnaBridge	189:f392fc9709a3	1099	__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
AnnaBridge	189:f392fc9709a3	1100	{
AnnaBridge	189:f392fc9709a3	1101	MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
AnnaBridge	189:f392fc9709a3	1102	}
AnnaBridge	189:f392fc9709a3	1103
AnnaBridge	189:f392fc9709a3	1104	/**
AnnaBridge	189:f392fc9709a3	1105	* @brief Retrieve TX pin active level logic configuration
AnnaBridge	189:f392fc9709a3	1106	* @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
AnnaBridge	189:f392fc9709a3	1107	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1108	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1109	* @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
AnnaBridge	189:f392fc9709a3	1110	* @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
AnnaBridge	189:f392fc9709a3	1111	*/
AnnaBridge	189:f392fc9709a3	1112	__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1113	{
AnnaBridge	189:f392fc9709a3	1114	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
AnnaBridge	189:f392fc9709a3	1115	}
AnnaBridge	189:f392fc9709a3	1116
AnnaBridge	189:f392fc9709a3	1117	/**
AnnaBridge	189:f392fc9709a3	1118	* @brief Configure Binary data logic.
AnnaBridge	189:f392fc9709a3	1119	*
AnnaBridge	189:f392fc9709a3	1120	* @note Allow to define how Logical data from the data register are send/received :
AnnaBridge	189:f392fc9709a3	1121	* either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
AnnaBridge	189:f392fc9709a3	1122	* @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
AnnaBridge	189:f392fc9709a3	1123	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1124	* @param DataLogic This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1125	* @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
AnnaBridge	189:f392fc9709a3	1126	* @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
AnnaBridge	189:f392fc9709a3	1127	* @retval None
AnnaBridge	189:f392fc9709a3	1128	*/
AnnaBridge	189:f392fc9709a3	1129	__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
AnnaBridge	189:f392fc9709a3	1130	{
AnnaBridge	189:f392fc9709a3	1131	MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
AnnaBridge	189:f392fc9709a3	1132	}
AnnaBridge	189:f392fc9709a3	1133
AnnaBridge	189:f392fc9709a3	1134	/**
AnnaBridge	189:f392fc9709a3	1135	* @brief Retrieve Binary data configuration
AnnaBridge	189:f392fc9709a3	1136	* @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
AnnaBridge	189:f392fc9709a3	1137	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1138	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1139	* @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
AnnaBridge	189:f392fc9709a3	1140	* @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
AnnaBridge	189:f392fc9709a3	1141	*/
AnnaBridge	189:f392fc9709a3	1142	__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1143	{
AnnaBridge	189:f392fc9709a3	1144	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
AnnaBridge	189:f392fc9709a3	1145	}
AnnaBridge	189:f392fc9709a3	1146
AnnaBridge	189:f392fc9709a3	1147	/**
AnnaBridge	189:f392fc9709a3	1148	* @brief Configure transfer bit order (either Less or Most Significant Bit First)
AnnaBridge	189:f392fc9709a3	1149	* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
AnnaBridge	189:f392fc9709a3	1150	* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
AnnaBridge	189:f392fc9709a3	1151	* @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
AnnaBridge	189:f392fc9709a3	1152	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1153	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1154	* @arg @ref LL_LPUART_BITORDER_LSBFIRST
AnnaBridge	189:f392fc9709a3	1155	* @arg @ref LL_LPUART_BITORDER_MSBFIRST
AnnaBridge	189:f392fc9709a3	1156	* @retval None
AnnaBridge	189:f392fc9709a3	1157	*/
AnnaBridge	189:f392fc9709a3	1158	__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
AnnaBridge	189:f392fc9709a3	1159	{
AnnaBridge	189:f392fc9709a3	1160	MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
AnnaBridge	189:f392fc9709a3	1161	}
AnnaBridge	189:f392fc9709a3	1162
AnnaBridge	189:f392fc9709a3	1163	/**
AnnaBridge	189:f392fc9709a3	1164	* @brief Return transfer bit order (either Less or Most Significant Bit First)
AnnaBridge	189:f392fc9709a3	1165	* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
AnnaBridge	189:f392fc9709a3	1166	* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
AnnaBridge	189:f392fc9709a3	1167	* @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
AnnaBridge	189:f392fc9709a3	1168	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1169	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1170	* @arg @ref LL_LPUART_BITORDER_LSBFIRST
AnnaBridge	189:f392fc9709a3	1171	* @arg @ref LL_LPUART_BITORDER_MSBFIRST
AnnaBridge	189:f392fc9709a3	1172	*/
AnnaBridge	189:f392fc9709a3	1173	__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1174	{
AnnaBridge	189:f392fc9709a3	1175	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
AnnaBridge	189:f392fc9709a3	1176	}
AnnaBridge	189:f392fc9709a3	1177
AnnaBridge	189:f392fc9709a3	1178	/**
AnnaBridge	189:f392fc9709a3	1179	* @brief Set Address of the LPUART node.
AnnaBridge	189:f392fc9709a3	1180	* @note This is used in multiprocessor communication during Mute mode or Stop mode,
AnnaBridge	189:f392fc9709a3	1181	* for wake up with address mark detection.
AnnaBridge	189:f392fc9709a3	1182	* @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
AnnaBridge	189:f392fc9709a3	1183	* (b7-b4 should be set to 0)
AnnaBridge	189:f392fc9709a3	1184	* 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
AnnaBridge	189:f392fc9709a3	1185	* (This is used in multiprocessor communication during Mute mode or Stop mode,
AnnaBridge	189:f392fc9709a3	1186	* for wake up with 7-bit address mark detection.
AnnaBridge	189:f392fc9709a3	1187	* The MSB of the character sent by the transmitter should be equal to 1.
AnnaBridge	189:f392fc9709a3	1188	* It may also be used for character detection during normal reception,
AnnaBridge	189:f392fc9709a3	1189	* Mute mode inactive (for example, end of block detection in ModBus protocol).
AnnaBridge	189:f392fc9709a3	1190	* In this case, the whole received character (8-bit) is compared to the ADD[7:0]
AnnaBridge	189:f392fc9709a3	1191	* value and CMF flag is set on match)
AnnaBridge	189:f392fc9709a3	1192	* @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
AnnaBridge	189:f392fc9709a3	1193	* CR2 ADDM7 LL_LPUART_ConfigNodeAddress
AnnaBridge	189:f392fc9709a3	1194	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1195	* @param AddressLen This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1196	* @arg @ref LL_LPUART_ADDRESS_DETECT_4B
AnnaBridge	189:f392fc9709a3	1197	* @arg @ref LL_LPUART_ADDRESS_DETECT_7B
AnnaBridge	189:f392fc9709a3	1198	* @param NodeAddress 4 or 7 bit Address of the LPUART node.
AnnaBridge	189:f392fc9709a3	1199	* @retval None
AnnaBridge	189:f392fc9709a3	1200	*/
AnnaBridge	189:f392fc9709a3	1201	__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
AnnaBridge	189:f392fc9709a3	1202	{
AnnaBridge	189:f392fc9709a3	1203	MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD \| USART_CR2_ADDM7,
AnnaBridge	189:f392fc9709a3	1204	(uint32_t)(AddressLen \| (NodeAddress << USART_CR2_ADD_Pos)));
AnnaBridge	189:f392fc9709a3	1205	}
AnnaBridge	189:f392fc9709a3	1206
AnnaBridge	189:f392fc9709a3	1207	/**
AnnaBridge	189:f392fc9709a3	1208	* @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
AnnaBridge	189:f392fc9709a3	1209	* @note If 4-bit Address Detection is selected in ADDM7,
AnnaBridge	189:f392fc9709a3	1210	* only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
AnnaBridge	189:f392fc9709a3	1211	* If 7-bit Address Detection is selected in ADDM7,
AnnaBridge	189:f392fc9709a3	1212	* only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
AnnaBridge	189:f392fc9709a3	1213	* @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
AnnaBridge	189:f392fc9709a3	1214	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1215	* @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
AnnaBridge	189:f392fc9709a3	1216	*/
AnnaBridge	189:f392fc9709a3	1217	__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1218	{
AnnaBridge	189:f392fc9709a3	1219	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
AnnaBridge	189:f392fc9709a3	1220	}
AnnaBridge	189:f392fc9709a3	1221
AnnaBridge	189:f392fc9709a3	1222	/**
AnnaBridge	189:f392fc9709a3	1223	* @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
AnnaBridge	189:f392fc9709a3	1224	* @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
AnnaBridge	189:f392fc9709a3	1225	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1226	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1227	* @arg @ref LL_LPUART_ADDRESS_DETECT_4B
AnnaBridge	189:f392fc9709a3	1228	* @arg @ref LL_LPUART_ADDRESS_DETECT_7B
AnnaBridge	189:f392fc9709a3	1229	*/
AnnaBridge	189:f392fc9709a3	1230	__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1231	{
AnnaBridge	189:f392fc9709a3	1232	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
AnnaBridge	189:f392fc9709a3	1233	}
AnnaBridge	189:f392fc9709a3	1234
AnnaBridge	189:f392fc9709a3	1235	/**
AnnaBridge	189:f392fc9709a3	1236	* @brief Enable RTS HW Flow Control
AnnaBridge	189:f392fc9709a3	1237	* @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
AnnaBridge	189:f392fc9709a3	1238	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1239	* @retval None
AnnaBridge	189:f392fc9709a3	1240	*/
AnnaBridge	189:f392fc9709a3	1241	__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1242	{
AnnaBridge	189:f392fc9709a3	1243	SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
AnnaBridge	189:f392fc9709a3	1244	}
AnnaBridge	189:f392fc9709a3	1245
AnnaBridge	189:f392fc9709a3	1246	/**
AnnaBridge	189:f392fc9709a3	1247	* @brief Disable RTS HW Flow Control
AnnaBridge	189:f392fc9709a3	1248	* @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
AnnaBridge	189:f392fc9709a3	1249	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1250	* @retval None
AnnaBridge	189:f392fc9709a3	1251	*/
AnnaBridge	189:f392fc9709a3	1252	__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1253	{
AnnaBridge	189:f392fc9709a3	1254	CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
AnnaBridge	189:f392fc9709a3	1255	}
AnnaBridge	189:f392fc9709a3	1256
AnnaBridge	189:f392fc9709a3	1257	/**
AnnaBridge	189:f392fc9709a3	1258	* @brief Enable CTS HW Flow Control
AnnaBridge	189:f392fc9709a3	1259	* @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
AnnaBridge	189:f392fc9709a3	1260	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1261	* @retval None
AnnaBridge	189:f392fc9709a3	1262	*/
AnnaBridge	189:f392fc9709a3	1263	__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1264	{
AnnaBridge	189:f392fc9709a3	1265	SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
AnnaBridge	189:f392fc9709a3	1266	}
AnnaBridge	189:f392fc9709a3	1267
AnnaBridge	189:f392fc9709a3	1268	/**
AnnaBridge	189:f392fc9709a3	1269	* @brief Disable CTS HW Flow Control
AnnaBridge	189:f392fc9709a3	1270	* @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
AnnaBridge	189:f392fc9709a3	1271	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1272	* @retval None
AnnaBridge	189:f392fc9709a3	1273	*/
AnnaBridge	189:f392fc9709a3	1274	__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1275	{
AnnaBridge	189:f392fc9709a3	1276	CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
AnnaBridge	189:f392fc9709a3	1277	}
AnnaBridge	189:f392fc9709a3	1278
AnnaBridge	189:f392fc9709a3	1279	/**
AnnaBridge	189:f392fc9709a3	1280	* @brief Configure HW Flow Control mode (both CTS and RTS)
AnnaBridge	189:f392fc9709a3	1281	* @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
AnnaBridge	189:f392fc9709a3	1282	* CR3 CTSE LL_LPUART_SetHWFlowCtrl
AnnaBridge	189:f392fc9709a3	1283	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1284	* @param HardwareFlowControl This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1285	* @arg @ref LL_LPUART_HWCONTROL_NONE
AnnaBridge	189:f392fc9709a3	1286	* @arg @ref LL_LPUART_HWCONTROL_RTS
AnnaBridge	189:f392fc9709a3	1287	* @arg @ref LL_LPUART_HWCONTROL_CTS
AnnaBridge	189:f392fc9709a3	1288	* @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
AnnaBridge	189:f392fc9709a3	1289	* @retval None
AnnaBridge	189:f392fc9709a3	1290	*/
AnnaBridge	189:f392fc9709a3	1291	__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
AnnaBridge	189:f392fc9709a3	1292	{
AnnaBridge	189:f392fc9709a3	1293	MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE \| USART_CR3_CTSE, HardwareFlowControl);
AnnaBridge	189:f392fc9709a3	1294	}
AnnaBridge	189:f392fc9709a3	1295
AnnaBridge	189:f392fc9709a3	1296	/**
AnnaBridge	189:f392fc9709a3	1297	* @brief Return HW Flow Control configuration (both CTS and RTS)
AnnaBridge	189:f392fc9709a3	1298	* @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
AnnaBridge	189:f392fc9709a3	1299	* CR3 CTSE LL_LPUART_GetHWFlowCtrl
AnnaBridge	189:f392fc9709a3	1300	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1301	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1302	* @arg @ref LL_LPUART_HWCONTROL_NONE
AnnaBridge	189:f392fc9709a3	1303	* @arg @ref LL_LPUART_HWCONTROL_RTS
AnnaBridge	189:f392fc9709a3	1304	* @arg @ref LL_LPUART_HWCONTROL_CTS
AnnaBridge	189:f392fc9709a3	1305	* @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
AnnaBridge	189:f392fc9709a3	1306	*/
AnnaBridge	189:f392fc9709a3	1307	__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1308	{
AnnaBridge	189:f392fc9709a3	1309	return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE \| USART_CR3_CTSE));
AnnaBridge	189:f392fc9709a3	1310	}
AnnaBridge	189:f392fc9709a3	1311
AnnaBridge	189:f392fc9709a3	1312	/**
AnnaBridge	189:f392fc9709a3	1313	* @brief Enable Overrun detection
AnnaBridge	189:f392fc9709a3	1314	* @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
AnnaBridge	189:f392fc9709a3	1315	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1316	* @retval None
AnnaBridge	189:f392fc9709a3	1317	*/
AnnaBridge	189:f392fc9709a3	1318	__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1319	{
AnnaBridge	189:f392fc9709a3	1320	CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
AnnaBridge	189:f392fc9709a3	1321	}
AnnaBridge	189:f392fc9709a3	1322
AnnaBridge	189:f392fc9709a3	1323	/**
AnnaBridge	189:f392fc9709a3	1324	* @brief Disable Overrun detection
AnnaBridge	189:f392fc9709a3	1325	* @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
AnnaBridge	189:f392fc9709a3	1326	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1327	* @retval None
AnnaBridge	189:f392fc9709a3	1328	*/
AnnaBridge	189:f392fc9709a3	1329	__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1330	{
AnnaBridge	189:f392fc9709a3	1331	SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
AnnaBridge	189:f392fc9709a3	1332	}
AnnaBridge	189:f392fc9709a3	1333
AnnaBridge	189:f392fc9709a3	1334	/**
AnnaBridge	189:f392fc9709a3	1335	* @brief Indicate if Overrun detection is enabled
AnnaBridge	189:f392fc9709a3	1336	* @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
AnnaBridge	189:f392fc9709a3	1337	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1338	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1339	*/
AnnaBridge	189:f392fc9709a3	1340	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1341	{
AnnaBridge	189:f392fc9709a3	1342	return (READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
AnnaBridge	189:f392fc9709a3	1343	}
AnnaBridge	189:f392fc9709a3	1344
AnnaBridge	189:f392fc9709a3	1345	/**
AnnaBridge	189:f392fc9709a3	1346	* @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
AnnaBridge	189:f392fc9709a3	1347	* @rmtoll CR3 WUS LL_LPUART_SetWKUPType
AnnaBridge	189:f392fc9709a3	1348	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1349	* @param Type This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1350	* @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
AnnaBridge	189:f392fc9709a3	1351	* @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
AnnaBridge	189:f392fc9709a3	1352	* @arg @ref LL_LPUART_WAKEUP_ON_RXNE
AnnaBridge	189:f392fc9709a3	1353	* @retval None
AnnaBridge	189:f392fc9709a3	1354	*/
AnnaBridge	189:f392fc9709a3	1355	__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
AnnaBridge	189:f392fc9709a3	1356	{
AnnaBridge	189:f392fc9709a3	1357	MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
AnnaBridge	189:f392fc9709a3	1358	}
AnnaBridge	189:f392fc9709a3	1359
AnnaBridge	189:f392fc9709a3	1360	/**
AnnaBridge	189:f392fc9709a3	1361	* @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
AnnaBridge	189:f392fc9709a3	1362	* @rmtoll CR3 WUS LL_LPUART_GetWKUPType
AnnaBridge	189:f392fc9709a3	1363	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1364	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1365	* @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
AnnaBridge	189:f392fc9709a3	1366	* @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
AnnaBridge	189:f392fc9709a3	1367	* @arg @ref LL_LPUART_WAKEUP_ON_RXNE
AnnaBridge	189:f392fc9709a3	1368	*/
AnnaBridge	189:f392fc9709a3	1369	__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1370	{
AnnaBridge	189:f392fc9709a3	1371	return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
AnnaBridge	189:f392fc9709a3	1372	}
AnnaBridge	189:f392fc9709a3	1373
AnnaBridge	189:f392fc9709a3	1374	/**
AnnaBridge	189:f392fc9709a3	1375	* @brief Configure LPUART BRR register for achieving expected Baud Rate value.
AnnaBridge	189:f392fc9709a3	1376	*
AnnaBridge	189:f392fc9709a3	1377	* @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
AnnaBridge	189:f392fc9709a3	1378	* according to used Peripheral Clock and expected Baud Rate values
AnnaBridge	189:f392fc9709a3	1379	* @note Peripheral clock and Baud Rate values provided as function parameters should be valid
AnnaBridge	189:f392fc9709a3	1380	* (Baud rate value != 0).
AnnaBridge	189:f392fc9709a3	1381	* @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
AnnaBridge	189:f392fc9709a3	1382	* a care should be taken when generating high baud rates using high PeriphClk
AnnaBridge	189:f392fc9709a3	1383	* values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
AnnaBridge	189:f392fc9709a3	1384	* @rmtoll BRR BRR LL_LPUART_SetBaudRate
AnnaBridge	189:f392fc9709a3	1385	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1386	* @param PeriphClk Peripheral Clock
AnnaBridge	189:f392fc9709a3	1387	@if USART_PRESC_PRESCALER
AnnaBridge	189:f392fc9709a3	1388	* @param PrescalerValue This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1389	* @arg @ref LL_LPUART_PRESCALER_DIV1
AnnaBridge	189:f392fc9709a3	1390	* @arg @ref LL_LPUART_PRESCALER_DIV2
AnnaBridge	189:f392fc9709a3	1391	* @arg @ref LL_LPUART_PRESCALER_DIV4
AnnaBridge	189:f392fc9709a3	1392	* @arg @ref LL_LPUART_PRESCALER_DIV6
AnnaBridge	189:f392fc9709a3	1393	* @arg @ref LL_LPUART_PRESCALER_DIV8
AnnaBridge	189:f392fc9709a3	1394	* @arg @ref LL_LPUART_PRESCALER_DIV10
AnnaBridge	189:f392fc9709a3	1395	* @arg @ref LL_LPUART_PRESCALER_DIV12
AnnaBridge	189:f392fc9709a3	1396	* @arg @ref LL_LPUART_PRESCALER_DIV16
AnnaBridge	189:f392fc9709a3	1397	* @arg @ref LL_LPUART_PRESCALER_DIV32
AnnaBridge	189:f392fc9709a3	1398	* @arg @ref LL_LPUART_PRESCALER_DIV64
AnnaBridge	189:f392fc9709a3	1399	* @arg @ref LL_LPUART_PRESCALER_DIV128
AnnaBridge	189:f392fc9709a3	1400	* @arg @ref LL_LPUART_PRESCALER_DIV256
AnnaBridge	189:f392fc9709a3	1401	@endif
AnnaBridge	189:f392fc9709a3	1402	* @param BaudRate Baud Rate
AnnaBridge	189:f392fc9709a3	1403	* @retval None
AnnaBridge	189:f392fc9709a3	1404	*/
AnnaBridge	189:f392fc9709a3	1405	#if defined(USART_PRESC_PRESCALER)
AnnaBridge	189:f392fc9709a3	1406	__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate)
AnnaBridge	189:f392fc9709a3	1407	#else
AnnaBridge	189:f392fc9709a3	1408	__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
AnnaBridge	189:f392fc9709a3	1409	#endif
AnnaBridge	189:f392fc9709a3	1410	{
AnnaBridge	189:f392fc9709a3	1411	#if defined(USART_PRESC_PRESCALER)
AnnaBridge	189:f392fc9709a3	1412	LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
AnnaBridge	189:f392fc9709a3	1413	#else
AnnaBridge	189:f392fc9709a3	1414	LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
AnnaBridge	189:f392fc9709a3	1415	#endif
AnnaBridge	189:f392fc9709a3	1416	}
AnnaBridge	189:f392fc9709a3	1417
AnnaBridge	189:f392fc9709a3	1418	/**
AnnaBridge	189:f392fc9709a3	1419	* @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
AnnaBridge	189:f392fc9709a3	1420	* (full BRR content), and to used Peripheral Clock values
AnnaBridge	189:f392fc9709a3	1421	* @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
AnnaBridge	189:f392fc9709a3	1422	* @rmtoll BRR BRR LL_LPUART_GetBaudRate
AnnaBridge	189:f392fc9709a3	1423	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1424	* @param PeriphClk Peripheral Clock
AnnaBridge	189:f392fc9709a3	1425	@if USART_PRESC_PRESCALER
AnnaBridge	189:f392fc9709a3	1426	* @param PrescalerValue This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1427	* @arg @ref LL_LPUART_PRESCALER_DIV1
AnnaBridge	189:f392fc9709a3	1428	* @arg @ref LL_LPUART_PRESCALER_DIV2
AnnaBridge	189:f392fc9709a3	1429	* @arg @ref LL_LPUART_PRESCALER_DIV4
AnnaBridge	189:f392fc9709a3	1430	* @arg @ref LL_LPUART_PRESCALER_DIV6
AnnaBridge	189:f392fc9709a3	1431	* @arg @ref LL_LPUART_PRESCALER_DIV8
AnnaBridge	189:f392fc9709a3	1432	* @arg @ref LL_LPUART_PRESCALER_DIV10
AnnaBridge	189:f392fc9709a3	1433	* @arg @ref LL_LPUART_PRESCALER_DIV12
AnnaBridge	189:f392fc9709a3	1434	* @arg @ref LL_LPUART_PRESCALER_DIV16
AnnaBridge	189:f392fc9709a3	1435	* @arg @ref LL_LPUART_PRESCALER_DIV32
AnnaBridge	189:f392fc9709a3	1436	* @arg @ref LL_LPUART_PRESCALER_DIV64
AnnaBridge	189:f392fc9709a3	1437	* @arg @ref LL_LPUART_PRESCALER_DIV128
AnnaBridge	189:f392fc9709a3	1438	* @arg @ref LL_LPUART_PRESCALER_DIV256
AnnaBridge	189:f392fc9709a3	1439	@endif
AnnaBridge	189:f392fc9709a3	1440	* @retval Baud Rate
AnnaBridge	189:f392fc9709a3	1441	*/
AnnaBridge	189:f392fc9709a3	1442	#if defined(USART_PRESC_PRESCALER)
AnnaBridge	189:f392fc9709a3	1443	__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
AnnaBridge	189:f392fc9709a3	1444	#else
AnnaBridge	189:f392fc9709a3	1445	__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk)
AnnaBridge	189:f392fc9709a3	1446	#endif
AnnaBridge	189:f392fc9709a3	1447	{
AnnaBridge	189:f392fc9709a3	1448	register uint32_t lpuartdiv = 0x0U;
AnnaBridge	189:f392fc9709a3	1449	register uint32_t brrresult = 0x0U;
AnnaBridge	189:f392fc9709a3	1450	#if defined(USART_PRESC_PRESCALER)
AnnaBridge	189:f392fc9709a3	1451	register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[PrescalerValue]));
AnnaBridge	189:f392fc9709a3	1452	#endif
AnnaBridge	189:f392fc9709a3	1453
AnnaBridge	189:f392fc9709a3	1454	lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
AnnaBridge	189:f392fc9709a3	1455
AnnaBridge	189:f392fc9709a3	1456	if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
AnnaBridge	189:f392fc9709a3	1457	{
AnnaBridge	189:f392fc9709a3	1458	#if defined(USART_PRESC_PRESCALER)
AnnaBridge	189:f392fc9709a3	1459	brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
AnnaBridge	189:f392fc9709a3	1460	#else
AnnaBridge	189:f392fc9709a3	1461	brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
AnnaBridge	189:f392fc9709a3	1462	#endif
AnnaBridge	189:f392fc9709a3	1463	}
AnnaBridge	189:f392fc9709a3	1464
AnnaBridge	189:f392fc9709a3	1465	return (brrresult);
AnnaBridge	189:f392fc9709a3	1466	}
AnnaBridge	189:f392fc9709a3	1467
AnnaBridge	189:f392fc9709a3	1468	/**
AnnaBridge	189:f392fc9709a3	1469	* @}
AnnaBridge	189:f392fc9709a3	1470	*/
AnnaBridge	189:f392fc9709a3	1471
AnnaBridge	189:f392fc9709a3	1472	/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
AnnaBridge	189:f392fc9709a3	1473	* @{
AnnaBridge	189:f392fc9709a3	1474	*/
AnnaBridge	189:f392fc9709a3	1475
AnnaBridge	189:f392fc9709a3	1476	/**
AnnaBridge	189:f392fc9709a3	1477	* @brief Enable Single Wire Half-Duplex mode
AnnaBridge	189:f392fc9709a3	1478	* @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
AnnaBridge	189:f392fc9709a3	1479	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1480	* @retval None
AnnaBridge	189:f392fc9709a3	1481	*/
AnnaBridge	189:f392fc9709a3	1482	__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1483	{
AnnaBridge	189:f392fc9709a3	1484	SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
AnnaBridge	189:f392fc9709a3	1485	}
AnnaBridge	189:f392fc9709a3	1486
AnnaBridge	189:f392fc9709a3	1487	/**
AnnaBridge	189:f392fc9709a3	1488	* @brief Disable Single Wire Half-Duplex mode
AnnaBridge	189:f392fc9709a3	1489	* @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
AnnaBridge	189:f392fc9709a3	1490	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1491	* @retval None
AnnaBridge	189:f392fc9709a3	1492	*/
AnnaBridge	189:f392fc9709a3	1493	__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1494	{
AnnaBridge	189:f392fc9709a3	1495	CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
AnnaBridge	189:f392fc9709a3	1496	}
AnnaBridge	189:f392fc9709a3	1497
AnnaBridge	189:f392fc9709a3	1498	/**
AnnaBridge	189:f392fc9709a3	1499	* @brief Indicate if Single Wire Half-Duplex mode is enabled
AnnaBridge	189:f392fc9709a3	1500	* @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
AnnaBridge	189:f392fc9709a3	1501	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1502	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1503	*/
AnnaBridge	189:f392fc9709a3	1504	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1505	{
AnnaBridge	189:f392fc9709a3	1506	return (READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
AnnaBridge	189:f392fc9709a3	1507	}
AnnaBridge	189:f392fc9709a3	1508
AnnaBridge	189:f392fc9709a3	1509	/**
AnnaBridge	189:f392fc9709a3	1510	* @}
AnnaBridge	189:f392fc9709a3	1511	*/
AnnaBridge	189:f392fc9709a3	1512
AnnaBridge	189:f392fc9709a3	1513	/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
AnnaBridge	189:f392fc9709a3	1514	* @{
AnnaBridge	189:f392fc9709a3	1515	*/
AnnaBridge	189:f392fc9709a3	1516
AnnaBridge	189:f392fc9709a3	1517	/**
AnnaBridge	189:f392fc9709a3	1518	* @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
AnnaBridge	189:f392fc9709a3	1519	* @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
AnnaBridge	189:f392fc9709a3	1520	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1521	* @param Time Value between Min_Data=0 and Max_Data=31
AnnaBridge	189:f392fc9709a3	1522	* @retval None
AnnaBridge	189:f392fc9709a3	1523	*/
AnnaBridge	189:f392fc9709a3	1524	__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
AnnaBridge	189:f392fc9709a3	1525	{
AnnaBridge	189:f392fc9709a3	1526	MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
AnnaBridge	189:f392fc9709a3	1527	}
AnnaBridge	189:f392fc9709a3	1528
AnnaBridge	189:f392fc9709a3	1529	/**
AnnaBridge	189:f392fc9709a3	1530	* @brief Return DEDT (Driver Enable De-Assertion Time)
AnnaBridge	189:f392fc9709a3	1531	* @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
AnnaBridge	189:f392fc9709a3	1532	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1533	* @retval Time value expressed on 5 bits ([4:0] bits) : c
AnnaBridge	189:f392fc9709a3	1534	*/
AnnaBridge	189:f392fc9709a3	1535	__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1536	{
AnnaBridge	189:f392fc9709a3	1537	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
AnnaBridge	189:f392fc9709a3	1538	}
AnnaBridge	189:f392fc9709a3	1539
AnnaBridge	189:f392fc9709a3	1540	/**
AnnaBridge	189:f392fc9709a3	1541	* @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
AnnaBridge	189:f392fc9709a3	1542	* @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
AnnaBridge	189:f392fc9709a3	1543	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1544	* @param Time Value between Min_Data=0 and Max_Data=31
AnnaBridge	189:f392fc9709a3	1545	* @retval None
AnnaBridge	189:f392fc9709a3	1546	*/
AnnaBridge	189:f392fc9709a3	1547	__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
AnnaBridge	189:f392fc9709a3	1548	{
AnnaBridge	189:f392fc9709a3	1549	MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
AnnaBridge	189:f392fc9709a3	1550	}
AnnaBridge	189:f392fc9709a3	1551
AnnaBridge	189:f392fc9709a3	1552	/**
AnnaBridge	189:f392fc9709a3	1553	* @brief Return DEAT (Driver Enable Assertion Time)
AnnaBridge	189:f392fc9709a3	1554	* @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
AnnaBridge	189:f392fc9709a3	1555	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1556	* @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
AnnaBridge	189:f392fc9709a3	1557	*/
AnnaBridge	189:f392fc9709a3	1558	__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1559	{
AnnaBridge	189:f392fc9709a3	1560	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
AnnaBridge	189:f392fc9709a3	1561	}
AnnaBridge	189:f392fc9709a3	1562
AnnaBridge	189:f392fc9709a3	1563	/**
AnnaBridge	189:f392fc9709a3	1564	* @brief Enable Driver Enable (DE) Mode
AnnaBridge	189:f392fc9709a3	1565	* @rmtoll CR3 DEM LL_LPUART_EnableDEMode
AnnaBridge	189:f392fc9709a3	1566	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1567	* @retval None
AnnaBridge	189:f392fc9709a3	1568	*/
AnnaBridge	189:f392fc9709a3	1569	__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1570	{
AnnaBridge	189:f392fc9709a3	1571	SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
AnnaBridge	189:f392fc9709a3	1572	}
AnnaBridge	189:f392fc9709a3	1573
AnnaBridge	189:f392fc9709a3	1574	/**
AnnaBridge	189:f392fc9709a3	1575	* @brief Disable Driver Enable (DE) Mode
AnnaBridge	189:f392fc9709a3	1576	* @rmtoll CR3 DEM LL_LPUART_DisableDEMode
AnnaBridge	189:f392fc9709a3	1577	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1578	* @retval None
AnnaBridge	189:f392fc9709a3	1579	*/
AnnaBridge	189:f392fc9709a3	1580	__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1581	{
AnnaBridge	189:f392fc9709a3	1582	CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
AnnaBridge	189:f392fc9709a3	1583	}
AnnaBridge	189:f392fc9709a3	1584
AnnaBridge	189:f392fc9709a3	1585	/**
AnnaBridge	189:f392fc9709a3	1586	* @brief Indicate if Driver Enable (DE) Mode is enabled
AnnaBridge	189:f392fc9709a3	1587	* @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
AnnaBridge	189:f392fc9709a3	1588	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1589	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1590	*/
AnnaBridge	189:f392fc9709a3	1591	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1592	{
AnnaBridge	189:f392fc9709a3	1593	return (READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
AnnaBridge	189:f392fc9709a3	1594	}
AnnaBridge	189:f392fc9709a3	1595
AnnaBridge	189:f392fc9709a3	1596	/**
AnnaBridge	189:f392fc9709a3	1597	* @brief Select Driver Enable Polarity
AnnaBridge	189:f392fc9709a3	1598	* @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
AnnaBridge	189:f392fc9709a3	1599	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1600	* @param Polarity This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1601	* @arg @ref LL_LPUART_DE_POLARITY_HIGH
AnnaBridge	189:f392fc9709a3	1602	* @arg @ref LL_LPUART_DE_POLARITY_LOW
AnnaBridge	189:f392fc9709a3	1603	* @retval None
AnnaBridge	189:f392fc9709a3	1604	*/
AnnaBridge	189:f392fc9709a3	1605	__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
AnnaBridge	189:f392fc9709a3	1606	{
AnnaBridge	189:f392fc9709a3	1607	MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
AnnaBridge	189:f392fc9709a3	1608	}
AnnaBridge	189:f392fc9709a3	1609
AnnaBridge	189:f392fc9709a3	1610	/**
AnnaBridge	189:f392fc9709a3	1611	* @brief Return Driver Enable Polarity
AnnaBridge	189:f392fc9709a3	1612	* @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
AnnaBridge	189:f392fc9709a3	1613	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1614	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1615	* @arg @ref LL_LPUART_DE_POLARITY_HIGH
AnnaBridge	189:f392fc9709a3	1616	* @arg @ref LL_LPUART_DE_POLARITY_LOW
AnnaBridge	189:f392fc9709a3	1617	*/
AnnaBridge	189:f392fc9709a3	1618	__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1619	{
AnnaBridge	189:f392fc9709a3	1620	return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
AnnaBridge	189:f392fc9709a3	1621	}
AnnaBridge	189:f392fc9709a3	1622
AnnaBridge	189:f392fc9709a3	1623	/**
AnnaBridge	189:f392fc9709a3	1624	* @}
AnnaBridge	189:f392fc9709a3	1625	*/
AnnaBridge	189:f392fc9709a3	1626
AnnaBridge	189:f392fc9709a3	1627	/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	189:f392fc9709a3	1628	* @{
AnnaBridge	189:f392fc9709a3	1629	*/
AnnaBridge	189:f392fc9709a3	1630
AnnaBridge	189:f392fc9709a3	1631	/**
AnnaBridge	189:f392fc9709a3	1632	* @brief Check if the LPUART Parity Error Flag is set or not
AnnaBridge	189:f392fc9709a3	1633	* @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
AnnaBridge	189:f392fc9709a3	1634	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1635	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1636	*/
AnnaBridge	189:f392fc9709a3	1637	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1638	{
AnnaBridge	189:f392fc9709a3	1639	return (READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
AnnaBridge	189:f392fc9709a3	1640	}
AnnaBridge	189:f392fc9709a3	1641
AnnaBridge	189:f392fc9709a3	1642	/**
AnnaBridge	189:f392fc9709a3	1643	* @brief Check if the LPUART Framing Error Flag is set or not
AnnaBridge	189:f392fc9709a3	1644	* @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
AnnaBridge	189:f392fc9709a3	1645	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1646	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1647	*/
AnnaBridge	189:f392fc9709a3	1648	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1649	{
AnnaBridge	189:f392fc9709a3	1650	return (READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
AnnaBridge	189:f392fc9709a3	1651	}
AnnaBridge	189:f392fc9709a3	1652
AnnaBridge	189:f392fc9709a3	1653	/**
AnnaBridge	189:f392fc9709a3	1654	* @brief Check if the LPUART Noise error detected Flag is set or not
AnnaBridge	189:f392fc9709a3	1655	* @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
AnnaBridge	189:f392fc9709a3	1656	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1657	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1658	*/
AnnaBridge	189:f392fc9709a3	1659	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1660	{
AnnaBridge	189:f392fc9709a3	1661	return (READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
AnnaBridge	189:f392fc9709a3	1662	}
AnnaBridge	189:f392fc9709a3	1663
AnnaBridge	189:f392fc9709a3	1664	/**
AnnaBridge	189:f392fc9709a3	1665	* @brief Check if the LPUART OverRun Error Flag is set or not
AnnaBridge	189:f392fc9709a3	1666	* @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
AnnaBridge	189:f392fc9709a3	1667	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1668	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1669	*/
AnnaBridge	189:f392fc9709a3	1670	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1671	{
AnnaBridge	189:f392fc9709a3	1672	return (READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
AnnaBridge	189:f392fc9709a3	1673	}
AnnaBridge	189:f392fc9709a3	1674
AnnaBridge	189:f392fc9709a3	1675	/**
AnnaBridge	189:f392fc9709a3	1676	* @brief Check if the LPUART IDLE line detected Flag is set or not
AnnaBridge	189:f392fc9709a3	1677	* @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
AnnaBridge	189:f392fc9709a3	1678	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1679	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1680	*/
AnnaBridge	189:f392fc9709a3	1681	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1682	{
AnnaBridge	189:f392fc9709a3	1683	return (READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
AnnaBridge	189:f392fc9709a3	1684	}
AnnaBridge	189:f392fc9709a3	1685
AnnaBridge	189:f392fc9709a3	1686	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	1687
AnnaBridge	189:f392fc9709a3	1688	/* Legacy define */
AnnaBridge	189:f392fc9709a3	1689	#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
AnnaBridge	189:f392fc9709a3	1690
AnnaBridge	189:f392fc9709a3	1691	/**
AnnaBridge	189:f392fc9709a3	1692	* @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
AnnaBridge	189:f392fc9709a3	1693	* @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
AnnaBridge	189:f392fc9709a3	1694	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1695	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1696	*/
AnnaBridge	189:f392fc9709a3	1697	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1698	{
AnnaBridge	189:f392fc9709a3	1699	return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE));
AnnaBridge	189:f392fc9709a3	1700	}
AnnaBridge	189:f392fc9709a3	1701	#else
AnnaBridge	189:f392fc9709a3	1702
AnnaBridge	189:f392fc9709a3	1703	/**
AnnaBridge	189:f392fc9709a3	1704	* @brief Check if the LPUART Read Data Register Not Empty Flag is set or not
AnnaBridge	189:f392fc9709a3	1705	* @rmtoll ISR RXNE LL_LPUART_IsActiveFlag_RXNE
AnnaBridge	189:f392fc9709a3	1706	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1707	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1708	*/
AnnaBridge	189:f392fc9709a3	1709	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1710	{
AnnaBridge	189:f392fc9709a3	1711	return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
AnnaBridge	189:f392fc9709a3	1712	}
AnnaBridge	189:f392fc9709a3	1713	#endif
AnnaBridge	189:f392fc9709a3	1714
AnnaBridge	189:f392fc9709a3	1715	/**
AnnaBridge	189:f392fc9709a3	1716	* @brief Check if the LPUART Transmission Complete Flag is set or not
AnnaBridge	189:f392fc9709a3	1717	* @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
AnnaBridge	189:f392fc9709a3	1718	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1719	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1720	*/
AnnaBridge	189:f392fc9709a3	1721	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1722	{
AnnaBridge	189:f392fc9709a3	1723	return (READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
AnnaBridge	189:f392fc9709a3	1724	}
AnnaBridge	189:f392fc9709a3	1725
AnnaBridge	189:f392fc9709a3	1726	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	1727
AnnaBridge	189:f392fc9709a3	1728	/* Legacy define */
AnnaBridge	189:f392fc9709a3	1729	#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
AnnaBridge	189:f392fc9709a3	1730
AnnaBridge	189:f392fc9709a3	1731	/**
AnnaBridge	189:f392fc9709a3	1732	* @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
AnnaBridge	189:f392fc9709a3	1733	* @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
AnnaBridge	189:f392fc9709a3	1734	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1735	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1736	*/
AnnaBridge	189:f392fc9709a3	1737	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1738	{
AnnaBridge	189:f392fc9709a3	1739	return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF));
AnnaBridge	189:f392fc9709a3	1740	}
AnnaBridge	189:f392fc9709a3	1741	#else
AnnaBridge	189:f392fc9709a3	1742
AnnaBridge	189:f392fc9709a3	1743	/**
AnnaBridge	189:f392fc9709a3	1744	* @brief Check if the LPUART Transmit Data Register Empty Flag is set or not
AnnaBridge	189:f392fc9709a3	1745	* @rmtoll ISR TXE LL_LPUART_IsActiveFlag_TXE
AnnaBridge	189:f392fc9709a3	1746	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1747	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1748	*/
AnnaBridge	189:f392fc9709a3	1749	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1750	{
AnnaBridge	189:f392fc9709a3	1751	return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
AnnaBridge	189:f392fc9709a3	1752	}
AnnaBridge	189:f392fc9709a3	1753	#endif
AnnaBridge	189:f392fc9709a3	1754
AnnaBridge	189:f392fc9709a3	1755	/**
AnnaBridge	189:f392fc9709a3	1756	* @brief Check if the LPUART CTS interrupt Flag is set or not
AnnaBridge	189:f392fc9709a3	1757	* @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
AnnaBridge	189:f392fc9709a3	1758	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1759	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1760	*/
AnnaBridge	189:f392fc9709a3	1761	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1762	{
AnnaBridge	189:f392fc9709a3	1763	return (READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
AnnaBridge	189:f392fc9709a3	1764	}
AnnaBridge	189:f392fc9709a3	1765
AnnaBridge	189:f392fc9709a3	1766	/**
AnnaBridge	189:f392fc9709a3	1767	* @brief Check if the LPUART CTS Flag is set or not
AnnaBridge	189:f392fc9709a3	1768	* @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
AnnaBridge	189:f392fc9709a3	1769	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1770	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1771	*/
AnnaBridge	189:f392fc9709a3	1772	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1773	{
AnnaBridge	189:f392fc9709a3	1774	return (READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
AnnaBridge	189:f392fc9709a3	1775	}
AnnaBridge	189:f392fc9709a3	1776
AnnaBridge	189:f392fc9709a3	1777	/**
AnnaBridge	189:f392fc9709a3	1778	* @brief Check if the LPUART Busy Flag is set or not
AnnaBridge	189:f392fc9709a3	1779	* @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
AnnaBridge	189:f392fc9709a3	1780	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1781	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1782	*/
AnnaBridge	189:f392fc9709a3	1783	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1784	{
AnnaBridge	189:f392fc9709a3	1785	return (READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
AnnaBridge	189:f392fc9709a3	1786	}
AnnaBridge	189:f392fc9709a3	1787
AnnaBridge	189:f392fc9709a3	1788	/**
AnnaBridge	189:f392fc9709a3	1789	* @brief Check if the LPUART Character Match Flag is set or not
AnnaBridge	189:f392fc9709a3	1790	* @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
AnnaBridge	189:f392fc9709a3	1791	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1792	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1793	*/
AnnaBridge	189:f392fc9709a3	1794	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1795	{
AnnaBridge	189:f392fc9709a3	1796	return (READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
AnnaBridge	189:f392fc9709a3	1797	}
AnnaBridge	189:f392fc9709a3	1798
AnnaBridge	189:f392fc9709a3	1799	/**
AnnaBridge	189:f392fc9709a3	1800	* @brief Check if the LPUART Send Break Flag is set or not
AnnaBridge	189:f392fc9709a3	1801	* @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
AnnaBridge	189:f392fc9709a3	1802	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1803	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1804	*/
AnnaBridge	189:f392fc9709a3	1805	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1806	{
AnnaBridge	189:f392fc9709a3	1807	return (READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
AnnaBridge	189:f392fc9709a3	1808	}
AnnaBridge	189:f392fc9709a3	1809
AnnaBridge	189:f392fc9709a3	1810	/**
AnnaBridge	189:f392fc9709a3	1811	* @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
AnnaBridge	189:f392fc9709a3	1812	* @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
AnnaBridge	189:f392fc9709a3	1813	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1814	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1815	*/
AnnaBridge	189:f392fc9709a3	1816	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1817	{
AnnaBridge	189:f392fc9709a3	1818	return (READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
AnnaBridge	189:f392fc9709a3	1819	}
AnnaBridge	189:f392fc9709a3	1820
AnnaBridge	189:f392fc9709a3	1821	/**
AnnaBridge	189:f392fc9709a3	1822	* @brief Check if the LPUART Wake Up from stop mode Flag is set or not
AnnaBridge	189:f392fc9709a3	1823	* @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
AnnaBridge	189:f392fc9709a3	1824	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1825	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1826	*/
AnnaBridge	189:f392fc9709a3	1827	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1828	{
AnnaBridge	189:f392fc9709a3	1829	return (READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
AnnaBridge	189:f392fc9709a3	1830	}
AnnaBridge	189:f392fc9709a3	1831
AnnaBridge	189:f392fc9709a3	1832	/**
AnnaBridge	189:f392fc9709a3	1833	* @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
AnnaBridge	189:f392fc9709a3	1834	* @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
AnnaBridge	189:f392fc9709a3	1835	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1836	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1837	*/
AnnaBridge	189:f392fc9709a3	1838	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1839	{
AnnaBridge	189:f392fc9709a3	1840	return (READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
AnnaBridge	189:f392fc9709a3	1841	}
AnnaBridge	189:f392fc9709a3	1842
AnnaBridge	189:f392fc9709a3	1843	/**
AnnaBridge	189:f392fc9709a3	1844	* @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
AnnaBridge	189:f392fc9709a3	1845	* @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
AnnaBridge	189:f392fc9709a3	1846	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1847	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1848	*/
AnnaBridge	189:f392fc9709a3	1849	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1850	{
AnnaBridge	189:f392fc9709a3	1851	return (READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
AnnaBridge	189:f392fc9709a3	1852	}
AnnaBridge	189:f392fc9709a3	1853
AnnaBridge	189:f392fc9709a3	1854	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	1855
AnnaBridge	189:f392fc9709a3	1856	/**
AnnaBridge	189:f392fc9709a3	1857	* @brief Check if the LPUART TX FIFO Empty Flag is set or not
AnnaBridge	189:f392fc9709a3	1858	* @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
AnnaBridge	189:f392fc9709a3	1859	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1860	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1861	*/
AnnaBridge	189:f392fc9709a3	1862	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1863	{
AnnaBridge	189:f392fc9709a3	1864	return (READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE));
AnnaBridge	189:f392fc9709a3	1865	}
AnnaBridge	189:f392fc9709a3	1866
AnnaBridge	189:f392fc9709a3	1867	/**
AnnaBridge	189:f392fc9709a3	1868	* @brief Check if the LPUART RX FIFO Full Flag is set or not
AnnaBridge	189:f392fc9709a3	1869	* @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
AnnaBridge	189:f392fc9709a3	1870	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1871	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1872	*/
AnnaBridge	189:f392fc9709a3	1873	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1874	{
AnnaBridge	189:f392fc9709a3	1875	return (READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF));
AnnaBridge	189:f392fc9709a3	1876	}
AnnaBridge	189:f392fc9709a3	1877
AnnaBridge	189:f392fc9709a3	1878	/**
AnnaBridge	189:f392fc9709a3	1879	* @brief Check if the LPUART TX FIFO Threshold Flag is set or not
AnnaBridge	189:f392fc9709a3	1880	* @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
AnnaBridge	189:f392fc9709a3	1881	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1882	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1883	*/
AnnaBridge	189:f392fc9709a3	1884	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1885	{
AnnaBridge	189:f392fc9709a3	1886	return (READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT));
AnnaBridge	189:f392fc9709a3	1887	}
AnnaBridge	189:f392fc9709a3	1888
AnnaBridge	189:f392fc9709a3	1889	/**
AnnaBridge	189:f392fc9709a3	1890	* @brief Check if the LPUART RX FIFO Threshold Flag is set or not
AnnaBridge	189:f392fc9709a3	1891	* @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
AnnaBridge	189:f392fc9709a3	1892	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1893	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1894	*/
AnnaBridge	189:f392fc9709a3	1895	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1896	{
AnnaBridge	189:f392fc9709a3	1897	return (READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT));
AnnaBridge	189:f392fc9709a3	1898	}
AnnaBridge	189:f392fc9709a3	1899	#endif
AnnaBridge	189:f392fc9709a3	1900
AnnaBridge	189:f392fc9709a3	1901	/**
AnnaBridge	189:f392fc9709a3	1902	* @brief Clear Parity Error Flag
AnnaBridge	189:f392fc9709a3	1903	* @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
AnnaBridge	189:f392fc9709a3	1904	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1905	* @retval None
AnnaBridge	189:f392fc9709a3	1906	*/
AnnaBridge	189:f392fc9709a3	1907	__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1908	{
AnnaBridge	189:f392fc9709a3	1909	WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
AnnaBridge	189:f392fc9709a3	1910	}
AnnaBridge	189:f392fc9709a3	1911
AnnaBridge	189:f392fc9709a3	1912	/**
AnnaBridge	189:f392fc9709a3	1913	* @brief Clear Framing Error Flag
AnnaBridge	189:f392fc9709a3	1914	* @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
AnnaBridge	189:f392fc9709a3	1915	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1916	* @retval None
AnnaBridge	189:f392fc9709a3	1917	*/
AnnaBridge	189:f392fc9709a3	1918	__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1919	{
AnnaBridge	189:f392fc9709a3	1920	WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
AnnaBridge	189:f392fc9709a3	1921	}
AnnaBridge	189:f392fc9709a3	1922
AnnaBridge	189:f392fc9709a3	1923	/**
AnnaBridge	189:f392fc9709a3	1924	* @brief Clear Noise detected Flag
AnnaBridge	189:f392fc9709a3	1925	* @rmtoll ICR NCF LL_LPUART_ClearFlag_NE
AnnaBridge	189:f392fc9709a3	1926	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1927	* @retval None
AnnaBridge	189:f392fc9709a3	1928	*/
AnnaBridge	189:f392fc9709a3	1929	__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1930	{
AnnaBridge	189:f392fc9709a3	1931	WRITE_REG(LPUARTx->ICR, USART_ICR_NCF);
AnnaBridge	189:f392fc9709a3	1932	}
AnnaBridge	189:f392fc9709a3	1933
AnnaBridge	189:f392fc9709a3	1934	/**
AnnaBridge	189:f392fc9709a3	1935	* @brief Clear OverRun Error Flag
AnnaBridge	189:f392fc9709a3	1936	* @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
AnnaBridge	189:f392fc9709a3	1937	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1938	* @retval None
AnnaBridge	189:f392fc9709a3	1939	*/
AnnaBridge	189:f392fc9709a3	1940	__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1941	{
AnnaBridge	189:f392fc9709a3	1942	WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
AnnaBridge	189:f392fc9709a3	1943	}
AnnaBridge	189:f392fc9709a3	1944
AnnaBridge	189:f392fc9709a3	1945	/**
AnnaBridge	189:f392fc9709a3	1946	* @brief Clear IDLE line detected Flag
AnnaBridge	189:f392fc9709a3	1947	* @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
AnnaBridge	189:f392fc9709a3	1948	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1949	* @retval None
AnnaBridge	189:f392fc9709a3	1950	*/
AnnaBridge	189:f392fc9709a3	1951	__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1952	{
AnnaBridge	189:f392fc9709a3	1953	WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
AnnaBridge	189:f392fc9709a3	1954	}
AnnaBridge	189:f392fc9709a3	1955
AnnaBridge	189:f392fc9709a3	1956	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	1957
AnnaBridge	189:f392fc9709a3	1958	/**
AnnaBridge	189:f392fc9709a3	1959	* @brief Clear TX FIFO Empty Flag
AnnaBridge	189:f392fc9709a3	1960	* @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE
AnnaBridge	189:f392fc9709a3	1961	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1962	* @retval None
AnnaBridge	189:f392fc9709a3	1963	*/
AnnaBridge	189:f392fc9709a3	1964	__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1965	{
AnnaBridge	189:f392fc9709a3	1966	WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF);
AnnaBridge	189:f392fc9709a3	1967	}
AnnaBridge	189:f392fc9709a3	1968	#endif
AnnaBridge	189:f392fc9709a3	1969
AnnaBridge	189:f392fc9709a3	1970	/**
AnnaBridge	189:f392fc9709a3	1971	* @brief Clear Transmission Complete Flag
AnnaBridge	189:f392fc9709a3	1972	* @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
AnnaBridge	189:f392fc9709a3	1973	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1974	* @retval None
AnnaBridge	189:f392fc9709a3	1975	*/
AnnaBridge	189:f392fc9709a3	1976	__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1977	{
AnnaBridge	189:f392fc9709a3	1978	WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
AnnaBridge	189:f392fc9709a3	1979	}
AnnaBridge	189:f392fc9709a3	1980
AnnaBridge	189:f392fc9709a3	1981	/**
AnnaBridge	189:f392fc9709a3	1982	* @brief Clear CTS Interrupt Flag
AnnaBridge	189:f392fc9709a3	1983	* @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
AnnaBridge	189:f392fc9709a3	1984	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1985	* @retval None
AnnaBridge	189:f392fc9709a3	1986	*/
AnnaBridge	189:f392fc9709a3	1987	__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1988	{
AnnaBridge	189:f392fc9709a3	1989	WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
AnnaBridge	189:f392fc9709a3	1990	}
AnnaBridge	189:f392fc9709a3	1991
AnnaBridge	189:f392fc9709a3	1992	/**
AnnaBridge	189:f392fc9709a3	1993	* @brief Clear Character Match Flag
AnnaBridge	189:f392fc9709a3	1994	* @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
AnnaBridge	189:f392fc9709a3	1995	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	1996	* @retval None
AnnaBridge	189:f392fc9709a3	1997	*/
AnnaBridge	189:f392fc9709a3	1998	__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	1999	{
AnnaBridge	189:f392fc9709a3	2000	WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
AnnaBridge	189:f392fc9709a3	2001	}
AnnaBridge	189:f392fc9709a3	2002
AnnaBridge	189:f392fc9709a3	2003	/**
AnnaBridge	189:f392fc9709a3	2004	* @brief Clear Wake Up from stop mode Flag
AnnaBridge	189:f392fc9709a3	2005	* @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
AnnaBridge	189:f392fc9709a3	2006	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2007	* @retval None
AnnaBridge	189:f392fc9709a3	2008	*/
AnnaBridge	189:f392fc9709a3	2009	__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2010	{
AnnaBridge	189:f392fc9709a3	2011	WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
AnnaBridge	189:f392fc9709a3	2012	}
AnnaBridge	189:f392fc9709a3	2013
AnnaBridge	189:f392fc9709a3	2014	/**
AnnaBridge	189:f392fc9709a3	2015	* @}
AnnaBridge	189:f392fc9709a3	2016	*/
AnnaBridge	189:f392fc9709a3	2017
AnnaBridge	189:f392fc9709a3	2018	/** @defgroup LPUART_LL_EF_IT_Management IT_Management
AnnaBridge	189:f392fc9709a3	2019	* @{
AnnaBridge	189:f392fc9709a3	2020	*/
AnnaBridge	189:f392fc9709a3	2021
AnnaBridge	189:f392fc9709a3	2022	/**
AnnaBridge	189:f392fc9709a3	2023	* @brief Enable IDLE Interrupt
AnnaBridge	189:f392fc9709a3	2024	* @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
AnnaBridge	189:f392fc9709a3	2025	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2026	* @retval None
AnnaBridge	189:f392fc9709a3	2027	*/
AnnaBridge	189:f392fc9709a3	2028	__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2029	{
AnnaBridge	189:f392fc9709a3	2030	SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
AnnaBridge	189:f392fc9709a3	2031	}
AnnaBridge	189:f392fc9709a3	2032
AnnaBridge	189:f392fc9709a3	2033	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	2034
AnnaBridge	189:f392fc9709a3	2035	/* Legacy define */
AnnaBridge	189:f392fc9709a3	2036	#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
AnnaBridge	189:f392fc9709a3	2037
AnnaBridge	189:f392fc9709a3	2038	/**
AnnaBridge	189:f392fc9709a3	2039	* @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
AnnaBridge	189:f392fc9709a3	2040	* @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
AnnaBridge	189:f392fc9709a3	2041	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2042	* @retval None
AnnaBridge	189:f392fc9709a3	2043	*/
AnnaBridge	189:f392fc9709a3	2044	__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2045	{
AnnaBridge	189:f392fc9709a3	2046	SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
AnnaBridge	189:f392fc9709a3	2047	}
AnnaBridge	189:f392fc9709a3	2048	#else
AnnaBridge	189:f392fc9709a3	2049
AnnaBridge	189:f392fc9709a3	2050	/**
AnnaBridge	189:f392fc9709a3	2051	* @brief Enable RX Not Empty Interrupt
AnnaBridge	189:f392fc9709a3	2052	* @rmtoll CR1 RXNEIE LL_LPUART_EnableIT_RXNE
AnnaBridge	189:f392fc9709a3	2053	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2054	* @retval None
AnnaBridge	189:f392fc9709a3	2055	*/
AnnaBridge	189:f392fc9709a3	2056	__STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2057	{
AnnaBridge	189:f392fc9709a3	2058	SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
AnnaBridge	189:f392fc9709a3	2059	}
AnnaBridge	189:f392fc9709a3	2060	#endif
AnnaBridge	189:f392fc9709a3	2061
AnnaBridge	189:f392fc9709a3	2062	/**
AnnaBridge	189:f392fc9709a3	2063	* @brief Enable Transmission Complete Interrupt
AnnaBridge	189:f392fc9709a3	2064	* @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
AnnaBridge	189:f392fc9709a3	2065	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2066	* @retval None
AnnaBridge	189:f392fc9709a3	2067	*/
AnnaBridge	189:f392fc9709a3	2068	__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2069	{
AnnaBridge	189:f392fc9709a3	2070	SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
AnnaBridge	189:f392fc9709a3	2071	}
AnnaBridge	189:f392fc9709a3	2072
AnnaBridge	189:f392fc9709a3	2073	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	2074
AnnaBridge	189:f392fc9709a3	2075	/* Legacy define */
AnnaBridge	189:f392fc9709a3	2076	#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
AnnaBridge	189:f392fc9709a3	2077
AnnaBridge	189:f392fc9709a3	2078	/**
AnnaBridge	189:f392fc9709a3	2079	* @brief Enable TX Empty and TX FIFO Not Full Interrupt
AnnaBridge	189:f392fc9709a3	2080	* @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
AnnaBridge	189:f392fc9709a3	2081	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2082	* @retval None
AnnaBridge	189:f392fc9709a3	2083	*/
AnnaBridge	189:f392fc9709a3	2084	__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2085	{
AnnaBridge	189:f392fc9709a3	2086	SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
AnnaBridge	189:f392fc9709a3	2087	}
AnnaBridge	189:f392fc9709a3	2088	#else
AnnaBridge	189:f392fc9709a3	2089
AnnaBridge	189:f392fc9709a3	2090	/**
AnnaBridge	189:f392fc9709a3	2091	* @brief Enable TX Empty Interrupt
AnnaBridge	189:f392fc9709a3	2092	* @rmtoll CR1 TXEIE LL_LPUART_EnableIT_TXE
AnnaBridge	189:f392fc9709a3	2093	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2094	* @retval None
AnnaBridge	189:f392fc9709a3	2095	*/
AnnaBridge	189:f392fc9709a3	2096	__STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2097	{
AnnaBridge	189:f392fc9709a3	2098	SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
AnnaBridge	189:f392fc9709a3	2099	}
AnnaBridge	189:f392fc9709a3	2100	#endif
AnnaBridge	189:f392fc9709a3	2101
AnnaBridge	189:f392fc9709a3	2102	/**
AnnaBridge	189:f392fc9709a3	2103	* @brief Enable Parity Error Interrupt
AnnaBridge	189:f392fc9709a3	2104	* @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
AnnaBridge	189:f392fc9709a3	2105	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2106	* @retval None
AnnaBridge	189:f392fc9709a3	2107	*/
AnnaBridge	189:f392fc9709a3	2108	__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2109	{
AnnaBridge	189:f392fc9709a3	2110	SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
AnnaBridge	189:f392fc9709a3	2111	}
AnnaBridge	189:f392fc9709a3	2112
AnnaBridge	189:f392fc9709a3	2113	/**
AnnaBridge	189:f392fc9709a3	2114	* @brief Enable Character Match Interrupt
AnnaBridge	189:f392fc9709a3	2115	* @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
AnnaBridge	189:f392fc9709a3	2116	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2117	* @retval None
AnnaBridge	189:f392fc9709a3	2118	*/
AnnaBridge	189:f392fc9709a3	2119	__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2120	{
AnnaBridge	189:f392fc9709a3	2121	SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
AnnaBridge	189:f392fc9709a3	2122	}
AnnaBridge	189:f392fc9709a3	2123
AnnaBridge	189:f392fc9709a3	2124	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	2125
AnnaBridge	189:f392fc9709a3	2126	/**
AnnaBridge	189:f392fc9709a3	2127	* @brief Enable TX FIFO Empty Interrupt
AnnaBridge	189:f392fc9709a3	2128	* @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
AnnaBridge	189:f392fc9709a3	2129	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2130	* @retval None
AnnaBridge	189:f392fc9709a3	2131	*/
AnnaBridge	189:f392fc9709a3	2132	__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2133	{
AnnaBridge	189:f392fc9709a3	2134	SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
AnnaBridge	189:f392fc9709a3	2135	}
AnnaBridge	189:f392fc9709a3	2136
AnnaBridge	189:f392fc9709a3	2137	/**
AnnaBridge	189:f392fc9709a3	2138	* @brief Enable RX FIFO Full Interrupt
AnnaBridge	189:f392fc9709a3	2139	* @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
AnnaBridge	189:f392fc9709a3	2140	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2141	* @retval None
AnnaBridge	189:f392fc9709a3	2142	*/
AnnaBridge	189:f392fc9709a3	2143	__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2144	{
AnnaBridge	189:f392fc9709a3	2145	SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
AnnaBridge	189:f392fc9709a3	2146	}
AnnaBridge	189:f392fc9709a3	2147	#endif
AnnaBridge	189:f392fc9709a3	2148
AnnaBridge	189:f392fc9709a3	2149	/**
AnnaBridge	189:f392fc9709a3	2150	* @brief Enable Error Interrupt
AnnaBridge	189:f392fc9709a3	2151	* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
AnnaBridge	189:f392fc9709a3	2152	* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
AnnaBridge	189:f392fc9709a3	2153	* - 0: Interrupt is inhibited
AnnaBridge	189:f392fc9709a3	2154	* - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
AnnaBridge	189:f392fc9709a3	2155	* @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
AnnaBridge	189:f392fc9709a3	2156	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2157	* @retval None
AnnaBridge	189:f392fc9709a3	2158	*/
AnnaBridge	189:f392fc9709a3	2159	__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2160	{
AnnaBridge	189:f392fc9709a3	2161	SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
AnnaBridge	189:f392fc9709a3	2162	}
AnnaBridge	189:f392fc9709a3	2163
AnnaBridge	189:f392fc9709a3	2164	/**
AnnaBridge	189:f392fc9709a3	2165	* @brief Enable CTS Interrupt
AnnaBridge	189:f392fc9709a3	2166	* @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
AnnaBridge	189:f392fc9709a3	2167	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2168	* @retval None
AnnaBridge	189:f392fc9709a3	2169	*/
AnnaBridge	189:f392fc9709a3	2170	__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2171	{
AnnaBridge	189:f392fc9709a3	2172	SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
AnnaBridge	189:f392fc9709a3	2173	}
AnnaBridge	189:f392fc9709a3	2174
AnnaBridge	189:f392fc9709a3	2175	/**
AnnaBridge	189:f392fc9709a3	2176	* @brief Enable Wake Up from Stop Mode Interrupt
AnnaBridge	189:f392fc9709a3	2177	* @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
AnnaBridge	189:f392fc9709a3	2178	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2179	* @retval None
AnnaBridge	189:f392fc9709a3	2180	*/
AnnaBridge	189:f392fc9709a3	2181	__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2182	{
AnnaBridge	189:f392fc9709a3	2183	SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
AnnaBridge	189:f392fc9709a3	2184	}
AnnaBridge	189:f392fc9709a3	2185
AnnaBridge	189:f392fc9709a3	2186	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	2187
AnnaBridge	189:f392fc9709a3	2188	/**
AnnaBridge	189:f392fc9709a3	2189	* @brief Enable TX FIFO Threshold Interrupt
AnnaBridge	189:f392fc9709a3	2190	* @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
AnnaBridge	189:f392fc9709a3	2191	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2192	* @retval None
AnnaBridge	189:f392fc9709a3	2193	*/
AnnaBridge	189:f392fc9709a3	2194	__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2195	{
AnnaBridge	189:f392fc9709a3	2196	SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
AnnaBridge	189:f392fc9709a3	2197	}
AnnaBridge	189:f392fc9709a3	2198
AnnaBridge	189:f392fc9709a3	2199	/**
AnnaBridge	189:f392fc9709a3	2200	* @brief Enable RX FIFO Threshold Interrupt
AnnaBridge	189:f392fc9709a3	2201	* @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
AnnaBridge	189:f392fc9709a3	2202	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2203	* @retval None
AnnaBridge	189:f392fc9709a3	2204	*/
AnnaBridge	189:f392fc9709a3	2205	__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2206	{
AnnaBridge	189:f392fc9709a3	2207	SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
AnnaBridge	189:f392fc9709a3	2208	}
AnnaBridge	189:f392fc9709a3	2209	#endif
AnnaBridge	189:f392fc9709a3	2210
AnnaBridge	189:f392fc9709a3	2211	/**
AnnaBridge	189:f392fc9709a3	2212	* @brief Disable IDLE Interrupt
AnnaBridge	189:f392fc9709a3	2213	* @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
AnnaBridge	189:f392fc9709a3	2214	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2215	* @retval None
AnnaBridge	189:f392fc9709a3	2216	*/
AnnaBridge	189:f392fc9709a3	2217	__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2218	{
AnnaBridge	189:f392fc9709a3	2219	CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
AnnaBridge	189:f392fc9709a3	2220	}
AnnaBridge	189:f392fc9709a3	2221
AnnaBridge	189:f392fc9709a3	2222	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	2223
AnnaBridge	189:f392fc9709a3	2224	/* Legacy define */
AnnaBridge	189:f392fc9709a3	2225	#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
AnnaBridge	189:f392fc9709a3	2226
AnnaBridge	189:f392fc9709a3	2227	/**
AnnaBridge	189:f392fc9709a3	2228	* @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
AnnaBridge	189:f392fc9709a3	2229	* @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
AnnaBridge	189:f392fc9709a3	2230	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2231	* @retval None
AnnaBridge	189:f392fc9709a3	2232	*/
AnnaBridge	189:f392fc9709a3	2233	__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2234	{
AnnaBridge	189:f392fc9709a3	2235	CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
AnnaBridge	189:f392fc9709a3	2236	}
AnnaBridge	189:f392fc9709a3	2237	#else
AnnaBridge	189:f392fc9709a3	2238
AnnaBridge	189:f392fc9709a3	2239	/**
AnnaBridge	189:f392fc9709a3	2240	* @brief Disable RX Not Empty Interrupt
AnnaBridge	189:f392fc9709a3	2241	* @rmtoll CR1 RXNEIE LL_LPUART_DisableIT_RXNE
AnnaBridge	189:f392fc9709a3	2242	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2243	* @retval None
AnnaBridge	189:f392fc9709a3	2244	*/
AnnaBridge	189:f392fc9709a3	2245	__STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2246	{
AnnaBridge	189:f392fc9709a3	2247	CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
AnnaBridge	189:f392fc9709a3	2248	}
AnnaBridge	189:f392fc9709a3	2249	#endif
AnnaBridge	189:f392fc9709a3	2250
AnnaBridge	189:f392fc9709a3	2251	/**
AnnaBridge	189:f392fc9709a3	2252	* @brief Disable Transmission Complete Interrupt
AnnaBridge	189:f392fc9709a3	2253	* @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
AnnaBridge	189:f392fc9709a3	2254	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2255	* @retval None
AnnaBridge	189:f392fc9709a3	2256	*/
AnnaBridge	189:f392fc9709a3	2257	__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2258	{
AnnaBridge	189:f392fc9709a3	2259	CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
AnnaBridge	189:f392fc9709a3	2260	}
AnnaBridge	189:f392fc9709a3	2261
AnnaBridge	189:f392fc9709a3	2262	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	2263
AnnaBridge	189:f392fc9709a3	2264	/* Legacy define */
AnnaBridge	189:f392fc9709a3	2265	#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
AnnaBridge	189:f392fc9709a3	2266
AnnaBridge	189:f392fc9709a3	2267	/**
AnnaBridge	189:f392fc9709a3	2268	* @brief Disable TX Empty and TX FIFO Not Full Interrupt
AnnaBridge	189:f392fc9709a3	2269	* @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
AnnaBridge	189:f392fc9709a3	2270	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2271	* @retval None
AnnaBridge	189:f392fc9709a3	2272	*/
AnnaBridge	189:f392fc9709a3	2273	__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2274	{
AnnaBridge	189:f392fc9709a3	2275	CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
AnnaBridge	189:f392fc9709a3	2276	}
AnnaBridge	189:f392fc9709a3	2277	#else
AnnaBridge	189:f392fc9709a3	2278
AnnaBridge	189:f392fc9709a3	2279	/**
AnnaBridge	189:f392fc9709a3	2280	* @brief Disable TX Empty Interrupt
AnnaBridge	189:f392fc9709a3	2281	* @rmtoll CR1 TXEIE LL_LPUART_DisableIT_TXE
AnnaBridge	189:f392fc9709a3	2282	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2283	* @retval None
AnnaBridge	189:f392fc9709a3	2284	*/
AnnaBridge	189:f392fc9709a3	2285	__STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2286	{
AnnaBridge	189:f392fc9709a3	2287	CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
AnnaBridge	189:f392fc9709a3	2288	}
AnnaBridge	189:f392fc9709a3	2289	#endif
AnnaBridge	189:f392fc9709a3	2290
AnnaBridge	189:f392fc9709a3	2291	/**
AnnaBridge	189:f392fc9709a3	2292	* @brief Disable Parity Error Interrupt
AnnaBridge	189:f392fc9709a3	2293	* @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
AnnaBridge	189:f392fc9709a3	2294	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2295	* @retval None
AnnaBridge	189:f392fc9709a3	2296	*/
AnnaBridge	189:f392fc9709a3	2297	__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2298	{
AnnaBridge	189:f392fc9709a3	2299	CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
AnnaBridge	189:f392fc9709a3	2300	}
AnnaBridge	189:f392fc9709a3	2301
AnnaBridge	189:f392fc9709a3	2302	/**
AnnaBridge	189:f392fc9709a3	2303	* @brief Disable Character Match Interrupt
AnnaBridge	189:f392fc9709a3	2304	* @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
AnnaBridge	189:f392fc9709a3	2305	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2306	* @retval None
AnnaBridge	189:f392fc9709a3	2307	*/
AnnaBridge	189:f392fc9709a3	2308	__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2309	{
AnnaBridge	189:f392fc9709a3	2310	CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
AnnaBridge	189:f392fc9709a3	2311	}
AnnaBridge	189:f392fc9709a3	2312
AnnaBridge	189:f392fc9709a3	2313	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	2314
AnnaBridge	189:f392fc9709a3	2315	/**
AnnaBridge	189:f392fc9709a3	2316	* @brief Disable TX FIFO Empty Interrupt
AnnaBridge	189:f392fc9709a3	2317	* @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
AnnaBridge	189:f392fc9709a3	2318	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2319	* @retval None
AnnaBridge	189:f392fc9709a3	2320	*/
AnnaBridge	189:f392fc9709a3	2321	__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2322	{
AnnaBridge	189:f392fc9709a3	2323	CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
AnnaBridge	189:f392fc9709a3	2324	}
AnnaBridge	189:f392fc9709a3	2325
AnnaBridge	189:f392fc9709a3	2326	/**
AnnaBridge	189:f392fc9709a3	2327	* @brief Disable RX FIFO Full Interrupt
AnnaBridge	189:f392fc9709a3	2328	* @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
AnnaBridge	189:f392fc9709a3	2329	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2330	* @retval None
AnnaBridge	189:f392fc9709a3	2331	*/
AnnaBridge	189:f392fc9709a3	2332	__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2333	{
AnnaBridge	189:f392fc9709a3	2334	CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
AnnaBridge	189:f392fc9709a3	2335	}
AnnaBridge	189:f392fc9709a3	2336	#endif
AnnaBridge	189:f392fc9709a3	2337
AnnaBridge	189:f392fc9709a3	2338	/**
AnnaBridge	189:f392fc9709a3	2339	* @brief Disable Error Interrupt
AnnaBridge	189:f392fc9709a3	2340	* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
AnnaBridge	189:f392fc9709a3	2341	* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
AnnaBridge	189:f392fc9709a3	2342	* - 0: Interrupt is inhibited
AnnaBridge	189:f392fc9709a3	2343	* - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
AnnaBridge	189:f392fc9709a3	2344	* @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
AnnaBridge	189:f392fc9709a3	2345	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2346	* @retval None
AnnaBridge	189:f392fc9709a3	2347	*/
AnnaBridge	189:f392fc9709a3	2348	__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2349	{
AnnaBridge	189:f392fc9709a3	2350	CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
AnnaBridge	189:f392fc9709a3	2351	}
AnnaBridge	189:f392fc9709a3	2352
AnnaBridge	189:f392fc9709a3	2353	/**
AnnaBridge	189:f392fc9709a3	2354	* @brief Disable CTS Interrupt
AnnaBridge	189:f392fc9709a3	2355	* @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
AnnaBridge	189:f392fc9709a3	2356	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2357	* @retval None
AnnaBridge	189:f392fc9709a3	2358	*/
AnnaBridge	189:f392fc9709a3	2359	__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2360	{
AnnaBridge	189:f392fc9709a3	2361	CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
AnnaBridge	189:f392fc9709a3	2362	}
AnnaBridge	189:f392fc9709a3	2363
AnnaBridge	189:f392fc9709a3	2364	/**
AnnaBridge	189:f392fc9709a3	2365	* @brief Disable Wake Up from Stop Mode Interrupt
AnnaBridge	189:f392fc9709a3	2366	* @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
AnnaBridge	189:f392fc9709a3	2367	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2368	* @retval None
AnnaBridge	189:f392fc9709a3	2369	*/
AnnaBridge	189:f392fc9709a3	2370	__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2371	{
AnnaBridge	189:f392fc9709a3	2372	CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
AnnaBridge	189:f392fc9709a3	2373	}
AnnaBridge	189:f392fc9709a3	2374
AnnaBridge	189:f392fc9709a3	2375	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	2376
AnnaBridge	189:f392fc9709a3	2377	/**
AnnaBridge	189:f392fc9709a3	2378	* @brief Disable TX FIFO Threshold Interrupt
AnnaBridge	189:f392fc9709a3	2379	* @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
AnnaBridge	189:f392fc9709a3	2380	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2381	* @retval None
AnnaBridge	189:f392fc9709a3	2382	*/
AnnaBridge	189:f392fc9709a3	2383	__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2384	{
AnnaBridge	189:f392fc9709a3	2385	CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
AnnaBridge	189:f392fc9709a3	2386	}
AnnaBridge	189:f392fc9709a3	2387
AnnaBridge	189:f392fc9709a3	2388	/**
AnnaBridge	189:f392fc9709a3	2389	* @brief Disable RX FIFO Threshold Interrupt
AnnaBridge	189:f392fc9709a3	2390	* @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
AnnaBridge	189:f392fc9709a3	2391	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2392	* @retval None
AnnaBridge	189:f392fc9709a3	2393	*/
AnnaBridge	189:f392fc9709a3	2394	__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2395	{
AnnaBridge	189:f392fc9709a3	2396	CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
AnnaBridge	189:f392fc9709a3	2397	}
AnnaBridge	189:f392fc9709a3	2398	#endif
AnnaBridge	189:f392fc9709a3	2399
AnnaBridge	189:f392fc9709a3	2400	/**
AnnaBridge	189:f392fc9709a3	2401	* @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2402	* @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
AnnaBridge	189:f392fc9709a3	2403	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2404	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2405	*/
AnnaBridge	189:f392fc9709a3	2406	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2407	{
AnnaBridge	189:f392fc9709a3	2408	return (READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
AnnaBridge	189:f392fc9709a3	2409	}
AnnaBridge	189:f392fc9709a3	2410
AnnaBridge	189:f392fc9709a3	2411	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	2412
AnnaBridge	189:f392fc9709a3	2413	/* Legacy define */
AnnaBridge	189:f392fc9709a3	2414	#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
AnnaBridge	189:f392fc9709a3	2415
AnnaBridge	189:f392fc9709a3	2416	/**
AnnaBridge	189:f392fc9709a3	2417	* @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2418	* @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
AnnaBridge	189:f392fc9709a3	2419	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2420	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2421	*/
AnnaBridge	189:f392fc9709a3	2422	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2423	{
AnnaBridge	189:f392fc9709a3	2424	return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE));
AnnaBridge	189:f392fc9709a3	2425	}
AnnaBridge	189:f392fc9709a3	2426	#else
AnnaBridge	189:f392fc9709a3	2427
AnnaBridge	189:f392fc9709a3	2428	/**
AnnaBridge	189:f392fc9709a3	2429	* @brief Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2430	* @rmtoll CR1 RXNEIE LL_LPUART_IsEnabledIT_RXNE
AnnaBridge	189:f392fc9709a3	2431	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2432	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2433	*/
AnnaBridge	189:f392fc9709a3	2434	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2435	{
AnnaBridge	189:f392fc9709a3	2436	return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
AnnaBridge	189:f392fc9709a3	2437	}
AnnaBridge	189:f392fc9709a3	2438	#endif
AnnaBridge	189:f392fc9709a3	2439
AnnaBridge	189:f392fc9709a3	2440	/**
AnnaBridge	189:f392fc9709a3	2441	* @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2442	* @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
AnnaBridge	189:f392fc9709a3	2443	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2444	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2445	*/
AnnaBridge	189:f392fc9709a3	2446	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2447	{
AnnaBridge	189:f392fc9709a3	2448	return (READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
AnnaBridge	189:f392fc9709a3	2449	}
AnnaBridge	189:f392fc9709a3	2450
AnnaBridge	189:f392fc9709a3	2451	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	2452
AnnaBridge	189:f392fc9709a3	2453	/* Legacy define */
AnnaBridge	189:f392fc9709a3	2454	#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF
AnnaBridge	189:f392fc9709a3	2455
AnnaBridge	189:f392fc9709a3	2456	/**
AnnaBridge	189:f392fc9709a3	2457	* @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
AnnaBridge	189:f392fc9709a3	2458	* @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
AnnaBridge	189:f392fc9709a3	2459	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2460	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2461	*/
AnnaBridge	189:f392fc9709a3	2462	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2463	{
AnnaBridge	189:f392fc9709a3	2464	return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE));
AnnaBridge	189:f392fc9709a3	2465	}
AnnaBridge	189:f392fc9709a3	2466	#else
AnnaBridge	189:f392fc9709a3	2467
AnnaBridge	189:f392fc9709a3	2468	/**
AnnaBridge	189:f392fc9709a3	2469	* @brief Check if the LPUART TX Empty Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2470	* @rmtoll CR1 TXEIE LL_LPUART_IsEnabledIT_TXE
AnnaBridge	189:f392fc9709a3	2471	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2472	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2473	*/
AnnaBridge	189:f392fc9709a3	2474	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2475	{
AnnaBridge	189:f392fc9709a3	2476	return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
AnnaBridge	189:f392fc9709a3	2477	}
AnnaBridge	189:f392fc9709a3	2478	#endif
AnnaBridge	189:f392fc9709a3	2479
AnnaBridge	189:f392fc9709a3	2480	/**
AnnaBridge	189:f392fc9709a3	2481	* @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2482	* @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
AnnaBridge	189:f392fc9709a3	2483	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2484	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2485	*/
AnnaBridge	189:f392fc9709a3	2486	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2487	{
AnnaBridge	189:f392fc9709a3	2488	return (READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
AnnaBridge	189:f392fc9709a3	2489	}
AnnaBridge	189:f392fc9709a3	2490
AnnaBridge	189:f392fc9709a3	2491	/**
AnnaBridge	189:f392fc9709a3	2492	* @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2493	* @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
AnnaBridge	189:f392fc9709a3	2494	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2495	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2496	*/
AnnaBridge	189:f392fc9709a3	2497	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2498	{
AnnaBridge	189:f392fc9709a3	2499	return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
AnnaBridge	189:f392fc9709a3	2500	}
AnnaBridge	189:f392fc9709a3	2501	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	2502
AnnaBridge	189:f392fc9709a3	2503	/**
AnnaBridge	189:f392fc9709a3	2504	* @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
AnnaBridge	189:f392fc9709a3	2505	* @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
AnnaBridge	189:f392fc9709a3	2506	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2507	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2508	*/
AnnaBridge	189:f392fc9709a3	2509	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2510	{
AnnaBridge	189:f392fc9709a3	2511	return (READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE));
AnnaBridge	189:f392fc9709a3	2512	}
AnnaBridge	189:f392fc9709a3	2513
AnnaBridge	189:f392fc9709a3	2514	/**
AnnaBridge	189:f392fc9709a3	2515	* @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
AnnaBridge	189:f392fc9709a3	2516	* @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
AnnaBridge	189:f392fc9709a3	2517	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2518	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2519	*/
AnnaBridge	189:f392fc9709a3	2520	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2521	{
AnnaBridge	189:f392fc9709a3	2522	return (READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE));
AnnaBridge	189:f392fc9709a3	2523	}
AnnaBridge	189:f392fc9709a3	2524	#endif
AnnaBridge	189:f392fc9709a3	2525
AnnaBridge	189:f392fc9709a3	2526	/**
AnnaBridge	189:f392fc9709a3	2527	* @brief Check if the LPUART Error Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2528	* @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
AnnaBridge	189:f392fc9709a3	2529	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2530	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2531	*/
AnnaBridge	189:f392fc9709a3	2532	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2533	{
AnnaBridge	189:f392fc9709a3	2534	return (READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
AnnaBridge	189:f392fc9709a3	2535	}
AnnaBridge	189:f392fc9709a3	2536
AnnaBridge	189:f392fc9709a3	2537	/**
AnnaBridge	189:f392fc9709a3	2538	* @brief Check if the LPUART CTS Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2539	* @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
AnnaBridge	189:f392fc9709a3	2540	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2541	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2542	*/
AnnaBridge	189:f392fc9709a3	2543	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2544	{
AnnaBridge	189:f392fc9709a3	2545	return (READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
AnnaBridge	189:f392fc9709a3	2546	}
AnnaBridge	189:f392fc9709a3	2547
AnnaBridge	189:f392fc9709a3	2548	/**
AnnaBridge	189:f392fc9709a3	2549	* @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2550	* @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
AnnaBridge	189:f392fc9709a3	2551	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2552	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2553	*/
AnnaBridge	189:f392fc9709a3	2554	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2555	{
AnnaBridge	189:f392fc9709a3	2556	return (READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
AnnaBridge	189:f392fc9709a3	2557	}
AnnaBridge	189:f392fc9709a3	2558
AnnaBridge	189:f392fc9709a3	2559	#if defined(USART_CR1_FIFOEN)
AnnaBridge	189:f392fc9709a3	2560
AnnaBridge	189:f392fc9709a3	2561	/**
AnnaBridge	189:f392fc9709a3	2562	* @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
AnnaBridge	189:f392fc9709a3	2563	* @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
AnnaBridge	189:f392fc9709a3	2564	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2565	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2566	*/
AnnaBridge	189:f392fc9709a3	2567	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2568	{
AnnaBridge	189:f392fc9709a3	2569	return (READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE));
AnnaBridge	189:f392fc9709a3	2570	}
AnnaBridge	189:f392fc9709a3	2571
AnnaBridge	189:f392fc9709a3	2572	/**
AnnaBridge	189:f392fc9709a3	2573	* @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
AnnaBridge	189:f392fc9709a3	2574	* @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
AnnaBridge	189:f392fc9709a3	2575	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2576	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2577	*/
AnnaBridge	189:f392fc9709a3	2578	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2579	{
AnnaBridge	189:f392fc9709a3	2580	return (READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE));
AnnaBridge	189:f392fc9709a3	2581	}
AnnaBridge	189:f392fc9709a3	2582	#endif
AnnaBridge	189:f392fc9709a3	2583
AnnaBridge	189:f392fc9709a3	2584	/**
AnnaBridge	189:f392fc9709a3	2585	* @}
AnnaBridge	189:f392fc9709a3	2586	*/
AnnaBridge	189:f392fc9709a3	2587
AnnaBridge	189:f392fc9709a3	2588	/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
AnnaBridge	189:f392fc9709a3	2589	* @{
AnnaBridge	189:f392fc9709a3	2590	*/
AnnaBridge	189:f392fc9709a3	2591
AnnaBridge	189:f392fc9709a3	2592	/**
AnnaBridge	189:f392fc9709a3	2593	* @brief Enable DMA Mode for reception
AnnaBridge	189:f392fc9709a3	2594	* @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
AnnaBridge	189:f392fc9709a3	2595	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2596	* @retval None
AnnaBridge	189:f392fc9709a3	2597	*/
AnnaBridge	189:f392fc9709a3	2598	__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2599	{
AnnaBridge	189:f392fc9709a3	2600	SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
AnnaBridge	189:f392fc9709a3	2601	}
AnnaBridge	189:f392fc9709a3	2602
AnnaBridge	189:f392fc9709a3	2603	/**
AnnaBridge	189:f392fc9709a3	2604	* @brief Disable DMA Mode for reception
AnnaBridge	189:f392fc9709a3	2605	* @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
AnnaBridge	189:f392fc9709a3	2606	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2607	* @retval None
AnnaBridge	189:f392fc9709a3	2608	*/
AnnaBridge	189:f392fc9709a3	2609	__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2610	{
AnnaBridge	189:f392fc9709a3	2611	CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
AnnaBridge	189:f392fc9709a3	2612	}
AnnaBridge	189:f392fc9709a3	2613
AnnaBridge	189:f392fc9709a3	2614	/**
AnnaBridge	189:f392fc9709a3	2615	* @brief Check if DMA Mode is enabled for reception
AnnaBridge	189:f392fc9709a3	2616	* @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
AnnaBridge	189:f392fc9709a3	2617	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2618	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2619	*/
AnnaBridge	189:f392fc9709a3	2620	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2621	{
AnnaBridge	189:f392fc9709a3	2622	return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
AnnaBridge	189:f392fc9709a3	2623	}
AnnaBridge	189:f392fc9709a3	2624
AnnaBridge	189:f392fc9709a3	2625	/**
AnnaBridge	189:f392fc9709a3	2626	* @brief Enable DMA Mode for transmission
AnnaBridge	189:f392fc9709a3	2627	* @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
AnnaBridge	189:f392fc9709a3	2628	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2629	* @retval None
AnnaBridge	189:f392fc9709a3	2630	*/
AnnaBridge	189:f392fc9709a3	2631	__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2632	{
AnnaBridge	189:f392fc9709a3	2633	SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
AnnaBridge	189:f392fc9709a3	2634	}
AnnaBridge	189:f392fc9709a3	2635
AnnaBridge	189:f392fc9709a3	2636	/**
AnnaBridge	189:f392fc9709a3	2637	* @brief Disable DMA Mode for transmission
AnnaBridge	189:f392fc9709a3	2638	* @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
AnnaBridge	189:f392fc9709a3	2639	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2640	* @retval None
AnnaBridge	189:f392fc9709a3	2641	*/
AnnaBridge	189:f392fc9709a3	2642	__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2643	{
AnnaBridge	189:f392fc9709a3	2644	CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
AnnaBridge	189:f392fc9709a3	2645	}
AnnaBridge	189:f392fc9709a3	2646
AnnaBridge	189:f392fc9709a3	2647	/**
AnnaBridge	189:f392fc9709a3	2648	* @brief Check if DMA Mode is enabled for transmission
AnnaBridge	189:f392fc9709a3	2649	* @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
AnnaBridge	189:f392fc9709a3	2650	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2651	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2652	*/
AnnaBridge	189:f392fc9709a3	2653	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2654	{
AnnaBridge	189:f392fc9709a3	2655	return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
AnnaBridge	189:f392fc9709a3	2656	}
AnnaBridge	189:f392fc9709a3	2657
AnnaBridge	189:f392fc9709a3	2658	/**
AnnaBridge	189:f392fc9709a3	2659	* @brief Enable DMA Disabling on Reception Error
AnnaBridge	189:f392fc9709a3	2660	* @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
AnnaBridge	189:f392fc9709a3	2661	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2662	* @retval None
AnnaBridge	189:f392fc9709a3	2663	*/
AnnaBridge	189:f392fc9709a3	2664	__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2665	{
AnnaBridge	189:f392fc9709a3	2666	SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
AnnaBridge	189:f392fc9709a3	2667	}
AnnaBridge	189:f392fc9709a3	2668
AnnaBridge	189:f392fc9709a3	2669	/**
AnnaBridge	189:f392fc9709a3	2670	* @brief Disable DMA Disabling on Reception Error
AnnaBridge	189:f392fc9709a3	2671	* @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
AnnaBridge	189:f392fc9709a3	2672	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2673	* @retval None
AnnaBridge	189:f392fc9709a3	2674	*/
AnnaBridge	189:f392fc9709a3	2675	__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2676	{
AnnaBridge	189:f392fc9709a3	2677	CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
AnnaBridge	189:f392fc9709a3	2678	}
AnnaBridge	189:f392fc9709a3	2679
AnnaBridge	189:f392fc9709a3	2680	/**
AnnaBridge	189:f392fc9709a3	2681	* @brief Indicate if DMA Disabling on Reception Error is disabled
AnnaBridge	189:f392fc9709a3	2682	* @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
AnnaBridge	189:f392fc9709a3	2683	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2684	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2685	*/
AnnaBridge	189:f392fc9709a3	2686	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2687	{
AnnaBridge	189:f392fc9709a3	2688	return (READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
AnnaBridge	189:f392fc9709a3	2689	}
AnnaBridge	189:f392fc9709a3	2690
AnnaBridge	189:f392fc9709a3	2691	/**
AnnaBridge	189:f392fc9709a3	2692	* @brief Get the LPUART data register address used for DMA transfer
AnnaBridge	189:f392fc9709a3	2693	* @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
AnnaBridge	189:f392fc9709a3	2694	* @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
AnnaBridge	189:f392fc9709a3	2695	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2696	* @param Direction This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2697	* @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
AnnaBridge	189:f392fc9709a3	2698	* @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
AnnaBridge	189:f392fc9709a3	2699	* @retval Address of data register
AnnaBridge	189:f392fc9709a3	2700	*/
AnnaBridge	189:f392fc9709a3	2701	__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
AnnaBridge	189:f392fc9709a3	2702	{
AnnaBridge	189:f392fc9709a3	2703	register uint32_t data_reg_addr = 0U;
AnnaBridge	189:f392fc9709a3	2704
AnnaBridge	189:f392fc9709a3	2705	if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
AnnaBridge	189:f392fc9709a3	2706	{
AnnaBridge	189:f392fc9709a3	2707	/* return address of TDR register */
AnnaBridge	189:f392fc9709a3	2708	data_reg_addr = (uint32_t) &(LPUARTx->TDR);
AnnaBridge	189:f392fc9709a3	2709	}
AnnaBridge	189:f392fc9709a3	2710	else
AnnaBridge	189:f392fc9709a3	2711	{
AnnaBridge	189:f392fc9709a3	2712	/* return address of RDR register */
AnnaBridge	189:f392fc9709a3	2713	data_reg_addr = (uint32_t) &(LPUARTx->RDR);
AnnaBridge	189:f392fc9709a3	2714	}
AnnaBridge	189:f392fc9709a3	2715
AnnaBridge	189:f392fc9709a3	2716	return data_reg_addr;
AnnaBridge	189:f392fc9709a3	2717	}
AnnaBridge	189:f392fc9709a3	2718
AnnaBridge	189:f392fc9709a3	2719	/**
AnnaBridge	189:f392fc9709a3	2720	* @}
AnnaBridge	189:f392fc9709a3	2721	*/
AnnaBridge	189:f392fc9709a3	2722
AnnaBridge	189:f392fc9709a3	2723	/** @defgroup LPUART_LL_EF_Data_Management Data_Management
AnnaBridge	189:f392fc9709a3	2724	* @{
AnnaBridge	189:f392fc9709a3	2725	*/
AnnaBridge	189:f392fc9709a3	2726
AnnaBridge	189:f392fc9709a3	2727	/**
AnnaBridge	189:f392fc9709a3	2728	* @brief Read Receiver Data register (Receive Data value, 8 bits)
AnnaBridge	189:f392fc9709a3	2729	* @rmtoll RDR RDR LL_LPUART_ReceiveData8
AnnaBridge	189:f392fc9709a3	2730	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2731	* @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	2732	*/
AnnaBridge	189:f392fc9709a3	2733	__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2734	{
AnnaBridge	189:f392fc9709a3	2735	return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
AnnaBridge	189:f392fc9709a3	2736	}
AnnaBridge	189:f392fc9709a3	2737
AnnaBridge	189:f392fc9709a3	2738	/**
AnnaBridge	189:f392fc9709a3	2739	* @brief Read Receiver Data register (Receive Data value, 9 bits)
AnnaBridge	189:f392fc9709a3	2740	* @rmtoll RDR RDR LL_LPUART_ReceiveData9
AnnaBridge	189:f392fc9709a3	2741	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2742	* @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
AnnaBridge	189:f392fc9709a3	2743	*/
AnnaBridge	189:f392fc9709a3	2744	__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2745	{
AnnaBridge	189:f392fc9709a3	2746	return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
AnnaBridge	189:f392fc9709a3	2747	}
AnnaBridge	189:f392fc9709a3	2748
AnnaBridge	189:f392fc9709a3	2749	/**
AnnaBridge	189:f392fc9709a3	2750	* @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
AnnaBridge	189:f392fc9709a3	2751	* @rmtoll TDR TDR LL_LPUART_TransmitData8
AnnaBridge	189:f392fc9709a3	2752	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2753	* @param Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	2754	* @retval None
AnnaBridge	189:f392fc9709a3	2755	*/
AnnaBridge	189:f392fc9709a3	2756	__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
AnnaBridge	189:f392fc9709a3	2757	{
AnnaBridge	189:f392fc9709a3	2758	LPUARTx->TDR = Value;
AnnaBridge	189:f392fc9709a3	2759	}
AnnaBridge	189:f392fc9709a3	2760
AnnaBridge	189:f392fc9709a3	2761	/**
AnnaBridge	189:f392fc9709a3	2762	* @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
AnnaBridge	189:f392fc9709a3	2763	* @rmtoll TDR TDR LL_LPUART_TransmitData9
AnnaBridge	189:f392fc9709a3	2764	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2765	* @param Value between Min_Data=0x00 and Max_Data=0x1FF
AnnaBridge	189:f392fc9709a3	2766	* @retval None
AnnaBridge	189:f392fc9709a3	2767	*/
AnnaBridge	189:f392fc9709a3	2768	__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
AnnaBridge	189:f392fc9709a3	2769	{
AnnaBridge	189:f392fc9709a3	2770	LPUARTx->TDR = Value & 0x1FFU;
AnnaBridge	189:f392fc9709a3	2771	}
AnnaBridge	189:f392fc9709a3	2772
AnnaBridge	189:f392fc9709a3	2773	/**
AnnaBridge	189:f392fc9709a3	2774	* @}
AnnaBridge	189:f392fc9709a3	2775	*/
AnnaBridge	189:f392fc9709a3	2776
AnnaBridge	189:f392fc9709a3	2777	/** @defgroup LPUART_LL_EF_Execution Execution
AnnaBridge	189:f392fc9709a3	2778	* @{
AnnaBridge	189:f392fc9709a3	2779	*/
AnnaBridge	189:f392fc9709a3	2780
AnnaBridge	189:f392fc9709a3	2781	/**
AnnaBridge	189:f392fc9709a3	2782	* @brief Request Break sending
AnnaBridge	189:f392fc9709a3	2783	* @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
AnnaBridge	189:f392fc9709a3	2784	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2785	* @retval None
AnnaBridge	189:f392fc9709a3	2786	*/
AnnaBridge	189:f392fc9709a3	2787	__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2788	{
AnnaBridge	189:f392fc9709a3	2789	SET_BIT(LPUARTx->RQR, USART_RQR_SBKRQ);
AnnaBridge	189:f392fc9709a3	2790	}
AnnaBridge	189:f392fc9709a3	2791
AnnaBridge	189:f392fc9709a3	2792	/**
AnnaBridge	189:f392fc9709a3	2793	* @brief Put LPUART in mute mode and set the RWU flag
AnnaBridge	189:f392fc9709a3	2794	* @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
AnnaBridge	189:f392fc9709a3	2795	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2796	* @retval None
AnnaBridge	189:f392fc9709a3	2797	*/
AnnaBridge	189:f392fc9709a3	2798	__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2799	{
AnnaBridge	189:f392fc9709a3	2800	SET_BIT(LPUARTx->RQR, USART_RQR_MMRQ);
AnnaBridge	189:f392fc9709a3	2801	}
AnnaBridge	189:f392fc9709a3	2802
AnnaBridge	189:f392fc9709a3	2803	/**
AnnaBridge	189:f392fc9709a3	2804	@if USART_CR1_FIFOEN
AnnaBridge	189:f392fc9709a3	2805	* @brief Request a Receive Data and FIFO flush
AnnaBridge	189:f392fc9709a3	2806	* @note Allows to discard the received data without reading them, and avoid an overrun
AnnaBridge	189:f392fc9709a3	2807	* condition.
AnnaBridge	189:f392fc9709a3	2808	@else
AnnaBridge	189:f392fc9709a3	2809	* @brief Request a Receive Data flush
AnnaBridge	189:f392fc9709a3	2810	@endif
AnnaBridge	189:f392fc9709a3	2811	* @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
AnnaBridge	189:f392fc9709a3	2812	* @param LPUARTx LPUART Instance
AnnaBridge	189:f392fc9709a3	2813	* @retval None
AnnaBridge	189:f392fc9709a3	2814	*/
AnnaBridge	189:f392fc9709a3	2815	__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
AnnaBridge	189:f392fc9709a3	2816	{
AnnaBridge	189:f392fc9709a3	2817	SET_BIT(LPUARTx->RQR, USART_RQR_RXFRQ);
AnnaBridge	189:f392fc9709a3	2818	}
AnnaBridge	189:f392fc9709a3	2819
AnnaBridge	189:f392fc9709a3	2820	/**
AnnaBridge	189:f392fc9709a3	2821	* @}
AnnaBridge	189:f392fc9709a3	2822	*/
AnnaBridge	189:f392fc9709a3	2823
AnnaBridge	189:f392fc9709a3	2824	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	2825	/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	189:f392fc9709a3	2826	* @{
AnnaBridge	189:f392fc9709a3	2827	*/
AnnaBridge	189:f392fc9709a3	2828	ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
AnnaBridge	189:f392fc9709a3	2829	ErrorStatus LL_LPUART_Init(USART_TypeDef LPUARTx, LL_LPUART_InitTypeDef LPUART_InitStruct);
AnnaBridge	189:f392fc9709a3	2830	void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
AnnaBridge	189:f392fc9709a3	2831	/**
AnnaBridge	189:f392fc9709a3	2832	* @}
AnnaBridge	189:f392fc9709a3	2833	*/
AnnaBridge	189:f392fc9709a3	2834	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	2835
AnnaBridge	189:f392fc9709a3	2836	/**
AnnaBridge	189:f392fc9709a3	2837	* @}
AnnaBridge	189:f392fc9709a3	2838	*/
AnnaBridge	189:f392fc9709a3	2839
AnnaBridge	189:f392fc9709a3	2840	/**
AnnaBridge	189:f392fc9709a3	2841	* @}
AnnaBridge	189:f392fc9709a3	2842	*/
AnnaBridge	189:f392fc9709a3	2843
AnnaBridge	189:f392fc9709a3	2844	#endif /* LPUART1 */
AnnaBridge	189:f392fc9709a3	2845
AnnaBridge	189:f392fc9709a3	2846	/**
AnnaBridge	189:f392fc9709a3	2847	* @}
AnnaBridge	189:f392fc9709a3	2848	*/
AnnaBridge	189:f392fc9709a3	2849
AnnaBridge	189:f392fc9709a3	2850	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	2851	}
AnnaBridge	189:f392fc9709a3	2852	#endif
AnnaBridge	189:f392fc9709a3	2853
AnnaBridge	189:f392fc9709a3	2854	#endif /* __STM32L4xx_LL_LPUART_H */
AnnaBridge	189:f392fc9709a3	2855
AnnaBridge	189:f392fc9709a3	2856	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/