mbed official
mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_ARM_STD/stm32l4xx_ll_crs.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_ll_crs.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of CRS LL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_LL_CRS_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_LL_CRS_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l4xx.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32L4xx_LL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | #if defined(CRS) |
| AnnaBridge | 189:f392fc9709a3 | 52 | |
| AnnaBridge | 189:f392fc9709a3 | 53 | /** @defgroup CRS_LL CRS |
| AnnaBridge | 189:f392fc9709a3 | 54 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 55 | */ |
| AnnaBridge | 189:f392fc9709a3 | 56 | |
| AnnaBridge | 189:f392fc9709a3 | 57 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 58 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 59 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 60 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 61 | |
| AnnaBridge | 189:f392fc9709a3 | 62 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 63 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 64 | /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 65 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 66 | */ |
| AnnaBridge | 189:f392fc9709a3 | 67 | |
| AnnaBridge | 189:f392fc9709a3 | 68 | /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines |
| AnnaBridge | 189:f392fc9709a3 | 69 | * @brief Flags defines which can be used with LL_CRS_ReadReg function |
| AnnaBridge | 189:f392fc9709a3 | 70 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 71 | */ |
| AnnaBridge | 189:f392fc9709a3 | 72 | #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF |
| AnnaBridge | 189:f392fc9709a3 | 73 | #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF |
| AnnaBridge | 189:f392fc9709a3 | 74 | #define LL_CRS_ISR_ERRF CRS_ISR_ERRF |
| AnnaBridge | 189:f392fc9709a3 | 75 | #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF |
| AnnaBridge | 189:f392fc9709a3 | 76 | #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR |
| AnnaBridge | 189:f392fc9709a3 | 77 | #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS |
| AnnaBridge | 189:f392fc9709a3 | 78 | #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF |
| AnnaBridge | 189:f392fc9709a3 | 79 | /** |
| AnnaBridge | 189:f392fc9709a3 | 80 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 81 | */ |
| AnnaBridge | 189:f392fc9709a3 | 82 | |
| AnnaBridge | 189:f392fc9709a3 | 83 | /** @defgroup CRS_LL_EC_IT IT Defines |
| AnnaBridge | 189:f392fc9709a3 | 84 | * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions |
| AnnaBridge | 189:f392fc9709a3 | 85 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 86 | */ |
| AnnaBridge | 189:f392fc9709a3 | 87 | #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE |
| AnnaBridge | 189:f392fc9709a3 | 88 | #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE |
| AnnaBridge | 189:f392fc9709a3 | 89 | #define LL_CRS_CR_ERRIE CRS_CR_ERRIE |
| AnnaBridge | 189:f392fc9709a3 | 90 | #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE |
| AnnaBridge | 189:f392fc9709a3 | 91 | /** |
| AnnaBridge | 189:f392fc9709a3 | 92 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 93 | */ |
| AnnaBridge | 189:f392fc9709a3 | 94 | |
| AnnaBridge | 189:f392fc9709a3 | 95 | /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider |
| AnnaBridge | 189:f392fc9709a3 | 96 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 97 | */ |
| AnnaBridge | 189:f392fc9709a3 | 98 | #define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */ |
| AnnaBridge | 189:f392fc9709a3 | 99 | #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 100 | #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ |
| AnnaBridge | 189:f392fc9709a3 | 101 | #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ |
| AnnaBridge | 189:f392fc9709a3 | 102 | #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ |
| AnnaBridge | 189:f392fc9709a3 | 103 | #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ |
| AnnaBridge | 189:f392fc9709a3 | 104 | #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ |
| AnnaBridge | 189:f392fc9709a3 | 105 | #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ |
| AnnaBridge | 189:f392fc9709a3 | 106 | /** |
| AnnaBridge | 189:f392fc9709a3 | 107 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 108 | */ |
| AnnaBridge | 189:f392fc9709a3 | 109 | |
| AnnaBridge | 189:f392fc9709a3 | 110 | /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source |
| AnnaBridge | 189:f392fc9709a3 | 111 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 112 | */ |
| AnnaBridge | 189:f392fc9709a3 | 113 | #define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 114 | #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ |
| AnnaBridge | 189:f392fc9709a3 | 115 | #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ |
| AnnaBridge | 189:f392fc9709a3 | 116 | /** |
| AnnaBridge | 189:f392fc9709a3 | 117 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 118 | */ |
| AnnaBridge | 189:f392fc9709a3 | 119 | |
| AnnaBridge | 189:f392fc9709a3 | 120 | /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity |
| AnnaBridge | 189:f392fc9709a3 | 121 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 122 | */ |
| AnnaBridge | 189:f392fc9709a3 | 123 | #define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */ |
| AnnaBridge | 189:f392fc9709a3 | 124 | #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ |
| AnnaBridge | 189:f392fc9709a3 | 125 | /** |
| AnnaBridge | 189:f392fc9709a3 | 126 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 127 | */ |
| AnnaBridge | 189:f392fc9709a3 | 128 | |
| AnnaBridge | 189:f392fc9709a3 | 129 | /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction |
| AnnaBridge | 189:f392fc9709a3 | 130 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 131 | */ |
| AnnaBridge | 189:f392fc9709a3 | 132 | #define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */ |
| AnnaBridge | 189:f392fc9709a3 | 133 | #define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ |
| AnnaBridge | 189:f392fc9709a3 | 134 | /** |
| AnnaBridge | 189:f392fc9709a3 | 135 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 136 | */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | |
| AnnaBridge | 189:f392fc9709a3 | 138 | /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values |
| AnnaBridge | 189:f392fc9709a3 | 139 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 140 | */ |
| AnnaBridge | 189:f392fc9709a3 | 141 | /** |
| AnnaBridge | 189:f392fc9709a3 | 142 | * @brief Reset value of the RELOAD field |
| AnnaBridge | 189:f392fc9709a3 | 143 | * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz |
| AnnaBridge | 189:f392fc9709a3 | 144 | * and a synchronization signal frequency of 1 kHz (SOF signal from USB) |
| AnnaBridge | 189:f392fc9709a3 | 145 | */ |
| AnnaBridge | 189:f392fc9709a3 | 146 | #define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) |
| AnnaBridge | 189:f392fc9709a3 | 147 | |
| AnnaBridge | 189:f392fc9709a3 | 148 | /** |
| AnnaBridge | 189:f392fc9709a3 | 149 | * @brief Reset value of Frequency error limit. |
| AnnaBridge | 189:f392fc9709a3 | 150 | */ |
| AnnaBridge | 189:f392fc9709a3 | 151 | #define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) |
| AnnaBridge | 189:f392fc9709a3 | 152 | |
| AnnaBridge | 189:f392fc9709a3 | 153 | /** |
| AnnaBridge | 189:f392fc9709a3 | 154 | * @brief Reset value of the HSI48 Calibration field |
| AnnaBridge | 189:f392fc9709a3 | 155 | * @note The default value is 32, which corresponds to the middle of the trimming interval. |
| AnnaBridge | 189:f392fc9709a3 | 156 | * The trimming step is around 67 kHz between two consecutive TRIM steps. |
| AnnaBridge | 189:f392fc9709a3 | 157 | * A higher TRIM value corresponds to a higher output frequency |
| AnnaBridge | 189:f392fc9709a3 | 158 | */ |
| AnnaBridge | 189:f392fc9709a3 | 159 | #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U) |
| AnnaBridge | 189:f392fc9709a3 | 160 | /** |
| AnnaBridge | 189:f392fc9709a3 | 161 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 162 | */ |
| AnnaBridge | 189:f392fc9709a3 | 163 | |
| AnnaBridge | 189:f392fc9709a3 | 164 | /** |
| AnnaBridge | 189:f392fc9709a3 | 165 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 166 | */ |
| AnnaBridge | 189:f392fc9709a3 | 167 | |
| AnnaBridge | 189:f392fc9709a3 | 168 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 169 | /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 170 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 171 | */ |
| AnnaBridge | 189:f392fc9709a3 | 172 | |
| AnnaBridge | 189:f392fc9709a3 | 173 | /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros |
| AnnaBridge | 189:f392fc9709a3 | 174 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 175 | */ |
| AnnaBridge | 189:f392fc9709a3 | 176 | |
| AnnaBridge | 189:f392fc9709a3 | 177 | /** |
| AnnaBridge | 189:f392fc9709a3 | 178 | * @brief Write a value in CRS register |
| AnnaBridge | 189:f392fc9709a3 | 179 | * @param __INSTANCE__ CRS Instance |
| AnnaBridge | 189:f392fc9709a3 | 180 | * @param __REG__ Register to be written |
| AnnaBridge | 189:f392fc9709a3 | 181 | * @param __VALUE__ Value to be written in the register |
| AnnaBridge | 189:f392fc9709a3 | 182 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 183 | */ |
| AnnaBridge | 189:f392fc9709a3 | 184 | #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
| AnnaBridge | 189:f392fc9709a3 | 185 | |
| AnnaBridge | 189:f392fc9709a3 | 186 | /** |
| AnnaBridge | 189:f392fc9709a3 | 187 | * @brief Read a value in CRS register |
| AnnaBridge | 189:f392fc9709a3 | 188 | * @param __INSTANCE__ CRS Instance |
| AnnaBridge | 189:f392fc9709a3 | 189 | * @param __REG__ Register to be read |
| AnnaBridge | 189:f392fc9709a3 | 190 | * @retval Register value |
| AnnaBridge | 189:f392fc9709a3 | 191 | */ |
| AnnaBridge | 189:f392fc9709a3 | 192 | #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
| AnnaBridge | 189:f392fc9709a3 | 193 | /** |
| AnnaBridge | 189:f392fc9709a3 | 194 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 195 | */ |
| AnnaBridge | 189:f392fc9709a3 | 196 | |
| AnnaBridge | 189:f392fc9709a3 | 197 | /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload |
| AnnaBridge | 189:f392fc9709a3 | 198 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 199 | */ |
| AnnaBridge | 189:f392fc9709a3 | 200 | |
| AnnaBridge | 189:f392fc9709a3 | 201 | /** |
| AnnaBridge | 189:f392fc9709a3 | 202 | * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies |
| AnnaBridge | 189:f392fc9709a3 | 203 | * @note The RELOAD value should be selected according to the ratio between |
| AnnaBridge | 189:f392fc9709a3 | 204 | * the target frequency and the frequency of the synchronization source after |
| AnnaBridge | 189:f392fc9709a3 | 205 | * prescaling. It is then decreased by one in order to reach the expected |
| AnnaBridge | 189:f392fc9709a3 | 206 | * synchronization on the zero value. The formula is the following: |
| AnnaBridge | 189:f392fc9709a3 | 207 | * RELOAD = (fTARGET / fSYNC) -1 |
| AnnaBridge | 189:f392fc9709a3 | 208 | * @param __FTARGET__ Target frequency (value in Hz) |
| AnnaBridge | 189:f392fc9709a3 | 209 | * @param __FSYNC__ Synchronization signal frequency (value in Hz) |
| AnnaBridge | 189:f392fc9709a3 | 210 | * @retval Reload value (in Hz) |
| AnnaBridge | 189:f392fc9709a3 | 211 | */ |
| AnnaBridge | 189:f392fc9709a3 | 212 | #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) |
| AnnaBridge | 189:f392fc9709a3 | 213 | |
| AnnaBridge | 189:f392fc9709a3 | 214 | /** |
| AnnaBridge | 189:f392fc9709a3 | 215 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 216 | */ |
| AnnaBridge | 189:f392fc9709a3 | 217 | |
| AnnaBridge | 189:f392fc9709a3 | 218 | /** |
| AnnaBridge | 189:f392fc9709a3 | 219 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 220 | */ |
| AnnaBridge | 189:f392fc9709a3 | 221 | |
| AnnaBridge | 189:f392fc9709a3 | 222 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 223 | /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 224 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 225 | */ |
| AnnaBridge | 189:f392fc9709a3 | 226 | |
| AnnaBridge | 189:f392fc9709a3 | 227 | /** @defgroup CRS_LL_EF_Configuration Configuration |
| AnnaBridge | 189:f392fc9709a3 | 228 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 229 | */ |
| AnnaBridge | 189:f392fc9709a3 | 230 | |
| AnnaBridge | 189:f392fc9709a3 | 231 | /** |
| AnnaBridge | 189:f392fc9709a3 | 232 | * @brief Enable Frequency error counter |
| AnnaBridge | 189:f392fc9709a3 | 233 | * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified |
| AnnaBridge | 189:f392fc9709a3 | 234 | * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter |
| AnnaBridge | 189:f392fc9709a3 | 235 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 236 | */ |
| AnnaBridge | 189:f392fc9709a3 | 237 | __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) |
| AnnaBridge | 189:f392fc9709a3 | 238 | { |
| AnnaBridge | 189:f392fc9709a3 | 239 | SET_BIT(CRS->CR, CRS_CR_CEN); |
| AnnaBridge | 189:f392fc9709a3 | 240 | } |
| AnnaBridge | 189:f392fc9709a3 | 241 | |
| AnnaBridge | 189:f392fc9709a3 | 242 | /** |
| AnnaBridge | 189:f392fc9709a3 | 243 | * @brief Disable Frequency error counter |
| AnnaBridge | 189:f392fc9709a3 | 244 | * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter |
| AnnaBridge | 189:f392fc9709a3 | 245 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 246 | */ |
| AnnaBridge | 189:f392fc9709a3 | 247 | __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) |
| AnnaBridge | 189:f392fc9709a3 | 248 | { |
| AnnaBridge | 189:f392fc9709a3 | 249 | CLEAR_BIT(CRS->CR, CRS_CR_CEN); |
| AnnaBridge | 189:f392fc9709a3 | 250 | } |
| AnnaBridge | 189:f392fc9709a3 | 251 | |
| AnnaBridge | 189:f392fc9709a3 | 252 | /** |
| AnnaBridge | 189:f392fc9709a3 | 253 | * @brief Check if Frequency error counter is enabled or not |
| AnnaBridge | 189:f392fc9709a3 | 254 | * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter |
| AnnaBridge | 189:f392fc9709a3 | 255 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 256 | */ |
| AnnaBridge | 189:f392fc9709a3 | 257 | __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) |
| AnnaBridge | 189:f392fc9709a3 | 258 | { |
| AnnaBridge | 189:f392fc9709a3 | 259 | return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)); |
| AnnaBridge | 189:f392fc9709a3 | 260 | } |
| AnnaBridge | 189:f392fc9709a3 | 261 | |
| AnnaBridge | 189:f392fc9709a3 | 262 | /** |
| AnnaBridge | 189:f392fc9709a3 | 263 | * @brief Enable Automatic trimming counter |
| AnnaBridge | 189:f392fc9709a3 | 264 | * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming |
| AnnaBridge | 189:f392fc9709a3 | 265 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 266 | */ |
| AnnaBridge | 189:f392fc9709a3 | 267 | __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) |
| AnnaBridge | 189:f392fc9709a3 | 268 | { |
| AnnaBridge | 189:f392fc9709a3 | 269 | SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); |
| AnnaBridge | 189:f392fc9709a3 | 270 | } |
| AnnaBridge | 189:f392fc9709a3 | 271 | |
| AnnaBridge | 189:f392fc9709a3 | 272 | /** |
| AnnaBridge | 189:f392fc9709a3 | 273 | * @brief Disable Automatic trimming counter |
| AnnaBridge | 189:f392fc9709a3 | 274 | * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming |
| AnnaBridge | 189:f392fc9709a3 | 275 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 276 | */ |
| AnnaBridge | 189:f392fc9709a3 | 277 | __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) |
| AnnaBridge | 189:f392fc9709a3 | 278 | { |
| AnnaBridge | 189:f392fc9709a3 | 279 | CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); |
| AnnaBridge | 189:f392fc9709a3 | 280 | } |
| AnnaBridge | 189:f392fc9709a3 | 281 | |
| AnnaBridge | 189:f392fc9709a3 | 282 | /** |
| AnnaBridge | 189:f392fc9709a3 | 283 | * @brief Check if Automatic trimming is enabled or not |
| AnnaBridge | 189:f392fc9709a3 | 284 | * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming |
| AnnaBridge | 189:f392fc9709a3 | 285 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 286 | */ |
| AnnaBridge | 189:f392fc9709a3 | 287 | __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) |
| AnnaBridge | 189:f392fc9709a3 | 288 | { |
| AnnaBridge | 189:f392fc9709a3 | 289 | return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)); |
| AnnaBridge | 189:f392fc9709a3 | 290 | } |
| AnnaBridge | 189:f392fc9709a3 | 291 | |
| AnnaBridge | 189:f392fc9709a3 | 292 | /** |
| AnnaBridge | 189:f392fc9709a3 | 293 | * @brief Set HSI48 oscillator smooth trimming |
| AnnaBridge | 189:f392fc9709a3 | 294 | * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only |
| AnnaBridge | 189:f392fc9709a3 | 295 | * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming |
| AnnaBridge | 189:f392fc9709a3 | 296 | * @param Value a number between Min_Data = 0 and Max_Data = 63 |
| AnnaBridge | 189:f392fc9709a3 | 297 | * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT |
| AnnaBridge | 189:f392fc9709a3 | 298 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 299 | */ |
| AnnaBridge | 189:f392fc9709a3 | 300 | __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) |
| AnnaBridge | 189:f392fc9709a3 | 301 | { |
| AnnaBridge | 189:f392fc9709a3 | 302 | MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); |
| AnnaBridge | 189:f392fc9709a3 | 303 | } |
| AnnaBridge | 189:f392fc9709a3 | 304 | |
| AnnaBridge | 189:f392fc9709a3 | 305 | /** |
| AnnaBridge | 189:f392fc9709a3 | 306 | * @brief Get HSI48 oscillator smooth trimming |
| AnnaBridge | 189:f392fc9709a3 | 307 | * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming |
| AnnaBridge | 189:f392fc9709a3 | 308 | * @retval a number between Min_Data = 0 and Max_Data = 63 |
| AnnaBridge | 189:f392fc9709a3 | 309 | */ |
| AnnaBridge | 189:f392fc9709a3 | 310 | __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) |
| AnnaBridge | 189:f392fc9709a3 | 311 | { |
| AnnaBridge | 189:f392fc9709a3 | 312 | return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); |
| AnnaBridge | 189:f392fc9709a3 | 313 | } |
| AnnaBridge | 189:f392fc9709a3 | 314 | |
| AnnaBridge | 189:f392fc9709a3 | 315 | /** |
| AnnaBridge | 189:f392fc9709a3 | 316 | * @brief Set counter reload value |
| AnnaBridge | 189:f392fc9709a3 | 317 | * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter |
| AnnaBridge | 189:f392fc9709a3 | 318 | * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF |
| AnnaBridge | 189:f392fc9709a3 | 319 | * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT |
| AnnaBridge | 189:f392fc9709a3 | 320 | * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) |
| AnnaBridge | 189:f392fc9709a3 | 321 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 322 | */ |
| AnnaBridge | 189:f392fc9709a3 | 323 | __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) |
| AnnaBridge | 189:f392fc9709a3 | 324 | { |
| AnnaBridge | 189:f392fc9709a3 | 325 | MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); |
| AnnaBridge | 189:f392fc9709a3 | 326 | } |
| AnnaBridge | 189:f392fc9709a3 | 327 | |
| AnnaBridge | 189:f392fc9709a3 | 328 | /** |
| AnnaBridge | 189:f392fc9709a3 | 329 | * @brief Get counter reload value |
| AnnaBridge | 189:f392fc9709a3 | 330 | * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter |
| AnnaBridge | 189:f392fc9709a3 | 331 | * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF |
| AnnaBridge | 189:f392fc9709a3 | 332 | */ |
| AnnaBridge | 189:f392fc9709a3 | 333 | __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) |
| AnnaBridge | 189:f392fc9709a3 | 334 | { |
| AnnaBridge | 189:f392fc9709a3 | 335 | return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); |
| AnnaBridge | 189:f392fc9709a3 | 336 | } |
| AnnaBridge | 189:f392fc9709a3 | 337 | |
| AnnaBridge | 189:f392fc9709a3 | 338 | /** |
| AnnaBridge | 189:f392fc9709a3 | 339 | * @brief Set frequency error limit |
| AnnaBridge | 189:f392fc9709a3 | 340 | * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit |
| AnnaBridge | 189:f392fc9709a3 | 341 | * @param Value a number between Min_Data = 0 and Max_Data = 255 |
| AnnaBridge | 189:f392fc9709a3 | 342 | * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT |
| AnnaBridge | 189:f392fc9709a3 | 343 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 344 | */ |
| AnnaBridge | 189:f392fc9709a3 | 345 | __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) |
| AnnaBridge | 189:f392fc9709a3 | 346 | { |
| AnnaBridge | 189:f392fc9709a3 | 347 | MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); |
| AnnaBridge | 189:f392fc9709a3 | 348 | } |
| AnnaBridge | 189:f392fc9709a3 | 349 | |
| AnnaBridge | 189:f392fc9709a3 | 350 | /** |
| AnnaBridge | 189:f392fc9709a3 | 351 | * @brief Get frequency error limit |
| AnnaBridge | 189:f392fc9709a3 | 352 | * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit |
| AnnaBridge | 189:f392fc9709a3 | 353 | * @retval A number between Min_Data = 0 and Max_Data = 255 |
| AnnaBridge | 189:f392fc9709a3 | 354 | */ |
| AnnaBridge | 189:f392fc9709a3 | 355 | __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) |
| AnnaBridge | 189:f392fc9709a3 | 356 | { |
| AnnaBridge | 189:f392fc9709a3 | 357 | return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); |
| AnnaBridge | 189:f392fc9709a3 | 358 | } |
| AnnaBridge | 189:f392fc9709a3 | 359 | |
| AnnaBridge | 189:f392fc9709a3 | 360 | /** |
| AnnaBridge | 189:f392fc9709a3 | 361 | * @brief Set division factor for SYNC signal |
| AnnaBridge | 189:f392fc9709a3 | 362 | * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider |
| AnnaBridge | 189:f392fc9709a3 | 363 | * @param Divider This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 364 | * @arg @ref LL_CRS_SYNC_DIV_1 |
| AnnaBridge | 189:f392fc9709a3 | 365 | * @arg @ref LL_CRS_SYNC_DIV_2 |
| AnnaBridge | 189:f392fc9709a3 | 366 | * @arg @ref LL_CRS_SYNC_DIV_4 |
| AnnaBridge | 189:f392fc9709a3 | 367 | * @arg @ref LL_CRS_SYNC_DIV_8 |
| AnnaBridge | 189:f392fc9709a3 | 368 | * @arg @ref LL_CRS_SYNC_DIV_16 |
| AnnaBridge | 189:f392fc9709a3 | 369 | * @arg @ref LL_CRS_SYNC_DIV_32 |
| AnnaBridge | 189:f392fc9709a3 | 370 | * @arg @ref LL_CRS_SYNC_DIV_64 |
| AnnaBridge | 189:f392fc9709a3 | 371 | * @arg @ref LL_CRS_SYNC_DIV_128 |
| AnnaBridge | 189:f392fc9709a3 | 372 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 373 | */ |
| AnnaBridge | 189:f392fc9709a3 | 374 | __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) |
| AnnaBridge | 189:f392fc9709a3 | 375 | { |
| AnnaBridge | 189:f392fc9709a3 | 376 | MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); |
| AnnaBridge | 189:f392fc9709a3 | 377 | } |
| AnnaBridge | 189:f392fc9709a3 | 378 | |
| AnnaBridge | 189:f392fc9709a3 | 379 | /** |
| AnnaBridge | 189:f392fc9709a3 | 380 | * @brief Get division factor for SYNC signal |
| AnnaBridge | 189:f392fc9709a3 | 381 | * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider |
| AnnaBridge | 189:f392fc9709a3 | 382 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 383 | * @arg @ref LL_CRS_SYNC_DIV_1 |
| AnnaBridge | 189:f392fc9709a3 | 384 | * @arg @ref LL_CRS_SYNC_DIV_2 |
| AnnaBridge | 189:f392fc9709a3 | 385 | * @arg @ref LL_CRS_SYNC_DIV_4 |
| AnnaBridge | 189:f392fc9709a3 | 386 | * @arg @ref LL_CRS_SYNC_DIV_8 |
| AnnaBridge | 189:f392fc9709a3 | 387 | * @arg @ref LL_CRS_SYNC_DIV_16 |
| AnnaBridge | 189:f392fc9709a3 | 388 | * @arg @ref LL_CRS_SYNC_DIV_32 |
| AnnaBridge | 189:f392fc9709a3 | 389 | * @arg @ref LL_CRS_SYNC_DIV_64 |
| AnnaBridge | 189:f392fc9709a3 | 390 | * @arg @ref LL_CRS_SYNC_DIV_128 |
| AnnaBridge | 189:f392fc9709a3 | 391 | */ |
| AnnaBridge | 189:f392fc9709a3 | 392 | __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) |
| AnnaBridge | 189:f392fc9709a3 | 393 | { |
| AnnaBridge | 189:f392fc9709a3 | 394 | return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); |
| AnnaBridge | 189:f392fc9709a3 | 395 | } |
| AnnaBridge | 189:f392fc9709a3 | 396 | |
| AnnaBridge | 189:f392fc9709a3 | 397 | /** |
| AnnaBridge | 189:f392fc9709a3 | 398 | * @brief Set SYNC signal source |
| AnnaBridge | 189:f392fc9709a3 | 399 | * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource |
| AnnaBridge | 189:f392fc9709a3 | 400 | * @param Source This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 401 | * @arg @ref LL_CRS_SYNC_SOURCE_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 402 | * @arg @ref LL_CRS_SYNC_SOURCE_LSE |
| AnnaBridge | 189:f392fc9709a3 | 403 | * @arg @ref LL_CRS_SYNC_SOURCE_USB |
| AnnaBridge | 189:f392fc9709a3 | 404 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 405 | */ |
| AnnaBridge | 189:f392fc9709a3 | 406 | __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) |
| AnnaBridge | 189:f392fc9709a3 | 407 | { |
| AnnaBridge | 189:f392fc9709a3 | 408 | MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); |
| AnnaBridge | 189:f392fc9709a3 | 409 | } |
| AnnaBridge | 189:f392fc9709a3 | 410 | |
| AnnaBridge | 189:f392fc9709a3 | 411 | /** |
| AnnaBridge | 189:f392fc9709a3 | 412 | * @brief Get SYNC signal source |
| AnnaBridge | 189:f392fc9709a3 | 413 | * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource |
| AnnaBridge | 189:f392fc9709a3 | 414 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 415 | * @arg @ref LL_CRS_SYNC_SOURCE_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 416 | * @arg @ref LL_CRS_SYNC_SOURCE_LSE |
| AnnaBridge | 189:f392fc9709a3 | 417 | * @arg @ref LL_CRS_SYNC_SOURCE_USB |
| AnnaBridge | 189:f392fc9709a3 | 418 | */ |
| AnnaBridge | 189:f392fc9709a3 | 419 | __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) |
| AnnaBridge | 189:f392fc9709a3 | 420 | { |
| AnnaBridge | 189:f392fc9709a3 | 421 | return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); |
| AnnaBridge | 189:f392fc9709a3 | 422 | } |
| AnnaBridge | 189:f392fc9709a3 | 423 | |
| AnnaBridge | 189:f392fc9709a3 | 424 | /** |
| AnnaBridge | 189:f392fc9709a3 | 425 | * @brief Set input polarity for the SYNC signal source |
| AnnaBridge | 189:f392fc9709a3 | 426 | * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity |
| AnnaBridge | 189:f392fc9709a3 | 427 | * @param Polarity This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 428 | * @arg @ref LL_CRS_SYNC_POLARITY_RISING |
| AnnaBridge | 189:f392fc9709a3 | 429 | * @arg @ref LL_CRS_SYNC_POLARITY_FALLING |
| AnnaBridge | 189:f392fc9709a3 | 430 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 431 | */ |
| AnnaBridge | 189:f392fc9709a3 | 432 | __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) |
| AnnaBridge | 189:f392fc9709a3 | 433 | { |
| AnnaBridge | 189:f392fc9709a3 | 434 | MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); |
| AnnaBridge | 189:f392fc9709a3 | 435 | } |
| AnnaBridge | 189:f392fc9709a3 | 436 | |
| AnnaBridge | 189:f392fc9709a3 | 437 | /** |
| AnnaBridge | 189:f392fc9709a3 | 438 | * @brief Get input polarity for the SYNC signal source |
| AnnaBridge | 189:f392fc9709a3 | 439 | * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity |
| AnnaBridge | 189:f392fc9709a3 | 440 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 441 | * @arg @ref LL_CRS_SYNC_POLARITY_RISING |
| AnnaBridge | 189:f392fc9709a3 | 442 | * @arg @ref LL_CRS_SYNC_POLARITY_FALLING |
| AnnaBridge | 189:f392fc9709a3 | 443 | */ |
| AnnaBridge | 189:f392fc9709a3 | 444 | __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) |
| AnnaBridge | 189:f392fc9709a3 | 445 | { |
| AnnaBridge | 189:f392fc9709a3 | 446 | return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); |
| AnnaBridge | 189:f392fc9709a3 | 447 | } |
| AnnaBridge | 189:f392fc9709a3 | 448 | |
| AnnaBridge | 189:f392fc9709a3 | 449 | /** |
| AnnaBridge | 189:f392fc9709a3 | 450 | * @brief Configure CRS for the synchronization |
| AnnaBridge | 189:f392fc9709a3 | 451 | * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n |
| AnnaBridge | 189:f392fc9709a3 | 452 | * CFGR RELOAD LL_CRS_ConfigSynchronization\n |
| AnnaBridge | 189:f392fc9709a3 | 453 | * CFGR FELIM LL_CRS_ConfigSynchronization\n |
| AnnaBridge | 189:f392fc9709a3 | 454 | * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n |
| AnnaBridge | 189:f392fc9709a3 | 455 | * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n |
| AnnaBridge | 189:f392fc9709a3 | 456 | * CFGR SYNCPOL LL_CRS_ConfigSynchronization |
| AnnaBridge | 189:f392fc9709a3 | 457 | * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 |
| AnnaBridge | 189:f392fc9709a3 | 458 | * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF |
| AnnaBridge | 189:f392fc9709a3 | 459 | * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 |
| AnnaBridge | 189:f392fc9709a3 | 460 | * @param Settings This parameter can be a combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 461 | * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 |
| AnnaBridge | 189:f392fc9709a3 | 462 | * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 |
| AnnaBridge | 189:f392fc9709a3 | 463 | * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB |
| AnnaBridge | 189:f392fc9709a3 | 464 | * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING |
| AnnaBridge | 189:f392fc9709a3 | 465 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 466 | */ |
| AnnaBridge | 189:f392fc9709a3 | 467 | __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) |
| AnnaBridge | 189:f392fc9709a3 | 468 | { |
| AnnaBridge | 189:f392fc9709a3 | 469 | MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); |
| AnnaBridge | 189:f392fc9709a3 | 470 | MODIFY_REG(CRS->CFGR, |
| AnnaBridge | 189:f392fc9709a3 | 471 | CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, |
| AnnaBridge | 189:f392fc9709a3 | 472 | ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); |
| AnnaBridge | 189:f392fc9709a3 | 473 | } |
| AnnaBridge | 189:f392fc9709a3 | 474 | |
| AnnaBridge | 189:f392fc9709a3 | 475 | /** |
| AnnaBridge | 189:f392fc9709a3 | 476 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 477 | */ |
| AnnaBridge | 189:f392fc9709a3 | 478 | |
| AnnaBridge | 189:f392fc9709a3 | 479 | /** @defgroup CRS_LL_EF_CRS_Management CRS_Management |
| AnnaBridge | 189:f392fc9709a3 | 480 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 481 | */ |
| AnnaBridge | 189:f392fc9709a3 | 482 | |
| AnnaBridge | 189:f392fc9709a3 | 483 | /** |
| AnnaBridge | 189:f392fc9709a3 | 484 | * @brief Generate software SYNC event |
| AnnaBridge | 189:f392fc9709a3 | 485 | * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC |
| AnnaBridge | 189:f392fc9709a3 | 486 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 487 | */ |
| AnnaBridge | 189:f392fc9709a3 | 488 | __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) |
| AnnaBridge | 189:f392fc9709a3 | 489 | { |
| AnnaBridge | 189:f392fc9709a3 | 490 | SET_BIT(CRS->CR, CRS_CR_SWSYNC); |
| AnnaBridge | 189:f392fc9709a3 | 491 | } |
| AnnaBridge | 189:f392fc9709a3 | 492 | |
| AnnaBridge | 189:f392fc9709a3 | 493 | /** |
| AnnaBridge | 189:f392fc9709a3 | 494 | * @brief Get the frequency error direction latched in the time of the last |
| AnnaBridge | 189:f392fc9709a3 | 495 | * SYNC event |
| AnnaBridge | 189:f392fc9709a3 | 496 | * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection |
| AnnaBridge | 189:f392fc9709a3 | 497 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 498 | * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP |
| AnnaBridge | 189:f392fc9709a3 | 499 | * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN |
| AnnaBridge | 189:f392fc9709a3 | 500 | */ |
| AnnaBridge | 189:f392fc9709a3 | 501 | __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) |
| AnnaBridge | 189:f392fc9709a3 | 502 | { |
| AnnaBridge | 189:f392fc9709a3 | 503 | return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); |
| AnnaBridge | 189:f392fc9709a3 | 504 | } |
| AnnaBridge | 189:f392fc9709a3 | 505 | |
| AnnaBridge | 189:f392fc9709a3 | 506 | /** |
| AnnaBridge | 189:f392fc9709a3 | 507 | * @brief Get the frequency error counter value latched in the time of the last SYNC event |
| AnnaBridge | 189:f392fc9709a3 | 508 | * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture |
| AnnaBridge | 189:f392fc9709a3 | 509 | * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF |
| AnnaBridge | 189:f392fc9709a3 | 510 | */ |
| AnnaBridge | 189:f392fc9709a3 | 511 | __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) |
| AnnaBridge | 189:f392fc9709a3 | 512 | { |
| AnnaBridge | 189:f392fc9709a3 | 513 | return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); |
| AnnaBridge | 189:f392fc9709a3 | 514 | } |
| AnnaBridge | 189:f392fc9709a3 | 515 | |
| AnnaBridge | 189:f392fc9709a3 | 516 | /** |
| AnnaBridge | 189:f392fc9709a3 | 517 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 518 | */ |
| AnnaBridge | 189:f392fc9709a3 | 519 | |
| AnnaBridge | 189:f392fc9709a3 | 520 | /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management |
| AnnaBridge | 189:f392fc9709a3 | 521 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 522 | */ |
| AnnaBridge | 189:f392fc9709a3 | 523 | |
| AnnaBridge | 189:f392fc9709a3 | 524 | /** |
| AnnaBridge | 189:f392fc9709a3 | 525 | * @brief Check if SYNC event OK signal occurred or not |
| AnnaBridge | 189:f392fc9709a3 | 526 | * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK |
| AnnaBridge | 189:f392fc9709a3 | 527 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 528 | */ |
| AnnaBridge | 189:f392fc9709a3 | 529 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) |
| AnnaBridge | 189:f392fc9709a3 | 530 | { |
| AnnaBridge | 189:f392fc9709a3 | 531 | return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)); |
| AnnaBridge | 189:f392fc9709a3 | 532 | } |
| AnnaBridge | 189:f392fc9709a3 | 533 | |
| AnnaBridge | 189:f392fc9709a3 | 534 | /** |
| AnnaBridge | 189:f392fc9709a3 | 535 | * @brief Check if SYNC warning signal occurred or not |
| AnnaBridge | 189:f392fc9709a3 | 536 | * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN |
| AnnaBridge | 189:f392fc9709a3 | 537 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 538 | */ |
| AnnaBridge | 189:f392fc9709a3 | 539 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) |
| AnnaBridge | 189:f392fc9709a3 | 540 | { |
| AnnaBridge | 189:f392fc9709a3 | 541 | return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)); |
| AnnaBridge | 189:f392fc9709a3 | 542 | } |
| AnnaBridge | 189:f392fc9709a3 | 543 | |
| AnnaBridge | 189:f392fc9709a3 | 544 | /** |
| AnnaBridge | 189:f392fc9709a3 | 545 | * @brief Check if Synchronization or trimming error signal occurred or not |
| AnnaBridge | 189:f392fc9709a3 | 546 | * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR |
| AnnaBridge | 189:f392fc9709a3 | 547 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 548 | */ |
| AnnaBridge | 189:f392fc9709a3 | 549 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) |
| AnnaBridge | 189:f392fc9709a3 | 550 | { |
| AnnaBridge | 189:f392fc9709a3 | 551 | return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)); |
| AnnaBridge | 189:f392fc9709a3 | 552 | } |
| AnnaBridge | 189:f392fc9709a3 | 553 | |
| AnnaBridge | 189:f392fc9709a3 | 554 | /** |
| AnnaBridge | 189:f392fc9709a3 | 555 | * @brief Check if Expected SYNC signal occurred or not |
| AnnaBridge | 189:f392fc9709a3 | 556 | * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC |
| AnnaBridge | 189:f392fc9709a3 | 557 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 558 | */ |
| AnnaBridge | 189:f392fc9709a3 | 559 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) |
| AnnaBridge | 189:f392fc9709a3 | 560 | { |
| AnnaBridge | 189:f392fc9709a3 | 561 | return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)); |
| AnnaBridge | 189:f392fc9709a3 | 562 | } |
| AnnaBridge | 189:f392fc9709a3 | 563 | |
| AnnaBridge | 189:f392fc9709a3 | 564 | /** |
| AnnaBridge | 189:f392fc9709a3 | 565 | * @brief Check if SYNC error signal occurred or not |
| AnnaBridge | 189:f392fc9709a3 | 566 | * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR |
| AnnaBridge | 189:f392fc9709a3 | 567 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 568 | */ |
| AnnaBridge | 189:f392fc9709a3 | 569 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) |
| AnnaBridge | 189:f392fc9709a3 | 570 | { |
| AnnaBridge | 189:f392fc9709a3 | 571 | return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)); |
| AnnaBridge | 189:f392fc9709a3 | 572 | } |
| AnnaBridge | 189:f392fc9709a3 | 573 | |
| AnnaBridge | 189:f392fc9709a3 | 574 | /** |
| AnnaBridge | 189:f392fc9709a3 | 575 | * @brief Check if SYNC missed error signal occurred or not |
| AnnaBridge | 189:f392fc9709a3 | 576 | * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS |
| AnnaBridge | 189:f392fc9709a3 | 577 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 578 | */ |
| AnnaBridge | 189:f392fc9709a3 | 579 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) |
| AnnaBridge | 189:f392fc9709a3 | 580 | { |
| AnnaBridge | 189:f392fc9709a3 | 581 | return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)); |
| AnnaBridge | 189:f392fc9709a3 | 582 | } |
| AnnaBridge | 189:f392fc9709a3 | 583 | |
| AnnaBridge | 189:f392fc9709a3 | 584 | /** |
| AnnaBridge | 189:f392fc9709a3 | 585 | * @brief Check if Trimming overflow or underflow occurred or not |
| AnnaBridge | 189:f392fc9709a3 | 586 | * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF |
| AnnaBridge | 189:f392fc9709a3 | 587 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 588 | */ |
| AnnaBridge | 189:f392fc9709a3 | 589 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) |
| AnnaBridge | 189:f392fc9709a3 | 590 | { |
| AnnaBridge | 189:f392fc9709a3 | 591 | return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)); |
| AnnaBridge | 189:f392fc9709a3 | 592 | } |
| AnnaBridge | 189:f392fc9709a3 | 593 | |
| AnnaBridge | 189:f392fc9709a3 | 594 | /** |
| AnnaBridge | 189:f392fc9709a3 | 595 | * @brief Clear the SYNC event OK flag |
| AnnaBridge | 189:f392fc9709a3 | 596 | * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK |
| AnnaBridge | 189:f392fc9709a3 | 597 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 598 | */ |
| AnnaBridge | 189:f392fc9709a3 | 599 | __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) |
| AnnaBridge | 189:f392fc9709a3 | 600 | { |
| AnnaBridge | 189:f392fc9709a3 | 601 | WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); |
| AnnaBridge | 189:f392fc9709a3 | 602 | } |
| AnnaBridge | 189:f392fc9709a3 | 603 | |
| AnnaBridge | 189:f392fc9709a3 | 604 | /** |
| AnnaBridge | 189:f392fc9709a3 | 605 | * @brief Clear the SYNC warning flag |
| AnnaBridge | 189:f392fc9709a3 | 606 | * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN |
| AnnaBridge | 189:f392fc9709a3 | 607 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 608 | */ |
| AnnaBridge | 189:f392fc9709a3 | 609 | __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) |
| AnnaBridge | 189:f392fc9709a3 | 610 | { |
| AnnaBridge | 189:f392fc9709a3 | 611 | WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); |
| AnnaBridge | 189:f392fc9709a3 | 612 | } |
| AnnaBridge | 189:f392fc9709a3 | 613 | |
| AnnaBridge | 189:f392fc9709a3 | 614 | /** |
| AnnaBridge | 189:f392fc9709a3 | 615 | * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also |
| AnnaBridge | 189:f392fc9709a3 | 616 | * the ERR flag |
| AnnaBridge | 189:f392fc9709a3 | 617 | * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR |
| AnnaBridge | 189:f392fc9709a3 | 618 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 619 | */ |
| AnnaBridge | 189:f392fc9709a3 | 620 | __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) |
| AnnaBridge | 189:f392fc9709a3 | 621 | { |
| AnnaBridge | 189:f392fc9709a3 | 622 | WRITE_REG(CRS->ICR, CRS_ICR_ERRC); |
| AnnaBridge | 189:f392fc9709a3 | 623 | } |
| AnnaBridge | 189:f392fc9709a3 | 624 | |
| AnnaBridge | 189:f392fc9709a3 | 625 | /** |
| AnnaBridge | 189:f392fc9709a3 | 626 | * @brief Clear Expected SYNC flag |
| AnnaBridge | 189:f392fc9709a3 | 627 | * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC |
| AnnaBridge | 189:f392fc9709a3 | 628 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 629 | */ |
| AnnaBridge | 189:f392fc9709a3 | 630 | __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) |
| AnnaBridge | 189:f392fc9709a3 | 631 | { |
| AnnaBridge | 189:f392fc9709a3 | 632 | WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); |
| AnnaBridge | 189:f392fc9709a3 | 633 | } |
| AnnaBridge | 189:f392fc9709a3 | 634 | |
| AnnaBridge | 189:f392fc9709a3 | 635 | /** |
| AnnaBridge | 189:f392fc9709a3 | 636 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 637 | */ |
| AnnaBridge | 189:f392fc9709a3 | 638 | |
| AnnaBridge | 189:f392fc9709a3 | 639 | /** @defgroup CRS_LL_EF_IT_Management IT_Management |
| AnnaBridge | 189:f392fc9709a3 | 640 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 641 | */ |
| AnnaBridge | 189:f392fc9709a3 | 642 | |
| AnnaBridge | 189:f392fc9709a3 | 643 | /** |
| AnnaBridge | 189:f392fc9709a3 | 644 | * @brief Enable SYNC event OK interrupt |
| AnnaBridge | 189:f392fc9709a3 | 645 | * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK |
| AnnaBridge | 189:f392fc9709a3 | 646 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 647 | */ |
| AnnaBridge | 189:f392fc9709a3 | 648 | __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) |
| AnnaBridge | 189:f392fc9709a3 | 649 | { |
| AnnaBridge | 189:f392fc9709a3 | 650 | SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); |
| AnnaBridge | 189:f392fc9709a3 | 651 | } |
| AnnaBridge | 189:f392fc9709a3 | 652 | |
| AnnaBridge | 189:f392fc9709a3 | 653 | /** |
| AnnaBridge | 189:f392fc9709a3 | 654 | * @brief Disable SYNC event OK interrupt |
| AnnaBridge | 189:f392fc9709a3 | 655 | * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK |
| AnnaBridge | 189:f392fc9709a3 | 656 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 657 | */ |
| AnnaBridge | 189:f392fc9709a3 | 658 | __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) |
| AnnaBridge | 189:f392fc9709a3 | 659 | { |
| AnnaBridge | 189:f392fc9709a3 | 660 | CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); |
| AnnaBridge | 189:f392fc9709a3 | 661 | } |
| AnnaBridge | 189:f392fc9709a3 | 662 | |
| AnnaBridge | 189:f392fc9709a3 | 663 | /** |
| AnnaBridge | 189:f392fc9709a3 | 664 | * @brief Check if SYNC event OK interrupt is enabled or not |
| AnnaBridge | 189:f392fc9709a3 | 665 | * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK |
| AnnaBridge | 189:f392fc9709a3 | 666 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 667 | */ |
| AnnaBridge | 189:f392fc9709a3 | 668 | __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) |
| AnnaBridge | 189:f392fc9709a3 | 669 | { |
| AnnaBridge | 189:f392fc9709a3 | 670 | return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)); |
| AnnaBridge | 189:f392fc9709a3 | 671 | } |
| AnnaBridge | 189:f392fc9709a3 | 672 | |
| AnnaBridge | 189:f392fc9709a3 | 673 | /** |
| AnnaBridge | 189:f392fc9709a3 | 674 | * @brief Enable SYNC warning interrupt |
| AnnaBridge | 189:f392fc9709a3 | 675 | * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN |
| AnnaBridge | 189:f392fc9709a3 | 676 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 677 | */ |
| AnnaBridge | 189:f392fc9709a3 | 678 | __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) |
| AnnaBridge | 189:f392fc9709a3 | 679 | { |
| AnnaBridge | 189:f392fc9709a3 | 680 | SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); |
| AnnaBridge | 189:f392fc9709a3 | 681 | } |
| AnnaBridge | 189:f392fc9709a3 | 682 | |
| AnnaBridge | 189:f392fc9709a3 | 683 | /** |
| AnnaBridge | 189:f392fc9709a3 | 684 | * @brief Disable SYNC warning interrupt |
| AnnaBridge | 189:f392fc9709a3 | 685 | * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN |
| AnnaBridge | 189:f392fc9709a3 | 686 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 687 | */ |
| AnnaBridge | 189:f392fc9709a3 | 688 | __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) |
| AnnaBridge | 189:f392fc9709a3 | 689 | { |
| AnnaBridge | 189:f392fc9709a3 | 690 | CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); |
| AnnaBridge | 189:f392fc9709a3 | 691 | } |
| AnnaBridge | 189:f392fc9709a3 | 692 | |
| AnnaBridge | 189:f392fc9709a3 | 693 | /** |
| AnnaBridge | 189:f392fc9709a3 | 694 | * @brief Check if SYNC warning interrupt is enabled or not |
| AnnaBridge | 189:f392fc9709a3 | 695 | * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN |
| AnnaBridge | 189:f392fc9709a3 | 696 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 697 | */ |
| AnnaBridge | 189:f392fc9709a3 | 698 | __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) |
| AnnaBridge | 189:f392fc9709a3 | 699 | { |
| AnnaBridge | 189:f392fc9709a3 | 700 | return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)); |
| AnnaBridge | 189:f392fc9709a3 | 701 | } |
| AnnaBridge | 189:f392fc9709a3 | 702 | |
| AnnaBridge | 189:f392fc9709a3 | 703 | /** |
| AnnaBridge | 189:f392fc9709a3 | 704 | * @brief Enable Synchronization or trimming error interrupt |
| AnnaBridge | 189:f392fc9709a3 | 705 | * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR |
| AnnaBridge | 189:f392fc9709a3 | 706 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 707 | */ |
| AnnaBridge | 189:f392fc9709a3 | 708 | __STATIC_INLINE void LL_CRS_EnableIT_ERR(void) |
| AnnaBridge | 189:f392fc9709a3 | 709 | { |
| AnnaBridge | 189:f392fc9709a3 | 710 | SET_BIT(CRS->CR, CRS_CR_ERRIE); |
| AnnaBridge | 189:f392fc9709a3 | 711 | } |
| AnnaBridge | 189:f392fc9709a3 | 712 | |
| AnnaBridge | 189:f392fc9709a3 | 713 | /** |
| AnnaBridge | 189:f392fc9709a3 | 714 | * @brief Disable Synchronization or trimming error interrupt |
| AnnaBridge | 189:f392fc9709a3 | 715 | * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR |
| AnnaBridge | 189:f392fc9709a3 | 716 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 717 | */ |
| AnnaBridge | 189:f392fc9709a3 | 718 | __STATIC_INLINE void LL_CRS_DisableIT_ERR(void) |
| AnnaBridge | 189:f392fc9709a3 | 719 | { |
| AnnaBridge | 189:f392fc9709a3 | 720 | CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); |
| AnnaBridge | 189:f392fc9709a3 | 721 | } |
| AnnaBridge | 189:f392fc9709a3 | 722 | |
| AnnaBridge | 189:f392fc9709a3 | 723 | /** |
| AnnaBridge | 189:f392fc9709a3 | 724 | * @brief Check if Synchronization or trimming error interrupt is enabled or not |
| AnnaBridge | 189:f392fc9709a3 | 725 | * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR |
| AnnaBridge | 189:f392fc9709a3 | 726 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 727 | */ |
| AnnaBridge | 189:f392fc9709a3 | 728 | __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) |
| AnnaBridge | 189:f392fc9709a3 | 729 | { |
| AnnaBridge | 189:f392fc9709a3 | 730 | return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)); |
| AnnaBridge | 189:f392fc9709a3 | 731 | } |
| AnnaBridge | 189:f392fc9709a3 | 732 | |
| AnnaBridge | 189:f392fc9709a3 | 733 | /** |
| AnnaBridge | 189:f392fc9709a3 | 734 | * @brief Enable Expected SYNC interrupt |
| AnnaBridge | 189:f392fc9709a3 | 735 | * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC |
| AnnaBridge | 189:f392fc9709a3 | 736 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 737 | */ |
| AnnaBridge | 189:f392fc9709a3 | 738 | __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) |
| AnnaBridge | 189:f392fc9709a3 | 739 | { |
| AnnaBridge | 189:f392fc9709a3 | 740 | SET_BIT(CRS->CR, CRS_CR_ESYNCIE); |
| AnnaBridge | 189:f392fc9709a3 | 741 | } |
| AnnaBridge | 189:f392fc9709a3 | 742 | |
| AnnaBridge | 189:f392fc9709a3 | 743 | /** |
| AnnaBridge | 189:f392fc9709a3 | 744 | * @brief Disable Expected SYNC interrupt |
| AnnaBridge | 189:f392fc9709a3 | 745 | * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC |
| AnnaBridge | 189:f392fc9709a3 | 746 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 747 | */ |
| AnnaBridge | 189:f392fc9709a3 | 748 | __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) |
| AnnaBridge | 189:f392fc9709a3 | 749 | { |
| AnnaBridge | 189:f392fc9709a3 | 750 | CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); |
| AnnaBridge | 189:f392fc9709a3 | 751 | } |
| AnnaBridge | 189:f392fc9709a3 | 752 | |
| AnnaBridge | 189:f392fc9709a3 | 753 | /** |
| AnnaBridge | 189:f392fc9709a3 | 754 | * @brief Check if Expected SYNC interrupt is enabled or not |
| AnnaBridge | 189:f392fc9709a3 | 755 | * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC |
| AnnaBridge | 189:f392fc9709a3 | 756 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 757 | */ |
| AnnaBridge | 189:f392fc9709a3 | 758 | __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) |
| AnnaBridge | 189:f392fc9709a3 | 759 | { |
| AnnaBridge | 189:f392fc9709a3 | 760 | return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)); |
| AnnaBridge | 189:f392fc9709a3 | 761 | } |
| AnnaBridge | 189:f392fc9709a3 | 762 | |
| AnnaBridge | 189:f392fc9709a3 | 763 | /** |
| AnnaBridge | 189:f392fc9709a3 | 764 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 765 | */ |
| AnnaBridge | 189:f392fc9709a3 | 766 | |
| AnnaBridge | 189:f392fc9709a3 | 767 | #if defined(USE_FULL_LL_DRIVER) |
| AnnaBridge | 189:f392fc9709a3 | 768 | /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions |
| AnnaBridge | 189:f392fc9709a3 | 769 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 770 | */ |
| AnnaBridge | 189:f392fc9709a3 | 771 | |
| AnnaBridge | 189:f392fc9709a3 | 772 | ErrorStatus LL_CRS_DeInit(void); |
| AnnaBridge | 189:f392fc9709a3 | 773 | |
| AnnaBridge | 189:f392fc9709a3 | 774 | /** |
| AnnaBridge | 189:f392fc9709a3 | 775 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 776 | */ |
| AnnaBridge | 189:f392fc9709a3 | 777 | #endif /* USE_FULL_LL_DRIVER */ |
| AnnaBridge | 189:f392fc9709a3 | 778 | |
| AnnaBridge | 189:f392fc9709a3 | 779 | /** |
| AnnaBridge | 189:f392fc9709a3 | 780 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 781 | */ |
| AnnaBridge | 189:f392fc9709a3 | 782 | |
| AnnaBridge | 189:f392fc9709a3 | 783 | /** |
| AnnaBridge | 189:f392fc9709a3 | 784 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 785 | */ |
| AnnaBridge | 189:f392fc9709a3 | 786 | |
| AnnaBridge | 189:f392fc9709a3 | 787 | #endif /* defined(CRS) */ |
| AnnaBridge | 189:f392fc9709a3 | 788 | |
| AnnaBridge | 189:f392fc9709a3 | 789 | /** |
| AnnaBridge | 189:f392fc9709a3 | 790 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 791 | */ |
| AnnaBridge | 189:f392fc9709a3 | 792 | |
| AnnaBridge | 189:f392fc9709a3 | 793 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 794 | } |
| AnnaBridge | 189:f392fc9709a3 | 795 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 796 | |
| AnnaBridge | 189:f392fc9709a3 | 797 | #endif /* __STM32L4xx_LL_CRS_H */ |
| AnnaBridge | 189:f392fc9709a3 | 798 | |
| AnnaBridge | 189:f392fc9709a3 | 799 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
