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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_ARM_STD/stm32l4xx_hal_tim_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_hal_tim_ex.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of TIM HAL Extended module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_HAL_TIM_EX_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_HAL_TIM_EX_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | /** @addtogroup TIMEx |
| AnnaBridge | 189:f392fc9709a3 | 52 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 53 | */ |
| AnnaBridge | 189:f392fc9709a3 | 54 | |
| AnnaBridge | 189:f392fc9709a3 | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 56 | /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 57 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 58 | */ |
| AnnaBridge | 189:f392fc9709a3 | 59 | |
| AnnaBridge | 189:f392fc9709a3 | 60 | /** |
| AnnaBridge | 189:f392fc9709a3 | 61 | * @brief TIM Hall sensor Configuration Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 62 | */ |
| AnnaBridge | 189:f392fc9709a3 | 63 | |
| AnnaBridge | 189:f392fc9709a3 | 64 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 65 | { |
| AnnaBridge | 189:f392fc9709a3 | 66 | |
| AnnaBridge | 189:f392fc9709a3 | 67 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
| AnnaBridge | 189:f392fc9709a3 | 68 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
| AnnaBridge | 189:f392fc9709a3 | 69 | |
| AnnaBridge | 189:f392fc9709a3 | 70 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
| AnnaBridge | 189:f392fc9709a3 | 71 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
| AnnaBridge | 189:f392fc9709a3 | 72 | |
| AnnaBridge | 189:f392fc9709a3 | 73 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
| AnnaBridge | 189:f392fc9709a3 | 74 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| AnnaBridge | 189:f392fc9709a3 | 75 | |
| AnnaBridge | 189:f392fc9709a3 | 76 | uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
| AnnaBridge | 189:f392fc9709a3 | 77 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
| AnnaBridge | 189:f392fc9709a3 | 78 | } TIM_HallSensor_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 79 | |
| AnnaBridge | 189:f392fc9709a3 | 80 | /** |
| AnnaBridge | 189:f392fc9709a3 | 81 | * @brief TIM Break/Break2 input configuration |
| AnnaBridge | 189:f392fc9709a3 | 82 | */ |
| AnnaBridge | 189:f392fc9709a3 | 83 | typedef struct { |
| AnnaBridge | 189:f392fc9709a3 | 84 | uint32_t Source; /*!< Specifies the source of the timer break input. |
| AnnaBridge | 189:f392fc9709a3 | 85 | This parameter can be a value of @ref TIMEx_Break_Input_Source */ |
| AnnaBridge | 189:f392fc9709a3 | 86 | uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 87 | This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 88 | uint32_t Polarity; /*!< Specifies the break input source polarity. |
| AnnaBridge | 189:f392fc9709a3 | 89 | This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity |
| AnnaBridge | 189:f392fc9709a3 | 90 | Not relevant when analog watchdog output of the DFSDM1 used as break input source */ |
| AnnaBridge | 189:f392fc9709a3 | 91 | } TIMEx_BreakInputConfigTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 92 | |
| AnnaBridge | 189:f392fc9709a3 | 93 | /** |
| AnnaBridge | 189:f392fc9709a3 | 94 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 95 | */ |
| AnnaBridge | 189:f392fc9709a3 | 96 | /* End of exported types -----------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 97 | |
| AnnaBridge | 189:f392fc9709a3 | 98 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 99 | /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 100 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 101 | */ |
| AnnaBridge | 189:f392fc9709a3 | 102 | |
| AnnaBridge | 189:f392fc9709a3 | 103 | /** @defgroup TIMEx_Remap TIM Extended Remapping |
| AnnaBridge | 189:f392fc9709a3 | 104 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 105 | */ |
| AnnaBridge | 189:f392fc9709a3 | 106 | #define TIM_TIM1_ETR_ADC1_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
| AnnaBridge | 189:f392fc9709a3 | 107 | #define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ |
| AnnaBridge | 189:f392fc9709a3 | 108 | #define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD2 */ |
| AnnaBridge | 189:f392fc9709a3 | 109 | #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 111 | defined (STM32L496xx) || defined (STM32L4A6xx) |
| AnnaBridge | 189:f392fc9709a3 | 112 | #define TIM_TIM1_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
| AnnaBridge | 189:f392fc9709a3 | 113 | #define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD1 */ |
| AnnaBridge | 189:f392fc9709a3 | 114 | #define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1) /* !< TIM1_ETR is connected to ADC3 AWD2 */ |
| AnnaBridge | 189:f392fc9709a3 | 115 | #define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */ |
| AnnaBridge | 189:f392fc9709a3 | 116 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 117 | /* STM32L496xx || STM32L4A6xx */ |
| AnnaBridge | 189:f392fc9709a3 | 118 | #define TIM_TIM1_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM1 TI1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 119 | #define TIM_TIM1_TI1_COMP1 (TIM1_OR1_TI1_RMP) /* !< TIM1 TI1 is connected to COMP1 */ |
| AnnaBridge | 189:f392fc9709a3 | 120 | #define TIM_TIM1_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM1_ETR is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | #define TIM_TIM1_ETR_COMP1 (TIM1_OR2_ETRSEL_0) /* !< TIM1_ETR is connected to COMP1 output */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | #define TIM_TIM1_ETR_COMP2 (TIM1_OR2_ETRSEL_1) /* !< TIM1_ETR is connected to COMP2 output */ |
| AnnaBridge | 189:f392fc9709a3 | 123 | |
| AnnaBridge | 189:f392fc9709a3 | 124 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 125 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 126 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 127 | #define TIM_TIM2_ITR1_TIM8_TRGO ((uint32_t)(0x00000000)) /* !< TIM2_ITR1 is connected to TIM8_TRGO */ |
| AnnaBridge | 189:f392fc9709a3 | 128 | #define TIM_TIM2_ITR1_OTG_FS_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to OTG_FS SOF */ |
| AnnaBridge | 189:f392fc9709a3 | 129 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 130 | /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 131 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 132 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 133 | defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) |
| AnnaBridge | 189:f392fc9709a3 | 134 | #define TIM_TIM2_ITR1_NONE ((uint32_t)(0x00000000)) /* !< No internal trigger on TIM2_ITR1 */ |
| AnnaBridge | 189:f392fc9709a3 | 135 | #define TIM_TIM2_ITR1_USB_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */ |
| AnnaBridge | 189:f392fc9709a3 | 136 | #endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | /* STM32L451xx || STM32L452xx || STM32L462xx */ |
| AnnaBridge | 189:f392fc9709a3 | 138 | #define TIM_TIM2_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM2_ETR is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 139 | #define TIM_TIM2_ETR_LSE (TIM2_OR1_ETR1_RMP) /* !< TIM2_ETR is connected to LSE */ |
| AnnaBridge | 189:f392fc9709a3 | 140 | #define TIM_TIM2_ETR_COMP1 (TIM2_OR2_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 output */ |
| AnnaBridge | 189:f392fc9709a3 | 141 | #define TIM_TIM2_ETR_COMP2 (TIM2_OR2_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 output */ |
| AnnaBridge | 189:f392fc9709a3 | 142 | #define TIM_TIM2_TI4_GPIO ((uint32_t)(0x00000000)) /* !< TIM2 TI4 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 143 | #define TIM_TIM2_TI4_COMP1 (TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to COMP1 output */ |
| AnnaBridge | 189:f392fc9709a3 | 144 | #define TIM_TIM2_TI4_COMP2 (TIM2_OR1_TI4_RMP_1) /* !< TIM2 TI4 is connected to COMP2 output */ |
| AnnaBridge | 189:f392fc9709a3 | 145 | #define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */ |
| AnnaBridge | 189:f392fc9709a3 | 146 | |
| AnnaBridge | 189:f392fc9709a3 | 147 | #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 148 | defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 149 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 150 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 151 | #define TIM_TIM3_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM3 TI1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 152 | #define TIM_TIM3_TI1_COMP1 (TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to COMP1 output */ |
| AnnaBridge | 189:f392fc9709a3 | 153 | #define TIM_TIM3_TI1_COMP2 (TIM3_OR1_TI1_RMP_1) /* !< TIM3 TI1 is connected to COMP2 output */ |
| AnnaBridge | 189:f392fc9709a3 | 154 | #define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */ |
| AnnaBridge | 189:f392fc9709a3 | 155 | #define TIM_TIM3_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM3_ETR is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 156 | #define TIM_TIM3_ETR_COMP1 (TIM3_OR2_ETRSEL_0) /* !< TIM3_ETR is connected to COMP1 output */ |
| AnnaBridge | 189:f392fc9709a3 | 157 | #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 158 | /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 159 | /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 160 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 161 | |
| AnnaBridge | 189:f392fc9709a3 | 162 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 163 | defined (STM32L496xx) || defined (STM32L4A6xx) |
| AnnaBridge | 189:f392fc9709a3 | 164 | #define TIM_TIM8_ETR_ADC2_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ |
| AnnaBridge | 189:f392fc9709a3 | 165 | #define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */ |
| AnnaBridge | 189:f392fc9709a3 | 166 | #define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1) /* !< TIM8_ETR is connected to ADC2 AWD2 */ |
| AnnaBridge | 189:f392fc9709a3 | 167 | #define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */ |
| AnnaBridge | 189:f392fc9709a3 | 168 | #define TIM_TIM8_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ |
| AnnaBridge | 189:f392fc9709a3 | 169 | #define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD1 */ |
| AnnaBridge | 189:f392fc9709a3 | 170 | #define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1) /* !< TIM8_ETR is connected to ADC3 AWD2 */ |
| AnnaBridge | 189:f392fc9709a3 | 171 | #define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */ |
| AnnaBridge | 189:f392fc9709a3 | 172 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 173 | /* STM32L496xx || STM32L4A6xx */ |
| AnnaBridge | 189:f392fc9709a3 | 174 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 175 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 176 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 177 | #define TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 178 | #define TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */ |
| AnnaBridge | 189:f392fc9709a3 | 179 | #define TIM_TIM8_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM8_ETR is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 180 | #define TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */ |
| AnnaBridge | 189:f392fc9709a3 | 181 | #define TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 183 | /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 184 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 185 | |
| AnnaBridge | 189:f392fc9709a3 | 186 | #define TIM_TIM15_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM15 TI1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 187 | #define TIM_TIM15_TI1_LSE (TIM15_OR1_TI1_RMP) /* !< TIM15 TI1 is connected to LSE */ |
| AnnaBridge | 189:f392fc9709a3 | 188 | #define TIM_TIM15_ENCODERMODE_NONE ((uint32_t)(0x00000000)) /* !< No redirection */ |
| AnnaBridge | 189:f392fc9709a3 | 189 | #define TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0) /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ |
| AnnaBridge | 189:f392fc9709a3 | 190 | #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 191 | defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 192 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 193 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 194 | #define TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1) /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ |
| AnnaBridge | 189:f392fc9709a3 | 195 | #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ |
| AnnaBridge | 189:f392fc9709a3 | 196 | /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 197 | /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 198 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 199 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 200 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 201 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 202 | #define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ |
| AnnaBridge | 189:f392fc9709a3 | 203 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 204 | /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 205 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 206 | |
| AnnaBridge | 189:f392fc9709a3 | 207 | #define TIM_TIM16_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM16 TI1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 208 | #define TIM_TIM16_TI1_LSI (TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to LSI */ |
| AnnaBridge | 189:f392fc9709a3 | 209 | #define TIM_TIM16_TI1_LSE (TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to LSE */ |
| AnnaBridge | 189:f392fc9709a3 | 210 | #define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 211 | #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 212 | defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 213 | defined (STM32L496xx) || defined (STM32L4A6xx) |
| AnnaBridge | 189:f392fc9709a3 | 214 | #define TIM_TIM16_TI1_MSI (TIM16_OR1_TI1_RMP_2) /* !< TIM16 TI1 is connected to MSI */ |
| AnnaBridge | 189:f392fc9709a3 | 215 | #define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */ |
| AnnaBridge | 189:f392fc9709a3 | 216 | #define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */ |
| AnnaBridge | 189:f392fc9709a3 | 217 | #endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 218 | /* STM32L451xx || STM32L452xx || STM32L462xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 219 | /* STM32L496xx || STM32L4A6xx */ |
| AnnaBridge | 189:f392fc9709a3 | 220 | |
| AnnaBridge | 189:f392fc9709a3 | 221 | #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 222 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 223 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 224 | #define TIM_TIM17_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM17 TI1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 225 | #define TIM_TIM17_TI1_MSI (TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MSI */ |
| AnnaBridge | 189:f392fc9709a3 | 226 | #define TIM_TIM17_TI1_HSE_32 (TIM17_OR1_TI1_RMP_1) /* !< TIM17 TI1 is connected to HSE div 32 */ |
| AnnaBridge | 189:f392fc9709a3 | 227 | #define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */ |
| AnnaBridge | 189:f392fc9709a3 | 228 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 229 | /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 230 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 231 | /** |
| AnnaBridge | 189:f392fc9709a3 | 232 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 233 | */ |
| AnnaBridge | 189:f392fc9709a3 | 234 | |
| AnnaBridge | 189:f392fc9709a3 | 235 | /** @defgroup TIMEx_Break_Input TIM Extended Break input |
| AnnaBridge | 189:f392fc9709a3 | 236 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 237 | */ |
| AnnaBridge | 189:f392fc9709a3 | 238 | #define TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */ |
| AnnaBridge | 189:f392fc9709a3 | 239 | #define TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */ |
| AnnaBridge | 189:f392fc9709a3 | 240 | /** |
| AnnaBridge | 189:f392fc9709a3 | 241 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 242 | */ |
| AnnaBridge | 189:f392fc9709a3 | 243 | |
| AnnaBridge | 189:f392fc9709a3 | 244 | /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source |
| AnnaBridge | 189:f392fc9709a3 | 245 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 246 | */ |
| AnnaBridge | 189:f392fc9709a3 | 247 | #define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */ |
| AnnaBridge | 189:f392fc9709a3 | 248 | #define TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */ |
| AnnaBridge | 189:f392fc9709a3 | 249 | #define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */ |
| AnnaBridge | 189:f392fc9709a3 | 250 | #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 251 | defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 252 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 253 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 254 | #define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ |
| AnnaBridge | 189:f392fc9709a3 | 255 | #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 256 | /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 257 | /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 258 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 259 | /** |
| AnnaBridge | 189:f392fc9709a3 | 260 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 261 | */ |
| AnnaBridge | 189:f392fc9709a3 | 262 | |
| AnnaBridge | 189:f392fc9709a3 | 263 | /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling |
| AnnaBridge | 189:f392fc9709a3 | 264 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 265 | */ |
| AnnaBridge | 189:f392fc9709a3 | 266 | #define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 267 | #define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */ |
| AnnaBridge | 189:f392fc9709a3 | 268 | /** |
| AnnaBridge | 189:f392fc9709a3 | 269 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 270 | */ |
| AnnaBridge | 189:f392fc9709a3 | 271 | |
| AnnaBridge | 189:f392fc9709a3 | 272 | /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity |
| AnnaBridge | 189:f392fc9709a3 | 273 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 274 | */ |
| AnnaBridge | 189:f392fc9709a3 | 275 | #define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */ |
| AnnaBridge | 189:f392fc9709a3 | 276 | #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */ |
| AnnaBridge | 189:f392fc9709a3 | 277 | /** |
| AnnaBridge | 189:f392fc9709a3 | 278 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 279 | */ |
| AnnaBridge | 189:f392fc9709a3 | 280 | |
| AnnaBridge | 189:f392fc9709a3 | 281 | /** |
| AnnaBridge | 189:f392fc9709a3 | 282 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 283 | */ |
| AnnaBridge | 189:f392fc9709a3 | 284 | /* End of exported constants -------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 285 | |
| AnnaBridge | 189:f392fc9709a3 | 286 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 287 | /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 288 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 289 | */ |
| AnnaBridge | 189:f392fc9709a3 | 290 | |
| AnnaBridge | 189:f392fc9709a3 | 291 | /** |
| AnnaBridge | 189:f392fc9709a3 | 292 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 293 | */ |
| AnnaBridge | 189:f392fc9709a3 | 294 | /* End of exported macro -----------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 295 | |
| AnnaBridge | 189:f392fc9709a3 | 296 | /* Private macro -------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 297 | /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 298 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 299 | */ |
| AnnaBridge | 189:f392fc9709a3 | 300 | #define IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F)) |
| AnnaBridge | 189:f392fc9709a3 | 301 | |
| AnnaBridge | 189:f392fc9709a3 | 302 | #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ |
| AnnaBridge | 189:f392fc9709a3 | 303 | ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) |
| AnnaBridge | 189:f392fc9709a3 | 304 | |
| AnnaBridge | 189:f392fc9709a3 | 305 | #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 306 | defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 307 | defined (STM32L496xx) || defined (STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 308 | defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 309 | #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ |
| AnnaBridge | 189:f392fc9709a3 | 310 | ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 311 | ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 312 | ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1)) |
| AnnaBridge | 189:f392fc9709a3 | 313 | #else |
| AnnaBridge | 189:f392fc9709a3 | 314 | #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ |
| AnnaBridge | 189:f392fc9709a3 | 315 | ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 316 | ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) |
| AnnaBridge | 189:f392fc9709a3 | 317 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 318 | /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 319 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 320 | |
| AnnaBridge | 189:f392fc9709a3 | 321 | #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 322 | ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 323 | |
| AnnaBridge | 189:f392fc9709a3 | 324 | #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ |
| AnnaBridge | 189:f392fc9709a3 | 325 | ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) |
| AnnaBridge | 189:f392fc9709a3 | 326 | /** |
| AnnaBridge | 189:f392fc9709a3 | 327 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 328 | */ |
| AnnaBridge | 189:f392fc9709a3 | 329 | /* End of private macro ------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 330 | |
| AnnaBridge | 189:f392fc9709a3 | 331 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 332 | /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 333 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 334 | */ |
| AnnaBridge | 189:f392fc9709a3 | 335 | |
| AnnaBridge | 189:f392fc9709a3 | 336 | /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions |
| AnnaBridge | 189:f392fc9709a3 | 337 | * @brief Timer Hall Sensor functions |
| AnnaBridge | 189:f392fc9709a3 | 338 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 339 | */ |
| AnnaBridge | 189:f392fc9709a3 | 340 | /* Timer Hall Sensor functions **********************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 341 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); |
| AnnaBridge | 189:f392fc9709a3 | 342 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 343 | |
| AnnaBridge | 189:f392fc9709a3 | 344 | void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 345 | void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 346 | |
| AnnaBridge | 189:f392fc9709a3 | 347 | /* Blocking mode: Polling */ |
| AnnaBridge | 189:f392fc9709a3 | 348 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 349 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 350 | /* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 351 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 352 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 353 | /* Non-Blocking mode: DMA */ |
| AnnaBridge | 189:f392fc9709a3 | 354 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
| AnnaBridge | 189:f392fc9709a3 | 355 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 356 | /** |
| AnnaBridge | 189:f392fc9709a3 | 357 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 358 | */ |
| AnnaBridge | 189:f392fc9709a3 | 359 | |
| AnnaBridge | 189:f392fc9709a3 | 360 | /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions |
| AnnaBridge | 189:f392fc9709a3 | 361 | * @brief Timer Complementary Output Compare functions |
| AnnaBridge | 189:f392fc9709a3 | 362 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 363 | */ |
| AnnaBridge | 189:f392fc9709a3 | 364 | /* Timer Complementary Output Compare functions *****************************/ |
| AnnaBridge | 189:f392fc9709a3 | 365 | /* Blocking mode: Polling */ |
| AnnaBridge | 189:f392fc9709a3 | 366 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 367 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 368 | |
| AnnaBridge | 189:f392fc9709a3 | 369 | /* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 370 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 371 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 372 | |
| AnnaBridge | 189:f392fc9709a3 | 373 | /* Non-Blocking mode: DMA */ |
| AnnaBridge | 189:f392fc9709a3 | 374 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
| AnnaBridge | 189:f392fc9709a3 | 375 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 376 | /** |
| AnnaBridge | 189:f392fc9709a3 | 377 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 378 | */ |
| AnnaBridge | 189:f392fc9709a3 | 379 | |
| AnnaBridge | 189:f392fc9709a3 | 380 | /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions |
| AnnaBridge | 189:f392fc9709a3 | 381 | * @brief Timer Complementary PWM functions |
| AnnaBridge | 189:f392fc9709a3 | 382 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 383 | */ |
| AnnaBridge | 189:f392fc9709a3 | 384 | /* Timer Complementary PWM functions ****************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 385 | /* Blocking mode: Polling */ |
| AnnaBridge | 189:f392fc9709a3 | 386 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 387 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 388 | |
| AnnaBridge | 189:f392fc9709a3 | 389 | /* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 390 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 391 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 392 | /* Non-Blocking mode: DMA */ |
| AnnaBridge | 189:f392fc9709a3 | 393 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
| AnnaBridge | 189:f392fc9709a3 | 394 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 395 | /** |
| AnnaBridge | 189:f392fc9709a3 | 396 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 397 | */ |
| AnnaBridge | 189:f392fc9709a3 | 398 | |
| AnnaBridge | 189:f392fc9709a3 | 399 | /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions |
| AnnaBridge | 189:f392fc9709a3 | 400 | * @brief Timer Complementary One Pulse functions |
| AnnaBridge | 189:f392fc9709a3 | 401 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 402 | */ |
| AnnaBridge | 189:f392fc9709a3 | 403 | /* Timer Complementary One Pulse functions **********************************/ |
| AnnaBridge | 189:f392fc9709a3 | 404 | /* Blocking mode: Polling */ |
| AnnaBridge | 189:f392fc9709a3 | 405 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| AnnaBridge | 189:f392fc9709a3 | 406 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| AnnaBridge | 189:f392fc9709a3 | 407 | |
| AnnaBridge | 189:f392fc9709a3 | 408 | /* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 409 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| AnnaBridge | 189:f392fc9709a3 | 410 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| AnnaBridge | 189:f392fc9709a3 | 411 | /** |
| AnnaBridge | 189:f392fc9709a3 | 412 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 413 | */ |
| AnnaBridge | 189:f392fc9709a3 | 414 | |
| AnnaBridge | 189:f392fc9709a3 | 415 | /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions |
| AnnaBridge | 189:f392fc9709a3 | 416 | * @brief Peripheral Control functions |
| AnnaBridge | 189:f392fc9709a3 | 417 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 418 | */ |
| AnnaBridge | 189:f392fc9709a3 | 419 | /* Extended Control functions ************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 420 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); |
| AnnaBridge | 189:f392fc9709a3 | 421 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); |
| AnnaBridge | 189:f392fc9709a3 | 422 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); |
| AnnaBridge | 189:f392fc9709a3 | 423 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); |
| AnnaBridge | 189:f392fc9709a3 | 424 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); |
| AnnaBridge | 189:f392fc9709a3 | 425 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); |
| AnnaBridge | 189:f392fc9709a3 | 426 | HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); |
| AnnaBridge | 189:f392fc9709a3 | 427 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); |
| AnnaBridge | 189:f392fc9709a3 | 428 | |
| AnnaBridge | 189:f392fc9709a3 | 429 | /** |
| AnnaBridge | 189:f392fc9709a3 | 430 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 431 | */ |
| AnnaBridge | 189:f392fc9709a3 | 432 | |
| AnnaBridge | 189:f392fc9709a3 | 433 | /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions |
| AnnaBridge | 189:f392fc9709a3 | 434 | * @brief Extended Callbacks functions |
| AnnaBridge | 189:f392fc9709a3 | 435 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 436 | */ |
| AnnaBridge | 189:f392fc9709a3 | 437 | /* Extended Callback **********************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 438 | void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 439 | void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 440 | /** |
| AnnaBridge | 189:f392fc9709a3 | 441 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 442 | */ |
| AnnaBridge | 189:f392fc9709a3 | 443 | |
| AnnaBridge | 189:f392fc9709a3 | 444 | /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions |
| AnnaBridge | 189:f392fc9709a3 | 445 | * @brief Extended Peripheral State functions |
| AnnaBridge | 189:f392fc9709a3 | 446 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 447 | */ |
| AnnaBridge | 189:f392fc9709a3 | 448 | /* Extended Peripheral State functions ***************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 449 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 450 | /** |
| AnnaBridge | 189:f392fc9709a3 | 451 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 452 | */ |
| AnnaBridge | 189:f392fc9709a3 | 453 | |
| AnnaBridge | 189:f392fc9709a3 | 454 | /** |
| AnnaBridge | 189:f392fc9709a3 | 455 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 456 | */ |
| AnnaBridge | 189:f392fc9709a3 | 457 | /* End of exported functions -------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 458 | |
| AnnaBridge | 189:f392fc9709a3 | 459 | /* Private functions----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 460 | /** @defgroup TIMEx_Private_Functions TIMEx Private Functions |
| AnnaBridge | 189:f392fc9709a3 | 461 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 462 | */ |
| AnnaBridge | 189:f392fc9709a3 | 463 | void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 189:f392fc9709a3 | 464 | /** |
| AnnaBridge | 189:f392fc9709a3 | 465 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 466 | */ |
| AnnaBridge | 189:f392fc9709a3 | 467 | /* End of private functions --------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 468 | |
| AnnaBridge | 189:f392fc9709a3 | 469 | /** |
| AnnaBridge | 189:f392fc9709a3 | 470 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 471 | */ |
| AnnaBridge | 189:f392fc9709a3 | 472 | |
| AnnaBridge | 189:f392fc9709a3 | 473 | /** |
| AnnaBridge | 189:f392fc9709a3 | 474 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 475 | */ |
| AnnaBridge | 189:f392fc9709a3 | 476 | |
| AnnaBridge | 189:f392fc9709a3 | 477 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 478 | } |
| AnnaBridge | 189:f392fc9709a3 | 479 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 480 | |
| AnnaBridge | 189:f392fc9709a3 | 481 | |
| AnnaBridge | 189:f392fc9709a3 | 482 | #endif /* __STM32L4xx_HAL_TIM_EX_H */ |
| AnnaBridge | 189:f392fc9709a3 | 483 | |
| AnnaBridge | 189:f392fc9709a3 | 484 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
