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mbed library sources. Supersedes mbed-src.

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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_ARM_STD/stm32l4xx_hal_sram.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /**
AnnaBridge 189:f392fc9709a3 2 ******************************************************************************
AnnaBridge 189:f392fc9709a3 3 * @file stm32l4xx_hal_sram.h
AnnaBridge 189:f392fc9709a3 4 * @author MCD Application Team
AnnaBridge 189:f392fc9709a3 5 * @brief Header file of SRAM HAL module.
AnnaBridge 189:f392fc9709a3 6 ******************************************************************************
AnnaBridge 189:f392fc9709a3 7 * @attention
AnnaBridge 189:f392fc9709a3 8 *
AnnaBridge 189:f392fc9709a3 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 189:f392fc9709a3 10 *
AnnaBridge 189:f392fc9709a3 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 12 * are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 189:f392fc9709a3 14 * this list of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 189:f392fc9709a3 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 189:f392fc9709a3 17 * and/or other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 189:f392fc9709a3 19 * may be used to endorse or promote products derived from this software
AnnaBridge 189:f392fc9709a3 20 * without specific prior written permission.
AnnaBridge 189:f392fc9709a3 21 *
AnnaBridge 189:f392fc9709a3 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 189:f392fc9709a3 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 189:f392fc9709a3 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 189:f392fc9709a3 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 189:f392fc9709a3 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 189:f392fc9709a3 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 189:f392fc9709a3 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 189:f392fc9709a3 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 189:f392fc9709a3 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 189:f392fc9709a3 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 32 *
AnnaBridge 189:f392fc9709a3 33 ******************************************************************************
AnnaBridge 189:f392fc9709a3 34 */
AnnaBridge 189:f392fc9709a3 35
AnnaBridge 189:f392fc9709a3 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 189:f392fc9709a3 37 #ifndef __STM32L4xx_HAL_SRAM_H
AnnaBridge 189:f392fc9709a3 38 #define __STM32L4xx_HAL_SRAM_H
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 41 extern "C" {
AnnaBridge 189:f392fc9709a3 42 #endif
AnnaBridge 189:f392fc9709a3 43
AnnaBridge 189:f392fc9709a3 44 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
AnnaBridge 189:f392fc9709a3 45 defined(STM32L496xx) || defined(STM32L4A6xx) || \
AnnaBridge 189:f392fc9709a3 46 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 189:f392fc9709a3 47
AnnaBridge 189:f392fc9709a3 48 /* Includes ------------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 49 #include "stm32l4xx_ll_fmc.h"
AnnaBridge 189:f392fc9709a3 50
AnnaBridge 189:f392fc9709a3 51 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 189:f392fc9709a3 52 * @{
AnnaBridge 189:f392fc9709a3 53 */
AnnaBridge 189:f392fc9709a3 54
AnnaBridge 189:f392fc9709a3 55 /** @addtogroup SRAM
AnnaBridge 189:f392fc9709a3 56 * @{
AnnaBridge 189:f392fc9709a3 57 */
AnnaBridge 189:f392fc9709a3 58
AnnaBridge 189:f392fc9709a3 59 /* Exported typedef ----------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 60
AnnaBridge 189:f392fc9709a3 61 /** @defgroup SRAM_Exported_Types SRAM Exported Types
AnnaBridge 189:f392fc9709a3 62 * @{
AnnaBridge 189:f392fc9709a3 63 */
AnnaBridge 189:f392fc9709a3 64 /**
AnnaBridge 189:f392fc9709a3 65 * @brief HAL SRAM State structures definition
AnnaBridge 189:f392fc9709a3 66 */
AnnaBridge 189:f392fc9709a3 67 typedef enum
AnnaBridge 189:f392fc9709a3 68 {
AnnaBridge 189:f392fc9709a3 69 HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */
AnnaBridge 189:f392fc9709a3 70 HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */
AnnaBridge 189:f392fc9709a3 71 HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */
AnnaBridge 189:f392fc9709a3 72 HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */
AnnaBridge 189:f392fc9709a3 73 HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
AnnaBridge 189:f392fc9709a3 74
AnnaBridge 189:f392fc9709a3 75 }HAL_SRAM_StateTypeDef;
AnnaBridge 189:f392fc9709a3 76
AnnaBridge 189:f392fc9709a3 77 /**
AnnaBridge 189:f392fc9709a3 78 * @brief SRAM handle Structure definition
AnnaBridge 189:f392fc9709a3 79 */
AnnaBridge 189:f392fc9709a3 80 typedef struct
AnnaBridge 189:f392fc9709a3 81 {
AnnaBridge 189:f392fc9709a3 82 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
AnnaBridge 189:f392fc9709a3 83
AnnaBridge 189:f392fc9709a3 84 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
AnnaBridge 189:f392fc9709a3 85
AnnaBridge 189:f392fc9709a3 86 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
AnnaBridge 189:f392fc9709a3 87
AnnaBridge 189:f392fc9709a3 88 HAL_LockTypeDef Lock; /*!< SRAM locking object */
AnnaBridge 189:f392fc9709a3 89
AnnaBridge 189:f392fc9709a3 90 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
AnnaBridge 189:f392fc9709a3 91
AnnaBridge 189:f392fc9709a3 92 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
AnnaBridge 189:f392fc9709a3 93
AnnaBridge 189:f392fc9709a3 94 }SRAM_HandleTypeDef;
AnnaBridge 189:f392fc9709a3 95
AnnaBridge 189:f392fc9709a3 96 /**
AnnaBridge 189:f392fc9709a3 97 * @}
AnnaBridge 189:f392fc9709a3 98 */
AnnaBridge 189:f392fc9709a3 99
AnnaBridge 189:f392fc9709a3 100 /* Exported constants --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 101 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 102
AnnaBridge 189:f392fc9709a3 103 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
AnnaBridge 189:f392fc9709a3 104 * @{
AnnaBridge 189:f392fc9709a3 105 */
AnnaBridge 189:f392fc9709a3 106
AnnaBridge 189:f392fc9709a3 107 /** @brief Reset SRAM handle state.
AnnaBridge 189:f392fc9709a3 108 * @param __HANDLE__: SRAM handle
AnnaBridge 189:f392fc9709a3 109 * @retval None
AnnaBridge 189:f392fc9709a3 110 */
AnnaBridge 189:f392fc9709a3 111 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
AnnaBridge 189:f392fc9709a3 112
AnnaBridge 189:f392fc9709a3 113 /**
AnnaBridge 189:f392fc9709a3 114 * @}
AnnaBridge 189:f392fc9709a3 115 */
AnnaBridge 189:f392fc9709a3 116
AnnaBridge 189:f392fc9709a3 117 /* Exported functions --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 118 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
AnnaBridge 189:f392fc9709a3 119 * @{
AnnaBridge 189:f392fc9709a3 120 */
AnnaBridge 189:f392fc9709a3 121
AnnaBridge 189:f392fc9709a3 122 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 189:f392fc9709a3 123 * @{
AnnaBridge 189:f392fc9709a3 124 */
AnnaBridge 189:f392fc9709a3 125
AnnaBridge 189:f392fc9709a3 126 /* Initialization/de-initialization functions ********************************/
AnnaBridge 189:f392fc9709a3 127 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
AnnaBridge 189:f392fc9709a3 128 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
AnnaBridge 189:f392fc9709a3 129 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
AnnaBridge 189:f392fc9709a3 130 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
AnnaBridge 189:f392fc9709a3 131
AnnaBridge 189:f392fc9709a3 132 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
AnnaBridge 189:f392fc9709a3 133 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
AnnaBridge 189:f392fc9709a3 134
AnnaBridge 189:f392fc9709a3 135 /**
AnnaBridge 189:f392fc9709a3 136 * @}
AnnaBridge 189:f392fc9709a3 137 */
AnnaBridge 189:f392fc9709a3 138
AnnaBridge 189:f392fc9709a3 139 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
AnnaBridge 189:f392fc9709a3 140 * @{
AnnaBridge 189:f392fc9709a3 141 */
AnnaBridge 189:f392fc9709a3 142
AnnaBridge 189:f392fc9709a3 143 /* I/O operation functions ***************************************************/
AnnaBridge 189:f392fc9709a3 144 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 189:f392fc9709a3 145 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 189:f392fc9709a3 146 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 189:f392fc9709a3 147 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 189:f392fc9709a3 148 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 189:f392fc9709a3 149 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 189:f392fc9709a3 150 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 189:f392fc9709a3 151 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 189:f392fc9709a3 152
AnnaBridge 189:f392fc9709a3 153 /**
AnnaBridge 189:f392fc9709a3 154 * @}
AnnaBridge 189:f392fc9709a3 155 */
AnnaBridge 189:f392fc9709a3 156
AnnaBridge 189:f392fc9709a3 157 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
AnnaBridge 189:f392fc9709a3 158 * @{
AnnaBridge 189:f392fc9709a3 159 */
AnnaBridge 189:f392fc9709a3 160
AnnaBridge 189:f392fc9709a3 161 /* SRAM Control functions ****************************************************/
AnnaBridge 189:f392fc9709a3 162 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
AnnaBridge 189:f392fc9709a3 163 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
AnnaBridge 189:f392fc9709a3 164
AnnaBridge 189:f392fc9709a3 165 /**
AnnaBridge 189:f392fc9709a3 166 * @}
AnnaBridge 189:f392fc9709a3 167 */
AnnaBridge 189:f392fc9709a3 168
AnnaBridge 189:f392fc9709a3 169 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
AnnaBridge 189:f392fc9709a3 170 * @{
AnnaBridge 189:f392fc9709a3 171 */
AnnaBridge 189:f392fc9709a3 172
AnnaBridge 189:f392fc9709a3 173 /* SRAM Peripheral State functions ********************************************/
AnnaBridge 189:f392fc9709a3 174 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
AnnaBridge 189:f392fc9709a3 175
AnnaBridge 189:f392fc9709a3 176 /**
AnnaBridge 189:f392fc9709a3 177 * @}
AnnaBridge 189:f392fc9709a3 178 */
AnnaBridge 189:f392fc9709a3 179
AnnaBridge 189:f392fc9709a3 180 /**
AnnaBridge 189:f392fc9709a3 181 * @}
AnnaBridge 189:f392fc9709a3 182 */
AnnaBridge 189:f392fc9709a3 183
AnnaBridge 189:f392fc9709a3 184 /**
AnnaBridge 189:f392fc9709a3 185 * @}
AnnaBridge 189:f392fc9709a3 186 */
AnnaBridge 189:f392fc9709a3 187
AnnaBridge 189:f392fc9709a3 188 /**
AnnaBridge 189:f392fc9709a3 189 * @}
AnnaBridge 189:f392fc9709a3 190 */
AnnaBridge 189:f392fc9709a3 191
AnnaBridge 189:f392fc9709a3 192 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
AnnaBridge 189:f392fc9709a3 193 /* STM32L496xx || STM32L4A6xx || */
AnnaBridge 189:f392fc9709a3 194 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 189:f392fc9709a3 195
AnnaBridge 189:f392fc9709a3 196 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 197 }
AnnaBridge 189:f392fc9709a3 198 #endif
AnnaBridge 189:f392fc9709a3 199
AnnaBridge 189:f392fc9709a3 200 #endif /* __STM32L4xx_HAL_SRAM_H */
AnnaBridge 189:f392fc9709a3 201
AnnaBridge 189:f392fc9709a3 202 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/