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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_ARM_STD/stm32l4xx_hal_pwr.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_hal_pwr.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of PWR HAL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_HAL_PWR_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_HAL_PWR_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | /** @addtogroup PWR |
| AnnaBridge | 189:f392fc9709a3 | 52 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 53 | */ |
| AnnaBridge | 189:f392fc9709a3 | 54 | |
| AnnaBridge | 189:f392fc9709a3 | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 56 | |
| AnnaBridge | 189:f392fc9709a3 | 57 | /** @defgroup PWR_Exported_Types PWR Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 58 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 59 | */ |
| AnnaBridge | 189:f392fc9709a3 | 60 | |
| AnnaBridge | 189:f392fc9709a3 | 61 | /** |
| AnnaBridge | 189:f392fc9709a3 | 62 | * @brief PWR PVD configuration structure definition |
| AnnaBridge | 189:f392fc9709a3 | 63 | */ |
| AnnaBridge | 189:f392fc9709a3 | 64 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 65 | { |
| AnnaBridge | 189:f392fc9709a3 | 66 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. |
| AnnaBridge | 189:f392fc9709a3 | 67 | This parameter can be a value of @ref PWR_PVD_detection_level. */ |
| AnnaBridge | 189:f392fc9709a3 | 68 | |
| AnnaBridge | 189:f392fc9709a3 | 69 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
| AnnaBridge | 189:f392fc9709a3 | 70 | This parameter can be a value of @ref PWR_PVD_Mode. */ |
| AnnaBridge | 189:f392fc9709a3 | 71 | }PWR_PVDTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 72 | |
| AnnaBridge | 189:f392fc9709a3 | 73 | |
| AnnaBridge | 189:f392fc9709a3 | 74 | /** |
| AnnaBridge | 189:f392fc9709a3 | 75 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 76 | */ |
| AnnaBridge | 189:f392fc9709a3 | 77 | |
| AnnaBridge | 189:f392fc9709a3 | 78 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 79 | |
| AnnaBridge | 189:f392fc9709a3 | 80 | /** @defgroup PWR_Exported_Constants PWR Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 81 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 82 | */ |
| AnnaBridge | 189:f392fc9709a3 | 83 | |
| AnnaBridge | 189:f392fc9709a3 | 84 | |
| AnnaBridge | 189:f392fc9709a3 | 85 | /** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels |
| AnnaBridge | 189:f392fc9709a3 | 86 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 87 | */ |
| AnnaBridge | 189:f392fc9709a3 | 88 | #define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */ |
| AnnaBridge | 189:f392fc9709a3 | 89 | #define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */ |
| AnnaBridge | 189:f392fc9709a3 | 90 | #define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */ |
| AnnaBridge | 189:f392fc9709a3 | 91 | #define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */ |
| AnnaBridge | 189:f392fc9709a3 | 92 | #define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */ |
| AnnaBridge | 189:f392fc9709a3 | 93 | #define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */ |
| AnnaBridge | 189:f392fc9709a3 | 94 | #define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */ |
| AnnaBridge | 189:f392fc9709a3 | 95 | #define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */ |
| AnnaBridge | 189:f392fc9709a3 | 96 | /** |
| AnnaBridge | 189:f392fc9709a3 | 97 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 98 | */ |
| AnnaBridge | 189:f392fc9709a3 | 99 | |
| AnnaBridge | 189:f392fc9709a3 | 100 | /** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode |
| AnnaBridge | 189:f392fc9709a3 | 101 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 102 | */ |
| AnnaBridge | 189:f392fc9709a3 | 103 | #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */ |
| AnnaBridge | 189:f392fc9709a3 | 104 | #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ |
| AnnaBridge | 189:f392fc9709a3 | 105 | #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ |
| AnnaBridge | 189:f392fc9709a3 | 106 | #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 189:f392fc9709a3 | 107 | #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ |
| AnnaBridge | 189:f392fc9709a3 | 108 | #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ |
| AnnaBridge | 189:f392fc9709a3 | 109 | #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | /** |
| AnnaBridge | 189:f392fc9709a3 | 111 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 112 | */ |
| AnnaBridge | 189:f392fc9709a3 | 113 | |
| AnnaBridge | 189:f392fc9709a3 | 114 | |
| AnnaBridge | 189:f392fc9709a3 | 115 | |
| AnnaBridge | 189:f392fc9709a3 | 116 | |
| AnnaBridge | 189:f392fc9709a3 | 117 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode |
| AnnaBridge | 189:f392fc9709a3 | 118 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 119 | */ |
| AnnaBridge | 189:f392fc9709a3 | 120 | #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | /** |
| AnnaBridge | 189:f392fc9709a3 | 123 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 124 | */ |
| AnnaBridge | 189:f392fc9709a3 | 125 | |
| AnnaBridge | 189:f392fc9709a3 | 126 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry |
| AnnaBridge | 189:f392fc9709a3 | 127 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 128 | */ |
| AnnaBridge | 189:f392fc9709a3 | 129 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */ |
| AnnaBridge | 189:f392fc9709a3 | 130 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */ |
| AnnaBridge | 189:f392fc9709a3 | 131 | /** |
| AnnaBridge | 189:f392fc9709a3 | 132 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 133 | */ |
| AnnaBridge | 189:f392fc9709a3 | 134 | |
| AnnaBridge | 189:f392fc9709a3 | 135 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry |
| AnnaBridge | 189:f392fc9709a3 | 136 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 137 | */ |
| AnnaBridge | 189:f392fc9709a3 | 138 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */ |
| AnnaBridge | 189:f392fc9709a3 | 139 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */ |
| AnnaBridge | 189:f392fc9709a3 | 140 | /** |
| AnnaBridge | 189:f392fc9709a3 | 141 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 142 | */ |
| AnnaBridge | 189:f392fc9709a3 | 143 | |
| AnnaBridge | 189:f392fc9709a3 | 144 | |
| AnnaBridge | 189:f392fc9709a3 | 145 | /** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line |
| AnnaBridge | 189:f392fc9709a3 | 146 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 147 | */ |
| AnnaBridge | 189:f392fc9709a3 | 148 | #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
| AnnaBridge | 189:f392fc9709a3 | 149 | /** |
| AnnaBridge | 189:f392fc9709a3 | 150 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 151 | */ |
| AnnaBridge | 189:f392fc9709a3 | 152 | |
| AnnaBridge | 189:f392fc9709a3 | 153 | /** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line |
| AnnaBridge | 189:f392fc9709a3 | 154 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 155 | */ |
| AnnaBridge | 189:f392fc9709a3 | 156 | #define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */ |
| AnnaBridge | 189:f392fc9709a3 | 157 | /** |
| AnnaBridge | 189:f392fc9709a3 | 158 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 159 | */ |
| AnnaBridge | 189:f392fc9709a3 | 160 | |
| AnnaBridge | 189:f392fc9709a3 | 161 | /** |
| AnnaBridge | 189:f392fc9709a3 | 162 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 163 | */ |
| AnnaBridge | 189:f392fc9709a3 | 164 | |
| AnnaBridge | 189:f392fc9709a3 | 165 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 166 | /** @defgroup PWR_Exported_Macros PWR Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 167 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 168 | */ |
| AnnaBridge | 189:f392fc9709a3 | 169 | |
| AnnaBridge | 189:f392fc9709a3 | 170 | /** @brief Check whether or not a specific PWR flag is set. |
| AnnaBridge | 189:f392fc9709a3 | 171 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 189:f392fc9709a3 | 172 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 173 | * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event |
| AnnaBridge | 189:f392fc9709a3 | 174 | * was received from the WKUP pin 1. |
| AnnaBridge | 189:f392fc9709a3 | 175 | * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event |
| AnnaBridge | 189:f392fc9709a3 | 176 | * was received from the WKUP pin 2. |
| AnnaBridge | 189:f392fc9709a3 | 177 | * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event |
| AnnaBridge | 189:f392fc9709a3 | 178 | * was received from the WKUP pin 3. |
| AnnaBridge | 189:f392fc9709a3 | 179 | * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event |
| AnnaBridge | 189:f392fc9709a3 | 180 | * was received from the WKUP pin 4. |
| AnnaBridge | 189:f392fc9709a3 | 181 | * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event |
| AnnaBridge | 189:f392fc9709a3 | 182 | * was received from the WKUP pin 5. |
| AnnaBridge | 189:f392fc9709a3 | 183 | * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system |
| AnnaBridge | 189:f392fc9709a3 | 184 | * entered StandBy mode. |
| AnnaBridge | 189:f392fc9709a3 | 185 | * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on |
| AnnaBridge | 189:f392fc9709a3 | 186 | * the internal wakeup line. |
| AnnaBridge | 189:f392fc9709a3 | 187 | * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the |
| AnnaBridge | 189:f392fc9709a3 | 188 | * low-power regulator is ready. |
| AnnaBridge | 189:f392fc9709a3 | 189 | * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the |
| AnnaBridge | 189:f392fc9709a3 | 190 | * regulator is ready in main mode or is in low-power mode. |
| AnnaBridge | 189:f392fc9709a3 | 191 | * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready |
| AnnaBridge | 189:f392fc9709a3 | 192 | * in the selected voltage range or is still changing to the required voltage level. |
| AnnaBridge | 189:f392fc9709a3 | 193 | * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is |
| AnnaBridge | 189:f392fc9709a3 | 194 | * below or above the selected PVD threshold. |
| AnnaBridge | 189:f392fc9709a3 | 195 | * @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is |
| AnnaBridge | 189:f392fc9709a3 | 196 | * is below or above PVM1 threshold (applicable when USB feature is supported). |
| AnnaBridge | 189:f392fc9709a3 | 197 | @if STM32L486xx |
| AnnaBridge | 189:f392fc9709a3 | 198 | * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is |
| AnnaBridge | 189:f392fc9709a3 | 199 | * is below or above PVM2 threshold (applicable when VDDIO2 is present on device). |
| AnnaBridge | 189:f392fc9709a3 | 200 | @endif |
| AnnaBridge | 189:f392fc9709a3 | 201 | * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is |
| AnnaBridge | 189:f392fc9709a3 | 202 | * is below or above PVM3 threshold. |
| AnnaBridge | 189:f392fc9709a3 | 203 | * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is |
| AnnaBridge | 189:f392fc9709a3 | 204 | * is below or above PVM4 threshold. |
| AnnaBridge | 189:f392fc9709a3 | 205 | * |
| AnnaBridge | 189:f392fc9709a3 | 206 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 189:f392fc9709a3 | 207 | */ |
| AnnaBridge | 189:f392fc9709a3 | 208 | #define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\ |
| AnnaBridge | 189:f392fc9709a3 | 209 | (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\ |
| AnnaBridge | 189:f392fc9709a3 | 210 | (PWR->SR2 & (1U << ((__FLAG__) & 31U))) ) |
| AnnaBridge | 189:f392fc9709a3 | 211 | |
| AnnaBridge | 189:f392fc9709a3 | 212 | /** @brief Clear a specific PWR flag. |
| AnnaBridge | 189:f392fc9709a3 | 213 | * @param __FLAG__: specifies the flag to clear. |
| AnnaBridge | 189:f392fc9709a3 | 214 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 215 | * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event |
| AnnaBridge | 189:f392fc9709a3 | 216 | * was received from the WKUP pin 1. |
| AnnaBridge | 189:f392fc9709a3 | 217 | * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event |
| AnnaBridge | 189:f392fc9709a3 | 218 | * was received from the WKUP pin 2. |
| AnnaBridge | 189:f392fc9709a3 | 219 | * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event |
| AnnaBridge | 189:f392fc9709a3 | 220 | * was received from the WKUP pin 3. |
| AnnaBridge | 189:f392fc9709a3 | 221 | * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event |
| AnnaBridge | 189:f392fc9709a3 | 222 | * was received from the WKUP pin 4. |
| AnnaBridge | 189:f392fc9709a3 | 223 | * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event |
| AnnaBridge | 189:f392fc9709a3 | 224 | * was received from the WKUP pin 5. |
| AnnaBridge | 189:f392fc9709a3 | 225 | * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags. |
| AnnaBridge | 189:f392fc9709a3 | 226 | * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system |
| AnnaBridge | 189:f392fc9709a3 | 227 | * entered Standby mode. |
| AnnaBridge | 189:f392fc9709a3 | 228 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 229 | */ |
| AnnaBridge | 189:f392fc9709a3 | 230 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\ |
| AnnaBridge | 189:f392fc9709a3 | 231 | (PWR->SCR = (__FLAG__)) :\ |
| AnnaBridge | 189:f392fc9709a3 | 232 | (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) |
| AnnaBridge | 189:f392fc9709a3 | 233 | /** |
| AnnaBridge | 189:f392fc9709a3 | 234 | * @brief Enable the PVD Extended Interrupt Line. |
| AnnaBridge | 189:f392fc9709a3 | 235 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 236 | */ |
| AnnaBridge | 189:f392fc9709a3 | 237 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 189:f392fc9709a3 | 238 | |
| AnnaBridge | 189:f392fc9709a3 | 239 | /** |
| AnnaBridge | 189:f392fc9709a3 | 240 | * @brief Disable the PVD Extended Interrupt Line. |
| AnnaBridge | 189:f392fc9709a3 | 241 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 242 | */ |
| AnnaBridge | 189:f392fc9709a3 | 243 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 189:f392fc9709a3 | 244 | |
| AnnaBridge | 189:f392fc9709a3 | 245 | /** |
| AnnaBridge | 189:f392fc9709a3 | 246 | * @brief Enable the PVD Event Line. |
| AnnaBridge | 189:f392fc9709a3 | 247 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 248 | */ |
| AnnaBridge | 189:f392fc9709a3 | 249 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) |
| AnnaBridge | 189:f392fc9709a3 | 250 | |
| AnnaBridge | 189:f392fc9709a3 | 251 | /** |
| AnnaBridge | 189:f392fc9709a3 | 252 | * @brief Disable the PVD Event Line. |
| AnnaBridge | 189:f392fc9709a3 | 253 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 254 | */ |
| AnnaBridge | 189:f392fc9709a3 | 255 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) |
| AnnaBridge | 189:f392fc9709a3 | 256 | |
| AnnaBridge | 189:f392fc9709a3 | 257 | /** |
| AnnaBridge | 189:f392fc9709a3 | 258 | * @brief Enable the PVD Extended Interrupt Rising Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 259 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 260 | */ |
| AnnaBridge | 189:f392fc9709a3 | 261 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 189:f392fc9709a3 | 262 | |
| AnnaBridge | 189:f392fc9709a3 | 263 | /** |
| AnnaBridge | 189:f392fc9709a3 | 264 | * @brief Disable the PVD Extended Interrupt Rising Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 265 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 266 | */ |
| AnnaBridge | 189:f392fc9709a3 | 267 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 189:f392fc9709a3 | 268 | |
| AnnaBridge | 189:f392fc9709a3 | 269 | /** |
| AnnaBridge | 189:f392fc9709a3 | 270 | * @brief Enable the PVD Extended Interrupt Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 271 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 272 | */ |
| AnnaBridge | 189:f392fc9709a3 | 273 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 189:f392fc9709a3 | 274 | |
| AnnaBridge | 189:f392fc9709a3 | 275 | |
| AnnaBridge | 189:f392fc9709a3 | 276 | /** |
| AnnaBridge | 189:f392fc9709a3 | 277 | * @brief Disable the PVD Extended Interrupt Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 278 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 279 | */ |
| AnnaBridge | 189:f392fc9709a3 | 280 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 189:f392fc9709a3 | 281 | |
| AnnaBridge | 189:f392fc9709a3 | 282 | |
| AnnaBridge | 189:f392fc9709a3 | 283 | /** |
| AnnaBridge | 189:f392fc9709a3 | 284 | * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 285 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 286 | */ |
| AnnaBridge | 189:f392fc9709a3 | 287 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 189:f392fc9709a3 | 288 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 289 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 290 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 291 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 292 | |
| AnnaBridge | 189:f392fc9709a3 | 293 | /** |
| AnnaBridge | 189:f392fc9709a3 | 294 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 189:f392fc9709a3 | 295 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 296 | */ |
| AnnaBridge | 189:f392fc9709a3 | 297 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 189:f392fc9709a3 | 298 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 299 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 300 | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ |
| AnnaBridge | 189:f392fc9709a3 | 301 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 302 | |
| AnnaBridge | 189:f392fc9709a3 | 303 | /** |
| AnnaBridge | 189:f392fc9709a3 | 304 | * @brief Generate a Software interrupt on selected EXTI line. |
| AnnaBridge | 189:f392fc9709a3 | 305 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 306 | */ |
| AnnaBridge | 189:f392fc9709a3 | 307 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 189:f392fc9709a3 | 308 | |
| AnnaBridge | 189:f392fc9709a3 | 309 | /** |
| AnnaBridge | 189:f392fc9709a3 | 310 | * @brief Check whether or not the PVD EXTI interrupt flag is set. |
| AnnaBridge | 189:f392fc9709a3 | 311 | * @retval EXTI PVD Line Status. |
| AnnaBridge | 189:f392fc9709a3 | 312 | */ |
| AnnaBridge | 189:f392fc9709a3 | 313 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD) |
| AnnaBridge | 189:f392fc9709a3 | 314 | |
| AnnaBridge | 189:f392fc9709a3 | 315 | /** |
| AnnaBridge | 189:f392fc9709a3 | 316 | * @brief Clear the PVD EXTI interrupt flag. |
| AnnaBridge | 189:f392fc9709a3 | 317 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 318 | */ |
| AnnaBridge | 189:f392fc9709a3 | 319 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 189:f392fc9709a3 | 320 | |
| AnnaBridge | 189:f392fc9709a3 | 321 | /** |
| AnnaBridge | 189:f392fc9709a3 | 322 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 323 | */ |
| AnnaBridge | 189:f392fc9709a3 | 324 | |
| AnnaBridge | 189:f392fc9709a3 | 325 | |
| AnnaBridge | 189:f392fc9709a3 | 326 | /* Private macros --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 327 | /** @addtogroup PWR_Private_Macros PWR Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 328 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 329 | */ |
| AnnaBridge | 189:f392fc9709a3 | 330 | |
| AnnaBridge | 189:f392fc9709a3 | 331 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
| AnnaBridge | 189:f392fc9709a3 | 332 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ |
| AnnaBridge | 189:f392fc9709a3 | 333 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ |
| AnnaBridge | 189:f392fc9709a3 | 334 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
| AnnaBridge | 189:f392fc9709a3 | 335 | |
| AnnaBridge | 189:f392fc9709a3 | 336 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 337 | ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 338 | ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 339 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 340 | ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 341 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 342 | ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) |
| AnnaBridge | 189:f392fc9709a3 | 343 | |
| AnnaBridge | 189:f392fc9709a3 | 344 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
| AnnaBridge | 189:f392fc9709a3 | 345 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
| AnnaBridge | 189:f392fc9709a3 | 346 | |
| AnnaBridge | 189:f392fc9709a3 | 347 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
| AnnaBridge | 189:f392fc9709a3 | 348 | |
| AnnaBridge | 189:f392fc9709a3 | 349 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) |
| AnnaBridge | 189:f392fc9709a3 | 350 | |
| AnnaBridge | 189:f392fc9709a3 | 351 | /** |
| AnnaBridge | 189:f392fc9709a3 | 352 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 353 | */ |
| AnnaBridge | 189:f392fc9709a3 | 354 | |
| AnnaBridge | 189:f392fc9709a3 | 355 | /* Include PWR HAL Extended module */ |
| AnnaBridge | 189:f392fc9709a3 | 356 | #include "stm32l4xx_hal_pwr_ex.h" |
| AnnaBridge | 189:f392fc9709a3 | 357 | |
| AnnaBridge | 189:f392fc9709a3 | 358 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 359 | |
| AnnaBridge | 189:f392fc9709a3 | 360 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 361 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 362 | */ |
| AnnaBridge | 189:f392fc9709a3 | 363 | |
| AnnaBridge | 189:f392fc9709a3 | 364 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 189:f392fc9709a3 | 365 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 366 | */ |
| AnnaBridge | 189:f392fc9709a3 | 367 | |
| AnnaBridge | 189:f392fc9709a3 | 368 | /* Initialization and de-initialization functions *******************************/ |
| AnnaBridge | 189:f392fc9709a3 | 369 | void HAL_PWR_DeInit(void); |
| AnnaBridge | 189:f392fc9709a3 | 370 | void HAL_PWR_EnableBkUpAccess(void); |
| AnnaBridge | 189:f392fc9709a3 | 371 | void HAL_PWR_DisableBkUpAccess(void); |
| AnnaBridge | 189:f392fc9709a3 | 372 | |
| AnnaBridge | 189:f392fc9709a3 | 373 | /** |
| AnnaBridge | 189:f392fc9709a3 | 374 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 375 | */ |
| AnnaBridge | 189:f392fc9709a3 | 376 | |
| AnnaBridge | 189:f392fc9709a3 | 377 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions |
| AnnaBridge | 189:f392fc9709a3 | 378 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 379 | */ |
| AnnaBridge | 189:f392fc9709a3 | 380 | |
| AnnaBridge | 189:f392fc9709a3 | 381 | /* Peripheral Control functions ************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 382 | HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
| AnnaBridge | 189:f392fc9709a3 | 383 | void HAL_PWR_EnablePVD(void); |
| AnnaBridge | 189:f392fc9709a3 | 384 | void HAL_PWR_DisablePVD(void); |
| AnnaBridge | 189:f392fc9709a3 | 385 | |
| AnnaBridge | 189:f392fc9709a3 | 386 | |
| AnnaBridge | 189:f392fc9709a3 | 387 | /* WakeUp pins configuration functions ****************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 388 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); |
| AnnaBridge | 189:f392fc9709a3 | 389 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
| AnnaBridge | 189:f392fc9709a3 | 390 | |
| AnnaBridge | 189:f392fc9709a3 | 391 | /* Low Power modes configuration functions ************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 392 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
| AnnaBridge | 189:f392fc9709a3 | 393 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
| AnnaBridge | 189:f392fc9709a3 | 394 | void HAL_PWR_EnterSTANDBYMode(void); |
| AnnaBridge | 189:f392fc9709a3 | 395 | |
| AnnaBridge | 189:f392fc9709a3 | 396 | void HAL_PWR_EnableSleepOnExit(void); |
| AnnaBridge | 189:f392fc9709a3 | 397 | void HAL_PWR_DisableSleepOnExit(void); |
| AnnaBridge | 189:f392fc9709a3 | 398 | void HAL_PWR_EnableSEVOnPend(void); |
| AnnaBridge | 189:f392fc9709a3 | 399 | void HAL_PWR_DisableSEVOnPend(void); |
| AnnaBridge | 189:f392fc9709a3 | 400 | |
| AnnaBridge | 189:f392fc9709a3 | 401 | void HAL_PWR_PVDCallback(void); |
| AnnaBridge | 189:f392fc9709a3 | 402 | |
| AnnaBridge | 189:f392fc9709a3 | 403 | |
| AnnaBridge | 189:f392fc9709a3 | 404 | /** |
| AnnaBridge | 189:f392fc9709a3 | 405 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 406 | */ |
| AnnaBridge | 189:f392fc9709a3 | 407 | |
| AnnaBridge | 189:f392fc9709a3 | 408 | /** |
| AnnaBridge | 189:f392fc9709a3 | 409 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 410 | */ |
| AnnaBridge | 189:f392fc9709a3 | 411 | |
| AnnaBridge | 189:f392fc9709a3 | 412 | /** |
| AnnaBridge | 189:f392fc9709a3 | 413 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 414 | */ |
| AnnaBridge | 189:f392fc9709a3 | 415 | |
| AnnaBridge | 189:f392fc9709a3 | 416 | /** |
| AnnaBridge | 189:f392fc9709a3 | 417 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 418 | */ |
| AnnaBridge | 189:f392fc9709a3 | 419 | |
| AnnaBridge | 189:f392fc9709a3 | 420 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 421 | } |
| AnnaBridge | 189:f392fc9709a3 | 422 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 423 | |
| AnnaBridge | 189:f392fc9709a3 | 424 | |
| AnnaBridge | 189:f392fc9709a3 | 425 | #endif /* __STM32L4xx_HAL_PWR_H */ |
| AnnaBridge | 189:f392fc9709a3 | 426 | |
| AnnaBridge | 189:f392fc9709a3 | 427 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
