mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_ARM_STD/stm32l4xx_hal_flash.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l4xx_hal_flash.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of FLASH HAL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L4xx_HAL_FLASH_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L4xx_HAL_FLASH_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	45	#include "stm32l4xx_hal_def.h"
AnnaBridge	189:f392fc9709a3	46
AnnaBridge	189:f392fc9709a3	47	/** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge	189:f392fc9709a3	48	* @{
AnnaBridge	189:f392fc9709a3	49	*/
AnnaBridge	189:f392fc9709a3	50
AnnaBridge	189:f392fc9709a3	51	/** @addtogroup FLASH
AnnaBridge	189:f392fc9709a3	52	* @{
AnnaBridge	189:f392fc9709a3	53	*/
AnnaBridge	189:f392fc9709a3	54
AnnaBridge	189:f392fc9709a3	55	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	56	/** @defgroup FLASH_Exported_Types FLASH Exported Types
AnnaBridge	189:f392fc9709a3	57	* @{
AnnaBridge	189:f392fc9709a3	58	*/
AnnaBridge	189:f392fc9709a3	59
AnnaBridge	189:f392fc9709a3	60	/**
AnnaBridge	189:f392fc9709a3	61	* @brief FLASH Erase structure definition
AnnaBridge	189:f392fc9709a3	62	*/
AnnaBridge	189:f392fc9709a3	63	typedef struct
AnnaBridge	189:f392fc9709a3	64	{
AnnaBridge	189:f392fc9709a3	65	uint32_t TypeErase; /*!< Mass erase or page erase.
AnnaBridge	189:f392fc9709a3	66	This parameter can be a value of @ref FLASH_Type_Erase */
AnnaBridge	189:f392fc9709a3	67	uint32_t Banks; /*!< Select bank to erase.
AnnaBridge	189:f392fc9709a3	68	This parameter must be a value of @ref FLASH_Banks
AnnaBridge	189:f392fc9709a3	69	(FLASH_BANK_BOTH should be used only for mass erase) */
AnnaBridge	189:f392fc9709a3	70	uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled
AnnaBridge	189:f392fc9709a3	71	This parameter must be a value between 0 and (max number of pages in the bank - 1)
AnnaBridge	189:f392fc9709a3	72	(eg : 255 for 1MB dual bank) */
AnnaBridge	189:f392fc9709a3	73	uint32_t NbPages; /*!< Number of pages to be erased.
AnnaBridge	189:f392fc9709a3	74	This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/
AnnaBridge	189:f392fc9709a3	75	} FLASH_EraseInitTypeDef;
AnnaBridge	189:f392fc9709a3	76
AnnaBridge	189:f392fc9709a3	77	/**
AnnaBridge	189:f392fc9709a3	78	* @brief FLASH Option Bytes Program structure definition
AnnaBridge	189:f392fc9709a3	79	*/
AnnaBridge	189:f392fc9709a3	80	typedef struct
AnnaBridge	189:f392fc9709a3	81	{
AnnaBridge	189:f392fc9709a3	82	uint32_t OptionType; /*!< Option byte to be configured.
AnnaBridge	189:f392fc9709a3	83	This parameter can be a combination of the values of @ref FLASH_OB_Type */
AnnaBridge	189:f392fc9709a3	84	uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
AnnaBridge	189:f392fc9709a3	85	Only one WRP area could be programmed at the same time.
AnnaBridge	189:f392fc9709a3	86	This parameter can be value of @ref FLASH_OB_WRP_Area */
AnnaBridge	189:f392fc9709a3	87	uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
AnnaBridge	189:f392fc9709a3	88	This parameter must be a value between 0 and (max number of pages in the bank - 1)
AnnaBridge	189:f392fc9709a3	89	(eg : 25 for 1MB dual bank) */
AnnaBridge	189:f392fc9709a3	90	uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
AnnaBridge	189:f392fc9709a3	91	This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
AnnaBridge	189:f392fc9709a3	92	uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
AnnaBridge	189:f392fc9709a3	93	This parameter can be a value of @ref FLASH_OB_Read_Protection */
AnnaBridge	189:f392fc9709a3	94	uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
AnnaBridge	189:f392fc9709a3	95	This parameter can be a combination of @ref FLASH_OB_USER_Type */
AnnaBridge	189:f392fc9709a3	96	uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
AnnaBridge	189:f392fc9709a3	97	This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
AnnaBridge	189:f392fc9709a3	98	@ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
AnnaBridge	189:f392fc9709a3	99	@ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
AnnaBridge	189:f392fc9709a3	100	@ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
AnnaBridge	189:f392fc9709a3	101	@ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2,
AnnaBridge	189:f392fc9709a3	102	@ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1,
AnnaBridge	189:f392fc9709a3	103	@ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */
AnnaBridge	189:f392fc9709a3	104	uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
AnnaBridge	189:f392fc9709a3	105	This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)
AnnaBridge	189:f392fc9709a3	106	and @ref FLASH_OB_PCROP_RDP */
AnnaBridge	189:f392fc9709a3	107	uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
AnnaBridge	189:f392fc9709a3	108	This parameter must be a value between begin and end of bank
AnnaBridge	189:f392fc9709a3	109	=> Be careful of the bank swapping for the address */
AnnaBridge	189:f392fc9709a3	110	uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
AnnaBridge	189:f392fc9709a3	111	This parameter must be a value between PCROP Start address and end of bank */
AnnaBridge	189:f392fc9709a3	112	} FLASH_OBProgramInitTypeDef;
AnnaBridge	189:f392fc9709a3	113
AnnaBridge	189:f392fc9709a3	114	/**
AnnaBridge	189:f392fc9709a3	115	* @brief FLASH Procedure structure definition
AnnaBridge	189:f392fc9709a3	116	*/
AnnaBridge	189:f392fc9709a3	117	typedef enum
AnnaBridge	189:f392fc9709a3	118	{
AnnaBridge	189:f392fc9709a3	119	FLASH_PROC_NONE = 0,
AnnaBridge	189:f392fc9709a3	120	FLASH_PROC_PAGE_ERASE,
AnnaBridge	189:f392fc9709a3	121	FLASH_PROC_MASS_ERASE,
AnnaBridge	189:f392fc9709a3	122	FLASH_PROC_PROGRAM,
AnnaBridge	189:f392fc9709a3	123	FLASH_PROC_PROGRAM_LAST
AnnaBridge	189:f392fc9709a3	124	} FLASH_ProcedureTypeDef;
AnnaBridge	189:f392fc9709a3	125
AnnaBridge	189:f392fc9709a3	126	/**
AnnaBridge	189:f392fc9709a3	127	* @brief FLASH Cache structure definition
AnnaBridge	189:f392fc9709a3	128	*/
AnnaBridge	189:f392fc9709a3	129	typedef enum
AnnaBridge	189:f392fc9709a3	130	{
AnnaBridge	189:f392fc9709a3	131	FLASH_CACHE_DISABLED = 0,
AnnaBridge	189:f392fc9709a3	132	FLASH_CACHE_ICACHE_ENABLED,
AnnaBridge	189:f392fc9709a3	133	FLASH_CACHE_DCACHE_ENABLED,
AnnaBridge	189:f392fc9709a3	134	FLASH_CACHE_ICACHE_DCACHE_ENABLED
AnnaBridge	189:f392fc9709a3	135	} FLASH_CacheTypeDef;
AnnaBridge	189:f392fc9709a3	136
AnnaBridge	189:f392fc9709a3	137	/**
AnnaBridge	189:f392fc9709a3	138	* @brief FLASH handle Structure definition
AnnaBridge	189:f392fc9709a3	139	*/
AnnaBridge	189:f392fc9709a3	140	typedef struct
AnnaBridge	189:f392fc9709a3	141	{
AnnaBridge	189:f392fc9709a3	142	HAL_LockTypeDef Lock; /* FLASH locking object */
AnnaBridge	189:f392fc9709a3	143	__IO uint32_t ErrorCode; /* FLASH error code */
AnnaBridge	189:f392fc9709a3	144	__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
AnnaBridge	189:f392fc9709a3	145	__IO uint32_t Address; /* Internal variable to save address selected for program in IT context */
AnnaBridge	189:f392fc9709a3	146	__IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */
AnnaBridge	189:f392fc9709a3	147	__IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
AnnaBridge	189:f392fc9709a3	148	__IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
AnnaBridge	189:f392fc9709a3	149	__IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
AnnaBridge	189:f392fc9709a3	150	}FLASH_ProcessTypeDef;
AnnaBridge	189:f392fc9709a3	151
AnnaBridge	189:f392fc9709a3	152	/**
AnnaBridge	189:f392fc9709a3	153	* @}
AnnaBridge	189:f392fc9709a3	154	*/
AnnaBridge	189:f392fc9709a3	155
AnnaBridge	189:f392fc9709a3	156	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	157	/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
AnnaBridge	189:f392fc9709a3	158	* @{
AnnaBridge	189:f392fc9709a3	159	*/
AnnaBridge	189:f392fc9709a3	160
AnnaBridge	189:f392fc9709a3	161	/** @defgroup FLASH_Error FLASH Error
AnnaBridge	189:f392fc9709a3	162	* @{
AnnaBridge	189:f392fc9709a3	163	*/
AnnaBridge	189:f392fc9709a3	164	#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000)
AnnaBridge	189:f392fc9709a3	165	#define HAL_FLASH_ERROR_OP ((uint32_t)0x00000001)
AnnaBridge	189:f392fc9709a3	166	#define HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002)
AnnaBridge	189:f392fc9709a3	167	#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004)
AnnaBridge	189:f392fc9709a3	168	#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008)
AnnaBridge	189:f392fc9709a3	169	#define HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010)
AnnaBridge	189:f392fc9709a3	170	#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020)
AnnaBridge	189:f392fc9709a3	171	#define HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040)
AnnaBridge	189:f392fc9709a3	172	#define HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080)
AnnaBridge	189:f392fc9709a3	173	#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000100)
AnnaBridge	189:f392fc9709a3	174	#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200)
AnnaBridge	189:f392fc9709a3	175	#define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400)
AnnaBridge	189:f392fc9709a3	176	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| \
AnnaBridge	189:f392fc9709a3	177	defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	189:f392fc9709a3	178	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	179	#define HAL_FLASH_ERROR_PEMPTY ((uint32_t)0x00000800)
AnnaBridge	189:f392fc9709a3	180	#endif
AnnaBridge	189:f392fc9709a3	181	/**
AnnaBridge	189:f392fc9709a3	182	* @}
AnnaBridge	189:f392fc9709a3	183	*/
AnnaBridge	189:f392fc9709a3	184
AnnaBridge	189:f392fc9709a3	185	/** @defgroup FLASH_Type_Erase FLASH Erase Type
AnnaBridge	189:f392fc9709a3	186	* @{
AnnaBridge	189:f392fc9709a3	187	*/
AnnaBridge	189:f392fc9709a3	188	#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /!<Pages erase only/
AnnaBridge	189:f392fc9709a3	189	#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /!<Flash mass erase activation/
AnnaBridge	189:f392fc9709a3	190	/**
AnnaBridge	189:f392fc9709a3	191	* @}
AnnaBridge	189:f392fc9709a3	192	*/
AnnaBridge	189:f392fc9709a3	193
AnnaBridge	189:f392fc9709a3	194	/** @defgroup FLASH_Banks FLASH Banks
AnnaBridge	189:f392fc9709a3	195	* @{
AnnaBridge	189:f392fc9709a3	196	*/
AnnaBridge	189:f392fc9709a3	197	#define FLASH_BANK_1 ((uint32_t)0x01) /!< Bank 1 /
AnnaBridge	189:f392fc9709a3	198	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	189:f392fc9709a3	199	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	189:f392fc9709a3	200	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	201	#define FLASH_BANK_2 ((uint32_t)0x02) /!< Bank 2 /
AnnaBridge	189:f392fc9709a3	202	#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 \| FLASH_BANK_2)) /!< Bank1 and Bank2 /
AnnaBridge	189:f392fc9709a3	203	#else
AnnaBridge	189:f392fc9709a3	204	#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1)) /!< Bank 1 /
AnnaBridge	189:f392fc9709a3	205	#endif
AnnaBridge	189:f392fc9709a3	206	/**
AnnaBridge	189:f392fc9709a3	207	* @}
AnnaBridge	189:f392fc9709a3	208	*/
AnnaBridge	189:f392fc9709a3	209
AnnaBridge	189:f392fc9709a3	210
AnnaBridge	189:f392fc9709a3	211	/** @defgroup FLASH_Type_Program FLASH Program Type
AnnaBridge	189:f392fc9709a3	212	* @{
AnnaBridge	189:f392fc9709a3	213	*/
AnnaBridge	189:f392fc9709a3	214	#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00) /!<Program a double-word (64-bit) at a specified address./
AnnaBridge	189:f392fc9709a3	215	#define FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01) /*!<Fast program a 32 row double-word (64-bit) at a specified address.
AnnaBridge	189:f392fc9709a3	216	And another 32 row double-word (64-bit) will be programmed */
AnnaBridge	189:f392fc9709a3	217	#define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02) /*!<Fast program a 32 row double-word (64-bit) at a specified address.
AnnaBridge	189:f392fc9709a3	218	And this is the last 32 row double-word (64-bit) programmed */
AnnaBridge	189:f392fc9709a3	219	/**
AnnaBridge	189:f392fc9709a3	220	* @}
AnnaBridge	189:f392fc9709a3	221	*/
AnnaBridge	189:f392fc9709a3	222
AnnaBridge	189:f392fc9709a3	223	/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
AnnaBridge	189:f392fc9709a3	224	* @{
AnnaBridge	189:f392fc9709a3	225	*/
AnnaBridge	189:f392fc9709a3	226	#define OPTIONBYTE_WRP ((uint32_t)0x01) /!< WRP option byte configuration /
AnnaBridge	189:f392fc9709a3	227	#define OPTIONBYTE_RDP ((uint32_t)0x02) /!< RDP option byte configuration /
AnnaBridge	189:f392fc9709a3	228	#define OPTIONBYTE_USER ((uint32_t)0x04) /!< USER option byte configuration /
AnnaBridge	189:f392fc9709a3	229	#define OPTIONBYTE_PCROP ((uint32_t)0x08) /!< PCROP option byte configuration /
AnnaBridge	189:f392fc9709a3	230	/**
AnnaBridge	189:f392fc9709a3	231	* @}
AnnaBridge	189:f392fc9709a3	232	*/
AnnaBridge	189:f392fc9709a3	233
AnnaBridge	189:f392fc9709a3	234	/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
AnnaBridge	189:f392fc9709a3	235	* @{
AnnaBridge	189:f392fc9709a3	236	*/
AnnaBridge	189:f392fc9709a3	237	#define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /!< Flash Bank 1 Area A /
AnnaBridge	189:f392fc9709a3	238	#define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /!< Flash Bank 1 Area B /
AnnaBridge	189:f392fc9709a3	239	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	189:f392fc9709a3	240	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	189:f392fc9709a3	241	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	242	#define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /!< Flash Bank 2 Area A /
AnnaBridge	189:f392fc9709a3	243	#define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /!< Flash Bank 2 Area B /
AnnaBridge	189:f392fc9709a3	244	#endif
AnnaBridge	189:f392fc9709a3	245	/**
AnnaBridge	189:f392fc9709a3	246	* @}
AnnaBridge	189:f392fc9709a3	247	*/
AnnaBridge	189:f392fc9709a3	248
AnnaBridge	189:f392fc9709a3	249	/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
AnnaBridge	189:f392fc9709a3	250	* @{
AnnaBridge	189:f392fc9709a3	251	*/
AnnaBridge	189:f392fc9709a3	252	#define OB_RDP_LEVEL_0 ((uint32_t)0xAA)
AnnaBridge	189:f392fc9709a3	253	#define OB_RDP_LEVEL_1 ((uint32_t)0xBB)
AnnaBridge	189:f392fc9709a3	254	#define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2
AnnaBridge	189:f392fc9709a3	255	it's no more possible to go back to level 1 or 0 */
AnnaBridge	189:f392fc9709a3	256	/**
AnnaBridge	189:f392fc9709a3	257	* @}
AnnaBridge	189:f392fc9709a3	258	*/
AnnaBridge	189:f392fc9709a3	259
AnnaBridge	189:f392fc9709a3	260	/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
AnnaBridge	189:f392fc9709a3	261	* @{
AnnaBridge	189:f392fc9709a3	262	*/
AnnaBridge	189:f392fc9709a3	263	#define OB_USER_BOR_LEV ((uint32_t)0x0001) /!< BOR reset Level /
AnnaBridge	189:f392fc9709a3	264	#define OB_USER_nRST_STOP ((uint32_t)0x0002) /!< Reset generated when entering the stop mode /
AnnaBridge	189:f392fc9709a3	265	#define OB_USER_nRST_STDBY ((uint32_t)0x0004) /!< Reset generated when entering the standby mode /
AnnaBridge	189:f392fc9709a3	266	#define OB_USER_IWDG_SW ((uint32_t)0x0008) /!< Independent watchdog selection /
AnnaBridge	189:f392fc9709a3	267	#define OB_USER_IWDG_STOP ((uint32_t)0x0010) /!< Independent watchdog counter freeze in stop mode /
AnnaBridge	189:f392fc9709a3	268	#define OB_USER_IWDG_STDBY ((uint32_t)0x0020) /!< Independent watchdog counter freeze in standby mode /
AnnaBridge	189:f392fc9709a3	269	#define OB_USER_WWDG_SW ((uint32_t)0x0040) /!< Window watchdog selection /
AnnaBridge	189:f392fc9709a3	270	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	189:f392fc9709a3	271	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	189:f392fc9709a3	272	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	273	#define OB_USER_BFB2 ((uint32_t)0x0080) /!< Dual-bank boot /
AnnaBridge	189:f392fc9709a3	274	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	275	#define OB_USER_DUALBANK ((uint32_t)0x0100) /!< Dual-Bank on 1MB or 512kB Flash memory devices /
AnnaBridge	189:f392fc9709a3	276	#else
AnnaBridge	189:f392fc9709a3	277	#define OB_USER_DUALBANK ((uint32_t)0x0100) /!< Dual-Bank on 512KB or 256KB Flash memory devices /
AnnaBridge	189:f392fc9709a3	278	#endif
AnnaBridge	189:f392fc9709a3	279	#endif
AnnaBridge	189:f392fc9709a3	280	#define OB_USER_nBOOT1 ((uint32_t)0x0200) /!< Boot configuration /
AnnaBridge	189:f392fc9709a3	281	#define OB_USER_SRAM2_PE ((uint32_t)0x0400) /!< SRAM2 parity check enable /
AnnaBridge	189:f392fc9709a3	282	#define OB_USER_SRAM2_RST ((uint32_t)0x0800) /!< SRAM2 Erase when system reset /
AnnaBridge	189:f392fc9709a3	283	#define OB_USER_nRST_SHDW ((uint32_t)0x1000) /!< Reset generated when entering the shutdown mode /
AnnaBridge	189:f392fc9709a3	284	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| \
AnnaBridge	189:f392fc9709a3	285	defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| \
AnnaBridge	189:f392fc9709a3	286	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	189:f392fc9709a3	287	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	288	#define OB_USER_nSWBOOT0 ((uint32_t)0x2000) /!< Software BOOT0 /
AnnaBridge	189:f392fc9709a3	289	#define OB_USER_nBOOT0 ((uint32_t)0x4000) /!< nBOOT0 option bit /
AnnaBridge	189:f392fc9709a3	290	#endif
AnnaBridge	189:f392fc9709a3	291	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	292	#define OB_USER_DBANK ((uint32_t)0x8000) /!< Single bank with 128-bits data or two banks with 64-bits data /
AnnaBridge	189:f392fc9709a3	293	#endif
AnnaBridge	189:f392fc9709a3	294	/**
AnnaBridge	189:f392fc9709a3	295	* @}
AnnaBridge	189:f392fc9709a3	296	*/
AnnaBridge	189:f392fc9709a3	297
AnnaBridge	189:f392fc9709a3	298	/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
AnnaBridge	189:f392fc9709a3	299	* @{
AnnaBridge	189:f392fc9709a3	300	*/
AnnaBridge	189:f392fc9709a3	301	#define OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0) /!< Reset level threshold is around 1.7V /
AnnaBridge	189:f392fc9709a3	302	#define OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1) /!< Reset level threshold is around 2.0V /
AnnaBridge	189:f392fc9709a3	303	#define OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2) /!< Reset level threshold is around 2.2V /
AnnaBridge	189:f392fc9709a3	304	#define OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3) /!< Reset level threshold is around 2.5V /
AnnaBridge	189:f392fc9709a3	305	#define OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4) /!< Reset level threshold is around 2.8V /
AnnaBridge	189:f392fc9709a3	306	/**
AnnaBridge	189:f392fc9709a3	307	* @}
AnnaBridge	189:f392fc9709a3	308	*/
AnnaBridge	189:f392fc9709a3	309
AnnaBridge	189:f392fc9709a3	310	/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
AnnaBridge	189:f392fc9709a3	311	* @{
AnnaBridge	189:f392fc9709a3	312	*/
AnnaBridge	189:f392fc9709a3	313	#define OB_STOP_RST ((uint32_t)0x0000) /!< Reset generated when entering the stop mode /
AnnaBridge	189:f392fc9709a3	314	#define OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP) /!< No reset generated when entering the stop mode /
AnnaBridge	189:f392fc9709a3	315	/**
AnnaBridge	189:f392fc9709a3	316	* @}
AnnaBridge	189:f392fc9709a3	317	*/
AnnaBridge	189:f392fc9709a3	318
AnnaBridge	189:f392fc9709a3	319	/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
AnnaBridge	189:f392fc9709a3	320	* @{
AnnaBridge	189:f392fc9709a3	321	*/
AnnaBridge	189:f392fc9709a3	322	#define OB_STANDBY_RST ((uint32_t)0x0000) /!< Reset generated when entering the standby mode /
AnnaBridge	189:f392fc9709a3	323	#define OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY) /!< No reset generated when entering the standby mode /
AnnaBridge	189:f392fc9709a3	324	/**
AnnaBridge	189:f392fc9709a3	325	* @}
AnnaBridge	189:f392fc9709a3	326	*/
AnnaBridge	189:f392fc9709a3	327
AnnaBridge	189:f392fc9709a3	328	/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
AnnaBridge	189:f392fc9709a3	329	* @{
AnnaBridge	189:f392fc9709a3	330	*/
AnnaBridge	189:f392fc9709a3	331	#define OB_SHUTDOWN_RST ((uint32_t)0x0000) /!< Reset generated when entering the shutdown mode /
AnnaBridge	189:f392fc9709a3	332	#define OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW) /!< No reset generated when entering the shutdown mode /
AnnaBridge	189:f392fc9709a3	333	/**
AnnaBridge	189:f392fc9709a3	334	* @}
AnnaBridge	189:f392fc9709a3	335	*/
AnnaBridge	189:f392fc9709a3	336
AnnaBridge	189:f392fc9709a3	337	/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
AnnaBridge	189:f392fc9709a3	338	* @{
AnnaBridge	189:f392fc9709a3	339	*/
AnnaBridge	189:f392fc9709a3	340	#define OB_IWDG_HW ((uint32_t)0x00000) /!< Hardware independent watchdog /
AnnaBridge	189:f392fc9709a3	341	#define OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW) /!< Software independent watchdog /
AnnaBridge	189:f392fc9709a3	342	/**
AnnaBridge	189:f392fc9709a3	343	* @}
AnnaBridge	189:f392fc9709a3	344	*/
AnnaBridge	189:f392fc9709a3	345
AnnaBridge	189:f392fc9709a3	346	/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
AnnaBridge	189:f392fc9709a3	347	* @{
AnnaBridge	189:f392fc9709a3	348	*/
AnnaBridge	189:f392fc9709a3	349	#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000) /!< Independent watchdog counter is frozen in Stop mode /
AnnaBridge	189:f392fc9709a3	350	#define OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP) /!< Independent watchdog counter is running in Stop mode /
AnnaBridge	189:f392fc9709a3	351	/**
AnnaBridge	189:f392fc9709a3	352	* @}
AnnaBridge	189:f392fc9709a3	353	*/
AnnaBridge	189:f392fc9709a3	354
AnnaBridge	189:f392fc9709a3	355	/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
AnnaBridge	189:f392fc9709a3	356	* @{
AnnaBridge	189:f392fc9709a3	357	*/
AnnaBridge	189:f392fc9709a3	358	#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000) /!< Independent watchdog counter is frozen in Standby mode /
AnnaBridge	189:f392fc9709a3	359	#define OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY) /!< Independent watchdog counter is running in Standby mode /
AnnaBridge	189:f392fc9709a3	360	/**
AnnaBridge	189:f392fc9709a3	361	* @}
AnnaBridge	189:f392fc9709a3	362	*/
AnnaBridge	189:f392fc9709a3	363
AnnaBridge	189:f392fc9709a3	364	/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
AnnaBridge	189:f392fc9709a3	365	* @{
AnnaBridge	189:f392fc9709a3	366	*/
AnnaBridge	189:f392fc9709a3	367	#define OB_WWDG_HW ((uint32_t)0x00000) /!< Hardware window watchdog /
AnnaBridge	189:f392fc9709a3	368	#define OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW) /!< Software window watchdog /
AnnaBridge	189:f392fc9709a3	369	/**
AnnaBridge	189:f392fc9709a3	370	* @}
AnnaBridge	189:f392fc9709a3	371	*/
AnnaBridge	189:f392fc9709a3	372
AnnaBridge	189:f392fc9709a3	373	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	189:f392fc9709a3	374	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	189:f392fc9709a3	375	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	376	/** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
AnnaBridge	189:f392fc9709a3	377	* @{
AnnaBridge	189:f392fc9709a3	378	*/
AnnaBridge	189:f392fc9709a3	379	#define OB_BFB2_DISABLE ((uint32_t)0x000000) /!< Dual-bank boot disable /
AnnaBridge	189:f392fc9709a3	380	#define OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2) /!< Dual-bank boot enable /
AnnaBridge	189:f392fc9709a3	381	/**
AnnaBridge	189:f392fc9709a3	382	* @}
AnnaBridge	189:f392fc9709a3	383	*/
AnnaBridge	189:f392fc9709a3	384	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	385	/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type
AnnaBridge	189:f392fc9709a3	386	* @{
AnnaBridge	189:f392fc9709a3	387	*/
AnnaBridge	189:f392fc9709a3	388	#define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /!< 1 MB/512 kB Single-bank Flash /
AnnaBridge	189:f392fc9709a3	389	#define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DB1M) /!< 1 MB/512 kB Dual-bank Flash /
AnnaBridge	189:f392fc9709a3	390	/**
AnnaBridge	189:f392fc9709a3	391	* @}
AnnaBridge	189:f392fc9709a3	392	*/
AnnaBridge	189:f392fc9709a3	393	#else
AnnaBridge	189:f392fc9709a3	394	/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type
AnnaBridge	189:f392fc9709a3	395	* @{
AnnaBridge	189:f392fc9709a3	396	*/
AnnaBridge	189:f392fc9709a3	397	#define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /!< 256 KB/512 KB Single-bank Flash /
AnnaBridge	189:f392fc9709a3	398	#define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK) /!< 256 KB/512 KB Dual-bank Flash /
AnnaBridge	189:f392fc9709a3	399	/**
AnnaBridge	189:f392fc9709a3	400	* @}
AnnaBridge	189:f392fc9709a3	401	*/
AnnaBridge	189:f392fc9709a3	402	#endif
AnnaBridge	189:f392fc9709a3	403	#endif
AnnaBridge	189:f392fc9709a3	404
AnnaBridge	189:f392fc9709a3	405	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	406	/** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type
AnnaBridge	189:f392fc9709a3	407	* @{
AnnaBridge	189:f392fc9709a3	408	*/
AnnaBridge	189:f392fc9709a3	409	#define OB_DBANK_128_BITS ((uint32_t)0x000000) /!< Single-bank with 128-bits data /
AnnaBridge	189:f392fc9709a3	410	#define OB_DBANK_64_BITS ((uint32_t)FLASH_OPTR_DBANK) /!< Dual-bank with 64-bits data /
AnnaBridge	189:f392fc9709a3	411	#endif
AnnaBridge	189:f392fc9709a3	412	/**
AnnaBridge	189:f392fc9709a3	413	* @}
AnnaBridge	189:f392fc9709a3	414	*/
AnnaBridge	189:f392fc9709a3	415	/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
AnnaBridge	189:f392fc9709a3	416	* @{
AnnaBridge	189:f392fc9709a3	417	*/
AnnaBridge	189:f392fc9709a3	418	#define OB_BOOT1_SRAM ((uint32_t)0x000000) /!< Embedded SRAM1 is selected as boot space (if BOOT0=1) /
AnnaBridge	189:f392fc9709a3	419	#define OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1) /!< System memory is selected as boot space (if BOOT0=1) /
AnnaBridge	189:f392fc9709a3	420	/**
AnnaBridge	189:f392fc9709a3	421	* @}
AnnaBridge	189:f392fc9709a3	422	*/
AnnaBridge	189:f392fc9709a3	423
AnnaBridge	189:f392fc9709a3	424	/** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type
AnnaBridge	189:f392fc9709a3	425	* @{
AnnaBridge	189:f392fc9709a3	426	*/
AnnaBridge	189:f392fc9709a3	427	#define OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000) /!< SRAM2 parity check enable /
AnnaBridge	189:f392fc9709a3	428	#define OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE) /!< SRAM2 parity check disable /
AnnaBridge	189:f392fc9709a3	429	/**
AnnaBridge	189:f392fc9709a3	430	* @}
AnnaBridge	189:f392fc9709a3	431	*/
AnnaBridge	189:f392fc9709a3	432
AnnaBridge	189:f392fc9709a3	433	/** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type
AnnaBridge	189:f392fc9709a3	434	* @{
AnnaBridge	189:f392fc9709a3	435	*/
AnnaBridge	189:f392fc9709a3	436	#define OB_SRAM2_RST_ERASE ((uint32_t)0x0000000) /!< SRAM2 erased when a system reset occurs /
AnnaBridge	189:f392fc9709a3	437	#define OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST) /!< SRAM2 is not erased when a system reset occurs /
AnnaBridge	189:f392fc9709a3	438	/**
AnnaBridge	189:f392fc9709a3	439	* @}
AnnaBridge	189:f392fc9709a3	440	*/
AnnaBridge	189:f392fc9709a3	441
AnnaBridge	189:f392fc9709a3	442	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| \
AnnaBridge	189:f392fc9709a3	443	defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| \
AnnaBridge	189:f392fc9709a3	444	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	189:f392fc9709a3	445	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	446	/** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
AnnaBridge	189:f392fc9709a3	447	* @{
AnnaBridge	189:f392fc9709a3	448	*/
AnnaBridge	189:f392fc9709a3	449	#define OB_BOOT0_FROM_OB ((uint32_t)0x0000000) /!< BOOT0 taken from the option bit nBOOT0 /
AnnaBridge	189:f392fc9709a3	450	#define OB_BOOT0_FROM_PIN ((uint32_t)FLASH_OPTR_nSWBOOT0) /!< BOOT0 taken from PH3/BOOT0 pin /
AnnaBridge	189:f392fc9709a3	451	/**
AnnaBridge	189:f392fc9709a3	452	* @}
AnnaBridge	189:f392fc9709a3	453	*/
AnnaBridge	189:f392fc9709a3	454
AnnaBridge	189:f392fc9709a3	455	/** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
AnnaBridge	189:f392fc9709a3	456	* @{
AnnaBridge	189:f392fc9709a3	457	*/
AnnaBridge	189:f392fc9709a3	458	#define OB_BOOT0_RESET ((uint32_t)0x0000000) /!< nBOOT0 = 0 /
AnnaBridge	189:f392fc9709a3	459	#define OB_BOOT0_SET ((uint32_t)FLASH_OPTR_nBOOT0) /!< nBOOT0 = 1 /
AnnaBridge	189:f392fc9709a3	460	/**
AnnaBridge	189:f392fc9709a3	461	* @}
AnnaBridge	189:f392fc9709a3	462	*/
AnnaBridge	189:f392fc9709a3	463	#endif
AnnaBridge	189:f392fc9709a3	464
AnnaBridge	189:f392fc9709a3	465	/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
AnnaBridge	189:f392fc9709a3	466	* @{
AnnaBridge	189:f392fc9709a3	467	*/
AnnaBridge	189:f392fc9709a3	468	#define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000) /*!< PCROP area is not erased when the RDP level
AnnaBridge	189:f392fc9709a3	469	is decreased from Level 1 to Level 0 */
AnnaBridge	189:f392fc9709a3	470	#define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is
AnnaBridge	189:f392fc9709a3	471	decreased from Level 1 to Level 0 (full mass erase) */
AnnaBridge	189:f392fc9709a3	472	/**
AnnaBridge	189:f392fc9709a3	473	* @}
AnnaBridge	189:f392fc9709a3	474	*/
AnnaBridge	189:f392fc9709a3	475
AnnaBridge	189:f392fc9709a3	476	/** @defgroup FLASH_Latency FLASH Latency
AnnaBridge	189:f392fc9709a3	477	* @{
AnnaBridge	189:f392fc9709a3	478	*/
AnnaBridge	189:f392fc9709a3	479	#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /!< FLASH Zero wait state /
AnnaBridge	189:f392fc9709a3	480	#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /!< FLASH One wait state /
AnnaBridge	189:f392fc9709a3	481	#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /!< FLASH Two wait states /
AnnaBridge	189:f392fc9709a3	482	#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /!< FLASH Three wait states /
AnnaBridge	189:f392fc9709a3	483	#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /!< FLASH Four wait states /
AnnaBridge	189:f392fc9709a3	484	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	485	#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /!< FLASH Five wait state /
AnnaBridge	189:f392fc9709a3	486	#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /!< FLASH Six wait state /
AnnaBridge	189:f392fc9709a3	487	#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /!< FLASH Seven wait states /
AnnaBridge	189:f392fc9709a3	488	#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /!< FLASH Eight wait states /
AnnaBridge	189:f392fc9709a3	489	#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /!< FLASH Nine wait states /
AnnaBridge	189:f392fc9709a3	490	#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /!< FLASH Ten wait state /
AnnaBridge	189:f392fc9709a3	491	#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /!< FLASH Eleven wait state /
AnnaBridge	189:f392fc9709a3	492	#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /!< FLASH Twelve wait states /
AnnaBridge	189:f392fc9709a3	493	#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /!< FLASH Thirteen wait states /
AnnaBridge	189:f392fc9709a3	494	#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /!< FLASH Fourteen wait states /
AnnaBridge	189:f392fc9709a3	495	#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /!< FLASH Fifteen wait states /
AnnaBridge	189:f392fc9709a3	496	#endif
AnnaBridge	189:f392fc9709a3	497	/**
AnnaBridge	189:f392fc9709a3	498	* @}
AnnaBridge	189:f392fc9709a3	499	*/
AnnaBridge	189:f392fc9709a3	500
AnnaBridge	189:f392fc9709a3	501	/** @defgroup FLASH_Keys FLASH Keys
AnnaBridge	189:f392fc9709a3	502	* @{
AnnaBridge	189:f392fc9709a3	503	*/
AnnaBridge	189:f392fc9709a3	504	#define FLASH_KEY1 0x45670123U /!< Flash key1 /
AnnaBridge	189:f392fc9709a3	505	#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1
AnnaBridge	189:f392fc9709a3	506	to unlock the FLASH registers access */
AnnaBridge	189:f392fc9709a3	507
AnnaBridge	189:f392fc9709a3	508	#define FLASH_PDKEY1 0x04152637U /!< Flash power down key1 /
AnnaBridge	189:f392fc9709a3	509	#define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
AnnaBridge	189:f392fc9709a3	510	to unlock the RUN_PD bit in FLASH_ACR */
AnnaBridge	189:f392fc9709a3	511
AnnaBridge	189:f392fc9709a3	512	#define FLASH_OPTKEY1 0x08192A3BU /!< Flash option byte key1 /
AnnaBridge	189:f392fc9709a3	513	#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1
AnnaBridge	189:f392fc9709a3	514	to allow option bytes operations */
AnnaBridge	189:f392fc9709a3	515	/**
AnnaBridge	189:f392fc9709a3	516	* @}
AnnaBridge	189:f392fc9709a3	517	*/
AnnaBridge	189:f392fc9709a3	518
AnnaBridge	189:f392fc9709a3	519	/** @defgroup FLASH_Flags FLASH Flags Definition
AnnaBridge	189:f392fc9709a3	520	* @{
AnnaBridge	189:f392fc9709a3	521	*/
AnnaBridge	189:f392fc9709a3	522	#define FLASH_FLAG_EOP FLASH_SR_EOP /!< FLASH End of operation flag /
AnnaBridge	189:f392fc9709a3	523	#define FLASH_FLAG_OPERR FLASH_SR_OPERR /!< FLASH Operation error flag /
AnnaBridge	189:f392fc9709a3	524	#define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /!< FLASH Programming error flag /
AnnaBridge	189:f392fc9709a3	525	#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /!< FLASH Write protection error flag /
AnnaBridge	189:f392fc9709a3	526	#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /!< FLASH Programming alignment error flag /
AnnaBridge	189:f392fc9709a3	527	#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /!< FLASH Size error flag /
AnnaBridge	189:f392fc9709a3	528	#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /!< FLASH Programming sequence error flag /
AnnaBridge	189:f392fc9709a3	529	#define FLASH_FLAG_MISERR FLASH_SR_MISERR /!< FLASH Fast programming data miss error flag /
AnnaBridge	189:f392fc9709a3	530	#define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /!< FLASH Fast programming error flag /
AnnaBridge	189:f392fc9709a3	531	#define FLASH_FLAG_RDERR FLASH_SR_RDERR /!< FLASH PCROP read error flag /
AnnaBridge	189:f392fc9709a3	532	#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /!< FLASH Option validity error flag /
AnnaBridge	189:f392fc9709a3	533	#define FLASH_FLAG_BSY FLASH_SR_BSY /!< FLASH Busy flag /
AnnaBridge	189:f392fc9709a3	534	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| \
AnnaBridge	189:f392fc9709a3	535	defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	189:f392fc9709a3	536	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	537	#define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /!< FLASH Program empty /
AnnaBridge	189:f392fc9709a3	538	#endif
AnnaBridge	189:f392fc9709a3	539	#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /!< FLASH ECC correction /
AnnaBridge	189:f392fc9709a3	540	#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /!< FLASH ECC detection /
AnnaBridge	189:f392fc9709a3	541
AnnaBridge	189:f392fc9709a3	542	#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR \| FLASH_FLAG_PROGERR \| FLASH_FLAG_WRPERR \| \
AnnaBridge	189:f392fc9709a3	543	FLASH_FLAG_PGAERR \| FLASH_FLAG_SIZERR \| FLASH_FLAG_PGSERR \| \
AnnaBridge	189:f392fc9709a3	544	FLASH_FLAG_MISERR \| FLASH_FLAG_FASTERR \| FLASH_FLAG_RDERR \| \
AnnaBridge	189:f392fc9709a3	545	FLASH_FLAG_OPTVERR \| FLASH_FLAG_ECCD)
AnnaBridge	189:f392fc9709a3	546	/**
AnnaBridge	189:f392fc9709a3	547	* @}
AnnaBridge	189:f392fc9709a3	548	*/
AnnaBridge	189:f392fc9709a3	549
AnnaBridge	189:f392fc9709a3	550	/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
AnnaBridge	189:f392fc9709a3	551	* @brief FLASH Interrupt definition
AnnaBridge	189:f392fc9709a3	552	* @{
AnnaBridge	189:f392fc9709a3	553	*/
AnnaBridge	189:f392fc9709a3	554	#define FLASH_IT_EOP FLASH_CR_EOPIE /!< End of FLASH Operation Interrupt source /
AnnaBridge	189:f392fc9709a3	555	#define FLASH_IT_OPERR FLASH_CR_ERRIE /!< Error Interrupt source /
AnnaBridge	189:f392fc9709a3	556	#define FLASH_IT_RDERR FLASH_CR_RDERRIE /!< PCROP Read Error Interrupt source/
AnnaBridge	189:f392fc9709a3	557	#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /!< ECC Correction Interrupt source /
AnnaBridge	189:f392fc9709a3	558	/**
AnnaBridge	189:f392fc9709a3	559	* @}
AnnaBridge	189:f392fc9709a3	560	*/
AnnaBridge	189:f392fc9709a3	561
AnnaBridge	189:f392fc9709a3	562	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	563	/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
AnnaBridge	189:f392fc9709a3	564	* @brief macros to control FLASH features
AnnaBridge	189:f392fc9709a3	565	* @{
AnnaBridge	189:f392fc9709a3	566	*/
AnnaBridge	189:f392fc9709a3	567
AnnaBridge	189:f392fc9709a3	568	/**
AnnaBridge	189:f392fc9709a3	569	* @brief Set the FLASH Latency.
AnnaBridge	189:f392fc9709a3	570	* @param __LATENCY__: FLASH Latency
AnnaBridge	189:f392fc9709a3	571	* This parameter can be one of the following values :
AnnaBridge	189:f392fc9709a3	572	* @arg FLASH_LATENCY_0: FLASH Zero wait state
AnnaBridge	189:f392fc9709a3	573	* @arg FLASH_LATENCY_1: FLASH One wait state
AnnaBridge	189:f392fc9709a3	574	* @arg FLASH_LATENCY_2: FLASH Two wait states
AnnaBridge	189:f392fc9709a3	575	* @arg FLASH_LATENCY_3: FLASH Three wait states
AnnaBridge	189:f392fc9709a3	576	* @arg FLASH_LATENCY_4: FLASH Four wait states
AnnaBridge	189:f392fc9709a3	577	* @retval None
AnnaBridge	189:f392fc9709a3	578	*/
AnnaBridge	189:f392fc9709a3	579	#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))
AnnaBridge	189:f392fc9709a3	580
AnnaBridge	189:f392fc9709a3	581	/**
AnnaBridge	189:f392fc9709a3	582	* @brief Get the FLASH Latency.
AnnaBridge	189:f392fc9709a3	583	* @retval FLASH Latency
AnnaBridge	189:f392fc9709a3	584	* This parameter can be one of the following values :
AnnaBridge	189:f392fc9709a3	585	* @arg FLASH_LATENCY_0: FLASH Zero wait state
AnnaBridge	189:f392fc9709a3	586	* @arg FLASH_LATENCY_1: FLASH One wait state
AnnaBridge	189:f392fc9709a3	587	* @arg FLASH_LATENCY_2: FLASH Two wait states
AnnaBridge	189:f392fc9709a3	588	* @arg FLASH_LATENCY_3: FLASH Three wait states
AnnaBridge	189:f392fc9709a3	589	* @arg FLASH_LATENCY_4: FLASH Four wait states
AnnaBridge	189:f392fc9709a3	590	*/
AnnaBridge	189:f392fc9709a3	591	#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
AnnaBridge	189:f392fc9709a3	592
AnnaBridge	189:f392fc9709a3	593	/**
AnnaBridge	189:f392fc9709a3	594	* @brief Enable the FLASH prefetch buffer.
AnnaBridge	189:f392fc9709a3	595	* @retval None
AnnaBridge	189:f392fc9709a3	596	*/
AnnaBridge	189:f392fc9709a3	597	#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
AnnaBridge	189:f392fc9709a3	598
AnnaBridge	189:f392fc9709a3	599	/**
AnnaBridge	189:f392fc9709a3	600	* @brief Disable the FLASH prefetch buffer.
AnnaBridge	189:f392fc9709a3	601	* @retval None
AnnaBridge	189:f392fc9709a3	602	*/
AnnaBridge	189:f392fc9709a3	603	#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
AnnaBridge	189:f392fc9709a3	604
AnnaBridge	189:f392fc9709a3	605	/**
AnnaBridge	189:f392fc9709a3	606	* @brief Enable the FLASH instruction cache.
AnnaBridge	189:f392fc9709a3	607	* @retval none
AnnaBridge	189:f392fc9709a3	608	*/
AnnaBridge	189:f392fc9709a3	609	#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
AnnaBridge	189:f392fc9709a3	610
AnnaBridge	189:f392fc9709a3	611	/**
AnnaBridge	189:f392fc9709a3	612	* @brief Disable the FLASH instruction cache.
AnnaBridge	189:f392fc9709a3	613	* @retval none
AnnaBridge	189:f392fc9709a3	614	*/
AnnaBridge	189:f392fc9709a3	615	#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
AnnaBridge	189:f392fc9709a3	616
AnnaBridge	189:f392fc9709a3	617	/**
AnnaBridge	189:f392fc9709a3	618	* @brief Enable the FLASH data cache.
AnnaBridge	189:f392fc9709a3	619	* @retval none
AnnaBridge	189:f392fc9709a3	620	*/
AnnaBridge	189:f392fc9709a3	621	#define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
AnnaBridge	189:f392fc9709a3	622
AnnaBridge	189:f392fc9709a3	623	/**
AnnaBridge	189:f392fc9709a3	624	* @brief Disable the FLASH data cache.
AnnaBridge	189:f392fc9709a3	625	* @retval none
AnnaBridge	189:f392fc9709a3	626	*/
AnnaBridge	189:f392fc9709a3	627	#define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
AnnaBridge	189:f392fc9709a3	628
AnnaBridge	189:f392fc9709a3	629	/**
AnnaBridge	189:f392fc9709a3	630	* @brief Reset the FLASH instruction Cache.
AnnaBridge	189:f392fc9709a3	631	* @note This function must be used only when the Instruction Cache is disabled.
AnnaBridge	189:f392fc9709a3	632	* @retval None
AnnaBridge	189:f392fc9709a3	633	*/
AnnaBridge	189:f392fc9709a3	634	#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
AnnaBridge	189:f392fc9709a3	635	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
AnnaBridge	189:f392fc9709a3	636	} while (0)
AnnaBridge	189:f392fc9709a3	637
AnnaBridge	189:f392fc9709a3	638	/**
AnnaBridge	189:f392fc9709a3	639	* @brief Reset the FLASH data Cache.
AnnaBridge	189:f392fc9709a3	640	* @note This function must be used only when the data Cache is disabled.
AnnaBridge	189:f392fc9709a3	641	* @retval None
AnnaBridge	189:f392fc9709a3	642	*/
AnnaBridge	189:f392fc9709a3	643	#define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
AnnaBridge	189:f392fc9709a3	644	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
AnnaBridge	189:f392fc9709a3	645	} while (0)
AnnaBridge	189:f392fc9709a3	646
AnnaBridge	189:f392fc9709a3	647	/**
AnnaBridge	189:f392fc9709a3	648	* @brief Enable the FLASH power down during Low-power run mode.
AnnaBridge	189:f392fc9709a3	649	* @note Writing this bit to 0 this bit, automatically the keys are
AnnaBridge	189:f392fc9709a3	650	* loss and a new unlock sequence is necessary to re-write it to 1.
AnnaBridge	189:f392fc9709a3	651	*/
AnnaBridge	189:f392fc9709a3	652	#define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
AnnaBridge	189:f392fc9709a3	653	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
AnnaBridge	189:f392fc9709a3	654	SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
AnnaBridge	189:f392fc9709a3	655	} while (0)
AnnaBridge	189:f392fc9709a3	656
AnnaBridge	189:f392fc9709a3	657	/**
AnnaBridge	189:f392fc9709a3	658	* @brief Disable the FLASH power down during Low-power run mode.
AnnaBridge	189:f392fc9709a3	659	* @note Writing this bit to 0 this bit, automatically the keys are
AnnaBridge	189:f392fc9709a3	660	* loss and a new unlock sequence is necessary to re-write it to 1.
AnnaBridge	189:f392fc9709a3	661	*/
AnnaBridge	189:f392fc9709a3	662	#define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
AnnaBridge	189:f392fc9709a3	663	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
AnnaBridge	189:f392fc9709a3	664	CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
AnnaBridge	189:f392fc9709a3	665	} while (0)
AnnaBridge	189:f392fc9709a3	666
AnnaBridge	189:f392fc9709a3	667	/**
AnnaBridge	189:f392fc9709a3	668	* @brief Enable the FLASH power down during Low-Power sleep mode
AnnaBridge	189:f392fc9709a3	669	* @retval none
AnnaBridge	189:f392fc9709a3	670	*/
AnnaBridge	189:f392fc9709a3	671	#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
AnnaBridge	189:f392fc9709a3	672
AnnaBridge	189:f392fc9709a3	673	/**
AnnaBridge	189:f392fc9709a3	674	* @brief Disable the FLASH power down during Low-Power sleep mode
AnnaBridge	189:f392fc9709a3	675	* @retval none
AnnaBridge	189:f392fc9709a3	676	*/
AnnaBridge	189:f392fc9709a3	677	#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
AnnaBridge	189:f392fc9709a3	678
AnnaBridge	189:f392fc9709a3	679	/**
AnnaBridge	189:f392fc9709a3	680	* @}
AnnaBridge	189:f392fc9709a3	681	*/
AnnaBridge	189:f392fc9709a3	682
AnnaBridge	189:f392fc9709a3	683	/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
AnnaBridge	189:f392fc9709a3	684	* @brief macros to handle FLASH interrupts
AnnaBridge	189:f392fc9709a3	685	* @{
AnnaBridge	189:f392fc9709a3	686	*/
AnnaBridge	189:f392fc9709a3	687
AnnaBridge	189:f392fc9709a3	688	/**
AnnaBridge	189:f392fc9709a3	689	* @brief Enable the specified FLASH interrupt.
AnnaBridge	189:f392fc9709a3	690	* @param __INTERRUPT__: FLASH interrupt
AnnaBridge	189:f392fc9709a3	691	* This parameter can be any combination of the following values:
AnnaBridge	189:f392fc9709a3	692	* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
AnnaBridge	189:f392fc9709a3	693	* @arg FLASH_IT_OPERR: Error Interrupt
AnnaBridge	189:f392fc9709a3	694	* @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
AnnaBridge	189:f392fc9709a3	695	* @arg FLASH_IT_ECCC: ECC Correction Interrupt
AnnaBridge	189:f392fc9709a3	696	* @retval none
AnnaBridge	189:f392fc9709a3	697	*/
AnnaBridge	189:f392fc9709a3	698	#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
AnnaBridge	189:f392fc9709a3	699	if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
AnnaBridge	189:f392fc9709a3	700	} while(0)
AnnaBridge	189:f392fc9709a3	701
AnnaBridge	189:f392fc9709a3	702	/**
AnnaBridge	189:f392fc9709a3	703	* @brief Disable the specified FLASH interrupt.
AnnaBridge	189:f392fc9709a3	704	* @param __INTERRUPT__: FLASH interrupt
AnnaBridge	189:f392fc9709a3	705	* This parameter can be any combination of the following values:
AnnaBridge	189:f392fc9709a3	706	* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
AnnaBridge	189:f392fc9709a3	707	* @arg FLASH_IT_OPERR: Error Interrupt
AnnaBridge	189:f392fc9709a3	708	* @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
AnnaBridge	189:f392fc9709a3	709	* @arg FLASH_IT_ECCC: ECC Correction Interrupt
AnnaBridge	189:f392fc9709a3	710	* @retval none
AnnaBridge	189:f392fc9709a3	711	*/
AnnaBridge	189:f392fc9709a3	712	#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
AnnaBridge	189:f392fc9709a3	713	if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
AnnaBridge	189:f392fc9709a3	714	} while(0)
AnnaBridge	189:f392fc9709a3	715
AnnaBridge	189:f392fc9709a3	716	/**
AnnaBridge	189:f392fc9709a3	717	* @brief Check whether the specified FLASH flag is set or not.
AnnaBridge	189:f392fc9709a3	718	* @param __FLAG__: specifies the FLASH flag to check.
AnnaBridge	189:f392fc9709a3	719	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	720	* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
AnnaBridge	189:f392fc9709a3	721	* @arg FLASH_FLAG_OPERR: FLASH Operation error flag
AnnaBridge	189:f392fc9709a3	722	* @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
AnnaBridge	189:f392fc9709a3	723	* @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
AnnaBridge	189:f392fc9709a3	724	* @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
AnnaBridge	189:f392fc9709a3	725	* @arg FLASH_FLAG_SIZERR: FLASH Size error flag
AnnaBridge	189:f392fc9709a3	726	* @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
AnnaBridge	189:f392fc9709a3	727	* @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
AnnaBridge	189:f392fc9709a3	728	* @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
AnnaBridge	189:f392fc9709a3	729	* @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
AnnaBridge	189:f392fc9709a3	730	* @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
AnnaBridge	189:f392fc9709a3	731	* @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
AnnaBridge	189:f392fc9709a3	732	* @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
AnnaBridge	189:f392fc9709a3	733	* @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
AnnaBridge	189:f392fc9709a3	734	* @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
AnnaBridge	189:f392fc9709a3	735	* @retval The new state of FLASH_FLAG (SET or RESET).
AnnaBridge	189:f392fc9709a3	736	*/
AnnaBridge	189:f392fc9709a3	737	#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) & (FLASH_FLAG_ECCC \| FLASH_FLAG_ECCD)) ? \
AnnaBridge	189:f392fc9709a3	738	(READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
AnnaBridge	189:f392fc9709a3	739	(READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
AnnaBridge	189:f392fc9709a3	740
AnnaBridge	189:f392fc9709a3	741	/**
AnnaBridge	189:f392fc9709a3	742	* @brief Clear the FLASH's pending flags.
AnnaBridge	189:f392fc9709a3	743	* @param __FLAG__: specifies the FLASH flags to clear.
AnnaBridge	189:f392fc9709a3	744	* This parameter can be any combination of the following values:
AnnaBridge	189:f392fc9709a3	745	* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
AnnaBridge	189:f392fc9709a3	746	* @arg FLASH_FLAG_OPERR: FLASH Operation error flag
AnnaBridge	189:f392fc9709a3	747	* @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
AnnaBridge	189:f392fc9709a3	748	* @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
AnnaBridge	189:f392fc9709a3	749	* @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
AnnaBridge	189:f392fc9709a3	750	* @arg FLASH_FLAG_SIZERR: FLASH Size error flag
AnnaBridge	189:f392fc9709a3	751	* @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
AnnaBridge	189:f392fc9709a3	752	* @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
AnnaBridge	189:f392fc9709a3	753	* @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
AnnaBridge	189:f392fc9709a3	754	* @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
AnnaBridge	189:f392fc9709a3	755	* @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
AnnaBridge	189:f392fc9709a3	756	* @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
AnnaBridge	189:f392fc9709a3	757	* @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
AnnaBridge	189:f392fc9709a3	758	* @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
AnnaBridge	189:f392fc9709a3	759	* @retval None
AnnaBridge	189:f392fc9709a3	760	*/
AnnaBridge	189:f392fc9709a3	761	#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if((__FLAG__) & (FLASH_FLAG_ECCC \| FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC \| FLASH_FLAG_ECCD))); }\
AnnaBridge	189:f392fc9709a3	762	if((__FLAG__) & ~(FLASH_FLAG_ECCC \| FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC \| FLASH_FLAG_ECCD))); }\
AnnaBridge	189:f392fc9709a3	763	} while(0)
AnnaBridge	189:f392fc9709a3	764	/**
AnnaBridge	189:f392fc9709a3	765	* @}
AnnaBridge	189:f392fc9709a3	766	*/
AnnaBridge	189:f392fc9709a3	767
AnnaBridge	189:f392fc9709a3	768	/* Include FLASH HAL Extended module */
AnnaBridge	189:f392fc9709a3	769	#include "stm32l4xx_hal_flash_ex.h"
AnnaBridge	189:f392fc9709a3	770	#include "stm32l4xx_hal_flash_ramfunc.h"
AnnaBridge	189:f392fc9709a3	771
AnnaBridge	189:f392fc9709a3	772	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	773	/** @addtogroup FLASH_Exported_Functions
AnnaBridge	189:f392fc9709a3	774	* @{
AnnaBridge	189:f392fc9709a3	775	*/
AnnaBridge	189:f392fc9709a3	776
AnnaBridge	189:f392fc9709a3	777	/* Program operation functions ***********************************************/
AnnaBridge	189:f392fc9709a3	778	/** @addtogroup FLASH_Exported_Functions_Group1
AnnaBridge	189:f392fc9709a3	779	* @{
AnnaBridge	189:f392fc9709a3	780	*/
AnnaBridge	189:f392fc9709a3	781	HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
AnnaBridge	189:f392fc9709a3	782	HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
AnnaBridge	189:f392fc9709a3	783	/* FLASH IRQ handler method */
AnnaBridge	189:f392fc9709a3	784	void HAL_FLASH_IRQHandler(void);
AnnaBridge	189:f392fc9709a3	785	/* Callbacks in non blocking modes */
AnnaBridge	189:f392fc9709a3	786	void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
AnnaBridge	189:f392fc9709a3	787	void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
AnnaBridge	189:f392fc9709a3	788	/**
AnnaBridge	189:f392fc9709a3	789	* @}
AnnaBridge	189:f392fc9709a3	790	*/
AnnaBridge	189:f392fc9709a3	791
AnnaBridge	189:f392fc9709a3	792	/* Peripheral Control functions **********************************************/
AnnaBridge	189:f392fc9709a3	793	/** @addtogroup FLASH_Exported_Functions_Group2
AnnaBridge	189:f392fc9709a3	794	* @{
AnnaBridge	189:f392fc9709a3	795	*/
AnnaBridge	189:f392fc9709a3	796	HAL_StatusTypeDef HAL_FLASH_Unlock(void);
AnnaBridge	189:f392fc9709a3	797	HAL_StatusTypeDef HAL_FLASH_Lock(void);
AnnaBridge	189:f392fc9709a3	798	/* Option bytes control */
AnnaBridge	189:f392fc9709a3	799	HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
AnnaBridge	189:f392fc9709a3	800	HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
AnnaBridge	189:f392fc9709a3	801	HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
AnnaBridge	189:f392fc9709a3	802	/**
AnnaBridge	189:f392fc9709a3	803	* @}
AnnaBridge	189:f392fc9709a3	804	*/
AnnaBridge	189:f392fc9709a3	805
AnnaBridge	189:f392fc9709a3	806	/* Peripheral State functions ************************************************/
AnnaBridge	189:f392fc9709a3	807	/** @addtogroup FLASH_Exported_Functions_Group3
AnnaBridge	189:f392fc9709a3	808	* @{
AnnaBridge	189:f392fc9709a3	809	*/
AnnaBridge	189:f392fc9709a3	810	uint32_t HAL_FLASH_GetError(void);
AnnaBridge	189:f392fc9709a3	811	/**
AnnaBridge	189:f392fc9709a3	812	* @}
AnnaBridge	189:f392fc9709a3	813	*/
AnnaBridge	189:f392fc9709a3	814
AnnaBridge	189:f392fc9709a3	815	/**
AnnaBridge	189:f392fc9709a3	816	* @}
AnnaBridge	189:f392fc9709a3	817	*/
AnnaBridge	189:f392fc9709a3	818
AnnaBridge	189:f392fc9709a3	819	/* Private constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	820	/** @defgroup FLASH_Private_Constants FLASH Private Constants
AnnaBridge	189:f392fc9709a3	821	* @{
AnnaBridge	189:f392fc9709a3	822	*/
AnnaBridge	189:f392fc9709a3	823	#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
AnnaBridge	189:f392fc9709a3	824
AnnaBridge	189:f392fc9709a3	825	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	826	#define FLASH_SIZE ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x800 << 10) : \
AnnaBridge	189:f392fc9709a3	827	(((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
AnnaBridge	189:f392fc9709a3	828	#elif defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx)
AnnaBridge	189:f392fc9709a3	829	#define FLASH_SIZE ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \
AnnaBridge	189:f392fc9709a3	830	(((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
AnnaBridge	189:f392fc9709a3	831	#else
AnnaBridge	189:f392fc9709a3	832	#define FLASH_SIZE ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \
AnnaBridge	189:f392fc9709a3	833	(((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
AnnaBridge	189:f392fc9709a3	834	#endif
AnnaBridge	189:f392fc9709a3	835
AnnaBridge	189:f392fc9709a3	836	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	189:f392fc9709a3	837	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	189:f392fc9709a3	838	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	839	#define FLASH_BANK_SIZE (FLASH_SIZE >> 1)
AnnaBridge	189:f392fc9709a3	840	#else
AnnaBridge	189:f392fc9709a3	841	#define FLASH_BANK_SIZE (FLASH_SIZE)
AnnaBridge	189:f392fc9709a3	842	#endif
AnnaBridge	189:f392fc9709a3	843
AnnaBridge	189:f392fc9709a3	844	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	845	#define FLASH_PAGE_SIZE ((uint32_t)0x1000)
AnnaBridge	189:f392fc9709a3	846	#define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000)
AnnaBridge	189:f392fc9709a3	847	#else
AnnaBridge	189:f392fc9709a3	848	#define FLASH_PAGE_SIZE ((uint32_t)0x800)
AnnaBridge	189:f392fc9709a3	849	#endif
AnnaBridge	189:f392fc9709a3	850
AnnaBridge	189:f392fc9709a3	851	#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
AnnaBridge	189:f392fc9709a3	852	/**
AnnaBridge	189:f392fc9709a3	853	* @}
AnnaBridge	189:f392fc9709a3	854	*/
AnnaBridge	189:f392fc9709a3	855
AnnaBridge	189:f392fc9709a3	856	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	857	/** @defgroup FLASH_Private_Macros FLASH Private Macros
AnnaBridge	189:f392fc9709a3	858	* @{
AnnaBridge	189:f392fc9709a3	859	*/
AnnaBridge	189:f392fc9709a3	860
AnnaBridge	189:f392fc9709a3	861	#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) \|\| \
AnnaBridge	189:f392fc9709a3	862	((VALUE) == FLASH_TYPEERASE_MASSERASE))
AnnaBridge	189:f392fc9709a3	863
AnnaBridge	189:f392fc9709a3	864	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	189:f392fc9709a3	865	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	189:f392fc9709a3	866	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	867	#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) \|\| \
AnnaBridge	189:f392fc9709a3	868	((BANK) == FLASH_BANK_2) \|\| \
AnnaBridge	189:f392fc9709a3	869	((BANK) == FLASH_BANK_BOTH))
AnnaBridge	189:f392fc9709a3	870
AnnaBridge	189:f392fc9709a3	871	#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) \|\| \
AnnaBridge	189:f392fc9709a3	872	((BANK) == FLASH_BANK_2))
AnnaBridge	189:f392fc9709a3	873	#else
AnnaBridge	189:f392fc9709a3	874	#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
AnnaBridge	189:f392fc9709a3	875
AnnaBridge	189:f392fc9709a3	876	#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
AnnaBridge	189:f392fc9709a3	877	#endif
AnnaBridge	189:f392fc9709a3	878
AnnaBridge	189:f392fc9709a3	879	#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) \|\| \
AnnaBridge	189:f392fc9709a3	880	((VALUE) == FLASH_TYPEPROGRAM_FAST) \|\| \
AnnaBridge	189:f392fc9709a3	881	((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
AnnaBridge	189:f392fc9709a3	882
AnnaBridge	189:f392fc9709a3	883	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	884	#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BASE+0x1FFFFF))
AnnaBridge	189:f392fc9709a3	885	#else
AnnaBridge	189:f392fc9709a3	886	#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \
AnnaBridge	189:f392fc9709a3	887	((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \
AnnaBridge	189:f392fc9709a3	888	((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \
AnnaBridge	189:f392fc9709a3	889	((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \
AnnaBridge	189:f392fc9709a3	890	((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF))))))
AnnaBridge	189:f392fc9709a3	891	#endif
AnnaBridge	189:f392fc9709a3	892
AnnaBridge	189:f392fc9709a3	893	#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF))
AnnaBridge	189:f392fc9709a3	894
AnnaBridge	189:f392fc9709a3	895	#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) \|\| IS_FLASH_OTP_ADDRESS(ADDRESS))
AnnaBridge	189:f392fc9709a3	896
AnnaBridge	189:f392fc9709a3	897	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	898	#define IS_FLASH_PAGE(PAGE) ((PAGE) < 256)
AnnaBridge	189:f392fc9709a3	899	#elif defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx) \|\| defined(STM32L496xx) \|\| defined(STM32L4A6xx)
AnnaBridge	189:f392fc9709a3	900	#define IS_FLASH_PAGE(PAGE) (((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \
AnnaBridge	189:f392fc9709a3	901	((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \
AnnaBridge	189:f392fc9709a3	902	((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \
AnnaBridge	189:f392fc9709a3	903	((PAGE) < 256)))))
AnnaBridge	189:f392fc9709a3	904	#elif defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx)
AnnaBridge	189:f392fc9709a3	905	#define IS_FLASH_PAGE(PAGE) (((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 256) : \
AnnaBridge	189:f392fc9709a3	906	((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
AnnaBridge	189:f392fc9709a3	907	((PAGE) < 256))))
AnnaBridge	189:f392fc9709a3	908	#else
AnnaBridge	189:f392fc9709a3	909	#define IS_FLASH_PAGE(PAGE) (((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
AnnaBridge	189:f392fc9709a3	910	((((((uint16_t )FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? ((PAGE) < 64) : \
AnnaBridge	189:f392fc9709a3	911	((PAGE) < 128))))
AnnaBridge	189:f392fc9709a3	912	#endif
AnnaBridge	189:f392fc9709a3	913
AnnaBridge	189:f392fc9709a3	914	#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP \| OPTIONBYTE_RDP \| OPTIONBYTE_USER \| OPTIONBYTE_PCROP)))
AnnaBridge	189:f392fc9709a3	915
AnnaBridge	189:f392fc9709a3	916	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	189:f392fc9709a3	917	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	189:f392fc9709a3	918	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	919	#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) \|\| ((VALUE) == OB_WRPAREA_BANK1_AREAB) \|\| \
AnnaBridge	189:f392fc9709a3	920	((VALUE) == OB_WRPAREA_BANK2_AREAA) \|\| ((VALUE) == OB_WRPAREA_BANK2_AREAB))
AnnaBridge	189:f392fc9709a3	921	#else
AnnaBridge	189:f392fc9709a3	922	#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) \|\| ((VALUE) == OB_WRPAREA_BANK1_AREAB))
AnnaBridge	189:f392fc9709a3	923	#endif
AnnaBridge	189:f392fc9709a3	924
AnnaBridge	189:f392fc9709a3	925	#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) \|\|\
AnnaBridge	189:f392fc9709a3	926	((LEVEL) == OB_RDP_LEVEL_1)/* \|\|\
AnnaBridge	189:f392fc9709a3	927	((LEVEL) == OB_RDP_LEVEL_2)*/)
AnnaBridge	189:f392fc9709a3	928
AnnaBridge	189:f392fc9709a3	929	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	930	#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFF) && ((TYPE) != 0))
AnnaBridge	189:f392fc9709a3	931	#elif defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx) \|\| defined(STM32L496xx) \|\| defined(STM32L4A6xx)
AnnaBridge	189:f392fc9709a3	932	#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0))
AnnaBridge	189:f392fc9709a3	933	#else
AnnaBridge	189:f392fc9709a3	934	#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0))
AnnaBridge	189:f392fc9709a3	935	#endif
AnnaBridge	189:f392fc9709a3	936
AnnaBridge	189:f392fc9709a3	937	#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) \|\| ((LEVEL) == OB_BOR_LEVEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	938	((LEVEL) == OB_BOR_LEVEL_2) \|\| ((LEVEL) == OB_BOR_LEVEL_3) \|\| \
AnnaBridge	189:f392fc9709a3	939	((LEVEL) == OB_BOR_LEVEL_4))
AnnaBridge	189:f392fc9709a3	940
AnnaBridge	189:f392fc9709a3	941	#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) \|\| ((VALUE) == OB_STOP_NORST))
AnnaBridge	189:f392fc9709a3	942
AnnaBridge	189:f392fc9709a3	943	#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) \|\| ((VALUE) == OB_STANDBY_NORST))
AnnaBridge	189:f392fc9709a3	944
AnnaBridge	189:f392fc9709a3	945	#define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) \|\| ((VALUE) == OB_SHUTDOWN_NORST))
AnnaBridge	189:f392fc9709a3	946
AnnaBridge	189:f392fc9709a3	947	#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) \|\| ((VALUE) == OB_IWDG_SW))
AnnaBridge	189:f392fc9709a3	948
AnnaBridge	189:f392fc9709a3	949	#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) \|\| ((VALUE) == OB_IWDG_STOP_RUN))
AnnaBridge	189:f392fc9709a3	950
AnnaBridge	189:f392fc9709a3	951	#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) \|\| ((VALUE) == OB_IWDG_STDBY_RUN))
AnnaBridge	189:f392fc9709a3	952
AnnaBridge	189:f392fc9709a3	953	#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) \|\| ((VALUE) == OB_WWDG_SW))
AnnaBridge	189:f392fc9709a3	954
AnnaBridge	189:f392fc9709a3	955	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| \
AnnaBridge	189:f392fc9709a3	956	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	189:f392fc9709a3	957	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	958	#define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) \|\| ((VALUE) == OB_BFB2_ENABLE))
AnnaBridge	189:f392fc9709a3	959
AnnaBridge	189:f392fc9709a3	960	#define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) \|\| ((VALUE) == OB_DUALBANK_DUAL))
AnnaBridge	189:f392fc9709a3	961	#endif
AnnaBridge	189:f392fc9709a3	962
AnnaBridge	189:f392fc9709a3	963	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	964	#define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) \|\| ((VALUE) == OB_DBANK_64_BITS))
AnnaBridge	189:f392fc9709a3	965	#endif
AnnaBridge	189:f392fc9709a3	966
AnnaBridge	189:f392fc9709a3	967	#define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) \|\| ((VALUE) == OB_BOOT1_SYSTEM))
AnnaBridge	189:f392fc9709a3	968
AnnaBridge	189:f392fc9709a3	969	#define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) \|\| ((VALUE) == OB_SRAM2_PARITY_DISABLE))
AnnaBridge	189:f392fc9709a3	970
AnnaBridge	189:f392fc9709a3	971	#define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) \|\| ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
AnnaBridge	189:f392fc9709a3	972
AnnaBridge	189:f392fc9709a3	973	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| \
AnnaBridge	189:f392fc9709a3	974	defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| \
AnnaBridge	189:f392fc9709a3	975	defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| \
AnnaBridge	189:f392fc9709a3	976	defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	977	#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) \|\| ((VALUE) == OB_BOOT0_FROM_PIN))
AnnaBridge	189:f392fc9709a3	978
AnnaBridge	189:f392fc9709a3	979	#define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) \|\| ((VALUE) == OB_BOOT0_SET))
AnnaBridge	189:f392fc9709a3	980	#endif
AnnaBridge	189:f392fc9709a3	981
AnnaBridge	189:f392fc9709a3	982	#define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) \|\| ((VALUE) == OB_PCROP_RDP_ERASE))
AnnaBridge	189:f392fc9709a3	983
AnnaBridge	189:f392fc9709a3	984	#if defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	985	#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) \|\| ((LATENCY) == FLASH_LATENCY_1) \|\| \
AnnaBridge	189:f392fc9709a3	986	((LATENCY) == FLASH_LATENCY_2) \|\| ((LATENCY) == FLASH_LATENCY_3) \|\| \
AnnaBridge	189:f392fc9709a3	987	((LATENCY) == FLASH_LATENCY_4) \|\| ((LATENCY) == FLASH_LATENCY_5) \|\| \
AnnaBridge	189:f392fc9709a3	988	((LATENCY) == FLASH_LATENCY_6) \|\| ((LATENCY) == FLASH_LATENCY_7) \|\| \
AnnaBridge	189:f392fc9709a3	989	((LATENCY) == FLASH_LATENCY_8) \|\| ((LATENCY) == FLASH_LATENCY_9) \|\| \
AnnaBridge	189:f392fc9709a3	990	((LATENCY) == FLASH_LATENCY_10) \|\| ((LATENCY) == FLASH_LATENCY_11) \|\| \
AnnaBridge	189:f392fc9709a3	991	((LATENCY) == FLASH_LATENCY_12) \|\| ((LATENCY) == FLASH_LATENCY_13) \|\| \
AnnaBridge	189:f392fc9709a3	992	((LATENCY) == FLASH_LATENCY_14) \|\| ((LATENCY) == FLASH_LATENCY_15))
AnnaBridge	189:f392fc9709a3	993	#else
AnnaBridge	189:f392fc9709a3	994	#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) \|\| \
AnnaBridge	189:f392fc9709a3	995	((LATENCY) == FLASH_LATENCY_1) \|\| \
AnnaBridge	189:f392fc9709a3	996	((LATENCY) == FLASH_LATENCY_2) \|\| \
AnnaBridge	189:f392fc9709a3	997	((LATENCY) == FLASH_LATENCY_3) \|\| \
AnnaBridge	189:f392fc9709a3	998	((LATENCY) == FLASH_LATENCY_4))
AnnaBridge	189:f392fc9709a3	999	#endif
AnnaBridge	189:f392fc9709a3	1000	/**
AnnaBridge	189:f392fc9709a3	1001	* @}
AnnaBridge	189:f392fc9709a3	1002	*/
AnnaBridge	189:f392fc9709a3	1003
AnnaBridge	189:f392fc9709a3	1004	/**
AnnaBridge	189:f392fc9709a3	1005	* @}
AnnaBridge	189:f392fc9709a3	1006	*/
AnnaBridge	189:f392fc9709a3	1007
AnnaBridge	189:f392fc9709a3	1008	/**
AnnaBridge	189:f392fc9709a3	1009	* @}
AnnaBridge	189:f392fc9709a3	1010	*/
AnnaBridge	189:f392fc9709a3	1011
AnnaBridge	189:f392fc9709a3	1012	/**
AnnaBridge	189:f392fc9709a3	1013	* @}
AnnaBridge	189:f392fc9709a3	1014	*/
AnnaBridge	189:f392fc9709a3	1015
AnnaBridge	189:f392fc9709a3	1016	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	1017	}
AnnaBridge	189:f392fc9709a3	1018	#endif
AnnaBridge	189:f392fc9709a3	1019
AnnaBridge	189:f392fc9709a3	1020	#endif /* __STM32L4xx_HAL_FLASH_H */
AnnaBridge	189:f392fc9709a3	1021
AnnaBridge	189:f392fc9709a3	1022	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/