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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_ARM_STD/stm32l4xx_hal_dfsdm.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_hal_dfsdm.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of DFSDM HAL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_HAL_DFSDM_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_HAL_DFSDM_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 45 | defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 46 | defined(STM32L496xx) || defined(STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 47 | defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 48 | |
| AnnaBridge | 189:f392fc9709a3 | 49 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 50 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 51 | |
| AnnaBridge | 189:f392fc9709a3 | 52 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 53 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 54 | */ |
| AnnaBridge | 189:f392fc9709a3 | 55 | |
| AnnaBridge | 189:f392fc9709a3 | 56 | /** @addtogroup DFSDM |
| AnnaBridge | 189:f392fc9709a3 | 57 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 58 | */ |
| AnnaBridge | 189:f392fc9709a3 | 59 | |
| AnnaBridge | 189:f392fc9709a3 | 60 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 61 | /** @defgroup DFSDM_Exported_Types DFSDM Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 62 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 63 | */ |
| AnnaBridge | 189:f392fc9709a3 | 64 | |
| AnnaBridge | 189:f392fc9709a3 | 65 | /** |
| AnnaBridge | 189:f392fc9709a3 | 66 | * @brief HAL DFSDM Channel states definition |
| AnnaBridge | 189:f392fc9709a3 | 67 | */ |
| AnnaBridge | 189:f392fc9709a3 | 68 | typedef enum |
| AnnaBridge | 189:f392fc9709a3 | 69 | { |
| AnnaBridge | 189:f392fc9709a3 | 70 | HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ |
| AnnaBridge | 189:f392fc9709a3 | 71 | HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ |
| AnnaBridge | 189:f392fc9709a3 | 72 | HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ |
| AnnaBridge | 189:f392fc9709a3 | 73 | }HAL_DFSDM_Channel_StateTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 74 | |
| AnnaBridge | 189:f392fc9709a3 | 75 | /** |
| AnnaBridge | 189:f392fc9709a3 | 76 | * @brief DFSDM channel output clock structure definition |
| AnnaBridge | 189:f392fc9709a3 | 77 | */ |
| AnnaBridge | 189:f392fc9709a3 | 78 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 79 | { |
| AnnaBridge | 189:f392fc9709a3 | 80 | FunctionalState Activation; /*!< Output clock enable/disable */ |
| AnnaBridge | 189:f392fc9709a3 | 81 | uint32_t Selection; /*!< Output clock is system clock or audio clock. |
| AnnaBridge | 189:f392fc9709a3 | 82 | This parameter can be a value of @ref DFSDM_Channel_OuputClock */ |
| AnnaBridge | 189:f392fc9709a3 | 83 | uint32_t Divider; /*!< Output clock divider. |
| AnnaBridge | 189:f392fc9709a3 | 84 | This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ |
| AnnaBridge | 189:f392fc9709a3 | 85 | }DFSDM_Channel_OutputClockTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 86 | |
| AnnaBridge | 189:f392fc9709a3 | 87 | /** |
| AnnaBridge | 189:f392fc9709a3 | 88 | * @brief DFSDM channel input structure definition |
| AnnaBridge | 189:f392fc9709a3 | 89 | */ |
| AnnaBridge | 189:f392fc9709a3 | 90 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 91 | { |
| AnnaBridge | 189:f392fc9709a3 | 92 | uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output. |
| AnnaBridge | 189:f392fc9709a3 | 93 | ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx, |
| AnnaBridge | 189:f392fc9709a3 | 94 | STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx, STM32L4R9xx, |
| AnnaBridge | 189:f392fc9709a3 | 95 | STM32L4S5xx, STM32L4S7xx and STM32L4S9xx products. |
| AnnaBridge | 189:f392fc9709a3 | 96 | This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ |
| AnnaBridge | 189:f392fc9709a3 | 97 | uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. |
| AnnaBridge | 189:f392fc9709a3 | 98 | This parameter can be a value of @ref DFSDM_Channel_DataPacking */ |
| AnnaBridge | 189:f392fc9709a3 | 99 | uint32_t Pins; /*!< Input pins are taken from same or following channel. |
| AnnaBridge | 189:f392fc9709a3 | 100 | This parameter can be a value of @ref DFSDM_Channel_InputPins */ |
| AnnaBridge | 189:f392fc9709a3 | 101 | }DFSDM_Channel_InputTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 102 | |
| AnnaBridge | 189:f392fc9709a3 | 103 | /** |
| AnnaBridge | 189:f392fc9709a3 | 104 | * @brief DFSDM channel serial interface structure definition |
| AnnaBridge | 189:f392fc9709a3 | 105 | */ |
| AnnaBridge | 189:f392fc9709a3 | 106 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 107 | { |
| AnnaBridge | 189:f392fc9709a3 | 108 | uint32_t Type; /*!< SPI or Manchester modes. |
| AnnaBridge | 189:f392fc9709a3 | 109 | This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). |
| AnnaBridge | 189:f392fc9709a3 | 111 | This parameter can be a value of @ref DFSDM_Channel_SpiClock */ |
| AnnaBridge | 189:f392fc9709a3 | 112 | }DFSDM_Channel_SerialInterfaceTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 113 | |
| AnnaBridge | 189:f392fc9709a3 | 114 | /** |
| AnnaBridge | 189:f392fc9709a3 | 115 | * @brief DFSDM channel analog watchdog structure definition |
| AnnaBridge | 189:f392fc9709a3 | 116 | */ |
| AnnaBridge | 189:f392fc9709a3 | 117 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 118 | { |
| AnnaBridge | 189:f392fc9709a3 | 119 | uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. |
| AnnaBridge | 189:f392fc9709a3 | 120 | This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. |
| AnnaBridge | 189:f392fc9709a3 | 122 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ |
| AnnaBridge | 189:f392fc9709a3 | 123 | }DFSDM_Channel_AwdTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 124 | |
| AnnaBridge | 189:f392fc9709a3 | 125 | /** |
| AnnaBridge | 189:f392fc9709a3 | 126 | * @brief DFSDM channel init structure definition |
| AnnaBridge | 189:f392fc9709a3 | 127 | */ |
| AnnaBridge | 189:f392fc9709a3 | 128 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 129 | { |
| AnnaBridge | 189:f392fc9709a3 | 130 | DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 131 | DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 132 | DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 133 | DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 134 | int32_t Offset; /*!< DFSDM channel offset. |
| AnnaBridge | 189:f392fc9709a3 | 135 | This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
| AnnaBridge | 189:f392fc9709a3 | 136 | uint32_t RightBitShift; /*!< DFSDM channel right bit shift. |
| AnnaBridge | 189:f392fc9709a3 | 137 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
| AnnaBridge | 189:f392fc9709a3 | 138 | }DFSDM_Channel_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 139 | |
| AnnaBridge | 189:f392fc9709a3 | 140 | /** |
| AnnaBridge | 189:f392fc9709a3 | 141 | * @brief DFSDM channel handle structure definition |
| AnnaBridge | 189:f392fc9709a3 | 142 | */ |
| AnnaBridge | 189:f392fc9709a3 | 143 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 144 | { |
| AnnaBridge | 189:f392fc9709a3 | 145 | DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ |
| AnnaBridge | 189:f392fc9709a3 | 146 | DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 147 | HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ |
| AnnaBridge | 189:f392fc9709a3 | 148 | }DFSDM_Channel_HandleTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 149 | |
| AnnaBridge | 189:f392fc9709a3 | 150 | /** |
| AnnaBridge | 189:f392fc9709a3 | 151 | * @brief HAL DFSDM Filter states definition |
| AnnaBridge | 189:f392fc9709a3 | 152 | */ |
| AnnaBridge | 189:f392fc9709a3 | 153 | typedef enum |
| AnnaBridge | 189:f392fc9709a3 | 154 | { |
| AnnaBridge | 189:f392fc9709a3 | 155 | HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ |
| AnnaBridge | 189:f392fc9709a3 | 156 | HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ |
| AnnaBridge | 189:f392fc9709a3 | 157 | HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ |
| AnnaBridge | 189:f392fc9709a3 | 158 | HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ |
| AnnaBridge | 189:f392fc9709a3 | 159 | HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ |
| AnnaBridge | 189:f392fc9709a3 | 160 | HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ |
| AnnaBridge | 189:f392fc9709a3 | 161 | }HAL_DFSDM_Filter_StateTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 162 | |
| AnnaBridge | 189:f392fc9709a3 | 163 | /** |
| AnnaBridge | 189:f392fc9709a3 | 164 | * @brief DFSDM filter regular conversion parameters structure definition |
| AnnaBridge | 189:f392fc9709a3 | 165 | */ |
| AnnaBridge | 189:f392fc9709a3 | 166 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 167 | { |
| AnnaBridge | 189:f392fc9709a3 | 168 | uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. |
| AnnaBridge | 189:f392fc9709a3 | 169 | This parameter can be a value of @ref DFSDM_Filter_Trigger */ |
| AnnaBridge | 189:f392fc9709a3 | 170 | FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ |
| AnnaBridge | 189:f392fc9709a3 | 171 | FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ |
| AnnaBridge | 189:f392fc9709a3 | 172 | }DFSDM_Filter_RegularParamTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 173 | |
| AnnaBridge | 189:f392fc9709a3 | 174 | /** |
| AnnaBridge | 189:f392fc9709a3 | 175 | * @brief DFSDM filter injected conversion parameters structure definition |
| AnnaBridge | 189:f392fc9709a3 | 176 | */ |
| AnnaBridge | 189:f392fc9709a3 | 177 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 178 | { |
| AnnaBridge | 189:f392fc9709a3 | 179 | uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. |
| AnnaBridge | 189:f392fc9709a3 | 180 | This parameter can be a value of @ref DFSDM_Filter_Trigger */ |
| AnnaBridge | 189:f392fc9709a3 | 181 | FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ |
| AnnaBridge | 189:f392fc9709a3 | 183 | uint32_t ExtTrigger; /*!< External trigger. |
| AnnaBridge | 189:f392fc9709a3 | 184 | This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ |
| AnnaBridge | 189:f392fc9709a3 | 185 | uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. |
| AnnaBridge | 189:f392fc9709a3 | 186 | This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ |
| AnnaBridge | 189:f392fc9709a3 | 187 | }DFSDM_Filter_InjectedParamTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 188 | |
| AnnaBridge | 189:f392fc9709a3 | 189 | /** |
| AnnaBridge | 189:f392fc9709a3 | 190 | * @brief DFSDM filter parameters structure definition |
| AnnaBridge | 189:f392fc9709a3 | 191 | */ |
| AnnaBridge | 189:f392fc9709a3 | 192 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 193 | { |
| AnnaBridge | 189:f392fc9709a3 | 194 | uint32_t SincOrder; /*!< Sinc filter order. |
| AnnaBridge | 189:f392fc9709a3 | 195 | This parameter can be a value of @ref DFSDM_Filter_SincOrder */ |
| AnnaBridge | 189:f392fc9709a3 | 196 | uint32_t Oversampling; /*!< Filter oversampling ratio. |
| AnnaBridge | 189:f392fc9709a3 | 197 | This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ |
| AnnaBridge | 189:f392fc9709a3 | 198 | uint32_t IntOversampling; /*!< Integrator oversampling ratio. |
| AnnaBridge | 189:f392fc9709a3 | 199 | This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ |
| AnnaBridge | 189:f392fc9709a3 | 200 | }DFSDM_Filter_FilterParamTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 201 | |
| AnnaBridge | 189:f392fc9709a3 | 202 | /** |
| AnnaBridge | 189:f392fc9709a3 | 203 | * @brief DFSDM filter init structure definition |
| AnnaBridge | 189:f392fc9709a3 | 204 | */ |
| AnnaBridge | 189:f392fc9709a3 | 205 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 206 | { |
| AnnaBridge | 189:f392fc9709a3 | 207 | DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 208 | DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 209 | DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 210 | }DFSDM_Filter_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 211 | |
| AnnaBridge | 189:f392fc9709a3 | 212 | /** |
| AnnaBridge | 189:f392fc9709a3 | 213 | * @brief DFSDM filter handle structure definition |
| AnnaBridge | 189:f392fc9709a3 | 214 | */ |
| AnnaBridge | 189:f392fc9709a3 | 215 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 216 | { |
| AnnaBridge | 189:f392fc9709a3 | 217 | DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ |
| AnnaBridge | 189:f392fc9709a3 | 218 | DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 219 | DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ |
| AnnaBridge | 189:f392fc9709a3 | 220 | DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ |
| AnnaBridge | 189:f392fc9709a3 | 221 | uint32_t RegularContMode; /*!< Regular conversion continuous mode */ |
| AnnaBridge | 189:f392fc9709a3 | 222 | uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ |
| AnnaBridge | 189:f392fc9709a3 | 223 | uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ |
| AnnaBridge | 189:f392fc9709a3 | 224 | uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ |
| AnnaBridge | 189:f392fc9709a3 | 225 | FunctionalState InjectedScanMode; /*!< Injected scanning mode */ |
| AnnaBridge | 189:f392fc9709a3 | 226 | uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ |
| AnnaBridge | 189:f392fc9709a3 | 227 | uint32_t InjConvRemaining; /*!< Injected conversions remaining */ |
| AnnaBridge | 189:f392fc9709a3 | 228 | HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ |
| AnnaBridge | 189:f392fc9709a3 | 229 | uint32_t ErrorCode; /*!< DFSDM filter error code */ |
| AnnaBridge | 189:f392fc9709a3 | 230 | }DFSDM_Filter_HandleTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 231 | |
| AnnaBridge | 189:f392fc9709a3 | 232 | /** |
| AnnaBridge | 189:f392fc9709a3 | 233 | * @brief DFSDM filter analog watchdog parameters structure definition |
| AnnaBridge | 189:f392fc9709a3 | 234 | */ |
| AnnaBridge | 189:f392fc9709a3 | 235 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 236 | { |
| AnnaBridge | 189:f392fc9709a3 | 237 | uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. |
| AnnaBridge | 189:f392fc9709a3 | 238 | This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ |
| AnnaBridge | 189:f392fc9709a3 | 239 | uint32_t Channel; /*!< Analog watchdog channel selection. |
| AnnaBridge | 189:f392fc9709a3 | 240 | This parameter can be a values combination of @ref DFSDM_Channel_Selection */ |
| AnnaBridge | 189:f392fc9709a3 | 241 | int32_t HighThreshold; /*!< High threshold for the analog watchdog. |
| AnnaBridge | 189:f392fc9709a3 | 242 | This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
| AnnaBridge | 189:f392fc9709a3 | 243 | int32_t LowThreshold; /*!< Low threshold for the analog watchdog. |
| AnnaBridge | 189:f392fc9709a3 | 244 | This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
| AnnaBridge | 189:f392fc9709a3 | 245 | uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. |
| AnnaBridge | 189:f392fc9709a3 | 246 | This parameter can be a values combination of @ref DFSDM_BreakSignals */ |
| AnnaBridge | 189:f392fc9709a3 | 247 | uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. |
| AnnaBridge | 189:f392fc9709a3 | 248 | This parameter can be a values combination of @ref DFSDM_BreakSignals */ |
| AnnaBridge | 189:f392fc9709a3 | 249 | }DFSDM_Filter_AwdParamTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 250 | |
| AnnaBridge | 189:f392fc9709a3 | 251 | /** |
| AnnaBridge | 189:f392fc9709a3 | 252 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 253 | */ |
| AnnaBridge | 189:f392fc9709a3 | 254 | /* End of exported types -----------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 255 | |
| AnnaBridge | 189:f392fc9709a3 | 256 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 257 | /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 258 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 259 | */ |
| AnnaBridge | 189:f392fc9709a3 | 260 | |
| AnnaBridge | 189:f392fc9709a3 | 261 | /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection |
| AnnaBridge | 189:f392fc9709a3 | 262 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 263 | */ |
| AnnaBridge | 189:f392fc9709a3 | 264 | #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */ |
| AnnaBridge | 189:f392fc9709a3 | 265 | #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ |
| AnnaBridge | 189:f392fc9709a3 | 266 | /** |
| AnnaBridge | 189:f392fc9709a3 | 267 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 268 | */ |
| AnnaBridge | 189:f392fc9709a3 | 269 | |
| AnnaBridge | 189:f392fc9709a3 | 270 | /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer |
| AnnaBridge | 189:f392fc9709a3 | 271 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 272 | */ |
| AnnaBridge | 189:f392fc9709a3 | 273 | #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */ |
| AnnaBridge | 189:f392fc9709a3 | 274 | #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 275 | defined(STM32L496xx) || defined(STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 276 | defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 277 | #define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */ |
| AnnaBridge | 189:f392fc9709a3 | 278 | #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 279 | #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ |
| AnnaBridge | 189:f392fc9709a3 | 280 | /** |
| AnnaBridge | 189:f392fc9709a3 | 281 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 282 | */ |
| AnnaBridge | 189:f392fc9709a3 | 283 | |
| AnnaBridge | 189:f392fc9709a3 | 284 | /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing |
| AnnaBridge | 189:f392fc9709a3 | 285 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 286 | */ |
| AnnaBridge | 189:f392fc9709a3 | 287 | #define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */ |
| AnnaBridge | 189:f392fc9709a3 | 288 | #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ |
| AnnaBridge | 189:f392fc9709a3 | 289 | #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ |
| AnnaBridge | 189:f392fc9709a3 | 290 | /** |
| AnnaBridge | 189:f392fc9709a3 | 291 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 292 | */ |
| AnnaBridge | 189:f392fc9709a3 | 293 | |
| AnnaBridge | 189:f392fc9709a3 | 294 | /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins |
| AnnaBridge | 189:f392fc9709a3 | 295 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 296 | */ |
| AnnaBridge | 189:f392fc9709a3 | 297 | #define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */ |
| AnnaBridge | 189:f392fc9709a3 | 298 | #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ |
| AnnaBridge | 189:f392fc9709a3 | 299 | /** |
| AnnaBridge | 189:f392fc9709a3 | 300 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 301 | */ |
| AnnaBridge | 189:f392fc9709a3 | 302 | |
| AnnaBridge | 189:f392fc9709a3 | 303 | /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type |
| AnnaBridge | 189:f392fc9709a3 | 304 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 305 | */ |
| AnnaBridge | 189:f392fc9709a3 | 306 | #define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */ |
| AnnaBridge | 189:f392fc9709a3 | 307 | #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ |
| AnnaBridge | 189:f392fc9709a3 | 308 | #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ |
| AnnaBridge | 189:f392fc9709a3 | 309 | #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ |
| AnnaBridge | 189:f392fc9709a3 | 310 | /** |
| AnnaBridge | 189:f392fc9709a3 | 311 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 312 | */ |
| AnnaBridge | 189:f392fc9709a3 | 313 | |
| AnnaBridge | 189:f392fc9709a3 | 314 | /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection |
| AnnaBridge | 189:f392fc9709a3 | 315 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 316 | */ |
| AnnaBridge | 189:f392fc9709a3 | 317 | #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */ |
| AnnaBridge | 189:f392fc9709a3 | 318 | #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ |
| AnnaBridge | 189:f392fc9709a3 | 319 | #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ |
| AnnaBridge | 189:f392fc9709a3 | 320 | #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ |
| AnnaBridge | 189:f392fc9709a3 | 321 | /** |
| AnnaBridge | 189:f392fc9709a3 | 322 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 323 | */ |
| AnnaBridge | 189:f392fc9709a3 | 324 | |
| AnnaBridge | 189:f392fc9709a3 | 325 | /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order |
| AnnaBridge | 189:f392fc9709a3 | 326 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 327 | */ |
| AnnaBridge | 189:f392fc9709a3 | 328 | #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ |
| AnnaBridge | 189:f392fc9709a3 | 329 | #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ |
| AnnaBridge | 189:f392fc9709a3 | 330 | #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ |
| AnnaBridge | 189:f392fc9709a3 | 331 | #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ |
| AnnaBridge | 189:f392fc9709a3 | 332 | /** |
| AnnaBridge | 189:f392fc9709a3 | 333 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 334 | */ |
| AnnaBridge | 189:f392fc9709a3 | 335 | |
| AnnaBridge | 189:f392fc9709a3 | 336 | /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger |
| AnnaBridge | 189:f392fc9709a3 | 337 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 338 | */ |
| AnnaBridge | 189:f392fc9709a3 | 339 | #define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */ |
| AnnaBridge | 189:f392fc9709a3 | 340 | #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */ |
| AnnaBridge | 189:f392fc9709a3 | 341 | #define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */ |
| AnnaBridge | 189:f392fc9709a3 | 342 | /** |
| AnnaBridge | 189:f392fc9709a3 | 343 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 344 | */ |
| AnnaBridge | 189:f392fc9709a3 | 345 | |
| AnnaBridge | 189:f392fc9709a3 | 346 | /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger |
| AnnaBridge | 189:f392fc9709a3 | 347 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 348 | */ |
| AnnaBridge | 189:f392fc9709a3 | 349 | #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) |
| AnnaBridge | 189:f392fc9709a3 | 350 | #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 351 | #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 352 | #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 353 | #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 354 | #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 355 | #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 356 | #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 357 | #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 358 | #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For all DFSDM filters */ |
| AnnaBridge | 189:f392fc9709a3 | 359 | #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */ |
| AnnaBridge | 189:f392fc9709a3 | 360 | #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */ |
| AnnaBridge | 189:f392fc9709a3 | 361 | #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */ |
| AnnaBridge | 189:f392fc9709a3 | 362 | #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */ |
| AnnaBridge | 189:f392fc9709a3 | 363 | #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ |
| AnnaBridge | 189:f392fc9709a3 | 364 | #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ |
| AnnaBridge | 189:f392fc9709a3 | 365 | #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ |
| AnnaBridge | 189:f392fc9709a3 | 366 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ |
| AnnaBridge | 189:f392fc9709a3 | 367 | #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */ |
| AnnaBridge | 189:f392fc9709a3 | 368 | #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ |
| AnnaBridge | 189:f392fc9709a3 | 369 | #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \ |
| AnnaBridge | 189:f392fc9709a3 | 370 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ |
| AnnaBridge | 189:f392fc9709a3 | 371 | #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ |
| AnnaBridge | 189:f392fc9709a3 | 372 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ |
| AnnaBridge | 189:f392fc9709a3 | 373 | #else |
| AnnaBridge | 189:f392fc9709a3 | 374 | #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 375 | #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 376 | #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 377 | #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 378 | #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 379 | #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1 and 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 380 | #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 381 | #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 382 | #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 383 | #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 384 | #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 385 | #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ |
| AnnaBridge | 189:f392fc9709a3 | 386 | /** |
| AnnaBridge | 189:f392fc9709a3 | 387 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 388 | */ |
| AnnaBridge | 189:f392fc9709a3 | 389 | |
| AnnaBridge | 189:f392fc9709a3 | 390 | /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge |
| AnnaBridge | 189:f392fc9709a3 | 391 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 392 | */ |
| AnnaBridge | 189:f392fc9709a3 | 393 | #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ |
| AnnaBridge | 189:f392fc9709a3 | 394 | #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ |
| AnnaBridge | 189:f392fc9709a3 | 395 | #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ |
| AnnaBridge | 189:f392fc9709a3 | 396 | /** |
| AnnaBridge | 189:f392fc9709a3 | 397 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 398 | */ |
| AnnaBridge | 189:f392fc9709a3 | 399 | |
| AnnaBridge | 189:f392fc9709a3 | 400 | /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order |
| AnnaBridge | 189:f392fc9709a3 | 401 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 402 | */ |
| AnnaBridge | 189:f392fc9709a3 | 403 | #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ |
| AnnaBridge | 189:f392fc9709a3 | 404 | #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ |
| AnnaBridge | 189:f392fc9709a3 | 405 | #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ |
| AnnaBridge | 189:f392fc9709a3 | 406 | #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ |
| AnnaBridge | 189:f392fc9709a3 | 407 | #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ |
| AnnaBridge | 189:f392fc9709a3 | 408 | #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ |
| AnnaBridge | 189:f392fc9709a3 | 409 | /** |
| AnnaBridge | 189:f392fc9709a3 | 410 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 411 | */ |
| AnnaBridge | 189:f392fc9709a3 | 412 | |
| AnnaBridge | 189:f392fc9709a3 | 413 | /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source |
| AnnaBridge | 189:f392fc9709a3 | 414 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 415 | */ |
| AnnaBridge | 189:f392fc9709a3 | 416 | #define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */ |
| AnnaBridge | 189:f392fc9709a3 | 417 | #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ |
| AnnaBridge | 189:f392fc9709a3 | 418 | /** |
| AnnaBridge | 189:f392fc9709a3 | 419 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 420 | */ |
| AnnaBridge | 189:f392fc9709a3 | 421 | |
| AnnaBridge | 189:f392fc9709a3 | 422 | /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code |
| AnnaBridge | 189:f392fc9709a3 | 423 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 424 | */ |
| AnnaBridge | 189:f392fc9709a3 | 425 | #define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
| AnnaBridge | 189:f392fc9709a3 | 426 | #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */ |
| AnnaBridge | 189:f392fc9709a3 | 427 | #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */ |
| AnnaBridge | 189:f392fc9709a3 | 428 | #define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */ |
| AnnaBridge | 189:f392fc9709a3 | 429 | /** |
| AnnaBridge | 189:f392fc9709a3 | 430 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 431 | */ |
| AnnaBridge | 189:f392fc9709a3 | 432 | |
| AnnaBridge | 189:f392fc9709a3 | 433 | /** @defgroup DFSDM_BreakSignals DFSDM break signals |
| AnnaBridge | 189:f392fc9709a3 | 434 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 435 | */ |
| AnnaBridge | 189:f392fc9709a3 | 436 | #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */ |
| AnnaBridge | 189:f392fc9709a3 | 437 | #define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */ |
| AnnaBridge | 189:f392fc9709a3 | 438 | #define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 439 | #define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 440 | #define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 441 | /** |
| AnnaBridge | 189:f392fc9709a3 | 442 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 443 | */ |
| AnnaBridge | 189:f392fc9709a3 | 444 | |
| AnnaBridge | 189:f392fc9709a3 | 445 | /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection |
| AnnaBridge | 189:f392fc9709a3 | 446 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 447 | */ |
| AnnaBridge | 189:f392fc9709a3 | 448 | /* DFSDM Channels ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 449 | /* The DFSDM channels are defined as follows: |
| AnnaBridge | 189:f392fc9709a3 | 450 | - in 16-bit LSB the channel mask is set |
| AnnaBridge | 189:f392fc9709a3 | 451 | - in 16-bit MSB the channel number is set |
| AnnaBridge | 189:f392fc9709a3 | 452 | e.g. for channel 5 definition: |
| AnnaBridge | 189:f392fc9709a3 | 453 | - the channel mask is 0x00000020 (bit 5 is set) |
| AnnaBridge | 189:f392fc9709a3 | 454 | - the channel number 5 is 0x00050000 |
| AnnaBridge | 189:f392fc9709a3 | 455 | --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ |
| AnnaBridge | 189:f392fc9709a3 | 456 | #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) |
| AnnaBridge | 189:f392fc9709a3 | 457 | #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) |
| AnnaBridge | 189:f392fc9709a3 | 458 | #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) |
| AnnaBridge | 189:f392fc9709a3 | 459 | #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) |
| AnnaBridge | 189:f392fc9709a3 | 460 | #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) |
| AnnaBridge | 189:f392fc9709a3 | 461 | #else |
| AnnaBridge | 189:f392fc9709a3 | 462 | #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) |
| AnnaBridge | 189:f392fc9709a3 | 463 | #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) |
| AnnaBridge | 189:f392fc9709a3 | 464 | #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) |
| AnnaBridge | 189:f392fc9709a3 | 465 | #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) |
| AnnaBridge | 189:f392fc9709a3 | 466 | #define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U) |
| AnnaBridge | 189:f392fc9709a3 | 467 | #define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U) |
| AnnaBridge | 189:f392fc9709a3 | 468 | #define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U) |
| AnnaBridge | 189:f392fc9709a3 | 469 | #define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U) |
| AnnaBridge | 189:f392fc9709a3 | 470 | #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ |
| AnnaBridge | 189:f392fc9709a3 | 471 | /** |
| AnnaBridge | 189:f392fc9709a3 | 472 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 473 | */ |
| AnnaBridge | 189:f392fc9709a3 | 474 | |
| AnnaBridge | 189:f392fc9709a3 | 475 | /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode |
| AnnaBridge | 189:f392fc9709a3 | 476 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 477 | */ |
| AnnaBridge | 189:f392fc9709a3 | 478 | #define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */ |
| AnnaBridge | 189:f392fc9709a3 | 479 | #define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */ |
| AnnaBridge | 189:f392fc9709a3 | 480 | /** |
| AnnaBridge | 189:f392fc9709a3 | 481 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 482 | */ |
| AnnaBridge | 189:f392fc9709a3 | 483 | |
| AnnaBridge | 189:f392fc9709a3 | 484 | /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold |
| AnnaBridge | 189:f392fc9709a3 | 485 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 486 | */ |
| AnnaBridge | 189:f392fc9709a3 | 487 | #define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */ |
| AnnaBridge | 189:f392fc9709a3 | 488 | #define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */ |
| AnnaBridge | 189:f392fc9709a3 | 489 | /** |
| AnnaBridge | 189:f392fc9709a3 | 490 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 491 | */ |
| AnnaBridge | 189:f392fc9709a3 | 492 | |
| AnnaBridge | 189:f392fc9709a3 | 493 | /** |
| AnnaBridge | 189:f392fc9709a3 | 494 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 495 | */ |
| AnnaBridge | 189:f392fc9709a3 | 496 | /* End of exported constants -------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 497 | |
| AnnaBridge | 189:f392fc9709a3 | 498 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 499 | /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 500 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 501 | */ |
| AnnaBridge | 189:f392fc9709a3 | 502 | |
| AnnaBridge | 189:f392fc9709a3 | 503 | /** @brief Reset DFSDM channel handle state. |
| AnnaBridge | 189:f392fc9709a3 | 504 | * @param __HANDLE__ DFSDM channel handle. |
| AnnaBridge | 189:f392fc9709a3 | 505 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 506 | */ |
| AnnaBridge | 189:f392fc9709a3 | 507 | #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) |
| AnnaBridge | 189:f392fc9709a3 | 508 | |
| AnnaBridge | 189:f392fc9709a3 | 509 | /** @brief Reset DFSDM filter handle state. |
| AnnaBridge | 189:f392fc9709a3 | 510 | * @param __HANDLE__ DFSDM filter handle. |
| AnnaBridge | 189:f392fc9709a3 | 511 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 512 | */ |
| AnnaBridge | 189:f392fc9709a3 | 513 | #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) |
| AnnaBridge | 189:f392fc9709a3 | 514 | |
| AnnaBridge | 189:f392fc9709a3 | 515 | /** |
| AnnaBridge | 189:f392fc9709a3 | 516 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 517 | */ |
| AnnaBridge | 189:f392fc9709a3 | 518 | /* End of exported macros ----------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 519 | |
| AnnaBridge | 189:f392fc9709a3 | 520 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 521 | /* Include DFSDM HAL Extension module */ |
| AnnaBridge | 189:f392fc9709a3 | 522 | #include "stm32l4xx_hal_dfsdm_ex.h" |
| AnnaBridge | 189:f392fc9709a3 | 523 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 524 | |
| AnnaBridge | 189:f392fc9709a3 | 525 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 526 | /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 527 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 528 | */ |
| AnnaBridge | 189:f392fc9709a3 | 529 | |
| AnnaBridge | 189:f392fc9709a3 | 530 | /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions |
| AnnaBridge | 189:f392fc9709a3 | 531 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 532 | */ |
| AnnaBridge | 189:f392fc9709a3 | 533 | /* Channel initialization and de-initialization functions *********************/ |
| AnnaBridge | 189:f392fc9709a3 | 534 | HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 535 | HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 536 | void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 537 | void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 538 | /** |
| AnnaBridge | 189:f392fc9709a3 | 539 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 540 | */ |
| AnnaBridge | 189:f392fc9709a3 | 541 | |
| AnnaBridge | 189:f392fc9709a3 | 542 | /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions |
| AnnaBridge | 189:f392fc9709a3 | 543 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 544 | */ |
| AnnaBridge | 189:f392fc9709a3 | 545 | /* Channel operation functions ************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 546 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 547 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 548 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 549 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 550 | |
| AnnaBridge | 189:f392fc9709a3 | 551 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); |
| AnnaBridge | 189:f392fc9709a3 | 552 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); |
| AnnaBridge | 189:f392fc9709a3 | 553 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 554 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 555 | |
| AnnaBridge | 189:f392fc9709a3 | 556 | int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 557 | HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); |
| AnnaBridge | 189:f392fc9709a3 | 558 | |
| AnnaBridge | 189:f392fc9709a3 | 559 | HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 560 | HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 561 | |
| AnnaBridge | 189:f392fc9709a3 | 562 | void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 563 | void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 564 | /** |
| AnnaBridge | 189:f392fc9709a3 | 565 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 566 | */ |
| AnnaBridge | 189:f392fc9709a3 | 567 | |
| AnnaBridge | 189:f392fc9709a3 | 568 | /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function |
| AnnaBridge | 189:f392fc9709a3 | 569 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 570 | */ |
| AnnaBridge | 189:f392fc9709a3 | 571 | /* Channel state function *****************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 572 | HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
| AnnaBridge | 189:f392fc9709a3 | 573 | /** |
| AnnaBridge | 189:f392fc9709a3 | 574 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 575 | */ |
| AnnaBridge | 189:f392fc9709a3 | 576 | |
| AnnaBridge | 189:f392fc9709a3 | 577 | /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions |
| AnnaBridge | 189:f392fc9709a3 | 578 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 579 | */ |
| AnnaBridge | 189:f392fc9709a3 | 580 | /* Filter initialization and de-initialization functions *********************/ |
| AnnaBridge | 189:f392fc9709a3 | 581 | HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 582 | HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 583 | void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 584 | void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 585 | /** |
| AnnaBridge | 189:f392fc9709a3 | 586 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 587 | */ |
| AnnaBridge | 189:f392fc9709a3 | 588 | |
| AnnaBridge | 189:f392fc9709a3 | 589 | /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions |
| AnnaBridge | 189:f392fc9709a3 | 590 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 591 | */ |
| AnnaBridge | 189:f392fc9709a3 | 592 | /* Filter control functions *********************/ |
| AnnaBridge | 189:f392fc9709a3 | 593 | HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
| AnnaBridge | 189:f392fc9709a3 | 594 | uint32_t Channel, |
| AnnaBridge | 189:f392fc9709a3 | 595 | uint32_t ContinuousMode); |
| AnnaBridge | 189:f392fc9709a3 | 596 | HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
| AnnaBridge | 189:f392fc9709a3 | 597 | uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 598 | /** |
| AnnaBridge | 189:f392fc9709a3 | 599 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 600 | */ |
| AnnaBridge | 189:f392fc9709a3 | 601 | |
| AnnaBridge | 189:f392fc9709a3 | 602 | /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions |
| AnnaBridge | 189:f392fc9709a3 | 603 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 604 | */ |
| AnnaBridge | 189:f392fc9709a3 | 605 | /* Filter operation functions *********************/ |
| AnnaBridge | 189:f392fc9709a3 | 606 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 607 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 608 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); |
| AnnaBridge | 189:f392fc9709a3 | 609 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); |
| AnnaBridge | 189:f392fc9709a3 | 610 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 611 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 612 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 613 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 614 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 615 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); |
| AnnaBridge | 189:f392fc9709a3 | 616 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); |
| AnnaBridge | 189:f392fc9709a3 | 617 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 618 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 619 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 620 | HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
| AnnaBridge | 189:f392fc9709a3 | 621 | DFSDM_Filter_AwdParamTypeDef* awdParam); |
| AnnaBridge | 189:f392fc9709a3 | 622 | HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 623 | HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 624 | HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 625 | |
| AnnaBridge | 189:f392fc9709a3 | 626 | int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
| AnnaBridge | 189:f392fc9709a3 | 627 | int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
| AnnaBridge | 189:f392fc9709a3 | 628 | int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
| AnnaBridge | 189:f392fc9709a3 | 629 | int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
| AnnaBridge | 189:f392fc9709a3 | 630 | uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 631 | |
| AnnaBridge | 189:f392fc9709a3 | 632 | void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 633 | |
| AnnaBridge | 189:f392fc9709a3 | 634 | HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 635 | HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 636 | |
| AnnaBridge | 189:f392fc9709a3 | 637 | void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 638 | void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 639 | void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 640 | void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 641 | void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); |
| AnnaBridge | 189:f392fc9709a3 | 642 | void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 643 | /** |
| AnnaBridge | 189:f392fc9709a3 | 644 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 645 | */ |
| AnnaBridge | 189:f392fc9709a3 | 646 | |
| AnnaBridge | 189:f392fc9709a3 | 647 | /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions |
| AnnaBridge | 189:f392fc9709a3 | 648 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 649 | */ |
| AnnaBridge | 189:f392fc9709a3 | 650 | /* Filter state functions *****************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 651 | HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 652 | uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
| AnnaBridge | 189:f392fc9709a3 | 653 | /** |
| AnnaBridge | 189:f392fc9709a3 | 654 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 655 | */ |
| AnnaBridge | 189:f392fc9709a3 | 656 | |
| AnnaBridge | 189:f392fc9709a3 | 657 | /** |
| AnnaBridge | 189:f392fc9709a3 | 658 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 659 | */ |
| AnnaBridge | 189:f392fc9709a3 | 660 | /* End of exported functions -------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 661 | |
| AnnaBridge | 189:f392fc9709a3 | 662 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 663 | /** @defgroup DFSDM_Private_Macros DFSDM Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 664 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 665 | */ |
| AnnaBridge | 189:f392fc9709a3 | 666 | #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ |
| AnnaBridge | 189:f392fc9709a3 | 667 | ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) |
| AnnaBridge | 189:f392fc9709a3 | 668 | #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) |
| AnnaBridge | 189:f392fc9709a3 | 669 | #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 670 | defined(STM32L496xx) || defined(STM32L4A6xx) || \ |
| AnnaBridge | 189:f392fc9709a3 | 671 | defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 672 | #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ |
| AnnaBridge | 189:f392fc9709a3 | 673 | ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 674 | ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) |
| AnnaBridge | 189:f392fc9709a3 | 675 | #else |
| AnnaBridge | 189:f392fc9709a3 | 676 | #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ |
| AnnaBridge | 189:f392fc9709a3 | 677 | ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) |
| AnnaBridge | 189:f392fc9709a3 | 678 | #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 679 | /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 680 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 681 | #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 682 | ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 683 | ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) |
| AnnaBridge | 189:f392fc9709a3 | 684 | #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ |
| AnnaBridge | 189:f392fc9709a3 | 685 | ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) |
| AnnaBridge | 189:f392fc9709a3 | 686 | #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ |
| AnnaBridge | 189:f392fc9709a3 | 687 | ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ |
| AnnaBridge | 189:f392fc9709a3 | 688 | ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ |
| AnnaBridge | 189:f392fc9709a3 | 689 | ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) |
| AnnaBridge | 189:f392fc9709a3 | 690 | #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ |
| AnnaBridge | 189:f392fc9709a3 | 691 | ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ |
| AnnaBridge | 189:f392fc9709a3 | 692 | ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ |
| AnnaBridge | 189:f392fc9709a3 | 693 | ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) |
| AnnaBridge | 189:f392fc9709a3 | 694 | #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ |
| AnnaBridge | 189:f392fc9709a3 | 695 | ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ |
| AnnaBridge | 189:f392fc9709a3 | 696 | ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ |
| AnnaBridge | 189:f392fc9709a3 | 697 | ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) |
| AnnaBridge | 189:f392fc9709a3 | 698 | #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32)) |
| AnnaBridge | 189:f392fc9709a3 | 699 | #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) |
| AnnaBridge | 189:f392fc9709a3 | 700 | #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F) |
| AnnaBridge | 189:f392fc9709a3 | 701 | #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF) |
| AnnaBridge | 189:f392fc9709a3 | 702 | #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ |
| AnnaBridge | 189:f392fc9709a3 | 703 | ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) |
| AnnaBridge | 189:f392fc9709a3 | 704 | #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ |
| AnnaBridge | 189:f392fc9709a3 | 705 | ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ |
| AnnaBridge | 189:f392fc9709a3 | 706 | ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) |
| AnnaBridge | 189:f392fc9709a3 | 707 | #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) |
| AnnaBridge | 189:f392fc9709a3 | 708 | #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 709 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 710 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 711 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 712 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 713 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ |
| AnnaBridge | 189:f392fc9709a3 | 714 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) |
| AnnaBridge | 189:f392fc9709a3 | 715 | #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
| AnnaBridge | 189:f392fc9709a3 | 716 | #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 717 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 718 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 719 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 720 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 721 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 722 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 723 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 724 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 725 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ |
| AnnaBridge | 189:f392fc9709a3 | 726 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \ |
| AnnaBridge | 189:f392fc9709a3 | 727 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT)) |
| AnnaBridge | 189:f392fc9709a3 | 728 | #else |
| AnnaBridge | 189:f392fc9709a3 | 729 | #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 730 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 731 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 732 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 733 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 734 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 735 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 736 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 737 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 738 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ |
| AnnaBridge | 189:f392fc9709a3 | 739 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) |
| AnnaBridge | 189:f392fc9709a3 | 740 | #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ |
| AnnaBridge | 189:f392fc9709a3 | 741 | #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 742 | ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 743 | ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) |
| AnnaBridge | 189:f392fc9709a3 | 744 | #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ |
| AnnaBridge | 189:f392fc9709a3 | 745 | ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ |
| AnnaBridge | 189:f392fc9709a3 | 746 | ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ |
| AnnaBridge | 189:f392fc9709a3 | 747 | ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ |
| AnnaBridge | 189:f392fc9709a3 | 748 | ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ |
| AnnaBridge | 189:f392fc9709a3 | 749 | ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) |
| AnnaBridge | 189:f392fc9709a3 | 750 | #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024)) |
| AnnaBridge | 189:f392fc9709a3 | 751 | #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256)) |
| AnnaBridge | 189:f392fc9709a3 | 752 | #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ |
| AnnaBridge | 189:f392fc9709a3 | 753 | ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) |
| AnnaBridge | 189:f392fc9709a3 | 754 | #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) |
| AnnaBridge | 189:f392fc9709a3 | 755 | #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) |
| AnnaBridge | 189:f392fc9709a3 | 756 | #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) |
| AnnaBridge | 189:f392fc9709a3 | 757 | #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ |
| AnnaBridge | 189:f392fc9709a3 | 758 | ((CHANNEL) == DFSDM_CHANNEL_1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 759 | ((CHANNEL) == DFSDM_CHANNEL_2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 760 | ((CHANNEL) == DFSDM_CHANNEL_3)) |
| AnnaBridge | 189:f392fc9709a3 | 761 | #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x0003000FU)) |
| AnnaBridge | 189:f392fc9709a3 | 762 | #else |
| AnnaBridge | 189:f392fc9709a3 | 763 | #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ |
| AnnaBridge | 189:f392fc9709a3 | 764 | ((CHANNEL) == DFSDM_CHANNEL_1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 765 | ((CHANNEL) == DFSDM_CHANNEL_2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 766 | ((CHANNEL) == DFSDM_CHANNEL_3) || \ |
| AnnaBridge | 189:f392fc9709a3 | 767 | ((CHANNEL) == DFSDM_CHANNEL_4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 768 | ((CHANNEL) == DFSDM_CHANNEL_5) || \ |
| AnnaBridge | 189:f392fc9709a3 | 769 | ((CHANNEL) == DFSDM_CHANNEL_6) || \ |
| AnnaBridge | 189:f392fc9709a3 | 770 | ((CHANNEL) == DFSDM_CHANNEL_7)) |
| AnnaBridge | 189:f392fc9709a3 | 771 | #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU)) |
| AnnaBridge | 189:f392fc9709a3 | 772 | #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ |
| AnnaBridge | 189:f392fc9709a3 | 773 | #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ |
| AnnaBridge | 189:f392fc9709a3 | 774 | ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) |
| AnnaBridge | 189:f392fc9709a3 | 775 | /** |
| AnnaBridge | 189:f392fc9709a3 | 776 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 777 | */ |
| AnnaBridge | 189:f392fc9709a3 | 778 | /* End of private macros -----------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 779 | |
| AnnaBridge | 189:f392fc9709a3 | 780 | /** |
| AnnaBridge | 189:f392fc9709a3 | 781 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 782 | */ |
| AnnaBridge | 189:f392fc9709a3 | 783 | |
| AnnaBridge | 189:f392fc9709a3 | 784 | /** |
| AnnaBridge | 189:f392fc9709a3 | 785 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 786 | */ |
| AnnaBridge | 189:f392fc9709a3 | 787 | #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 788 | /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 789 | /* STM32L496xx || STM32L4A6xx || */ |
| AnnaBridge | 189:f392fc9709a3 | 790 | /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
| AnnaBridge | 189:f392fc9709a3 | 791 | |
| AnnaBridge | 189:f392fc9709a3 | 792 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 793 | } |
| AnnaBridge | 189:f392fc9709a3 | 794 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 795 | |
| AnnaBridge | 189:f392fc9709a3 | 796 | #endif /* __STM32L4xx_HAL_DFSDM_H */ |
| AnnaBridge | 189:f392fc9709a3 | 797 | |
| AnnaBridge | 189:f392fc9709a3 | 798 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
