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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_ARM_STD/stm32l4xx_hal_cortex.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l4xx_hal_cortex.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of CORTEX HAL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L4xx_HAL_CORTEX_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L4xx_HAL_CORTEX_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l4xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32L4xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | /** @defgroup CORTEX CORTEX |
| AnnaBridge | 189:f392fc9709a3 | 52 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 53 | */ |
| AnnaBridge | 189:f392fc9709a3 | 54 | |
| AnnaBridge | 189:f392fc9709a3 | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 56 | /** @defgroup CORTEX_Exported_Types CORTEX Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 57 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 58 | */ |
| AnnaBridge | 189:f392fc9709a3 | 59 | |
| AnnaBridge | 189:f392fc9709a3 | 60 | #if (__MPU_PRESENT == 1) |
| AnnaBridge | 189:f392fc9709a3 | 61 | /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition |
| AnnaBridge | 189:f392fc9709a3 | 62 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 63 | */ |
| AnnaBridge | 189:f392fc9709a3 | 64 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 65 | { |
| AnnaBridge | 189:f392fc9709a3 | 66 | uint8_t Enable; /*!< Specifies the status of the region. |
| AnnaBridge | 189:f392fc9709a3 | 67 | This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 68 | uint8_t Number; /*!< Specifies the number of the region to protect. |
| AnnaBridge | 189:f392fc9709a3 | 69 | This parameter can be a value of @ref CORTEX_MPU_Region_Number */ |
| AnnaBridge | 189:f392fc9709a3 | 70 | uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ |
| AnnaBridge | 189:f392fc9709a3 | 71 | uint8_t Size; /*!< Specifies the size of the region to protect. |
| AnnaBridge | 189:f392fc9709a3 | 72 | This parameter can be a value of @ref CORTEX_MPU_Region_Size */ |
| AnnaBridge | 189:f392fc9709a3 | 73 | uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. |
| AnnaBridge | 189:f392fc9709a3 | 74 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
| AnnaBridge | 189:f392fc9709a3 | 75 | uint8_t TypeExtField; /*!< Specifies the TEX field level. |
| AnnaBridge | 189:f392fc9709a3 | 76 | This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ |
| AnnaBridge | 189:f392fc9709a3 | 77 | uint8_t AccessPermission; /*!< Specifies the region access permission type. |
| AnnaBridge | 189:f392fc9709a3 | 78 | This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ |
| AnnaBridge | 189:f392fc9709a3 | 79 | uint8_t DisableExec; /*!< Specifies the instruction access status. |
| AnnaBridge | 189:f392fc9709a3 | 80 | This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ |
| AnnaBridge | 189:f392fc9709a3 | 81 | uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. |
| AnnaBridge | 189:f392fc9709a3 | 82 | This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ |
| AnnaBridge | 189:f392fc9709a3 | 83 | uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. |
| AnnaBridge | 189:f392fc9709a3 | 84 | This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ |
| AnnaBridge | 189:f392fc9709a3 | 85 | uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. |
| AnnaBridge | 189:f392fc9709a3 | 86 | This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ |
| AnnaBridge | 189:f392fc9709a3 | 87 | }MPU_Region_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 88 | /** |
| AnnaBridge | 189:f392fc9709a3 | 89 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 90 | */ |
| AnnaBridge | 189:f392fc9709a3 | 91 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 189:f392fc9709a3 | 92 | |
| AnnaBridge | 189:f392fc9709a3 | 93 | /** |
| AnnaBridge | 189:f392fc9709a3 | 94 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 95 | */ |
| AnnaBridge | 189:f392fc9709a3 | 96 | |
| AnnaBridge | 189:f392fc9709a3 | 97 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 98 | |
| AnnaBridge | 189:f392fc9709a3 | 99 | /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 100 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 101 | */ |
| AnnaBridge | 189:f392fc9709a3 | 102 | |
| AnnaBridge | 189:f392fc9709a3 | 103 | /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group |
| AnnaBridge | 189:f392fc9709a3 | 104 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 105 | */ |
| AnnaBridge | 189:f392fc9709a3 | 106 | #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, |
| AnnaBridge | 189:f392fc9709a3 | 107 | 4 bits for subpriority */ |
| AnnaBridge | 189:f392fc9709a3 | 108 | #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, |
| AnnaBridge | 189:f392fc9709a3 | 109 | 3 bits for subpriority */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, |
| AnnaBridge | 189:f392fc9709a3 | 111 | 2 bits for subpriority */ |
| AnnaBridge | 189:f392fc9709a3 | 112 | #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, |
| AnnaBridge | 189:f392fc9709a3 | 113 | 1 bit for subpriority */ |
| AnnaBridge | 189:f392fc9709a3 | 114 | #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, |
| AnnaBridge | 189:f392fc9709a3 | 115 | 0 bit for subpriority */ |
| AnnaBridge | 189:f392fc9709a3 | 116 | /** |
| AnnaBridge | 189:f392fc9709a3 | 117 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 118 | */ |
| AnnaBridge | 189:f392fc9709a3 | 119 | |
| AnnaBridge | 189:f392fc9709a3 | 120 | /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source |
| AnnaBridge | 189:f392fc9709a3 | 121 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 122 | */ |
| AnnaBridge | 189:f392fc9709a3 | 123 | #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 124 | #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) |
| AnnaBridge | 189:f392fc9709a3 | 125 | /** |
| AnnaBridge | 189:f392fc9709a3 | 126 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 127 | */ |
| AnnaBridge | 189:f392fc9709a3 | 128 | |
| AnnaBridge | 189:f392fc9709a3 | 129 | #if (__MPU_PRESENT == 1) |
| AnnaBridge | 189:f392fc9709a3 | 130 | /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control |
| AnnaBridge | 189:f392fc9709a3 | 131 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 132 | */ |
| AnnaBridge | 189:f392fc9709a3 | 133 | #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) |
| AnnaBridge | 189:f392fc9709a3 | 134 | #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) |
| AnnaBridge | 189:f392fc9709a3 | 135 | #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) |
| AnnaBridge | 189:f392fc9709a3 | 136 | #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) |
| AnnaBridge | 189:f392fc9709a3 | 137 | /** |
| AnnaBridge | 189:f392fc9709a3 | 138 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 139 | */ |
| AnnaBridge | 189:f392fc9709a3 | 140 | |
| AnnaBridge | 189:f392fc9709a3 | 141 | /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable |
| AnnaBridge | 189:f392fc9709a3 | 142 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 143 | */ |
| AnnaBridge | 189:f392fc9709a3 | 144 | #define MPU_REGION_ENABLE ((uint8_t)0x01) |
| AnnaBridge | 189:f392fc9709a3 | 145 | #define MPU_REGION_DISABLE ((uint8_t)0x00) |
| AnnaBridge | 189:f392fc9709a3 | 146 | /** |
| AnnaBridge | 189:f392fc9709a3 | 147 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 148 | */ |
| AnnaBridge | 189:f392fc9709a3 | 149 | |
| AnnaBridge | 189:f392fc9709a3 | 150 | /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access |
| AnnaBridge | 189:f392fc9709a3 | 151 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 152 | */ |
| AnnaBridge | 189:f392fc9709a3 | 153 | #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) |
| AnnaBridge | 189:f392fc9709a3 | 154 | #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) |
| AnnaBridge | 189:f392fc9709a3 | 155 | /** |
| AnnaBridge | 189:f392fc9709a3 | 156 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 157 | */ |
| AnnaBridge | 189:f392fc9709a3 | 158 | |
| AnnaBridge | 189:f392fc9709a3 | 159 | /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable |
| AnnaBridge | 189:f392fc9709a3 | 160 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 161 | */ |
| AnnaBridge | 189:f392fc9709a3 | 162 | #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) |
| AnnaBridge | 189:f392fc9709a3 | 163 | #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) |
| AnnaBridge | 189:f392fc9709a3 | 164 | /** |
| AnnaBridge | 189:f392fc9709a3 | 165 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 166 | */ |
| AnnaBridge | 189:f392fc9709a3 | 167 | |
| AnnaBridge | 189:f392fc9709a3 | 168 | /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable |
| AnnaBridge | 189:f392fc9709a3 | 169 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 170 | */ |
| AnnaBridge | 189:f392fc9709a3 | 171 | #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) |
| AnnaBridge | 189:f392fc9709a3 | 172 | #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) |
| AnnaBridge | 189:f392fc9709a3 | 173 | /** |
| AnnaBridge | 189:f392fc9709a3 | 174 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 175 | */ |
| AnnaBridge | 189:f392fc9709a3 | 176 | |
| AnnaBridge | 189:f392fc9709a3 | 177 | /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable |
| AnnaBridge | 189:f392fc9709a3 | 178 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 179 | */ |
| AnnaBridge | 189:f392fc9709a3 | 180 | #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) |
| AnnaBridge | 189:f392fc9709a3 | 181 | #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) |
| AnnaBridge | 189:f392fc9709a3 | 182 | /** |
| AnnaBridge | 189:f392fc9709a3 | 183 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 184 | */ |
| AnnaBridge | 189:f392fc9709a3 | 185 | |
| AnnaBridge | 189:f392fc9709a3 | 186 | /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels |
| AnnaBridge | 189:f392fc9709a3 | 187 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 188 | */ |
| AnnaBridge | 189:f392fc9709a3 | 189 | #define MPU_TEX_LEVEL0 ((uint8_t)0x00) |
| AnnaBridge | 189:f392fc9709a3 | 190 | #define MPU_TEX_LEVEL1 ((uint8_t)0x01) |
| AnnaBridge | 189:f392fc9709a3 | 191 | #define MPU_TEX_LEVEL2 ((uint8_t)0x02) |
| AnnaBridge | 189:f392fc9709a3 | 192 | /** |
| AnnaBridge | 189:f392fc9709a3 | 193 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 194 | */ |
| AnnaBridge | 189:f392fc9709a3 | 195 | |
| AnnaBridge | 189:f392fc9709a3 | 196 | /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size |
| AnnaBridge | 189:f392fc9709a3 | 197 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 198 | */ |
| AnnaBridge | 189:f392fc9709a3 | 199 | #define MPU_REGION_SIZE_32B ((uint8_t)0x04) |
| AnnaBridge | 189:f392fc9709a3 | 200 | #define MPU_REGION_SIZE_64B ((uint8_t)0x05) |
| AnnaBridge | 189:f392fc9709a3 | 201 | #define MPU_REGION_SIZE_128B ((uint8_t)0x06) |
| AnnaBridge | 189:f392fc9709a3 | 202 | #define MPU_REGION_SIZE_256B ((uint8_t)0x07) |
| AnnaBridge | 189:f392fc9709a3 | 203 | #define MPU_REGION_SIZE_512B ((uint8_t)0x08) |
| AnnaBridge | 189:f392fc9709a3 | 204 | #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) |
| AnnaBridge | 189:f392fc9709a3 | 205 | #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) |
| AnnaBridge | 189:f392fc9709a3 | 206 | #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) |
| AnnaBridge | 189:f392fc9709a3 | 207 | #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) |
| AnnaBridge | 189:f392fc9709a3 | 208 | #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) |
| AnnaBridge | 189:f392fc9709a3 | 209 | #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) |
| AnnaBridge | 189:f392fc9709a3 | 210 | #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) |
| AnnaBridge | 189:f392fc9709a3 | 211 | #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) |
| AnnaBridge | 189:f392fc9709a3 | 212 | #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) |
| AnnaBridge | 189:f392fc9709a3 | 213 | #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) |
| AnnaBridge | 189:f392fc9709a3 | 214 | #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) |
| AnnaBridge | 189:f392fc9709a3 | 215 | #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) |
| AnnaBridge | 189:f392fc9709a3 | 216 | #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) |
| AnnaBridge | 189:f392fc9709a3 | 217 | #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) |
| AnnaBridge | 189:f392fc9709a3 | 218 | #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) |
| AnnaBridge | 189:f392fc9709a3 | 219 | #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) |
| AnnaBridge | 189:f392fc9709a3 | 220 | #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) |
| AnnaBridge | 189:f392fc9709a3 | 221 | #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) |
| AnnaBridge | 189:f392fc9709a3 | 222 | #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) |
| AnnaBridge | 189:f392fc9709a3 | 223 | #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) |
| AnnaBridge | 189:f392fc9709a3 | 224 | #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) |
| AnnaBridge | 189:f392fc9709a3 | 225 | #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) |
| AnnaBridge | 189:f392fc9709a3 | 226 | #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) |
| AnnaBridge | 189:f392fc9709a3 | 227 | /** |
| AnnaBridge | 189:f392fc9709a3 | 228 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 229 | */ |
| AnnaBridge | 189:f392fc9709a3 | 230 | |
| AnnaBridge | 189:f392fc9709a3 | 231 | /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes |
| AnnaBridge | 189:f392fc9709a3 | 232 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 233 | */ |
| AnnaBridge | 189:f392fc9709a3 | 234 | #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) |
| AnnaBridge | 189:f392fc9709a3 | 235 | #define MPU_REGION_PRIV_RW ((uint8_t)0x01) |
| AnnaBridge | 189:f392fc9709a3 | 236 | #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) |
| AnnaBridge | 189:f392fc9709a3 | 237 | #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) |
| AnnaBridge | 189:f392fc9709a3 | 238 | #define MPU_REGION_PRIV_RO ((uint8_t)0x05) |
| AnnaBridge | 189:f392fc9709a3 | 239 | #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) |
| AnnaBridge | 189:f392fc9709a3 | 240 | /** |
| AnnaBridge | 189:f392fc9709a3 | 241 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 242 | */ |
| AnnaBridge | 189:f392fc9709a3 | 243 | |
| AnnaBridge | 189:f392fc9709a3 | 244 | /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number |
| AnnaBridge | 189:f392fc9709a3 | 245 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 246 | */ |
| AnnaBridge | 189:f392fc9709a3 | 247 | #define MPU_REGION_NUMBER0 ((uint8_t)0x00) |
| AnnaBridge | 189:f392fc9709a3 | 248 | #define MPU_REGION_NUMBER1 ((uint8_t)0x01) |
| AnnaBridge | 189:f392fc9709a3 | 249 | #define MPU_REGION_NUMBER2 ((uint8_t)0x02) |
| AnnaBridge | 189:f392fc9709a3 | 250 | #define MPU_REGION_NUMBER3 ((uint8_t)0x03) |
| AnnaBridge | 189:f392fc9709a3 | 251 | #define MPU_REGION_NUMBER4 ((uint8_t)0x04) |
| AnnaBridge | 189:f392fc9709a3 | 252 | #define MPU_REGION_NUMBER5 ((uint8_t)0x05) |
| AnnaBridge | 189:f392fc9709a3 | 253 | #define MPU_REGION_NUMBER6 ((uint8_t)0x06) |
| AnnaBridge | 189:f392fc9709a3 | 254 | #define MPU_REGION_NUMBER7 ((uint8_t)0x07) |
| AnnaBridge | 189:f392fc9709a3 | 255 | /** |
| AnnaBridge | 189:f392fc9709a3 | 256 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 257 | */ |
| AnnaBridge | 189:f392fc9709a3 | 258 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 189:f392fc9709a3 | 259 | |
| AnnaBridge | 189:f392fc9709a3 | 260 | /** |
| AnnaBridge | 189:f392fc9709a3 | 261 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 262 | */ |
| AnnaBridge | 189:f392fc9709a3 | 263 | |
| AnnaBridge | 189:f392fc9709a3 | 264 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 265 | /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 266 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 267 | */ |
| AnnaBridge | 189:f392fc9709a3 | 268 | |
| AnnaBridge | 189:f392fc9709a3 | 269 | /** |
| AnnaBridge | 189:f392fc9709a3 | 270 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 271 | */ |
| AnnaBridge | 189:f392fc9709a3 | 272 | |
| AnnaBridge | 189:f392fc9709a3 | 273 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 274 | /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 275 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 276 | */ |
| AnnaBridge | 189:f392fc9709a3 | 277 | |
| AnnaBridge | 189:f392fc9709a3 | 278 | /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions |
| AnnaBridge | 189:f392fc9709a3 | 279 | * @brief Initialization and Configuration functions |
| AnnaBridge | 189:f392fc9709a3 | 280 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 281 | */ |
| AnnaBridge | 189:f392fc9709a3 | 282 | /* Initialization and Configuration functions *****************************/ |
| AnnaBridge | 189:f392fc9709a3 | 283 | void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); |
| AnnaBridge | 189:f392fc9709a3 | 284 | void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); |
| AnnaBridge | 189:f392fc9709a3 | 285 | void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); |
| AnnaBridge | 189:f392fc9709a3 | 286 | void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); |
| AnnaBridge | 189:f392fc9709a3 | 287 | void HAL_NVIC_SystemReset(void); |
| AnnaBridge | 189:f392fc9709a3 | 288 | uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); |
| AnnaBridge | 189:f392fc9709a3 | 289 | |
| AnnaBridge | 189:f392fc9709a3 | 290 | /** |
| AnnaBridge | 189:f392fc9709a3 | 291 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 292 | */ |
| AnnaBridge | 189:f392fc9709a3 | 293 | |
| AnnaBridge | 189:f392fc9709a3 | 294 | /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions |
| AnnaBridge | 189:f392fc9709a3 | 295 | * @brief Cortex control functions |
| AnnaBridge | 189:f392fc9709a3 | 296 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 297 | */ |
| AnnaBridge | 189:f392fc9709a3 | 298 | /* Peripheral Control functions ***********************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 299 | uint32_t HAL_NVIC_GetPriorityGrouping(void); |
| AnnaBridge | 189:f392fc9709a3 | 300 | void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); |
| AnnaBridge | 189:f392fc9709a3 | 301 | uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); |
| AnnaBridge | 189:f392fc9709a3 | 302 | void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); |
| AnnaBridge | 189:f392fc9709a3 | 303 | void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); |
| AnnaBridge | 189:f392fc9709a3 | 304 | uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); |
| AnnaBridge | 189:f392fc9709a3 | 305 | void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); |
| AnnaBridge | 189:f392fc9709a3 | 306 | void HAL_SYSTICK_IRQHandler(void); |
| AnnaBridge | 189:f392fc9709a3 | 307 | void HAL_SYSTICK_Callback(void); |
| AnnaBridge | 189:f392fc9709a3 | 308 | |
| AnnaBridge | 189:f392fc9709a3 | 309 | #if (__MPU_PRESENT == 1) |
| AnnaBridge | 189:f392fc9709a3 | 310 | void HAL_MPU_Enable(uint32_t MPU_Control); |
| AnnaBridge | 189:f392fc9709a3 | 311 | void HAL_MPU_Disable(void); |
| AnnaBridge | 189:f392fc9709a3 | 312 | void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); |
| AnnaBridge | 189:f392fc9709a3 | 313 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 189:f392fc9709a3 | 314 | /** |
| AnnaBridge | 189:f392fc9709a3 | 315 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 316 | */ |
| AnnaBridge | 189:f392fc9709a3 | 317 | |
| AnnaBridge | 189:f392fc9709a3 | 318 | /** |
| AnnaBridge | 189:f392fc9709a3 | 319 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 320 | */ |
| AnnaBridge | 189:f392fc9709a3 | 321 | |
| AnnaBridge | 189:f392fc9709a3 | 322 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 323 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 324 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 325 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 326 | /** @defgroup CORTEX_Private_Macros CORTEX Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 327 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 328 | */ |
| AnnaBridge | 189:f392fc9709a3 | 329 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ |
| AnnaBridge | 189:f392fc9709a3 | 330 | ((GROUP) == NVIC_PRIORITYGROUP_1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 331 | ((GROUP) == NVIC_PRIORITYGROUP_2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 332 | ((GROUP) == NVIC_PRIORITYGROUP_3) || \ |
| AnnaBridge | 189:f392fc9709a3 | 333 | ((GROUP) == NVIC_PRIORITYGROUP_4)) |
| AnnaBridge | 189:f392fc9709a3 | 334 | |
| AnnaBridge | 189:f392fc9709a3 | 335 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) |
| AnnaBridge | 189:f392fc9709a3 | 336 | |
| AnnaBridge | 189:f392fc9709a3 | 337 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) |
| AnnaBridge | 189:f392fc9709a3 | 338 | |
| AnnaBridge | 189:f392fc9709a3 | 339 | #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) |
| AnnaBridge | 189:f392fc9709a3 | 340 | |
| AnnaBridge | 189:f392fc9709a3 | 341 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ |
| AnnaBridge | 189:f392fc9709a3 | 342 | ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) |
| AnnaBridge | 189:f392fc9709a3 | 343 | |
| AnnaBridge | 189:f392fc9709a3 | 344 | #if (__MPU_PRESENT == 1) |
| AnnaBridge | 189:f392fc9709a3 | 345 | #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 346 | ((STATE) == MPU_REGION_DISABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 347 | |
| AnnaBridge | 189:f392fc9709a3 | 348 | #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 349 | ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 350 | |
| AnnaBridge | 189:f392fc9709a3 | 351 | #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 352 | ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 353 | |
| AnnaBridge | 189:f392fc9709a3 | 354 | #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 355 | ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 356 | |
| AnnaBridge | 189:f392fc9709a3 | 357 | #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 358 | ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 359 | |
| AnnaBridge | 189:f392fc9709a3 | 360 | #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ |
| AnnaBridge | 189:f392fc9709a3 | 361 | ((TYPE) == MPU_TEX_LEVEL1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 362 | ((TYPE) == MPU_TEX_LEVEL2)) |
| AnnaBridge | 189:f392fc9709a3 | 363 | |
| AnnaBridge | 189:f392fc9709a3 | 364 | #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ |
| AnnaBridge | 189:f392fc9709a3 | 365 | ((TYPE) == MPU_REGION_PRIV_RW) || \ |
| AnnaBridge | 189:f392fc9709a3 | 366 | ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 367 | ((TYPE) == MPU_REGION_FULL_ACCESS) || \ |
| AnnaBridge | 189:f392fc9709a3 | 368 | ((TYPE) == MPU_REGION_PRIV_RO) || \ |
| AnnaBridge | 189:f392fc9709a3 | 369 | ((TYPE) == MPU_REGION_PRIV_RO_URO)) |
| AnnaBridge | 189:f392fc9709a3 | 370 | |
| AnnaBridge | 189:f392fc9709a3 | 371 | #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ |
| AnnaBridge | 189:f392fc9709a3 | 372 | ((NUMBER) == MPU_REGION_NUMBER1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 373 | ((NUMBER) == MPU_REGION_NUMBER2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 374 | ((NUMBER) == MPU_REGION_NUMBER3) || \ |
| AnnaBridge | 189:f392fc9709a3 | 375 | ((NUMBER) == MPU_REGION_NUMBER4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 376 | ((NUMBER) == MPU_REGION_NUMBER5) || \ |
| AnnaBridge | 189:f392fc9709a3 | 377 | ((NUMBER) == MPU_REGION_NUMBER6) || \ |
| AnnaBridge | 189:f392fc9709a3 | 378 | ((NUMBER) == MPU_REGION_NUMBER7)) |
| AnnaBridge | 189:f392fc9709a3 | 379 | |
| AnnaBridge | 189:f392fc9709a3 | 380 | #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ |
| AnnaBridge | 189:f392fc9709a3 | 381 | ((SIZE) == MPU_REGION_SIZE_64B) || \ |
| AnnaBridge | 189:f392fc9709a3 | 382 | ((SIZE) == MPU_REGION_SIZE_128B) || \ |
| AnnaBridge | 189:f392fc9709a3 | 383 | ((SIZE) == MPU_REGION_SIZE_256B) || \ |
| AnnaBridge | 189:f392fc9709a3 | 384 | ((SIZE) == MPU_REGION_SIZE_512B) || \ |
| AnnaBridge | 189:f392fc9709a3 | 385 | ((SIZE) == MPU_REGION_SIZE_1KB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 386 | ((SIZE) == MPU_REGION_SIZE_2KB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 387 | ((SIZE) == MPU_REGION_SIZE_4KB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 388 | ((SIZE) == MPU_REGION_SIZE_8KB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 389 | ((SIZE) == MPU_REGION_SIZE_16KB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 390 | ((SIZE) == MPU_REGION_SIZE_32KB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 391 | ((SIZE) == MPU_REGION_SIZE_64KB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 392 | ((SIZE) == MPU_REGION_SIZE_128KB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 393 | ((SIZE) == MPU_REGION_SIZE_256KB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 394 | ((SIZE) == MPU_REGION_SIZE_512KB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 395 | ((SIZE) == MPU_REGION_SIZE_1MB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 396 | ((SIZE) == MPU_REGION_SIZE_2MB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 397 | ((SIZE) == MPU_REGION_SIZE_4MB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 398 | ((SIZE) == MPU_REGION_SIZE_8MB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 399 | ((SIZE) == MPU_REGION_SIZE_16MB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 400 | ((SIZE) == MPU_REGION_SIZE_32MB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 401 | ((SIZE) == MPU_REGION_SIZE_64MB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 402 | ((SIZE) == MPU_REGION_SIZE_128MB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 403 | ((SIZE) == MPU_REGION_SIZE_256MB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 404 | ((SIZE) == MPU_REGION_SIZE_512MB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 405 | ((SIZE) == MPU_REGION_SIZE_1GB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 406 | ((SIZE) == MPU_REGION_SIZE_2GB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 407 | ((SIZE) == MPU_REGION_SIZE_4GB)) |
| AnnaBridge | 189:f392fc9709a3 | 408 | |
| AnnaBridge | 189:f392fc9709a3 | 409 | #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) |
| AnnaBridge | 189:f392fc9709a3 | 410 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 189:f392fc9709a3 | 411 | |
| AnnaBridge | 189:f392fc9709a3 | 412 | /** |
| AnnaBridge | 189:f392fc9709a3 | 413 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 414 | */ |
| AnnaBridge | 189:f392fc9709a3 | 415 | |
| AnnaBridge | 189:f392fc9709a3 | 416 | /* Private functions ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 417 | |
| AnnaBridge | 189:f392fc9709a3 | 418 | /** |
| AnnaBridge | 189:f392fc9709a3 | 419 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 420 | */ |
| AnnaBridge | 189:f392fc9709a3 | 421 | |
| AnnaBridge | 189:f392fc9709a3 | 422 | /** |
| AnnaBridge | 189:f392fc9709a3 | 423 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 424 | */ |
| AnnaBridge | 189:f392fc9709a3 | 425 | |
| AnnaBridge | 189:f392fc9709a3 | 426 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 427 | } |
| AnnaBridge | 189:f392fc9709a3 | 428 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 429 | |
| AnnaBridge | 189:f392fc9709a3 | 430 | #endif /* __STM32L4xx_HAL_CORTEX_H */ |
| AnnaBridge | 189:f392fc9709a3 | 431 | |
| AnnaBridge | 189:f392fc9709a3 | 432 | |
| AnnaBridge | 189:f392fc9709a3 | 433 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
