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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_ARM_STD/stm32l4xx_hal_adc_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

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AnnaBridge 189:f392fc9709a3 1 /**
AnnaBridge 189:f392fc9709a3 2 ******************************************************************************
AnnaBridge 189:f392fc9709a3 3 * @file stm32l4xx_hal_adc_ex.h
AnnaBridge 189:f392fc9709a3 4 * @author MCD Application Team
AnnaBridge 189:f392fc9709a3 5 * @brief Header file of ADC HAL extended module.
AnnaBridge 189:f392fc9709a3 6 ******************************************************************************
AnnaBridge 189:f392fc9709a3 7 * @attention
AnnaBridge 189:f392fc9709a3 8 *
AnnaBridge 189:f392fc9709a3 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 189:f392fc9709a3 10 *
AnnaBridge 189:f392fc9709a3 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 12 * are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 189:f392fc9709a3 14 * this list of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 189:f392fc9709a3 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 189:f392fc9709a3 17 * and/or other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 189:f392fc9709a3 19 * may be used to endorse or promote products derived from this software
AnnaBridge 189:f392fc9709a3 20 * without specific prior written permission.
AnnaBridge 189:f392fc9709a3 21 *
AnnaBridge 189:f392fc9709a3 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 189:f392fc9709a3 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 189:f392fc9709a3 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 189:f392fc9709a3 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 189:f392fc9709a3 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 189:f392fc9709a3 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 189:f392fc9709a3 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 189:f392fc9709a3 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 189:f392fc9709a3 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 189:f392fc9709a3 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 32 *
AnnaBridge 189:f392fc9709a3 33 ******************************************************************************
AnnaBridge 189:f392fc9709a3 34 */
AnnaBridge 189:f392fc9709a3 35
AnnaBridge 189:f392fc9709a3 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 189:f392fc9709a3 37 #ifndef __STM32L4xx_HAL_ADC_EX_H
AnnaBridge 189:f392fc9709a3 38 #define __STM32L4xx_HAL_ADC_EX_H
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 41 extern "C" {
AnnaBridge 189:f392fc9709a3 42 #endif
AnnaBridge 189:f392fc9709a3 43
AnnaBridge 189:f392fc9709a3 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 45 #include "stm32l4xx_hal_def.h"
AnnaBridge 189:f392fc9709a3 46
AnnaBridge 189:f392fc9709a3 47 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 189:f392fc9709a3 48 * @{
AnnaBridge 189:f392fc9709a3 49 */
AnnaBridge 189:f392fc9709a3 50
AnnaBridge 189:f392fc9709a3 51 /** @addtogroup ADCEx
AnnaBridge 189:f392fc9709a3 52 * @{
AnnaBridge 189:f392fc9709a3 53 */
AnnaBridge 189:f392fc9709a3 54
AnnaBridge 189:f392fc9709a3 55 /* Exported types ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 56 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
AnnaBridge 189:f392fc9709a3 57 * @{
AnnaBridge 189:f392fc9709a3 58 */
AnnaBridge 189:f392fc9709a3 59
AnnaBridge 189:f392fc9709a3 60 /**
AnnaBridge 189:f392fc9709a3 61 * @brief ADC Injected Conversion Oversampling structure definition
AnnaBridge 189:f392fc9709a3 62 */
AnnaBridge 189:f392fc9709a3 63 typedef struct
AnnaBridge 189:f392fc9709a3 64 {
AnnaBridge 189:f392fc9709a3 65 uint32_t Ratio; /*!< Configures the oversampling ratio.
AnnaBridge 189:f392fc9709a3 66 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
AnnaBridge 189:f392fc9709a3 67
AnnaBridge 189:f392fc9709a3 68 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
AnnaBridge 189:f392fc9709a3 69 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
AnnaBridge 189:f392fc9709a3 70 }ADC_InjOversamplingTypeDef;
AnnaBridge 189:f392fc9709a3 71
AnnaBridge 189:f392fc9709a3 72 /**
AnnaBridge 189:f392fc9709a3 73 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
AnnaBridge 189:f392fc9709a3 74 * @note Parameters of this structure are shared within 2 scopes:
AnnaBridge 189:f392fc9709a3 75 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
AnnaBridge 189:f392fc9709a3 76 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
AnnaBridge 189:f392fc9709a3 77 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
AnnaBridge 189:f392fc9709a3 78 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
AnnaBridge 189:f392fc9709a3 79 * ADC state can be either:
AnnaBridge 189:f392fc9709a3 80 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
AnnaBridge 189:f392fc9709a3 81 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
AnnaBridge 189:f392fc9709a3 82 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
AnnaBridge 189:f392fc9709a3 83 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
AnnaBridge 189:f392fc9709a3 84 * on ADC groups regular and injected.
AnnaBridge 189:f392fc9709a3 85 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
AnnaBridge 189:f392fc9709a3 86 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
AnnaBridge 189:f392fc9709a3 87 */
AnnaBridge 189:f392fc9709a3 88 typedef struct
AnnaBridge 189:f392fc9709a3 89 {
AnnaBridge 189:f392fc9709a3 90 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
AnnaBridge 189:f392fc9709a3 91 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
AnnaBridge 189:f392fc9709a3 92 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
AnnaBridge 189:f392fc9709a3 93
AnnaBridge 189:f392fc9709a3 94 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
AnnaBridge 189:f392fc9709a3 95 This parameter must be a value of @ref ADC_LL_EC_INJ_SEQ_RANKS.
AnnaBridge 189:f392fc9709a3 96 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
AnnaBridge 189:f392fc9709a3 97 the new channel setting (or parameter number of conversions adjusted) */
AnnaBridge 189:f392fc9709a3 98
AnnaBridge 189:f392fc9709a3 99 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
AnnaBridge 189:f392fc9709a3 100 Unit: ADC clock cycles.
AnnaBridge 189:f392fc9709a3 101 Conversion time is the addition of sampling time and processing time
AnnaBridge 189:f392fc9709a3 102 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
AnnaBridge 189:f392fc9709a3 103 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
AnnaBridge 189:f392fc9709a3 104 Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
AnnaBridge 189:f392fc9709a3 105 It overwrites the last setting.
AnnaBridge 189:f392fc9709a3 106 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
AnnaBridge 189:f392fc9709a3 107 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
AnnaBridge 189:f392fc9709a3 108 Refer to device datasheet for timings values. */
AnnaBridge 189:f392fc9709a3 109
AnnaBridge 189:f392fc9709a3 110 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
AnnaBridge 189:f392fc9709a3 111 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
AnnaBridge 189:f392fc9709a3 112 Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
AnnaBridge 189:f392fc9709a3 113 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
AnnaBridge 189:f392fc9709a3 114 Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
AnnaBridge 189:f392fc9709a3 115 It overwrites the last setting.
AnnaBridge 189:f392fc9709a3 116 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
AnnaBridge 189:f392fc9709a3 117 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
AnnaBridge 189:f392fc9709a3 118 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
AnnaBridge 189:f392fc9709a3 119 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
AnnaBridge 189:f392fc9709a3 120 of another parameter update on the fly) */
AnnaBridge 189:f392fc9709a3 121
AnnaBridge 189:f392fc9709a3 122 uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
AnnaBridge 189:f392fc9709a3 123 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
AnnaBridge 189:f392fc9709a3 124 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
AnnaBridge 189:f392fc9709a3 125
AnnaBridge 189:f392fc9709a3 126 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
AnnaBridge 189:f392fc9709a3 127 Offset value must be a positive number.
AnnaBridge 189:f392fc9709a3 128 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
AnnaBridge 189:f392fc9709a3 129 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
AnnaBridge 189:f392fc9709a3 130 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
AnnaBridge 189:f392fc9709a3 131 without continuous mode or external trigger that could launch a conversion). */
AnnaBridge 189:f392fc9709a3 132
AnnaBridge 189:f392fc9709a3 133 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
AnnaBridge 189:f392fc9709a3 134 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
AnnaBridge 189:f392fc9709a3 135 This parameter must be a number between Min_Data = 1 and Max_Data = 4.
AnnaBridge 189:f392fc9709a3 136 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
AnnaBridge 189:f392fc9709a3 137 configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge 189:f392fc9709a3 138
AnnaBridge 189:f392fc9709a3 139 uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
AnnaBridge 189:f392fc9709a3 140 (main sequence subdivided in successive parts).
AnnaBridge 189:f392fc9709a3 141 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
AnnaBridge 189:f392fc9709a3 142 Discontinuous mode can be enabled only if continuous mode is disabled.
AnnaBridge 189:f392fc9709a3 143 This parameter can be set to ENABLE or DISABLE.
AnnaBridge 189:f392fc9709a3 144 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
AnnaBridge 189:f392fc9709a3 145 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
AnnaBridge 189:f392fc9709a3 146 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
AnnaBridge 189:f392fc9709a3 147 configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge 189:f392fc9709a3 148
AnnaBridge 189:f392fc9709a3 149 uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
AnnaBridge 189:f392fc9709a3 150 This parameter can be set to ENABLE or DISABLE.
AnnaBridge 189:f392fc9709a3 151 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
AnnaBridge 189:f392fc9709a3 152 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
AnnaBridge 189:f392fc9709a3 153 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
AnnaBridge 189:f392fc9709a3 154 To maintain JAUTO always enabled, DMA must be configured in circular mode.
AnnaBridge 189:f392fc9709a3 155 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
AnnaBridge 189:f392fc9709a3 156 configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge 189:f392fc9709a3 157
AnnaBridge 189:f392fc9709a3 158 uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
AnnaBridge 189:f392fc9709a3 159 This parameter can be set to ENABLE or DISABLE.
AnnaBridge 189:f392fc9709a3 160 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
AnnaBridge 189:f392fc9709a3 161 new injected context is set when queue is full, error is triggered by interruption and through function
AnnaBridge 189:f392fc9709a3 162 'HAL_ADCEx_InjectedQueueOverflowCallback'.
AnnaBridge 189:f392fc9709a3 163 Caution: This feature request that the sequence is fully configured before injected conversion start.
AnnaBridge 189:f392fc9709a3 164 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
AnnaBridge 189:f392fc9709a3 165 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
AnnaBridge 189:f392fc9709a3 166 configure a channel on injected group can impact the configuration of other channels previously set.
AnnaBridge 189:f392fc9709a3 167 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
AnnaBridge 189:f392fc9709a3 168
AnnaBridge 189:f392fc9709a3 169 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
AnnaBridge 189:f392fc9709a3 170 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
AnnaBridge 189:f392fc9709a3 171 This parameter can be a value of @ref ADC_injected_external_trigger_source.
AnnaBridge 189:f392fc9709a3 172 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
AnnaBridge 189:f392fc9709a3 173 configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge 189:f392fc9709a3 174
AnnaBridge 189:f392fc9709a3 175 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
AnnaBridge 189:f392fc9709a3 176 This parameter can be a value of @ref ADC_injected_external_trigger_edge.
AnnaBridge 189:f392fc9709a3 177 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
AnnaBridge 189:f392fc9709a3 178 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
AnnaBridge 189:f392fc9709a3 179 configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge 189:f392fc9709a3 180
AnnaBridge 189:f392fc9709a3 181 uint32_t InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
AnnaBridge 189:f392fc9709a3 182 This parameter can be set to ENABLE or DISABLE.
AnnaBridge 189:f392fc9709a3 183 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
AnnaBridge 189:f392fc9709a3 184
AnnaBridge 189:f392fc9709a3 185 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
AnnaBridge 189:f392fc9709a3 186 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
AnnaBridge 189:f392fc9709a3 187 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
AnnaBridge 189:f392fc9709a3 188 }ADC_InjectionConfTypeDef;
AnnaBridge 189:f392fc9709a3 189
AnnaBridge 189:f392fc9709a3 190 #if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge 189:f392fc9709a3 191 /**
AnnaBridge 189:f392fc9709a3 192 * @brief Structure definition of ADC multimode
AnnaBridge 189:f392fc9709a3 193 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
AnnaBridge 189:f392fc9709a3 194 * Both Master and Slave ADCs must be disabled.
AnnaBridge 189:f392fc9709a3 195 */
AnnaBridge 189:f392fc9709a3 196 typedef struct
AnnaBridge 189:f392fc9709a3 197 {
AnnaBridge 189:f392fc9709a3 198 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode.
AnnaBridge 189:f392fc9709a3 199 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
AnnaBridge 189:f392fc9709a3 200
AnnaBridge 189:f392fc9709a3 201 uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC:
AnnaBridge 189:f392fc9709a3 202 selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
AnnaBridge 189:f392fc9709a3 203 This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */
AnnaBridge 189:f392fc9709a3 204
AnnaBridge 189:f392fc9709a3 205 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
AnnaBridge 189:f392fc9709a3 206 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.
AnnaBridge 189:f392fc9709a3 207 Delay range depends on selected resolution:
AnnaBridge 189:f392fc9709a3 208 from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
AnnaBridge 189:f392fc9709a3 209 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */
AnnaBridge 189:f392fc9709a3 210 }ADC_MultiModeTypeDef;
AnnaBridge 189:f392fc9709a3 211 #endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge 189:f392fc9709a3 212
AnnaBridge 189:f392fc9709a3 213 /**
AnnaBridge 189:f392fc9709a3 214 * @}
AnnaBridge 189:f392fc9709a3 215 */
AnnaBridge 189:f392fc9709a3 216
AnnaBridge 189:f392fc9709a3 217 /* Exported constants --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 218
AnnaBridge 189:f392fc9709a3 219 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
AnnaBridge 189:f392fc9709a3 220 * @{
AnnaBridge 189:f392fc9709a3 221 */
AnnaBridge 189:f392fc9709a3 222
AnnaBridge 189:f392fc9709a3 223 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
AnnaBridge 189:f392fc9709a3 224 * @{
AnnaBridge 189:f392fc9709a3 225 */
AnnaBridge 189:f392fc9709a3 226 /* ADC group regular trigger sources for all ADC instances */
AnnaBridge 189:f392fc9709a3 227 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */
AnnaBridge 189:f392fc9709a3 228 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 229 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 230 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 231 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 232 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 233 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 234 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 235 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 236 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 237 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 238 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 239 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 240 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 241 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 242 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 243 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
AnnaBridge 189:f392fc9709a3 244 /**
AnnaBridge 189:f392fc9709a3 245 * @}
AnnaBridge 189:f392fc9709a3 246 */
AnnaBridge 189:f392fc9709a3 247
AnnaBridge 189:f392fc9709a3 248 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
AnnaBridge 189:f392fc9709a3 249 * @{
AnnaBridge 189:f392fc9709a3 250 */
AnnaBridge 189:f392fc9709a3 251 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) /*!< Injected conversions hardware trigger detection disabled */
AnnaBridge 189:f392fc9709a3 252 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */
AnnaBridge 189:f392fc9709a3 253 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */
AnnaBridge 189:f392fc9709a3 254 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
AnnaBridge 189:f392fc9709a3 255 /**
AnnaBridge 189:f392fc9709a3 256 * @}
AnnaBridge 189:f392fc9709a3 257 */
AnnaBridge 189:f392fc9709a3 258
AnnaBridge 189:f392fc9709a3 259 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
AnnaBridge 189:f392fc9709a3 260 * @{
AnnaBridge 189:f392fc9709a3 261 */
AnnaBridge 189:f392fc9709a3 262 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
AnnaBridge 189:f392fc9709a3 263 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
AnnaBridge 189:f392fc9709a3 264 /**
AnnaBridge 189:f392fc9709a3 265 * @}
AnnaBridge 189:f392fc9709a3 266 */
AnnaBridge 189:f392fc9709a3 267
AnnaBridge 189:f392fc9709a3 268 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
AnnaBridge 189:f392fc9709a3 269 * @{
AnnaBridge 189:f392fc9709a3 270 */
AnnaBridge 189:f392fc9709a3 271 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */
AnnaBridge 189:f392fc9709a3 272 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
AnnaBridge 189:f392fc9709a3 273 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
AnnaBridge 189:f392fc9709a3 274 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
AnnaBridge 189:f392fc9709a3 275 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
AnnaBridge 189:f392fc9709a3 276 /**
AnnaBridge 189:f392fc9709a3 277 * @}
AnnaBridge 189:f392fc9709a3 278 */
AnnaBridge 189:f392fc9709a3 279
AnnaBridge 189:f392fc9709a3 280 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
AnnaBridge 189:f392fc9709a3 281 * @{
AnnaBridge 189:f392fc9709a3 282 */
AnnaBridge 189:f392fc9709a3 283 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
AnnaBridge 189:f392fc9709a3 284 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
AnnaBridge 189:f392fc9709a3 285 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
AnnaBridge 189:f392fc9709a3 286 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
AnnaBridge 189:f392fc9709a3 287 /**
AnnaBridge 189:f392fc9709a3 288 * @}
AnnaBridge 189:f392fc9709a3 289 */
AnnaBridge 189:f392fc9709a3 290
AnnaBridge 189:f392fc9709a3 291 #if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge 189:f392fc9709a3 292 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode
AnnaBridge 189:f392fc9709a3 293 * @{
AnnaBridge 189:f392fc9709a3 294 */
AnnaBridge 189:f392fc9709a3 295 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */
AnnaBridge 189:f392fc9709a3 296 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */
AnnaBridge 189:f392fc9709a3 297 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */
AnnaBridge 189:f392fc9709a3 298 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */
AnnaBridge 189:f392fc9709a3 299 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
AnnaBridge 189:f392fc9709a3 300 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
AnnaBridge 189:f392fc9709a3 301 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
AnnaBridge 189:f392fc9709a3 302 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
AnnaBridge 189:f392fc9709a3 303
AnnaBridge 189:f392fc9709a3 304 /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution
AnnaBridge 189:f392fc9709a3 305 * @{
AnnaBridge 189:f392fc9709a3 306 */
AnnaBridge 189:f392fc9709a3 307 #define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /*!< DMA multimode disabled: each ADC uses its own DMA channel */
AnnaBridge 189:f392fc9709a3 308 #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
AnnaBridge 189:f392fc9709a3 309 #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
AnnaBridge 189:f392fc9709a3 310 /**
AnnaBridge 189:f392fc9709a3 311 * @}
AnnaBridge 189:f392fc9709a3 312 */
AnnaBridge 189:f392fc9709a3 313
AnnaBridge 189:f392fc9709a3 314 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
AnnaBridge 189:f392fc9709a3 315 * @{
AnnaBridge 189:f392fc9709a3 316 */
AnnaBridge 189:f392fc9709a3 317 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
AnnaBridge 189:f392fc9709a3 318 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
AnnaBridge 189:f392fc9709a3 319 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
AnnaBridge 189:f392fc9709a3 320 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
AnnaBridge 189:f392fc9709a3 321 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
AnnaBridge 189:f392fc9709a3 322 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
AnnaBridge 189:f392fc9709a3 323 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
AnnaBridge 189:f392fc9709a3 324 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
AnnaBridge 189:f392fc9709a3 325 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
AnnaBridge 189:f392fc9709a3 326 #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
AnnaBridge 189:f392fc9709a3 327 #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
AnnaBridge 189:f392fc9709a3 328 #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
AnnaBridge 189:f392fc9709a3 329 /**
AnnaBridge 189:f392fc9709a3 330 * @}
AnnaBridge 189:f392fc9709a3 331 */
AnnaBridge 189:f392fc9709a3 332
AnnaBridge 189:f392fc9709a3 333 /**
AnnaBridge 189:f392fc9709a3 334 * @}
AnnaBridge 189:f392fc9709a3 335 */
AnnaBridge 189:f392fc9709a3 336 #endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge 189:f392fc9709a3 337
AnnaBridge 189:f392fc9709a3 338 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
AnnaBridge 189:f392fc9709a3 339 * @{
AnnaBridge 189:f392fc9709a3 340 */
AnnaBridge 189:f392fc9709a3 341 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
AnnaBridge 189:f392fc9709a3 342 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/
AnnaBridge 189:f392fc9709a3 343 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
AnnaBridge 189:f392fc9709a3 344 /**
AnnaBridge 189:f392fc9709a3 345 * @}
AnnaBridge 189:f392fc9709a3 346 */
AnnaBridge 189:f392fc9709a3 347
AnnaBridge 189:f392fc9709a3 348 /** @defgroup ADC_CFGR_fields ADCx CFGR fields
AnnaBridge 189:f392fc9709a3 349 * @{
AnnaBridge 189:f392fc9709a3 350 */
AnnaBridge 189:f392fc9709a3 351 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
AnnaBridge 189:f392fc9709a3 352 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\
AnnaBridge 189:f392fc9709a3 353 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\
AnnaBridge 189:f392fc9709a3 354 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\
AnnaBridge 189:f392fc9709a3 355 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
AnnaBridge 189:f392fc9709a3 356 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
AnnaBridge 189:f392fc9709a3 357 ADC_CFGR_RES | ADC_CFGR_DFSDMCFG | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)
AnnaBridge 189:f392fc9709a3 358 #else
AnnaBridge 189:f392fc9709a3 359 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\
AnnaBridge 189:f392fc9709a3 360 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\
AnnaBridge 189:f392fc9709a3 361 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\
AnnaBridge 189:f392fc9709a3 362 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
AnnaBridge 189:f392fc9709a3 363 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
AnnaBridge 189:f392fc9709a3 364 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
AnnaBridge 189:f392fc9709a3 365 #endif
AnnaBridge 189:f392fc9709a3 366 /**
AnnaBridge 189:f392fc9709a3 367 * @}
AnnaBridge 189:f392fc9709a3 368 */
AnnaBridge 189:f392fc9709a3 369
AnnaBridge 189:f392fc9709a3 370 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
AnnaBridge 189:f392fc9709a3 371 * @{
AnnaBridge 189:f392fc9709a3 372 */
AnnaBridge 189:f392fc9709a3 373 #if defined(ADC_SMPR1_SMPPLUS)
AnnaBridge 189:f392fc9709a3 374 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
AnnaBridge 189:f392fc9709a3 375 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
AnnaBridge 189:f392fc9709a3 376 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
AnnaBridge 189:f392fc9709a3 377 ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS)
AnnaBridge 189:f392fc9709a3 378 #else
AnnaBridge 189:f392fc9709a3 379 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
AnnaBridge 189:f392fc9709a3 380 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
AnnaBridge 189:f392fc9709a3 381 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
AnnaBridge 189:f392fc9709a3 382 ADC_SMPR1_SMP0)
AnnaBridge 189:f392fc9709a3 383 #endif
AnnaBridge 189:f392fc9709a3 384 /**
AnnaBridge 189:f392fc9709a3 385 * @}
AnnaBridge 189:f392fc9709a3 386 */
AnnaBridge 189:f392fc9709a3 387
AnnaBridge 189:f392fc9709a3 388 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
AnnaBridge 189:f392fc9709a3 389 * @{
AnnaBridge 189:f392fc9709a3 390 */
AnnaBridge 189:f392fc9709a3 391 /* ADC_CFGR fields of parameters that can be updated when no conversion
AnnaBridge 189:f392fc9709a3 392 (neither regular nor injected) is on-going */
AnnaBridge 189:f392fc9709a3 393 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
AnnaBridge 189:f392fc9709a3 394 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG))
AnnaBridge 189:f392fc9709a3 395 #else
AnnaBridge 189:f392fc9709a3 396 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
AnnaBridge 189:f392fc9709a3 397 #endif
AnnaBridge 189:f392fc9709a3 398 /**
AnnaBridge 189:f392fc9709a3 399 * @}
AnnaBridge 189:f392fc9709a3 400 */
AnnaBridge 189:f392fc9709a3 401
AnnaBridge 189:f392fc9709a3 402 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
AnnaBridge 189:f392fc9709a3 403 /** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
AnnaBridge 189:f392fc9709a3 404 * @{
AnnaBridge 189:f392fc9709a3 405 */
AnnaBridge 189:f392fc9709a3 406 #define ADC_DFSDM_MODE_DISABLE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */
AnnaBridge 189:f392fc9709a3 407 #define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
AnnaBridge 189:f392fc9709a3 408 /**
AnnaBridge 189:f392fc9709a3 409 * @}
AnnaBridge 189:f392fc9709a3 410 */
AnnaBridge 189:f392fc9709a3 411 #endif
AnnaBridge 189:f392fc9709a3 412
AnnaBridge 189:f392fc9709a3 413 /**
AnnaBridge 189:f392fc9709a3 414 * @}
AnnaBridge 189:f392fc9709a3 415 */
AnnaBridge 189:f392fc9709a3 416
AnnaBridge 189:f392fc9709a3 417 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 418
AnnaBridge 189:f392fc9709a3 419 #if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge 189:f392fc9709a3 420 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
AnnaBridge 189:f392fc9709a3 421 * @{
AnnaBridge 189:f392fc9709a3 422 */
AnnaBridge 189:f392fc9709a3 423
AnnaBridge 189:f392fc9709a3 424 /** @brief Force ADC instance in multimode mode independant (multimode disable).
AnnaBridge 189:f392fc9709a3 425 * @note This macro must be used only in case of transition from multimode
AnnaBridge 189:f392fc9709a3 426 * to mode independent and in case of unknown previous state,
AnnaBridge 189:f392fc9709a3 427 * to ensure ADC configuration is in mode independent.
AnnaBridge 189:f392fc9709a3 428 * @note Standard way of multimode configuration change is done from
AnnaBridge 189:f392fc9709a3 429 * HAL ADC handle of ADC master using function
AnnaBridge 189:f392fc9709a3 430 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
AnnaBridge 189:f392fc9709a3 431 * Usage of this macro is not the Standard way of multimode
AnnaBridge 189:f392fc9709a3 432 * configuration and can lead to have HAL ADC handles status
AnnaBridge 189:f392fc9709a3 433 * misaligned. Usage of this macro must be limited to cases
AnnaBridge 189:f392fc9709a3 434 * mentionned above.
AnnaBridge 189:f392fc9709a3 435 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 436 * @retval None
AnnaBridge 189:f392fc9709a3 437 */
AnnaBridge 189:f392fc9709a3 438 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 439 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
AnnaBridge 189:f392fc9709a3 440
AnnaBridge 189:f392fc9709a3 441 /**
AnnaBridge 189:f392fc9709a3 442 * @}
AnnaBridge 189:f392fc9709a3 443 */
AnnaBridge 189:f392fc9709a3 444 #endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge 189:f392fc9709a3 445
AnnaBridge 189:f392fc9709a3 446 /* Private macros ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 447
AnnaBridge 189:f392fc9709a3 448 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
AnnaBridge 189:f392fc9709a3 449 * @{
AnnaBridge 189:f392fc9709a3 450 */
AnnaBridge 189:f392fc9709a3 451 /* Macro reserved for internal HAL driver usage, not intended to be used in */
AnnaBridge 189:f392fc9709a3 452 /* code of final user. */
AnnaBridge 189:f392fc9709a3 453
AnnaBridge 189:f392fc9709a3 454 /**
AnnaBridge 189:f392fc9709a3 455 * @brief Test if conversion trigger of injected group is software start
AnnaBridge 189:f392fc9709a3 456 * or external trigger.
AnnaBridge 189:f392fc9709a3 457 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 458 * @retval SET (software start) or RESET (external trigger).
AnnaBridge 189:f392fc9709a3 459 */
AnnaBridge 189:f392fc9709a3 460 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 461 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
AnnaBridge 189:f392fc9709a3 462
AnnaBridge 189:f392fc9709a3 463 /**
AnnaBridge 189:f392fc9709a3 464 * @brief Check if conversion is on going on regular or injected groups.
AnnaBridge 189:f392fc9709a3 465 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 466 * @retval SET (conversion is on going) or RESET (no conversion is on going).
AnnaBridge 189:f392fc9709a3 467 */
AnnaBridge 189:f392fc9709a3 468 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 469 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \
AnnaBridge 189:f392fc9709a3 470 ) ? RESET : SET)
AnnaBridge 189:f392fc9709a3 471
AnnaBridge 189:f392fc9709a3 472 /**
AnnaBridge 189:f392fc9709a3 473 * @brief Check if conversion is on going on injected group.
AnnaBridge 189:f392fc9709a3 474 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 475 * @retval SET (conversion is on going) or RESET (no conversion is on going).
AnnaBridge 189:f392fc9709a3 476 */
AnnaBridge 189:f392fc9709a3 477 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 478 (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))
AnnaBridge 189:f392fc9709a3 479
AnnaBridge 189:f392fc9709a3 480 /**
AnnaBridge 189:f392fc9709a3 481 * @brief Check whether or not ADC is independent.
AnnaBridge 189:f392fc9709a3 482 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 483 * @note When multimode feature is not available, the macro always returns SET.
AnnaBridge 189:f392fc9709a3 484 * @retval SET (ADC is independent) or RESET (ADC is not).
AnnaBridge 189:f392fc9709a3 485 */
AnnaBridge 189:f392fc9709a3 486 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 189:f392fc9709a3 487 #define ADC_IS_INDEPENDENT(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 488 ( ( ( ((__HANDLE__)->Instance) == ADC3) \
AnnaBridge 189:f392fc9709a3 489 )? \
AnnaBridge 189:f392fc9709a3 490 SET \
AnnaBridge 189:f392fc9709a3 491 : \
AnnaBridge 189:f392fc9709a3 492 RESET \
AnnaBridge 189:f392fc9709a3 493 )
AnnaBridge 189:f392fc9709a3 494 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
AnnaBridge 189:f392fc9709a3 495 #define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
AnnaBridge 189:f392fc9709a3 496 #endif
AnnaBridge 189:f392fc9709a3 497
AnnaBridge 189:f392fc9709a3 498 /**
AnnaBridge 189:f392fc9709a3 499 * @brief Set the selected injected Channel rank.
AnnaBridge 189:f392fc9709a3 500 * @param __CHANNELNB__ Channel number.
AnnaBridge 189:f392fc9709a3 501 * @param __RANKNB__ Rank number.
AnnaBridge 189:f392fc9709a3 502 * @retval None
AnnaBridge 189:f392fc9709a3 503 */
AnnaBridge 189:f392fc9709a3 504 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
AnnaBridge 189:f392fc9709a3 505
AnnaBridge 189:f392fc9709a3 506 /**
AnnaBridge 189:f392fc9709a3 507 * @brief Configure ADC injected context queue
AnnaBridge 189:f392fc9709a3 508 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
AnnaBridge 189:f392fc9709a3 509 * @retval None
AnnaBridge 189:f392fc9709a3 510 */
AnnaBridge 189:f392fc9709a3 511 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
AnnaBridge 189:f392fc9709a3 512
AnnaBridge 189:f392fc9709a3 513 /**
AnnaBridge 189:f392fc9709a3 514 * @brief Configure ADC discontinuous conversion mode for injected group
AnnaBridge 189:f392fc9709a3 515 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
AnnaBridge 189:f392fc9709a3 516 * @retval None
AnnaBridge 189:f392fc9709a3 517 */
AnnaBridge 189:f392fc9709a3 518 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
AnnaBridge 189:f392fc9709a3 519
AnnaBridge 189:f392fc9709a3 520 /**
AnnaBridge 189:f392fc9709a3 521 * @brief Configure ADC discontinuous conversion mode for regular group
AnnaBridge 189:f392fc9709a3 522 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
AnnaBridge 189:f392fc9709a3 523 * @retval None
AnnaBridge 189:f392fc9709a3 524 */
AnnaBridge 189:f392fc9709a3 525 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
AnnaBridge 189:f392fc9709a3 526
AnnaBridge 189:f392fc9709a3 527 /**
AnnaBridge 189:f392fc9709a3 528 * @brief Configure the number of discontinuous conversions for regular group.
AnnaBridge 189:f392fc9709a3 529 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
AnnaBridge 189:f392fc9709a3 530 * @retval None
AnnaBridge 189:f392fc9709a3 531 */
AnnaBridge 189:f392fc9709a3 532 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << ADC_CFGR_DISCNUM_Pos)
AnnaBridge 189:f392fc9709a3 533
AnnaBridge 189:f392fc9709a3 534 /**
AnnaBridge 189:f392fc9709a3 535 * @brief Configure the ADC auto delay mode.
AnnaBridge 189:f392fc9709a3 536 * @param __AUTOWAIT__ Auto delay bit enable or disable.
AnnaBridge 189:f392fc9709a3 537 * @retval None
AnnaBridge 189:f392fc9709a3 538 */
AnnaBridge 189:f392fc9709a3 539 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
AnnaBridge 189:f392fc9709a3 540
AnnaBridge 189:f392fc9709a3 541 /**
AnnaBridge 189:f392fc9709a3 542 * @brief Configure ADC continuous conversion mode.
AnnaBridge 189:f392fc9709a3 543 * @param __CONTINUOUS_MODE__ Continuous mode.
AnnaBridge 189:f392fc9709a3 544 * @retval None
AnnaBridge 189:f392fc9709a3 545 */
AnnaBridge 189:f392fc9709a3 546 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
AnnaBridge 189:f392fc9709a3 547
AnnaBridge 189:f392fc9709a3 548 /**
AnnaBridge 189:f392fc9709a3 549 * @brief Configure the ADC DMA continuous request.
AnnaBridge 189:f392fc9709a3 550 * @param __DMACONTREQ_MODE__ DMA continuous request mode.
AnnaBridge 189:f392fc9709a3 551 * @retval None
AnnaBridge 189:f392fc9709a3 552 */
AnnaBridge 189:f392fc9709a3 553 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)
AnnaBridge 189:f392fc9709a3 554
AnnaBridge 189:f392fc9709a3 555 /**
AnnaBridge 189:f392fc9709a3 556 * @brief Configure the channel number into offset OFRx register.
AnnaBridge 189:f392fc9709a3 557 * @param __CHANNEL__ ADC Channel.
AnnaBridge 189:f392fc9709a3 558 * @retval None
AnnaBridge 189:f392fc9709a3 559 */
AnnaBridge 189:f392fc9709a3 560 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)
AnnaBridge 189:f392fc9709a3 561
AnnaBridge 189:f392fc9709a3 562 /**
AnnaBridge 189:f392fc9709a3 563 * @brief Configure the channel number into differential mode selection register.
AnnaBridge 189:f392fc9709a3 564 * @param __CHANNEL__ ADC Channel.
AnnaBridge 189:f392fc9709a3 565 * @retval None
AnnaBridge 189:f392fc9709a3 566 */
AnnaBridge 189:f392fc9709a3 567 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__))
AnnaBridge 189:f392fc9709a3 568
AnnaBridge 189:f392fc9709a3 569 /**
AnnaBridge 189:f392fc9709a3 570 * @brief Configure calibration factor in differential mode to be set into calibration register.
AnnaBridge 189:f392fc9709a3 571 * @param __CALIBRATION_FACTOR__ Calibration factor value.
AnnaBridge 189:f392fc9709a3 572 * @retval None
AnnaBridge 189:f392fc9709a3 573 */
AnnaBridge 189:f392fc9709a3 574 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
AnnaBridge 189:f392fc9709a3 575
AnnaBridge 189:f392fc9709a3 576 /**
AnnaBridge 189:f392fc9709a3 577 * @brief Calibration factor in differential mode to be retrieved from calibration register.
AnnaBridge 189:f392fc9709a3 578 * @param __CALIBRATION_FACTOR__ Calibration factor value.
AnnaBridge 189:f392fc9709a3 579 * @retval None
AnnaBridge 189:f392fc9709a3 580 */
AnnaBridge 189:f392fc9709a3 581 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)
AnnaBridge 189:f392fc9709a3 582
AnnaBridge 189:f392fc9709a3 583 /**
AnnaBridge 189:f392fc9709a3 584 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
AnnaBridge 189:f392fc9709a3 585 * @param __THRESHOLD__ Threshold value.
AnnaBridge 189:f392fc9709a3 586 * @retval None
AnnaBridge 189:f392fc9709a3 587 */
AnnaBridge 189:f392fc9709a3 588 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
AnnaBridge 189:f392fc9709a3 589
AnnaBridge 189:f392fc9709a3 590 #if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge 189:f392fc9709a3 591 /**
AnnaBridge 189:f392fc9709a3 592 * @brief Configure the ADC DMA continuous request for ADC multimode.
AnnaBridge 189:f392fc9709a3 593 * @param __DMACONTREQ_MODE__ DMA continuous request mode.
AnnaBridge 189:f392fc9709a3 594 * @retval None
AnnaBridge 189:f392fc9709a3 595 */
AnnaBridge 189:f392fc9709a3 596 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
AnnaBridge 189:f392fc9709a3 597 #endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge 189:f392fc9709a3 598 /**
AnnaBridge 189:f392fc9709a3 599 * @brief Enable the ADC peripheral.
AnnaBridge 189:f392fc9709a3 600 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 601 * @retval None
AnnaBridge 189:f392fc9709a3 602 */
AnnaBridge 189:f392fc9709a3 603 #define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
AnnaBridge 189:f392fc9709a3 604
AnnaBridge 189:f392fc9709a3 605 /**
AnnaBridge 189:f392fc9709a3 606 * @brief Verification of hardware constraints before ADC can be enabled.
AnnaBridge 189:f392fc9709a3 607 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 608 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
AnnaBridge 189:f392fc9709a3 609 */
AnnaBridge 189:f392fc9709a3 610 #define ADC_ENABLING_CONDITIONS(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 611 (( ( ((__HANDLE__)->Instance->CR) & \
AnnaBridge 189:f392fc9709a3 612 (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | \
AnnaBridge 189:f392fc9709a3 613 ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \
AnnaBridge 189:f392fc9709a3 614 ) == RESET \
AnnaBridge 189:f392fc9709a3 615 ) ? SET : RESET)
AnnaBridge 189:f392fc9709a3 616
AnnaBridge 189:f392fc9709a3 617 /**
AnnaBridge 189:f392fc9709a3 618 * @brief Disable the ADC peripheral.
AnnaBridge 189:f392fc9709a3 619 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 620 * @retval None
AnnaBridge 189:f392fc9709a3 621 */
AnnaBridge 189:f392fc9709a3 622 #define ADC_DISABLE(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 623 do{ \
AnnaBridge 189:f392fc9709a3 624 (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \
AnnaBridge 189:f392fc9709a3 625 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
AnnaBridge 189:f392fc9709a3 626 } while(0)
AnnaBridge 189:f392fc9709a3 627
AnnaBridge 189:f392fc9709a3 628 /**
AnnaBridge 189:f392fc9709a3 629 * @brief Verification of hardware constraints before ADC can be disabled.
AnnaBridge 189:f392fc9709a3 630 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 631 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
AnnaBridge 189:f392fc9709a3 632 */
AnnaBridge 189:f392fc9709a3 633 #define ADC_DISABLING_CONDITIONS(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 634 (( ( ((__HANDLE__)->Instance->CR) & \
AnnaBridge 189:f392fc9709a3 635 (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
AnnaBridge 189:f392fc9709a3 636 ) ? SET : RESET)
AnnaBridge 189:f392fc9709a3 637
AnnaBridge 189:f392fc9709a3 638 /**
AnnaBridge 189:f392fc9709a3 639 * @brief Shift the offset with respect to the selected ADC resolution.
AnnaBridge 189:f392fc9709a3 640 * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
AnnaBridge 189:f392fc9709a3 641 * If resolution 12 bits, no shift.
AnnaBridge 189:f392fc9709a3 642 * If resolution 10 bits, shift of 2 ranks on the left.
AnnaBridge 189:f392fc9709a3 643 * If resolution 8 bits, shift of 4 ranks on the left.
AnnaBridge 189:f392fc9709a3 644 * If resolution 6 bits, shift of 6 ranks on the left.
AnnaBridge 189:f392fc9709a3 645 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
AnnaBridge 189:f392fc9709a3 646 * @param __HANDLE__ ADC handle
AnnaBridge 189:f392fc9709a3 647 * @param __OFFSET__ Value to be shifted
AnnaBridge 189:f392fc9709a3 648 * @retval None
AnnaBridge 189:f392fc9709a3 649 */
AnnaBridge 189:f392fc9709a3 650 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
AnnaBridge 189:f392fc9709a3 651 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
AnnaBridge 189:f392fc9709a3 652
AnnaBridge 189:f392fc9709a3 653
AnnaBridge 189:f392fc9709a3 654 /**
AnnaBridge 189:f392fc9709a3 655 * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
AnnaBridge 189:f392fc9709a3 656 * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
AnnaBridge 189:f392fc9709a3 657 * If resolution 12 bits, no shift.
AnnaBridge 189:f392fc9709a3 658 * If resolution 10 bits, shift of 2 ranks on the left.
AnnaBridge 189:f392fc9709a3 659 * If resolution 8 bits, shift of 4 ranks on the left.
AnnaBridge 189:f392fc9709a3 660 * If resolution 6 bits, shift of 6 ranks on the left.
AnnaBridge 189:f392fc9709a3 661 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
AnnaBridge 189:f392fc9709a3 662 * @param __HANDLE__ ADC handle
AnnaBridge 189:f392fc9709a3 663 * @param __THRESHOLD__ Value to be shifted
AnnaBridge 189:f392fc9709a3 664 * @retval None
AnnaBridge 189:f392fc9709a3 665 */
AnnaBridge 189:f392fc9709a3 666 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
AnnaBridge 189:f392fc9709a3 667 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
AnnaBridge 189:f392fc9709a3 668
AnnaBridge 189:f392fc9709a3 669 /**
AnnaBridge 189:f392fc9709a3 670 * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
AnnaBridge 189:f392fc9709a3 671 * @note Thresholds have to be left-aligned on bit 7.
AnnaBridge 189:f392fc9709a3 672 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
AnnaBridge 189:f392fc9709a3 673 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
AnnaBridge 189:f392fc9709a3 674 * If resolution 8 bits, no shift.
AnnaBridge 189:f392fc9709a3 675 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
AnnaBridge 189:f392fc9709a3 676 * @param __HANDLE__ ADC handle
AnnaBridge 189:f392fc9709a3 677 * @param __THRESHOLD__ Value to be shifted
AnnaBridge 189:f392fc9709a3 678 * @retval None
AnnaBridge 189:f392fc9709a3 679 */
AnnaBridge 189:f392fc9709a3 680 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
AnnaBridge 189:f392fc9709a3 681 ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \
AnnaBridge 189:f392fc9709a3 682 ((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
AnnaBridge 189:f392fc9709a3 683 (__THRESHOLD__) << 2 )
AnnaBridge 189:f392fc9709a3 684
AnnaBridge 189:f392fc9709a3 685 /**
AnnaBridge 189:f392fc9709a3 686 * @brief Report Master Instance.
AnnaBridge 189:f392fc9709a3 687 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 688 * @note Return same instance if ADC of input handle is independent ADC or if
AnnaBridge 189:f392fc9709a3 689 * multimode feature is not available.
AnnaBridge 189:f392fc9709a3 690 * @retval Master Instance
AnnaBridge 189:f392fc9709a3 691 */
AnnaBridge 189:f392fc9709a3 692 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 189:f392fc9709a3 693 #define ADC_MASTER_REGISTER(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 694 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
AnnaBridge 189:f392fc9709a3 695 )? \
AnnaBridge 189:f392fc9709a3 696 ((__HANDLE__)->Instance) \
AnnaBridge 189:f392fc9709a3 697 : \
AnnaBridge 189:f392fc9709a3 698 (ADC1) \
AnnaBridge 189:f392fc9709a3 699 )
AnnaBridge 189:f392fc9709a3 700 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
AnnaBridge 189:f392fc9709a3 701 #define ADC_MASTER_REGISTER(__HANDLE__) ((__HANDLE__)->Instance)
AnnaBridge 189:f392fc9709a3 702 #endif
AnnaBridge 189:f392fc9709a3 703
AnnaBridge 189:f392fc9709a3 704 /**
AnnaBridge 189:f392fc9709a3 705 * @brief Clear Common Control Register.
AnnaBridge 189:f392fc9709a3 706 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 707 * @retval None
AnnaBridge 189:f392fc9709a3 708 */
AnnaBridge 189:f392fc9709a3 709 #if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge 189:f392fc9709a3 710 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
AnnaBridge 189:f392fc9709a3 711 ADC_CCR_PRESC | \
AnnaBridge 189:f392fc9709a3 712 ADC_CCR_VBATEN | \
AnnaBridge 189:f392fc9709a3 713 ADC_CCR_TSEN | \
AnnaBridge 189:f392fc9709a3 714 ADC_CCR_VREFEN | \
AnnaBridge 189:f392fc9709a3 715 ADC_CCR_MDMA | \
AnnaBridge 189:f392fc9709a3 716 ADC_CCR_DMACFG | \
AnnaBridge 189:f392fc9709a3 717 ADC_CCR_DELAY | \
AnnaBridge 189:f392fc9709a3 718 ADC_CCR_DUAL )
AnnaBridge 189:f392fc9709a3 719 #else
AnnaBridge 189:f392fc9709a3 720 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
AnnaBridge 189:f392fc9709a3 721 ADC_CCR_PRESC | \
AnnaBridge 189:f392fc9709a3 722 ADC_CCR_VBATEN | \
AnnaBridge 189:f392fc9709a3 723 ADC_CCR_TSEN | \
AnnaBridge 189:f392fc9709a3 724 ADC_CCR_VREFEN )
AnnaBridge 189:f392fc9709a3 725
AnnaBridge 189:f392fc9709a3 726 #endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge 189:f392fc9709a3 727
AnnaBridge 189:f392fc9709a3 728 /**
AnnaBridge 189:f392fc9709a3 729 * @brief Check whether or not dual conversions are enabled.
AnnaBridge 189:f392fc9709a3 730 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 731 * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.
AnnaBridge 189:f392fc9709a3 732 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
AnnaBridge 189:f392fc9709a3 733 */
AnnaBridge 189:f392fc9709a3 734 #if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge 189:f392fc9709a3 735 #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 736 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
AnnaBridge 189:f392fc9709a3 737 )? \
AnnaBridge 189:f392fc9709a3 738 ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) ) \
AnnaBridge 189:f392fc9709a3 739 : \
AnnaBridge 189:f392fc9709a3 740 RESET \
AnnaBridge 189:f392fc9709a3 741 )
AnnaBridge 189:f392fc9709a3 742 #else
AnnaBridge 189:f392fc9709a3 743 #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) (RESET)
AnnaBridge 189:f392fc9709a3 744 #endif
AnnaBridge 189:f392fc9709a3 745
AnnaBridge 189:f392fc9709a3 746 /**
AnnaBridge 189:f392fc9709a3 747 * @brief Check whether or not dual regular conversions are enabled.
AnnaBridge 189:f392fc9709a3 748 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 749 * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.
AnnaBridge 189:f392fc9709a3 750 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
AnnaBridge 189:f392fc9709a3 751 */
AnnaBridge 189:f392fc9709a3 752 #if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge 189:f392fc9709a3 753 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 754 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
AnnaBridge 189:f392fc9709a3 755 )? \
AnnaBridge 189:f392fc9709a3 756 ( (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
AnnaBridge 189:f392fc9709a3 757 (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
AnnaBridge 189:f392fc9709a3 758 (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
AnnaBridge 189:f392fc9709a3 759 : \
AnnaBridge 189:f392fc9709a3 760 RESET \
AnnaBridge 189:f392fc9709a3 761 )
AnnaBridge 189:f392fc9709a3 762 #else
AnnaBridge 189:f392fc9709a3 763 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) (RESET)
AnnaBridge 189:f392fc9709a3 764 #endif
AnnaBridge 189:f392fc9709a3 765
AnnaBridge 189:f392fc9709a3 766 /**
AnnaBridge 189:f392fc9709a3 767 * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master.
AnnaBridge 189:f392fc9709a3 768 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 769 * @note Return SET if multimode feature is not available.
AnnaBridge 189:f392fc9709a3 770 * @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode)
AnnaBridge 189:f392fc9709a3 771 */
AnnaBridge 189:f392fc9709a3 772 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 189:f392fc9709a3 773 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 774 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
AnnaBridge 189:f392fc9709a3 775 )? \
AnnaBridge 189:f392fc9709a3 776 SET \
AnnaBridge 189:f392fc9709a3 777 : \
AnnaBridge 189:f392fc9709a3 778 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
AnnaBridge 189:f392fc9709a3 779 )
AnnaBridge 189:f392fc9709a3 780 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
AnnaBridge 189:f392fc9709a3 781 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (SET)
AnnaBridge 189:f392fc9709a3 782 #endif
AnnaBridge 189:f392fc9709a3 783
AnnaBridge 189:f392fc9709a3 784 /**
AnnaBridge 189:f392fc9709a3 785 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
AnnaBridge 189:f392fc9709a3 786 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 787 * @note Return SET if multimode feature is not available.
AnnaBridge 189:f392fc9709a3 788 * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
AnnaBridge 189:f392fc9709a3 789 */
AnnaBridge 189:f392fc9709a3 790 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 189:f392fc9709a3 791 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 792 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
AnnaBridge 189:f392fc9709a3 793 )? \
AnnaBridge 189:f392fc9709a3 794 SET \
AnnaBridge 189:f392fc9709a3 795 : \
AnnaBridge 189:f392fc9709a3 796 ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
AnnaBridge 189:f392fc9709a3 797 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
AnnaBridge 189:f392fc9709a3 798 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
AnnaBridge 189:f392fc9709a3 799 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined( STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
AnnaBridge 189:f392fc9709a3 800 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) (SET)
AnnaBridge 189:f392fc9709a3 801 #endif
AnnaBridge 189:f392fc9709a3 802
AnnaBridge 189:f392fc9709a3 803 /**
AnnaBridge 189:f392fc9709a3 804 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
AnnaBridge 189:f392fc9709a3 805 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 806 * @note Return SET if multimode feature is not available.
AnnaBridge 189:f392fc9709a3 807 * @retval SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
AnnaBridge 189:f392fc9709a3 808 */
AnnaBridge 189:f392fc9709a3 809 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 189:f392fc9709a3 810 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 811 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
AnnaBridge 189:f392fc9709a3 812 )? \
AnnaBridge 189:f392fc9709a3 813 SET \
AnnaBridge 189:f392fc9709a3 814 : \
AnnaBridge 189:f392fc9709a3 815 ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
AnnaBridge 189:f392fc9709a3 816 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
AnnaBridge 189:f392fc9709a3 817 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
AnnaBridge 189:f392fc9709a3 818 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
AnnaBridge 189:f392fc9709a3 819 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) (SET)
AnnaBridge 189:f392fc9709a3 820 #endif
AnnaBridge 189:f392fc9709a3 821
AnnaBridge 189:f392fc9709a3 822 /**
AnnaBridge 189:f392fc9709a3 823 * @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.
AnnaBridge 189:f392fc9709a3 824 * @param __INSTANCE__ ADC instance.
AnnaBridge 189:f392fc9709a3 825 * @retval SET (ADC enabled) or RESET (ADC disabled)
AnnaBridge 189:f392fc9709a3 826 */
AnnaBridge 189:f392fc9709a3 827 #define ADC_INSTANCE_IS_ENABLED(__INSTANCE__) \
AnnaBridge 189:f392fc9709a3 828 (( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
AnnaBridge 189:f392fc9709a3 829 ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
AnnaBridge 189:f392fc9709a3 830 ) ? SET : RESET)
AnnaBridge 189:f392fc9709a3 831
AnnaBridge 189:f392fc9709a3 832 /**
AnnaBridge 189:f392fc9709a3 833 * @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.
AnnaBridge 189:f392fc9709a3 834 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 835 * @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled)
AnnaBridge 189:f392fc9709a3 836 */
AnnaBridge 189:f392fc9709a3 837 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 189:f392fc9709a3 838 #define ADC_ANY_OTHER_ENABLED(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 839 ( ( ((__HANDLE__)->Instance == ADC1) \
AnnaBridge 189:f392fc9709a3 840 )? \
AnnaBridge 189:f392fc9709a3 841 (ADC_INSTANCE_IS_ENABLED(ADC2)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \
AnnaBridge 189:f392fc9709a3 842 : \
AnnaBridge 189:f392fc9709a3 843 ( ( ((__HANDLE__)->Instance == ADC2) \
AnnaBridge 189:f392fc9709a3 844 )? \
AnnaBridge 189:f392fc9709a3 845 (ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \
AnnaBridge 189:f392fc9709a3 846 : \
AnnaBridge 189:f392fc9709a3 847 ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2)) \
AnnaBridge 189:f392fc9709a3 848 )
AnnaBridge 189:f392fc9709a3 849 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
AnnaBridge 189:f392fc9709a3 850 #define ADC_ANY_OTHER_ENABLED(__HANDLE__) (RESET)
AnnaBridge 189:f392fc9709a3 851 #endif
AnnaBridge 189:f392fc9709a3 852
AnnaBridge 189:f392fc9709a3 853 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 189:f392fc9709a3 854 /**
AnnaBridge 189:f392fc9709a3 855 * @brief Set handle instance of the ADC slave associated to the ADC master.
AnnaBridge 189:f392fc9709a3 856 * @param __HANDLE_MASTER__ ADC master handle.
AnnaBridge 189:f392fc9709a3 857 * @param __HANDLE_SLAVE__ ADC slave handle.
AnnaBridge 189:f392fc9709a3 858 * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.
AnnaBridge 189:f392fc9709a3 859 * @retval None
AnnaBridge 189:f392fc9709a3 860 */
AnnaBridge 189:f392fc9709a3 861 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
AnnaBridge 189:f392fc9709a3 862 ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
AnnaBridge 189:f392fc9709a3 863 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
AnnaBridge 189:f392fc9709a3 864
AnnaBridge 189:f392fc9709a3 865 /**
AnnaBridge 189:f392fc9709a3 866 * @brief Check whether or not multimode is configured in DMA mode.
AnnaBridge 189:f392fc9709a3 867 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 868 * @note Return RESET if multimode feature is not available.
AnnaBridge 189:f392fc9709a3 869 * @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled)
AnnaBridge 189:f392fc9709a3 870 */
AnnaBridge 189:f392fc9709a3 871 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 189:f392fc9709a3 872 #define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) \
AnnaBridge 189:f392fc9709a3 873 ((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \
AnnaBridge 189:f392fc9709a3 874 || (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS))
AnnaBridge 189:f392fc9709a3 875 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
AnnaBridge 189:f392fc9709a3 876 #define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) (RESET)
AnnaBridge 189:f392fc9709a3 877 #endif
AnnaBridge 189:f392fc9709a3 878
AnnaBridge 189:f392fc9709a3 879 /**
AnnaBridge 189:f392fc9709a3 880 * @brief Verify the ADC instance connected to the temperature sensor.
AnnaBridge 189:f392fc9709a3 881 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 882 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
AnnaBridge 189:f392fc9709a3 883 */
AnnaBridge 189:f392fc9709a3 884 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
AnnaBridge 189:f392fc9709a3 885 /* The temperature sensor measurement path (channel 17) is available on ADC1 */
AnnaBridge 189:f392fc9709a3 886 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
AnnaBridge 189:f392fc9709a3 887 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 189:f392fc9709a3 888 /* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */
AnnaBridge 189:f392fc9709a3 889 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
AnnaBridge 189:f392fc9709a3 890 #endif
AnnaBridge 189:f392fc9709a3 891
AnnaBridge 189:f392fc9709a3 892 /**
AnnaBridge 189:f392fc9709a3 893 * @brief Verify the ADC instance connected to the battery voltage VBAT.
AnnaBridge 189:f392fc9709a3 894 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 895 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
AnnaBridge 189:f392fc9709a3 896 */
AnnaBridge 189:f392fc9709a3 897 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
AnnaBridge 189:f392fc9709a3 898 /* The battery voltage measurement path (channel 18) is available on ADC1 */
AnnaBridge 189:f392fc9709a3 899 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
AnnaBridge 189:f392fc9709a3 900 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 189:f392fc9709a3 901 /* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */
AnnaBridge 189:f392fc9709a3 902 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
AnnaBridge 189:f392fc9709a3 903 #endif
AnnaBridge 189:f392fc9709a3 904
AnnaBridge 189:f392fc9709a3 905 /**
AnnaBridge 189:f392fc9709a3 906 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
AnnaBridge 189:f392fc9709a3 907 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 908 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
AnnaBridge 189:f392fc9709a3 909 */
AnnaBridge 189:f392fc9709a3 910 /* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */
AnnaBridge 189:f392fc9709a3 911 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
AnnaBridge 189:f392fc9709a3 912
AnnaBridge 189:f392fc9709a3 913 /**
AnnaBridge 189:f392fc9709a3 914 * @brief Verify the length of scheduled injected conversions group.
AnnaBridge 189:f392fc9709a3 915 * @param __LENGTH__ number of programmed conversions.
AnnaBridge 189:f392fc9709a3 916 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
AnnaBridge 189:f392fc9709a3 917 */
AnnaBridge 189:f392fc9709a3 918 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
AnnaBridge 189:f392fc9709a3 919
AnnaBridge 189:f392fc9709a3 920 /**
AnnaBridge 189:f392fc9709a3 921 * @brief Calibration factor size verification (7 bits maximum).
AnnaBridge 189:f392fc9709a3 922 * @param __CALIBRATION_FACTOR__ Calibration factor value.
AnnaBridge 189:f392fc9709a3 923 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
AnnaBridge 189:f392fc9709a3 924 */
AnnaBridge 189:f392fc9709a3 925 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
AnnaBridge 189:f392fc9709a3 926
AnnaBridge 189:f392fc9709a3 927
AnnaBridge 189:f392fc9709a3 928 /**
AnnaBridge 189:f392fc9709a3 929 * @brief Verify the ADC channel setting.
AnnaBridge 189:f392fc9709a3 930 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 931 * @param __CHANNEL__ programmed ADC channel.
AnnaBridge 189:f392fc9709a3 932 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
AnnaBridge 189:f392fc9709a3 933 */
AnnaBridge 189:f392fc9709a3 934 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
AnnaBridge 189:f392fc9709a3 935 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \
AnnaBridge 189:f392fc9709a3 936 (((__CHANNEL__) == ADC_CHANNEL_1) || \
AnnaBridge 189:f392fc9709a3 937 ((__CHANNEL__) == ADC_CHANNEL_2) || \
AnnaBridge 189:f392fc9709a3 938 ((__CHANNEL__) == ADC_CHANNEL_3) || \
AnnaBridge 189:f392fc9709a3 939 ((__CHANNEL__) == ADC_CHANNEL_4) || \
AnnaBridge 189:f392fc9709a3 940 ((__CHANNEL__) == ADC_CHANNEL_5) || \
AnnaBridge 189:f392fc9709a3 941 ((__CHANNEL__) == ADC_CHANNEL_6) || \
AnnaBridge 189:f392fc9709a3 942 ((__CHANNEL__) == ADC_CHANNEL_7) || \
AnnaBridge 189:f392fc9709a3 943 ((__CHANNEL__) == ADC_CHANNEL_8) || \
AnnaBridge 189:f392fc9709a3 944 ((__CHANNEL__) == ADC_CHANNEL_9) || \
AnnaBridge 189:f392fc9709a3 945 ((__CHANNEL__) == ADC_CHANNEL_10) || \
AnnaBridge 189:f392fc9709a3 946 ((__CHANNEL__) == ADC_CHANNEL_11) || \
AnnaBridge 189:f392fc9709a3 947 ((__CHANNEL__) == ADC_CHANNEL_12) || \
AnnaBridge 189:f392fc9709a3 948 ((__CHANNEL__) == ADC_CHANNEL_13) || \
AnnaBridge 189:f392fc9709a3 949 ((__CHANNEL__) == ADC_CHANNEL_14) || \
AnnaBridge 189:f392fc9709a3 950 ((__CHANNEL__) == ADC_CHANNEL_15) || \
AnnaBridge 189:f392fc9709a3 951 ((__CHANNEL__) == ADC_CHANNEL_16) || \
AnnaBridge 189:f392fc9709a3 952 ((__CHANNEL__) == ADC_CHANNEL_17) || \
AnnaBridge 189:f392fc9709a3 953 ((__CHANNEL__) == ADC_CHANNEL_18) || \
AnnaBridge 189:f392fc9709a3 954 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
AnnaBridge 189:f392fc9709a3 955 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
AnnaBridge 189:f392fc9709a3 956 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
AnnaBridge 189:f392fc9709a3 957 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1) || \
AnnaBridge 189:f392fc9709a3 958 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2)))
AnnaBridge 189:f392fc9709a3 959 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 189:f392fc9709a3 960 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \
AnnaBridge 189:f392fc9709a3 961 (((__CHANNEL__) == ADC_CHANNEL_1) || \
AnnaBridge 189:f392fc9709a3 962 ((__CHANNEL__) == ADC_CHANNEL_2) || \
AnnaBridge 189:f392fc9709a3 963 ((__CHANNEL__) == ADC_CHANNEL_3) || \
AnnaBridge 189:f392fc9709a3 964 ((__CHANNEL__) == ADC_CHANNEL_4) || \
AnnaBridge 189:f392fc9709a3 965 ((__CHANNEL__) == ADC_CHANNEL_5) || \
AnnaBridge 189:f392fc9709a3 966 ((__CHANNEL__) == ADC_CHANNEL_6) || \
AnnaBridge 189:f392fc9709a3 967 ((__CHANNEL__) == ADC_CHANNEL_7) || \
AnnaBridge 189:f392fc9709a3 968 ((__CHANNEL__) == ADC_CHANNEL_8) || \
AnnaBridge 189:f392fc9709a3 969 ((__CHANNEL__) == ADC_CHANNEL_9) || \
AnnaBridge 189:f392fc9709a3 970 ((__CHANNEL__) == ADC_CHANNEL_10) || \
AnnaBridge 189:f392fc9709a3 971 ((__CHANNEL__) == ADC_CHANNEL_11) || \
AnnaBridge 189:f392fc9709a3 972 ((__CHANNEL__) == ADC_CHANNEL_12) || \
AnnaBridge 189:f392fc9709a3 973 ((__CHANNEL__) == ADC_CHANNEL_13) || \
AnnaBridge 189:f392fc9709a3 974 ((__CHANNEL__) == ADC_CHANNEL_14) || \
AnnaBridge 189:f392fc9709a3 975 ((__CHANNEL__) == ADC_CHANNEL_15) || \
AnnaBridge 189:f392fc9709a3 976 ((__CHANNEL__) == ADC_CHANNEL_16) || \
AnnaBridge 189:f392fc9709a3 977 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
AnnaBridge 189:f392fc9709a3 978 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
AnnaBridge 189:f392fc9709a3 979 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \
AnnaBridge 189:f392fc9709a3 980 ((((__HANDLE__)->Instance) == ADC2) && \
AnnaBridge 189:f392fc9709a3 981 (((__CHANNEL__) == ADC_CHANNEL_1) || \
AnnaBridge 189:f392fc9709a3 982 ((__CHANNEL__) == ADC_CHANNEL_2) || \
AnnaBridge 189:f392fc9709a3 983 ((__CHANNEL__) == ADC_CHANNEL_3) || \
AnnaBridge 189:f392fc9709a3 984 ((__CHANNEL__) == ADC_CHANNEL_4) || \
AnnaBridge 189:f392fc9709a3 985 ((__CHANNEL__) == ADC_CHANNEL_5) || \
AnnaBridge 189:f392fc9709a3 986 ((__CHANNEL__) == ADC_CHANNEL_6) || \
AnnaBridge 189:f392fc9709a3 987 ((__CHANNEL__) == ADC_CHANNEL_7) || \
AnnaBridge 189:f392fc9709a3 988 ((__CHANNEL__) == ADC_CHANNEL_8) || \
AnnaBridge 189:f392fc9709a3 989 ((__CHANNEL__) == ADC_CHANNEL_9) || \
AnnaBridge 189:f392fc9709a3 990 ((__CHANNEL__) == ADC_CHANNEL_10) || \
AnnaBridge 189:f392fc9709a3 991 ((__CHANNEL__) == ADC_CHANNEL_11) || \
AnnaBridge 189:f392fc9709a3 992 ((__CHANNEL__) == ADC_CHANNEL_12) || \
AnnaBridge 189:f392fc9709a3 993 ((__CHANNEL__) == ADC_CHANNEL_13) || \
AnnaBridge 189:f392fc9709a3 994 ((__CHANNEL__) == ADC_CHANNEL_14) || \
AnnaBridge 189:f392fc9709a3 995 ((__CHANNEL__) == ADC_CHANNEL_15) || \
AnnaBridge 189:f392fc9709a3 996 ((__CHANNEL__) == ADC_CHANNEL_16) || \
AnnaBridge 189:f392fc9709a3 997 ((__CHANNEL__) == ADC_CHANNEL_17) || \
AnnaBridge 189:f392fc9709a3 998 ((__CHANNEL__) == ADC_CHANNEL_18) || \
AnnaBridge 189:f392fc9709a3 999 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \
AnnaBridge 189:f392fc9709a3 1000 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))) || \
AnnaBridge 189:f392fc9709a3 1001 ((((__HANDLE__)->Instance) == ADC3) && \
AnnaBridge 189:f392fc9709a3 1002 (((__CHANNEL__) == ADC_CHANNEL_1) || \
AnnaBridge 189:f392fc9709a3 1003 ((__CHANNEL__) == ADC_CHANNEL_2) || \
AnnaBridge 189:f392fc9709a3 1004 ((__CHANNEL__) == ADC_CHANNEL_3) || \
AnnaBridge 189:f392fc9709a3 1005 ((__CHANNEL__) == ADC_CHANNEL_4) || \
AnnaBridge 189:f392fc9709a3 1006 ((__CHANNEL__) == ADC_CHANNEL_6) || \
AnnaBridge 189:f392fc9709a3 1007 ((__CHANNEL__) == ADC_CHANNEL_7) || \
AnnaBridge 189:f392fc9709a3 1008 ((__CHANNEL__) == ADC_CHANNEL_8) || \
AnnaBridge 189:f392fc9709a3 1009 ((__CHANNEL__) == ADC_CHANNEL_9) || \
AnnaBridge 189:f392fc9709a3 1010 ((__CHANNEL__) == ADC_CHANNEL_10) || \
AnnaBridge 189:f392fc9709a3 1011 ((__CHANNEL__) == ADC_CHANNEL_11) || \
AnnaBridge 189:f392fc9709a3 1012 ((__CHANNEL__) == ADC_CHANNEL_12) || \
AnnaBridge 189:f392fc9709a3 1013 ((__CHANNEL__) == ADC_CHANNEL_13) || \
AnnaBridge 189:f392fc9709a3 1014 ((__CHANNEL__) == ADC_CHANNEL_14) || \
AnnaBridge 189:f392fc9709a3 1015 ((__CHANNEL__) == ADC_CHANNEL_15) || \
AnnaBridge 189:f392fc9709a3 1016 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
AnnaBridge 189:f392fc9709a3 1017 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
AnnaBridge 189:f392fc9709a3 1018 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC3) || \
AnnaBridge 189:f392fc9709a3 1019 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC3) )))
AnnaBridge 189:f392fc9709a3 1020 #endif
AnnaBridge 189:f392fc9709a3 1021
AnnaBridge 189:f392fc9709a3 1022 /**
AnnaBridge 189:f392fc9709a3 1023 * @brief Verify the ADC channel setting in differential mode.
AnnaBridge 189:f392fc9709a3 1024 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 1025 * @param __CHANNEL__ programmed ADC channel.
AnnaBridge 189:f392fc9709a3 1026 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
AnnaBridge 189:f392fc9709a3 1027 */
AnnaBridge 189:f392fc9709a3 1028 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
AnnaBridge 189:f392fc9709a3 1029 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
AnnaBridge 189:f392fc9709a3 1030 ((__CHANNEL__) == ADC_CHANNEL_2) || \
AnnaBridge 189:f392fc9709a3 1031 ((__CHANNEL__) == ADC_CHANNEL_3) || \
AnnaBridge 189:f392fc9709a3 1032 ((__CHANNEL__) == ADC_CHANNEL_4) || \
AnnaBridge 189:f392fc9709a3 1033 ((__CHANNEL__) == ADC_CHANNEL_5) || \
AnnaBridge 189:f392fc9709a3 1034 ((__CHANNEL__) == ADC_CHANNEL_6) || \
AnnaBridge 189:f392fc9709a3 1035 ((__CHANNEL__) == ADC_CHANNEL_7) || \
AnnaBridge 189:f392fc9709a3 1036 ((__CHANNEL__) == ADC_CHANNEL_8) || \
AnnaBridge 189:f392fc9709a3 1037 ((__CHANNEL__) == ADC_CHANNEL_9) || \
AnnaBridge 189:f392fc9709a3 1038 ((__CHANNEL__) == ADC_CHANNEL_10) || \
AnnaBridge 189:f392fc9709a3 1039 ((__CHANNEL__) == ADC_CHANNEL_11) || \
AnnaBridge 189:f392fc9709a3 1040 ((__CHANNEL__) == ADC_CHANNEL_12) || \
AnnaBridge 189:f392fc9709a3 1041 ((__CHANNEL__) == ADC_CHANNEL_13) || \
AnnaBridge 189:f392fc9709a3 1042 ((__CHANNEL__) == ADC_CHANNEL_14) || \
AnnaBridge 189:f392fc9709a3 1043 ((__CHANNEL__) == ADC_CHANNEL_15) )
AnnaBridge 189:f392fc9709a3 1044 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
AnnaBridge 189:f392fc9709a3 1045 /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode,
AnnaBridge 189:f392fc9709a3 1046 channels 0, 16 to 18 can be only used in single-ended mode.
AnnaBridge 189:f392fc9709a3 1047 For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode,
AnnaBridge 189:f392fc9709a3 1048 channels 4, 5 and 13 to 18 can only be used in single-ended mode. */
AnnaBridge 189:f392fc9709a3 1049 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ((((((__HANDLE__)->Instance) == ADC1) || \
AnnaBridge 189:f392fc9709a3 1050 (((__HANDLE__)->Instance) == ADC2)) && \
AnnaBridge 189:f392fc9709a3 1051 (((__CHANNEL__) == ADC_CHANNEL_1) || \
AnnaBridge 189:f392fc9709a3 1052 ((__CHANNEL__) == ADC_CHANNEL_2) || \
AnnaBridge 189:f392fc9709a3 1053 ((__CHANNEL__) == ADC_CHANNEL_3) || \
AnnaBridge 189:f392fc9709a3 1054 ((__CHANNEL__) == ADC_CHANNEL_4) || \
AnnaBridge 189:f392fc9709a3 1055 ((__CHANNEL__) == ADC_CHANNEL_5) || \
AnnaBridge 189:f392fc9709a3 1056 ((__CHANNEL__) == ADC_CHANNEL_6) || \
AnnaBridge 189:f392fc9709a3 1057 ((__CHANNEL__) == ADC_CHANNEL_7) || \
AnnaBridge 189:f392fc9709a3 1058 ((__CHANNEL__) == ADC_CHANNEL_8) || \
AnnaBridge 189:f392fc9709a3 1059 ((__CHANNEL__) == ADC_CHANNEL_9) || \
AnnaBridge 189:f392fc9709a3 1060 ((__CHANNEL__) == ADC_CHANNEL_10) || \
AnnaBridge 189:f392fc9709a3 1061 ((__CHANNEL__) == ADC_CHANNEL_11) || \
AnnaBridge 189:f392fc9709a3 1062 ((__CHANNEL__) == ADC_CHANNEL_12) || \
AnnaBridge 189:f392fc9709a3 1063 ((__CHANNEL__) == ADC_CHANNEL_13) || \
AnnaBridge 189:f392fc9709a3 1064 ((__CHANNEL__) == ADC_CHANNEL_14) || \
AnnaBridge 189:f392fc9709a3 1065 ((__CHANNEL__) == ADC_CHANNEL_15))) || \
AnnaBridge 189:f392fc9709a3 1066 ((((__HANDLE__)->Instance) == ADC3) && \
AnnaBridge 189:f392fc9709a3 1067 (((__CHANNEL__) == ADC_CHANNEL_1) || \
AnnaBridge 189:f392fc9709a3 1068 ((__CHANNEL__) == ADC_CHANNEL_2) || \
AnnaBridge 189:f392fc9709a3 1069 ((__CHANNEL__) == ADC_CHANNEL_3) || \
AnnaBridge 189:f392fc9709a3 1070 ((__CHANNEL__) == ADC_CHANNEL_6) || \
AnnaBridge 189:f392fc9709a3 1071 ((__CHANNEL__) == ADC_CHANNEL_7) || \
AnnaBridge 189:f392fc9709a3 1072 ((__CHANNEL__) == ADC_CHANNEL_8) || \
AnnaBridge 189:f392fc9709a3 1073 ((__CHANNEL__) == ADC_CHANNEL_9) || \
AnnaBridge 189:f392fc9709a3 1074 ((__CHANNEL__) == ADC_CHANNEL_10) || \
AnnaBridge 189:f392fc9709a3 1075 ((__CHANNEL__) == ADC_CHANNEL_11) || \
AnnaBridge 189:f392fc9709a3 1076 ((__CHANNEL__) == ADC_CHANNEL_12) )))
AnnaBridge 189:f392fc9709a3 1077 #endif
AnnaBridge 189:f392fc9709a3 1078
AnnaBridge 189:f392fc9709a3 1079 /**
AnnaBridge 189:f392fc9709a3 1080 * @brief Verify the ADC single-ended input or differential mode setting.
AnnaBridge 189:f392fc9709a3 1081 * @param __SING_DIFF__ programmed channel setting.
AnnaBridge 189:f392fc9709a3 1082 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
AnnaBridge 189:f392fc9709a3 1083 */
AnnaBridge 189:f392fc9709a3 1084 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
AnnaBridge 189:f392fc9709a3 1085 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
AnnaBridge 189:f392fc9709a3 1086
AnnaBridge 189:f392fc9709a3 1087 /**
AnnaBridge 189:f392fc9709a3 1088 * @brief Verify the ADC offset management setting.
AnnaBridge 189:f392fc9709a3 1089 * @param __OFFSET_NUMBER__ ADC offset management.
AnnaBridge 189:f392fc9709a3 1090 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
AnnaBridge 189:f392fc9709a3 1091 */
AnnaBridge 189:f392fc9709a3 1092 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
AnnaBridge 189:f392fc9709a3 1093 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
AnnaBridge 189:f392fc9709a3 1094 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
AnnaBridge 189:f392fc9709a3 1095 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
AnnaBridge 189:f392fc9709a3 1096 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
AnnaBridge 189:f392fc9709a3 1097
AnnaBridge 189:f392fc9709a3 1098 /**
AnnaBridge 189:f392fc9709a3 1099 * @brief Verify the ADC injected channel setting.
AnnaBridge 189:f392fc9709a3 1100 * @param __CHANNEL__ programmed ADC injected channel.
AnnaBridge 189:f392fc9709a3 1101 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
AnnaBridge 189:f392fc9709a3 1102 */
AnnaBridge 189:f392fc9709a3 1103 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
AnnaBridge 189:f392fc9709a3 1104 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
AnnaBridge 189:f392fc9709a3 1105 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
AnnaBridge 189:f392fc9709a3 1106 ((__CHANNEL__) == ADC_INJECTED_RANK_4) )
AnnaBridge 189:f392fc9709a3 1107
AnnaBridge 189:f392fc9709a3 1108 /**
AnnaBridge 189:f392fc9709a3 1109 * @brief Verify the ADC injected conversions external trigger.
AnnaBridge 189:f392fc9709a3 1110 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 1111 * @param __INJTRIG__ programmed ADC injected conversions external trigger.
AnnaBridge 189:f392fc9709a3 1112 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
AnnaBridge 189:f392fc9709a3 1113 */
AnnaBridge 189:f392fc9709a3 1114 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
AnnaBridge 189:f392fc9709a3 1115 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
AnnaBridge 189:f392fc9709a3 1116 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
AnnaBridge 189:f392fc9709a3 1117 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
AnnaBridge 189:f392fc9709a3 1118 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
AnnaBridge 189:f392fc9709a3 1119 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
AnnaBridge 189:f392fc9709a3 1120 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
AnnaBridge 189:f392fc9709a3 1121 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
AnnaBridge 189:f392fc9709a3 1122 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
AnnaBridge 189:f392fc9709a3 1123 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
AnnaBridge 189:f392fc9709a3 1124 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
AnnaBridge 189:f392fc9709a3 1125 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
AnnaBridge 189:f392fc9709a3 1126 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
AnnaBridge 189:f392fc9709a3 1127 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
AnnaBridge 189:f392fc9709a3 1128 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
AnnaBridge 189:f392fc9709a3 1129 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
AnnaBridge 189:f392fc9709a3 1130 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
AnnaBridge 189:f392fc9709a3 1131
AnnaBridge 189:f392fc9709a3 1132 /**
AnnaBridge 189:f392fc9709a3 1133 * @brief Verify the ADC edge trigger setting for injected group.
AnnaBridge 189:f392fc9709a3 1134 * @param __EDGE__ programmed ADC edge trigger setting.
AnnaBridge 189:f392fc9709a3 1135 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
AnnaBridge 189:f392fc9709a3 1136 */
AnnaBridge 189:f392fc9709a3 1137 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
AnnaBridge 189:f392fc9709a3 1138 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
AnnaBridge 189:f392fc9709a3 1139 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
AnnaBridge 189:f392fc9709a3 1140 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
AnnaBridge 189:f392fc9709a3 1141
AnnaBridge 189:f392fc9709a3 1142 #if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge 189:f392fc9709a3 1143 /**
AnnaBridge 189:f392fc9709a3 1144 * @brief Verify the ADC multimode setting.
AnnaBridge 189:f392fc9709a3 1145 * @param __MODE__ programmed ADC multimode setting.
AnnaBridge 189:f392fc9709a3 1146 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
AnnaBridge 189:f392fc9709a3 1147 */
AnnaBridge 189:f392fc9709a3 1148 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
AnnaBridge 189:f392fc9709a3 1149 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
AnnaBridge 189:f392fc9709a3 1150 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
AnnaBridge 189:f392fc9709a3 1151 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
AnnaBridge 189:f392fc9709a3 1152 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
AnnaBridge 189:f392fc9709a3 1153 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
AnnaBridge 189:f392fc9709a3 1154 ((__MODE__) == ADC_DUALMODE_INTERL) || \
AnnaBridge 189:f392fc9709a3 1155 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
AnnaBridge 189:f392fc9709a3 1156
AnnaBridge 189:f392fc9709a3 1157 /**
AnnaBridge 189:f392fc9709a3 1158 * @brief Verify the ADC multimode DMA access setting.
AnnaBridge 189:f392fc9709a3 1159 * @param __MODE__ programmed ADC multimode DMA access setting.
AnnaBridge 189:f392fc9709a3 1160 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
AnnaBridge 189:f392fc9709a3 1161 */
AnnaBridge 189:f392fc9709a3 1162 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \
AnnaBridge 189:f392fc9709a3 1163 ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
AnnaBridge 189:f392fc9709a3 1164 ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) )
AnnaBridge 189:f392fc9709a3 1165
AnnaBridge 189:f392fc9709a3 1166 /**
AnnaBridge 189:f392fc9709a3 1167 * @brief Verify the ADC multimode delay setting.
AnnaBridge 189:f392fc9709a3 1168 * @param __DELAY__ programmed ADC multimode delay setting.
AnnaBridge 189:f392fc9709a3 1169 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
AnnaBridge 189:f392fc9709a3 1170 */
AnnaBridge 189:f392fc9709a3 1171 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
AnnaBridge 189:f392fc9709a3 1172 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
AnnaBridge 189:f392fc9709a3 1173 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
AnnaBridge 189:f392fc9709a3 1174 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
AnnaBridge 189:f392fc9709a3 1175 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
AnnaBridge 189:f392fc9709a3 1176 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
AnnaBridge 189:f392fc9709a3 1177 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
AnnaBridge 189:f392fc9709a3 1178 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
AnnaBridge 189:f392fc9709a3 1179 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
AnnaBridge 189:f392fc9709a3 1180 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
AnnaBridge 189:f392fc9709a3 1181 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
AnnaBridge 189:f392fc9709a3 1182 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) )
AnnaBridge 189:f392fc9709a3 1183 #endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge 189:f392fc9709a3 1184
AnnaBridge 189:f392fc9709a3 1185 /**
AnnaBridge 189:f392fc9709a3 1186 * @brief Verify the ADC analog watchdog setting.
AnnaBridge 189:f392fc9709a3 1187 * @param __WATCHDOG__ programmed ADC analog watchdog setting.
AnnaBridge 189:f392fc9709a3 1188 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
AnnaBridge 189:f392fc9709a3 1189 */
AnnaBridge 189:f392fc9709a3 1190 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
AnnaBridge 189:f392fc9709a3 1191 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
AnnaBridge 189:f392fc9709a3 1192 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
AnnaBridge 189:f392fc9709a3 1193
AnnaBridge 189:f392fc9709a3 1194 /**
AnnaBridge 189:f392fc9709a3 1195 * @brief Verify the ADC analog watchdog mode setting.
AnnaBridge 189:f392fc9709a3 1196 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
AnnaBridge 189:f392fc9709a3 1197 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
AnnaBridge 189:f392fc9709a3 1198 */
AnnaBridge 189:f392fc9709a3 1199 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
AnnaBridge 189:f392fc9709a3 1200 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
AnnaBridge 189:f392fc9709a3 1201 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
AnnaBridge 189:f392fc9709a3 1202 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
AnnaBridge 189:f392fc9709a3 1203 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
AnnaBridge 189:f392fc9709a3 1204 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
AnnaBridge 189:f392fc9709a3 1205 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
AnnaBridge 189:f392fc9709a3 1206
AnnaBridge 189:f392fc9709a3 1207 /**
AnnaBridge 189:f392fc9709a3 1208 * @brief Verify the ADC conversion (regular or injected or both).
AnnaBridge 189:f392fc9709a3 1209 * @param __CONVERSION__ ADC conversion group.
AnnaBridge 189:f392fc9709a3 1210 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
AnnaBridge 189:f392fc9709a3 1211 */
AnnaBridge 189:f392fc9709a3 1212 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
AnnaBridge 189:f392fc9709a3 1213 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \
AnnaBridge 189:f392fc9709a3 1214 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
AnnaBridge 189:f392fc9709a3 1215
AnnaBridge 189:f392fc9709a3 1216 /**
AnnaBridge 189:f392fc9709a3 1217 * @brief Verify the ADC event type.
AnnaBridge 189:f392fc9709a3 1218 * @param __EVENT__ ADC event.
AnnaBridge 189:f392fc9709a3 1219 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
AnnaBridge 189:f392fc9709a3 1220 */
AnnaBridge 189:f392fc9709a3 1221 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
AnnaBridge 189:f392fc9709a3 1222 ((__EVENT__) == ADC_AWD_EVENT) || \
AnnaBridge 189:f392fc9709a3 1223 ((__EVENT__) == ADC_AWD2_EVENT) || \
AnnaBridge 189:f392fc9709a3 1224 ((__EVENT__) == ADC_AWD3_EVENT) || \
AnnaBridge 189:f392fc9709a3 1225 ((__EVENT__) == ADC_OVR_EVENT) || \
AnnaBridge 189:f392fc9709a3 1226 ((__EVENT__) == ADC_JQOVF_EVENT) )
AnnaBridge 189:f392fc9709a3 1227
AnnaBridge 189:f392fc9709a3 1228 /**
AnnaBridge 189:f392fc9709a3 1229 * @brief Verify the ADC oversampling ratio.
AnnaBridge 189:f392fc9709a3 1230 * @param __RATIO__ programmed ADC oversampling ratio.
AnnaBridge 189:f392fc9709a3 1231 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
AnnaBridge 189:f392fc9709a3 1232 */
AnnaBridge 189:f392fc9709a3 1233 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \
AnnaBridge 189:f392fc9709a3 1234 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \
AnnaBridge 189:f392fc9709a3 1235 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \
AnnaBridge 189:f392fc9709a3 1236 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \
AnnaBridge 189:f392fc9709a3 1237 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \
AnnaBridge 189:f392fc9709a3 1238 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
AnnaBridge 189:f392fc9709a3 1239 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
AnnaBridge 189:f392fc9709a3 1240 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
AnnaBridge 189:f392fc9709a3 1241
AnnaBridge 189:f392fc9709a3 1242 /**
AnnaBridge 189:f392fc9709a3 1243 * @brief Verify the ADC oversampling shift.
AnnaBridge 189:f392fc9709a3 1244 * @param __SHIFT__ programmed ADC oversampling shift.
AnnaBridge 189:f392fc9709a3 1245 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
AnnaBridge 189:f392fc9709a3 1246 */
AnnaBridge 189:f392fc9709a3 1247 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
AnnaBridge 189:f392fc9709a3 1248 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
AnnaBridge 189:f392fc9709a3 1249 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
AnnaBridge 189:f392fc9709a3 1250 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
AnnaBridge 189:f392fc9709a3 1251 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
AnnaBridge 189:f392fc9709a3 1252 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
AnnaBridge 189:f392fc9709a3 1253 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
AnnaBridge 189:f392fc9709a3 1254 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
AnnaBridge 189:f392fc9709a3 1255 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
AnnaBridge 189:f392fc9709a3 1256
AnnaBridge 189:f392fc9709a3 1257 /**
AnnaBridge 189:f392fc9709a3 1258 * @brief Verify the ADC oversampling triggered mode.
AnnaBridge 189:f392fc9709a3 1259 * @param __MODE__ programmed ADC oversampling triggered mode.
AnnaBridge 189:f392fc9709a3 1260 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
AnnaBridge 189:f392fc9709a3 1261 */
AnnaBridge 189:f392fc9709a3 1262 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
AnnaBridge 189:f392fc9709a3 1263 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
AnnaBridge 189:f392fc9709a3 1264
AnnaBridge 189:f392fc9709a3 1265 /**
AnnaBridge 189:f392fc9709a3 1266 * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
AnnaBridge 189:f392fc9709a3 1267 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
AnnaBridge 189:f392fc9709a3 1268 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
AnnaBridge 189:f392fc9709a3 1269 */
AnnaBridge 189:f392fc9709a3 1270 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
AnnaBridge 189:f392fc9709a3 1271 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
AnnaBridge 189:f392fc9709a3 1272
AnnaBridge 189:f392fc9709a3 1273 /**
AnnaBridge 189:f392fc9709a3 1274 * @brief Verify the DFSDM mode configuration.
AnnaBridge 189:f392fc9709a3 1275 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 1276 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
AnnaBridge 189:f392fc9709a3 1277 * this reason, the input parameter is the ADC handle and not the configuration parameter
AnnaBridge 189:f392fc9709a3 1278 * directly.
AnnaBridge 189:f392fc9709a3 1279 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
AnnaBridge 189:f392fc9709a3 1280 */
AnnaBridge 189:f392fc9709a3 1281 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
AnnaBridge 189:f392fc9709a3 1282 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \
AnnaBridge 189:f392fc9709a3 1283 ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) )
AnnaBridge 189:f392fc9709a3 1284 #else
AnnaBridge 189:f392fc9709a3 1285 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
AnnaBridge 189:f392fc9709a3 1286 #endif
AnnaBridge 189:f392fc9709a3 1287
AnnaBridge 189:f392fc9709a3 1288 /**
AnnaBridge 189:f392fc9709a3 1289 * @brief Return the DFSDM configuration mode.
AnnaBridge 189:f392fc9709a3 1290 * @param __HANDLE__ ADC handle.
AnnaBridge 189:f392fc9709a3 1291 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
AnnaBridge 189:f392fc9709a3 1292 * For this reason, the input parameter is the ADC handle and not the configuration parameter
AnnaBridge 189:f392fc9709a3 1293 * directly.
AnnaBridge 189:f392fc9709a3 1294 * @retval DFSDM configuration mode
AnnaBridge 189:f392fc9709a3 1295 */
AnnaBridge 189:f392fc9709a3 1296 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
AnnaBridge 189:f392fc9709a3 1297 #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig)
AnnaBridge 189:f392fc9709a3 1298 #else
AnnaBridge 189:f392fc9709a3 1299 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0)
AnnaBridge 189:f392fc9709a3 1300 #endif
AnnaBridge 189:f392fc9709a3 1301
AnnaBridge 189:f392fc9709a3 1302 /**
AnnaBridge 189:f392fc9709a3 1303 * @}
AnnaBridge 189:f392fc9709a3 1304 */
AnnaBridge 189:f392fc9709a3 1305
AnnaBridge 189:f392fc9709a3 1306
AnnaBridge 189:f392fc9709a3 1307 /* Exported functions --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 1308 /** @addtogroup ADCEx_Exported_Functions
AnnaBridge 189:f392fc9709a3 1309 * @{
AnnaBridge 189:f392fc9709a3 1310 */
AnnaBridge 189:f392fc9709a3 1311
AnnaBridge 189:f392fc9709a3 1312 /** @addtogroup ADCEx_Exported_Functions_Group1
AnnaBridge 189:f392fc9709a3 1313 * @{
AnnaBridge 189:f392fc9709a3 1314 */
AnnaBridge 189:f392fc9709a3 1315 /* IO operation functions *****************************************************/
AnnaBridge 189:f392fc9709a3 1316
AnnaBridge 189:f392fc9709a3 1317 /* ADC calibration */
AnnaBridge 189:f392fc9709a3 1318 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
AnnaBridge 189:f392fc9709a3 1319 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
AnnaBridge 189:f392fc9709a3 1320 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
AnnaBridge 189:f392fc9709a3 1321
AnnaBridge 189:f392fc9709a3 1322 /* Blocking mode: Polling */
AnnaBridge 189:f392fc9709a3 1323 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1324 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1325 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
AnnaBridge 189:f392fc9709a3 1326
AnnaBridge 189:f392fc9709a3 1327 /* Non-blocking mode: Interruption */
AnnaBridge 189:f392fc9709a3 1328 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1329 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1330
AnnaBridge 189:f392fc9709a3 1331 #if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge 189:f392fc9709a3 1332 /* ADC multimode */
AnnaBridge 189:f392fc9709a3 1333 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
AnnaBridge 189:f392fc9709a3 1334 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
AnnaBridge 189:f392fc9709a3 1335 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
AnnaBridge 189:f392fc9709a3 1336 #endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge 189:f392fc9709a3 1337
AnnaBridge 189:f392fc9709a3 1338 /* ADC retrieve conversion value intended to be used with polling or interruption */
AnnaBridge 189:f392fc9709a3 1339 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
AnnaBridge 189:f392fc9709a3 1340
AnnaBridge 189:f392fc9709a3 1341 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
AnnaBridge 189:f392fc9709a3 1342 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1343 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1344 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1345 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1346 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1347
AnnaBridge 189:f392fc9709a3 1348 /* ADC group regular conversions stop */
AnnaBridge 189:f392fc9709a3 1349 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1350 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1351 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1352 #if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge 189:f392fc9709a3 1353 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1354 #endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge 189:f392fc9709a3 1355
AnnaBridge 189:f392fc9709a3 1356 /**
AnnaBridge 189:f392fc9709a3 1357 * @}
AnnaBridge 189:f392fc9709a3 1358 */
AnnaBridge 189:f392fc9709a3 1359
AnnaBridge 189:f392fc9709a3 1360 /** @addtogroup ADCEx_Exported_Functions_Group2
AnnaBridge 189:f392fc9709a3 1361 * @{
AnnaBridge 189:f392fc9709a3 1362 */
AnnaBridge 189:f392fc9709a3 1363 /* Peripheral Control functions ***********************************************/
AnnaBridge 189:f392fc9709a3 1364 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
AnnaBridge 189:f392fc9709a3 1365 #if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge 189:f392fc9709a3 1366 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
AnnaBridge 189:f392fc9709a3 1367 #endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge 189:f392fc9709a3 1368 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1369 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1370 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1371 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc);
AnnaBridge 189:f392fc9709a3 1372
AnnaBridge 189:f392fc9709a3 1373 /**
AnnaBridge 189:f392fc9709a3 1374 * @}
AnnaBridge 189:f392fc9709a3 1375 */
AnnaBridge 189:f392fc9709a3 1376
AnnaBridge 189:f392fc9709a3 1377 /**
AnnaBridge 189:f392fc9709a3 1378 * @}
AnnaBridge 189:f392fc9709a3 1379 */
AnnaBridge 189:f392fc9709a3 1380
AnnaBridge 189:f392fc9709a3 1381 /**
AnnaBridge 189:f392fc9709a3 1382 * @}
AnnaBridge 189:f392fc9709a3 1383 */
AnnaBridge 189:f392fc9709a3 1384
AnnaBridge 189:f392fc9709a3 1385 /**
AnnaBridge 189:f392fc9709a3 1386 * @}
AnnaBridge 189:f392fc9709a3 1387 */
AnnaBridge 189:f392fc9709a3 1388
AnnaBridge 189:f392fc9709a3 1389 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 1390 }
AnnaBridge 189:f392fc9709a3 1391 #endif
AnnaBridge 189:f392fc9709a3 1392
AnnaBridge 189:f392fc9709a3 1393 #endif /* __STM32L4xx_HAL_ADC_EX_H */
AnnaBridge 189:f392fc9709a3 1394
AnnaBridge 189:f392fc9709a3 1395
AnnaBridge 189:f392fc9709a3 1396 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/