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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_ARM_STD/core_armv8mbl.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /**************************************************************************//**
AnnaBridge 189:f392fc9709a3 2 * @file core_armv8mbl.h
AnnaBridge 189:f392fc9709a3 3 * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
AnnaBridge 189:f392fc9709a3 4 * @version V5.0.7
AnnaBridge 189:f392fc9709a3 5 * @date 22. June 2018
AnnaBridge 189:f392fc9709a3 6 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 7 /*
AnnaBridge 189:f392fc9709a3 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 189:f392fc9709a3 9 *
AnnaBridge 189:f392fc9709a3 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 189:f392fc9709a3 11 *
AnnaBridge 189:f392fc9709a3 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 189:f392fc9709a3 13 * not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 14 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 15 *
AnnaBridge 189:f392fc9709a3 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 17 *
AnnaBridge 189:f392fc9709a3 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 189:f392fc9709a3 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 21 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 22 * limitations under the License.
AnnaBridge 189:f392fc9709a3 23 */
AnnaBridge 189:f392fc9709a3 24
AnnaBridge 189:f392fc9709a3 25 #if defined ( __ICCARM__ )
AnnaBridge 189:f392fc9709a3 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 189:f392fc9709a3 27 #elif defined (__clang__)
AnnaBridge 189:f392fc9709a3 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 189:f392fc9709a3 29 #endif
AnnaBridge 189:f392fc9709a3 30
AnnaBridge 189:f392fc9709a3 31 #ifndef __CORE_ARMV8MBL_H_GENERIC
AnnaBridge 189:f392fc9709a3 32 #define __CORE_ARMV8MBL_H_GENERIC
AnnaBridge 189:f392fc9709a3 33
AnnaBridge 189:f392fc9709a3 34 #include <stdint.h>
AnnaBridge 189:f392fc9709a3 35
AnnaBridge 189:f392fc9709a3 36 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 37 extern "C" {
AnnaBridge 189:f392fc9709a3 38 #endif
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 /**
AnnaBridge 189:f392fc9709a3 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 189:f392fc9709a3 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 189:f392fc9709a3 43
AnnaBridge 189:f392fc9709a3 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 189:f392fc9709a3 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 189:f392fc9709a3 46
AnnaBridge 189:f392fc9709a3 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 189:f392fc9709a3 48 Unions are used for effective representation of core registers.
AnnaBridge 189:f392fc9709a3 49
AnnaBridge 189:f392fc9709a3 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 189:f392fc9709a3 51 Function-like macros are used to allow more efficient code.
AnnaBridge 189:f392fc9709a3 52 */
AnnaBridge 189:f392fc9709a3 53
AnnaBridge 189:f392fc9709a3 54
AnnaBridge 189:f392fc9709a3 55 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 56 * CMSIS definitions
AnnaBridge 189:f392fc9709a3 57 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 58 /**
AnnaBridge 189:f392fc9709a3 59 \ingroup Cortex_ARMv8MBL
AnnaBridge 189:f392fc9709a3 60 @{
AnnaBridge 189:f392fc9709a3 61 */
AnnaBridge 189:f392fc9709a3 62
AnnaBridge 189:f392fc9709a3 63 #include "cmsis_version.h"
AnnaBridge 189:f392fc9709a3 64
AnnaBridge 189:f392fc9709a3 65 /* CMSIS definitions */
AnnaBridge 189:f392fc9709a3 66 #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
AnnaBridge 189:f392fc9709a3 67 #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 189:f392fc9709a3 68 #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 189:f392fc9709a3 69 __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 189:f392fc9709a3 70
AnnaBridge 189:f392fc9709a3 71 #define __CORTEX_M ( 2U) /*!< Cortex-M Core */
AnnaBridge 189:f392fc9709a3 72
AnnaBridge 189:f392fc9709a3 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 189:f392fc9709a3 74 This core does not support an FPU at all
AnnaBridge 189:f392fc9709a3 75 */
AnnaBridge 189:f392fc9709a3 76 #define __FPU_USED 0U
AnnaBridge 189:f392fc9709a3 77
AnnaBridge 189:f392fc9709a3 78 #if defined ( __CC_ARM )
AnnaBridge 189:f392fc9709a3 79 #if defined __TARGET_FPU_VFP
AnnaBridge 189:f392fc9709a3 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 81 #endif
AnnaBridge 189:f392fc9709a3 82
AnnaBridge 189:f392fc9709a3 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 189:f392fc9709a3 84 #if defined __ARM_FP
AnnaBridge 189:f392fc9709a3 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 86 #endif
AnnaBridge 189:f392fc9709a3 87
AnnaBridge 189:f392fc9709a3 88 #elif defined ( __GNUC__ )
AnnaBridge 189:f392fc9709a3 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 189:f392fc9709a3 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 91 #endif
AnnaBridge 189:f392fc9709a3 92
AnnaBridge 189:f392fc9709a3 93 #elif defined ( __ICCARM__ )
AnnaBridge 189:f392fc9709a3 94 #if defined __ARMVFP__
AnnaBridge 189:f392fc9709a3 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 96 #endif
AnnaBridge 189:f392fc9709a3 97
AnnaBridge 189:f392fc9709a3 98 #elif defined ( __TI_ARM__ )
AnnaBridge 189:f392fc9709a3 99 #if defined __TI_VFP_SUPPORT__
AnnaBridge 189:f392fc9709a3 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 101 #endif
AnnaBridge 189:f392fc9709a3 102
AnnaBridge 189:f392fc9709a3 103 #elif defined ( __TASKING__ )
AnnaBridge 189:f392fc9709a3 104 #if defined __FPU_VFP__
AnnaBridge 189:f392fc9709a3 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 106 #endif
AnnaBridge 189:f392fc9709a3 107
AnnaBridge 189:f392fc9709a3 108 #elif defined ( __CSMC__ )
AnnaBridge 189:f392fc9709a3 109 #if ( __CSMC__ & 0x400U)
AnnaBridge 189:f392fc9709a3 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 111 #endif
AnnaBridge 189:f392fc9709a3 112
AnnaBridge 189:f392fc9709a3 113 #endif
AnnaBridge 189:f392fc9709a3 114
AnnaBridge 189:f392fc9709a3 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 189:f392fc9709a3 116
AnnaBridge 189:f392fc9709a3 117
AnnaBridge 189:f392fc9709a3 118 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 119 }
AnnaBridge 189:f392fc9709a3 120 #endif
AnnaBridge 189:f392fc9709a3 121
AnnaBridge 189:f392fc9709a3 122 #endif /* __CORE_ARMV8MBL_H_GENERIC */
AnnaBridge 189:f392fc9709a3 123
AnnaBridge 189:f392fc9709a3 124 #ifndef __CMSIS_GENERIC
AnnaBridge 189:f392fc9709a3 125
AnnaBridge 189:f392fc9709a3 126 #ifndef __CORE_ARMV8MBL_H_DEPENDANT
AnnaBridge 189:f392fc9709a3 127 #define __CORE_ARMV8MBL_H_DEPENDANT
AnnaBridge 189:f392fc9709a3 128
AnnaBridge 189:f392fc9709a3 129 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 130 extern "C" {
AnnaBridge 189:f392fc9709a3 131 #endif
AnnaBridge 189:f392fc9709a3 132
AnnaBridge 189:f392fc9709a3 133 /* check device defines and use defaults */
AnnaBridge 189:f392fc9709a3 134 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 189:f392fc9709a3 135 #ifndef __ARMv8MBL_REV
AnnaBridge 189:f392fc9709a3 136 #define __ARMv8MBL_REV 0x0000U
AnnaBridge 189:f392fc9709a3 137 #warning "__ARMv8MBL_REV not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 138 #endif
AnnaBridge 189:f392fc9709a3 139
AnnaBridge 189:f392fc9709a3 140 #ifndef __FPU_PRESENT
AnnaBridge 189:f392fc9709a3 141 #define __FPU_PRESENT 0U
AnnaBridge 189:f392fc9709a3 142 #warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 143 #endif
AnnaBridge 189:f392fc9709a3 144
AnnaBridge 189:f392fc9709a3 145 #ifndef __MPU_PRESENT
AnnaBridge 189:f392fc9709a3 146 #define __MPU_PRESENT 0U
AnnaBridge 189:f392fc9709a3 147 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 148 #endif
AnnaBridge 189:f392fc9709a3 149
AnnaBridge 189:f392fc9709a3 150 #ifndef __SAUREGION_PRESENT
AnnaBridge 189:f392fc9709a3 151 #define __SAUREGION_PRESENT 0U
AnnaBridge 189:f392fc9709a3 152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 153 #endif
AnnaBridge 189:f392fc9709a3 154
AnnaBridge 189:f392fc9709a3 155 #ifndef __VTOR_PRESENT
AnnaBridge 189:f392fc9709a3 156 #define __VTOR_PRESENT 0U
AnnaBridge 189:f392fc9709a3 157 #warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 158 #endif
AnnaBridge 189:f392fc9709a3 159
AnnaBridge 189:f392fc9709a3 160 #ifndef __NVIC_PRIO_BITS
AnnaBridge 189:f392fc9709a3 161 #define __NVIC_PRIO_BITS 2U
AnnaBridge 189:f392fc9709a3 162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 163 #endif
AnnaBridge 189:f392fc9709a3 164
AnnaBridge 189:f392fc9709a3 165 #ifndef __Vendor_SysTickConfig
AnnaBridge 189:f392fc9709a3 166 #define __Vendor_SysTickConfig 0U
AnnaBridge 189:f392fc9709a3 167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 168 #endif
AnnaBridge 189:f392fc9709a3 169
AnnaBridge 189:f392fc9709a3 170 #ifndef __ETM_PRESENT
AnnaBridge 189:f392fc9709a3 171 #define __ETM_PRESENT 0U
AnnaBridge 189:f392fc9709a3 172 #warning "__ETM_PRESENT not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 173 #endif
AnnaBridge 189:f392fc9709a3 174
AnnaBridge 189:f392fc9709a3 175 #ifndef __MTB_PRESENT
AnnaBridge 189:f392fc9709a3 176 #define __MTB_PRESENT 0U
AnnaBridge 189:f392fc9709a3 177 #warning "__MTB_PRESENT not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 178 #endif
AnnaBridge 189:f392fc9709a3 179
AnnaBridge 189:f392fc9709a3 180 #endif
AnnaBridge 189:f392fc9709a3 181
AnnaBridge 189:f392fc9709a3 182 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 189:f392fc9709a3 183 /**
AnnaBridge 189:f392fc9709a3 184 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 189:f392fc9709a3 185
AnnaBridge 189:f392fc9709a3 186 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 189:f392fc9709a3 187 \li to specify the access to peripheral variables.
AnnaBridge 189:f392fc9709a3 188 \li for automatic generation of peripheral register debug information.
AnnaBridge 189:f392fc9709a3 189 */
AnnaBridge 189:f392fc9709a3 190 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 191 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 189:f392fc9709a3 192 #else
AnnaBridge 189:f392fc9709a3 193 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 189:f392fc9709a3 194 #endif
AnnaBridge 189:f392fc9709a3 195 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 189:f392fc9709a3 196 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 189:f392fc9709a3 197
AnnaBridge 189:f392fc9709a3 198 /* following defines should be used for structure members */
AnnaBridge 189:f392fc9709a3 199 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 189:f392fc9709a3 200 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 189:f392fc9709a3 201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 189:f392fc9709a3 202
AnnaBridge 189:f392fc9709a3 203 /*@} end of group ARMv8MBL */
AnnaBridge 189:f392fc9709a3 204
AnnaBridge 189:f392fc9709a3 205
AnnaBridge 189:f392fc9709a3 206
AnnaBridge 189:f392fc9709a3 207 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 208 * Register Abstraction
AnnaBridge 189:f392fc9709a3 209 Core Register contain:
AnnaBridge 189:f392fc9709a3 210 - Core Register
AnnaBridge 189:f392fc9709a3 211 - Core NVIC Register
AnnaBridge 189:f392fc9709a3 212 - Core SCB Register
AnnaBridge 189:f392fc9709a3 213 - Core SysTick Register
AnnaBridge 189:f392fc9709a3 214 - Core Debug Register
AnnaBridge 189:f392fc9709a3 215 - Core MPU Register
AnnaBridge 189:f392fc9709a3 216 - Core SAU Register
AnnaBridge 189:f392fc9709a3 217 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 218 /**
AnnaBridge 189:f392fc9709a3 219 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 189:f392fc9709a3 220 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 189:f392fc9709a3 221 */
AnnaBridge 189:f392fc9709a3 222
AnnaBridge 189:f392fc9709a3 223 /**
AnnaBridge 189:f392fc9709a3 224 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 225 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 189:f392fc9709a3 226 \brief Core Register type definitions.
AnnaBridge 189:f392fc9709a3 227 @{
AnnaBridge 189:f392fc9709a3 228 */
AnnaBridge 189:f392fc9709a3 229
AnnaBridge 189:f392fc9709a3 230 /**
AnnaBridge 189:f392fc9709a3 231 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 189:f392fc9709a3 232 */
AnnaBridge 189:f392fc9709a3 233 typedef union
AnnaBridge 189:f392fc9709a3 234 {
AnnaBridge 189:f392fc9709a3 235 struct
AnnaBridge 189:f392fc9709a3 236 {
AnnaBridge 189:f392fc9709a3 237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 189:f392fc9709a3 238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 189:f392fc9709a3 239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 189:f392fc9709a3 240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 189:f392fc9709a3 241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 189:f392fc9709a3 242 } b; /*!< Structure used for bit access */
AnnaBridge 189:f392fc9709a3 243 uint32_t w; /*!< Type used for word access */
AnnaBridge 189:f392fc9709a3 244 } APSR_Type;
AnnaBridge 189:f392fc9709a3 245
AnnaBridge 189:f392fc9709a3 246 /* APSR Register Definitions */
AnnaBridge 189:f392fc9709a3 247 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 189:f392fc9709a3 248 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 189:f392fc9709a3 249
AnnaBridge 189:f392fc9709a3 250 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 189:f392fc9709a3 251 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 189:f392fc9709a3 252
AnnaBridge 189:f392fc9709a3 253 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 189:f392fc9709a3 254 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 189:f392fc9709a3 255
AnnaBridge 189:f392fc9709a3 256 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 189:f392fc9709a3 257 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 189:f392fc9709a3 258
AnnaBridge 189:f392fc9709a3 259
AnnaBridge 189:f392fc9709a3 260 /**
AnnaBridge 189:f392fc9709a3 261 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 189:f392fc9709a3 262 */
AnnaBridge 189:f392fc9709a3 263 typedef union
AnnaBridge 189:f392fc9709a3 264 {
AnnaBridge 189:f392fc9709a3 265 struct
AnnaBridge 189:f392fc9709a3 266 {
AnnaBridge 189:f392fc9709a3 267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 189:f392fc9709a3 268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 189:f392fc9709a3 269 } b; /*!< Structure used for bit access */
AnnaBridge 189:f392fc9709a3 270 uint32_t w; /*!< Type used for word access */
AnnaBridge 189:f392fc9709a3 271 } IPSR_Type;
AnnaBridge 189:f392fc9709a3 272
AnnaBridge 189:f392fc9709a3 273 /* IPSR Register Definitions */
AnnaBridge 189:f392fc9709a3 274 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 189:f392fc9709a3 275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 189:f392fc9709a3 276
AnnaBridge 189:f392fc9709a3 277
AnnaBridge 189:f392fc9709a3 278 /**
AnnaBridge 189:f392fc9709a3 279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 189:f392fc9709a3 280 */
AnnaBridge 189:f392fc9709a3 281 typedef union
AnnaBridge 189:f392fc9709a3 282 {
AnnaBridge 189:f392fc9709a3 283 struct
AnnaBridge 189:f392fc9709a3 284 {
AnnaBridge 189:f392fc9709a3 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 189:f392fc9709a3 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 189:f392fc9709a3 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 189:f392fc9709a3 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 189:f392fc9709a3 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 189:f392fc9709a3 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 189:f392fc9709a3 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 189:f392fc9709a3 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 189:f392fc9709a3 293 } b; /*!< Structure used for bit access */
AnnaBridge 189:f392fc9709a3 294 uint32_t w; /*!< Type used for word access */
AnnaBridge 189:f392fc9709a3 295 } xPSR_Type;
AnnaBridge 189:f392fc9709a3 296
AnnaBridge 189:f392fc9709a3 297 /* xPSR Register Definitions */
AnnaBridge 189:f392fc9709a3 298 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 189:f392fc9709a3 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 189:f392fc9709a3 300
AnnaBridge 189:f392fc9709a3 301 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 189:f392fc9709a3 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 189:f392fc9709a3 303
AnnaBridge 189:f392fc9709a3 304 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 189:f392fc9709a3 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 189:f392fc9709a3 306
AnnaBridge 189:f392fc9709a3 307 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 189:f392fc9709a3 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 189:f392fc9709a3 309
AnnaBridge 189:f392fc9709a3 310 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 189:f392fc9709a3 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 189:f392fc9709a3 312
AnnaBridge 189:f392fc9709a3 313 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 189:f392fc9709a3 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 189:f392fc9709a3 315
AnnaBridge 189:f392fc9709a3 316
AnnaBridge 189:f392fc9709a3 317 /**
AnnaBridge 189:f392fc9709a3 318 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 189:f392fc9709a3 319 */
AnnaBridge 189:f392fc9709a3 320 typedef union
AnnaBridge 189:f392fc9709a3 321 {
AnnaBridge 189:f392fc9709a3 322 struct
AnnaBridge 189:f392fc9709a3 323 {
AnnaBridge 189:f392fc9709a3 324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 189:f392fc9709a3 325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
AnnaBridge 189:f392fc9709a3 326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 189:f392fc9709a3 327 } b; /*!< Structure used for bit access */
AnnaBridge 189:f392fc9709a3 328 uint32_t w; /*!< Type used for word access */
AnnaBridge 189:f392fc9709a3 329 } CONTROL_Type;
AnnaBridge 189:f392fc9709a3 330
AnnaBridge 189:f392fc9709a3 331 /* CONTROL Register Definitions */
AnnaBridge 189:f392fc9709a3 332 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 189:f392fc9709a3 333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 189:f392fc9709a3 334
AnnaBridge 189:f392fc9709a3 335 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
AnnaBridge 189:f392fc9709a3 336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 189:f392fc9709a3 337
AnnaBridge 189:f392fc9709a3 338 /*@} end of group CMSIS_CORE */
AnnaBridge 189:f392fc9709a3 339
AnnaBridge 189:f392fc9709a3 340
AnnaBridge 189:f392fc9709a3 341 /**
AnnaBridge 189:f392fc9709a3 342 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 189:f392fc9709a3 344 \brief Type definitions for the NVIC Registers
AnnaBridge 189:f392fc9709a3 345 @{
AnnaBridge 189:f392fc9709a3 346 */
AnnaBridge 189:f392fc9709a3 347
AnnaBridge 189:f392fc9709a3 348 /**
AnnaBridge 189:f392fc9709a3 349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 189:f392fc9709a3 350 */
AnnaBridge 189:f392fc9709a3 351 typedef struct
AnnaBridge 189:f392fc9709a3 352 {
AnnaBridge 189:f392fc9709a3 353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 189:f392fc9709a3 354 uint32_t RESERVED0[16U];
AnnaBridge 189:f392fc9709a3 355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 189:f392fc9709a3 356 uint32_t RSERVED1[16U];
AnnaBridge 189:f392fc9709a3 357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 189:f392fc9709a3 358 uint32_t RESERVED2[16U];
AnnaBridge 189:f392fc9709a3 359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 189:f392fc9709a3 360 uint32_t RESERVED3[16U];
AnnaBridge 189:f392fc9709a3 361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 189:f392fc9709a3 362 uint32_t RESERVED4[16U];
AnnaBridge 189:f392fc9709a3 363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
AnnaBridge 189:f392fc9709a3 364 uint32_t RESERVED5[16U];
AnnaBridge 189:f392fc9709a3 365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 189:f392fc9709a3 366 } NVIC_Type;
AnnaBridge 189:f392fc9709a3 367
AnnaBridge 189:f392fc9709a3 368 /*@} end of group CMSIS_NVIC */
AnnaBridge 189:f392fc9709a3 369
AnnaBridge 189:f392fc9709a3 370
AnnaBridge 189:f392fc9709a3 371 /**
AnnaBridge 189:f392fc9709a3 372 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 373 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 189:f392fc9709a3 374 \brief Type definitions for the System Control Block Registers
AnnaBridge 189:f392fc9709a3 375 @{
AnnaBridge 189:f392fc9709a3 376 */
AnnaBridge 189:f392fc9709a3 377
AnnaBridge 189:f392fc9709a3 378 /**
AnnaBridge 189:f392fc9709a3 379 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 189:f392fc9709a3 380 */
AnnaBridge 189:f392fc9709a3 381 typedef struct
AnnaBridge 189:f392fc9709a3 382 {
AnnaBridge 189:f392fc9709a3 383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 189:f392fc9709a3 384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 189:f392fc9709a3 385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 189:f392fc9709a3 387 #else
AnnaBridge 189:f392fc9709a3 388 uint32_t RESERVED0;
AnnaBridge 189:f392fc9709a3 389 #endif
AnnaBridge 189:f392fc9709a3 390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 189:f392fc9709a3 391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 189:f392fc9709a3 392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 189:f392fc9709a3 393 uint32_t RESERVED1;
AnnaBridge 189:f392fc9709a3 394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 189:f392fc9709a3 395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 189:f392fc9709a3 396 } SCB_Type;
AnnaBridge 189:f392fc9709a3 397
AnnaBridge 189:f392fc9709a3 398 /* SCB CPUID Register Definitions */
AnnaBridge 189:f392fc9709a3 399 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 189:f392fc9709a3 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 189:f392fc9709a3 401
AnnaBridge 189:f392fc9709a3 402 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 189:f392fc9709a3 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 189:f392fc9709a3 404
AnnaBridge 189:f392fc9709a3 405 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 189:f392fc9709a3 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 189:f392fc9709a3 407
AnnaBridge 189:f392fc9709a3 408 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 189:f392fc9709a3 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 189:f392fc9709a3 410
AnnaBridge 189:f392fc9709a3 411 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 189:f392fc9709a3 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 189:f392fc9709a3 413
AnnaBridge 189:f392fc9709a3 414 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 189:f392fc9709a3 415 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
AnnaBridge 189:f392fc9709a3 416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
AnnaBridge 189:f392fc9709a3 417
AnnaBridge 189:f392fc9709a3 418 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
AnnaBridge 189:f392fc9709a3 419 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
AnnaBridge 189:f392fc9709a3 420
AnnaBridge 189:f392fc9709a3 421 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
AnnaBridge 189:f392fc9709a3 422 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
AnnaBridge 189:f392fc9709a3 423
AnnaBridge 189:f392fc9709a3 424 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 189:f392fc9709a3 425 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 189:f392fc9709a3 426
AnnaBridge 189:f392fc9709a3 427 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 189:f392fc9709a3 428 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 189:f392fc9709a3 429
AnnaBridge 189:f392fc9709a3 430 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 189:f392fc9709a3 431 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 189:f392fc9709a3 432
AnnaBridge 189:f392fc9709a3 433 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 189:f392fc9709a3 434 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 189:f392fc9709a3 435
AnnaBridge 189:f392fc9709a3 436 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
AnnaBridge 189:f392fc9709a3 437 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
AnnaBridge 189:f392fc9709a3 438
AnnaBridge 189:f392fc9709a3 439 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 189:f392fc9709a3 440 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 189:f392fc9709a3 441
AnnaBridge 189:f392fc9709a3 442 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 189:f392fc9709a3 443 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 189:f392fc9709a3 444
AnnaBridge 189:f392fc9709a3 445 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 189:f392fc9709a3 446 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 189:f392fc9709a3 447
AnnaBridge 189:f392fc9709a3 448 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
AnnaBridge 189:f392fc9709a3 449 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
AnnaBridge 189:f392fc9709a3 450
AnnaBridge 189:f392fc9709a3 451 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 189:f392fc9709a3 452 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 189:f392fc9709a3 453
AnnaBridge 189:f392fc9709a3 454 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 455 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 189:f392fc9709a3 456 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 189:f392fc9709a3 457 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 189:f392fc9709a3 458 #endif
AnnaBridge 189:f392fc9709a3 459
AnnaBridge 189:f392fc9709a3 460 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 189:f392fc9709a3 461 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 189:f392fc9709a3 462 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 189:f392fc9709a3 463
AnnaBridge 189:f392fc9709a3 464 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 189:f392fc9709a3 465 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 189:f392fc9709a3 466
AnnaBridge 189:f392fc9709a3 467 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 189:f392fc9709a3 468 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 189:f392fc9709a3 469
AnnaBridge 189:f392fc9709a3 470 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
AnnaBridge 189:f392fc9709a3 471 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
AnnaBridge 189:f392fc9709a3 472
AnnaBridge 189:f392fc9709a3 473 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
AnnaBridge 189:f392fc9709a3 474 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
AnnaBridge 189:f392fc9709a3 475
AnnaBridge 189:f392fc9709a3 476 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
AnnaBridge 189:f392fc9709a3 477 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
AnnaBridge 189:f392fc9709a3 478
AnnaBridge 189:f392fc9709a3 479 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 189:f392fc9709a3 480 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 189:f392fc9709a3 481
AnnaBridge 189:f392fc9709a3 482 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 189:f392fc9709a3 483 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 189:f392fc9709a3 484
AnnaBridge 189:f392fc9709a3 485 /* SCB System Control Register Definitions */
AnnaBridge 189:f392fc9709a3 486 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 189:f392fc9709a3 487 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 189:f392fc9709a3 488
AnnaBridge 189:f392fc9709a3 489 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
AnnaBridge 189:f392fc9709a3 490 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
AnnaBridge 189:f392fc9709a3 491
AnnaBridge 189:f392fc9709a3 492 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 189:f392fc9709a3 493 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 189:f392fc9709a3 494
AnnaBridge 189:f392fc9709a3 495 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 189:f392fc9709a3 496 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 189:f392fc9709a3 497
AnnaBridge 189:f392fc9709a3 498 /* SCB Configuration Control Register Definitions */
AnnaBridge 189:f392fc9709a3 499 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
AnnaBridge 189:f392fc9709a3 500 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
AnnaBridge 189:f392fc9709a3 501
AnnaBridge 189:f392fc9709a3 502 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
AnnaBridge 189:f392fc9709a3 503 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
AnnaBridge 189:f392fc9709a3 504
AnnaBridge 189:f392fc9709a3 505 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
AnnaBridge 189:f392fc9709a3 506 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
AnnaBridge 189:f392fc9709a3 507
AnnaBridge 189:f392fc9709a3 508 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
AnnaBridge 189:f392fc9709a3 509 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
AnnaBridge 189:f392fc9709a3 510
AnnaBridge 189:f392fc9709a3 511 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
AnnaBridge 189:f392fc9709a3 512 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
AnnaBridge 189:f392fc9709a3 513
AnnaBridge 189:f392fc9709a3 514 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
AnnaBridge 189:f392fc9709a3 515 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
AnnaBridge 189:f392fc9709a3 516
AnnaBridge 189:f392fc9709a3 517 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 189:f392fc9709a3 518 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 189:f392fc9709a3 519
AnnaBridge 189:f392fc9709a3 520 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
AnnaBridge 189:f392fc9709a3 521 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
AnnaBridge 189:f392fc9709a3 522
AnnaBridge 189:f392fc9709a3 523 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 189:f392fc9709a3 524 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
AnnaBridge 189:f392fc9709a3 525 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
AnnaBridge 189:f392fc9709a3 526
AnnaBridge 189:f392fc9709a3 527 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 189:f392fc9709a3 528 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 189:f392fc9709a3 529
AnnaBridge 189:f392fc9709a3 530 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
AnnaBridge 189:f392fc9709a3 531 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
AnnaBridge 189:f392fc9709a3 532
AnnaBridge 189:f392fc9709a3 533 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
AnnaBridge 189:f392fc9709a3 534 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
AnnaBridge 189:f392fc9709a3 535
AnnaBridge 189:f392fc9709a3 536 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
AnnaBridge 189:f392fc9709a3 537 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
AnnaBridge 189:f392fc9709a3 538
AnnaBridge 189:f392fc9709a3 539 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
AnnaBridge 189:f392fc9709a3 540 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
AnnaBridge 189:f392fc9709a3 541
AnnaBridge 189:f392fc9709a3 542 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
AnnaBridge 189:f392fc9709a3 543 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
AnnaBridge 189:f392fc9709a3 544
AnnaBridge 189:f392fc9709a3 545 /*@} end of group CMSIS_SCB */
AnnaBridge 189:f392fc9709a3 546
AnnaBridge 189:f392fc9709a3 547
AnnaBridge 189:f392fc9709a3 548 /**
AnnaBridge 189:f392fc9709a3 549 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 550 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 189:f392fc9709a3 551 \brief Type definitions for the System Timer Registers.
AnnaBridge 189:f392fc9709a3 552 @{
AnnaBridge 189:f392fc9709a3 553 */
AnnaBridge 189:f392fc9709a3 554
AnnaBridge 189:f392fc9709a3 555 /**
AnnaBridge 189:f392fc9709a3 556 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 189:f392fc9709a3 557 */
AnnaBridge 189:f392fc9709a3 558 typedef struct
AnnaBridge 189:f392fc9709a3 559 {
AnnaBridge 189:f392fc9709a3 560 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 189:f392fc9709a3 561 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 189:f392fc9709a3 562 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 189:f392fc9709a3 563 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 189:f392fc9709a3 564 } SysTick_Type;
AnnaBridge 189:f392fc9709a3 565
AnnaBridge 189:f392fc9709a3 566 /* SysTick Control / Status Register Definitions */
AnnaBridge 189:f392fc9709a3 567 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 189:f392fc9709a3 568 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 189:f392fc9709a3 569
AnnaBridge 189:f392fc9709a3 570 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 189:f392fc9709a3 571 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 189:f392fc9709a3 572
AnnaBridge 189:f392fc9709a3 573 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 189:f392fc9709a3 574 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 189:f392fc9709a3 575
AnnaBridge 189:f392fc9709a3 576 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 189:f392fc9709a3 577 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 189:f392fc9709a3 578
AnnaBridge 189:f392fc9709a3 579 /* SysTick Reload Register Definitions */
AnnaBridge 189:f392fc9709a3 580 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 189:f392fc9709a3 581 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 189:f392fc9709a3 582
AnnaBridge 189:f392fc9709a3 583 /* SysTick Current Register Definitions */
AnnaBridge 189:f392fc9709a3 584 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 189:f392fc9709a3 585 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 189:f392fc9709a3 586
AnnaBridge 189:f392fc9709a3 587 /* SysTick Calibration Register Definitions */
AnnaBridge 189:f392fc9709a3 588 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 189:f392fc9709a3 589 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 189:f392fc9709a3 590
AnnaBridge 189:f392fc9709a3 591 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 189:f392fc9709a3 592 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 189:f392fc9709a3 593
AnnaBridge 189:f392fc9709a3 594 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 189:f392fc9709a3 595 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 189:f392fc9709a3 596
AnnaBridge 189:f392fc9709a3 597 /*@} end of group CMSIS_SysTick */
AnnaBridge 189:f392fc9709a3 598
AnnaBridge 189:f392fc9709a3 599
AnnaBridge 189:f392fc9709a3 600 /**
AnnaBridge 189:f392fc9709a3 601 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 602 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 189:f392fc9709a3 603 \brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge 189:f392fc9709a3 604 @{
AnnaBridge 189:f392fc9709a3 605 */
AnnaBridge 189:f392fc9709a3 606
AnnaBridge 189:f392fc9709a3 607 /**
AnnaBridge 189:f392fc9709a3 608 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge 189:f392fc9709a3 609 */
AnnaBridge 189:f392fc9709a3 610 typedef struct
AnnaBridge 189:f392fc9709a3 611 {
AnnaBridge 189:f392fc9709a3 612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 189:f392fc9709a3 613 uint32_t RESERVED0[6U];
AnnaBridge 189:f392fc9709a3 614 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 189:f392fc9709a3 615 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 189:f392fc9709a3 616 uint32_t RESERVED1[1U];
AnnaBridge 189:f392fc9709a3 617 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 189:f392fc9709a3 618 uint32_t RESERVED2[1U];
AnnaBridge 189:f392fc9709a3 619 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 189:f392fc9709a3 620 uint32_t RESERVED3[1U];
AnnaBridge 189:f392fc9709a3 621 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 189:f392fc9709a3 622 uint32_t RESERVED4[1U];
AnnaBridge 189:f392fc9709a3 623 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 189:f392fc9709a3 624 uint32_t RESERVED5[1U];
AnnaBridge 189:f392fc9709a3 625 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 189:f392fc9709a3 626 uint32_t RESERVED6[1U];
AnnaBridge 189:f392fc9709a3 627 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 189:f392fc9709a3 628 uint32_t RESERVED7[1U];
AnnaBridge 189:f392fc9709a3 629 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
AnnaBridge 189:f392fc9709a3 630 uint32_t RESERVED8[1U];
AnnaBridge 189:f392fc9709a3 631 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
AnnaBridge 189:f392fc9709a3 632 uint32_t RESERVED9[1U];
AnnaBridge 189:f392fc9709a3 633 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
AnnaBridge 189:f392fc9709a3 634 uint32_t RESERVED10[1U];
AnnaBridge 189:f392fc9709a3 635 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
AnnaBridge 189:f392fc9709a3 636 uint32_t RESERVED11[1U];
AnnaBridge 189:f392fc9709a3 637 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
AnnaBridge 189:f392fc9709a3 638 uint32_t RESERVED12[1U];
AnnaBridge 189:f392fc9709a3 639 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
AnnaBridge 189:f392fc9709a3 640 uint32_t RESERVED13[1U];
AnnaBridge 189:f392fc9709a3 641 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
AnnaBridge 189:f392fc9709a3 642 uint32_t RESERVED14[1U];
AnnaBridge 189:f392fc9709a3 643 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
AnnaBridge 189:f392fc9709a3 644 uint32_t RESERVED15[1U];
AnnaBridge 189:f392fc9709a3 645 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
AnnaBridge 189:f392fc9709a3 646 uint32_t RESERVED16[1U];
AnnaBridge 189:f392fc9709a3 647 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
AnnaBridge 189:f392fc9709a3 648 uint32_t RESERVED17[1U];
AnnaBridge 189:f392fc9709a3 649 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
AnnaBridge 189:f392fc9709a3 650 uint32_t RESERVED18[1U];
AnnaBridge 189:f392fc9709a3 651 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
AnnaBridge 189:f392fc9709a3 652 uint32_t RESERVED19[1U];
AnnaBridge 189:f392fc9709a3 653 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
AnnaBridge 189:f392fc9709a3 654 uint32_t RESERVED20[1U];
AnnaBridge 189:f392fc9709a3 655 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
AnnaBridge 189:f392fc9709a3 656 uint32_t RESERVED21[1U];
AnnaBridge 189:f392fc9709a3 657 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
AnnaBridge 189:f392fc9709a3 658 uint32_t RESERVED22[1U];
AnnaBridge 189:f392fc9709a3 659 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
AnnaBridge 189:f392fc9709a3 660 uint32_t RESERVED23[1U];
AnnaBridge 189:f392fc9709a3 661 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
AnnaBridge 189:f392fc9709a3 662 uint32_t RESERVED24[1U];
AnnaBridge 189:f392fc9709a3 663 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
AnnaBridge 189:f392fc9709a3 664 uint32_t RESERVED25[1U];
AnnaBridge 189:f392fc9709a3 665 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
AnnaBridge 189:f392fc9709a3 666 uint32_t RESERVED26[1U];
AnnaBridge 189:f392fc9709a3 667 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
AnnaBridge 189:f392fc9709a3 668 uint32_t RESERVED27[1U];
AnnaBridge 189:f392fc9709a3 669 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
AnnaBridge 189:f392fc9709a3 670 uint32_t RESERVED28[1U];
AnnaBridge 189:f392fc9709a3 671 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
AnnaBridge 189:f392fc9709a3 672 uint32_t RESERVED29[1U];
AnnaBridge 189:f392fc9709a3 673 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
AnnaBridge 189:f392fc9709a3 674 uint32_t RESERVED30[1U];
AnnaBridge 189:f392fc9709a3 675 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
AnnaBridge 189:f392fc9709a3 676 uint32_t RESERVED31[1U];
AnnaBridge 189:f392fc9709a3 677 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
AnnaBridge 189:f392fc9709a3 678 } DWT_Type;
AnnaBridge 189:f392fc9709a3 679
AnnaBridge 189:f392fc9709a3 680 /* DWT Control Register Definitions */
AnnaBridge 189:f392fc9709a3 681 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
AnnaBridge 189:f392fc9709a3 682 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
AnnaBridge 189:f392fc9709a3 683
AnnaBridge 189:f392fc9709a3 684 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
AnnaBridge 189:f392fc9709a3 685 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
AnnaBridge 189:f392fc9709a3 686
AnnaBridge 189:f392fc9709a3 687 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
AnnaBridge 189:f392fc9709a3 688 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
AnnaBridge 189:f392fc9709a3 689
AnnaBridge 189:f392fc9709a3 690 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
AnnaBridge 189:f392fc9709a3 691 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
AnnaBridge 189:f392fc9709a3 692
AnnaBridge 189:f392fc9709a3 693 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
AnnaBridge 189:f392fc9709a3 694 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
AnnaBridge 189:f392fc9709a3 695
AnnaBridge 189:f392fc9709a3 696 /* DWT Comparator Function Register Definitions */
AnnaBridge 189:f392fc9709a3 697 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
AnnaBridge 189:f392fc9709a3 698 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
AnnaBridge 189:f392fc9709a3 699
AnnaBridge 189:f392fc9709a3 700 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
AnnaBridge 189:f392fc9709a3 701 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
AnnaBridge 189:f392fc9709a3 702
AnnaBridge 189:f392fc9709a3 703 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
AnnaBridge 189:f392fc9709a3 704 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
AnnaBridge 189:f392fc9709a3 705
AnnaBridge 189:f392fc9709a3 706 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
AnnaBridge 189:f392fc9709a3 707 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
AnnaBridge 189:f392fc9709a3 708
AnnaBridge 189:f392fc9709a3 709 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
AnnaBridge 189:f392fc9709a3 710 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
AnnaBridge 189:f392fc9709a3 711
AnnaBridge 189:f392fc9709a3 712 /*@}*/ /* end of group CMSIS_DWT */
AnnaBridge 189:f392fc9709a3 713
AnnaBridge 189:f392fc9709a3 714
AnnaBridge 189:f392fc9709a3 715 /**
AnnaBridge 189:f392fc9709a3 716 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 717 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 189:f392fc9709a3 718 \brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge 189:f392fc9709a3 719 @{
AnnaBridge 189:f392fc9709a3 720 */
AnnaBridge 189:f392fc9709a3 721
AnnaBridge 189:f392fc9709a3 722 /**
AnnaBridge 189:f392fc9709a3 723 \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge 189:f392fc9709a3 724 */
AnnaBridge 189:f392fc9709a3 725 typedef struct
AnnaBridge 189:f392fc9709a3 726 {
AnnaBridge 189:f392fc9709a3 727 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
AnnaBridge 189:f392fc9709a3 728 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
AnnaBridge 189:f392fc9709a3 729 uint32_t RESERVED0[2U];
AnnaBridge 189:f392fc9709a3 730 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 189:f392fc9709a3 731 uint32_t RESERVED1[55U];
AnnaBridge 189:f392fc9709a3 732 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 189:f392fc9709a3 733 uint32_t RESERVED2[131U];
AnnaBridge 189:f392fc9709a3 734 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 189:f392fc9709a3 735 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 189:f392fc9709a3 736 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
AnnaBridge 189:f392fc9709a3 737 uint32_t RESERVED3[809U];
AnnaBridge 189:f392fc9709a3 738 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
AnnaBridge 189:f392fc9709a3 739 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
AnnaBridge 189:f392fc9709a3 740 uint32_t RESERVED4[4U];
AnnaBridge 189:f392fc9709a3 741 __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
AnnaBridge 189:f392fc9709a3 742 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
AnnaBridge 189:f392fc9709a3 743 } TPI_Type;
AnnaBridge 189:f392fc9709a3 744
AnnaBridge 189:f392fc9709a3 745 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 189:f392fc9709a3 746 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
AnnaBridge 189:f392fc9709a3 747 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
AnnaBridge 189:f392fc9709a3 748
AnnaBridge 189:f392fc9709a3 749 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 189:f392fc9709a3 750 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
AnnaBridge 189:f392fc9709a3 751 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
AnnaBridge 189:f392fc9709a3 752
AnnaBridge 189:f392fc9709a3 753 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 189:f392fc9709a3 754 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
AnnaBridge 189:f392fc9709a3 755 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
AnnaBridge 189:f392fc9709a3 756
AnnaBridge 189:f392fc9709a3 757 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
AnnaBridge 189:f392fc9709a3 758 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
AnnaBridge 189:f392fc9709a3 759
AnnaBridge 189:f392fc9709a3 760 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
AnnaBridge 189:f392fc9709a3 761 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
AnnaBridge 189:f392fc9709a3 762
AnnaBridge 189:f392fc9709a3 763 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
AnnaBridge 189:f392fc9709a3 764 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
AnnaBridge 189:f392fc9709a3 765
AnnaBridge 189:f392fc9709a3 766 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 189:f392fc9709a3 767 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
AnnaBridge 189:f392fc9709a3 768 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
AnnaBridge 189:f392fc9709a3 769
AnnaBridge 189:f392fc9709a3 770 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
AnnaBridge 189:f392fc9709a3 771 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
AnnaBridge 189:f392fc9709a3 772
AnnaBridge 189:f392fc9709a3 773 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
AnnaBridge 189:f392fc9709a3 774 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
AnnaBridge 189:f392fc9709a3 775
AnnaBridge 189:f392fc9709a3 776 /* TPI Periodic Synchronization Control Register Definitions */
AnnaBridge 189:f392fc9709a3 777 #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
AnnaBridge 189:f392fc9709a3 778 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
AnnaBridge 189:f392fc9709a3 779
AnnaBridge 189:f392fc9709a3 780 /* TPI Software Lock Status Register Definitions */
AnnaBridge 189:f392fc9709a3 781 #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
AnnaBridge 189:f392fc9709a3 782 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
AnnaBridge 189:f392fc9709a3 783
AnnaBridge 189:f392fc9709a3 784 #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
AnnaBridge 189:f392fc9709a3 785 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
AnnaBridge 189:f392fc9709a3 786
AnnaBridge 189:f392fc9709a3 787 #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
AnnaBridge 189:f392fc9709a3 788 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
AnnaBridge 189:f392fc9709a3 789
AnnaBridge 189:f392fc9709a3 790 /* TPI DEVID Register Definitions */
AnnaBridge 189:f392fc9709a3 791 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
AnnaBridge 189:f392fc9709a3 792 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
AnnaBridge 189:f392fc9709a3 793
AnnaBridge 189:f392fc9709a3 794 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
AnnaBridge 189:f392fc9709a3 795 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
AnnaBridge 189:f392fc9709a3 796
AnnaBridge 189:f392fc9709a3 797 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
AnnaBridge 189:f392fc9709a3 798 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
AnnaBridge 189:f392fc9709a3 799
AnnaBridge 189:f392fc9709a3 800 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
AnnaBridge 189:f392fc9709a3 801 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
AnnaBridge 189:f392fc9709a3 802
AnnaBridge 189:f392fc9709a3 803 /* TPI DEVTYPE Register Definitions */
AnnaBridge 189:f392fc9709a3 804 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 189:f392fc9709a3 805 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
AnnaBridge 189:f392fc9709a3 806
AnnaBridge 189:f392fc9709a3 807 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 189:f392fc9709a3 808 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
AnnaBridge 189:f392fc9709a3 809
AnnaBridge 189:f392fc9709a3 810 /*@}*/ /* end of group CMSIS_TPI */
AnnaBridge 189:f392fc9709a3 811
AnnaBridge 189:f392fc9709a3 812
AnnaBridge 189:f392fc9709a3 813 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 814 /**
AnnaBridge 189:f392fc9709a3 815 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 816 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 189:f392fc9709a3 817 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 189:f392fc9709a3 818 @{
AnnaBridge 189:f392fc9709a3 819 */
AnnaBridge 189:f392fc9709a3 820
AnnaBridge 189:f392fc9709a3 821 /**
AnnaBridge 189:f392fc9709a3 822 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 189:f392fc9709a3 823 */
AnnaBridge 189:f392fc9709a3 824 typedef struct
AnnaBridge 189:f392fc9709a3 825 {
AnnaBridge 189:f392fc9709a3 826 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 189:f392fc9709a3 827 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 189:f392fc9709a3 828 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
AnnaBridge 189:f392fc9709a3 829 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 189:f392fc9709a3 830 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
AnnaBridge 189:f392fc9709a3 831 uint32_t RESERVED0[7U];
AnnaBridge 189:f392fc9709a3 832 union {
AnnaBridge 189:f392fc9709a3 833 __IOM uint32_t MAIR[2];
AnnaBridge 189:f392fc9709a3 834 struct {
AnnaBridge 189:f392fc9709a3 835 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
AnnaBridge 189:f392fc9709a3 836 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
AnnaBridge 189:f392fc9709a3 837 };
AnnaBridge 189:f392fc9709a3 838 };
AnnaBridge 189:f392fc9709a3 839 } MPU_Type;
AnnaBridge 189:f392fc9709a3 840
AnnaBridge 189:f392fc9709a3 841 #define MPU_TYPE_RALIASES 1U
AnnaBridge 189:f392fc9709a3 842
AnnaBridge 189:f392fc9709a3 843 /* MPU Type Register Definitions */
AnnaBridge 189:f392fc9709a3 844 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 189:f392fc9709a3 845 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 189:f392fc9709a3 846
AnnaBridge 189:f392fc9709a3 847 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 189:f392fc9709a3 848 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 189:f392fc9709a3 849
AnnaBridge 189:f392fc9709a3 850 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 189:f392fc9709a3 851 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 189:f392fc9709a3 852
AnnaBridge 189:f392fc9709a3 853 /* MPU Control Register Definitions */
AnnaBridge 189:f392fc9709a3 854 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 189:f392fc9709a3 855 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 189:f392fc9709a3 856
AnnaBridge 189:f392fc9709a3 857 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 189:f392fc9709a3 858 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 189:f392fc9709a3 859
AnnaBridge 189:f392fc9709a3 860 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 189:f392fc9709a3 861 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 189:f392fc9709a3 862
AnnaBridge 189:f392fc9709a3 863 /* MPU Region Number Register Definitions */
AnnaBridge 189:f392fc9709a3 864 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 189:f392fc9709a3 865 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 189:f392fc9709a3 866
AnnaBridge 189:f392fc9709a3 867 /* MPU Region Base Address Register Definitions */
AnnaBridge 189:f392fc9709a3 868 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
AnnaBridge 189:f392fc9709a3 869 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
AnnaBridge 189:f392fc9709a3 870
AnnaBridge 189:f392fc9709a3 871 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
AnnaBridge 189:f392fc9709a3 872 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
AnnaBridge 189:f392fc9709a3 873
AnnaBridge 189:f392fc9709a3 874 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
AnnaBridge 189:f392fc9709a3 875 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
AnnaBridge 189:f392fc9709a3 876
AnnaBridge 189:f392fc9709a3 877 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
AnnaBridge 189:f392fc9709a3 878 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
AnnaBridge 189:f392fc9709a3 879
AnnaBridge 189:f392fc9709a3 880 /* MPU Region Limit Address Register Definitions */
AnnaBridge 189:f392fc9709a3 881 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
AnnaBridge 189:f392fc9709a3 882 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
AnnaBridge 189:f392fc9709a3 883
AnnaBridge 189:f392fc9709a3 884 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
AnnaBridge 189:f392fc9709a3 885 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
AnnaBridge 189:f392fc9709a3 886
AnnaBridge 189:f392fc9709a3 887 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
AnnaBridge 189:f392fc9709a3 888 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
AnnaBridge 189:f392fc9709a3 889
AnnaBridge 189:f392fc9709a3 890 /* MPU Memory Attribute Indirection Register 0 Definitions */
AnnaBridge 189:f392fc9709a3 891 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
AnnaBridge 189:f392fc9709a3 892 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
AnnaBridge 189:f392fc9709a3 893
AnnaBridge 189:f392fc9709a3 894 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
AnnaBridge 189:f392fc9709a3 895 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
AnnaBridge 189:f392fc9709a3 896
AnnaBridge 189:f392fc9709a3 897 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
AnnaBridge 189:f392fc9709a3 898 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
AnnaBridge 189:f392fc9709a3 899
AnnaBridge 189:f392fc9709a3 900 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
AnnaBridge 189:f392fc9709a3 901 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
AnnaBridge 189:f392fc9709a3 902
AnnaBridge 189:f392fc9709a3 903 /* MPU Memory Attribute Indirection Register 1 Definitions */
AnnaBridge 189:f392fc9709a3 904 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
AnnaBridge 189:f392fc9709a3 905 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
AnnaBridge 189:f392fc9709a3 906
AnnaBridge 189:f392fc9709a3 907 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
AnnaBridge 189:f392fc9709a3 908 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
AnnaBridge 189:f392fc9709a3 909
AnnaBridge 189:f392fc9709a3 910 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
AnnaBridge 189:f392fc9709a3 911 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
AnnaBridge 189:f392fc9709a3 912
AnnaBridge 189:f392fc9709a3 913 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
AnnaBridge 189:f392fc9709a3 914 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
AnnaBridge 189:f392fc9709a3 915
AnnaBridge 189:f392fc9709a3 916 /*@} end of group CMSIS_MPU */
AnnaBridge 189:f392fc9709a3 917 #endif
AnnaBridge 189:f392fc9709a3 918
AnnaBridge 189:f392fc9709a3 919
AnnaBridge 189:f392fc9709a3 920 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 189:f392fc9709a3 921 /**
AnnaBridge 189:f392fc9709a3 922 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 923 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
AnnaBridge 189:f392fc9709a3 924 \brief Type definitions for the Security Attribution Unit (SAU)
AnnaBridge 189:f392fc9709a3 925 @{
AnnaBridge 189:f392fc9709a3 926 */
AnnaBridge 189:f392fc9709a3 927
AnnaBridge 189:f392fc9709a3 928 /**
AnnaBridge 189:f392fc9709a3 929 \brief Structure type to access the Security Attribution Unit (SAU).
AnnaBridge 189:f392fc9709a3 930 */
AnnaBridge 189:f392fc9709a3 931 typedef struct
AnnaBridge 189:f392fc9709a3 932 {
AnnaBridge 189:f392fc9709a3 933 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
AnnaBridge 189:f392fc9709a3 934 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
AnnaBridge 189:f392fc9709a3 935 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 936 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
AnnaBridge 189:f392fc9709a3 937 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
AnnaBridge 189:f392fc9709a3 938 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
AnnaBridge 189:f392fc9709a3 939 #endif
AnnaBridge 189:f392fc9709a3 940 } SAU_Type;
AnnaBridge 189:f392fc9709a3 941
AnnaBridge 189:f392fc9709a3 942 /* SAU Control Register Definitions */
AnnaBridge 189:f392fc9709a3 943 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
AnnaBridge 189:f392fc9709a3 944 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
AnnaBridge 189:f392fc9709a3 945
AnnaBridge 189:f392fc9709a3 946 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
AnnaBridge 189:f392fc9709a3 947 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
AnnaBridge 189:f392fc9709a3 948
AnnaBridge 189:f392fc9709a3 949 /* SAU Type Register Definitions */
AnnaBridge 189:f392fc9709a3 950 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
AnnaBridge 189:f392fc9709a3 951 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
AnnaBridge 189:f392fc9709a3 952
AnnaBridge 189:f392fc9709a3 953 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 954 /* SAU Region Number Register Definitions */
AnnaBridge 189:f392fc9709a3 955 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
AnnaBridge 189:f392fc9709a3 956 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
AnnaBridge 189:f392fc9709a3 957
AnnaBridge 189:f392fc9709a3 958 /* SAU Region Base Address Register Definitions */
AnnaBridge 189:f392fc9709a3 959 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
AnnaBridge 189:f392fc9709a3 960 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
AnnaBridge 189:f392fc9709a3 961
AnnaBridge 189:f392fc9709a3 962 /* SAU Region Limit Address Register Definitions */
AnnaBridge 189:f392fc9709a3 963 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
AnnaBridge 189:f392fc9709a3 964 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
AnnaBridge 189:f392fc9709a3 965
AnnaBridge 189:f392fc9709a3 966 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
AnnaBridge 189:f392fc9709a3 967 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
AnnaBridge 189:f392fc9709a3 968
AnnaBridge 189:f392fc9709a3 969 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
AnnaBridge 189:f392fc9709a3 970 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
AnnaBridge 189:f392fc9709a3 971
AnnaBridge 189:f392fc9709a3 972 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
AnnaBridge 189:f392fc9709a3 973
AnnaBridge 189:f392fc9709a3 974 /*@} end of group CMSIS_SAU */
AnnaBridge 189:f392fc9709a3 975 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 189:f392fc9709a3 976
AnnaBridge 189:f392fc9709a3 977
AnnaBridge 189:f392fc9709a3 978 /**
AnnaBridge 189:f392fc9709a3 979 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 980 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 189:f392fc9709a3 981 \brief Type definitions for the Core Debug Registers
AnnaBridge 189:f392fc9709a3 982 @{
AnnaBridge 189:f392fc9709a3 983 */
AnnaBridge 189:f392fc9709a3 984
AnnaBridge 189:f392fc9709a3 985 /**
AnnaBridge 189:f392fc9709a3 986 \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge 189:f392fc9709a3 987 */
AnnaBridge 189:f392fc9709a3 988 typedef struct
AnnaBridge 189:f392fc9709a3 989 {
AnnaBridge 189:f392fc9709a3 990 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 189:f392fc9709a3 991 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 189:f392fc9709a3 992 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 189:f392fc9709a3 993 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
AnnaBridge 189:f392fc9709a3 994 uint32_t RESERVED4[1U];
AnnaBridge 189:f392fc9709a3 995 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
AnnaBridge 189:f392fc9709a3 996 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
AnnaBridge 189:f392fc9709a3 997 } CoreDebug_Type;
AnnaBridge 189:f392fc9709a3 998
AnnaBridge 189:f392fc9709a3 999 /* Debug Halting Control and Status Register Definitions */
AnnaBridge 189:f392fc9709a3 1000 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
AnnaBridge 189:f392fc9709a3 1001 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
AnnaBridge 189:f392fc9709a3 1002
AnnaBridge 189:f392fc9709a3 1003 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
AnnaBridge 189:f392fc9709a3 1004 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
AnnaBridge 189:f392fc9709a3 1005
AnnaBridge 189:f392fc9709a3 1006 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
AnnaBridge 189:f392fc9709a3 1007 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
AnnaBridge 189:f392fc9709a3 1008
AnnaBridge 189:f392fc9709a3 1009 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
AnnaBridge 189:f392fc9709a3 1010 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
AnnaBridge 189:f392fc9709a3 1011
AnnaBridge 189:f392fc9709a3 1012 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
AnnaBridge 189:f392fc9709a3 1013 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
AnnaBridge 189:f392fc9709a3 1014
AnnaBridge 189:f392fc9709a3 1015 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
AnnaBridge 189:f392fc9709a3 1016 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
AnnaBridge 189:f392fc9709a3 1017
AnnaBridge 189:f392fc9709a3 1018 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
AnnaBridge 189:f392fc9709a3 1019 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
AnnaBridge 189:f392fc9709a3 1020
AnnaBridge 189:f392fc9709a3 1021 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
AnnaBridge 189:f392fc9709a3 1022 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
AnnaBridge 189:f392fc9709a3 1023
AnnaBridge 189:f392fc9709a3 1024 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
AnnaBridge 189:f392fc9709a3 1025 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
AnnaBridge 189:f392fc9709a3 1026
AnnaBridge 189:f392fc9709a3 1027 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
AnnaBridge 189:f392fc9709a3 1028 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
AnnaBridge 189:f392fc9709a3 1029
AnnaBridge 189:f392fc9709a3 1030 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
AnnaBridge 189:f392fc9709a3 1031 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
AnnaBridge 189:f392fc9709a3 1032
AnnaBridge 189:f392fc9709a3 1033 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
AnnaBridge 189:f392fc9709a3 1034 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
AnnaBridge 189:f392fc9709a3 1035
AnnaBridge 189:f392fc9709a3 1036 /* Debug Core Register Selector Register Definitions */
AnnaBridge 189:f392fc9709a3 1037 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
AnnaBridge 189:f392fc9709a3 1038 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
AnnaBridge 189:f392fc9709a3 1039
AnnaBridge 189:f392fc9709a3 1040 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
AnnaBridge 189:f392fc9709a3 1041 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
AnnaBridge 189:f392fc9709a3 1042
AnnaBridge 189:f392fc9709a3 1043 /* Debug Exception and Monitor Control Register */
AnnaBridge 189:f392fc9709a3 1044 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
AnnaBridge 189:f392fc9709a3 1045 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
AnnaBridge 189:f392fc9709a3 1046
AnnaBridge 189:f392fc9709a3 1047 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
AnnaBridge 189:f392fc9709a3 1048 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
AnnaBridge 189:f392fc9709a3 1049
AnnaBridge 189:f392fc9709a3 1050 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
AnnaBridge 189:f392fc9709a3 1051 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
AnnaBridge 189:f392fc9709a3 1052
AnnaBridge 189:f392fc9709a3 1053 /* Debug Authentication Control Register Definitions */
AnnaBridge 189:f392fc9709a3 1054 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
AnnaBridge 189:f392fc9709a3 1055 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
AnnaBridge 189:f392fc9709a3 1056
AnnaBridge 189:f392fc9709a3 1057 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
AnnaBridge 189:f392fc9709a3 1058 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
AnnaBridge 189:f392fc9709a3 1059
AnnaBridge 189:f392fc9709a3 1060 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
AnnaBridge 189:f392fc9709a3 1061 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
AnnaBridge 189:f392fc9709a3 1062
AnnaBridge 189:f392fc9709a3 1063 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
AnnaBridge 189:f392fc9709a3 1064 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
AnnaBridge 189:f392fc9709a3 1065
AnnaBridge 189:f392fc9709a3 1066 /* Debug Security Control and Status Register Definitions */
AnnaBridge 189:f392fc9709a3 1067 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
AnnaBridge 189:f392fc9709a3 1068 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
AnnaBridge 189:f392fc9709a3 1069
AnnaBridge 189:f392fc9709a3 1070 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
AnnaBridge 189:f392fc9709a3 1071 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
AnnaBridge 189:f392fc9709a3 1072
AnnaBridge 189:f392fc9709a3 1073 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
AnnaBridge 189:f392fc9709a3 1074 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
AnnaBridge 189:f392fc9709a3 1075
AnnaBridge 189:f392fc9709a3 1076 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 189:f392fc9709a3 1077
AnnaBridge 189:f392fc9709a3 1078
AnnaBridge 189:f392fc9709a3 1079 /**
AnnaBridge 189:f392fc9709a3 1080 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 1081 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 189:f392fc9709a3 1082 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 189:f392fc9709a3 1083 @{
AnnaBridge 189:f392fc9709a3 1084 */
AnnaBridge 189:f392fc9709a3 1085
AnnaBridge 189:f392fc9709a3 1086 /**
AnnaBridge 189:f392fc9709a3 1087 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 189:f392fc9709a3 1088 \param[in] field Name of the register bit field.
AnnaBridge 189:f392fc9709a3 1089 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 189:f392fc9709a3 1090 \return Masked and shifted value.
AnnaBridge 189:f392fc9709a3 1091 */
AnnaBridge 189:f392fc9709a3 1092 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 189:f392fc9709a3 1093
AnnaBridge 189:f392fc9709a3 1094 /**
AnnaBridge 189:f392fc9709a3 1095 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 189:f392fc9709a3 1096 \param[in] field Name of the register bit field.
AnnaBridge 189:f392fc9709a3 1097 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 189:f392fc9709a3 1098 \return Masked and shifted bit field value.
AnnaBridge 189:f392fc9709a3 1099 */
AnnaBridge 189:f392fc9709a3 1100 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 189:f392fc9709a3 1101
AnnaBridge 189:f392fc9709a3 1102 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 189:f392fc9709a3 1103
AnnaBridge 189:f392fc9709a3 1104
AnnaBridge 189:f392fc9709a3 1105 /**
AnnaBridge 189:f392fc9709a3 1106 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 1107 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 189:f392fc9709a3 1108 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 189:f392fc9709a3 1109 @{
AnnaBridge 189:f392fc9709a3 1110 */
AnnaBridge 189:f392fc9709a3 1111
AnnaBridge 189:f392fc9709a3 1112 /* Memory mapping of Core Hardware */
AnnaBridge 189:f392fc9709a3 1113 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 189:f392fc9709a3 1114 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 189:f392fc9709a3 1115 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 189:f392fc9709a3 1116 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 189:f392fc9709a3 1117 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 189:f392fc9709a3 1118 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 189:f392fc9709a3 1119 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 189:f392fc9709a3 1120
AnnaBridge 189:f392fc9709a3 1121
AnnaBridge 189:f392fc9709a3 1122 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 189:f392fc9709a3 1123 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 189:f392fc9709a3 1124 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 189:f392fc9709a3 1125 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 189:f392fc9709a3 1126 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 189:f392fc9709a3 1127 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
AnnaBridge 189:f392fc9709a3 1128
AnnaBridge 189:f392fc9709a3 1129 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 1130 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 189:f392fc9709a3 1131 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 189:f392fc9709a3 1132 #endif
AnnaBridge 189:f392fc9709a3 1133
AnnaBridge 189:f392fc9709a3 1134 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 189:f392fc9709a3 1135 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
AnnaBridge 189:f392fc9709a3 1136 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
AnnaBridge 189:f392fc9709a3 1137 #endif
AnnaBridge 189:f392fc9709a3 1138
AnnaBridge 189:f392fc9709a3 1139 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 189:f392fc9709a3 1140 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
AnnaBridge 189:f392fc9709a3 1141 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
AnnaBridge 189:f392fc9709a3 1142 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
AnnaBridge 189:f392fc9709a3 1143 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
AnnaBridge 189:f392fc9709a3 1144 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
AnnaBridge 189:f392fc9709a3 1145
AnnaBridge 189:f392fc9709a3 1146 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
AnnaBridge 189:f392fc9709a3 1147 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
AnnaBridge 189:f392fc9709a3 1148 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
AnnaBridge 189:f392fc9709a3 1149 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
AnnaBridge 189:f392fc9709a3 1150
AnnaBridge 189:f392fc9709a3 1151 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 1152 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
AnnaBridge 189:f392fc9709a3 1153 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
AnnaBridge 189:f392fc9709a3 1154 #endif
AnnaBridge 189:f392fc9709a3 1155
AnnaBridge 189:f392fc9709a3 1156 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 189:f392fc9709a3 1157 /*@} */
AnnaBridge 189:f392fc9709a3 1158
AnnaBridge 189:f392fc9709a3 1159
AnnaBridge 189:f392fc9709a3 1160
AnnaBridge 189:f392fc9709a3 1161 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 1162 * Hardware Abstraction Layer
AnnaBridge 189:f392fc9709a3 1163 Core Function Interface contains:
AnnaBridge 189:f392fc9709a3 1164 - Core NVIC Functions
AnnaBridge 189:f392fc9709a3 1165 - Core SysTick Functions
AnnaBridge 189:f392fc9709a3 1166 - Core Register Access Functions
AnnaBridge 189:f392fc9709a3 1167 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 1168 /**
AnnaBridge 189:f392fc9709a3 1169 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 189:f392fc9709a3 1170 */
AnnaBridge 189:f392fc9709a3 1171
AnnaBridge 189:f392fc9709a3 1172
AnnaBridge 189:f392fc9709a3 1173
AnnaBridge 189:f392fc9709a3 1174 /* ########################## NVIC functions #################################### */
AnnaBridge 189:f392fc9709a3 1175 /**
AnnaBridge 189:f392fc9709a3 1176 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 189:f392fc9709a3 1177 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 189:f392fc9709a3 1178 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 189:f392fc9709a3 1179 @{
AnnaBridge 189:f392fc9709a3 1180 */
AnnaBridge 189:f392fc9709a3 1181
AnnaBridge 189:f392fc9709a3 1182 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 189:f392fc9709a3 1183 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 189:f392fc9709a3 1184 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 189:f392fc9709a3 1185 #endif
AnnaBridge 189:f392fc9709a3 1186 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 189:f392fc9709a3 1187 #else
AnnaBridge 189:f392fc9709a3 1188 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge 189:f392fc9709a3 1189 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge 189:f392fc9709a3 1190 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 189:f392fc9709a3 1191 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 189:f392fc9709a3 1192 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 189:f392fc9709a3 1193 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 189:f392fc9709a3 1194 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 189:f392fc9709a3 1195 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 189:f392fc9709a3 1196 #define NVIC_GetActive __NVIC_GetActive
AnnaBridge 189:f392fc9709a3 1197 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 189:f392fc9709a3 1198 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 189:f392fc9709a3 1199 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 189:f392fc9709a3 1200 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 189:f392fc9709a3 1201
AnnaBridge 189:f392fc9709a3 1202 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 189:f392fc9709a3 1203 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 189:f392fc9709a3 1204 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 189:f392fc9709a3 1205 #endif
AnnaBridge 189:f392fc9709a3 1206 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 189:f392fc9709a3 1207 #else
AnnaBridge 189:f392fc9709a3 1208 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 189:f392fc9709a3 1209 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 189:f392fc9709a3 1210 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 189:f392fc9709a3 1211
AnnaBridge 189:f392fc9709a3 1212 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 189:f392fc9709a3 1213
AnnaBridge 189:f392fc9709a3 1214
AnnaBridge 189:f392fc9709a3 1215 /* Special LR values for Secure/Non-Secure call handling and exception handling */
AnnaBridge 189:f392fc9709a3 1216
AnnaBridge 189:f392fc9709a3 1217 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
AnnaBridge 189:f392fc9709a3 1218 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
AnnaBridge 189:f392fc9709a3 1219
AnnaBridge 189:f392fc9709a3 1220 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
AnnaBridge 189:f392fc9709a3 1221 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
AnnaBridge 189:f392fc9709a3 1222 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
AnnaBridge 189:f392fc9709a3 1223 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
AnnaBridge 189:f392fc9709a3 1224 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
AnnaBridge 189:f392fc9709a3 1225 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
AnnaBridge 189:f392fc9709a3 1226 #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
AnnaBridge 189:f392fc9709a3 1227 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
AnnaBridge 189:f392fc9709a3 1228
AnnaBridge 189:f392fc9709a3 1229 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
AnnaBridge 189:f392fc9709a3 1230 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
AnnaBridge 189:f392fc9709a3 1231 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
AnnaBridge 189:f392fc9709a3 1232 #else
AnnaBridge 189:f392fc9709a3 1233 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
AnnaBridge 189:f392fc9709a3 1234 #endif
AnnaBridge 189:f392fc9709a3 1235
AnnaBridge 189:f392fc9709a3 1236
AnnaBridge 189:f392fc9709a3 1237 /* Interrupt Priorities are WORD accessible only under Armv6-M */
AnnaBridge 189:f392fc9709a3 1238 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 189:f392fc9709a3 1239 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 189:f392fc9709a3 1240 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 189:f392fc9709a3 1241 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 189:f392fc9709a3 1242
AnnaBridge 189:f392fc9709a3 1243 #define __NVIC_SetPriorityGrouping(X) (void)(X)
AnnaBridge 189:f392fc9709a3 1244 #define __NVIC_GetPriorityGrouping() (0U)
AnnaBridge 189:f392fc9709a3 1245
AnnaBridge 189:f392fc9709a3 1246 /**
AnnaBridge 189:f392fc9709a3 1247 \brief Enable Interrupt
AnnaBridge 189:f392fc9709a3 1248 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 189:f392fc9709a3 1249 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1250 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1251 */
AnnaBridge 189:f392fc9709a3 1252 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1253 {
AnnaBridge 189:f392fc9709a3 1254 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1255 {
AnnaBridge 189:f392fc9709a3 1256 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 189:f392fc9709a3 1257 }
AnnaBridge 189:f392fc9709a3 1258 }
AnnaBridge 189:f392fc9709a3 1259
AnnaBridge 189:f392fc9709a3 1260
AnnaBridge 189:f392fc9709a3 1261 /**
AnnaBridge 189:f392fc9709a3 1262 \brief Get Interrupt Enable status
AnnaBridge 189:f392fc9709a3 1263 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 189:f392fc9709a3 1264 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1265 \return 0 Interrupt is not enabled.
AnnaBridge 189:f392fc9709a3 1266 \return 1 Interrupt is enabled.
AnnaBridge 189:f392fc9709a3 1267 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1268 */
AnnaBridge 189:f392fc9709a3 1269 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1270 {
AnnaBridge 189:f392fc9709a3 1271 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1272 {
AnnaBridge 189:f392fc9709a3 1273 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 189:f392fc9709a3 1274 }
AnnaBridge 189:f392fc9709a3 1275 else
AnnaBridge 189:f392fc9709a3 1276 {
AnnaBridge 189:f392fc9709a3 1277 return(0U);
AnnaBridge 189:f392fc9709a3 1278 }
AnnaBridge 189:f392fc9709a3 1279 }
AnnaBridge 189:f392fc9709a3 1280
AnnaBridge 189:f392fc9709a3 1281
AnnaBridge 189:f392fc9709a3 1282 /**
AnnaBridge 189:f392fc9709a3 1283 \brief Disable Interrupt
AnnaBridge 189:f392fc9709a3 1284 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 189:f392fc9709a3 1285 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1286 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1287 */
AnnaBridge 189:f392fc9709a3 1288 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1289 {
AnnaBridge 189:f392fc9709a3 1290 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1291 {
AnnaBridge 189:f392fc9709a3 1292 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 189:f392fc9709a3 1293 __DSB();
AnnaBridge 189:f392fc9709a3 1294 __ISB();
AnnaBridge 189:f392fc9709a3 1295 }
AnnaBridge 189:f392fc9709a3 1296 }
AnnaBridge 189:f392fc9709a3 1297
AnnaBridge 189:f392fc9709a3 1298
AnnaBridge 189:f392fc9709a3 1299 /**
AnnaBridge 189:f392fc9709a3 1300 \brief Get Pending Interrupt
AnnaBridge 189:f392fc9709a3 1301 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 189:f392fc9709a3 1302 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1303 \return 0 Interrupt status is not pending.
AnnaBridge 189:f392fc9709a3 1304 \return 1 Interrupt status is pending.
AnnaBridge 189:f392fc9709a3 1305 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1306 */
AnnaBridge 189:f392fc9709a3 1307 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1308 {
AnnaBridge 189:f392fc9709a3 1309 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1310 {
AnnaBridge 189:f392fc9709a3 1311 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 189:f392fc9709a3 1312 }
AnnaBridge 189:f392fc9709a3 1313 else
AnnaBridge 189:f392fc9709a3 1314 {
AnnaBridge 189:f392fc9709a3 1315 return(0U);
AnnaBridge 189:f392fc9709a3 1316 }
AnnaBridge 189:f392fc9709a3 1317 }
AnnaBridge 189:f392fc9709a3 1318
AnnaBridge 189:f392fc9709a3 1319
AnnaBridge 189:f392fc9709a3 1320 /**
AnnaBridge 189:f392fc9709a3 1321 \brief Set Pending Interrupt
AnnaBridge 189:f392fc9709a3 1322 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 189:f392fc9709a3 1323 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1324 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1325 */
AnnaBridge 189:f392fc9709a3 1326 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1327 {
AnnaBridge 189:f392fc9709a3 1328 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1329 {
AnnaBridge 189:f392fc9709a3 1330 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 189:f392fc9709a3 1331 }
AnnaBridge 189:f392fc9709a3 1332 }
AnnaBridge 189:f392fc9709a3 1333
AnnaBridge 189:f392fc9709a3 1334
AnnaBridge 189:f392fc9709a3 1335 /**
AnnaBridge 189:f392fc9709a3 1336 \brief Clear Pending Interrupt
AnnaBridge 189:f392fc9709a3 1337 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 189:f392fc9709a3 1338 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1339 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1340 */
AnnaBridge 189:f392fc9709a3 1341 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1342 {
AnnaBridge 189:f392fc9709a3 1343 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1344 {
AnnaBridge 189:f392fc9709a3 1345 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 189:f392fc9709a3 1346 }
AnnaBridge 189:f392fc9709a3 1347 }
AnnaBridge 189:f392fc9709a3 1348
AnnaBridge 189:f392fc9709a3 1349
AnnaBridge 189:f392fc9709a3 1350 /**
AnnaBridge 189:f392fc9709a3 1351 \brief Get Active Interrupt
AnnaBridge 189:f392fc9709a3 1352 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge 189:f392fc9709a3 1353 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1354 \return 0 Interrupt status is not active.
AnnaBridge 189:f392fc9709a3 1355 \return 1 Interrupt status is active.
AnnaBridge 189:f392fc9709a3 1356 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1357 */
AnnaBridge 189:f392fc9709a3 1358 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1359 {
AnnaBridge 189:f392fc9709a3 1360 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1361 {
AnnaBridge 189:f392fc9709a3 1362 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 189:f392fc9709a3 1363 }
AnnaBridge 189:f392fc9709a3 1364 else
AnnaBridge 189:f392fc9709a3 1365 {
AnnaBridge 189:f392fc9709a3 1366 return(0U);
AnnaBridge 189:f392fc9709a3 1367 }
AnnaBridge 189:f392fc9709a3 1368 }
AnnaBridge 189:f392fc9709a3 1369
AnnaBridge 189:f392fc9709a3 1370
AnnaBridge 189:f392fc9709a3 1371 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 189:f392fc9709a3 1372 /**
AnnaBridge 189:f392fc9709a3 1373 \brief Get Interrupt Target State
AnnaBridge 189:f392fc9709a3 1374 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 189:f392fc9709a3 1375 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1376 \return 0 if interrupt is assigned to Secure
AnnaBridge 189:f392fc9709a3 1377 \return 1 if interrupt is assigned to Non Secure
AnnaBridge 189:f392fc9709a3 1378 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1379 */
AnnaBridge 189:f392fc9709a3 1380 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1381 {
AnnaBridge 189:f392fc9709a3 1382 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1383 {
AnnaBridge 189:f392fc9709a3 1384 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 189:f392fc9709a3 1385 }
AnnaBridge 189:f392fc9709a3 1386 else
AnnaBridge 189:f392fc9709a3 1387 {
AnnaBridge 189:f392fc9709a3 1388 return(0U);
AnnaBridge 189:f392fc9709a3 1389 }
AnnaBridge 189:f392fc9709a3 1390 }
AnnaBridge 189:f392fc9709a3 1391
AnnaBridge 189:f392fc9709a3 1392
AnnaBridge 189:f392fc9709a3 1393 /**
AnnaBridge 189:f392fc9709a3 1394 \brief Set Interrupt Target State
AnnaBridge 189:f392fc9709a3 1395 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 189:f392fc9709a3 1396 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1397 \return 0 if interrupt is assigned to Secure
AnnaBridge 189:f392fc9709a3 1398 1 if interrupt is assigned to Non Secure
AnnaBridge 189:f392fc9709a3 1399 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1400 */
AnnaBridge 189:f392fc9709a3 1401 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1402 {
AnnaBridge 189:f392fc9709a3 1403 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1404 {
AnnaBridge 189:f392fc9709a3 1405 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
AnnaBridge 189:f392fc9709a3 1406 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 189:f392fc9709a3 1407 }
AnnaBridge 189:f392fc9709a3 1408 else
AnnaBridge 189:f392fc9709a3 1409 {
AnnaBridge 189:f392fc9709a3 1410 return(0U);
AnnaBridge 189:f392fc9709a3 1411 }
AnnaBridge 189:f392fc9709a3 1412 }
AnnaBridge 189:f392fc9709a3 1413
AnnaBridge 189:f392fc9709a3 1414
AnnaBridge 189:f392fc9709a3 1415 /**
AnnaBridge 189:f392fc9709a3 1416 \brief Clear Interrupt Target State
AnnaBridge 189:f392fc9709a3 1417 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 189:f392fc9709a3 1418 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1419 \return 0 if interrupt is assigned to Secure
AnnaBridge 189:f392fc9709a3 1420 1 if interrupt is assigned to Non Secure
AnnaBridge 189:f392fc9709a3 1421 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1422 */
AnnaBridge 189:f392fc9709a3 1423 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1424 {
AnnaBridge 189:f392fc9709a3 1425 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1426 {
AnnaBridge 189:f392fc9709a3 1427 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
AnnaBridge 189:f392fc9709a3 1428 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 189:f392fc9709a3 1429 }
AnnaBridge 189:f392fc9709a3 1430 else
AnnaBridge 189:f392fc9709a3 1431 {
AnnaBridge 189:f392fc9709a3 1432 return(0U);
AnnaBridge 189:f392fc9709a3 1433 }
AnnaBridge 189:f392fc9709a3 1434 }
AnnaBridge 189:f392fc9709a3 1435 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 189:f392fc9709a3 1436
AnnaBridge 189:f392fc9709a3 1437
AnnaBridge 189:f392fc9709a3 1438 /**
AnnaBridge 189:f392fc9709a3 1439 \brief Set Interrupt Priority
AnnaBridge 189:f392fc9709a3 1440 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 189:f392fc9709a3 1441 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 189:f392fc9709a3 1442 or negative to specify a processor exception.
AnnaBridge 189:f392fc9709a3 1443 \param [in] IRQn Interrupt number.
AnnaBridge 189:f392fc9709a3 1444 \param [in] priority Priority to set.
AnnaBridge 189:f392fc9709a3 1445 \note The priority cannot be set for every processor exception.
AnnaBridge 189:f392fc9709a3 1446 */
AnnaBridge 189:f392fc9709a3 1447 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 189:f392fc9709a3 1448 {
AnnaBridge 189:f392fc9709a3 1449 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1450 {
AnnaBridge 189:f392fc9709a3 1451 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 189:f392fc9709a3 1452 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 189:f392fc9709a3 1453 }
AnnaBridge 189:f392fc9709a3 1454 else
AnnaBridge 189:f392fc9709a3 1455 {
AnnaBridge 189:f392fc9709a3 1456 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 189:f392fc9709a3 1457 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 189:f392fc9709a3 1458 }
AnnaBridge 189:f392fc9709a3 1459 }
AnnaBridge 189:f392fc9709a3 1460
AnnaBridge 189:f392fc9709a3 1461
AnnaBridge 189:f392fc9709a3 1462 /**
AnnaBridge 189:f392fc9709a3 1463 \brief Get Interrupt Priority
AnnaBridge 189:f392fc9709a3 1464 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 189:f392fc9709a3 1465 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 189:f392fc9709a3 1466 or negative to specify a processor exception.
AnnaBridge 189:f392fc9709a3 1467 \param [in] IRQn Interrupt number.
AnnaBridge 189:f392fc9709a3 1468 \return Interrupt Priority.
AnnaBridge 189:f392fc9709a3 1469 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 189:f392fc9709a3 1470 */
AnnaBridge 189:f392fc9709a3 1471 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1472 {
AnnaBridge 189:f392fc9709a3 1473
AnnaBridge 189:f392fc9709a3 1474 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1475 {
AnnaBridge 189:f392fc9709a3 1476 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 189:f392fc9709a3 1477 }
AnnaBridge 189:f392fc9709a3 1478 else
AnnaBridge 189:f392fc9709a3 1479 {
AnnaBridge 189:f392fc9709a3 1480 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 189:f392fc9709a3 1481 }
AnnaBridge 189:f392fc9709a3 1482 }
AnnaBridge 189:f392fc9709a3 1483
AnnaBridge 189:f392fc9709a3 1484
AnnaBridge 189:f392fc9709a3 1485 /**
AnnaBridge 189:f392fc9709a3 1486 \brief Encode Priority
AnnaBridge 189:f392fc9709a3 1487 \details Encodes the priority for an interrupt with the given priority group,
AnnaBridge 189:f392fc9709a3 1488 preemptive priority value, and subpriority value.
AnnaBridge 189:f392fc9709a3 1489 In case of a conflict between priority grouping and available
AnnaBridge 189:f392fc9709a3 1490 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 189:f392fc9709a3 1491 \param [in] PriorityGroup Used priority group.
AnnaBridge 189:f392fc9709a3 1492 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 189:f392fc9709a3 1493 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 189:f392fc9709a3 1494 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge 189:f392fc9709a3 1495 */
AnnaBridge 189:f392fc9709a3 1496 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge 189:f392fc9709a3 1497 {
AnnaBridge 189:f392fc9709a3 1498 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 189:f392fc9709a3 1499 uint32_t PreemptPriorityBits;
AnnaBridge 189:f392fc9709a3 1500 uint32_t SubPriorityBits;
AnnaBridge 189:f392fc9709a3 1501
AnnaBridge 189:f392fc9709a3 1502 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 189:f392fc9709a3 1503 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 189:f392fc9709a3 1504
AnnaBridge 189:f392fc9709a3 1505 return (
AnnaBridge 189:f392fc9709a3 1506 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
AnnaBridge 189:f392fc9709a3 1507 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge 189:f392fc9709a3 1508 );
AnnaBridge 189:f392fc9709a3 1509 }
AnnaBridge 189:f392fc9709a3 1510
AnnaBridge 189:f392fc9709a3 1511
AnnaBridge 189:f392fc9709a3 1512 /**
AnnaBridge 189:f392fc9709a3 1513 \brief Decode Priority
AnnaBridge 189:f392fc9709a3 1514 \details Decodes an interrupt priority value with a given priority group to
AnnaBridge 189:f392fc9709a3 1515 preemptive priority value and subpriority value.
AnnaBridge 189:f392fc9709a3 1516 In case of a conflict between priority grouping and available
AnnaBridge 189:f392fc9709a3 1517 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 189:f392fc9709a3 1518 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 189:f392fc9709a3 1519 \param [in] PriorityGroup Used priority group.
AnnaBridge 189:f392fc9709a3 1520 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 189:f392fc9709a3 1521 \param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge 189:f392fc9709a3 1522 */
AnnaBridge 189:f392fc9709a3 1523 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge 189:f392fc9709a3 1524 {
AnnaBridge 189:f392fc9709a3 1525 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 189:f392fc9709a3 1526 uint32_t PreemptPriorityBits;
AnnaBridge 189:f392fc9709a3 1527 uint32_t SubPriorityBits;
AnnaBridge 189:f392fc9709a3 1528
AnnaBridge 189:f392fc9709a3 1529 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 189:f392fc9709a3 1530 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 189:f392fc9709a3 1531
AnnaBridge 189:f392fc9709a3 1532 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge 189:f392fc9709a3 1533 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge 189:f392fc9709a3 1534 }
AnnaBridge 189:f392fc9709a3 1535
AnnaBridge 189:f392fc9709a3 1536
AnnaBridge 189:f392fc9709a3 1537 /**
AnnaBridge 189:f392fc9709a3 1538 \brief Set Interrupt Vector
AnnaBridge 189:f392fc9709a3 1539 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 189:f392fc9709a3 1540 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 189:f392fc9709a3 1541 or negative to specify a processor exception.
AnnaBridge 189:f392fc9709a3 1542 VTOR must been relocated to SRAM before.
AnnaBridge 189:f392fc9709a3 1543 If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge 189:f392fc9709a3 1544 \param [in] IRQn Interrupt number
AnnaBridge 189:f392fc9709a3 1545 \param [in] vector Address of interrupt handler function
AnnaBridge 189:f392fc9709a3 1546 */
AnnaBridge 189:f392fc9709a3 1547 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 189:f392fc9709a3 1548 {
AnnaBridge 189:f392fc9709a3 1549 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 1550 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 189:f392fc9709a3 1551 #else
AnnaBridge 189:f392fc9709a3 1552 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 189:f392fc9709a3 1553 #endif
AnnaBridge 189:f392fc9709a3 1554 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 189:f392fc9709a3 1555 }
AnnaBridge 189:f392fc9709a3 1556
AnnaBridge 189:f392fc9709a3 1557
AnnaBridge 189:f392fc9709a3 1558 /**
AnnaBridge 189:f392fc9709a3 1559 \brief Get Interrupt Vector
AnnaBridge 189:f392fc9709a3 1560 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 189:f392fc9709a3 1561 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 189:f392fc9709a3 1562 or negative to specify a processor exception.
AnnaBridge 189:f392fc9709a3 1563 \param [in] IRQn Interrupt number.
AnnaBridge 189:f392fc9709a3 1564 \return Address of interrupt handler function
AnnaBridge 189:f392fc9709a3 1565 */
AnnaBridge 189:f392fc9709a3 1566 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1567 {
AnnaBridge 189:f392fc9709a3 1568 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 1569 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 189:f392fc9709a3 1570 #else
AnnaBridge 189:f392fc9709a3 1571 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 189:f392fc9709a3 1572 #endif
AnnaBridge 189:f392fc9709a3 1573 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 189:f392fc9709a3 1574 }
AnnaBridge 189:f392fc9709a3 1575
AnnaBridge 189:f392fc9709a3 1576
AnnaBridge 189:f392fc9709a3 1577 /**
AnnaBridge 189:f392fc9709a3 1578 \brief System Reset
AnnaBridge 189:f392fc9709a3 1579 \details Initiates a system reset request to reset the MCU.
AnnaBridge 189:f392fc9709a3 1580 */
AnnaBridge 189:f392fc9709a3 1581 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 189:f392fc9709a3 1582 {
AnnaBridge 189:f392fc9709a3 1583 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 189:f392fc9709a3 1584 buffered write are completed before reset */
AnnaBridge 189:f392fc9709a3 1585 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 189:f392fc9709a3 1586 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 189:f392fc9709a3 1587 __DSB(); /* Ensure completion of memory access */
AnnaBridge 189:f392fc9709a3 1588
AnnaBridge 189:f392fc9709a3 1589 for(;;) /* wait until reset */
AnnaBridge 189:f392fc9709a3 1590 {
AnnaBridge 189:f392fc9709a3 1591 __NOP();
AnnaBridge 189:f392fc9709a3 1592 }
AnnaBridge 189:f392fc9709a3 1593 }
AnnaBridge 189:f392fc9709a3 1594
AnnaBridge 189:f392fc9709a3 1595 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 189:f392fc9709a3 1596 /**
AnnaBridge 189:f392fc9709a3 1597 \brief Enable Interrupt (non-secure)
AnnaBridge 189:f392fc9709a3 1598 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 189:f392fc9709a3 1599 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1600 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1601 */
AnnaBridge 189:f392fc9709a3 1602 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1603 {
AnnaBridge 189:f392fc9709a3 1604 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1605 {
AnnaBridge 189:f392fc9709a3 1606 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 189:f392fc9709a3 1607 }
AnnaBridge 189:f392fc9709a3 1608 }
AnnaBridge 189:f392fc9709a3 1609
AnnaBridge 189:f392fc9709a3 1610
AnnaBridge 189:f392fc9709a3 1611 /**
AnnaBridge 189:f392fc9709a3 1612 \brief Get Interrupt Enable status (non-secure)
AnnaBridge 189:f392fc9709a3 1613 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 189:f392fc9709a3 1614 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1615 \return 0 Interrupt is not enabled.
AnnaBridge 189:f392fc9709a3 1616 \return 1 Interrupt is enabled.
AnnaBridge 189:f392fc9709a3 1617 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1618 */
AnnaBridge 189:f392fc9709a3 1619 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1620 {
AnnaBridge 189:f392fc9709a3 1621 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1622 {
AnnaBridge 189:f392fc9709a3 1623 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 189:f392fc9709a3 1624 }
AnnaBridge 189:f392fc9709a3 1625 else
AnnaBridge 189:f392fc9709a3 1626 {
AnnaBridge 189:f392fc9709a3 1627 return(0U);
AnnaBridge 189:f392fc9709a3 1628 }
AnnaBridge 189:f392fc9709a3 1629 }
AnnaBridge 189:f392fc9709a3 1630
AnnaBridge 189:f392fc9709a3 1631
AnnaBridge 189:f392fc9709a3 1632 /**
AnnaBridge 189:f392fc9709a3 1633 \brief Disable Interrupt (non-secure)
AnnaBridge 189:f392fc9709a3 1634 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 189:f392fc9709a3 1635 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1636 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1637 */
AnnaBridge 189:f392fc9709a3 1638 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1639 {
AnnaBridge 189:f392fc9709a3 1640 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1641 {
AnnaBridge 189:f392fc9709a3 1642 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 189:f392fc9709a3 1643 }
AnnaBridge 189:f392fc9709a3 1644 }
AnnaBridge 189:f392fc9709a3 1645
AnnaBridge 189:f392fc9709a3 1646
AnnaBridge 189:f392fc9709a3 1647 /**
AnnaBridge 189:f392fc9709a3 1648 \brief Get Pending Interrupt (non-secure)
AnnaBridge 189:f392fc9709a3 1649 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
AnnaBridge 189:f392fc9709a3 1650 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1651 \return 0 Interrupt status is not pending.
AnnaBridge 189:f392fc9709a3 1652 \return 1 Interrupt status is pending.
AnnaBridge 189:f392fc9709a3 1653 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1654 */
AnnaBridge 189:f392fc9709a3 1655 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1656 {
AnnaBridge 189:f392fc9709a3 1657 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1658 {
AnnaBridge 189:f392fc9709a3 1659 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 189:f392fc9709a3 1660 }
AnnaBridge 189:f392fc9709a3 1661 else
AnnaBridge 189:f392fc9709a3 1662 {
AnnaBridge 189:f392fc9709a3 1663 return(0U);
AnnaBridge 189:f392fc9709a3 1664 }
AnnaBridge 189:f392fc9709a3 1665 }
AnnaBridge 189:f392fc9709a3 1666
AnnaBridge 189:f392fc9709a3 1667
AnnaBridge 189:f392fc9709a3 1668 /**
AnnaBridge 189:f392fc9709a3 1669 \brief Set Pending Interrupt (non-secure)
AnnaBridge 189:f392fc9709a3 1670 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge 189:f392fc9709a3 1671 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1672 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1673 */
AnnaBridge 189:f392fc9709a3 1674 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1675 {
AnnaBridge 189:f392fc9709a3 1676 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1677 {
AnnaBridge 189:f392fc9709a3 1678 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 189:f392fc9709a3 1679 }
AnnaBridge 189:f392fc9709a3 1680 }
AnnaBridge 189:f392fc9709a3 1681
AnnaBridge 189:f392fc9709a3 1682
AnnaBridge 189:f392fc9709a3 1683 /**
AnnaBridge 189:f392fc9709a3 1684 \brief Clear Pending Interrupt (non-secure)
AnnaBridge 189:f392fc9709a3 1685 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge 189:f392fc9709a3 1686 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1687 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1688 */
AnnaBridge 189:f392fc9709a3 1689 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1690 {
AnnaBridge 189:f392fc9709a3 1691 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1692 {
AnnaBridge 189:f392fc9709a3 1693 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 189:f392fc9709a3 1694 }
AnnaBridge 189:f392fc9709a3 1695 }
AnnaBridge 189:f392fc9709a3 1696
AnnaBridge 189:f392fc9709a3 1697
AnnaBridge 189:f392fc9709a3 1698 /**
AnnaBridge 189:f392fc9709a3 1699 \brief Get Active Interrupt (non-secure)
AnnaBridge 189:f392fc9709a3 1700 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
AnnaBridge 189:f392fc9709a3 1701 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 1702 \return 0 Interrupt status is not active.
AnnaBridge 189:f392fc9709a3 1703 \return 1 Interrupt status is active.
AnnaBridge 189:f392fc9709a3 1704 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 1705 */
AnnaBridge 189:f392fc9709a3 1706 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1707 {
AnnaBridge 189:f392fc9709a3 1708 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1709 {
AnnaBridge 189:f392fc9709a3 1710 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 189:f392fc9709a3 1711 }
AnnaBridge 189:f392fc9709a3 1712 else
AnnaBridge 189:f392fc9709a3 1713 {
AnnaBridge 189:f392fc9709a3 1714 return(0U);
AnnaBridge 189:f392fc9709a3 1715 }
AnnaBridge 189:f392fc9709a3 1716 }
AnnaBridge 189:f392fc9709a3 1717
AnnaBridge 189:f392fc9709a3 1718
AnnaBridge 189:f392fc9709a3 1719 /**
AnnaBridge 189:f392fc9709a3 1720 \brief Set Interrupt Priority (non-secure)
AnnaBridge 189:f392fc9709a3 1721 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge 189:f392fc9709a3 1722 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 189:f392fc9709a3 1723 or negative to specify a processor exception.
AnnaBridge 189:f392fc9709a3 1724 \param [in] IRQn Interrupt number.
AnnaBridge 189:f392fc9709a3 1725 \param [in] priority Priority to set.
AnnaBridge 189:f392fc9709a3 1726 \note The priority cannot be set for every non-secure processor exception.
AnnaBridge 189:f392fc9709a3 1727 */
AnnaBridge 189:f392fc9709a3 1728 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 189:f392fc9709a3 1729 {
AnnaBridge 189:f392fc9709a3 1730 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1731 {
AnnaBridge 189:f392fc9709a3 1732 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 189:f392fc9709a3 1733 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 189:f392fc9709a3 1734 }
AnnaBridge 189:f392fc9709a3 1735 else
AnnaBridge 189:f392fc9709a3 1736 {
AnnaBridge 189:f392fc9709a3 1737 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 189:f392fc9709a3 1738 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 189:f392fc9709a3 1739 }
AnnaBridge 189:f392fc9709a3 1740 }
AnnaBridge 189:f392fc9709a3 1741
AnnaBridge 189:f392fc9709a3 1742
AnnaBridge 189:f392fc9709a3 1743 /**
AnnaBridge 189:f392fc9709a3 1744 \brief Get Interrupt Priority (non-secure)
AnnaBridge 189:f392fc9709a3 1745 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge 189:f392fc9709a3 1746 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 189:f392fc9709a3 1747 or negative to specify a processor exception.
AnnaBridge 189:f392fc9709a3 1748 \param [in] IRQn Interrupt number.
AnnaBridge 189:f392fc9709a3 1749 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 189:f392fc9709a3 1750 */
AnnaBridge 189:f392fc9709a3 1751 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 1752 {
AnnaBridge 189:f392fc9709a3 1753
AnnaBridge 189:f392fc9709a3 1754 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 1755 {
AnnaBridge 189:f392fc9709a3 1756 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 189:f392fc9709a3 1757 }
AnnaBridge 189:f392fc9709a3 1758 else
AnnaBridge 189:f392fc9709a3 1759 {
AnnaBridge 189:f392fc9709a3 1760 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 189:f392fc9709a3 1761 }
AnnaBridge 189:f392fc9709a3 1762 }
AnnaBridge 189:f392fc9709a3 1763 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 189:f392fc9709a3 1764
AnnaBridge 189:f392fc9709a3 1765 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 189:f392fc9709a3 1766
AnnaBridge 189:f392fc9709a3 1767 /* ########################## MPU functions #################################### */
AnnaBridge 189:f392fc9709a3 1768
AnnaBridge 189:f392fc9709a3 1769 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 1770
AnnaBridge 189:f392fc9709a3 1771 #include "mpu_armv8.h"
AnnaBridge 189:f392fc9709a3 1772
AnnaBridge 189:f392fc9709a3 1773 #endif
AnnaBridge 189:f392fc9709a3 1774
AnnaBridge 189:f392fc9709a3 1775 /* ########################## FPU functions #################################### */
AnnaBridge 189:f392fc9709a3 1776 /**
AnnaBridge 189:f392fc9709a3 1777 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 189:f392fc9709a3 1778 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 189:f392fc9709a3 1779 \brief Function that provides FPU type.
AnnaBridge 189:f392fc9709a3 1780 @{
AnnaBridge 189:f392fc9709a3 1781 */
AnnaBridge 189:f392fc9709a3 1782
AnnaBridge 189:f392fc9709a3 1783 /**
AnnaBridge 189:f392fc9709a3 1784 \brief get FPU type
AnnaBridge 189:f392fc9709a3 1785 \details returns the FPU type
AnnaBridge 189:f392fc9709a3 1786 \returns
AnnaBridge 189:f392fc9709a3 1787 - \b 0: No FPU
AnnaBridge 189:f392fc9709a3 1788 - \b 1: Single precision FPU
AnnaBridge 189:f392fc9709a3 1789 - \b 2: Double + Single precision FPU
AnnaBridge 189:f392fc9709a3 1790 */
AnnaBridge 189:f392fc9709a3 1791 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 189:f392fc9709a3 1792 {
AnnaBridge 189:f392fc9709a3 1793 return 0U; /* No FPU */
AnnaBridge 189:f392fc9709a3 1794 }
AnnaBridge 189:f392fc9709a3 1795
AnnaBridge 189:f392fc9709a3 1796
AnnaBridge 189:f392fc9709a3 1797 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 189:f392fc9709a3 1798
AnnaBridge 189:f392fc9709a3 1799
AnnaBridge 189:f392fc9709a3 1800
AnnaBridge 189:f392fc9709a3 1801 /* ########################## SAU functions #################################### */
AnnaBridge 189:f392fc9709a3 1802 /**
AnnaBridge 189:f392fc9709a3 1803 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 189:f392fc9709a3 1804 \defgroup CMSIS_Core_SAUFunctions SAU Functions
AnnaBridge 189:f392fc9709a3 1805 \brief Functions that configure the SAU.
AnnaBridge 189:f392fc9709a3 1806 @{
AnnaBridge 189:f392fc9709a3 1807 */
AnnaBridge 189:f392fc9709a3 1808
AnnaBridge 189:f392fc9709a3 1809 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 189:f392fc9709a3 1810
AnnaBridge 189:f392fc9709a3 1811 /**
AnnaBridge 189:f392fc9709a3 1812 \brief Enable SAU
AnnaBridge 189:f392fc9709a3 1813 \details Enables the Security Attribution Unit (SAU).
AnnaBridge 189:f392fc9709a3 1814 */
AnnaBridge 189:f392fc9709a3 1815 __STATIC_INLINE void TZ_SAU_Enable(void)
AnnaBridge 189:f392fc9709a3 1816 {
AnnaBridge 189:f392fc9709a3 1817 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
AnnaBridge 189:f392fc9709a3 1818 }
AnnaBridge 189:f392fc9709a3 1819
AnnaBridge 189:f392fc9709a3 1820
AnnaBridge 189:f392fc9709a3 1821
AnnaBridge 189:f392fc9709a3 1822 /**
AnnaBridge 189:f392fc9709a3 1823 \brief Disable SAU
AnnaBridge 189:f392fc9709a3 1824 \details Disables the Security Attribution Unit (SAU).
AnnaBridge 189:f392fc9709a3 1825 */
AnnaBridge 189:f392fc9709a3 1826 __STATIC_INLINE void TZ_SAU_Disable(void)
AnnaBridge 189:f392fc9709a3 1827 {
AnnaBridge 189:f392fc9709a3 1828 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
AnnaBridge 189:f392fc9709a3 1829 }
AnnaBridge 189:f392fc9709a3 1830
AnnaBridge 189:f392fc9709a3 1831 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 189:f392fc9709a3 1832
AnnaBridge 189:f392fc9709a3 1833 /*@} end of CMSIS_Core_SAUFunctions */
AnnaBridge 189:f392fc9709a3 1834
AnnaBridge 189:f392fc9709a3 1835
AnnaBridge 189:f392fc9709a3 1836
AnnaBridge 189:f392fc9709a3 1837
AnnaBridge 189:f392fc9709a3 1838 /* ################################## SysTick function ############################################ */
AnnaBridge 189:f392fc9709a3 1839 /**
AnnaBridge 189:f392fc9709a3 1840 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 189:f392fc9709a3 1841 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 189:f392fc9709a3 1842 \brief Functions that configure the System.
AnnaBridge 189:f392fc9709a3 1843 @{
AnnaBridge 189:f392fc9709a3 1844 */
AnnaBridge 189:f392fc9709a3 1845
AnnaBridge 189:f392fc9709a3 1846 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 189:f392fc9709a3 1847
AnnaBridge 189:f392fc9709a3 1848 /**
AnnaBridge 189:f392fc9709a3 1849 \brief System Tick Configuration
AnnaBridge 189:f392fc9709a3 1850 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 189:f392fc9709a3 1851 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 189:f392fc9709a3 1852 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 189:f392fc9709a3 1853 \return 0 Function succeeded.
AnnaBridge 189:f392fc9709a3 1854 \return 1 Function failed.
AnnaBridge 189:f392fc9709a3 1855 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 189:f392fc9709a3 1856 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 189:f392fc9709a3 1857 must contain a vendor-specific implementation of this function.
AnnaBridge 189:f392fc9709a3 1858 */
AnnaBridge 189:f392fc9709a3 1859 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 189:f392fc9709a3 1860 {
AnnaBridge 189:f392fc9709a3 1861 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 189:f392fc9709a3 1862 {
AnnaBridge 189:f392fc9709a3 1863 return (1UL); /* Reload value impossible */
AnnaBridge 189:f392fc9709a3 1864 }
AnnaBridge 189:f392fc9709a3 1865
AnnaBridge 189:f392fc9709a3 1866 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 189:f392fc9709a3 1867 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 189:f392fc9709a3 1868 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 189:f392fc9709a3 1869 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 189:f392fc9709a3 1870 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 189:f392fc9709a3 1871 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 189:f392fc9709a3 1872 return (0UL); /* Function successful */
AnnaBridge 189:f392fc9709a3 1873 }
AnnaBridge 189:f392fc9709a3 1874
AnnaBridge 189:f392fc9709a3 1875 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 189:f392fc9709a3 1876 /**
AnnaBridge 189:f392fc9709a3 1877 \brief System Tick Configuration (non-secure)
AnnaBridge 189:f392fc9709a3 1878 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
AnnaBridge 189:f392fc9709a3 1879 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 189:f392fc9709a3 1880 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 189:f392fc9709a3 1881 \return 0 Function succeeded.
AnnaBridge 189:f392fc9709a3 1882 \return 1 Function failed.
AnnaBridge 189:f392fc9709a3 1883 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 189:f392fc9709a3 1884 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 189:f392fc9709a3 1885 must contain a vendor-specific implementation of this function.
AnnaBridge 189:f392fc9709a3 1886
AnnaBridge 189:f392fc9709a3 1887 */
AnnaBridge 189:f392fc9709a3 1888 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
AnnaBridge 189:f392fc9709a3 1889 {
AnnaBridge 189:f392fc9709a3 1890 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 189:f392fc9709a3 1891 {
AnnaBridge 189:f392fc9709a3 1892 return (1UL); /* Reload value impossible */
AnnaBridge 189:f392fc9709a3 1893 }
AnnaBridge 189:f392fc9709a3 1894
AnnaBridge 189:f392fc9709a3 1895 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 189:f392fc9709a3 1896 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 189:f392fc9709a3 1897 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 189:f392fc9709a3 1898 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 189:f392fc9709a3 1899 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 189:f392fc9709a3 1900 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 189:f392fc9709a3 1901 return (0UL); /* Function successful */
AnnaBridge 189:f392fc9709a3 1902 }
AnnaBridge 189:f392fc9709a3 1903 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 189:f392fc9709a3 1904
AnnaBridge 189:f392fc9709a3 1905 #endif
AnnaBridge 189:f392fc9709a3 1906
AnnaBridge 189:f392fc9709a3 1907 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 189:f392fc9709a3 1908
AnnaBridge 189:f392fc9709a3 1909
AnnaBridge 189:f392fc9709a3 1910
AnnaBridge 189:f392fc9709a3 1911
AnnaBridge 189:f392fc9709a3 1912 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 1913 }
AnnaBridge 189:f392fc9709a3 1914 #endif
AnnaBridge 189:f392fc9709a3 1915
AnnaBridge 189:f392fc9709a3 1916 #endif /* __CORE_ARMV8MBL_H_DEPENDANT */
AnnaBridge 189:f392fc9709a3 1917
AnnaBridge 189:f392fc9709a3 1918 #endif /* __CMSIS_GENERIC */