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cmsis/BUILD/mbed/TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/stm32l0xx_ll_spi.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l0xx_ll_spi.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of SPI LL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L0xx_LL_SPI_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L0xx_LL_SPI_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	45	#include "stm32l0xx.h"
AnnaBridge	189:f392fc9709a3	46
AnnaBridge	189:f392fc9709a3	47	/** @addtogroup STM32L0xx_LL_Driver
AnnaBridge	189:f392fc9709a3	48	* @{
AnnaBridge	189:f392fc9709a3	49	*/
AnnaBridge	189:f392fc9709a3	50
AnnaBridge	189:f392fc9709a3	51	#if defined (SPI1) \|\| defined (SPI2)
AnnaBridge	189:f392fc9709a3	52
AnnaBridge	189:f392fc9709a3	53	/** @defgroup SPI_LL SPI
AnnaBridge	189:f392fc9709a3	54	* @{
AnnaBridge	189:f392fc9709a3	55	*/
AnnaBridge	189:f392fc9709a3	56
AnnaBridge	189:f392fc9709a3	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	59	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	60
AnnaBridge	189:f392fc9709a3	61	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	62	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	63	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
AnnaBridge	189:f392fc9709a3	64	* @{
AnnaBridge	189:f392fc9709a3	65	*/
AnnaBridge	189:f392fc9709a3	66
AnnaBridge	189:f392fc9709a3	67	/**
AnnaBridge	189:f392fc9709a3	68	* @brief SPI Init structures definition
AnnaBridge	189:f392fc9709a3	69	*/
AnnaBridge	189:f392fc9709a3	70	typedef struct
AnnaBridge	189:f392fc9709a3	71	{
AnnaBridge	189:f392fc9709a3	72	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
AnnaBridge	189:f392fc9709a3	73	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
AnnaBridge	189:f392fc9709a3	74
AnnaBridge	189:f392fc9709a3	75	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
AnnaBridge	189:f392fc9709a3	76
AnnaBridge	189:f392fc9709a3	77	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
AnnaBridge	189:f392fc9709a3	78	This parameter can be a value of @ref SPI_LL_EC_MODE.
AnnaBridge	189:f392fc9709a3	79
AnnaBridge	189:f392fc9709a3	80	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
AnnaBridge	189:f392fc9709a3	81
AnnaBridge	189:f392fc9709a3	82	uint32_t DataWidth; /*!< Specifies the SPI data width.
AnnaBridge	189:f392fc9709a3	83	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
AnnaBridge	189:f392fc9709a3	84
AnnaBridge	189:f392fc9709a3	85	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
AnnaBridge	189:f392fc9709a3	86
AnnaBridge	189:f392fc9709a3	87	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge	189:f392fc9709a3	88	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
AnnaBridge	189:f392fc9709a3	89
AnnaBridge	189:f392fc9709a3	90	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
AnnaBridge	189:f392fc9709a3	91
AnnaBridge	189:f392fc9709a3	92	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge	189:f392fc9709a3	93	This parameter can be a value of @ref SPI_LL_EC_PHASE.
AnnaBridge	189:f392fc9709a3	94
AnnaBridge	189:f392fc9709a3	95	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
AnnaBridge	189:f392fc9709a3	96
AnnaBridge	189:f392fc9709a3	97	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
AnnaBridge	189:f392fc9709a3	98	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
AnnaBridge	189:f392fc9709a3	99
AnnaBridge	189:f392fc9709a3	100	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
AnnaBridge	189:f392fc9709a3	101
AnnaBridge	189:f392fc9709a3	102	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
AnnaBridge	189:f392fc9709a3	103	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
AnnaBridge	189:f392fc9709a3	104	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
AnnaBridge	189:f392fc9709a3	105
AnnaBridge	189:f392fc9709a3	106	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
AnnaBridge	189:f392fc9709a3	107
AnnaBridge	189:f392fc9709a3	108	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge	189:f392fc9709a3	109	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
AnnaBridge	189:f392fc9709a3	110
AnnaBridge	189:f392fc9709a3	111	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
AnnaBridge	189:f392fc9709a3	112
AnnaBridge	189:f392fc9709a3	113	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge	189:f392fc9709a3	114	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
AnnaBridge	189:f392fc9709a3	115
AnnaBridge	189:f392fc9709a3	116	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
AnnaBridge	189:f392fc9709a3	117
AnnaBridge	189:f392fc9709a3	118	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge	189:f392fc9709a3	119	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
AnnaBridge	189:f392fc9709a3	120
AnnaBridge	189:f392fc9709a3	121	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
AnnaBridge	189:f392fc9709a3	122
AnnaBridge	189:f392fc9709a3	123	} LL_SPI_InitTypeDef;
AnnaBridge	189:f392fc9709a3	124
AnnaBridge	189:f392fc9709a3	125	/**
AnnaBridge	189:f392fc9709a3	126	* @}
AnnaBridge	189:f392fc9709a3	127	*/
AnnaBridge	189:f392fc9709a3	128	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	129
AnnaBridge	189:f392fc9709a3	130	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	131	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
AnnaBridge	189:f392fc9709a3	132	* @{
AnnaBridge	189:f392fc9709a3	133	*/
AnnaBridge	189:f392fc9709a3	134
AnnaBridge	189:f392fc9709a3	135	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	189:f392fc9709a3	136	* @brief Flags defines which can be used with LL_SPI_ReadReg function
AnnaBridge	189:f392fc9709a3	137	* @{
AnnaBridge	189:f392fc9709a3	138	*/
AnnaBridge	189:f392fc9709a3	139	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	189:f392fc9709a3	140	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	189:f392fc9709a3	141	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
AnnaBridge	189:f392fc9709a3	142	#define LL_SPI_SR_UDR SPI_SR_UDR /!< Underrun flag /
AnnaBridge	189:f392fc9709a3	143	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
AnnaBridge	189:f392fc9709a3	144	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
AnnaBridge	189:f392fc9709a3	145	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
AnnaBridge	189:f392fc9709a3	146	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	189:f392fc9709a3	147	/**
AnnaBridge	189:f392fc9709a3	148	* @}
AnnaBridge	189:f392fc9709a3	149	*/
AnnaBridge	189:f392fc9709a3	150
AnnaBridge	189:f392fc9709a3	151	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	189:f392fc9709a3	152	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	189:f392fc9709a3	153	* @{
AnnaBridge	189:f392fc9709a3	154	*/
AnnaBridge	189:f392fc9709a3	155	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	189:f392fc9709a3	156	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	189:f392fc9709a3	157	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	189:f392fc9709a3	158	/**
AnnaBridge	189:f392fc9709a3	159	* @}
AnnaBridge	189:f392fc9709a3	160	*/
AnnaBridge	189:f392fc9709a3	161
AnnaBridge	189:f392fc9709a3	162	/** @defgroup SPI_LL_EC_MODE Operation Mode
AnnaBridge	189:f392fc9709a3	163	* @{
AnnaBridge	189:f392fc9709a3	164	*/
AnnaBridge	189:f392fc9709a3	165	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
AnnaBridge	189:f392fc9709a3	166	#define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U) /!< Slave configuration /
AnnaBridge	189:f392fc9709a3	167	/**
AnnaBridge	189:f392fc9709a3	168	* @}
AnnaBridge	189:f392fc9709a3	169	*/
AnnaBridge	189:f392fc9709a3	170
AnnaBridge	189:f392fc9709a3	171	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
AnnaBridge	189:f392fc9709a3	172	* @{
AnnaBridge	189:f392fc9709a3	173	*/
AnnaBridge	189:f392fc9709a3	174	#define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U) /!< Motorola mode. Used as default value /
AnnaBridge	189:f392fc9709a3	175	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
AnnaBridge	189:f392fc9709a3	176	/**
AnnaBridge	189:f392fc9709a3	177	* @}
AnnaBridge	189:f392fc9709a3	178	*/
AnnaBridge	189:f392fc9709a3	179
AnnaBridge	189:f392fc9709a3	180	/** @defgroup SPI_LL_EC_PHASE Clock Phase
AnnaBridge	189:f392fc9709a3	181	* @{
AnnaBridge	189:f392fc9709a3	182	*/
AnnaBridge	189:f392fc9709a3	183	#define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U) /!< First clock transition is the first data capture edge /
AnnaBridge	189:f392fc9709a3	184	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
AnnaBridge	189:f392fc9709a3	185	/**
AnnaBridge	189:f392fc9709a3	186	* @}
AnnaBridge	189:f392fc9709a3	187	*/
AnnaBridge	189:f392fc9709a3	188
AnnaBridge	189:f392fc9709a3	189	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
AnnaBridge	189:f392fc9709a3	190	* @{
AnnaBridge	189:f392fc9709a3	191	*/
AnnaBridge	189:f392fc9709a3	192	#define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U) /!< Clock to 0 when idle /
AnnaBridge	189:f392fc9709a3	193	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
AnnaBridge	189:f392fc9709a3	194	/**
AnnaBridge	189:f392fc9709a3	195	* @}
AnnaBridge	189:f392fc9709a3	196	*/
AnnaBridge	189:f392fc9709a3	197
AnnaBridge	189:f392fc9709a3	198	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
AnnaBridge	189:f392fc9709a3	199	* @{
AnnaBridge	189:f392fc9709a3	200	*/
AnnaBridge	189:f392fc9709a3	201	#define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U) /!< BaudRate control equal to fPCLK/2 /
AnnaBridge	189:f392fc9709a3	202	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
AnnaBridge	189:f392fc9709a3	203	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
AnnaBridge	189:f392fc9709a3	204	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
AnnaBridge	189:f392fc9709a3	205	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
AnnaBridge	189:f392fc9709a3	206	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
AnnaBridge	189:f392fc9709a3	207	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
AnnaBridge	189:f392fc9709a3	208	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
AnnaBridge	189:f392fc9709a3	209	/**
AnnaBridge	189:f392fc9709a3	210	* @}
AnnaBridge	189:f392fc9709a3	211	*/
AnnaBridge	189:f392fc9709a3	212
AnnaBridge	189:f392fc9709a3	213	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
AnnaBridge	189:f392fc9709a3	214	* @{
AnnaBridge	189:f392fc9709a3	215	*/
AnnaBridge	189:f392fc9709a3	216	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
AnnaBridge	189:f392fc9709a3	217	#define LL_SPI_MSB_FIRST ((uint32_t)0x00000000U) /!< Data is transmitted/received with the MSB first /
AnnaBridge	189:f392fc9709a3	218	/**
AnnaBridge	189:f392fc9709a3	219	* @}
AnnaBridge	189:f392fc9709a3	220	*/
AnnaBridge	189:f392fc9709a3	221
AnnaBridge	189:f392fc9709a3	222	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
AnnaBridge	189:f392fc9709a3	223	* @{
AnnaBridge	189:f392fc9709a3	224	*/
AnnaBridge	189:f392fc9709a3	225	#define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U) /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
AnnaBridge	189:f392fc9709a3	226	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
AnnaBridge	189:f392fc9709a3	227	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
AnnaBridge	189:f392fc9709a3	228	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
AnnaBridge	189:f392fc9709a3	229	/**
AnnaBridge	189:f392fc9709a3	230	* @}
AnnaBridge	189:f392fc9709a3	231	*/
AnnaBridge	189:f392fc9709a3	232
AnnaBridge	189:f392fc9709a3	233	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
AnnaBridge	189:f392fc9709a3	234	* @{
AnnaBridge	189:f392fc9709a3	235	*/
AnnaBridge	189:f392fc9709a3	236	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
AnnaBridge	189:f392fc9709a3	237	#define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) /!< NSS pin used in Input. Only used in Master mode /
AnnaBridge	189:f392fc9709a3	238	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
AnnaBridge	189:f392fc9709a3	239	/**
AnnaBridge	189:f392fc9709a3	240	* @}
AnnaBridge	189:f392fc9709a3	241	*/
AnnaBridge	189:f392fc9709a3	242
AnnaBridge	189:f392fc9709a3	243	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
AnnaBridge	189:f392fc9709a3	244	* @{
AnnaBridge	189:f392fc9709a3	245	*/
AnnaBridge	189:f392fc9709a3	246	#define LL_SPI_DATAWIDTH_8BIT ((uint32_t)0x00000000U) /!< Data length for SPI transfer: 8 bits /
AnnaBridge	189:f392fc9709a3	247	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /!< Data length for SPI transfer: 16 bits /
AnnaBridge	189:f392fc9709a3	248	/**
AnnaBridge	189:f392fc9709a3	249	* @}
AnnaBridge	189:f392fc9709a3	250	*/
AnnaBridge	189:f392fc9709a3	251	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	252
AnnaBridge	189:f392fc9709a3	253	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
AnnaBridge	189:f392fc9709a3	254	* @{
AnnaBridge	189:f392fc9709a3	255	*/
AnnaBridge	189:f392fc9709a3	256	#define LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) /!< CRC calculation disabled /
AnnaBridge	189:f392fc9709a3	257	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
AnnaBridge	189:f392fc9709a3	258	/**
AnnaBridge	189:f392fc9709a3	259	* @}
AnnaBridge	189:f392fc9709a3	260	*/
AnnaBridge	189:f392fc9709a3	261	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	262
AnnaBridge	189:f392fc9709a3	263	/**
AnnaBridge	189:f392fc9709a3	264	* @}
AnnaBridge	189:f392fc9709a3	265	*/
AnnaBridge	189:f392fc9709a3	266
AnnaBridge	189:f392fc9709a3	267	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	268	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
AnnaBridge	189:f392fc9709a3	269	* @{
AnnaBridge	189:f392fc9709a3	270	*/
AnnaBridge	189:f392fc9709a3	271
AnnaBridge	189:f392fc9709a3	272	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	189:f392fc9709a3	273	* @{
AnnaBridge	189:f392fc9709a3	274	*/
AnnaBridge	189:f392fc9709a3	275
AnnaBridge	189:f392fc9709a3	276	/**
AnnaBridge	189:f392fc9709a3	277	* @brief Write a value in SPI register
AnnaBridge	189:f392fc9709a3	278	* @param __INSTANCE__ SPI Instance
AnnaBridge	189:f392fc9709a3	279	* @param __REG__ Register to be written
AnnaBridge	189:f392fc9709a3	280	* @param __VALUE__ Value to be written in the register
AnnaBridge	189:f392fc9709a3	281	* @retval None
AnnaBridge	189:f392fc9709a3	282	*/
AnnaBridge	189:f392fc9709a3	283	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	189:f392fc9709a3	284
AnnaBridge	189:f392fc9709a3	285	/**
AnnaBridge	189:f392fc9709a3	286	* @brief Read a value in SPI register
AnnaBridge	189:f392fc9709a3	287	* @param __INSTANCE__ SPI Instance
AnnaBridge	189:f392fc9709a3	288	* @param __REG__ Register to be read
AnnaBridge	189:f392fc9709a3	289	* @retval Register value
AnnaBridge	189:f392fc9709a3	290	*/
AnnaBridge	189:f392fc9709a3	291	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	189:f392fc9709a3	292	/**
AnnaBridge	189:f392fc9709a3	293	* @}
AnnaBridge	189:f392fc9709a3	294	*/
AnnaBridge	189:f392fc9709a3	295
AnnaBridge	189:f392fc9709a3	296	/**
AnnaBridge	189:f392fc9709a3	297	* @}
AnnaBridge	189:f392fc9709a3	298	*/
AnnaBridge	189:f392fc9709a3	299
AnnaBridge	189:f392fc9709a3	300	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	301	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
AnnaBridge	189:f392fc9709a3	302	* @{
AnnaBridge	189:f392fc9709a3	303	*/
AnnaBridge	189:f392fc9709a3	304
AnnaBridge	189:f392fc9709a3	305	/** @defgroup SPI_LL_EF_Configuration Configuration
AnnaBridge	189:f392fc9709a3	306	* @{
AnnaBridge	189:f392fc9709a3	307	*/
AnnaBridge	189:f392fc9709a3	308
AnnaBridge	189:f392fc9709a3	309	/**
AnnaBridge	189:f392fc9709a3	310	* @brief Enable SPI peripheral
AnnaBridge	189:f392fc9709a3	311	* @rmtoll CR1 SPE LL_SPI_Enable
AnnaBridge	189:f392fc9709a3	312	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	313	* @retval None
AnnaBridge	189:f392fc9709a3	314	*/
AnnaBridge	189:f392fc9709a3	315	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	316	{
AnnaBridge	189:f392fc9709a3	317	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	189:f392fc9709a3	318	}
AnnaBridge	189:f392fc9709a3	319
AnnaBridge	189:f392fc9709a3	320	/**
AnnaBridge	189:f392fc9709a3	321	* @brief Disable SPI peripheral
AnnaBridge	189:f392fc9709a3	322	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
AnnaBridge	189:f392fc9709a3	323	* @rmtoll CR1 SPE LL_SPI_Disable
AnnaBridge	189:f392fc9709a3	324	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	325	* @retval None
AnnaBridge	189:f392fc9709a3	326	*/
AnnaBridge	189:f392fc9709a3	327	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	328	{
AnnaBridge	189:f392fc9709a3	329	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	189:f392fc9709a3	330	}
AnnaBridge	189:f392fc9709a3	331
AnnaBridge	189:f392fc9709a3	332	/**
AnnaBridge	189:f392fc9709a3	333	* @brief Check if SPI peripheral is enabled
AnnaBridge	189:f392fc9709a3	334	* @rmtoll CR1 SPE LL_SPI_IsEnabled
AnnaBridge	189:f392fc9709a3	335	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	336	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	337	*/
AnnaBridge	189:f392fc9709a3	338	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	339	{
AnnaBridge	189:f392fc9709a3	340	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
AnnaBridge	189:f392fc9709a3	341	}
AnnaBridge	189:f392fc9709a3	342
AnnaBridge	189:f392fc9709a3	343	/**
AnnaBridge	189:f392fc9709a3	344	* @brief Set SPI operation mode to Master or Slave
AnnaBridge	189:f392fc9709a3	345	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	189:f392fc9709a3	346	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
AnnaBridge	189:f392fc9709a3	347	* CR1 SSI LL_SPI_SetMode
AnnaBridge	189:f392fc9709a3	348	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	349	* @param Mode This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	350	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	189:f392fc9709a3	351	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	189:f392fc9709a3	352	* @retval None
AnnaBridge	189:f392fc9709a3	353	*/
AnnaBridge	189:f392fc9709a3	354	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	189:f392fc9709a3	355	{
AnnaBridge	189:f392fc9709a3	356	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
AnnaBridge	189:f392fc9709a3	357	}
AnnaBridge	189:f392fc9709a3	358
AnnaBridge	189:f392fc9709a3	359	/**
AnnaBridge	189:f392fc9709a3	360	* @brief Get SPI operation mode (Master or Slave)
AnnaBridge	189:f392fc9709a3	361	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
AnnaBridge	189:f392fc9709a3	362	* CR1 SSI LL_SPI_GetMode
AnnaBridge	189:f392fc9709a3	363	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	364	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	365	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	189:f392fc9709a3	366	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	189:f392fc9709a3	367	*/
AnnaBridge	189:f392fc9709a3	368	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	369	{
AnnaBridge	189:f392fc9709a3	370	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
AnnaBridge	189:f392fc9709a3	371	}
AnnaBridge	189:f392fc9709a3	372
AnnaBridge	189:f392fc9709a3	373	/**
AnnaBridge	189:f392fc9709a3	374	* @brief Set serial protocol used
AnnaBridge	189:f392fc9709a3	375	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	189:f392fc9709a3	376	* @rmtoll CR2 FRF LL_SPI_SetStandard
AnnaBridge	189:f392fc9709a3	377	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	378	* @param Standard This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	379	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	189:f392fc9709a3	380	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	189:f392fc9709a3	381	* @retval None
AnnaBridge	189:f392fc9709a3	382	*/
AnnaBridge	189:f392fc9709a3	383	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	189:f392fc9709a3	384	{
AnnaBridge	189:f392fc9709a3	385	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
AnnaBridge	189:f392fc9709a3	386	}
AnnaBridge	189:f392fc9709a3	387
AnnaBridge	189:f392fc9709a3	388	/**
AnnaBridge	189:f392fc9709a3	389	* @brief Get serial protocol used
AnnaBridge	189:f392fc9709a3	390	* @rmtoll CR2 FRF LL_SPI_GetStandard
AnnaBridge	189:f392fc9709a3	391	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	392	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	393	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	189:f392fc9709a3	394	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	189:f392fc9709a3	395	*/
AnnaBridge	189:f392fc9709a3	396	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	397	{
AnnaBridge	189:f392fc9709a3	398	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
AnnaBridge	189:f392fc9709a3	399	}
AnnaBridge	189:f392fc9709a3	400
AnnaBridge	189:f392fc9709a3	401	/**
AnnaBridge	189:f392fc9709a3	402	* @brief Set clock phase
AnnaBridge	189:f392fc9709a3	403	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	189:f392fc9709a3	404	* This bit is not used in SPI TI mode.
AnnaBridge	189:f392fc9709a3	405	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
AnnaBridge	189:f392fc9709a3	406	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	407	* @param ClockPhase This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	408	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	189:f392fc9709a3	409	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	189:f392fc9709a3	410	* @retval None
AnnaBridge	189:f392fc9709a3	411	*/
AnnaBridge	189:f392fc9709a3	412	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
AnnaBridge	189:f392fc9709a3	413	{
AnnaBridge	189:f392fc9709a3	414	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
AnnaBridge	189:f392fc9709a3	415	}
AnnaBridge	189:f392fc9709a3	416
AnnaBridge	189:f392fc9709a3	417	/**
AnnaBridge	189:f392fc9709a3	418	* @brief Get clock phase
AnnaBridge	189:f392fc9709a3	419	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
AnnaBridge	189:f392fc9709a3	420	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	421	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	422	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	189:f392fc9709a3	423	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	189:f392fc9709a3	424	*/
AnnaBridge	189:f392fc9709a3	425	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	426	{
AnnaBridge	189:f392fc9709a3	427	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
AnnaBridge	189:f392fc9709a3	428	}
AnnaBridge	189:f392fc9709a3	429
AnnaBridge	189:f392fc9709a3	430	/**
AnnaBridge	189:f392fc9709a3	431	* @brief Set clock polarity
AnnaBridge	189:f392fc9709a3	432	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	189:f392fc9709a3	433	* This bit is not used in SPI TI mode.
AnnaBridge	189:f392fc9709a3	434	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
AnnaBridge	189:f392fc9709a3	435	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	436	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	437	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	189:f392fc9709a3	438	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	189:f392fc9709a3	439	* @retval None
AnnaBridge	189:f392fc9709a3	440	*/
AnnaBridge	189:f392fc9709a3	441	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	189:f392fc9709a3	442	{
AnnaBridge	189:f392fc9709a3	443	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
AnnaBridge	189:f392fc9709a3	444	}
AnnaBridge	189:f392fc9709a3	445
AnnaBridge	189:f392fc9709a3	446	/**
AnnaBridge	189:f392fc9709a3	447	* @brief Get clock polarity
AnnaBridge	189:f392fc9709a3	448	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
AnnaBridge	189:f392fc9709a3	449	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	450	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	451	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	189:f392fc9709a3	452	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	189:f392fc9709a3	453	*/
AnnaBridge	189:f392fc9709a3	454	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	455	{
AnnaBridge	189:f392fc9709a3	456	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
AnnaBridge	189:f392fc9709a3	457	}
AnnaBridge	189:f392fc9709a3	458
AnnaBridge	189:f392fc9709a3	459	/**
AnnaBridge	189:f392fc9709a3	460	* @brief Set baud rate prescaler
AnnaBridge	189:f392fc9709a3	461	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
AnnaBridge	189:f392fc9709a3	462	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
AnnaBridge	189:f392fc9709a3	463	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	464	* @param BaudRate This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	465	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	189:f392fc9709a3	466	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	189:f392fc9709a3	467	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	189:f392fc9709a3	468	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	189:f392fc9709a3	469	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	189:f392fc9709a3	470	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	189:f392fc9709a3	471	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	189:f392fc9709a3	472	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	189:f392fc9709a3	473	* @retval None
AnnaBridge	189:f392fc9709a3	474	*/
AnnaBridge	189:f392fc9709a3	475	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
AnnaBridge	189:f392fc9709a3	476	{
AnnaBridge	189:f392fc9709a3	477	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
AnnaBridge	189:f392fc9709a3	478	}
AnnaBridge	189:f392fc9709a3	479
AnnaBridge	189:f392fc9709a3	480	/**
AnnaBridge	189:f392fc9709a3	481	* @brief Get baud rate prescaler
AnnaBridge	189:f392fc9709a3	482	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
AnnaBridge	189:f392fc9709a3	483	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	484	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	485	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	189:f392fc9709a3	486	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	189:f392fc9709a3	487	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	189:f392fc9709a3	488	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	189:f392fc9709a3	489	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	189:f392fc9709a3	490	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	189:f392fc9709a3	491	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	189:f392fc9709a3	492	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	189:f392fc9709a3	493	*/
AnnaBridge	189:f392fc9709a3	494	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	495	{
AnnaBridge	189:f392fc9709a3	496	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
AnnaBridge	189:f392fc9709a3	497	}
AnnaBridge	189:f392fc9709a3	498
AnnaBridge	189:f392fc9709a3	499	/**
AnnaBridge	189:f392fc9709a3	500	* @brief Set transfer bit order
AnnaBridge	189:f392fc9709a3	501	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	189:f392fc9709a3	502	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
AnnaBridge	189:f392fc9709a3	503	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	504	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	505	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	189:f392fc9709a3	506	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	189:f392fc9709a3	507	* @retval None
AnnaBridge	189:f392fc9709a3	508	*/
AnnaBridge	189:f392fc9709a3	509	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge	189:f392fc9709a3	510	{
AnnaBridge	189:f392fc9709a3	511	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
AnnaBridge	189:f392fc9709a3	512	}
AnnaBridge	189:f392fc9709a3	513
AnnaBridge	189:f392fc9709a3	514	/**
AnnaBridge	189:f392fc9709a3	515	* @brief Get transfer bit order
AnnaBridge	189:f392fc9709a3	516	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
AnnaBridge	189:f392fc9709a3	517	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	518	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	519	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	189:f392fc9709a3	520	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	189:f392fc9709a3	521	*/
AnnaBridge	189:f392fc9709a3	522	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	523	{
AnnaBridge	189:f392fc9709a3	524	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
AnnaBridge	189:f392fc9709a3	525	}
AnnaBridge	189:f392fc9709a3	526
AnnaBridge	189:f392fc9709a3	527	/**
AnnaBridge	189:f392fc9709a3	528	* @brief Set transfer direction mode
AnnaBridge	189:f392fc9709a3	529	* @note For Half-Duplex mode, Rx Direction is set by default.
AnnaBridge	189:f392fc9709a3	530	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
AnnaBridge	189:f392fc9709a3	531	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
AnnaBridge	189:f392fc9709a3	532	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
AnnaBridge	189:f392fc9709a3	533	* CR1 BIDIOE LL_SPI_SetTransferDirection
AnnaBridge	189:f392fc9709a3	534	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	535	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	536	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	189:f392fc9709a3	537	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	189:f392fc9709a3	538	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	189:f392fc9709a3	539	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	189:f392fc9709a3	540	* @retval None
AnnaBridge	189:f392fc9709a3	541	*/
AnnaBridge	189:f392fc9709a3	542	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
AnnaBridge	189:f392fc9709a3	543	{
AnnaBridge	189:f392fc9709a3	544	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
AnnaBridge	189:f392fc9709a3	545	}
AnnaBridge	189:f392fc9709a3	546
AnnaBridge	189:f392fc9709a3	547	/**
AnnaBridge	189:f392fc9709a3	548	* @brief Get transfer direction mode
AnnaBridge	189:f392fc9709a3	549	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
AnnaBridge	189:f392fc9709a3	550	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
AnnaBridge	189:f392fc9709a3	551	* CR1 BIDIOE LL_SPI_GetTransferDirection
AnnaBridge	189:f392fc9709a3	552	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	553	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	554	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	189:f392fc9709a3	555	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	189:f392fc9709a3	556	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	189:f392fc9709a3	557	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	189:f392fc9709a3	558	*/
AnnaBridge	189:f392fc9709a3	559	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	560	{
AnnaBridge	189:f392fc9709a3	561	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
AnnaBridge	189:f392fc9709a3	562	}
AnnaBridge	189:f392fc9709a3	563
AnnaBridge	189:f392fc9709a3	564	/**
AnnaBridge	189:f392fc9709a3	565	* @brief Set frame data width
AnnaBridge	189:f392fc9709a3	566	* @rmtoll CR1 DFF LL_SPI_SetDataWidth
AnnaBridge	189:f392fc9709a3	567	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	568	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	569	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	189:f392fc9709a3	570	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	189:f392fc9709a3	571	* @retval None
AnnaBridge	189:f392fc9709a3	572	*/
AnnaBridge	189:f392fc9709a3	573	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
AnnaBridge	189:f392fc9709a3	574	{
AnnaBridge	189:f392fc9709a3	575	MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
AnnaBridge	189:f392fc9709a3	576	}
AnnaBridge	189:f392fc9709a3	577
AnnaBridge	189:f392fc9709a3	578	/**
AnnaBridge	189:f392fc9709a3	579	* @brief Get frame data width
AnnaBridge	189:f392fc9709a3	580	* @rmtoll CR1 DFF LL_SPI_GetDataWidth
AnnaBridge	189:f392fc9709a3	581	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	582	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	583	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	189:f392fc9709a3	584	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	189:f392fc9709a3	585	*/
AnnaBridge	189:f392fc9709a3	586	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	587	{
AnnaBridge	189:f392fc9709a3	588	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
AnnaBridge	189:f392fc9709a3	589	}
AnnaBridge	189:f392fc9709a3	590
AnnaBridge	189:f392fc9709a3	591	/**
AnnaBridge	189:f392fc9709a3	592	* @}
AnnaBridge	189:f392fc9709a3	593	*/
AnnaBridge	189:f392fc9709a3	594
AnnaBridge	189:f392fc9709a3	595	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
AnnaBridge	189:f392fc9709a3	596	* @{
AnnaBridge	189:f392fc9709a3	597	*/
AnnaBridge	189:f392fc9709a3	598
AnnaBridge	189:f392fc9709a3	599	/**
AnnaBridge	189:f392fc9709a3	600	* @brief Enable CRC
AnnaBridge	189:f392fc9709a3	601	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	189:f392fc9709a3	602	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
AnnaBridge	189:f392fc9709a3	603	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	604	* @retval None
AnnaBridge	189:f392fc9709a3	605	*/
AnnaBridge	189:f392fc9709a3	606	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	607	{
AnnaBridge	189:f392fc9709a3	608	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	189:f392fc9709a3	609	}
AnnaBridge	189:f392fc9709a3	610
AnnaBridge	189:f392fc9709a3	611	/**
AnnaBridge	189:f392fc9709a3	612	* @brief Disable CRC
AnnaBridge	189:f392fc9709a3	613	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	189:f392fc9709a3	614	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
AnnaBridge	189:f392fc9709a3	615	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	616	* @retval None
AnnaBridge	189:f392fc9709a3	617	*/
AnnaBridge	189:f392fc9709a3	618	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	619	{
AnnaBridge	189:f392fc9709a3	620	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	189:f392fc9709a3	621	}
AnnaBridge	189:f392fc9709a3	622
AnnaBridge	189:f392fc9709a3	623	/**
AnnaBridge	189:f392fc9709a3	624	* @brief Check if CRC is enabled
AnnaBridge	189:f392fc9709a3	625	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	189:f392fc9709a3	626	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
AnnaBridge	189:f392fc9709a3	627	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	628	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	629	*/
AnnaBridge	189:f392fc9709a3	630	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	631	{
AnnaBridge	189:f392fc9709a3	632	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
AnnaBridge	189:f392fc9709a3	633	}
AnnaBridge	189:f392fc9709a3	634
AnnaBridge	189:f392fc9709a3	635	/**
AnnaBridge	189:f392fc9709a3	636	* @brief Set CRCNext to transfer CRC on the line
AnnaBridge	189:f392fc9709a3	637	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
AnnaBridge	189:f392fc9709a3	638	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
AnnaBridge	189:f392fc9709a3	639	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	640	* @retval None
AnnaBridge	189:f392fc9709a3	641	*/
AnnaBridge	189:f392fc9709a3	642	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	643	{
AnnaBridge	189:f392fc9709a3	644	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
AnnaBridge	189:f392fc9709a3	645	}
AnnaBridge	189:f392fc9709a3	646
AnnaBridge	189:f392fc9709a3	647	/**
AnnaBridge	189:f392fc9709a3	648	* @brief Set polynomial for CRC calculation
AnnaBridge	189:f392fc9709a3	649	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
AnnaBridge	189:f392fc9709a3	650	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	651	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	189:f392fc9709a3	652	* @retval None
AnnaBridge	189:f392fc9709a3	653	*/
AnnaBridge	189:f392fc9709a3	654	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
AnnaBridge	189:f392fc9709a3	655	{
AnnaBridge	189:f392fc9709a3	656	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
AnnaBridge	189:f392fc9709a3	657	}
AnnaBridge	189:f392fc9709a3	658
AnnaBridge	189:f392fc9709a3	659	/**
AnnaBridge	189:f392fc9709a3	660	* @brief Get polynomial for CRC calculation
AnnaBridge	189:f392fc9709a3	661	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
AnnaBridge	189:f392fc9709a3	662	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	663	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	189:f392fc9709a3	664	*/
AnnaBridge	189:f392fc9709a3	665	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	666	{
AnnaBridge	189:f392fc9709a3	667	return (uint32_t)(READ_REG(SPIx->CRCPR));
AnnaBridge	189:f392fc9709a3	668	}
AnnaBridge	189:f392fc9709a3	669
AnnaBridge	189:f392fc9709a3	670	/**
AnnaBridge	189:f392fc9709a3	671	* @brief Get Rx CRC
AnnaBridge	189:f392fc9709a3	672	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
AnnaBridge	189:f392fc9709a3	673	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	674	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	189:f392fc9709a3	675	*/
AnnaBridge	189:f392fc9709a3	676	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	677	{
AnnaBridge	189:f392fc9709a3	678	return (uint32_t)(READ_REG(SPIx->RXCRCR));
AnnaBridge	189:f392fc9709a3	679	}
AnnaBridge	189:f392fc9709a3	680
AnnaBridge	189:f392fc9709a3	681	/**
AnnaBridge	189:f392fc9709a3	682	* @brief Get Tx CRC
AnnaBridge	189:f392fc9709a3	683	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
AnnaBridge	189:f392fc9709a3	684	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	685	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	189:f392fc9709a3	686	*/
AnnaBridge	189:f392fc9709a3	687	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	688	{
AnnaBridge	189:f392fc9709a3	689	return (uint32_t)(READ_REG(SPIx->TXCRCR));
AnnaBridge	189:f392fc9709a3	690	}
AnnaBridge	189:f392fc9709a3	691
AnnaBridge	189:f392fc9709a3	692	/**
AnnaBridge	189:f392fc9709a3	693	* @}
AnnaBridge	189:f392fc9709a3	694	*/
AnnaBridge	189:f392fc9709a3	695
AnnaBridge	189:f392fc9709a3	696	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
AnnaBridge	189:f392fc9709a3	697	* @{
AnnaBridge	189:f392fc9709a3	698	*/
AnnaBridge	189:f392fc9709a3	699
AnnaBridge	189:f392fc9709a3	700	/**
AnnaBridge	189:f392fc9709a3	701	* @brief Set NSS mode
AnnaBridge	189:f392fc9709a3	702	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
AnnaBridge	189:f392fc9709a3	703	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
AnnaBridge	189:f392fc9709a3	704	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
AnnaBridge	189:f392fc9709a3	705	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	706	* @param NSS This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	707	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	189:f392fc9709a3	708	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	189:f392fc9709a3	709	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	189:f392fc9709a3	710	* @retval None
AnnaBridge	189:f392fc9709a3	711	*/
AnnaBridge	189:f392fc9709a3	712	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
AnnaBridge	189:f392fc9709a3	713	{
AnnaBridge	189:f392fc9709a3	714	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
AnnaBridge	189:f392fc9709a3	715	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
AnnaBridge	189:f392fc9709a3	716	}
AnnaBridge	189:f392fc9709a3	717
AnnaBridge	189:f392fc9709a3	718	/**
AnnaBridge	189:f392fc9709a3	719	* @brief Get NSS mode
AnnaBridge	189:f392fc9709a3	720	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
AnnaBridge	189:f392fc9709a3	721	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
AnnaBridge	189:f392fc9709a3	722	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	723	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	724	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	189:f392fc9709a3	725	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	189:f392fc9709a3	726	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	189:f392fc9709a3	727	*/
AnnaBridge	189:f392fc9709a3	728	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	729	{
AnnaBridge	189:f392fc9709a3	730	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
AnnaBridge	189:f392fc9709a3	731	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
AnnaBridge	189:f392fc9709a3	732	return (Ssm \| Ssoe);
AnnaBridge	189:f392fc9709a3	733	}
AnnaBridge	189:f392fc9709a3	734
AnnaBridge	189:f392fc9709a3	735	/**
AnnaBridge	189:f392fc9709a3	736	* @}
AnnaBridge	189:f392fc9709a3	737	*/
AnnaBridge	189:f392fc9709a3	738
AnnaBridge	189:f392fc9709a3	739	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
AnnaBridge	189:f392fc9709a3	740	* @{
AnnaBridge	189:f392fc9709a3	741	*/
AnnaBridge	189:f392fc9709a3	742
AnnaBridge	189:f392fc9709a3	743	/**
AnnaBridge	189:f392fc9709a3	744	* @brief Check if Rx buffer is not empty
AnnaBridge	189:f392fc9709a3	745	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
AnnaBridge	189:f392fc9709a3	746	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	747	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	748	*/
AnnaBridge	189:f392fc9709a3	749	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	750	{
AnnaBridge	189:f392fc9709a3	751	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
AnnaBridge	189:f392fc9709a3	752	}
AnnaBridge	189:f392fc9709a3	753
AnnaBridge	189:f392fc9709a3	754	/**
AnnaBridge	189:f392fc9709a3	755	* @brief Check if Tx buffer is empty
AnnaBridge	189:f392fc9709a3	756	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
AnnaBridge	189:f392fc9709a3	757	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	758	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	759	*/
AnnaBridge	189:f392fc9709a3	760	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	761	{
AnnaBridge	189:f392fc9709a3	762	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
AnnaBridge	189:f392fc9709a3	763	}
AnnaBridge	189:f392fc9709a3	764
AnnaBridge	189:f392fc9709a3	765	/**
AnnaBridge	189:f392fc9709a3	766	* @brief Get CRC error flag
AnnaBridge	189:f392fc9709a3	767	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
AnnaBridge	189:f392fc9709a3	768	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	769	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	770	*/
AnnaBridge	189:f392fc9709a3	771	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	772	{
AnnaBridge	189:f392fc9709a3	773	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
AnnaBridge	189:f392fc9709a3	774	}
AnnaBridge	189:f392fc9709a3	775
AnnaBridge	189:f392fc9709a3	776	/**
AnnaBridge	189:f392fc9709a3	777	* @brief Get mode fault error flag
AnnaBridge	189:f392fc9709a3	778	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
AnnaBridge	189:f392fc9709a3	779	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	780	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	781	*/
AnnaBridge	189:f392fc9709a3	782	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	783	{
AnnaBridge	189:f392fc9709a3	784	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
AnnaBridge	189:f392fc9709a3	785	}
AnnaBridge	189:f392fc9709a3	786
AnnaBridge	189:f392fc9709a3	787	/**
AnnaBridge	189:f392fc9709a3	788	* @brief Get overrun error flag
AnnaBridge	189:f392fc9709a3	789	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
AnnaBridge	189:f392fc9709a3	790	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	791	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	792	*/
AnnaBridge	189:f392fc9709a3	793	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	794	{
AnnaBridge	189:f392fc9709a3	795	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
AnnaBridge	189:f392fc9709a3	796	}
AnnaBridge	189:f392fc9709a3	797
AnnaBridge	189:f392fc9709a3	798	/**
AnnaBridge	189:f392fc9709a3	799	* @brief Get busy flag
AnnaBridge	189:f392fc9709a3	800	* @note The BSY flag is cleared under any one of the following conditions:
AnnaBridge	189:f392fc9709a3	801	* -When the SPI is correctly disabled
AnnaBridge	189:f392fc9709a3	802	* -When a fault is detected in Master mode (MODF bit set to 1)
AnnaBridge	189:f392fc9709a3	803	* -In Master mode, when it finishes a data transmission and no new data is ready to be
AnnaBridge	189:f392fc9709a3	804	* sent
AnnaBridge	189:f392fc9709a3	805	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
AnnaBridge	189:f392fc9709a3	806	* each data transfer.
AnnaBridge	189:f392fc9709a3	807	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
AnnaBridge	189:f392fc9709a3	808	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	809	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	810	*/
AnnaBridge	189:f392fc9709a3	811	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	812	{
AnnaBridge	189:f392fc9709a3	813	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
AnnaBridge	189:f392fc9709a3	814	}
AnnaBridge	189:f392fc9709a3	815
AnnaBridge	189:f392fc9709a3	816	/**
AnnaBridge	189:f392fc9709a3	817	* @brief Get frame format error flag
AnnaBridge	189:f392fc9709a3	818	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
AnnaBridge	189:f392fc9709a3	819	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	820	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	821	*/
AnnaBridge	189:f392fc9709a3	822	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	823	{
AnnaBridge	189:f392fc9709a3	824	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
AnnaBridge	189:f392fc9709a3	825	}
AnnaBridge	189:f392fc9709a3	826
AnnaBridge	189:f392fc9709a3	827	/**
AnnaBridge	189:f392fc9709a3	828	* @brief Clear CRC error flag
AnnaBridge	189:f392fc9709a3	829	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
AnnaBridge	189:f392fc9709a3	830	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	831	* @retval None
AnnaBridge	189:f392fc9709a3	832	*/
AnnaBridge	189:f392fc9709a3	833	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	834	{
AnnaBridge	189:f392fc9709a3	835	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
AnnaBridge	189:f392fc9709a3	836	}
AnnaBridge	189:f392fc9709a3	837
AnnaBridge	189:f392fc9709a3	838	/**
AnnaBridge	189:f392fc9709a3	839	* @brief Clear mode fault error flag
AnnaBridge	189:f392fc9709a3	840	* @note Clearing this flag is done by a read access to the SPIx_SR
AnnaBridge	189:f392fc9709a3	841	* register followed by a write access to the SPIx_CR1 register
AnnaBridge	189:f392fc9709a3	842	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
AnnaBridge	189:f392fc9709a3	843	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	844	* @retval None
AnnaBridge	189:f392fc9709a3	845	*/
AnnaBridge	189:f392fc9709a3	846	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	847	{
AnnaBridge	189:f392fc9709a3	848	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	849	tmpreg = SPIx->SR;
AnnaBridge	189:f392fc9709a3	850	(void) tmpreg;
AnnaBridge	189:f392fc9709a3	851	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	189:f392fc9709a3	852	(void) tmpreg;
AnnaBridge	189:f392fc9709a3	853	}
AnnaBridge	189:f392fc9709a3	854
AnnaBridge	189:f392fc9709a3	855	/**
AnnaBridge	189:f392fc9709a3	856	* @brief Clear overrun error flag
AnnaBridge	189:f392fc9709a3	857	* @note Clearing this flag is done by a read access to the SPIx_DR
AnnaBridge	189:f392fc9709a3	858	* register followed by a read access to the SPIx_SR register
AnnaBridge	189:f392fc9709a3	859	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
AnnaBridge	189:f392fc9709a3	860	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	861	* @retval None
AnnaBridge	189:f392fc9709a3	862	*/
AnnaBridge	189:f392fc9709a3	863	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	864	{
AnnaBridge	189:f392fc9709a3	865	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	866	tmpreg = SPIx->DR;
AnnaBridge	189:f392fc9709a3	867	(void) tmpreg;
AnnaBridge	189:f392fc9709a3	868	tmpreg = SPIx->SR;
AnnaBridge	189:f392fc9709a3	869	(void) tmpreg;
AnnaBridge	189:f392fc9709a3	870	}
AnnaBridge	189:f392fc9709a3	871
AnnaBridge	189:f392fc9709a3	872	/**
AnnaBridge	189:f392fc9709a3	873	* @brief Clear frame format error flag
AnnaBridge	189:f392fc9709a3	874	* @note Clearing this flag is done by reading SPIx_SR register
AnnaBridge	189:f392fc9709a3	875	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
AnnaBridge	189:f392fc9709a3	876	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	877	* @retval None
AnnaBridge	189:f392fc9709a3	878	*/
AnnaBridge	189:f392fc9709a3	879	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	880	{
AnnaBridge	189:f392fc9709a3	881	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	882	tmpreg = SPIx->SR;
AnnaBridge	189:f392fc9709a3	883	(void) tmpreg;
AnnaBridge	189:f392fc9709a3	884	}
AnnaBridge	189:f392fc9709a3	885
AnnaBridge	189:f392fc9709a3	886	/**
AnnaBridge	189:f392fc9709a3	887	* @}
AnnaBridge	189:f392fc9709a3	888	*/
AnnaBridge	189:f392fc9709a3	889
AnnaBridge	189:f392fc9709a3	890	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
AnnaBridge	189:f392fc9709a3	891	* @{
AnnaBridge	189:f392fc9709a3	892	*/
AnnaBridge	189:f392fc9709a3	893
AnnaBridge	189:f392fc9709a3	894	/**
AnnaBridge	189:f392fc9709a3	895	* @brief Enable error interrupt
AnnaBridge	189:f392fc9709a3	896	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	189:f392fc9709a3	897	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
AnnaBridge	189:f392fc9709a3	898	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	899	* @retval None
AnnaBridge	189:f392fc9709a3	900	*/
AnnaBridge	189:f392fc9709a3	901	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	902	{
AnnaBridge	189:f392fc9709a3	903	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	189:f392fc9709a3	904	}
AnnaBridge	189:f392fc9709a3	905
AnnaBridge	189:f392fc9709a3	906	/**
AnnaBridge	189:f392fc9709a3	907	* @brief Enable Rx buffer not empty interrupt
AnnaBridge	189:f392fc9709a3	908	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
AnnaBridge	189:f392fc9709a3	909	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	910	* @retval None
AnnaBridge	189:f392fc9709a3	911	*/
AnnaBridge	189:f392fc9709a3	912	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	913	{
AnnaBridge	189:f392fc9709a3	914	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	189:f392fc9709a3	915	}
AnnaBridge	189:f392fc9709a3	916
AnnaBridge	189:f392fc9709a3	917	/**
AnnaBridge	189:f392fc9709a3	918	* @brief Enable Tx buffer empty interrupt
AnnaBridge	189:f392fc9709a3	919	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
AnnaBridge	189:f392fc9709a3	920	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	921	* @retval None
AnnaBridge	189:f392fc9709a3	922	*/
AnnaBridge	189:f392fc9709a3	923	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	924	{
AnnaBridge	189:f392fc9709a3	925	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	189:f392fc9709a3	926	}
AnnaBridge	189:f392fc9709a3	927
AnnaBridge	189:f392fc9709a3	928	/**
AnnaBridge	189:f392fc9709a3	929	* @brief Disable error interrupt
AnnaBridge	189:f392fc9709a3	930	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	189:f392fc9709a3	931	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
AnnaBridge	189:f392fc9709a3	932	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	933	* @retval None
AnnaBridge	189:f392fc9709a3	934	*/
AnnaBridge	189:f392fc9709a3	935	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	936	{
AnnaBridge	189:f392fc9709a3	937	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	189:f392fc9709a3	938	}
AnnaBridge	189:f392fc9709a3	939
AnnaBridge	189:f392fc9709a3	940	/**
AnnaBridge	189:f392fc9709a3	941	* @brief Disable Rx buffer not empty interrupt
AnnaBridge	189:f392fc9709a3	942	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
AnnaBridge	189:f392fc9709a3	943	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	944	* @retval None
AnnaBridge	189:f392fc9709a3	945	*/
AnnaBridge	189:f392fc9709a3	946	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	947	{
AnnaBridge	189:f392fc9709a3	948	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	189:f392fc9709a3	949	}
AnnaBridge	189:f392fc9709a3	950
AnnaBridge	189:f392fc9709a3	951	/**
AnnaBridge	189:f392fc9709a3	952	* @brief Disable Tx buffer empty interrupt
AnnaBridge	189:f392fc9709a3	953	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
AnnaBridge	189:f392fc9709a3	954	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	955	* @retval None
AnnaBridge	189:f392fc9709a3	956	*/
AnnaBridge	189:f392fc9709a3	957	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	958	{
AnnaBridge	189:f392fc9709a3	959	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	189:f392fc9709a3	960	}
AnnaBridge	189:f392fc9709a3	961
AnnaBridge	189:f392fc9709a3	962	/**
AnnaBridge	189:f392fc9709a3	963	* @brief Check if error interrupt is enabled
AnnaBridge	189:f392fc9709a3	964	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
AnnaBridge	189:f392fc9709a3	965	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	966	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	967	*/
AnnaBridge	189:f392fc9709a3	968	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	969	{
AnnaBridge	189:f392fc9709a3	970	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
AnnaBridge	189:f392fc9709a3	971	}
AnnaBridge	189:f392fc9709a3	972
AnnaBridge	189:f392fc9709a3	973	/**
AnnaBridge	189:f392fc9709a3	974	* @brief Check if Rx buffer not empty interrupt is enabled
AnnaBridge	189:f392fc9709a3	975	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
AnnaBridge	189:f392fc9709a3	976	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	977	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	978	*/
AnnaBridge	189:f392fc9709a3	979	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	980	{
AnnaBridge	189:f392fc9709a3	981	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
AnnaBridge	189:f392fc9709a3	982	}
AnnaBridge	189:f392fc9709a3	983
AnnaBridge	189:f392fc9709a3	984	/**
AnnaBridge	189:f392fc9709a3	985	* @brief Check if Tx buffer empty interrupt
AnnaBridge	189:f392fc9709a3	986	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
AnnaBridge	189:f392fc9709a3	987	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	988	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	989	*/
AnnaBridge	189:f392fc9709a3	990	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	991	{
AnnaBridge	189:f392fc9709a3	992	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
AnnaBridge	189:f392fc9709a3	993	}
AnnaBridge	189:f392fc9709a3	994
AnnaBridge	189:f392fc9709a3	995	/**
AnnaBridge	189:f392fc9709a3	996	* @}
AnnaBridge	189:f392fc9709a3	997	*/
AnnaBridge	189:f392fc9709a3	998
AnnaBridge	189:f392fc9709a3	999	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
AnnaBridge	189:f392fc9709a3	1000	* @{
AnnaBridge	189:f392fc9709a3	1001	*/
AnnaBridge	189:f392fc9709a3	1002
AnnaBridge	189:f392fc9709a3	1003	/**
AnnaBridge	189:f392fc9709a3	1004	* @brief Enable DMA Rx
AnnaBridge	189:f392fc9709a3	1005	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
AnnaBridge	189:f392fc9709a3	1006	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1007	* @retval None
AnnaBridge	189:f392fc9709a3	1008	*/
AnnaBridge	189:f392fc9709a3	1009	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1010	{
AnnaBridge	189:f392fc9709a3	1011	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	189:f392fc9709a3	1012	}
AnnaBridge	189:f392fc9709a3	1013
AnnaBridge	189:f392fc9709a3	1014	/**
AnnaBridge	189:f392fc9709a3	1015	* @brief Disable DMA Rx
AnnaBridge	189:f392fc9709a3	1016	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
AnnaBridge	189:f392fc9709a3	1017	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1018	* @retval None
AnnaBridge	189:f392fc9709a3	1019	*/
AnnaBridge	189:f392fc9709a3	1020	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1021	{
AnnaBridge	189:f392fc9709a3	1022	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	189:f392fc9709a3	1023	}
AnnaBridge	189:f392fc9709a3	1024
AnnaBridge	189:f392fc9709a3	1025	/**
AnnaBridge	189:f392fc9709a3	1026	* @brief Check if DMA Rx is enabled
AnnaBridge	189:f392fc9709a3	1027	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
AnnaBridge	189:f392fc9709a3	1028	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1029	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1030	*/
AnnaBridge	189:f392fc9709a3	1031	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1032	{
AnnaBridge	189:f392fc9709a3	1033	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
AnnaBridge	189:f392fc9709a3	1034	}
AnnaBridge	189:f392fc9709a3	1035
AnnaBridge	189:f392fc9709a3	1036	/**
AnnaBridge	189:f392fc9709a3	1037	* @brief Enable DMA Tx
AnnaBridge	189:f392fc9709a3	1038	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
AnnaBridge	189:f392fc9709a3	1039	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1040	* @retval None
AnnaBridge	189:f392fc9709a3	1041	*/
AnnaBridge	189:f392fc9709a3	1042	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1043	{
AnnaBridge	189:f392fc9709a3	1044	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	189:f392fc9709a3	1045	}
AnnaBridge	189:f392fc9709a3	1046
AnnaBridge	189:f392fc9709a3	1047	/**
AnnaBridge	189:f392fc9709a3	1048	* @brief Disable DMA Tx
AnnaBridge	189:f392fc9709a3	1049	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
AnnaBridge	189:f392fc9709a3	1050	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1051	* @retval None
AnnaBridge	189:f392fc9709a3	1052	*/
AnnaBridge	189:f392fc9709a3	1053	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1054	{
AnnaBridge	189:f392fc9709a3	1055	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	189:f392fc9709a3	1056	}
AnnaBridge	189:f392fc9709a3	1057
AnnaBridge	189:f392fc9709a3	1058	/**
AnnaBridge	189:f392fc9709a3	1059	* @brief Check if DMA Tx is enabled
AnnaBridge	189:f392fc9709a3	1060	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
AnnaBridge	189:f392fc9709a3	1061	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1062	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1063	*/
AnnaBridge	189:f392fc9709a3	1064	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1065	{
AnnaBridge	189:f392fc9709a3	1066	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
AnnaBridge	189:f392fc9709a3	1067	}
AnnaBridge	189:f392fc9709a3	1068
AnnaBridge	189:f392fc9709a3	1069	/**
AnnaBridge	189:f392fc9709a3	1070	* @brief Get the data register address used for DMA transfer
AnnaBridge	189:f392fc9709a3	1071	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
AnnaBridge	189:f392fc9709a3	1072	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1073	* @retval Address of data register
AnnaBridge	189:f392fc9709a3	1074	*/
AnnaBridge	189:f392fc9709a3	1075	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1076	{
AnnaBridge	189:f392fc9709a3	1077	return (uint32_t) & (SPIx->DR);
AnnaBridge	189:f392fc9709a3	1078	}
AnnaBridge	189:f392fc9709a3	1079
AnnaBridge	189:f392fc9709a3	1080	/**
AnnaBridge	189:f392fc9709a3	1081	* @}
AnnaBridge	189:f392fc9709a3	1082	*/
AnnaBridge	189:f392fc9709a3	1083
AnnaBridge	189:f392fc9709a3	1084	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
AnnaBridge	189:f392fc9709a3	1085	* @{
AnnaBridge	189:f392fc9709a3	1086	*/
AnnaBridge	189:f392fc9709a3	1087
AnnaBridge	189:f392fc9709a3	1088	/**
AnnaBridge	189:f392fc9709a3	1089	* @brief Read 8-Bits in the data register
AnnaBridge	189:f392fc9709a3	1090	* @rmtoll DR DR LL_SPI_ReceiveData8
AnnaBridge	189:f392fc9709a3	1091	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1092	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	1093	*/
AnnaBridge	189:f392fc9709a3	1094	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1095	{
AnnaBridge	189:f392fc9709a3	1096	return (uint8_t)(READ_REG(SPIx->DR));
AnnaBridge	189:f392fc9709a3	1097	}
AnnaBridge	189:f392fc9709a3	1098
AnnaBridge	189:f392fc9709a3	1099	/**
AnnaBridge	189:f392fc9709a3	1100	* @brief Read 16-Bits in the data register
AnnaBridge	189:f392fc9709a3	1101	* @rmtoll DR DR LL_SPI_ReceiveData16
AnnaBridge	189:f392fc9709a3	1102	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1103	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	189:f392fc9709a3	1104	*/
AnnaBridge	189:f392fc9709a3	1105	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1106	{
AnnaBridge	189:f392fc9709a3	1107	return (uint16_t)(READ_REG(SPIx->DR));
AnnaBridge	189:f392fc9709a3	1108	}
AnnaBridge	189:f392fc9709a3	1109
AnnaBridge	189:f392fc9709a3	1110	/**
AnnaBridge	189:f392fc9709a3	1111	* @brief Write 8-Bits in the data register
AnnaBridge	189:f392fc9709a3	1112	* @rmtoll DR DR LL_SPI_TransmitData8
AnnaBridge	189:f392fc9709a3	1113	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1114	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	1115	* @retval None
AnnaBridge	189:f392fc9709a3	1116	*/
AnnaBridge	189:f392fc9709a3	1117	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
AnnaBridge	189:f392fc9709a3	1118	{
AnnaBridge	189:f392fc9709a3	1119	((__IO uint8_t )&SPIx->DR) = TxData;
AnnaBridge	189:f392fc9709a3	1120	}
AnnaBridge	189:f392fc9709a3	1121
AnnaBridge	189:f392fc9709a3	1122	#if __GNUC__
AnnaBridge	189:f392fc9709a3	1123	# define MAY_ALIAS __attribute__ ((__may_alias__))
AnnaBridge	189:f392fc9709a3	1124	#else
AnnaBridge	189:f392fc9709a3	1125	# define MAY_ALIAS
AnnaBridge	189:f392fc9709a3	1126	#endif
AnnaBridge	189:f392fc9709a3	1127
AnnaBridge	189:f392fc9709a3	1128	typedef __IO uint16_t MAY_ALIAS uint16_io_t;
AnnaBridge	189:f392fc9709a3	1129
AnnaBridge	189:f392fc9709a3	1130	/**
AnnaBridge	189:f392fc9709a3	1131	* @brief Write 16-Bits in the data register
AnnaBridge	189:f392fc9709a3	1132	* @rmtoll DR DR LL_SPI_TransmitData16
AnnaBridge	189:f392fc9709a3	1133	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1134	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	189:f392fc9709a3	1135	* @retval None
AnnaBridge	189:f392fc9709a3	1136	*/
AnnaBridge	189:f392fc9709a3	1137	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	189:f392fc9709a3	1138	{
AnnaBridge	189:f392fc9709a3	1139	((uint16_io_t)&SPIx->DR) = TxData;
AnnaBridge	189:f392fc9709a3	1140	}
AnnaBridge	189:f392fc9709a3	1141
AnnaBridge	189:f392fc9709a3	1142	/**
AnnaBridge	189:f392fc9709a3	1143	* @}
AnnaBridge	189:f392fc9709a3	1144	*/
AnnaBridge	189:f392fc9709a3	1145	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	1146	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	189:f392fc9709a3	1147	* @{
AnnaBridge	189:f392fc9709a3	1148	*/
AnnaBridge	189:f392fc9709a3	1149
AnnaBridge	189:f392fc9709a3	1150	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	189:f392fc9709a3	1151	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
AnnaBridge	189:f392fc9709a3	1152	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge	189:f392fc9709a3	1153
AnnaBridge	189:f392fc9709a3	1154	/**
AnnaBridge	189:f392fc9709a3	1155	* @}
AnnaBridge	189:f392fc9709a3	1156	*/
AnnaBridge	189:f392fc9709a3	1157	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	1158	/**
AnnaBridge	189:f392fc9709a3	1159	* @}
AnnaBridge	189:f392fc9709a3	1160	*/
AnnaBridge	189:f392fc9709a3	1161
AnnaBridge	189:f392fc9709a3	1162	/**
AnnaBridge	189:f392fc9709a3	1163	* @}
AnnaBridge	189:f392fc9709a3	1164	*/
AnnaBridge	189:f392fc9709a3	1165
AnnaBridge	189:f392fc9709a3	1166	#if defined(SPI_I2S_SUPPORT)
AnnaBridge	189:f392fc9709a3	1167	/** @defgroup I2S_LL I2S
AnnaBridge	189:f392fc9709a3	1168	* @{
AnnaBridge	189:f392fc9709a3	1169	*/
AnnaBridge	189:f392fc9709a3	1170
AnnaBridge	189:f392fc9709a3	1171	/* Private variables ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1172	/* Private constants ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1173	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1174
AnnaBridge	189:f392fc9709a3	1175	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1176	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	1177	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
AnnaBridge	189:f392fc9709a3	1178	* @{
AnnaBridge	189:f392fc9709a3	1179	*/
AnnaBridge	189:f392fc9709a3	1180
AnnaBridge	189:f392fc9709a3	1181	/**
AnnaBridge	189:f392fc9709a3	1182	* @brief I2S Init structure definition
AnnaBridge	189:f392fc9709a3	1183	*/
AnnaBridge	189:f392fc9709a3	1184
AnnaBridge	189:f392fc9709a3	1185	typedef struct
AnnaBridge	189:f392fc9709a3	1186	{
AnnaBridge	189:f392fc9709a3	1187	uint32_t Mode; /*!< Specifies the I2S operating mode.
AnnaBridge	189:f392fc9709a3	1188	This parameter can be a value of @ref I2S_LL_EC_MODE
AnnaBridge	189:f392fc9709a3	1189
AnnaBridge	189:f392fc9709a3	1190	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
AnnaBridge	189:f392fc9709a3	1191
AnnaBridge	189:f392fc9709a3	1192	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
AnnaBridge	189:f392fc9709a3	1193	This parameter can be a value of @ref I2S_LL_EC_STANDARD
AnnaBridge	189:f392fc9709a3	1194
AnnaBridge	189:f392fc9709a3	1195	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
AnnaBridge	189:f392fc9709a3	1196
AnnaBridge	189:f392fc9709a3	1197
AnnaBridge	189:f392fc9709a3	1198	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
AnnaBridge	189:f392fc9709a3	1199	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
AnnaBridge	189:f392fc9709a3	1200
AnnaBridge	189:f392fc9709a3	1201	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
AnnaBridge	189:f392fc9709a3	1202
AnnaBridge	189:f392fc9709a3	1203
AnnaBridge	189:f392fc9709a3	1204	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
AnnaBridge	189:f392fc9709a3	1205	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
AnnaBridge	189:f392fc9709a3	1206
AnnaBridge	189:f392fc9709a3	1207	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
AnnaBridge	189:f392fc9709a3	1208
AnnaBridge	189:f392fc9709a3	1209
AnnaBridge	189:f392fc9709a3	1210	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
AnnaBridge	189:f392fc9709a3	1211	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
AnnaBridge	189:f392fc9709a3	1212
AnnaBridge	189:f392fc9709a3	1213	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
AnnaBridge	189:f392fc9709a3	1214	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
AnnaBridge	189:f392fc9709a3	1215
AnnaBridge	189:f392fc9709a3	1216
AnnaBridge	189:f392fc9709a3	1217	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
AnnaBridge	189:f392fc9709a3	1218	This parameter can be a value of @ref I2S_LL_EC_POLARITY
AnnaBridge	189:f392fc9709a3	1219
AnnaBridge	189:f392fc9709a3	1220	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
AnnaBridge	189:f392fc9709a3	1221
AnnaBridge	189:f392fc9709a3	1222	} LL_I2S_InitTypeDef;
AnnaBridge	189:f392fc9709a3	1223
AnnaBridge	189:f392fc9709a3	1224	/**
AnnaBridge	189:f392fc9709a3	1225	* @}
AnnaBridge	189:f392fc9709a3	1226	*/
AnnaBridge	189:f392fc9709a3	1227	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	189:f392fc9709a3	1228
AnnaBridge	189:f392fc9709a3	1229	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1230	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
AnnaBridge	189:f392fc9709a3	1231	* @{
AnnaBridge	189:f392fc9709a3	1232	*/
AnnaBridge	189:f392fc9709a3	1233
AnnaBridge	189:f392fc9709a3	1234	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	189:f392fc9709a3	1235	* @brief Flags defines which can be used with LL_I2S_ReadReg function
AnnaBridge	189:f392fc9709a3	1236	* @{
AnnaBridge	189:f392fc9709a3	1237	*/
AnnaBridge	189:f392fc9709a3	1238	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	189:f392fc9709a3	1239	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	189:f392fc9709a3	1240	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
AnnaBridge	189:f392fc9709a3	1241	#define LL_I2S_SR_UDR LL_SPI_SR_UDR /!< Underrun flag /
AnnaBridge	189:f392fc9709a3	1242	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
AnnaBridge	189:f392fc9709a3	1243	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	189:f392fc9709a3	1244	/**
AnnaBridge	189:f392fc9709a3	1245	* @}
AnnaBridge	189:f392fc9709a3	1246	*/
AnnaBridge	189:f392fc9709a3	1247
AnnaBridge	189:f392fc9709a3	1248	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	189:f392fc9709a3	1249	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	189:f392fc9709a3	1250	* @{
AnnaBridge	189:f392fc9709a3	1251	*/
AnnaBridge	189:f392fc9709a3	1252	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	189:f392fc9709a3	1253	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	189:f392fc9709a3	1254	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	189:f392fc9709a3	1255	/**
AnnaBridge	189:f392fc9709a3	1256	* @}
AnnaBridge	189:f392fc9709a3	1257	*/
AnnaBridge	189:f392fc9709a3	1258
AnnaBridge	189:f392fc9709a3	1259	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
AnnaBridge	189:f392fc9709a3	1260	* @{
AnnaBridge	189:f392fc9709a3	1261	*/
AnnaBridge	189:f392fc9709a3	1262	#define LL_I2S_DATAFORMAT_16B ((uint32_t)0x00000000U) /!< Data length 16 bits, Channel lenght 16bit /
AnnaBridge	189:f392fc9709a3	1263	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	189:f392fc9709a3	1264	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
AnnaBridge	189:f392fc9709a3	1265	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	189:f392fc9709a3	1266	/**
AnnaBridge	189:f392fc9709a3	1267	* @}
AnnaBridge	189:f392fc9709a3	1268	*/
AnnaBridge	189:f392fc9709a3	1269
AnnaBridge	189:f392fc9709a3	1270	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
AnnaBridge	189:f392fc9709a3	1271	* @{
AnnaBridge	189:f392fc9709a3	1272	*/
AnnaBridge	189:f392fc9709a3	1273	#define LL_I2S_POLARITY_LOW ((uint32_t)0x00000000U) /!< Clock steady state is low level /
AnnaBridge	189:f392fc9709a3	1274	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
AnnaBridge	189:f392fc9709a3	1275	/**
AnnaBridge	189:f392fc9709a3	1276	* @}
AnnaBridge	189:f392fc9709a3	1277	*/
AnnaBridge	189:f392fc9709a3	1278
AnnaBridge	189:f392fc9709a3	1279	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
AnnaBridge	189:f392fc9709a3	1280	* @{
AnnaBridge	189:f392fc9709a3	1281	*/
AnnaBridge	189:f392fc9709a3	1282	#define LL_I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U) /!< I2S standard philips /
AnnaBridge	189:f392fc9709a3	1283	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
AnnaBridge	189:f392fc9709a3	1284	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
AnnaBridge	189:f392fc9709a3	1285	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
AnnaBridge	189:f392fc9709a3	1286	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
AnnaBridge	189:f392fc9709a3	1287	/**
AnnaBridge	189:f392fc9709a3	1288	* @}
AnnaBridge	189:f392fc9709a3	1289	*/
AnnaBridge	189:f392fc9709a3	1290
AnnaBridge	189:f392fc9709a3	1291	/** @defgroup I2S_LL_EC_MODE Operation Mode
AnnaBridge	189:f392fc9709a3	1292	* @{
AnnaBridge	189:f392fc9709a3	1293	*/
AnnaBridge	189:f392fc9709a3	1294	#define LL_I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U) /!< Slave Tx configuration /
AnnaBridge	189:f392fc9709a3	1295	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
AnnaBridge	189:f392fc9709a3	1296	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
AnnaBridge	189:f392fc9709a3	1297	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
AnnaBridge	189:f392fc9709a3	1298	/**
AnnaBridge	189:f392fc9709a3	1299	* @}
AnnaBridge	189:f392fc9709a3	1300	*/
AnnaBridge	189:f392fc9709a3	1301
AnnaBridge	189:f392fc9709a3	1302	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
AnnaBridge	189:f392fc9709a3	1303	* @{
AnnaBridge	189:f392fc9709a3	1304	*/
AnnaBridge	189:f392fc9709a3	1305	#define LL_I2S_PRESCALER_PARITY_EVEN ((uint32_t)0x00000000U) /!< Odd factor: Real divider value is = I2SDIV 2 */
AnnaBridge	189:f392fc9709a3	1306	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
AnnaBridge	189:f392fc9709a3	1307	/**
AnnaBridge	189:f392fc9709a3	1308	* @}
AnnaBridge	189:f392fc9709a3	1309	*/
AnnaBridge	189:f392fc9709a3	1310
AnnaBridge	189:f392fc9709a3	1311	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	1312
AnnaBridge	189:f392fc9709a3	1313	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
AnnaBridge	189:f392fc9709a3	1314	* @{
AnnaBridge	189:f392fc9709a3	1315	*/
AnnaBridge	189:f392fc9709a3	1316	#define LL_I2S_MCLK_OUTPUT_DISABLE ((uint32_t)0x00000000U) /!< Master clock output is disabled /
AnnaBridge	189:f392fc9709a3	1317	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
AnnaBridge	189:f392fc9709a3	1318	/**
AnnaBridge	189:f392fc9709a3	1319	* @}
AnnaBridge	189:f392fc9709a3	1320	*/
AnnaBridge	189:f392fc9709a3	1321
AnnaBridge	189:f392fc9709a3	1322	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
AnnaBridge	189:f392fc9709a3	1323	* @{
AnnaBridge	189:f392fc9709a3	1324	*/
AnnaBridge	189:f392fc9709a3	1325
AnnaBridge	189:f392fc9709a3	1326	#define LL_I2S_AUDIOFREQ_192K ((uint32_t)192000) /!< Audio Frequency configuration 192000 Hz /
AnnaBridge	189:f392fc9709a3	1327	#define LL_I2S_AUDIOFREQ_96K ((uint32_t) 96000) /!< Audio Frequency configuration 96000 Hz /
AnnaBridge	189:f392fc9709a3	1328	#define LL_I2S_AUDIOFREQ_48K ((uint32_t) 48000) /!< Audio Frequency configuration 48000 Hz /
AnnaBridge	189:f392fc9709a3	1329	#define LL_I2S_AUDIOFREQ_44K ((uint32_t) 44100) /!< Audio Frequency configuration 44100 Hz /
AnnaBridge	189:f392fc9709a3	1330	#define LL_I2S_AUDIOFREQ_32K ((uint32_t) 32000) /!< Audio Frequency configuration 32000 Hz /
AnnaBridge	189:f392fc9709a3	1331	#define LL_I2S_AUDIOFREQ_22K ((uint32_t) 22050) /!< Audio Frequency configuration 22050 Hz /
AnnaBridge	189:f392fc9709a3	1332	#define LL_I2S_AUDIOFREQ_16K ((uint32_t) 16000) /!< Audio Frequency configuration 16000 Hz /
AnnaBridge	189:f392fc9709a3	1333	#define LL_I2S_AUDIOFREQ_11K ((uint32_t) 11025) /!< Audio Frequency configuration 11025 Hz /
AnnaBridge	189:f392fc9709a3	1334	#define LL_I2S_AUDIOFREQ_8K ((uint32_t) 8000) /!< Audio Frequency configuration 8000 Hz /
AnnaBridge	189:f392fc9709a3	1335	#define LL_I2S_AUDIOFREQ_DEFAULT ((uint32_t) 2) /!< Audio Freq not specified. Register I2SDIV = 2 /
AnnaBridge	189:f392fc9709a3	1336	/**
AnnaBridge	189:f392fc9709a3	1337	* @}
AnnaBridge	189:f392fc9709a3	1338	*/
AnnaBridge	189:f392fc9709a3	1339	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	1340
AnnaBridge	189:f392fc9709a3	1341	/**
AnnaBridge	189:f392fc9709a3	1342	* @}
AnnaBridge	189:f392fc9709a3	1343	*/
AnnaBridge	189:f392fc9709a3	1344
AnnaBridge	189:f392fc9709a3	1345	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1346	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
AnnaBridge	189:f392fc9709a3	1347	* @{
AnnaBridge	189:f392fc9709a3	1348	*/
AnnaBridge	189:f392fc9709a3	1349
AnnaBridge	189:f392fc9709a3	1350	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	189:f392fc9709a3	1351	* @{
AnnaBridge	189:f392fc9709a3	1352	*/
AnnaBridge	189:f392fc9709a3	1353
AnnaBridge	189:f392fc9709a3	1354	/**
AnnaBridge	189:f392fc9709a3	1355	* @brief Write a value in I2S register
AnnaBridge	189:f392fc9709a3	1356	* @param __INSTANCE__ I2S Instance
AnnaBridge	189:f392fc9709a3	1357	* @param __REG__ Register to be written
AnnaBridge	189:f392fc9709a3	1358	* @param __VALUE__ Value to be written in the register
AnnaBridge	189:f392fc9709a3	1359	* @retval None
AnnaBridge	189:f392fc9709a3	1360	*/
AnnaBridge	189:f392fc9709a3	1361	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	189:f392fc9709a3	1362
AnnaBridge	189:f392fc9709a3	1363	/**
AnnaBridge	189:f392fc9709a3	1364	* @brief Read a value in I2S register
AnnaBridge	189:f392fc9709a3	1365	* @param __INSTANCE__ I2S Instance
AnnaBridge	189:f392fc9709a3	1366	* @param __REG__ Register to be read
AnnaBridge	189:f392fc9709a3	1367	* @retval Register value
AnnaBridge	189:f392fc9709a3	1368	*/
AnnaBridge	189:f392fc9709a3	1369	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	189:f392fc9709a3	1370	/**
AnnaBridge	189:f392fc9709a3	1371	* @}
AnnaBridge	189:f392fc9709a3	1372	*/
AnnaBridge	189:f392fc9709a3	1373
AnnaBridge	189:f392fc9709a3	1374	/**
AnnaBridge	189:f392fc9709a3	1375	* @}
AnnaBridge	189:f392fc9709a3	1376	*/
AnnaBridge	189:f392fc9709a3	1377
AnnaBridge	189:f392fc9709a3	1378
AnnaBridge	189:f392fc9709a3	1379	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1380
AnnaBridge	189:f392fc9709a3	1381	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
AnnaBridge	189:f392fc9709a3	1382	* @{
AnnaBridge	189:f392fc9709a3	1383	*/
AnnaBridge	189:f392fc9709a3	1384
AnnaBridge	189:f392fc9709a3	1385	/** @defgroup I2S_LL_EF_Configuration Configuration
AnnaBridge	189:f392fc9709a3	1386	* @{
AnnaBridge	189:f392fc9709a3	1387	*/
AnnaBridge	189:f392fc9709a3	1388
AnnaBridge	189:f392fc9709a3	1389	/**
AnnaBridge	189:f392fc9709a3	1390	* @brief Select I2S mode and Enable I2S peripheral
AnnaBridge	189:f392fc9709a3	1391	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
AnnaBridge	189:f392fc9709a3	1392	* I2SCFGR I2SE LL_I2S_Enable
AnnaBridge	189:f392fc9709a3	1393	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1394	* @retval None
AnnaBridge	189:f392fc9709a3	1395	*/
AnnaBridge	189:f392fc9709a3	1396	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1397	{
AnnaBridge	189:f392fc9709a3	1398	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	189:f392fc9709a3	1399	}
AnnaBridge	189:f392fc9709a3	1400
AnnaBridge	189:f392fc9709a3	1401	/**
AnnaBridge	189:f392fc9709a3	1402	* @brief Disable I2S peripheral
AnnaBridge	189:f392fc9709a3	1403	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
AnnaBridge	189:f392fc9709a3	1404	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1405	* @retval None
AnnaBridge	189:f392fc9709a3	1406	*/
AnnaBridge	189:f392fc9709a3	1407	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1408	{
AnnaBridge	189:f392fc9709a3	1409	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	189:f392fc9709a3	1410	}
AnnaBridge	189:f392fc9709a3	1411
AnnaBridge	189:f392fc9709a3	1412	/**
AnnaBridge	189:f392fc9709a3	1413	* @brief Check if I2S peripheral is enabled
AnnaBridge	189:f392fc9709a3	1414	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
AnnaBridge	189:f392fc9709a3	1415	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1416	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1417	*/
AnnaBridge	189:f392fc9709a3	1418	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1419	{
AnnaBridge	189:f392fc9709a3	1420	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
AnnaBridge	189:f392fc9709a3	1421	}
AnnaBridge	189:f392fc9709a3	1422
AnnaBridge	189:f392fc9709a3	1423	/**
AnnaBridge	189:f392fc9709a3	1424	* @brief Set I2S data frame length
AnnaBridge	189:f392fc9709a3	1425	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
AnnaBridge	189:f392fc9709a3	1426	* I2SCFGR CHLEN LL_I2S_SetDataFormat
AnnaBridge	189:f392fc9709a3	1427	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1428	* @param DataFormat This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1429	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	189:f392fc9709a3	1430	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	189:f392fc9709a3	1431	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	189:f392fc9709a3	1432	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	189:f392fc9709a3	1433	* @retval None
AnnaBridge	189:f392fc9709a3	1434	*/
AnnaBridge	189:f392fc9709a3	1435	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
AnnaBridge	189:f392fc9709a3	1436	{
AnnaBridge	189:f392fc9709a3	1437	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
AnnaBridge	189:f392fc9709a3	1438	}
AnnaBridge	189:f392fc9709a3	1439
AnnaBridge	189:f392fc9709a3	1440	/**
AnnaBridge	189:f392fc9709a3	1441	* @brief Get I2S data frame length
AnnaBridge	189:f392fc9709a3	1442	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
AnnaBridge	189:f392fc9709a3	1443	* I2SCFGR CHLEN LL_I2S_GetDataFormat
AnnaBridge	189:f392fc9709a3	1444	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1445	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1446	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	189:f392fc9709a3	1447	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	189:f392fc9709a3	1448	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	189:f392fc9709a3	1449	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	189:f392fc9709a3	1450	*/
AnnaBridge	189:f392fc9709a3	1451	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1452	{
AnnaBridge	189:f392fc9709a3	1453	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
AnnaBridge	189:f392fc9709a3	1454	}
AnnaBridge	189:f392fc9709a3	1455
AnnaBridge	189:f392fc9709a3	1456	/**
AnnaBridge	189:f392fc9709a3	1457	* @brief Set I2S clock polarity
AnnaBridge	189:f392fc9709a3	1458	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
AnnaBridge	189:f392fc9709a3	1459	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1460	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1461	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	189:f392fc9709a3	1462	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	189:f392fc9709a3	1463	* @retval None
AnnaBridge	189:f392fc9709a3	1464	*/
AnnaBridge	189:f392fc9709a3	1465	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	189:f392fc9709a3	1466	{
AnnaBridge	189:f392fc9709a3	1467	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
AnnaBridge	189:f392fc9709a3	1468	}
AnnaBridge	189:f392fc9709a3	1469
AnnaBridge	189:f392fc9709a3	1470	/**
AnnaBridge	189:f392fc9709a3	1471	* @brief Get I2S clock polarity
AnnaBridge	189:f392fc9709a3	1472	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
AnnaBridge	189:f392fc9709a3	1473	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1474	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1475	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	189:f392fc9709a3	1476	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	189:f392fc9709a3	1477	*/
AnnaBridge	189:f392fc9709a3	1478	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1479	{
AnnaBridge	189:f392fc9709a3	1480	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
AnnaBridge	189:f392fc9709a3	1481	}
AnnaBridge	189:f392fc9709a3	1482
AnnaBridge	189:f392fc9709a3	1483	/**
AnnaBridge	189:f392fc9709a3	1484	* @brief Set I2S standard protocol
AnnaBridge	189:f392fc9709a3	1485	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
AnnaBridge	189:f392fc9709a3	1486	* I2SCFGR PCMSYNC LL_I2S_SetStandard
AnnaBridge	189:f392fc9709a3	1487	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1488	* @param Standard This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1489	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	189:f392fc9709a3	1490	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	189:f392fc9709a3	1491	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	189:f392fc9709a3	1492	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	189:f392fc9709a3	1493	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	189:f392fc9709a3	1494	* @retval None
AnnaBridge	189:f392fc9709a3	1495	*/
AnnaBridge	189:f392fc9709a3	1496	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	189:f392fc9709a3	1497	{
AnnaBridge	189:f392fc9709a3	1498	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
AnnaBridge	189:f392fc9709a3	1499	}
AnnaBridge	189:f392fc9709a3	1500
AnnaBridge	189:f392fc9709a3	1501	/**
AnnaBridge	189:f392fc9709a3	1502	* @brief Get I2S standard protocol
AnnaBridge	189:f392fc9709a3	1503	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
AnnaBridge	189:f392fc9709a3	1504	* I2SCFGR PCMSYNC LL_I2S_GetStandard
AnnaBridge	189:f392fc9709a3	1505	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1506	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1507	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	189:f392fc9709a3	1508	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	189:f392fc9709a3	1509	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	189:f392fc9709a3	1510	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	189:f392fc9709a3	1511	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	189:f392fc9709a3	1512	*/
AnnaBridge	189:f392fc9709a3	1513	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1514	{
AnnaBridge	189:f392fc9709a3	1515	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
AnnaBridge	189:f392fc9709a3	1516	}
AnnaBridge	189:f392fc9709a3	1517
AnnaBridge	189:f392fc9709a3	1518	/**
AnnaBridge	189:f392fc9709a3	1519	* @brief Set I2S transfer mode
AnnaBridge	189:f392fc9709a3	1520	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
AnnaBridge	189:f392fc9709a3	1521	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1522	* @param Mode This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1523	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	189:f392fc9709a3	1524	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	189:f392fc9709a3	1525	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	189:f392fc9709a3	1526	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	189:f392fc9709a3	1527	* @retval None
AnnaBridge	189:f392fc9709a3	1528	*/
AnnaBridge	189:f392fc9709a3	1529	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	189:f392fc9709a3	1530	{
AnnaBridge	189:f392fc9709a3	1531	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
AnnaBridge	189:f392fc9709a3	1532	}
AnnaBridge	189:f392fc9709a3	1533
AnnaBridge	189:f392fc9709a3	1534	/**
AnnaBridge	189:f392fc9709a3	1535	* @brief Get I2S transfer mode
AnnaBridge	189:f392fc9709a3	1536	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
AnnaBridge	189:f392fc9709a3	1537	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1538	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1539	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	189:f392fc9709a3	1540	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	189:f392fc9709a3	1541	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	189:f392fc9709a3	1542	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	189:f392fc9709a3	1543	*/
AnnaBridge	189:f392fc9709a3	1544	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1545	{
AnnaBridge	189:f392fc9709a3	1546	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
AnnaBridge	189:f392fc9709a3	1547	}
AnnaBridge	189:f392fc9709a3	1548
AnnaBridge	189:f392fc9709a3	1549	/**
AnnaBridge	189:f392fc9709a3	1550	* @brief Set I2S linear prescaler
AnnaBridge	189:f392fc9709a3	1551	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
AnnaBridge	189:f392fc9709a3	1552	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1553	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	1554	* @retval None
AnnaBridge	189:f392fc9709a3	1555	*/
AnnaBridge	189:f392fc9709a3	1556	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
AnnaBridge	189:f392fc9709a3	1557	{
AnnaBridge	189:f392fc9709a3	1558	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
AnnaBridge	189:f392fc9709a3	1559	}
AnnaBridge	189:f392fc9709a3	1560
AnnaBridge	189:f392fc9709a3	1561	/**
AnnaBridge	189:f392fc9709a3	1562	* @brief Get I2S linear prescaler
AnnaBridge	189:f392fc9709a3	1563	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
AnnaBridge	189:f392fc9709a3	1564	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1565	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	1566	*/
AnnaBridge	189:f392fc9709a3	1567	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1568	{
AnnaBridge	189:f392fc9709a3	1569	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
AnnaBridge	189:f392fc9709a3	1570	}
AnnaBridge	189:f392fc9709a3	1571
AnnaBridge	189:f392fc9709a3	1572	/**
AnnaBridge	189:f392fc9709a3	1573	* @brief Set I2S parity prescaler
AnnaBridge	189:f392fc9709a3	1574	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
AnnaBridge	189:f392fc9709a3	1575	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1576	* @param PrescalerParity This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1577	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	189:f392fc9709a3	1578	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	189:f392fc9709a3	1579	* @retval None
AnnaBridge	189:f392fc9709a3	1580	*/
AnnaBridge	189:f392fc9709a3	1581	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
AnnaBridge	189:f392fc9709a3	1582	{
AnnaBridge	189:f392fc9709a3	1583	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
AnnaBridge	189:f392fc9709a3	1584	}
AnnaBridge	189:f392fc9709a3	1585
AnnaBridge	189:f392fc9709a3	1586	/**
AnnaBridge	189:f392fc9709a3	1587	* @brief Get I2S parity prescaler
AnnaBridge	189:f392fc9709a3	1588	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
AnnaBridge	189:f392fc9709a3	1589	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1590	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1591	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	189:f392fc9709a3	1592	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	189:f392fc9709a3	1593	*/
AnnaBridge	189:f392fc9709a3	1594	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1595	{
AnnaBridge	189:f392fc9709a3	1596	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
AnnaBridge	189:f392fc9709a3	1597	}
AnnaBridge	189:f392fc9709a3	1598
AnnaBridge	189:f392fc9709a3	1599	/**
AnnaBridge	189:f392fc9709a3	1600	* @brief Enable the master clock ouput (Pin MCK)
AnnaBridge	189:f392fc9709a3	1601	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
AnnaBridge	189:f392fc9709a3	1602	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1603	* @retval None
AnnaBridge	189:f392fc9709a3	1604	*/
AnnaBridge	189:f392fc9709a3	1605	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1606	{
AnnaBridge	189:f392fc9709a3	1607	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	189:f392fc9709a3	1608	}
AnnaBridge	189:f392fc9709a3	1609
AnnaBridge	189:f392fc9709a3	1610	/**
AnnaBridge	189:f392fc9709a3	1611	* @brief Disable the master clock ouput (Pin MCK)
AnnaBridge	189:f392fc9709a3	1612	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
AnnaBridge	189:f392fc9709a3	1613	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1614	* @retval None
AnnaBridge	189:f392fc9709a3	1615	*/
AnnaBridge	189:f392fc9709a3	1616	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1617	{
AnnaBridge	189:f392fc9709a3	1618	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	189:f392fc9709a3	1619	}
AnnaBridge	189:f392fc9709a3	1620
AnnaBridge	189:f392fc9709a3	1621	/**
AnnaBridge	189:f392fc9709a3	1622	* @brief Check if the master clock ouput (Pin MCK) is enabled
AnnaBridge	189:f392fc9709a3	1623	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
AnnaBridge	189:f392fc9709a3	1624	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1625	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1626	*/
AnnaBridge	189:f392fc9709a3	1627	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1628	{
AnnaBridge	189:f392fc9709a3	1629	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
AnnaBridge	189:f392fc9709a3	1630	}
AnnaBridge	189:f392fc9709a3	1631
AnnaBridge	189:f392fc9709a3	1632	#if defined(SPI_I2SCFGR_ASTRTEN)
AnnaBridge	189:f392fc9709a3	1633	/**
AnnaBridge	189:f392fc9709a3	1634	* @brief Enable asynchronous start
AnnaBridge	189:f392fc9709a3	1635	* @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
AnnaBridge	189:f392fc9709a3	1636	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1637	* @retval None
AnnaBridge	189:f392fc9709a3	1638	*/
AnnaBridge	189:f392fc9709a3	1639	__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1640	{
AnnaBridge	189:f392fc9709a3	1641	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
AnnaBridge	189:f392fc9709a3	1642	}
AnnaBridge	189:f392fc9709a3	1643
AnnaBridge	189:f392fc9709a3	1644	/**
AnnaBridge	189:f392fc9709a3	1645	* @brief Disable asynchronous start
AnnaBridge	189:f392fc9709a3	1646	* @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
AnnaBridge	189:f392fc9709a3	1647	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1648	* @retval None
AnnaBridge	189:f392fc9709a3	1649	*/
AnnaBridge	189:f392fc9709a3	1650	__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1651	{
AnnaBridge	189:f392fc9709a3	1652	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
AnnaBridge	189:f392fc9709a3	1653	}
AnnaBridge	189:f392fc9709a3	1654
AnnaBridge	189:f392fc9709a3	1655	/**
AnnaBridge	189:f392fc9709a3	1656	* @brief Check if asynchronous start is enabled
AnnaBridge	189:f392fc9709a3	1657	* @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
AnnaBridge	189:f392fc9709a3	1658	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1659	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1660	*/
AnnaBridge	189:f392fc9709a3	1661	__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1662	{
AnnaBridge	189:f392fc9709a3	1663	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
AnnaBridge	189:f392fc9709a3	1664	}
AnnaBridge	189:f392fc9709a3	1665	#endif /* SPI_I2SCFGR_ASTRTEN */
AnnaBridge	189:f392fc9709a3	1666
AnnaBridge	189:f392fc9709a3	1667	/**
AnnaBridge	189:f392fc9709a3	1668	* @}
AnnaBridge	189:f392fc9709a3	1669	*/
AnnaBridge	189:f392fc9709a3	1670
AnnaBridge	189:f392fc9709a3	1671	/** @defgroup I2S_LL_EF_FLAG FLAG Management
AnnaBridge	189:f392fc9709a3	1672	* @{
AnnaBridge	189:f392fc9709a3	1673	*/
AnnaBridge	189:f392fc9709a3	1674
AnnaBridge	189:f392fc9709a3	1675	/**
AnnaBridge	189:f392fc9709a3	1676	* @brief Check if Rx buffer is not empty
AnnaBridge	189:f392fc9709a3	1677	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
AnnaBridge	189:f392fc9709a3	1678	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1679	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1680	*/
AnnaBridge	189:f392fc9709a3	1681	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1682	{
AnnaBridge	189:f392fc9709a3	1683	return LL_SPI_IsActiveFlag_RXNE(SPIx);
AnnaBridge	189:f392fc9709a3	1684	}
AnnaBridge	189:f392fc9709a3	1685
AnnaBridge	189:f392fc9709a3	1686	/**
AnnaBridge	189:f392fc9709a3	1687	* @brief Check if Tx buffer is empty
AnnaBridge	189:f392fc9709a3	1688	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
AnnaBridge	189:f392fc9709a3	1689	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1690	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1691	*/
AnnaBridge	189:f392fc9709a3	1692	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1693	{
AnnaBridge	189:f392fc9709a3	1694	return LL_SPI_IsActiveFlag_TXE(SPIx);
AnnaBridge	189:f392fc9709a3	1695	}
AnnaBridge	189:f392fc9709a3	1696
AnnaBridge	189:f392fc9709a3	1697	/**
AnnaBridge	189:f392fc9709a3	1698	* @brief Get busy flag
AnnaBridge	189:f392fc9709a3	1699	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
AnnaBridge	189:f392fc9709a3	1700	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1701	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1702	*/
AnnaBridge	189:f392fc9709a3	1703	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1704	{
AnnaBridge	189:f392fc9709a3	1705	return LL_SPI_IsActiveFlag_BSY(SPIx);
AnnaBridge	189:f392fc9709a3	1706	}
AnnaBridge	189:f392fc9709a3	1707
AnnaBridge	189:f392fc9709a3	1708	/**
AnnaBridge	189:f392fc9709a3	1709	* @brief Get overrun error flag
AnnaBridge	189:f392fc9709a3	1710	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
AnnaBridge	189:f392fc9709a3	1711	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1712	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1713	*/
AnnaBridge	189:f392fc9709a3	1714	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1715	{
AnnaBridge	189:f392fc9709a3	1716	return LL_SPI_IsActiveFlag_OVR(SPIx);
AnnaBridge	189:f392fc9709a3	1717	}
AnnaBridge	189:f392fc9709a3	1718
AnnaBridge	189:f392fc9709a3	1719	/**
AnnaBridge	189:f392fc9709a3	1720	* @brief Get underrun error flag
AnnaBridge	189:f392fc9709a3	1721	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
AnnaBridge	189:f392fc9709a3	1722	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1723	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1724	*/
AnnaBridge	189:f392fc9709a3	1725	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1726	{
AnnaBridge	189:f392fc9709a3	1727	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
AnnaBridge	189:f392fc9709a3	1728	}
AnnaBridge	189:f392fc9709a3	1729
AnnaBridge	189:f392fc9709a3	1730	/**
AnnaBridge	189:f392fc9709a3	1731	* @brief Get frame format error flag
AnnaBridge	189:f392fc9709a3	1732	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
AnnaBridge	189:f392fc9709a3	1733	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1734	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1735	*/
AnnaBridge	189:f392fc9709a3	1736	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1737	{
AnnaBridge	189:f392fc9709a3	1738	return LL_SPI_IsActiveFlag_FRE(SPIx);
AnnaBridge	189:f392fc9709a3	1739	}
AnnaBridge	189:f392fc9709a3	1740
AnnaBridge	189:f392fc9709a3	1741	/**
AnnaBridge	189:f392fc9709a3	1742	* @brief Get channel side flag.
AnnaBridge	189:f392fc9709a3	1743	* @note 0: Channel Left has to be transmitted or has been received\n
AnnaBridge	189:f392fc9709a3	1744	* 1: Channel Right has to be transmitted or has been received\n
AnnaBridge	189:f392fc9709a3	1745	* It has no significance in PCM mode.
AnnaBridge	189:f392fc9709a3	1746	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
AnnaBridge	189:f392fc9709a3	1747	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1748	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1749	*/
AnnaBridge	189:f392fc9709a3	1750	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1751	{
AnnaBridge	189:f392fc9709a3	1752	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
AnnaBridge	189:f392fc9709a3	1753	}
AnnaBridge	189:f392fc9709a3	1754
AnnaBridge	189:f392fc9709a3	1755	/**
AnnaBridge	189:f392fc9709a3	1756	* @brief Clear overrun error flag
AnnaBridge	189:f392fc9709a3	1757	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
AnnaBridge	189:f392fc9709a3	1758	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1759	* @retval None
AnnaBridge	189:f392fc9709a3	1760	*/
AnnaBridge	189:f392fc9709a3	1761	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1762	{
AnnaBridge	189:f392fc9709a3	1763	LL_SPI_ClearFlag_OVR(SPIx);
AnnaBridge	189:f392fc9709a3	1764	}
AnnaBridge	189:f392fc9709a3	1765
AnnaBridge	189:f392fc9709a3	1766	/**
AnnaBridge	189:f392fc9709a3	1767	* @brief Clear underrun error flag
AnnaBridge	189:f392fc9709a3	1768	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
AnnaBridge	189:f392fc9709a3	1769	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1770	* @retval None
AnnaBridge	189:f392fc9709a3	1771	*/
AnnaBridge	189:f392fc9709a3	1772	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1773	{
AnnaBridge	189:f392fc9709a3	1774	__IO uint32_t tmpreg;
AnnaBridge	189:f392fc9709a3	1775	tmpreg = SPIx->SR;
AnnaBridge	189:f392fc9709a3	1776	(void)tmpreg;
AnnaBridge	189:f392fc9709a3	1777	}
AnnaBridge	189:f392fc9709a3	1778
AnnaBridge	189:f392fc9709a3	1779	/**
AnnaBridge	189:f392fc9709a3	1780	* @brief Clear frame format error flag
AnnaBridge	189:f392fc9709a3	1781	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
AnnaBridge	189:f392fc9709a3	1782	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1783	* @retval None
AnnaBridge	189:f392fc9709a3	1784	*/
AnnaBridge	189:f392fc9709a3	1785	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1786	{
AnnaBridge	189:f392fc9709a3	1787	LL_SPI_ClearFlag_FRE(SPIx);
AnnaBridge	189:f392fc9709a3	1788	}
AnnaBridge	189:f392fc9709a3	1789
AnnaBridge	189:f392fc9709a3	1790	/**
AnnaBridge	189:f392fc9709a3	1791	* @}
AnnaBridge	189:f392fc9709a3	1792	*/
AnnaBridge	189:f392fc9709a3	1793
AnnaBridge	189:f392fc9709a3	1794	/** @defgroup I2S_LL_EF_IT Interrupt Management
AnnaBridge	189:f392fc9709a3	1795	* @{
AnnaBridge	189:f392fc9709a3	1796	*/
AnnaBridge	189:f392fc9709a3	1797
AnnaBridge	189:f392fc9709a3	1798	/**
AnnaBridge	189:f392fc9709a3	1799	* @brief Enable error IT
AnnaBridge	189:f392fc9709a3	1800	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	189:f392fc9709a3	1801	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
AnnaBridge	189:f392fc9709a3	1802	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1803	* @retval None
AnnaBridge	189:f392fc9709a3	1804	*/
AnnaBridge	189:f392fc9709a3	1805	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1806	{
AnnaBridge	189:f392fc9709a3	1807	LL_SPI_EnableIT_ERR(SPIx);
AnnaBridge	189:f392fc9709a3	1808	}
AnnaBridge	189:f392fc9709a3	1809
AnnaBridge	189:f392fc9709a3	1810	/**
AnnaBridge	189:f392fc9709a3	1811	* @brief Enable Rx buffer not empty IT
AnnaBridge	189:f392fc9709a3	1812	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
AnnaBridge	189:f392fc9709a3	1813	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1814	* @retval None
AnnaBridge	189:f392fc9709a3	1815	*/
AnnaBridge	189:f392fc9709a3	1816	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1817	{
AnnaBridge	189:f392fc9709a3	1818	LL_SPI_EnableIT_RXNE(SPIx);
AnnaBridge	189:f392fc9709a3	1819	}
AnnaBridge	189:f392fc9709a3	1820
AnnaBridge	189:f392fc9709a3	1821	/**
AnnaBridge	189:f392fc9709a3	1822	* @brief Enable Tx buffer empty IT
AnnaBridge	189:f392fc9709a3	1823	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
AnnaBridge	189:f392fc9709a3	1824	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1825	* @retval None
AnnaBridge	189:f392fc9709a3	1826	*/
AnnaBridge	189:f392fc9709a3	1827	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1828	{
AnnaBridge	189:f392fc9709a3	1829	LL_SPI_EnableIT_TXE(SPIx);
AnnaBridge	189:f392fc9709a3	1830	}
AnnaBridge	189:f392fc9709a3	1831
AnnaBridge	189:f392fc9709a3	1832	/**
AnnaBridge	189:f392fc9709a3	1833	* @brief Disable error IT
AnnaBridge	189:f392fc9709a3	1834	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	189:f392fc9709a3	1835	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
AnnaBridge	189:f392fc9709a3	1836	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1837	* @retval None
AnnaBridge	189:f392fc9709a3	1838	*/
AnnaBridge	189:f392fc9709a3	1839	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1840	{
AnnaBridge	189:f392fc9709a3	1841	LL_SPI_DisableIT_ERR(SPIx);
AnnaBridge	189:f392fc9709a3	1842	}
AnnaBridge	189:f392fc9709a3	1843
AnnaBridge	189:f392fc9709a3	1844	/**
AnnaBridge	189:f392fc9709a3	1845	* @brief Disable Rx buffer not empty IT
AnnaBridge	189:f392fc9709a3	1846	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
AnnaBridge	189:f392fc9709a3	1847	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1848	* @retval None
AnnaBridge	189:f392fc9709a3	1849	*/
AnnaBridge	189:f392fc9709a3	1850	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1851	{
AnnaBridge	189:f392fc9709a3	1852	LL_SPI_DisableIT_RXNE(SPIx);
AnnaBridge	189:f392fc9709a3	1853	}
AnnaBridge	189:f392fc9709a3	1854
AnnaBridge	189:f392fc9709a3	1855	/**
AnnaBridge	189:f392fc9709a3	1856	* @brief Disable Tx buffer empty IT
AnnaBridge	189:f392fc9709a3	1857	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
AnnaBridge	189:f392fc9709a3	1858	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1859	* @retval None
AnnaBridge	189:f392fc9709a3	1860	*/
AnnaBridge	189:f392fc9709a3	1861	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1862	{
AnnaBridge	189:f392fc9709a3	1863	LL_SPI_DisableIT_TXE(SPIx);
AnnaBridge	189:f392fc9709a3	1864	}
AnnaBridge	189:f392fc9709a3	1865
AnnaBridge	189:f392fc9709a3	1866	/**
AnnaBridge	189:f392fc9709a3	1867	* @brief Check if ERR IT is enabled
AnnaBridge	189:f392fc9709a3	1868	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
AnnaBridge	189:f392fc9709a3	1869	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1870	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1871	*/
AnnaBridge	189:f392fc9709a3	1872	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1873	{
AnnaBridge	189:f392fc9709a3	1874	return LL_SPI_IsEnabledIT_ERR(SPIx);
AnnaBridge	189:f392fc9709a3	1875	}
AnnaBridge	189:f392fc9709a3	1876
AnnaBridge	189:f392fc9709a3	1877	/**
AnnaBridge	189:f392fc9709a3	1878	* @brief Check if RXNE IT is enabled
AnnaBridge	189:f392fc9709a3	1879	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
AnnaBridge	189:f392fc9709a3	1880	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1881	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1882	*/
AnnaBridge	189:f392fc9709a3	1883	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1884	{
AnnaBridge	189:f392fc9709a3	1885	return LL_SPI_IsEnabledIT_RXNE(SPIx);
AnnaBridge	189:f392fc9709a3	1886	}
AnnaBridge	189:f392fc9709a3	1887
AnnaBridge	189:f392fc9709a3	1888	/**
AnnaBridge	189:f392fc9709a3	1889	* @brief Check if TXE IT is enabled
AnnaBridge	189:f392fc9709a3	1890	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
AnnaBridge	189:f392fc9709a3	1891	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1892	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1893	*/
AnnaBridge	189:f392fc9709a3	1894	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1895	{
AnnaBridge	189:f392fc9709a3	1896	return LL_SPI_IsEnabledIT_TXE(SPIx);
AnnaBridge	189:f392fc9709a3	1897	}
AnnaBridge	189:f392fc9709a3	1898
AnnaBridge	189:f392fc9709a3	1899	/**
AnnaBridge	189:f392fc9709a3	1900	* @}
AnnaBridge	189:f392fc9709a3	1901	*/
AnnaBridge	189:f392fc9709a3	1902
AnnaBridge	189:f392fc9709a3	1903	/** @defgroup I2S_LL_EF_DMA DMA Management
AnnaBridge	189:f392fc9709a3	1904	* @{
AnnaBridge	189:f392fc9709a3	1905	*/
AnnaBridge	189:f392fc9709a3	1906
AnnaBridge	189:f392fc9709a3	1907	/**
AnnaBridge	189:f392fc9709a3	1908	* @brief Enable DMA Rx
AnnaBridge	189:f392fc9709a3	1909	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
AnnaBridge	189:f392fc9709a3	1910	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1911	* @retval None
AnnaBridge	189:f392fc9709a3	1912	*/
AnnaBridge	189:f392fc9709a3	1913	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1914	{
AnnaBridge	189:f392fc9709a3	1915	LL_SPI_EnableDMAReq_RX(SPIx);
AnnaBridge	189:f392fc9709a3	1916	}
AnnaBridge	189:f392fc9709a3	1917
AnnaBridge	189:f392fc9709a3	1918	/**
AnnaBridge	189:f392fc9709a3	1919	* @brief Disable DMA Rx
AnnaBridge	189:f392fc9709a3	1920	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
AnnaBridge	189:f392fc9709a3	1921	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1922	* @retval None
AnnaBridge	189:f392fc9709a3	1923	*/
AnnaBridge	189:f392fc9709a3	1924	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1925	{
AnnaBridge	189:f392fc9709a3	1926	LL_SPI_DisableDMAReq_RX(SPIx);
AnnaBridge	189:f392fc9709a3	1927	}
AnnaBridge	189:f392fc9709a3	1928
AnnaBridge	189:f392fc9709a3	1929	/**
AnnaBridge	189:f392fc9709a3	1930	* @brief Check if DMA Rx is enabled
AnnaBridge	189:f392fc9709a3	1931	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
AnnaBridge	189:f392fc9709a3	1932	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1933	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1934	*/
AnnaBridge	189:f392fc9709a3	1935	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1936	{
AnnaBridge	189:f392fc9709a3	1937	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
AnnaBridge	189:f392fc9709a3	1938	}
AnnaBridge	189:f392fc9709a3	1939
AnnaBridge	189:f392fc9709a3	1940	/**
AnnaBridge	189:f392fc9709a3	1941	* @brief Enable DMA Tx
AnnaBridge	189:f392fc9709a3	1942	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
AnnaBridge	189:f392fc9709a3	1943	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1944	* @retval None
AnnaBridge	189:f392fc9709a3	1945	*/
AnnaBridge	189:f392fc9709a3	1946	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1947	{
AnnaBridge	189:f392fc9709a3	1948	LL_SPI_EnableDMAReq_TX(SPIx);
AnnaBridge	189:f392fc9709a3	1949	}
AnnaBridge	189:f392fc9709a3	1950
AnnaBridge	189:f392fc9709a3	1951	/**
AnnaBridge	189:f392fc9709a3	1952	* @brief Disable DMA Tx
AnnaBridge	189:f392fc9709a3	1953	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
AnnaBridge	189:f392fc9709a3	1954	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1955	* @retval None
AnnaBridge	189:f392fc9709a3	1956	*/
AnnaBridge	189:f392fc9709a3	1957	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1958	{
AnnaBridge	189:f392fc9709a3	1959	LL_SPI_DisableDMAReq_TX(SPIx);
AnnaBridge	189:f392fc9709a3	1960	}
AnnaBridge	189:f392fc9709a3	1961
AnnaBridge	189:f392fc9709a3	1962	/**
AnnaBridge	189:f392fc9709a3	1963	* @brief Check if DMA Tx is enabled
AnnaBridge	189:f392fc9709a3	1964	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
AnnaBridge	189:f392fc9709a3	1965	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1966	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1967	*/
AnnaBridge	189:f392fc9709a3	1968	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1969	{
AnnaBridge	189:f392fc9709a3	1970	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
AnnaBridge	189:f392fc9709a3	1971	}
AnnaBridge	189:f392fc9709a3	1972
AnnaBridge	189:f392fc9709a3	1973	/**
AnnaBridge	189:f392fc9709a3	1974	* @}
AnnaBridge	189:f392fc9709a3	1975	*/
AnnaBridge	189:f392fc9709a3	1976
AnnaBridge	189:f392fc9709a3	1977	/** @defgroup I2S_LL_EF_DATA DATA Management
AnnaBridge	189:f392fc9709a3	1978	* @{
AnnaBridge	189:f392fc9709a3	1979	*/
AnnaBridge	189:f392fc9709a3	1980
AnnaBridge	189:f392fc9709a3	1981	/**
AnnaBridge	189:f392fc9709a3	1982	* @brief Read 16-Bits in data register
AnnaBridge	189:f392fc9709a3	1983	* @rmtoll DR DR LL_I2S_ReceiveData16
AnnaBridge	189:f392fc9709a3	1984	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1985	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	189:f392fc9709a3	1986	*/
AnnaBridge	189:f392fc9709a3	1987	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	189:f392fc9709a3	1988	{
AnnaBridge	189:f392fc9709a3	1989	return LL_SPI_ReceiveData16(SPIx);
AnnaBridge	189:f392fc9709a3	1990	}
AnnaBridge	189:f392fc9709a3	1991
AnnaBridge	189:f392fc9709a3	1992	/**
AnnaBridge	189:f392fc9709a3	1993	* @brief Write 16-Bits in data register
AnnaBridge	189:f392fc9709a3	1994	* @rmtoll DR DR LL_I2S_TransmitData16
AnnaBridge	189:f392fc9709a3	1995	* @param SPIx SPI Instance
AnnaBridge	189:f392fc9709a3	1996	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	189:f392fc9709a3	1997	* @retval None
AnnaBridge	189:f392fc9709a3	1998	*/
AnnaBridge	189:f392fc9709a3	1999	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	189:f392fc9709a3	2000	{
AnnaBridge	189:f392fc9709a3	2001	LL_SPI_TransmitData16(SPIx, TxData);
AnnaBridge	189:f392fc9709a3	2002	}
AnnaBridge	189:f392fc9709a3	2003
AnnaBridge	189:f392fc9709a3	2004	/**
AnnaBridge	189:f392fc9709a3	2005	* @}
AnnaBridge	189:f392fc9709a3	2006	*/
AnnaBridge	189:f392fc9709a3	2007
AnnaBridge	189:f392fc9709a3	2008	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	2009	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	189:f392fc9709a3	2010	* @{
AnnaBridge	189:f392fc9709a3	2011	*/
AnnaBridge	189:f392fc9709a3	2012
AnnaBridge	189:f392fc9709a3	2013	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	189:f392fc9709a3	2014	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
AnnaBridge	189:f392fc9709a3	2015	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
AnnaBridge	189:f392fc9709a3	2016	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
AnnaBridge	189:f392fc9709a3	2017
AnnaBridge	189:f392fc9709a3	2018	/**
AnnaBridge	189:f392fc9709a3	2019	* @}
AnnaBridge	189:f392fc9709a3	2020	*/
AnnaBridge	189:f392fc9709a3	2021	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	2022
AnnaBridge	189:f392fc9709a3	2023	/**
AnnaBridge	189:f392fc9709a3	2024	* @}
AnnaBridge	189:f392fc9709a3	2025	*/
AnnaBridge	189:f392fc9709a3	2026
AnnaBridge	189:f392fc9709a3	2027	/**
AnnaBridge	189:f392fc9709a3	2028	* @}
AnnaBridge	189:f392fc9709a3	2029	*/
AnnaBridge	189:f392fc9709a3	2030	#endif /* SPI_I2S_SUPPORT */
AnnaBridge	189:f392fc9709a3	2031
AnnaBridge	189:f392fc9709a3	2032	#endif /* defined (SPI1) \|\| defined (SPI2) */
AnnaBridge	189:f392fc9709a3	2033
AnnaBridge	189:f392fc9709a3	2034	/**
AnnaBridge	189:f392fc9709a3	2035	* @}
AnnaBridge	189:f392fc9709a3	2036	*/
AnnaBridge	189:f392fc9709a3	2037
AnnaBridge	189:f392fc9709a3	2038	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	2039	}
AnnaBridge	189:f392fc9709a3	2040	#endif
AnnaBridge	189:f392fc9709a3	2041
AnnaBridge	189:f392fc9709a3	2042	#endif /* __STM32L0xx_LL_SPI_H */
AnnaBridge	189:f392fc9709a3	2043
AnnaBridge	189:f392fc9709a3	2044	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/