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cmsis/BUILD/mbed/TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/stm32l0xx_ll_rcc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l0xx_ll_rcc.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of RCC LL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L0xx_LL_RCC_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L0xx_LL_RCC_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	45	#include "stm32l0xx.h"
AnnaBridge	189:f392fc9709a3	46
AnnaBridge	189:f392fc9709a3	47	/** @addtogroup STM32L0xx_LL_Driver
AnnaBridge	189:f392fc9709a3	48	* @{
AnnaBridge	189:f392fc9709a3	49	*/
AnnaBridge	189:f392fc9709a3	50
AnnaBridge	189:f392fc9709a3	51	#if defined(RCC)
AnnaBridge	189:f392fc9709a3	52
AnnaBridge	189:f392fc9709a3	53	/** @defgroup RCC_LL RCC
AnnaBridge	189:f392fc9709a3	54	* @{
AnnaBridge	189:f392fc9709a3	55	*/
AnnaBridge	189:f392fc9709a3	56
AnnaBridge	189:f392fc9709a3	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	59	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
AnnaBridge	189:f392fc9709a3	60	* @{
AnnaBridge	189:f392fc9709a3	61	*/
AnnaBridge	189:f392fc9709a3	62
AnnaBridge	189:f392fc9709a3	63	/**
AnnaBridge	189:f392fc9709a3	64	* @}
AnnaBridge	189:f392fc9709a3	65	*/
AnnaBridge	189:f392fc9709a3	66
AnnaBridge	189:f392fc9709a3	67	/* Private constants ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	68	/** @defgroup RCC_LL_Private_Constants RCC Private Constants
AnnaBridge	189:f392fc9709a3	69	* @{
AnnaBridge	189:f392fc9709a3	70	*/
AnnaBridge	189:f392fc9709a3	71	/* Defines used for the bit position in the register and perform offsets*/
AnnaBridge	189:f392fc9709a3	72	#define RCC_POSITION_HPRE (uint32_t)4U /!< field position in register RCC_CFGR /
AnnaBridge	189:f392fc9709a3	73	#define RCC_POSITION_PPRE1 (uint32_t)8U /!< field position in register RCC_CFGR /
AnnaBridge	189:f392fc9709a3	74	#define RCC_POSITION_PPRE2 (uint32_t)11U /!< field position in register RCC_CFGR /
AnnaBridge	189:f392fc9709a3	75	#define RCC_POSITION_PLLDIV (uint32_t)22U /!< field position in register RCC_CFGR /
AnnaBridge	189:f392fc9709a3	76	#define RCC_POSITION_PLLMUL (uint32_t)18U /!< field position in register RCC_CFGR /
AnnaBridge	189:f392fc9709a3	77	#define RCC_POSITION_HSICAL (uint32_t)0U /!< field position in register RCC_ICSCR /
AnnaBridge	189:f392fc9709a3	78	#define RCC_POSITION_HSITRIM (uint32_t)8U /!< field position in register RCC_ICSCR /
AnnaBridge	189:f392fc9709a3	79	#define RCC_POSITION_MSIRANGE (uint32_t)13U /!< field position in register RCC_ICSCR /
AnnaBridge	189:f392fc9709a3	80	#define RCC_POSITION_MSICAL (uint32_t)16U /!< field position in register RCC_ICSCR /
AnnaBridge	189:f392fc9709a3	81	#define RCC_POSITION_MSITRIM (uint32_t)24U /!< field position in register RCC_ICSCR /
AnnaBridge	189:f392fc9709a3	82	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	83	#define RCC_POSITION_HSI48CAL (uint32_t)8U /!< field position in register RCC_CRRCR /
AnnaBridge	189:f392fc9709a3	84	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	85
AnnaBridge	189:f392fc9709a3	86	/**
AnnaBridge	189:f392fc9709a3	87	* @}
AnnaBridge	189:f392fc9709a3	88	*/
AnnaBridge	189:f392fc9709a3	89
AnnaBridge	189:f392fc9709a3	90	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	91	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	92	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
AnnaBridge	189:f392fc9709a3	93	* @{
AnnaBridge	189:f392fc9709a3	94	*/
AnnaBridge	189:f392fc9709a3	95	/**
AnnaBridge	189:f392fc9709a3	96	* @}
AnnaBridge	189:f392fc9709a3	97	*/
AnnaBridge	189:f392fc9709a3	98	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	189:f392fc9709a3	99	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	100	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	101	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
AnnaBridge	189:f392fc9709a3	102	* @{
AnnaBridge	189:f392fc9709a3	103	*/
AnnaBridge	189:f392fc9709a3	104
AnnaBridge	189:f392fc9709a3	105	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
AnnaBridge	189:f392fc9709a3	106	* @{
AnnaBridge	189:f392fc9709a3	107	*/
AnnaBridge	189:f392fc9709a3	108
AnnaBridge	189:f392fc9709a3	109	/**
AnnaBridge	189:f392fc9709a3	110	* @brief RCC Clocks Frequency Structure
AnnaBridge	189:f392fc9709a3	111	*/
AnnaBridge	189:f392fc9709a3	112	typedef struct
AnnaBridge	189:f392fc9709a3	113	{
AnnaBridge	189:f392fc9709a3	114	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
AnnaBridge	189:f392fc9709a3	115	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
AnnaBridge	189:f392fc9709a3	116	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
AnnaBridge	189:f392fc9709a3	117	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
AnnaBridge	189:f392fc9709a3	118	} LL_RCC_ClocksTypeDef;
AnnaBridge	189:f392fc9709a3	119
AnnaBridge	189:f392fc9709a3	120	/**
AnnaBridge	189:f392fc9709a3	121	* @}
AnnaBridge	189:f392fc9709a3	122	*/
AnnaBridge	189:f392fc9709a3	123
AnnaBridge	189:f392fc9709a3	124	/**
AnnaBridge	189:f392fc9709a3	125	* @}
AnnaBridge	189:f392fc9709a3	126	*/
AnnaBridge	189:f392fc9709a3	127	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	128
AnnaBridge	189:f392fc9709a3	129	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	130	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
AnnaBridge	189:f392fc9709a3	131	* @{
AnnaBridge	189:f392fc9709a3	132	*/
AnnaBridge	189:f392fc9709a3	133
AnnaBridge	189:f392fc9709a3	134	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
AnnaBridge	189:f392fc9709a3	135	* @brief Defines used to adapt values of different oscillators
AnnaBridge	189:f392fc9709a3	136	* @note These values could be modified in the user environment according to
AnnaBridge	189:f392fc9709a3	137	* HW set-up.
AnnaBridge	189:f392fc9709a3	138	* @{
AnnaBridge	189:f392fc9709a3	139	*/
AnnaBridge	189:f392fc9709a3	140	#if !defined (HSE_VALUE)
AnnaBridge	189:f392fc9709a3	141	#define HSE_VALUE ((uint32_t)8000000U) /!< Value of the HSE oscillator in Hz /
AnnaBridge	189:f392fc9709a3	142	#endif /* HSE_VALUE */
AnnaBridge	189:f392fc9709a3	143
AnnaBridge	189:f392fc9709a3	144	#if !defined (HSI_VALUE)
AnnaBridge	189:f392fc9709a3	145	#define HSI_VALUE ((uint32_t)16000000U) /!< Value of the HSI oscillator in Hz /
AnnaBridge	189:f392fc9709a3	146	#endif /* HSI_VALUE */
AnnaBridge	189:f392fc9709a3	147
AnnaBridge	189:f392fc9709a3	148	#if !defined (LSE_VALUE)
AnnaBridge	189:f392fc9709a3	149	#define LSE_VALUE ((uint32_t)32768U) /!< Value of the LSE oscillator in Hz /
AnnaBridge	189:f392fc9709a3	150	#endif /* LSE_VALUE */
AnnaBridge	189:f392fc9709a3	151
AnnaBridge	189:f392fc9709a3	152	#if !defined (LSI_VALUE)
AnnaBridge	189:f392fc9709a3	153	#define LSI_VALUE ((uint32_t)37000U) /!< Value of the LSI oscillator in Hz /
AnnaBridge	189:f392fc9709a3	154	#endif /* LSI_VALUE */
AnnaBridge	189:f392fc9709a3	155	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	156
AnnaBridge	189:f392fc9709a3	157	#if !defined (HSI48_VALUE)
AnnaBridge	189:f392fc9709a3	158	#define HSI48_VALUE ((uint32_t)48000000U) /!< Value of the HSI48 oscillator in Hz /
AnnaBridge	189:f392fc9709a3	159	#endif /* HSI48_VALUE */
AnnaBridge	189:f392fc9709a3	160	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	161	/**
AnnaBridge	189:f392fc9709a3	162	* @}
AnnaBridge	189:f392fc9709a3	163	*/
AnnaBridge	189:f392fc9709a3	164
AnnaBridge	189:f392fc9709a3	165	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	189:f392fc9709a3	166	* @brief Flags defines which can be used with LL_RCC_WriteReg function
AnnaBridge	189:f392fc9709a3	167	* @{
AnnaBridge	189:f392fc9709a3	168	*/
AnnaBridge	189:f392fc9709a3	169	#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /!< LSI Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	170	#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /!< LSE Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	171	#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /!< HSI Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	172	#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /!< HSE Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	173	#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /!< PLL Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	174	#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /!< MSI Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	175	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	176	#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /!< HSI48 Ready Interrupt Clear /
AnnaBridge	189:f392fc9709a3	177	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	178	#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /!< LSE Clock Security System Interrupt Clear /
AnnaBridge	189:f392fc9709a3	179	#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /!< Clock Security System Interrupt Clear /
AnnaBridge	189:f392fc9709a3	180	/**
AnnaBridge	189:f392fc9709a3	181	* @}
AnnaBridge	189:f392fc9709a3	182	*/
AnnaBridge	189:f392fc9709a3	183
AnnaBridge	189:f392fc9709a3	184	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	189:f392fc9709a3	185	* @brief Flags defines which can be used with LL_RCC_ReadReg function
AnnaBridge	189:f392fc9709a3	186	* @{
AnnaBridge	189:f392fc9709a3	187	*/
AnnaBridge	189:f392fc9709a3	188	#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /!< LSI Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	189	#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /!< LSE Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	190	#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /!< HSI Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	191	#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /!< HSE Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	192	#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /!< PLL Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	193	#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /!< MSI Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	194	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	195	#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
AnnaBridge	189:f392fc9709a3	196	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	197	#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /!< LSE Clock Security System Interrupt flag /
AnnaBridge	189:f392fc9709a3	198	#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /!< Clock Security System Interrupt flag /
AnnaBridge	189:f392fc9709a3	199	#define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /!< Firewall reset flag /
AnnaBridge	189:f392fc9709a3	200	#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /!< OBL reset flag /
AnnaBridge	189:f392fc9709a3	201	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
AnnaBridge	189:f392fc9709a3	202	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
AnnaBridge	189:f392fc9709a3	203	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
AnnaBridge	189:f392fc9709a3	204	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
AnnaBridge	189:f392fc9709a3	205	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
AnnaBridge	189:f392fc9709a3	206	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
AnnaBridge	189:f392fc9709a3	207	/**
AnnaBridge	189:f392fc9709a3	208	* @}
AnnaBridge	189:f392fc9709a3	209	*/
AnnaBridge	189:f392fc9709a3	210
AnnaBridge	189:f392fc9709a3	211	/** @defgroup RCC_LL_EC_IT IT Defines
AnnaBridge	189:f392fc9709a3	212	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
AnnaBridge	189:f392fc9709a3	213	* @{
AnnaBridge	189:f392fc9709a3	214	*/
AnnaBridge	189:f392fc9709a3	215	#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /!< LSI Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	216	#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /!< LSE Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	217	#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /!< HSI Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	218	#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /!< HSE Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	219	#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /!< PLL Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	220	#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /!< MSI Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	221	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	222	#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /!< HSI48 Ready Interrupt Enable /
AnnaBridge	189:f392fc9709a3	223	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	224	#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /!< LSE CSS Interrupt Enable /
AnnaBridge	189:f392fc9709a3	225	/**
AnnaBridge	189:f392fc9709a3	226	* @}
AnnaBridge	189:f392fc9709a3	227	*/
AnnaBridge	189:f392fc9709a3	228
AnnaBridge	189:f392fc9709a3	229	/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
AnnaBridge	189:f392fc9709a3	230	* @{
AnnaBridge	189:f392fc9709a3	231	*/
AnnaBridge	189:f392fc9709a3	232	#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /!< Xtal mode lower driving capability /
AnnaBridge	189:f392fc9709a3	233	#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0 /!< Xtal mode medium low driving capability /
AnnaBridge	189:f392fc9709a3	234	#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1 /!< Xtal mode medium high driving capability /
AnnaBridge	189:f392fc9709a3	235	#define LL_RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV /!< Xtal mode higher driving capability /
AnnaBridge	189:f392fc9709a3	236	/**
AnnaBridge	189:f392fc9709a3	237	* @}
AnnaBridge	189:f392fc9709a3	238	*/
AnnaBridge	189:f392fc9709a3	239
AnnaBridge	189:f392fc9709a3	240	/** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler
AnnaBridge	189:f392fc9709a3	241	* @{
AnnaBridge	189:f392fc9709a3	242	*/
AnnaBridge	189:f392fc9709a3	243	#define LL_RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U/!< HSE is divided by 2 for RTC clock /
AnnaBridge	189:f392fc9709a3	244	#define LL_RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /!< HSE is divided by 4 for RTC clock /
AnnaBridge	189:f392fc9709a3	245	#define LL_RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /!< HSE is divided by 8 for RTC clock /
AnnaBridge	189:f392fc9709a3	246	#define LL_RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /!< HSE is divided by 16 for RTC clock /
AnnaBridge	189:f392fc9709a3	247	/**
AnnaBridge	189:f392fc9709a3	248	* @}
AnnaBridge	189:f392fc9709a3	249	*/
AnnaBridge	189:f392fc9709a3	250
AnnaBridge	189:f392fc9709a3	251	/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
AnnaBridge	189:f392fc9709a3	252	* @{
AnnaBridge	189:f392fc9709a3	253	*/
AnnaBridge	189:f392fc9709a3	254	#define LL_RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
AnnaBridge	189:f392fc9709a3	255	#define LL_RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz/
AnnaBridge	189:f392fc9709a3	256	#define LL_RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
AnnaBridge	189:f392fc9709a3	257	#define LL_RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
AnnaBridge	189:f392fc9709a3	258	#define LL_RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
AnnaBridge	189:f392fc9709a3	259	#define LL_RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
AnnaBridge	189:f392fc9709a3	260	#define LL_RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
AnnaBridge	189:f392fc9709a3	261	/**
AnnaBridge	189:f392fc9709a3	262	* @}
AnnaBridge	189:f392fc9709a3	263	*/
AnnaBridge	189:f392fc9709a3	264
AnnaBridge	189:f392fc9709a3	265	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
AnnaBridge	189:f392fc9709a3	266	* @{
AnnaBridge	189:f392fc9709a3	267	*/
AnnaBridge	189:f392fc9709a3	268	#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
AnnaBridge	189:f392fc9709a3	269	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
AnnaBridge	189:f392fc9709a3	270	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
AnnaBridge	189:f392fc9709a3	271	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
AnnaBridge	189:f392fc9709a3	272	/**
AnnaBridge	189:f392fc9709a3	273	* @}
AnnaBridge	189:f392fc9709a3	274	*/
AnnaBridge	189:f392fc9709a3	275
AnnaBridge	189:f392fc9709a3	276	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
AnnaBridge	189:f392fc9709a3	277	* @{
AnnaBridge	189:f392fc9709a3	278	*/
AnnaBridge	189:f392fc9709a3	279	#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
AnnaBridge	189:f392fc9709a3	280	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	189:f392fc9709a3	281	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	189:f392fc9709a3	282	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	189:f392fc9709a3	283	/**
AnnaBridge	189:f392fc9709a3	284	* @}
AnnaBridge	189:f392fc9709a3	285	*/
AnnaBridge	189:f392fc9709a3	286
AnnaBridge	189:f392fc9709a3	287	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
AnnaBridge	189:f392fc9709a3	288	* @{
AnnaBridge	189:f392fc9709a3	289	*/
AnnaBridge	189:f392fc9709a3	290	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	189:f392fc9709a3	291	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	189:f392fc9709a3	292	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	189:f392fc9709a3	293	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	189:f392fc9709a3	294	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	189:f392fc9709a3	295	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	189:f392fc9709a3	296	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	189:f392fc9709a3	297	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	189:f392fc9709a3	298	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	189:f392fc9709a3	299	/**
AnnaBridge	189:f392fc9709a3	300	* @}
AnnaBridge	189:f392fc9709a3	301	*/
AnnaBridge	189:f392fc9709a3	302
AnnaBridge	189:f392fc9709a3	303	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
AnnaBridge	189:f392fc9709a3	304	* @{
AnnaBridge	189:f392fc9709a3	305	*/
AnnaBridge	189:f392fc9709a3	306	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	189:f392fc9709a3	307	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	189:f392fc9709a3	308	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	189:f392fc9709a3	309	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	189:f392fc9709a3	310	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	189:f392fc9709a3	311	/**
AnnaBridge	189:f392fc9709a3	312	* @}
AnnaBridge	189:f392fc9709a3	313	*/
AnnaBridge	189:f392fc9709a3	314
AnnaBridge	189:f392fc9709a3	315	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
AnnaBridge	189:f392fc9709a3	316	* @{
AnnaBridge	189:f392fc9709a3	317	*/
AnnaBridge	189:f392fc9709a3	318	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
AnnaBridge	189:f392fc9709a3	319	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
AnnaBridge	189:f392fc9709a3	320	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
AnnaBridge	189:f392fc9709a3	321	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
AnnaBridge	189:f392fc9709a3	322	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
AnnaBridge	189:f392fc9709a3	323	/**
AnnaBridge	189:f392fc9709a3	324	* @}
AnnaBridge	189:f392fc9709a3	325	*/
AnnaBridge	189:f392fc9709a3	326
AnnaBridge	189:f392fc9709a3	327	/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
AnnaBridge	189:f392fc9709a3	328	* @{
AnnaBridge	189:f392fc9709a3	329	*/
AnnaBridge	189:f392fc9709a3	330	#define LL_RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /!< MSI selection after wake-up from STOP /
AnnaBridge	189:f392fc9709a3	331	#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
AnnaBridge	189:f392fc9709a3	332	/**
AnnaBridge	189:f392fc9709a3	333	* @}
AnnaBridge	189:f392fc9709a3	334	*/
AnnaBridge	189:f392fc9709a3	335
AnnaBridge	189:f392fc9709a3	336	/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
AnnaBridge	189:f392fc9709a3	337	* @{
AnnaBridge	189:f392fc9709a3	338	*/
AnnaBridge	189:f392fc9709a3	339	#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /!< MCO output disabled, no clock on MCO /
AnnaBridge	189:f392fc9709a3	340	#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /!< SYSCLK selection as MCO source /
AnnaBridge	189:f392fc9709a3	341	#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /!< HSI selection as MCO source /
AnnaBridge	189:f392fc9709a3	342	#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_MSI /!< MSI selection as MCO source /
AnnaBridge	189:f392fc9709a3	343	#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /!< HSE selection as MCO source /
AnnaBridge	189:f392fc9709a3	344	#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /!< LSI selection as MCO source /
AnnaBridge	189:f392fc9709a3	345	#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /!< LSE selection as MCO source /
AnnaBridge	189:f392fc9709a3	346	#if defined(RCC_CFGR_MCOSEL_HSI48)
AnnaBridge	189:f392fc9709a3	347	#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /!< HSI48 selection as MCO source /
AnnaBridge	189:f392fc9709a3	348	#endif /* RCC_CFGR_MCOSEL_HSI48 */
AnnaBridge	189:f392fc9709a3	349	#define LL_RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCOSEL_PLL /!< PLLCLK selection as MCO source /
AnnaBridge	189:f392fc9709a3	350	/**
AnnaBridge	189:f392fc9709a3	351	* @}
AnnaBridge	189:f392fc9709a3	352	*/
AnnaBridge	189:f392fc9709a3	353
AnnaBridge	189:f392fc9709a3	354	/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
AnnaBridge	189:f392fc9709a3	355	* @{
AnnaBridge	189:f392fc9709a3	356	*/
AnnaBridge	189:f392fc9709a3	357	#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /!< MCO Clock divided by 1 /
AnnaBridge	189:f392fc9709a3	358	#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO Clock divided by 2 /
AnnaBridge	189:f392fc9709a3	359	#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO Clock divided by 4 /
AnnaBridge	189:f392fc9709a3	360	#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO Clock divided by 8 /
AnnaBridge	189:f392fc9709a3	361	#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO Clock divided by 16 /
AnnaBridge	189:f392fc9709a3	362	/**
AnnaBridge	189:f392fc9709a3	363	* @}
AnnaBridge	189:f392fc9709a3	364	*/
AnnaBridge	189:f392fc9709a3	365	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	366	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
AnnaBridge	189:f392fc9709a3	367	* @{
AnnaBridge	189:f392fc9709a3	368	*/
AnnaBridge	189:f392fc9709a3	369	#define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /!< No clock enabled for the peripheral /
AnnaBridge	189:f392fc9709a3	370	#define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
AnnaBridge	189:f392fc9709a3	371	/**
AnnaBridge	189:f392fc9709a3	372	* @}
AnnaBridge	189:f392fc9709a3	373	*/
AnnaBridge	189:f392fc9709a3	374	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	375
AnnaBridge	189:f392fc9709a3	376	/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
AnnaBridge	189:f392fc9709a3	377	* @{
AnnaBridge	189:f392fc9709a3	378	*/
AnnaBridge	189:f392fc9709a3	379	#if defined(RCC_CCIPR_USART1SEL)
AnnaBridge	189:f392fc9709a3	380	#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_CCIPR_USART1SEL << 16U) \| 0x00000000U) /!< PCLK2 selected as USART1 clock /
AnnaBridge	189:f392fc9709a3	381	#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL_0) /!< SYSCLK selected as USART1 clock /
AnnaBridge	189:f392fc9709a3	382	#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL_1) /!< HSI selected as USART1 clock /
AnnaBridge	189:f392fc9709a3	383	#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL) /!< LSE selected as USART1 clock/
AnnaBridge	189:f392fc9709a3	384	#endif /* RCC_CCIPR_USART1SEL */
AnnaBridge	189:f392fc9709a3	385	#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART2SEL << 16U) \| 0x00000000U) /!< PCLK1 selected as USART2 clock /
AnnaBridge	189:f392fc9709a3	386	#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL_0) /!< SYSCLK selected as USART2 clock /
AnnaBridge	189:f392fc9709a3	387	#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL_1) /!< HSI selected as USART2 clock /
AnnaBridge	189:f392fc9709a3	388	#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL) /!< LSE selected as USART2 clock/
AnnaBridge	189:f392fc9709a3	389	/**
AnnaBridge	189:f392fc9709a3	390	* @}
AnnaBridge	189:f392fc9709a3	391	*/
AnnaBridge	189:f392fc9709a3	392
AnnaBridge	189:f392fc9709a3	393
AnnaBridge	189:f392fc9709a3	394
AnnaBridge	189:f392fc9709a3	395	/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
AnnaBridge	189:f392fc9709a3	396	* @{
AnnaBridge	189:f392fc9709a3	397	*/
AnnaBridge	189:f392fc9709a3	398	#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 (uint32_t)0x00000000U /!< PCLK1 selected as LPUART1 clock /
AnnaBridge	189:f392fc9709a3	399	#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /!< SYSCLK selected as LPUART1 clock /
AnnaBridge	189:f392fc9709a3	400	#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /!< HSI selected as LPUART1 clock /
AnnaBridge	189:f392fc9709a3	401	#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /!< LSE selected as LPUART1 clock/
AnnaBridge	189:f392fc9709a3	402	/**
AnnaBridge	189:f392fc9709a3	403	* @}
AnnaBridge	189:f392fc9709a3	404	*/
AnnaBridge	189:f392fc9709a3	405
AnnaBridge	189:f392fc9709a3	406	/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
AnnaBridge	189:f392fc9709a3	407	* @{
AnnaBridge	189:f392fc9709a3	408	*/
AnnaBridge	189:f392fc9709a3	409	#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) \| (0x00000000U >> 4U)) /!< PCLK1 selected as I2C1 clock /
AnnaBridge	189:f392fc9709a3	410	#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) \| (RCC_CCIPR_I2C1SEL_0 >> 4U)) /!< SYSCLK selected as I2C1 clock /
AnnaBridge	189:f392fc9709a3	411	#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) \| (RCC_CCIPR_I2C1SEL_1 >> 4U)) /!< HSI selected as I2C1 clock /
AnnaBridge	189:f392fc9709a3	412	#if defined(RCC_CCIPR_I2C3SEL)
AnnaBridge	189:f392fc9709a3	413	#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) \| (0x00000000U >> 4U)) /!< PCLK1 selected as I2C3 clock /
AnnaBridge	189:f392fc9709a3	414	#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) \| (RCC_CCIPR_I2C3SEL_0 >> 4U)) /!< SYSCLK selected as I2C3 clock /
AnnaBridge	189:f392fc9709a3	415	#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) \| (RCC_CCIPR_I2C3SEL_1 >> 4U)) /!< HSI selected as I2C3 clock /
AnnaBridge	189:f392fc9709a3	416	#endif /RCC_CCIPR_I2C3SEL/
AnnaBridge	189:f392fc9709a3	417	/**
AnnaBridge	189:f392fc9709a3	418	* @}
AnnaBridge	189:f392fc9709a3	419	*/
AnnaBridge	189:f392fc9709a3	420
AnnaBridge	189:f392fc9709a3	421	/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
AnnaBridge	189:f392fc9709a3	422	* @{
AnnaBridge	189:f392fc9709a3	423	*/
AnnaBridge	189:f392fc9709a3	424	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(0x00000000U) /!< PCLK1 selected as LPTIM1 clock /
AnnaBridge	189:f392fc9709a3	425	#define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)RCC_CCIPR_LPTIM1SEL_0 /!< LSI selected as LPTIM1 clock /
AnnaBridge	189:f392fc9709a3	426	#define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)RCC_CCIPR_LPTIM1SEL_1 /!< HSI selected as LPTIM1 clock /
AnnaBridge	189:f392fc9709a3	427	#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)RCC_CCIPR_LPTIM1SEL /!< LSE selected as LPTIM1 clock/
AnnaBridge	189:f392fc9709a3	428	/**
AnnaBridge	189:f392fc9709a3	429	* @}
AnnaBridge	189:f392fc9709a3	430	*/
AnnaBridge	189:f392fc9709a3	431
AnnaBridge	189:f392fc9709a3	432	#if defined(RCC_CCIPR_HSI48SEL)
AnnaBridge	189:f392fc9709a3	433
AnnaBridge	189:f392fc9709a3	434	#if defined(RNG)
AnnaBridge	189:f392fc9709a3	435	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
AnnaBridge	189:f392fc9709a3	436	* @{
AnnaBridge	189:f392fc9709a3	437	*/
AnnaBridge	189:f392fc9709a3	438	#define LL_RCC_RNG_CLKSOURCE_PLL (uint32_t)(0x00000000U) /!< PLL selected as RNG clock /
AnnaBridge	189:f392fc9709a3	439	#define LL_RCC_RNG_CLKSOURCE_HSI48 (uint32_t)(RCC_CCIPR_HSI48SEL) /!< HSI48 selected as RNG clock/
AnnaBridge	189:f392fc9709a3	440	/**
AnnaBridge	189:f392fc9709a3	441	* @}
AnnaBridge	189:f392fc9709a3	442	*/
AnnaBridge	189:f392fc9709a3	443	#endif /* RNG */
AnnaBridge	189:f392fc9709a3	444	#if defined(USB)
AnnaBridge	189:f392fc9709a3	445	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
AnnaBridge	189:f392fc9709a3	446	* @{
AnnaBridge	189:f392fc9709a3	447	*/
AnnaBridge	189:f392fc9709a3	448	#define LL_RCC_USB_CLKSOURCE_PLL (uint32_t)(0x00000000U) /!< PLL selected as USB clock /
AnnaBridge	189:f392fc9709a3	449	#define LL_RCC_USB_CLKSOURCE_HSI48 (uint32_t)(RCC_CCIPR_HSI48SEL) /!< HSI48 selected as USB clock/
AnnaBridge	189:f392fc9709a3	450	/**
AnnaBridge	189:f392fc9709a3	451	* @}
AnnaBridge	189:f392fc9709a3	452	*/
AnnaBridge	189:f392fc9709a3	453
AnnaBridge	189:f392fc9709a3	454	#endif /* USB */
AnnaBridge	189:f392fc9709a3	455	#endif /* RCC_CCIPR_HSI48SEL */
AnnaBridge	189:f392fc9709a3	456
AnnaBridge	189:f392fc9709a3	457
AnnaBridge	189:f392fc9709a3	458	/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
AnnaBridge	189:f392fc9709a3	459	* @{
AnnaBridge	189:f392fc9709a3	460	*/
AnnaBridge	189:f392fc9709a3	461	#if defined(RCC_CCIPR_USART1SEL)
AnnaBridge	189:f392fc9709a3	462	#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /!< USART1 clock source selection bits /
AnnaBridge	189:f392fc9709a3	463	#endif /* RCC_CCIPR_USART1SEL */
AnnaBridge	189:f392fc9709a3	464	#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /!< USART2 clock source selection bits /
AnnaBridge	189:f392fc9709a3	465	/**
AnnaBridge	189:f392fc9709a3	466	* @}
AnnaBridge	189:f392fc9709a3	467	*/
AnnaBridge	189:f392fc9709a3	468
AnnaBridge	189:f392fc9709a3	469
AnnaBridge	189:f392fc9709a3	470	/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
AnnaBridge	189:f392fc9709a3	471	* @{
AnnaBridge	189:f392fc9709a3	472	*/
AnnaBridge	189:f392fc9709a3	473	#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /!< LPUART1 clock source selection bits /
AnnaBridge	189:f392fc9709a3	474	/**
AnnaBridge	189:f392fc9709a3	475	* @}
AnnaBridge	189:f392fc9709a3	476	*/
AnnaBridge	189:f392fc9709a3	477
AnnaBridge	189:f392fc9709a3	478	/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
AnnaBridge	189:f392fc9709a3	479	* @{
AnnaBridge	189:f392fc9709a3	480	*/
AnnaBridge	189:f392fc9709a3	481	#define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /!< I2C1 clock source selection bits /
AnnaBridge	189:f392fc9709a3	482	#if defined(RCC_CCIPR_I2C3SEL)
AnnaBridge	189:f392fc9709a3	483	#define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /!< I2C3 clock source selection bits /
AnnaBridge	189:f392fc9709a3	484	#endif /RCC_CCIPR_I2C3SEL/
AnnaBridge	189:f392fc9709a3	485	/**
AnnaBridge	189:f392fc9709a3	486	* @}
AnnaBridge	189:f392fc9709a3	487	*/
AnnaBridge	189:f392fc9709a3	488
AnnaBridge	189:f392fc9709a3	489	/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
AnnaBridge	189:f392fc9709a3	490	* @{
AnnaBridge	189:f392fc9709a3	491	*/
AnnaBridge	189:f392fc9709a3	492	#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /!< LPTIM1 clock source selection bits /
AnnaBridge	189:f392fc9709a3	493	/**
AnnaBridge	189:f392fc9709a3	494	* @}
AnnaBridge	189:f392fc9709a3	495	*/
AnnaBridge	189:f392fc9709a3	496
AnnaBridge	189:f392fc9709a3	497	#if defined(RCC_CCIPR_HSI48SEL)
AnnaBridge	189:f392fc9709a3	498	#if defined(RNG)
AnnaBridge	189:f392fc9709a3	499	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
AnnaBridge	189:f392fc9709a3	500	* @{
AnnaBridge	189:f392fc9709a3	501	*/
AnnaBridge	189:f392fc9709a3	502	#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_HSI48SEL /!< HSI48 RC clock source selection bit for RNG/
AnnaBridge	189:f392fc9709a3	503	/**
AnnaBridge	189:f392fc9709a3	504	* @}
AnnaBridge	189:f392fc9709a3	505	*/
AnnaBridge	189:f392fc9709a3	506	#endif /* RNG */
AnnaBridge	189:f392fc9709a3	507
AnnaBridge	189:f392fc9709a3	508	#if defined(USB)
AnnaBridge	189:f392fc9709a3	509	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
AnnaBridge	189:f392fc9709a3	510	* @{
AnnaBridge	189:f392fc9709a3	511	*/
AnnaBridge	189:f392fc9709a3	512	#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_HSI48SEL /!< HSI48 RC clock source selection bit for USB/
AnnaBridge	189:f392fc9709a3	513	/**
AnnaBridge	189:f392fc9709a3	514	* @}
AnnaBridge	189:f392fc9709a3	515	*/
AnnaBridge	189:f392fc9709a3	516
AnnaBridge	189:f392fc9709a3	517	#endif /* USB */
AnnaBridge	189:f392fc9709a3	518	#endif /* RCC_CCIPR_HSI48SEL */
AnnaBridge	189:f392fc9709a3	519
AnnaBridge	189:f392fc9709a3	520	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
AnnaBridge	189:f392fc9709a3	521	* @{
AnnaBridge	189:f392fc9709a3	522	*/
AnnaBridge	189:f392fc9709a3	523	#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /!< No clock used as RTC clock /
AnnaBridge	189:f392fc9709a3	524	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /!< LSE oscillator clock used as RTC clock /
AnnaBridge	189:f392fc9709a3	525	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /!< LSI oscillator clock used as RTC clock /
AnnaBridge	189:f392fc9709a3	526	#define LL_RCC_RTC_CLKSOURCE_HSE RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by a programmable prescaler
AnnaBridge	189:f392fc9709a3	527	(selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */
AnnaBridge	189:f392fc9709a3	528	/**
AnnaBridge	189:f392fc9709a3	529	* @}
AnnaBridge	189:f392fc9709a3	530	*/
AnnaBridge	189:f392fc9709a3	531
AnnaBridge	189:f392fc9709a3	532	/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
AnnaBridge	189:f392fc9709a3	533	* @{
AnnaBridge	189:f392fc9709a3	534	*/
AnnaBridge	189:f392fc9709a3	535	#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /!< PLL input clock 3 */
AnnaBridge	189:f392fc9709a3	536	#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /!< PLL input clock 4 */
AnnaBridge	189:f392fc9709a3	537	#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /!< PLL input clock 6 */
AnnaBridge	189:f392fc9709a3	538	#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /!< PLL input clock 8 */
AnnaBridge	189:f392fc9709a3	539	#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /!< PLL input clock 12 */
AnnaBridge	189:f392fc9709a3	540	#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /!< PLL input clock 16 */
AnnaBridge	189:f392fc9709a3	541	#define LL_RCC_PLL_MUL_24 RCC_CFGR_PLLMUL24 /!< PLL input clock 24 */
AnnaBridge	189:f392fc9709a3	542	#define LL_RCC_PLL_MUL_32 RCC_CFGR_PLLMUL32 /!< PLL input clock 32 */
AnnaBridge	189:f392fc9709a3	543	#define LL_RCC_PLL_MUL_48 RCC_CFGR_PLLMUL48 /!< PLL input clock 48 */
AnnaBridge	189:f392fc9709a3	544	/**
AnnaBridge	189:f392fc9709a3	545	* @}
AnnaBridge	189:f392fc9709a3	546	*/
AnnaBridge	189:f392fc9709a3	547
AnnaBridge	189:f392fc9709a3	548	/** @defgroup RCC_LL_EC_PLL_DIV PLL division factor
AnnaBridge	189:f392fc9709a3	549	* @{
AnnaBridge	189:f392fc9709a3	550	*/
AnnaBridge	189:f392fc9709a3	551	#define LL_RCC_PLL_DIV_2 RCC_CFGR_PLLDIV2 /!< PLL clock output = PLLVCO / 2 /
AnnaBridge	189:f392fc9709a3	552	#define LL_RCC_PLL_DIV_3 RCC_CFGR_PLLDIV3 /!< PLL clock output = PLLVCO / 3 /
AnnaBridge	189:f392fc9709a3	553	#define LL_RCC_PLL_DIV_4 RCC_CFGR_PLLDIV4 /!< PLL clock output = PLLVCO / 4 /
AnnaBridge	189:f392fc9709a3	554	/**
AnnaBridge	189:f392fc9709a3	555	* @}
AnnaBridge	189:f392fc9709a3	556	*/
AnnaBridge	189:f392fc9709a3	557
AnnaBridge	189:f392fc9709a3	558	/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
AnnaBridge	189:f392fc9709a3	559	* @{
AnnaBridge	189:f392fc9709a3	560	*/
AnnaBridge	189:f392fc9709a3	561	#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
AnnaBridge	189:f392fc9709a3	562	#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
AnnaBridge	189:f392fc9709a3	563	/**
AnnaBridge	189:f392fc9709a3	564	* @}
AnnaBridge	189:f392fc9709a3	565	*/
AnnaBridge	189:f392fc9709a3	566
AnnaBridge	189:f392fc9709a3	567	/**
AnnaBridge	189:f392fc9709a3	568	* @}
AnnaBridge	189:f392fc9709a3	569	*/
AnnaBridge	189:f392fc9709a3	570
AnnaBridge	189:f392fc9709a3	571	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	572	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
AnnaBridge	189:f392fc9709a3	573	* @{
AnnaBridge	189:f392fc9709a3	574	*/
AnnaBridge	189:f392fc9709a3	575
AnnaBridge	189:f392fc9709a3	576	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	189:f392fc9709a3	577	* @{
AnnaBridge	189:f392fc9709a3	578	*/
AnnaBridge	189:f392fc9709a3	579
AnnaBridge	189:f392fc9709a3	580	/**
AnnaBridge	189:f392fc9709a3	581	* @brief Write a value in RCC register
AnnaBridge	189:f392fc9709a3	582	* @param __REG__ Register to be written
AnnaBridge	189:f392fc9709a3	583	* @param __VALUE__ Value to be written in the register
AnnaBridge	189:f392fc9709a3	584	* @retval None
AnnaBridge	189:f392fc9709a3	585	*/
AnnaBridge	189:f392fc9709a3	586	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
AnnaBridge	189:f392fc9709a3	587
AnnaBridge	189:f392fc9709a3	588	/**
AnnaBridge	189:f392fc9709a3	589	* @brief Read a value in RCC register
AnnaBridge	189:f392fc9709a3	590	* @param __REG__ Register to be read
AnnaBridge	189:f392fc9709a3	591	* @retval Register value
AnnaBridge	189:f392fc9709a3	592	*/
AnnaBridge	189:f392fc9709a3	593	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
AnnaBridge	189:f392fc9709a3	594	/**
AnnaBridge	189:f392fc9709a3	595	* @}
AnnaBridge	189:f392fc9709a3	596	*/
AnnaBridge	189:f392fc9709a3	597
AnnaBridge	189:f392fc9709a3	598	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
AnnaBridge	189:f392fc9709a3	599	* @{
AnnaBridge	189:f392fc9709a3	600	*/
AnnaBridge	189:f392fc9709a3	601
AnnaBridge	189:f392fc9709a3	602	/**
AnnaBridge	189:f392fc9709a3	603	* @brief Helper macro to calculate the PLLCLK frequency
AnnaBridge	189:f392fc9709a3	604	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,
AnnaBridge	189:f392fc9709a3	605	* @ref LL_RCC_PLL_GetMultiplicator (),
AnnaBridge	189:f392fc9709a3	606	* @ref LL_RCC_PLL_GetDivider ());
AnnaBridge	189:f392fc9709a3	607	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	189:f392fc9709a3	608	* @param __PLLMUL__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	609	* @arg @ref LL_RCC_PLL_MUL_3
AnnaBridge	189:f392fc9709a3	610	* @arg @ref LL_RCC_PLL_MUL_4
AnnaBridge	189:f392fc9709a3	611	* @arg @ref LL_RCC_PLL_MUL_6
AnnaBridge	189:f392fc9709a3	612	* @arg @ref LL_RCC_PLL_MUL_8
AnnaBridge	189:f392fc9709a3	613	* @arg @ref LL_RCC_PLL_MUL_12
AnnaBridge	189:f392fc9709a3	614	* @arg @ref LL_RCC_PLL_MUL_16
AnnaBridge	189:f392fc9709a3	615	* @arg @ref LL_RCC_PLL_MUL_24
AnnaBridge	189:f392fc9709a3	616	* @arg @ref LL_RCC_PLL_MUL_32
AnnaBridge	189:f392fc9709a3	617	* @arg @ref LL_RCC_PLL_MUL_48
AnnaBridge	189:f392fc9709a3	618	* @param __PLLDIV__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	619	* @arg @ref LL_RCC_PLL_DIV_2
AnnaBridge	189:f392fc9709a3	620	* @arg @ref LL_RCC_PLL_DIV_3
AnnaBridge	189:f392fc9709a3	621	* @arg @ref LL_RCC_PLL_DIV_4
AnnaBridge	189:f392fc9709a3	622	* @retval PLL clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	623	*/
AnnaBridge	189:f392fc9709a3	624	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_POSITION_PLLMUL]) / (((__PLLDIV__) >> RCC_POSITION_PLLDIV)+1U))
AnnaBridge	189:f392fc9709a3	625
AnnaBridge	189:f392fc9709a3	626	/**
AnnaBridge	189:f392fc9709a3	627	* @brief Helper macro to calculate the HCLK frequency
AnnaBridge	189:f392fc9709a3	628	* @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
AnnaBridge	189:f392fc9709a3	629	* ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
AnnaBridge	189:f392fc9709a3	630	* @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
AnnaBridge	189:f392fc9709a3	631	* @param __AHBPRESCALER__: This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	632	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	189:f392fc9709a3	633	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	189:f392fc9709a3	634	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	189:f392fc9709a3	635	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	189:f392fc9709a3	636	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	189:f392fc9709a3	637	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	189:f392fc9709a3	638	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	189:f392fc9709a3	639	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	189:f392fc9709a3	640	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	189:f392fc9709a3	641	* @retval HCLK clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	642	*/
AnnaBridge	189:f392fc9709a3	643	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE])
AnnaBridge	189:f392fc9709a3	644
AnnaBridge	189:f392fc9709a3	645	/**
AnnaBridge	189:f392fc9709a3	646	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
AnnaBridge	189:f392fc9709a3	647	* @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
AnnaBridge	189:f392fc9709a3	648	* ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
AnnaBridge	189:f392fc9709a3	649	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	189:f392fc9709a3	650	* @param __APB1PRESCALER__: This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	651	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	189:f392fc9709a3	652	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	189:f392fc9709a3	653	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	189:f392fc9709a3	654	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	189:f392fc9709a3	655	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	189:f392fc9709a3	656	* @retval PCLK1 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	657	*/
AnnaBridge	189:f392fc9709a3	658	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1])
AnnaBridge	189:f392fc9709a3	659
AnnaBridge	189:f392fc9709a3	660	/**
AnnaBridge	189:f392fc9709a3	661	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
AnnaBridge	189:f392fc9709a3	662	* @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
AnnaBridge	189:f392fc9709a3	663	* ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
AnnaBridge	189:f392fc9709a3	664	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	189:f392fc9709a3	665	* @param __APB2PRESCALER__: This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	666	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	189:f392fc9709a3	667	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	189:f392fc9709a3	668	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	189:f392fc9709a3	669	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	189:f392fc9709a3	670	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	189:f392fc9709a3	671	* @retval PCLK2 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	672	*/
AnnaBridge	189:f392fc9709a3	673	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2])
AnnaBridge	189:f392fc9709a3	674
AnnaBridge	189:f392fc9709a3	675	/**
AnnaBridge	189:f392fc9709a3	676	* @brief Helper macro to calculate the MSI frequency (in Hz)
AnnaBridge	189:f392fc9709a3	677	* @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange
AnnaBridge	189:f392fc9709a3	678	* ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange())
AnnaBridge	189:f392fc9709a3	679	* @param __MSIRANGE__: This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	680	* @arg @ref LL_RCC_MSIRANGE_0
AnnaBridge	189:f392fc9709a3	681	* @arg @ref LL_RCC_MSIRANGE_1
AnnaBridge	189:f392fc9709a3	682	* @arg @ref LL_RCC_MSIRANGE_2
AnnaBridge	189:f392fc9709a3	683	* @arg @ref LL_RCC_MSIRANGE_3
AnnaBridge	189:f392fc9709a3	684	* @arg @ref LL_RCC_MSIRANGE_4
AnnaBridge	189:f392fc9709a3	685	* @arg @ref LL_RCC_MSIRANGE_5
AnnaBridge	189:f392fc9709a3	686	* @arg @ref LL_RCC_MSIRANGE_6
AnnaBridge	189:f392fc9709a3	687	* @retval MSI clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	688	*/
AnnaBridge	189:f392fc9709a3	689	#define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) ((32768U * ( 1U << (((__MSIRANGE__) >> RCC_POSITION_MSIRANGE) + 1U))))
AnnaBridge	189:f392fc9709a3	690
AnnaBridge	189:f392fc9709a3	691	/**
AnnaBridge	189:f392fc9709a3	692	* @}
AnnaBridge	189:f392fc9709a3	693	*/
AnnaBridge	189:f392fc9709a3	694
AnnaBridge	189:f392fc9709a3	695	/**
AnnaBridge	189:f392fc9709a3	696	* @}
AnnaBridge	189:f392fc9709a3	697	*/
AnnaBridge	189:f392fc9709a3	698
AnnaBridge	189:f392fc9709a3	699	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	700	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
AnnaBridge	189:f392fc9709a3	701	* @{
AnnaBridge	189:f392fc9709a3	702	*/
AnnaBridge	189:f392fc9709a3	703
AnnaBridge	189:f392fc9709a3	704	/** @defgroup RCC_LL_EF_HSE HSE
AnnaBridge	189:f392fc9709a3	705	* @{
AnnaBridge	189:f392fc9709a3	706	*/
AnnaBridge	189:f392fc9709a3	707
AnnaBridge	189:f392fc9709a3	708	#if defined(RCC_HSECSS_SUPPORT)
AnnaBridge	189:f392fc9709a3	709	/**
AnnaBridge	189:f392fc9709a3	710	* @brief Enable the Clock Security System.
AnnaBridge	189:f392fc9709a3	711	* @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS
AnnaBridge	189:f392fc9709a3	712	* @retval None
AnnaBridge	189:f392fc9709a3	713	*/
AnnaBridge	189:f392fc9709a3	714	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
AnnaBridge	189:f392fc9709a3	715	{
AnnaBridge	189:f392fc9709a3	716	SET_BIT(RCC->CR, RCC_CR_CSSON);
AnnaBridge	189:f392fc9709a3	717	}
AnnaBridge	189:f392fc9709a3	718	#endif /* RCC_HSECSS_SUPPORT */
AnnaBridge	189:f392fc9709a3	719
AnnaBridge	189:f392fc9709a3	720	/**
AnnaBridge	189:f392fc9709a3	721	* @brief Enable HSE external oscillator (HSE Bypass)
AnnaBridge	189:f392fc9709a3	722	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
AnnaBridge	189:f392fc9709a3	723	* @retval None
AnnaBridge	189:f392fc9709a3	724	*/
AnnaBridge	189:f392fc9709a3	725	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
AnnaBridge	189:f392fc9709a3	726	{
AnnaBridge	189:f392fc9709a3	727	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	189:f392fc9709a3	728	}
AnnaBridge	189:f392fc9709a3	729
AnnaBridge	189:f392fc9709a3	730	/**
AnnaBridge	189:f392fc9709a3	731	* @brief Disable HSE external oscillator (HSE Bypass)
AnnaBridge	189:f392fc9709a3	732	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
AnnaBridge	189:f392fc9709a3	733	* @retval None
AnnaBridge	189:f392fc9709a3	734	*/
AnnaBridge	189:f392fc9709a3	735	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
AnnaBridge	189:f392fc9709a3	736	{
AnnaBridge	189:f392fc9709a3	737	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	189:f392fc9709a3	738	}
AnnaBridge	189:f392fc9709a3	739
AnnaBridge	189:f392fc9709a3	740	/**
AnnaBridge	189:f392fc9709a3	741	* @brief Enable HSE crystal oscillator (HSE ON)
AnnaBridge	189:f392fc9709a3	742	* @rmtoll CR HSEON LL_RCC_HSE_Enable
AnnaBridge	189:f392fc9709a3	743	* @retval None
AnnaBridge	189:f392fc9709a3	744	*/
AnnaBridge	189:f392fc9709a3	745	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
AnnaBridge	189:f392fc9709a3	746	{
AnnaBridge	189:f392fc9709a3	747	SET_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	189:f392fc9709a3	748	}
AnnaBridge	189:f392fc9709a3	749
AnnaBridge	189:f392fc9709a3	750	/**
AnnaBridge	189:f392fc9709a3	751	* @brief Disable HSE crystal oscillator (HSE ON)
AnnaBridge	189:f392fc9709a3	752	* @rmtoll CR HSEON LL_RCC_HSE_Disable
AnnaBridge	189:f392fc9709a3	753	* @retval None
AnnaBridge	189:f392fc9709a3	754	*/
AnnaBridge	189:f392fc9709a3	755	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
AnnaBridge	189:f392fc9709a3	756	{
AnnaBridge	189:f392fc9709a3	757	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	189:f392fc9709a3	758	}
AnnaBridge	189:f392fc9709a3	759
AnnaBridge	189:f392fc9709a3	760	/**
AnnaBridge	189:f392fc9709a3	761	* @brief Check if HSE oscillator Ready
AnnaBridge	189:f392fc9709a3	762	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
AnnaBridge	189:f392fc9709a3	763	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	764	*/
AnnaBridge	189:f392fc9709a3	765	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
AnnaBridge	189:f392fc9709a3	766	{
AnnaBridge	189:f392fc9709a3	767	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
AnnaBridge	189:f392fc9709a3	768	}
AnnaBridge	189:f392fc9709a3	769
AnnaBridge	189:f392fc9709a3	770	/**
AnnaBridge	189:f392fc9709a3	771	* @brief Configure the RTC prescaler (divider)
AnnaBridge	189:f392fc9709a3	772	* @rmtoll CR RTCPRE LL_RCC_SetRTC_HSEPrescaler
AnnaBridge	189:f392fc9709a3	773	* @param Div This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	774	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	189:f392fc9709a3	775	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	189:f392fc9709a3	776	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	189:f392fc9709a3	777	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	189:f392fc9709a3	778	* @retval None
AnnaBridge	189:f392fc9709a3	779	*/
AnnaBridge	189:f392fc9709a3	780	__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div)
AnnaBridge	189:f392fc9709a3	781	{
AnnaBridge	189:f392fc9709a3	782	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div);
AnnaBridge	189:f392fc9709a3	783	}
AnnaBridge	189:f392fc9709a3	784
AnnaBridge	189:f392fc9709a3	785	/**
AnnaBridge	189:f392fc9709a3	786	* @brief Get the RTC divider (prescaler)
AnnaBridge	189:f392fc9709a3	787	* @rmtoll CR RTCPRE LL_RCC_GetRTC_HSEPrescaler
AnnaBridge	189:f392fc9709a3	788	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	789	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	189:f392fc9709a3	790	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	189:f392fc9709a3	791	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	189:f392fc9709a3	792	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	189:f392fc9709a3	793	*/
AnnaBridge	189:f392fc9709a3	794	__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
AnnaBridge	189:f392fc9709a3	795	{
AnnaBridge	189:f392fc9709a3	796	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE));
AnnaBridge	189:f392fc9709a3	797	}
AnnaBridge	189:f392fc9709a3	798
AnnaBridge	189:f392fc9709a3	799	/**
AnnaBridge	189:f392fc9709a3	800	* @}
AnnaBridge	189:f392fc9709a3	801	*/
AnnaBridge	189:f392fc9709a3	802
AnnaBridge	189:f392fc9709a3	803	/** @defgroup RCC_LL_EF_HSI HSI
AnnaBridge	189:f392fc9709a3	804	* @{
AnnaBridge	189:f392fc9709a3	805	*/
AnnaBridge	189:f392fc9709a3	806
AnnaBridge	189:f392fc9709a3	807	/**
AnnaBridge	189:f392fc9709a3	808	* @brief Enable HSI oscillator
AnnaBridge	189:f392fc9709a3	809	* @rmtoll CR HSION LL_RCC_HSI_Enable
AnnaBridge	189:f392fc9709a3	810	* @retval None
AnnaBridge	189:f392fc9709a3	811	*/
AnnaBridge	189:f392fc9709a3	812	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
AnnaBridge	189:f392fc9709a3	813	{
AnnaBridge	189:f392fc9709a3	814	SET_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	189:f392fc9709a3	815	}
AnnaBridge	189:f392fc9709a3	816
AnnaBridge	189:f392fc9709a3	817	/**
AnnaBridge	189:f392fc9709a3	818	* @brief Disable HSI oscillator
AnnaBridge	189:f392fc9709a3	819	* @rmtoll CR HSION LL_RCC_HSI_Disable
AnnaBridge	189:f392fc9709a3	820	* @retval None
AnnaBridge	189:f392fc9709a3	821	*/
AnnaBridge	189:f392fc9709a3	822	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
AnnaBridge	189:f392fc9709a3	823	{
AnnaBridge	189:f392fc9709a3	824	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	189:f392fc9709a3	825	}
AnnaBridge	189:f392fc9709a3	826
AnnaBridge	189:f392fc9709a3	827	/**
AnnaBridge	189:f392fc9709a3	828	* @brief Check if HSI clock is ready
AnnaBridge	189:f392fc9709a3	829	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
AnnaBridge	189:f392fc9709a3	830	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	831	*/
AnnaBridge	189:f392fc9709a3	832	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
AnnaBridge	189:f392fc9709a3	833	{
AnnaBridge	189:f392fc9709a3	834	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
AnnaBridge	189:f392fc9709a3	835	}
AnnaBridge	189:f392fc9709a3	836
AnnaBridge	189:f392fc9709a3	837	/**
AnnaBridge	189:f392fc9709a3	838	* @brief Enable HSI even in stop mode
AnnaBridge	189:f392fc9709a3	839	* @note HSI oscillator is forced ON even in Stop mode
AnnaBridge	189:f392fc9709a3	840	* @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
AnnaBridge	189:f392fc9709a3	841	* @retval None
AnnaBridge	189:f392fc9709a3	842	*/
AnnaBridge	189:f392fc9709a3	843	__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
AnnaBridge	189:f392fc9709a3	844	{
AnnaBridge	189:f392fc9709a3	845	SET_BIT(RCC->CR, RCC_CR_HSIKERON);
AnnaBridge	189:f392fc9709a3	846	}
AnnaBridge	189:f392fc9709a3	847
AnnaBridge	189:f392fc9709a3	848	/**
AnnaBridge	189:f392fc9709a3	849	* @brief Disable HSI in stop mode
AnnaBridge	189:f392fc9709a3	850	* @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
AnnaBridge	189:f392fc9709a3	851	* @retval None
AnnaBridge	189:f392fc9709a3	852	*/
AnnaBridge	189:f392fc9709a3	853	__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
AnnaBridge	189:f392fc9709a3	854	{
AnnaBridge	189:f392fc9709a3	855	CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
AnnaBridge	189:f392fc9709a3	856	}
AnnaBridge	189:f392fc9709a3	857
AnnaBridge	189:f392fc9709a3	858	/**
AnnaBridge	189:f392fc9709a3	859	* @brief Enable HSI Divider (it divides by 4)
AnnaBridge	189:f392fc9709a3	860	* @rmtoll CR HSIDIVEN LL_RCC_HSI_EnableDivider
AnnaBridge	189:f392fc9709a3	861	* @retval None
AnnaBridge	189:f392fc9709a3	862	*/
AnnaBridge	189:f392fc9709a3	863	__STATIC_INLINE void LL_RCC_HSI_EnableDivider(void)
AnnaBridge	189:f392fc9709a3	864	{
AnnaBridge	189:f392fc9709a3	865	SET_BIT(RCC->CR, RCC_CR_HSIDIVEN);
AnnaBridge	189:f392fc9709a3	866	}
AnnaBridge	189:f392fc9709a3	867
AnnaBridge	189:f392fc9709a3	868	/**
AnnaBridge	189:f392fc9709a3	869	* @brief Disable HSI Divider (it divides by 4)
AnnaBridge	189:f392fc9709a3	870	* @rmtoll CR HSIDIVEN LL_RCC_HSI_DisableDivider
AnnaBridge	189:f392fc9709a3	871	* @retval None
AnnaBridge	189:f392fc9709a3	872	*/
AnnaBridge	189:f392fc9709a3	873	__STATIC_INLINE void LL_RCC_HSI_DisableDivider(void)
AnnaBridge	189:f392fc9709a3	874	{
AnnaBridge	189:f392fc9709a3	875	CLEAR_BIT(RCC->CR, RCC_CR_HSIDIVEN);
AnnaBridge	189:f392fc9709a3	876	}
AnnaBridge	189:f392fc9709a3	877
AnnaBridge	189:f392fc9709a3	878
AnnaBridge	189:f392fc9709a3	879
AnnaBridge	189:f392fc9709a3	880	#if defined(RCC_CR_HSIOUTEN)
AnnaBridge	189:f392fc9709a3	881	/**
AnnaBridge	189:f392fc9709a3	882	* @brief Enable HSI Output
AnnaBridge	189:f392fc9709a3	883	* @rmtoll CR HSIOUTEN LL_RCC_HSI_EnableOutput
AnnaBridge	189:f392fc9709a3	884	* @retval None
AnnaBridge	189:f392fc9709a3	885	*/
AnnaBridge	189:f392fc9709a3	886	__STATIC_INLINE void LL_RCC_HSI_EnableOutput(void)
AnnaBridge	189:f392fc9709a3	887	{
AnnaBridge	189:f392fc9709a3	888	SET_BIT(RCC->CR, RCC_CR_HSIOUTEN);
AnnaBridge	189:f392fc9709a3	889	}
AnnaBridge	189:f392fc9709a3	890
AnnaBridge	189:f392fc9709a3	891	/**
AnnaBridge	189:f392fc9709a3	892	* @brief Disable HSI Output
AnnaBridge	189:f392fc9709a3	893	* @rmtoll CR HSIOUTEN LL_RCC_HSI_DisableOutput
AnnaBridge	189:f392fc9709a3	894	* @retval None
AnnaBridge	189:f392fc9709a3	895	*/
AnnaBridge	189:f392fc9709a3	896	__STATIC_INLINE void LL_RCC_HSI_DisableOutput(void)
AnnaBridge	189:f392fc9709a3	897	{
AnnaBridge	189:f392fc9709a3	898	CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN);
AnnaBridge	189:f392fc9709a3	899	}
AnnaBridge	189:f392fc9709a3	900	#endif /* RCC_CR_HSIOUTEN */
AnnaBridge	189:f392fc9709a3	901
AnnaBridge	189:f392fc9709a3	902	/**
AnnaBridge	189:f392fc9709a3	903	* @brief Get HSI Calibration value
AnnaBridge	189:f392fc9709a3	904	* @note When HSITRIM is written, HSICAL is updated with the sum of
AnnaBridge	189:f392fc9709a3	905	* HSITRIM and the factory trim value
AnnaBridge	189:f392fc9709a3	906	* @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
AnnaBridge	189:f392fc9709a3	907	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	189:f392fc9709a3	908	*/
AnnaBridge	189:f392fc9709a3	909	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
AnnaBridge	189:f392fc9709a3	910	{
AnnaBridge	189:f392fc9709a3	911	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL);
AnnaBridge	189:f392fc9709a3	912	}
AnnaBridge	189:f392fc9709a3	913
AnnaBridge	189:f392fc9709a3	914	/**
AnnaBridge	189:f392fc9709a3	915	* @brief Set HSI Calibration trimming
AnnaBridge	189:f392fc9709a3	916	* @note user-programmable trimming value that is added to the HSICAL
AnnaBridge	189:f392fc9709a3	917	* @note Default value is 16, which, when added to the HSICAL value,
AnnaBridge	189:f392fc9709a3	918	* should trim the HSI to 16 MHz +/- 1 %
AnnaBridge	189:f392fc9709a3	919	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
AnnaBridge	189:f392fc9709a3	920	* @param Value between Min_Data = 0x00 and Max_Data = 0x1F
AnnaBridge	189:f392fc9709a3	921	* @retval None
AnnaBridge	189:f392fc9709a3	922	*/
AnnaBridge	189:f392fc9709a3	923	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	189:f392fc9709a3	924	{
AnnaBridge	189:f392fc9709a3	925	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM);
AnnaBridge	189:f392fc9709a3	926	}
AnnaBridge	189:f392fc9709a3	927
AnnaBridge	189:f392fc9709a3	928	/**
AnnaBridge	189:f392fc9709a3	929	* @brief Get HSI Calibration trimming
AnnaBridge	189:f392fc9709a3	930	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
AnnaBridge	189:f392fc9709a3	931	* @retval Between Min_Data = 0x00 and Max_Data = 0x1F
AnnaBridge	189:f392fc9709a3	932	*/
AnnaBridge	189:f392fc9709a3	933	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
AnnaBridge	189:f392fc9709a3	934	{
AnnaBridge	189:f392fc9709a3	935	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM);
AnnaBridge	189:f392fc9709a3	936	}
AnnaBridge	189:f392fc9709a3	937
AnnaBridge	189:f392fc9709a3	938	/**
AnnaBridge	189:f392fc9709a3	939	* @}
AnnaBridge	189:f392fc9709a3	940	*/
AnnaBridge	189:f392fc9709a3	941
AnnaBridge	189:f392fc9709a3	942	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	943	/** @defgroup RCC_LL_EF_HSI48 HSI48
AnnaBridge	189:f392fc9709a3	944	* @{
AnnaBridge	189:f392fc9709a3	945	*/
AnnaBridge	189:f392fc9709a3	946
AnnaBridge	189:f392fc9709a3	947	/**
AnnaBridge	189:f392fc9709a3	948	* @brief Enable HSI48
AnnaBridge	189:f392fc9709a3	949	* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
AnnaBridge	189:f392fc9709a3	950	* @retval None
AnnaBridge	189:f392fc9709a3	951	*/
AnnaBridge	189:f392fc9709a3	952	__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
AnnaBridge	189:f392fc9709a3	953	{
AnnaBridge	189:f392fc9709a3	954	SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
AnnaBridge	189:f392fc9709a3	955	}
AnnaBridge	189:f392fc9709a3	956
AnnaBridge	189:f392fc9709a3	957	/**
AnnaBridge	189:f392fc9709a3	958	* @brief Disable HSI48
AnnaBridge	189:f392fc9709a3	959	* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
AnnaBridge	189:f392fc9709a3	960	* @retval None
AnnaBridge	189:f392fc9709a3	961	*/
AnnaBridge	189:f392fc9709a3	962	__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
AnnaBridge	189:f392fc9709a3	963	{
AnnaBridge	189:f392fc9709a3	964	CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
AnnaBridge	189:f392fc9709a3	965	}
AnnaBridge	189:f392fc9709a3	966
AnnaBridge	189:f392fc9709a3	967	/**
AnnaBridge	189:f392fc9709a3	968	* @brief Check if HSI48 oscillator Ready
AnnaBridge	189:f392fc9709a3	969	* @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
AnnaBridge	189:f392fc9709a3	970	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	971	*/
AnnaBridge	189:f392fc9709a3	972	__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
AnnaBridge	189:f392fc9709a3	973	{
AnnaBridge	189:f392fc9709a3	974	return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY));
AnnaBridge	189:f392fc9709a3	975	}
AnnaBridge	189:f392fc9709a3	976
AnnaBridge	189:f392fc9709a3	977	/**
AnnaBridge	189:f392fc9709a3	978	* @brief Get HSI48 Calibration value
AnnaBridge	189:f392fc9709a3	979	* @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
AnnaBridge	189:f392fc9709a3	980	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	189:f392fc9709a3	981	*/
AnnaBridge	189:f392fc9709a3	982	__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
AnnaBridge	189:f392fc9709a3	983	{
AnnaBridge	189:f392fc9709a3	984	return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_POSITION_HSI48CAL);
AnnaBridge	189:f392fc9709a3	985	}
AnnaBridge	189:f392fc9709a3	986
AnnaBridge	189:f392fc9709a3	987	#if defined(RCC_CRRCR_HSI48DIV6OUTEN)
AnnaBridge	189:f392fc9709a3	988	/**
AnnaBridge	189:f392fc9709a3	989	* @brief Enable HSI48 Divider (it divides by 6)
AnnaBridge	189:f392fc9709a3	990	* @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_EnableDivider
AnnaBridge	189:f392fc9709a3	991	* @retval None
AnnaBridge	189:f392fc9709a3	992	*/
AnnaBridge	189:f392fc9709a3	993	__STATIC_INLINE void LL_RCC_HSI48_EnableDivider(void)
AnnaBridge	189:f392fc9709a3	994	{
AnnaBridge	189:f392fc9709a3	995	SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN);
AnnaBridge	189:f392fc9709a3	996	}
AnnaBridge	189:f392fc9709a3	997
AnnaBridge	189:f392fc9709a3	998	/**
AnnaBridge	189:f392fc9709a3	999	* @brief Disable HSI48 Divider (it divides by 6)
AnnaBridge	189:f392fc9709a3	1000	* @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_DisableDivider
AnnaBridge	189:f392fc9709a3	1001	* @retval None
AnnaBridge	189:f392fc9709a3	1002	*/
AnnaBridge	189:f392fc9709a3	1003	__STATIC_INLINE void LL_RCC_HSI48_DisableDivider(void)
AnnaBridge	189:f392fc9709a3	1004	{
AnnaBridge	189:f392fc9709a3	1005	CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN);
AnnaBridge	189:f392fc9709a3	1006	}
AnnaBridge	189:f392fc9709a3	1007
AnnaBridge	189:f392fc9709a3	1008	/**
AnnaBridge	189:f392fc9709a3	1009	* @brief Check if HSI48 Divider is enabled (it divides by 6)
AnnaBridge	189:f392fc9709a3	1010	* @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_IsDivided
AnnaBridge	189:f392fc9709a3	1011	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1012	*/
AnnaBridge	189:f392fc9709a3	1013	__STATIC_INLINE uint32_t LL_RCC_HSI48_IsDivided(void)
AnnaBridge	189:f392fc9709a3	1014	{
AnnaBridge	189:f392fc9709a3	1015	return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN) == (RCC_CRRCR_HSI48DIV6OUTEN));
AnnaBridge	189:f392fc9709a3	1016	}
AnnaBridge	189:f392fc9709a3	1017
AnnaBridge	189:f392fc9709a3	1018	#endif /RCC_CRRCR_HSI48DIV6OUTEN/
AnnaBridge	189:f392fc9709a3	1019
AnnaBridge	189:f392fc9709a3	1020	/**
AnnaBridge	189:f392fc9709a3	1021	* @}
AnnaBridge	189:f392fc9709a3	1022	*/
AnnaBridge	189:f392fc9709a3	1023
AnnaBridge	189:f392fc9709a3	1024	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	1025
AnnaBridge	189:f392fc9709a3	1026	/** @defgroup RCC_LL_EF_LSE LSE
AnnaBridge	189:f392fc9709a3	1027	* @{
AnnaBridge	189:f392fc9709a3	1028	*/
AnnaBridge	189:f392fc9709a3	1029
AnnaBridge	189:f392fc9709a3	1030	/**
AnnaBridge	189:f392fc9709a3	1031	* @brief Enable Low Speed External (LSE) crystal.
AnnaBridge	189:f392fc9709a3	1032	* @rmtoll CSR LSEON LL_RCC_LSE_Enable
AnnaBridge	189:f392fc9709a3	1033	* @retval None
AnnaBridge	189:f392fc9709a3	1034	*/
AnnaBridge	189:f392fc9709a3	1035	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
AnnaBridge	189:f392fc9709a3	1036	{
AnnaBridge	189:f392fc9709a3	1037	SET_BIT(RCC->CSR, RCC_CSR_LSEON);
AnnaBridge	189:f392fc9709a3	1038	}
AnnaBridge	189:f392fc9709a3	1039
AnnaBridge	189:f392fc9709a3	1040	/**
AnnaBridge	189:f392fc9709a3	1041	* @brief Disable Low Speed External (LSE) crystal.
AnnaBridge	189:f392fc9709a3	1042	* @rmtoll CSR LSEON LL_RCC_LSE_Disable
AnnaBridge	189:f392fc9709a3	1043	* @retval None
AnnaBridge	189:f392fc9709a3	1044	*/
AnnaBridge	189:f392fc9709a3	1045	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
AnnaBridge	189:f392fc9709a3	1046	{
AnnaBridge	189:f392fc9709a3	1047	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);
AnnaBridge	189:f392fc9709a3	1048	}
AnnaBridge	189:f392fc9709a3	1049
AnnaBridge	189:f392fc9709a3	1050	/**
AnnaBridge	189:f392fc9709a3	1051	* @brief Enable external clock source (LSE bypass).
AnnaBridge	189:f392fc9709a3	1052	* @rmtoll CSR LSEBYP LL_RCC_LSE_EnableBypass
AnnaBridge	189:f392fc9709a3	1053	* @retval None
AnnaBridge	189:f392fc9709a3	1054	*/
AnnaBridge	189:f392fc9709a3	1055	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
AnnaBridge	189:f392fc9709a3	1056	{
AnnaBridge	189:f392fc9709a3	1057	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);
AnnaBridge	189:f392fc9709a3	1058	}
AnnaBridge	189:f392fc9709a3	1059
AnnaBridge	189:f392fc9709a3	1060	/**
AnnaBridge	189:f392fc9709a3	1061	* @brief Disable external clock source (LSE bypass).
AnnaBridge	189:f392fc9709a3	1062	* @rmtoll CSR LSEBYP LL_RCC_LSE_DisableBypass
AnnaBridge	189:f392fc9709a3	1063	* @retval None
AnnaBridge	189:f392fc9709a3	1064	*/
AnnaBridge	189:f392fc9709a3	1065	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
AnnaBridge	189:f392fc9709a3	1066	{
AnnaBridge	189:f392fc9709a3	1067	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);
AnnaBridge	189:f392fc9709a3	1068	}
AnnaBridge	189:f392fc9709a3	1069
AnnaBridge	189:f392fc9709a3	1070	/**
AnnaBridge	189:f392fc9709a3	1071	* @brief Set LSE oscillator drive capability
AnnaBridge	189:f392fc9709a3	1072	* @note The oscillator is in Xtal mode when it is not in bypass mode.
AnnaBridge	189:f392fc9709a3	1073	* @rmtoll CSR LSEDRV LL_RCC_LSE_SetDriveCapability
AnnaBridge	189:f392fc9709a3	1074	* @param LSEDrive This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1075	* @arg @ref LL_RCC_LSEDRIVE_LOW
AnnaBridge	189:f392fc9709a3	1076	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
AnnaBridge	189:f392fc9709a3	1077	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
AnnaBridge	189:f392fc9709a3	1078	* @arg @ref LL_RCC_LSEDRIVE_HIGH
AnnaBridge	189:f392fc9709a3	1079	* @retval None
AnnaBridge	189:f392fc9709a3	1080	*/
AnnaBridge	189:f392fc9709a3	1081	__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
AnnaBridge	189:f392fc9709a3	1082	{
AnnaBridge	189:f392fc9709a3	1083	MODIFY_REG(RCC->CSR, RCC_CSR_LSEDRV, LSEDrive);
AnnaBridge	189:f392fc9709a3	1084	}
AnnaBridge	189:f392fc9709a3	1085
AnnaBridge	189:f392fc9709a3	1086	/**
AnnaBridge	189:f392fc9709a3	1087	* @brief Get LSE oscillator drive capability
AnnaBridge	189:f392fc9709a3	1088	* @rmtoll CSR LSEDRV LL_RCC_LSE_GetDriveCapability
AnnaBridge	189:f392fc9709a3	1089	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1090	* @arg @ref LL_RCC_LSEDRIVE_LOW
AnnaBridge	189:f392fc9709a3	1091	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
AnnaBridge	189:f392fc9709a3	1092	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
AnnaBridge	189:f392fc9709a3	1093	* @arg @ref LL_RCC_LSEDRIVE_HIGH
AnnaBridge	189:f392fc9709a3	1094	*/
AnnaBridge	189:f392fc9709a3	1095	__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
AnnaBridge	189:f392fc9709a3	1096	{
AnnaBridge	189:f392fc9709a3	1097	return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_LSEDRV));
AnnaBridge	189:f392fc9709a3	1098	}
AnnaBridge	189:f392fc9709a3	1099
AnnaBridge	189:f392fc9709a3	1100	/**
AnnaBridge	189:f392fc9709a3	1101	* @brief Enable Clock security system on LSE.
AnnaBridge	189:f392fc9709a3	1102	* @rmtoll CSR LSECSSON LL_RCC_LSE_EnableCSS
AnnaBridge	189:f392fc9709a3	1103	* @retval None
AnnaBridge	189:f392fc9709a3	1104	*/
AnnaBridge	189:f392fc9709a3	1105	__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
AnnaBridge	189:f392fc9709a3	1106	{
AnnaBridge	189:f392fc9709a3	1107	SET_BIT(RCC->CSR, RCC_CSR_LSECSSON);
AnnaBridge	189:f392fc9709a3	1108	}
AnnaBridge	189:f392fc9709a3	1109
AnnaBridge	189:f392fc9709a3	1110	/**
AnnaBridge	189:f392fc9709a3	1111	* @brief Disable Clock security system on LSE.
AnnaBridge	189:f392fc9709a3	1112	* @note Clock security system can be disabled only after a LSE
AnnaBridge	189:f392fc9709a3	1113	* failure detection. In that case it MUST be disabled by software.
AnnaBridge	189:f392fc9709a3	1114	* @rmtoll CSR LSECSSON LL_RCC_LSE_DisableCSS
AnnaBridge	189:f392fc9709a3	1115	* @retval None
AnnaBridge	189:f392fc9709a3	1116	*/
AnnaBridge	189:f392fc9709a3	1117	__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
AnnaBridge	189:f392fc9709a3	1118	{
AnnaBridge	189:f392fc9709a3	1119	CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON);
AnnaBridge	189:f392fc9709a3	1120	}
AnnaBridge	189:f392fc9709a3	1121
AnnaBridge	189:f392fc9709a3	1122	/**
AnnaBridge	189:f392fc9709a3	1123	* @brief Check if LSE oscillator Ready
AnnaBridge	189:f392fc9709a3	1124	* @rmtoll CSR LSERDY LL_RCC_LSE_IsReady
AnnaBridge	189:f392fc9709a3	1125	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1126	*/
AnnaBridge	189:f392fc9709a3	1127	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
AnnaBridge	189:f392fc9709a3	1128	{
AnnaBridge	189:f392fc9709a3	1129	return (READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == (RCC_CSR_LSERDY));
AnnaBridge	189:f392fc9709a3	1130	}
AnnaBridge	189:f392fc9709a3	1131
AnnaBridge	189:f392fc9709a3	1132	/**
AnnaBridge	189:f392fc9709a3	1133	* @brief Check if CSS on LSE failure Detection
AnnaBridge	189:f392fc9709a3	1134	* @rmtoll CSR LSECSSD LL_RCC_LSE_IsCSSDetected
AnnaBridge	189:f392fc9709a3	1135	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1136	*/
AnnaBridge	189:f392fc9709a3	1137	__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
AnnaBridge	189:f392fc9709a3	1138	{
AnnaBridge	189:f392fc9709a3	1139	return (READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == (RCC_CSR_LSECSSD));
AnnaBridge	189:f392fc9709a3	1140	}
AnnaBridge	189:f392fc9709a3	1141
AnnaBridge	189:f392fc9709a3	1142	/**
AnnaBridge	189:f392fc9709a3	1143	* @}
AnnaBridge	189:f392fc9709a3	1144	*/
AnnaBridge	189:f392fc9709a3	1145
AnnaBridge	189:f392fc9709a3	1146	/** @defgroup RCC_LL_EF_LSI LSI
AnnaBridge	189:f392fc9709a3	1147	* @{
AnnaBridge	189:f392fc9709a3	1148	*/
AnnaBridge	189:f392fc9709a3	1149
AnnaBridge	189:f392fc9709a3	1150	/**
AnnaBridge	189:f392fc9709a3	1151	* @brief Enable LSI Oscillator
AnnaBridge	189:f392fc9709a3	1152	* @rmtoll CSR LSION LL_RCC_LSI_Enable
AnnaBridge	189:f392fc9709a3	1153	* @retval None
AnnaBridge	189:f392fc9709a3	1154	*/
AnnaBridge	189:f392fc9709a3	1155	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
AnnaBridge	189:f392fc9709a3	1156	{
AnnaBridge	189:f392fc9709a3	1157	SET_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	189:f392fc9709a3	1158	}
AnnaBridge	189:f392fc9709a3	1159
AnnaBridge	189:f392fc9709a3	1160	/**
AnnaBridge	189:f392fc9709a3	1161	* @brief Disable LSI Oscillator
AnnaBridge	189:f392fc9709a3	1162	* @rmtoll CSR LSION LL_RCC_LSI_Disable
AnnaBridge	189:f392fc9709a3	1163	* @retval None
AnnaBridge	189:f392fc9709a3	1164	*/
AnnaBridge	189:f392fc9709a3	1165	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
AnnaBridge	189:f392fc9709a3	1166	{
AnnaBridge	189:f392fc9709a3	1167	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	189:f392fc9709a3	1168	}
AnnaBridge	189:f392fc9709a3	1169
AnnaBridge	189:f392fc9709a3	1170	/**
AnnaBridge	189:f392fc9709a3	1171	* @brief Check if LSI is Ready
AnnaBridge	189:f392fc9709a3	1172	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
AnnaBridge	189:f392fc9709a3	1173	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1174	*/
AnnaBridge	189:f392fc9709a3	1175	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
AnnaBridge	189:f392fc9709a3	1176	{
AnnaBridge	189:f392fc9709a3	1177	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
AnnaBridge	189:f392fc9709a3	1178	}
AnnaBridge	189:f392fc9709a3	1179
AnnaBridge	189:f392fc9709a3	1180	/**
AnnaBridge	189:f392fc9709a3	1181	* @}
AnnaBridge	189:f392fc9709a3	1182	*/
AnnaBridge	189:f392fc9709a3	1183
AnnaBridge	189:f392fc9709a3	1184	/** @defgroup RCC_LL_EF_MSI MSI
AnnaBridge	189:f392fc9709a3	1185	* @{
AnnaBridge	189:f392fc9709a3	1186	*/
AnnaBridge	189:f392fc9709a3	1187
AnnaBridge	189:f392fc9709a3	1188	/**
AnnaBridge	189:f392fc9709a3	1189	* @brief Enable MSI oscillator
AnnaBridge	189:f392fc9709a3	1190	* @rmtoll CR MSION LL_RCC_MSI_Enable
AnnaBridge	189:f392fc9709a3	1191	* @retval None
AnnaBridge	189:f392fc9709a3	1192	*/
AnnaBridge	189:f392fc9709a3	1193	__STATIC_INLINE void LL_RCC_MSI_Enable(void)
AnnaBridge	189:f392fc9709a3	1194	{
AnnaBridge	189:f392fc9709a3	1195	SET_BIT(RCC->CR, RCC_CR_MSION);
AnnaBridge	189:f392fc9709a3	1196	}
AnnaBridge	189:f392fc9709a3	1197
AnnaBridge	189:f392fc9709a3	1198	/**
AnnaBridge	189:f392fc9709a3	1199	* @brief Disable MSI oscillator
AnnaBridge	189:f392fc9709a3	1200	* @rmtoll CR MSION LL_RCC_MSI_Disable
AnnaBridge	189:f392fc9709a3	1201	* @retval None
AnnaBridge	189:f392fc9709a3	1202	*/
AnnaBridge	189:f392fc9709a3	1203	__STATIC_INLINE void LL_RCC_MSI_Disable(void)
AnnaBridge	189:f392fc9709a3	1204	{
AnnaBridge	189:f392fc9709a3	1205	CLEAR_BIT(RCC->CR, RCC_CR_MSION);
AnnaBridge	189:f392fc9709a3	1206	}
AnnaBridge	189:f392fc9709a3	1207
AnnaBridge	189:f392fc9709a3	1208	/**
AnnaBridge	189:f392fc9709a3	1209	* @brief Check if MSI oscillator Ready
AnnaBridge	189:f392fc9709a3	1210	* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
AnnaBridge	189:f392fc9709a3	1211	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1212	*/
AnnaBridge	189:f392fc9709a3	1213	__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
AnnaBridge	189:f392fc9709a3	1214	{
AnnaBridge	189:f392fc9709a3	1215	return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
AnnaBridge	189:f392fc9709a3	1216	}
AnnaBridge	189:f392fc9709a3	1217
AnnaBridge	189:f392fc9709a3	1218	/**
AnnaBridge	189:f392fc9709a3	1219	* @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
AnnaBridge	189:f392fc9709a3	1220	* @rmtoll ICSCR MSIRANGE LL_RCC_MSI_SetRange
AnnaBridge	189:f392fc9709a3	1221	* @param Range This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1222	* @arg @ref LL_RCC_MSIRANGE_0
AnnaBridge	189:f392fc9709a3	1223	* @arg @ref LL_RCC_MSIRANGE_1
AnnaBridge	189:f392fc9709a3	1224	* @arg @ref LL_RCC_MSIRANGE_2
AnnaBridge	189:f392fc9709a3	1225	* @arg @ref LL_RCC_MSIRANGE_3
AnnaBridge	189:f392fc9709a3	1226	* @arg @ref LL_RCC_MSIRANGE_4
AnnaBridge	189:f392fc9709a3	1227	* @arg @ref LL_RCC_MSIRANGE_5
AnnaBridge	189:f392fc9709a3	1228	* @arg @ref LL_RCC_MSIRANGE_6
AnnaBridge	189:f392fc9709a3	1229	* @retval None
AnnaBridge	189:f392fc9709a3	1230	*/
AnnaBridge	189:f392fc9709a3	1231	__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
AnnaBridge	189:f392fc9709a3	1232	{
AnnaBridge	189:f392fc9709a3	1233	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
AnnaBridge	189:f392fc9709a3	1234	}
AnnaBridge	189:f392fc9709a3	1235
AnnaBridge	189:f392fc9709a3	1236	/**
AnnaBridge	189:f392fc9709a3	1237	* @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
AnnaBridge	189:f392fc9709a3	1238	* @rmtoll ICSCR MSIRANGE LL_RCC_MSI_GetRange
AnnaBridge	189:f392fc9709a3	1239	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1240	* @arg @ref LL_RCC_MSIRANGE_0
AnnaBridge	189:f392fc9709a3	1241	* @arg @ref LL_RCC_MSIRANGE_1
AnnaBridge	189:f392fc9709a3	1242	* @arg @ref LL_RCC_MSIRANGE_2
AnnaBridge	189:f392fc9709a3	1243	* @arg @ref LL_RCC_MSIRANGE_3
AnnaBridge	189:f392fc9709a3	1244	* @arg @ref LL_RCC_MSIRANGE_4
AnnaBridge	189:f392fc9709a3	1245	* @arg @ref LL_RCC_MSIRANGE_5
AnnaBridge	189:f392fc9709a3	1246	* @arg @ref LL_RCC_MSIRANGE_6
AnnaBridge	189:f392fc9709a3	1247	*/
AnnaBridge	189:f392fc9709a3	1248	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
AnnaBridge	189:f392fc9709a3	1249	{
AnnaBridge	189:f392fc9709a3	1250	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE));
AnnaBridge	189:f392fc9709a3	1251	}
AnnaBridge	189:f392fc9709a3	1252
AnnaBridge	189:f392fc9709a3	1253	/**
AnnaBridge	189:f392fc9709a3	1254	* @brief Get MSI Calibration value
AnnaBridge	189:f392fc9709a3	1255	* @note When MSITRIM is written, MSICAL is updated with the sum of
AnnaBridge	189:f392fc9709a3	1256	* MSITRIM and the factory trim value
AnnaBridge	189:f392fc9709a3	1257	* @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
AnnaBridge	189:f392fc9709a3	1258	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	189:f392fc9709a3	1259	*/
AnnaBridge	189:f392fc9709a3	1260	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
AnnaBridge	189:f392fc9709a3	1261	{
AnnaBridge	189:f392fc9709a3	1262	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL);
AnnaBridge	189:f392fc9709a3	1263	}
AnnaBridge	189:f392fc9709a3	1264
AnnaBridge	189:f392fc9709a3	1265	/**
AnnaBridge	189:f392fc9709a3	1266	* @brief Set MSI Calibration trimming
AnnaBridge	189:f392fc9709a3	1267	* @note user-programmable trimming value that is added to the MSICAL
AnnaBridge	189:f392fc9709a3	1268	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
AnnaBridge	189:f392fc9709a3	1269	* @param Value between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	189:f392fc9709a3	1270	* @retval None
AnnaBridge	189:f392fc9709a3	1271	*/
AnnaBridge	189:f392fc9709a3	1272	__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	189:f392fc9709a3	1273	{
AnnaBridge	189:f392fc9709a3	1274	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM);
AnnaBridge	189:f392fc9709a3	1275	}
AnnaBridge	189:f392fc9709a3	1276
AnnaBridge	189:f392fc9709a3	1277	/**
AnnaBridge	189:f392fc9709a3	1278	* @brief Get MSI Calibration trimming
AnnaBridge	189:f392fc9709a3	1279	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
AnnaBridge	189:f392fc9709a3	1280	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	189:f392fc9709a3	1281	*/
AnnaBridge	189:f392fc9709a3	1282	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
AnnaBridge	189:f392fc9709a3	1283	{
AnnaBridge	189:f392fc9709a3	1284	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM);
AnnaBridge	189:f392fc9709a3	1285	}
AnnaBridge	189:f392fc9709a3	1286
AnnaBridge	189:f392fc9709a3	1287	/**
AnnaBridge	189:f392fc9709a3	1288	* @}
AnnaBridge	189:f392fc9709a3	1289	*/
AnnaBridge	189:f392fc9709a3	1290
AnnaBridge	189:f392fc9709a3	1291	/** @defgroup RCC_LL_EF_System System
AnnaBridge	189:f392fc9709a3	1292	* @{
AnnaBridge	189:f392fc9709a3	1293	*/
AnnaBridge	189:f392fc9709a3	1294
AnnaBridge	189:f392fc9709a3	1295	/**
AnnaBridge	189:f392fc9709a3	1296	* @brief Configure the system clock source
AnnaBridge	189:f392fc9709a3	1297	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
AnnaBridge	189:f392fc9709a3	1298	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1299	* @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
AnnaBridge	189:f392fc9709a3	1300	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	1301	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
AnnaBridge	189:f392fc9709a3	1302	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	1303	* @retval None
AnnaBridge	189:f392fc9709a3	1304	*/
AnnaBridge	189:f392fc9709a3	1305	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
AnnaBridge	189:f392fc9709a3	1306	{
AnnaBridge	189:f392fc9709a3	1307	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
AnnaBridge	189:f392fc9709a3	1308	}
AnnaBridge	189:f392fc9709a3	1309
AnnaBridge	189:f392fc9709a3	1310	/**
AnnaBridge	189:f392fc9709a3	1311	* @brief Get the system clock source
AnnaBridge	189:f392fc9709a3	1312	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
AnnaBridge	189:f392fc9709a3	1313	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1314	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
AnnaBridge	189:f392fc9709a3	1315	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
AnnaBridge	189:f392fc9709a3	1316	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
AnnaBridge	189:f392fc9709a3	1317	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
AnnaBridge	189:f392fc9709a3	1318	*/
AnnaBridge	189:f392fc9709a3	1319	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
AnnaBridge	189:f392fc9709a3	1320	{
AnnaBridge	189:f392fc9709a3	1321	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
AnnaBridge	189:f392fc9709a3	1322	}
AnnaBridge	189:f392fc9709a3	1323
AnnaBridge	189:f392fc9709a3	1324	/**
AnnaBridge	189:f392fc9709a3	1325	* @brief Set AHB prescaler
AnnaBridge	189:f392fc9709a3	1326	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
AnnaBridge	189:f392fc9709a3	1327	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1328	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	189:f392fc9709a3	1329	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	189:f392fc9709a3	1330	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	189:f392fc9709a3	1331	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	189:f392fc9709a3	1332	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	189:f392fc9709a3	1333	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	189:f392fc9709a3	1334	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	189:f392fc9709a3	1335	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	189:f392fc9709a3	1336	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	189:f392fc9709a3	1337	* @retval None
AnnaBridge	189:f392fc9709a3	1338	*/
AnnaBridge	189:f392fc9709a3	1339	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
AnnaBridge	189:f392fc9709a3	1340	{
AnnaBridge	189:f392fc9709a3	1341	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
AnnaBridge	189:f392fc9709a3	1342	}
AnnaBridge	189:f392fc9709a3	1343
AnnaBridge	189:f392fc9709a3	1344	/**
AnnaBridge	189:f392fc9709a3	1345	* @brief Set APB1 prescaler
AnnaBridge	189:f392fc9709a3	1346	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
AnnaBridge	189:f392fc9709a3	1347	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1348	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	189:f392fc9709a3	1349	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	189:f392fc9709a3	1350	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	189:f392fc9709a3	1351	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	189:f392fc9709a3	1352	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	189:f392fc9709a3	1353	* @retval None
AnnaBridge	189:f392fc9709a3	1354	*/
AnnaBridge	189:f392fc9709a3	1355	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
AnnaBridge	189:f392fc9709a3	1356	{
AnnaBridge	189:f392fc9709a3	1357	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
AnnaBridge	189:f392fc9709a3	1358	}
AnnaBridge	189:f392fc9709a3	1359
AnnaBridge	189:f392fc9709a3	1360	/**
AnnaBridge	189:f392fc9709a3	1361	* @brief Set APB2 prescaler
AnnaBridge	189:f392fc9709a3	1362	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
AnnaBridge	189:f392fc9709a3	1363	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1364	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	189:f392fc9709a3	1365	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	189:f392fc9709a3	1366	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	189:f392fc9709a3	1367	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	189:f392fc9709a3	1368	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	189:f392fc9709a3	1369	* @retval None
AnnaBridge	189:f392fc9709a3	1370	*/
AnnaBridge	189:f392fc9709a3	1371	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
AnnaBridge	189:f392fc9709a3	1372	{
AnnaBridge	189:f392fc9709a3	1373	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
AnnaBridge	189:f392fc9709a3	1374	}
AnnaBridge	189:f392fc9709a3	1375
AnnaBridge	189:f392fc9709a3	1376	/**
AnnaBridge	189:f392fc9709a3	1377	* @brief Get AHB prescaler
AnnaBridge	189:f392fc9709a3	1378	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
AnnaBridge	189:f392fc9709a3	1379	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1380	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	189:f392fc9709a3	1381	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	189:f392fc9709a3	1382	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	189:f392fc9709a3	1383	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	189:f392fc9709a3	1384	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	189:f392fc9709a3	1385	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	189:f392fc9709a3	1386	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	189:f392fc9709a3	1387	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	189:f392fc9709a3	1388	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	189:f392fc9709a3	1389	*/
AnnaBridge	189:f392fc9709a3	1390	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
AnnaBridge	189:f392fc9709a3	1391	{
AnnaBridge	189:f392fc9709a3	1392	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
AnnaBridge	189:f392fc9709a3	1393	}
AnnaBridge	189:f392fc9709a3	1394
AnnaBridge	189:f392fc9709a3	1395	/**
AnnaBridge	189:f392fc9709a3	1396	* @brief Get APB1 prescaler
AnnaBridge	189:f392fc9709a3	1397	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
AnnaBridge	189:f392fc9709a3	1398	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1399	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	189:f392fc9709a3	1400	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	189:f392fc9709a3	1401	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	189:f392fc9709a3	1402	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	189:f392fc9709a3	1403	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	189:f392fc9709a3	1404	*/
AnnaBridge	189:f392fc9709a3	1405	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
AnnaBridge	189:f392fc9709a3	1406	{
AnnaBridge	189:f392fc9709a3	1407	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
AnnaBridge	189:f392fc9709a3	1408	}
AnnaBridge	189:f392fc9709a3	1409
AnnaBridge	189:f392fc9709a3	1410	/**
AnnaBridge	189:f392fc9709a3	1411	* @brief Get APB2 prescaler
AnnaBridge	189:f392fc9709a3	1412	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
AnnaBridge	189:f392fc9709a3	1413	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1414	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	189:f392fc9709a3	1415	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	189:f392fc9709a3	1416	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	189:f392fc9709a3	1417	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	189:f392fc9709a3	1418	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	189:f392fc9709a3	1419	*/
AnnaBridge	189:f392fc9709a3	1420	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
AnnaBridge	189:f392fc9709a3	1421	{
AnnaBridge	189:f392fc9709a3	1422	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
AnnaBridge	189:f392fc9709a3	1423	}
AnnaBridge	189:f392fc9709a3	1424
AnnaBridge	189:f392fc9709a3	1425	/**
AnnaBridge	189:f392fc9709a3	1426	* @brief Set Clock After Wake-Up From Stop mode
AnnaBridge	189:f392fc9709a3	1427	* @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
AnnaBridge	189:f392fc9709a3	1428	* @param Clock This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1429	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
AnnaBridge	189:f392fc9709a3	1430	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
AnnaBridge	189:f392fc9709a3	1431	* @retval None
AnnaBridge	189:f392fc9709a3	1432	*/
AnnaBridge	189:f392fc9709a3	1433	__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
AnnaBridge	189:f392fc9709a3	1434	{
AnnaBridge	189:f392fc9709a3	1435	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
AnnaBridge	189:f392fc9709a3	1436	}
AnnaBridge	189:f392fc9709a3	1437
AnnaBridge	189:f392fc9709a3	1438	/**
AnnaBridge	189:f392fc9709a3	1439	* @brief Get Clock After Wake-Up From Stop mode
AnnaBridge	189:f392fc9709a3	1440	* @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
AnnaBridge	189:f392fc9709a3	1441	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1442	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
AnnaBridge	189:f392fc9709a3	1443	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
AnnaBridge	189:f392fc9709a3	1444	*/
AnnaBridge	189:f392fc9709a3	1445	__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
AnnaBridge	189:f392fc9709a3	1446	{
AnnaBridge	189:f392fc9709a3	1447	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
AnnaBridge	189:f392fc9709a3	1448	}
AnnaBridge	189:f392fc9709a3	1449
AnnaBridge	189:f392fc9709a3	1450	/**
AnnaBridge	189:f392fc9709a3	1451	* @}
AnnaBridge	189:f392fc9709a3	1452	*/
AnnaBridge	189:f392fc9709a3	1453
AnnaBridge	189:f392fc9709a3	1454	/** @defgroup RCC_LL_EF_MCO MCO
AnnaBridge	189:f392fc9709a3	1455	* @{
AnnaBridge	189:f392fc9709a3	1456	*/
AnnaBridge	189:f392fc9709a3	1457
AnnaBridge	189:f392fc9709a3	1458	/**
AnnaBridge	189:f392fc9709a3	1459	* @brief Configure MCOx
AnnaBridge	189:f392fc9709a3	1460	* @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
AnnaBridge	189:f392fc9709a3	1461	* CFGR MCOPRE LL_RCC_ConfigMCO
AnnaBridge	189:f392fc9709a3	1462	* @param MCOxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1463	* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
AnnaBridge	189:f392fc9709a3	1464	* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	1465	* @arg @ref LL_RCC_MCO1SOURCE_HSI
AnnaBridge	189:f392fc9709a3	1466	* @arg @ref LL_RCC_MCO1SOURCE_MSI
AnnaBridge	189:f392fc9709a3	1467	* @arg @ref LL_RCC_MCO1SOURCE_HSE
AnnaBridge	189:f392fc9709a3	1468	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
AnnaBridge	189:f392fc9709a3	1469	* @arg @ref LL_RCC_MCO1SOURCE_LSI
AnnaBridge	189:f392fc9709a3	1470	* @arg @ref LL_RCC_MCO1SOURCE_LSE
AnnaBridge	189:f392fc9709a3	1471	* @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
AnnaBridge	189:f392fc9709a3	1472	*
AnnaBridge	189:f392fc9709a3	1473	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1474	* @param MCOxPrescaler This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1475	* @arg @ref LL_RCC_MCO1_DIV_1
AnnaBridge	189:f392fc9709a3	1476	* @arg @ref LL_RCC_MCO1_DIV_2
AnnaBridge	189:f392fc9709a3	1477	* @arg @ref LL_RCC_MCO1_DIV_4
AnnaBridge	189:f392fc9709a3	1478	* @arg @ref LL_RCC_MCO1_DIV_8
AnnaBridge	189:f392fc9709a3	1479	* @arg @ref LL_RCC_MCO1_DIV_16
AnnaBridge	189:f392fc9709a3	1480	* @retval None
AnnaBridge	189:f392fc9709a3	1481	*/
AnnaBridge	189:f392fc9709a3	1482	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
AnnaBridge	189:f392fc9709a3	1483	{
AnnaBridge	189:f392fc9709a3	1484	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE, MCOxSource \| MCOxPrescaler);
AnnaBridge	189:f392fc9709a3	1485	}
AnnaBridge	189:f392fc9709a3	1486
AnnaBridge	189:f392fc9709a3	1487	/**
AnnaBridge	189:f392fc9709a3	1488	* @}
AnnaBridge	189:f392fc9709a3	1489	*/
AnnaBridge	189:f392fc9709a3	1490
AnnaBridge	189:f392fc9709a3	1491	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
AnnaBridge	189:f392fc9709a3	1492	* @{
AnnaBridge	189:f392fc9709a3	1493	*/
AnnaBridge	189:f392fc9709a3	1494
AnnaBridge	189:f392fc9709a3	1495	/**
AnnaBridge	189:f392fc9709a3	1496	* @brief Configure USARTx clock source
AnnaBridge	189:f392fc9709a3	1497	* @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
AnnaBridge	189:f392fc9709a3	1498	* @param USARTxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1499	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
AnnaBridge	189:f392fc9709a3	1500	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*)
AnnaBridge	189:f392fc9709a3	1501	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*)
AnnaBridge	189:f392fc9709a3	1502	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*)
AnnaBridge	189:f392fc9709a3	1503	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	1504	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	1505	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	1506	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	1507	*
AnnaBridge	189:f392fc9709a3	1508	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1509	* @retval None
AnnaBridge	189:f392fc9709a3	1510	*/
AnnaBridge	189:f392fc9709a3	1511	__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
AnnaBridge	189:f392fc9709a3	1512	{
AnnaBridge	189:f392fc9709a3	1513	MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
AnnaBridge	189:f392fc9709a3	1514	}
AnnaBridge	189:f392fc9709a3	1515
AnnaBridge	189:f392fc9709a3	1516	/**
AnnaBridge	189:f392fc9709a3	1517	* @brief Configure LPUART1x clock source
AnnaBridge	189:f392fc9709a3	1518	* @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
AnnaBridge	189:f392fc9709a3	1519	* @param LPUARTxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1520	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	1521	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	1522	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	1523	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	1524	* @retval None
AnnaBridge	189:f392fc9709a3	1525	*/
AnnaBridge	189:f392fc9709a3	1526	__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
AnnaBridge	189:f392fc9709a3	1527	{
AnnaBridge	189:f392fc9709a3	1528	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
AnnaBridge	189:f392fc9709a3	1529	}
AnnaBridge	189:f392fc9709a3	1530
AnnaBridge	189:f392fc9709a3	1531	/**
AnnaBridge	189:f392fc9709a3	1532	* @brief Configure I2Cx clock source
AnnaBridge	189:f392fc9709a3	1533	* @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
AnnaBridge	189:f392fc9709a3	1534	* @param I2CxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1535	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	1536	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	1537	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	1538	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*)
AnnaBridge	189:f392fc9709a3	1539	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
AnnaBridge	189:f392fc9709a3	1540	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
AnnaBridge	189:f392fc9709a3	1541	*
AnnaBridge	189:f392fc9709a3	1542	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1543	* @retval None
AnnaBridge	189:f392fc9709a3	1544	*/
AnnaBridge	189:f392fc9709a3	1545	__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
AnnaBridge	189:f392fc9709a3	1546	{
AnnaBridge	189:f392fc9709a3	1547	MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4U) & 0x000FF000U), ((I2CxSource << 4U) & 0x000FF000U));
AnnaBridge	189:f392fc9709a3	1548	}
AnnaBridge	189:f392fc9709a3	1549
AnnaBridge	189:f392fc9709a3	1550	/**
AnnaBridge	189:f392fc9709a3	1551	* @brief Configure LPTIMx clock source
AnnaBridge	189:f392fc9709a3	1552	* @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
AnnaBridge	189:f392fc9709a3	1553	* @param LPTIMxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1554	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	1555	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	1556	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	1557	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	1558	* @retval None
AnnaBridge	189:f392fc9709a3	1559	*/
AnnaBridge	189:f392fc9709a3	1560	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
AnnaBridge	189:f392fc9709a3	1561	{
AnnaBridge	189:f392fc9709a3	1562	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource);
AnnaBridge	189:f392fc9709a3	1563	}
AnnaBridge	189:f392fc9709a3	1564
AnnaBridge	189:f392fc9709a3	1565	#if defined(RCC_CCIPR_HSI48SEL)
AnnaBridge	189:f392fc9709a3	1566	#if defined(RNG)
AnnaBridge	189:f392fc9709a3	1567	/**
AnnaBridge	189:f392fc9709a3	1568	* @brief Configure RNG clock source
AnnaBridge	189:f392fc9709a3	1569	* @rmtoll CCIPR HSI48SEL LL_RCC_SetRNGClockSource
AnnaBridge	189:f392fc9709a3	1570	* @param RNGxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1571	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	1572	* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
AnnaBridge	189:f392fc9709a3	1573	* @retval None
AnnaBridge	189:f392fc9709a3	1574	*/
AnnaBridge	189:f392fc9709a3	1575	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
AnnaBridge	189:f392fc9709a3	1576	{
AnnaBridge	189:f392fc9709a3	1577	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, RNGxSource);
AnnaBridge	189:f392fc9709a3	1578	}
AnnaBridge	189:f392fc9709a3	1579	#endif /* RNG */
AnnaBridge	189:f392fc9709a3	1580
AnnaBridge	189:f392fc9709a3	1581	#if defined(USB)
AnnaBridge	189:f392fc9709a3	1582	/**
AnnaBridge	189:f392fc9709a3	1583	* @brief Configure USB clock source
AnnaBridge	189:f392fc9709a3	1584	* @rmtoll CCIPR HSI48SEL LL_RCC_SetUSBClockSource
AnnaBridge	189:f392fc9709a3	1585	* @param USBxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1586	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	1587	* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
AnnaBridge	189:f392fc9709a3	1588	* @retval None
AnnaBridge	189:f392fc9709a3	1589	*/
AnnaBridge	189:f392fc9709a3	1590	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
AnnaBridge	189:f392fc9709a3	1591	{
AnnaBridge	189:f392fc9709a3	1592	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, USBxSource);
AnnaBridge	189:f392fc9709a3	1593	}
AnnaBridge	189:f392fc9709a3	1594	#endif /* USB */
AnnaBridge	189:f392fc9709a3	1595
AnnaBridge	189:f392fc9709a3	1596	#endif /* RCC_CCIPR_HSI48SEL */
AnnaBridge	189:f392fc9709a3	1597
AnnaBridge	189:f392fc9709a3	1598	/**
AnnaBridge	189:f392fc9709a3	1599	* @brief Get USARTx clock source
AnnaBridge	189:f392fc9709a3	1600	* @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
AnnaBridge	189:f392fc9709a3	1601	* @param USARTx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1602	* @arg @ref LL_RCC_USART1_CLKSOURCE (*)
AnnaBridge	189:f392fc9709a3	1603	* @arg @ref LL_RCC_USART2_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1604	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1605	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
AnnaBridge	189:f392fc9709a3	1606	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*)
AnnaBridge	189:f392fc9709a3	1607	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*)
AnnaBridge	189:f392fc9709a3	1608	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*)
AnnaBridge	189:f392fc9709a3	1609	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	1610	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	1611	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	1612	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	1613	*
AnnaBridge	189:f392fc9709a3	1614	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1615	*/
AnnaBridge	189:f392fc9709a3	1616	__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
AnnaBridge	189:f392fc9709a3	1617	{
AnnaBridge	189:f392fc9709a3	1618	return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) \| (USARTx << 16U));
AnnaBridge	189:f392fc9709a3	1619	}
AnnaBridge	189:f392fc9709a3	1620
AnnaBridge	189:f392fc9709a3	1621
AnnaBridge	189:f392fc9709a3	1622
AnnaBridge	189:f392fc9709a3	1623	/**
AnnaBridge	189:f392fc9709a3	1624	* @brief Get LPUARTx clock source
AnnaBridge	189:f392fc9709a3	1625	* @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
AnnaBridge	189:f392fc9709a3	1626	* @param LPUARTx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1627	* @arg @ref LL_RCC_LPUART1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1628	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1629	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	1630	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	1631	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	1632	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	1633	*/
AnnaBridge	189:f392fc9709a3	1634	__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
AnnaBridge	189:f392fc9709a3	1635	{
AnnaBridge	189:f392fc9709a3	1636	return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
AnnaBridge	189:f392fc9709a3	1637	}
AnnaBridge	189:f392fc9709a3	1638
AnnaBridge	189:f392fc9709a3	1639	/**
AnnaBridge	189:f392fc9709a3	1640	* @brief Get I2Cx clock source
AnnaBridge	189:f392fc9709a3	1641	* @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
AnnaBridge	189:f392fc9709a3	1642	* @param I2Cx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1643	* @arg @ref LL_RCC_I2C1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1644	* @arg @ref LL_RCC_I2C3_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1645	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1646	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	1647	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
AnnaBridge	189:f392fc9709a3	1648	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	1649	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*)
AnnaBridge	189:f392fc9709a3	1650	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
AnnaBridge	189:f392fc9709a3	1651	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
AnnaBridge	189:f392fc9709a3	1652	*
AnnaBridge	189:f392fc9709a3	1653	* (*) value not defined in all devices.
AnnaBridge	189:f392fc9709a3	1654	*/
AnnaBridge	189:f392fc9709a3	1655	__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
AnnaBridge	189:f392fc9709a3	1656	{
AnnaBridge	189:f392fc9709a3	1657	return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4U) \| (I2Cx << 4U));
AnnaBridge	189:f392fc9709a3	1658	}
AnnaBridge	189:f392fc9709a3	1659
AnnaBridge	189:f392fc9709a3	1660	/**
AnnaBridge	189:f392fc9709a3	1661	* @brief Get LPTIMx clock source
AnnaBridge	189:f392fc9709a3	1662	* @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
AnnaBridge	189:f392fc9709a3	1663	* @param LPTIMx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1664	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1665	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1666	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	189:f392fc9709a3	1667	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	1668	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	1669	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	1670	*/
AnnaBridge	189:f392fc9709a3	1671	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
AnnaBridge	189:f392fc9709a3	1672	{
AnnaBridge	189:f392fc9709a3	1673	return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx));
AnnaBridge	189:f392fc9709a3	1674	}
AnnaBridge	189:f392fc9709a3	1675
AnnaBridge	189:f392fc9709a3	1676	#if defined(RCC_CCIPR_HSI48SEL)
AnnaBridge	189:f392fc9709a3	1677	#if defined(RNG)
AnnaBridge	189:f392fc9709a3	1678	/**
AnnaBridge	189:f392fc9709a3	1679	* @brief Get RNGx clock source
AnnaBridge	189:f392fc9709a3	1680	* @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
AnnaBridge	189:f392fc9709a3	1681	* @param RNGx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1682	* @arg @ref LL_RCC_RNG_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1683	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1684	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	1685	* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
AnnaBridge	189:f392fc9709a3	1686	*/
AnnaBridge	189:f392fc9709a3	1687	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
AnnaBridge	189:f392fc9709a3	1688	{
AnnaBridge	189:f392fc9709a3	1689	return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
AnnaBridge	189:f392fc9709a3	1690	}
AnnaBridge	189:f392fc9709a3	1691	#endif /* RNG */
AnnaBridge	189:f392fc9709a3	1692
AnnaBridge	189:f392fc9709a3	1693	#if defined(USB)
AnnaBridge	189:f392fc9709a3	1694	/**
AnnaBridge	189:f392fc9709a3	1695	* @brief Get USBx clock source
AnnaBridge	189:f392fc9709a3	1696	* @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
AnnaBridge	189:f392fc9709a3	1697	* @param USBx This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1698	* @arg @ref LL_RCC_USB_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1699	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1700	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	1701	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
AnnaBridge	189:f392fc9709a3	1702	*/
AnnaBridge	189:f392fc9709a3	1703	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
AnnaBridge	189:f392fc9709a3	1704	{
AnnaBridge	189:f392fc9709a3	1705	return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
AnnaBridge	189:f392fc9709a3	1706	}
AnnaBridge	189:f392fc9709a3	1707	#endif /* USB */
AnnaBridge	189:f392fc9709a3	1708
AnnaBridge	189:f392fc9709a3	1709	#endif /* RCC_CCIPR_HSI48SEL */
AnnaBridge	189:f392fc9709a3	1710
AnnaBridge	189:f392fc9709a3	1711	/**
AnnaBridge	189:f392fc9709a3	1712	* @}
AnnaBridge	189:f392fc9709a3	1713	*/
AnnaBridge	189:f392fc9709a3	1714
AnnaBridge	189:f392fc9709a3	1715	/** @defgroup RCC_LL_EF_RTC RTC
AnnaBridge	189:f392fc9709a3	1716	* @{
AnnaBridge	189:f392fc9709a3	1717	*/
AnnaBridge	189:f392fc9709a3	1718
AnnaBridge	189:f392fc9709a3	1719	/**
AnnaBridge	189:f392fc9709a3	1720	* @brief Set RTC Clock Source
AnnaBridge	189:f392fc9709a3	1721	* @note Once the RTC clock source has been selected, it cannot be changed any more unless
AnnaBridge	189:f392fc9709a3	1722	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
AnnaBridge	189:f392fc9709a3	1723	* set). The RTCRST bit can be used to reset them.
AnnaBridge	189:f392fc9709a3	1724	* @rmtoll CSR RTCSEL LL_RCC_SetRTCClockSource
AnnaBridge	189:f392fc9709a3	1725	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1726	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	189:f392fc9709a3	1727	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	1728	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	1729	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	189:f392fc9709a3	1730	* @retval None
AnnaBridge	189:f392fc9709a3	1731	*/
AnnaBridge	189:f392fc9709a3	1732	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
AnnaBridge	189:f392fc9709a3	1733	{
AnnaBridge	189:f392fc9709a3	1734	MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source);
AnnaBridge	189:f392fc9709a3	1735	}
AnnaBridge	189:f392fc9709a3	1736
AnnaBridge	189:f392fc9709a3	1737	/**
AnnaBridge	189:f392fc9709a3	1738	* @brief Get RTC Clock Source
AnnaBridge	189:f392fc9709a3	1739	* @rmtoll CSR RTCSEL LL_RCC_GetRTCClockSource
AnnaBridge	189:f392fc9709a3	1740	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1741	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	189:f392fc9709a3	1742	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	1743	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	1744	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	189:f392fc9709a3	1745	*/
AnnaBridge	189:f392fc9709a3	1746	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
AnnaBridge	189:f392fc9709a3	1747	{
AnnaBridge	189:f392fc9709a3	1748	return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL));
AnnaBridge	189:f392fc9709a3	1749	}
AnnaBridge	189:f392fc9709a3	1750
AnnaBridge	189:f392fc9709a3	1751	/**
AnnaBridge	189:f392fc9709a3	1752	* @brief Enable RTC
AnnaBridge	189:f392fc9709a3	1753	* @rmtoll CSR RTCEN LL_RCC_EnableRTC
AnnaBridge	189:f392fc9709a3	1754	* @retval None
AnnaBridge	189:f392fc9709a3	1755	*/
AnnaBridge	189:f392fc9709a3	1756	__STATIC_INLINE void LL_RCC_EnableRTC(void)
AnnaBridge	189:f392fc9709a3	1757	{
AnnaBridge	189:f392fc9709a3	1758	SET_BIT(RCC->CSR, RCC_CSR_RTCEN);
AnnaBridge	189:f392fc9709a3	1759	}
AnnaBridge	189:f392fc9709a3	1760
AnnaBridge	189:f392fc9709a3	1761	/**
AnnaBridge	189:f392fc9709a3	1762	* @brief Disable RTC
AnnaBridge	189:f392fc9709a3	1763	* @rmtoll CSR RTCEN LL_RCC_DisableRTC
AnnaBridge	189:f392fc9709a3	1764	* @retval None
AnnaBridge	189:f392fc9709a3	1765	*/
AnnaBridge	189:f392fc9709a3	1766	__STATIC_INLINE void LL_RCC_DisableRTC(void)
AnnaBridge	189:f392fc9709a3	1767	{
AnnaBridge	189:f392fc9709a3	1768	CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN);
AnnaBridge	189:f392fc9709a3	1769	}
AnnaBridge	189:f392fc9709a3	1770
AnnaBridge	189:f392fc9709a3	1771	/**
AnnaBridge	189:f392fc9709a3	1772	* @brief Check if RTC has been enabled or not
AnnaBridge	189:f392fc9709a3	1773	* @rmtoll CSR RTCEN LL_RCC_IsEnabledRTC
AnnaBridge	189:f392fc9709a3	1774	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1775	*/
AnnaBridge	189:f392fc9709a3	1776	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
AnnaBridge	189:f392fc9709a3	1777	{
AnnaBridge	189:f392fc9709a3	1778	return (READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == (RCC_CSR_RTCEN));
AnnaBridge	189:f392fc9709a3	1779	}
AnnaBridge	189:f392fc9709a3	1780
AnnaBridge	189:f392fc9709a3	1781	/**
AnnaBridge	189:f392fc9709a3	1782	* @brief Force the Backup domain reset
AnnaBridge	189:f392fc9709a3	1783	* @rmtoll CSR RTCRST LL_RCC_ForceBackupDomainReset
AnnaBridge	189:f392fc9709a3	1784	* @retval None
AnnaBridge	189:f392fc9709a3	1785	*/
AnnaBridge	189:f392fc9709a3	1786	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
AnnaBridge	189:f392fc9709a3	1787	{
AnnaBridge	189:f392fc9709a3	1788	SET_BIT(RCC->CSR, RCC_CSR_RTCRST);
AnnaBridge	189:f392fc9709a3	1789	}
AnnaBridge	189:f392fc9709a3	1790
AnnaBridge	189:f392fc9709a3	1791	/**
AnnaBridge	189:f392fc9709a3	1792	* @brief Release the Backup domain reset
AnnaBridge	189:f392fc9709a3	1793	* @rmtoll CSR RTCRST LL_RCC_ReleaseBackupDomainReset
AnnaBridge	189:f392fc9709a3	1794	* @retval None
AnnaBridge	189:f392fc9709a3	1795	*/
AnnaBridge	189:f392fc9709a3	1796	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
AnnaBridge	189:f392fc9709a3	1797	{
AnnaBridge	189:f392fc9709a3	1798	CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST);
AnnaBridge	189:f392fc9709a3	1799	}
AnnaBridge	189:f392fc9709a3	1800
AnnaBridge	189:f392fc9709a3	1801	/**
AnnaBridge	189:f392fc9709a3	1802	* @}
AnnaBridge	189:f392fc9709a3	1803	*/
AnnaBridge	189:f392fc9709a3	1804
AnnaBridge	189:f392fc9709a3	1805	/** @defgroup RCC_LL_EF_PLL PLL
AnnaBridge	189:f392fc9709a3	1806	* @{
AnnaBridge	189:f392fc9709a3	1807	*/
AnnaBridge	189:f392fc9709a3	1808
AnnaBridge	189:f392fc9709a3	1809	/**
AnnaBridge	189:f392fc9709a3	1810	* @brief Enable PLL
AnnaBridge	189:f392fc9709a3	1811	* @rmtoll CR PLLON LL_RCC_PLL_Enable
AnnaBridge	189:f392fc9709a3	1812	* @retval None
AnnaBridge	189:f392fc9709a3	1813	*/
AnnaBridge	189:f392fc9709a3	1814	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
AnnaBridge	189:f392fc9709a3	1815	{
AnnaBridge	189:f392fc9709a3	1816	SET_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	189:f392fc9709a3	1817	}
AnnaBridge	189:f392fc9709a3	1818
AnnaBridge	189:f392fc9709a3	1819	/**
AnnaBridge	189:f392fc9709a3	1820	* @brief Disable PLL
AnnaBridge	189:f392fc9709a3	1821	* @note Cannot be disabled if the PLL clock is used as the system clock
AnnaBridge	189:f392fc9709a3	1822	* @rmtoll CR PLLON LL_RCC_PLL_Disable
AnnaBridge	189:f392fc9709a3	1823	* @retval None
AnnaBridge	189:f392fc9709a3	1824	*/
AnnaBridge	189:f392fc9709a3	1825	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
AnnaBridge	189:f392fc9709a3	1826	{
AnnaBridge	189:f392fc9709a3	1827	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	189:f392fc9709a3	1828	}
AnnaBridge	189:f392fc9709a3	1829
AnnaBridge	189:f392fc9709a3	1830	/**
AnnaBridge	189:f392fc9709a3	1831	* @brief Check if PLL Ready
AnnaBridge	189:f392fc9709a3	1832	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
AnnaBridge	189:f392fc9709a3	1833	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1834	*/
AnnaBridge	189:f392fc9709a3	1835	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
AnnaBridge	189:f392fc9709a3	1836	{
AnnaBridge	189:f392fc9709a3	1837	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
AnnaBridge	189:f392fc9709a3	1838	}
AnnaBridge	189:f392fc9709a3	1839
AnnaBridge	189:f392fc9709a3	1840	/**
AnnaBridge	189:f392fc9709a3	1841	* @brief Configure PLL used for SYSCLK Domain
AnnaBridge	189:f392fc9709a3	1842	* @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	189:f392fc9709a3	1843	* CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	189:f392fc9709a3	1844	* CFGR PLLDIV LL_RCC_PLL_ConfigDomain_SYS
AnnaBridge	189:f392fc9709a3	1845	* @param Source This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1846	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	1847	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	1848	* @param PLLMul This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1849	* @arg @ref LL_RCC_PLL_MUL_3
AnnaBridge	189:f392fc9709a3	1850	* @arg @ref LL_RCC_PLL_MUL_4
AnnaBridge	189:f392fc9709a3	1851	* @arg @ref LL_RCC_PLL_MUL_6
AnnaBridge	189:f392fc9709a3	1852	* @arg @ref LL_RCC_PLL_MUL_8
AnnaBridge	189:f392fc9709a3	1853	* @arg @ref LL_RCC_PLL_MUL_12
AnnaBridge	189:f392fc9709a3	1854	* @arg @ref LL_RCC_PLL_MUL_16
AnnaBridge	189:f392fc9709a3	1855	* @arg @ref LL_RCC_PLL_MUL_24
AnnaBridge	189:f392fc9709a3	1856	* @arg @ref LL_RCC_PLL_MUL_32
AnnaBridge	189:f392fc9709a3	1857	* @arg @ref LL_RCC_PLL_MUL_48
AnnaBridge	189:f392fc9709a3	1858	* @param PLLDiv This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1859	* @arg @ref LL_RCC_PLL_DIV_2
AnnaBridge	189:f392fc9709a3	1860	* @arg @ref LL_RCC_PLL_DIV_3
AnnaBridge	189:f392fc9709a3	1861	* @arg @ref LL_RCC_PLL_DIV_4
AnnaBridge	189:f392fc9709a3	1862	* @retval None
AnnaBridge	189:f392fc9709a3	1863	*/
AnnaBridge	189:f392fc9709a3	1864	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
AnnaBridge	189:f392fc9709a3	1865	{
AnnaBridge	189:f392fc9709a3	1866	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMUL \| RCC_CFGR_PLLDIV, Source \| PLLMul \| PLLDiv);
AnnaBridge	189:f392fc9709a3	1867	}
AnnaBridge	189:f392fc9709a3	1868
AnnaBridge	189:f392fc9709a3	1869	/**
AnnaBridge	189:f392fc9709a3	1870	* @brief Get the oscillator used as PLL clock source.
AnnaBridge	189:f392fc9709a3	1871	* @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
AnnaBridge	189:f392fc9709a3	1872	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1873	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	189:f392fc9709a3	1874	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	189:f392fc9709a3	1875	*/
AnnaBridge	189:f392fc9709a3	1876	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
AnnaBridge	189:f392fc9709a3	1877	{
AnnaBridge	189:f392fc9709a3	1878	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
AnnaBridge	189:f392fc9709a3	1879	}
AnnaBridge	189:f392fc9709a3	1880
AnnaBridge	189:f392fc9709a3	1881	/**
AnnaBridge	189:f392fc9709a3	1882	* @brief Get PLL multiplication Factor
AnnaBridge	189:f392fc9709a3	1883	* @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
AnnaBridge	189:f392fc9709a3	1884	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1885	* @arg @ref LL_RCC_PLL_MUL_3
AnnaBridge	189:f392fc9709a3	1886	* @arg @ref LL_RCC_PLL_MUL_4
AnnaBridge	189:f392fc9709a3	1887	* @arg @ref LL_RCC_PLL_MUL_6
AnnaBridge	189:f392fc9709a3	1888	* @arg @ref LL_RCC_PLL_MUL_8
AnnaBridge	189:f392fc9709a3	1889	* @arg @ref LL_RCC_PLL_MUL_12
AnnaBridge	189:f392fc9709a3	1890	* @arg @ref LL_RCC_PLL_MUL_16
AnnaBridge	189:f392fc9709a3	1891	* @arg @ref LL_RCC_PLL_MUL_24
AnnaBridge	189:f392fc9709a3	1892	* @arg @ref LL_RCC_PLL_MUL_32
AnnaBridge	189:f392fc9709a3	1893	* @arg @ref LL_RCC_PLL_MUL_48
AnnaBridge	189:f392fc9709a3	1894	*/
AnnaBridge	189:f392fc9709a3	1895	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
AnnaBridge	189:f392fc9709a3	1896	{
AnnaBridge	189:f392fc9709a3	1897	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
AnnaBridge	189:f392fc9709a3	1898	}
AnnaBridge	189:f392fc9709a3	1899
AnnaBridge	189:f392fc9709a3	1900	/**
AnnaBridge	189:f392fc9709a3	1901	* @brief Get Division factor for the main PLL and other PLL
AnnaBridge	189:f392fc9709a3	1902	* @rmtoll CFGR PLLDIV LL_RCC_PLL_GetDivider
AnnaBridge	189:f392fc9709a3	1903	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1904	* @arg @ref LL_RCC_PLL_DIV_2
AnnaBridge	189:f392fc9709a3	1905	* @arg @ref LL_RCC_PLL_DIV_3
AnnaBridge	189:f392fc9709a3	1906	* @arg @ref LL_RCC_PLL_DIV_4
AnnaBridge	189:f392fc9709a3	1907	*/
AnnaBridge	189:f392fc9709a3	1908	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
AnnaBridge	189:f392fc9709a3	1909	{
AnnaBridge	189:f392fc9709a3	1910	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV));
AnnaBridge	189:f392fc9709a3	1911	}
AnnaBridge	189:f392fc9709a3	1912
AnnaBridge	189:f392fc9709a3	1913	/**
AnnaBridge	189:f392fc9709a3	1914	* @}
AnnaBridge	189:f392fc9709a3	1915	*/
AnnaBridge	189:f392fc9709a3	1916
AnnaBridge	189:f392fc9709a3	1917	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	189:f392fc9709a3	1918	* @{
AnnaBridge	189:f392fc9709a3	1919	*/
AnnaBridge	189:f392fc9709a3	1920
AnnaBridge	189:f392fc9709a3	1921	/**
AnnaBridge	189:f392fc9709a3	1922	* @brief Clear LSI ready interrupt flag
AnnaBridge	189:f392fc9709a3	1923	* @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
AnnaBridge	189:f392fc9709a3	1924	* @retval None
AnnaBridge	189:f392fc9709a3	1925	*/
AnnaBridge	189:f392fc9709a3	1926	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
AnnaBridge	189:f392fc9709a3	1927	{
AnnaBridge	189:f392fc9709a3	1928	SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
AnnaBridge	189:f392fc9709a3	1929	}
AnnaBridge	189:f392fc9709a3	1930
AnnaBridge	189:f392fc9709a3	1931	/**
AnnaBridge	189:f392fc9709a3	1932	* @brief Clear LSE ready interrupt flag
AnnaBridge	189:f392fc9709a3	1933	* @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
AnnaBridge	189:f392fc9709a3	1934	* @retval None
AnnaBridge	189:f392fc9709a3	1935	*/
AnnaBridge	189:f392fc9709a3	1936	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
AnnaBridge	189:f392fc9709a3	1937	{
AnnaBridge	189:f392fc9709a3	1938	SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
AnnaBridge	189:f392fc9709a3	1939	}
AnnaBridge	189:f392fc9709a3	1940
AnnaBridge	189:f392fc9709a3	1941	/**
AnnaBridge	189:f392fc9709a3	1942	* @brief Clear MSI ready interrupt flag
AnnaBridge	189:f392fc9709a3	1943	* @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
AnnaBridge	189:f392fc9709a3	1944	* @retval None
AnnaBridge	189:f392fc9709a3	1945	*/
AnnaBridge	189:f392fc9709a3	1946	__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
AnnaBridge	189:f392fc9709a3	1947	{
AnnaBridge	189:f392fc9709a3	1948	SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
AnnaBridge	189:f392fc9709a3	1949	}
AnnaBridge	189:f392fc9709a3	1950
AnnaBridge	189:f392fc9709a3	1951	/**
AnnaBridge	189:f392fc9709a3	1952	* @brief Clear HSI ready interrupt flag
AnnaBridge	189:f392fc9709a3	1953	* @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
AnnaBridge	189:f392fc9709a3	1954	* @retval None
AnnaBridge	189:f392fc9709a3	1955	*/
AnnaBridge	189:f392fc9709a3	1956	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
AnnaBridge	189:f392fc9709a3	1957	{
AnnaBridge	189:f392fc9709a3	1958	SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
AnnaBridge	189:f392fc9709a3	1959	}
AnnaBridge	189:f392fc9709a3	1960
AnnaBridge	189:f392fc9709a3	1961	/**
AnnaBridge	189:f392fc9709a3	1962	* @brief Clear HSE ready interrupt flag
AnnaBridge	189:f392fc9709a3	1963	* @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
AnnaBridge	189:f392fc9709a3	1964	* @retval None
AnnaBridge	189:f392fc9709a3	1965	*/
AnnaBridge	189:f392fc9709a3	1966	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
AnnaBridge	189:f392fc9709a3	1967	{
AnnaBridge	189:f392fc9709a3	1968	SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
AnnaBridge	189:f392fc9709a3	1969	}
AnnaBridge	189:f392fc9709a3	1970
AnnaBridge	189:f392fc9709a3	1971	/**
AnnaBridge	189:f392fc9709a3	1972	* @brief Clear PLL ready interrupt flag
AnnaBridge	189:f392fc9709a3	1973	* @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
AnnaBridge	189:f392fc9709a3	1974	* @retval None
AnnaBridge	189:f392fc9709a3	1975	*/
AnnaBridge	189:f392fc9709a3	1976	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
AnnaBridge	189:f392fc9709a3	1977	{
AnnaBridge	189:f392fc9709a3	1978	SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
AnnaBridge	189:f392fc9709a3	1979	}
AnnaBridge	189:f392fc9709a3	1980
AnnaBridge	189:f392fc9709a3	1981	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	1982	/**
AnnaBridge	189:f392fc9709a3	1983	* @brief Clear HSI48 ready interrupt flag
AnnaBridge	189:f392fc9709a3	1984	* @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
AnnaBridge	189:f392fc9709a3	1985	* @retval None
AnnaBridge	189:f392fc9709a3	1986	*/
AnnaBridge	189:f392fc9709a3	1987	__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
AnnaBridge	189:f392fc9709a3	1988	{
AnnaBridge	189:f392fc9709a3	1989	SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
AnnaBridge	189:f392fc9709a3	1990	}
AnnaBridge	189:f392fc9709a3	1991	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	1992
AnnaBridge	189:f392fc9709a3	1993	#if defined(RCC_HSECSS_SUPPORT)
AnnaBridge	189:f392fc9709a3	1994	/**
AnnaBridge	189:f392fc9709a3	1995	* @brief Clear Clock security system interrupt flag
AnnaBridge	189:f392fc9709a3	1996	* @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
AnnaBridge	189:f392fc9709a3	1997	* @retval None
AnnaBridge	189:f392fc9709a3	1998	*/
AnnaBridge	189:f392fc9709a3	1999	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
AnnaBridge	189:f392fc9709a3	2000	{
AnnaBridge	189:f392fc9709a3	2001	SET_BIT(RCC->CICR, RCC_CICR_CSSC);
AnnaBridge	189:f392fc9709a3	2002	}
AnnaBridge	189:f392fc9709a3	2003	#endif /* RCC_HSECSS_SUPPORT */
AnnaBridge	189:f392fc9709a3	2004
AnnaBridge	189:f392fc9709a3	2005	/**
AnnaBridge	189:f392fc9709a3	2006	* @brief Clear LSE Clock security system interrupt flag
AnnaBridge	189:f392fc9709a3	2007	* @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
AnnaBridge	189:f392fc9709a3	2008	* @retval None
AnnaBridge	189:f392fc9709a3	2009	*/
AnnaBridge	189:f392fc9709a3	2010	__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
AnnaBridge	189:f392fc9709a3	2011	{
AnnaBridge	189:f392fc9709a3	2012	SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
AnnaBridge	189:f392fc9709a3	2013	}
AnnaBridge	189:f392fc9709a3	2014
AnnaBridge	189:f392fc9709a3	2015	/**
AnnaBridge	189:f392fc9709a3	2016	* @brief Check if LSI ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	2017	* @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
AnnaBridge	189:f392fc9709a3	2018	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2019	*/
AnnaBridge	189:f392fc9709a3	2020	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
AnnaBridge	189:f392fc9709a3	2021	{
AnnaBridge	189:f392fc9709a3	2022	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF));
AnnaBridge	189:f392fc9709a3	2023	}
AnnaBridge	189:f392fc9709a3	2024
AnnaBridge	189:f392fc9709a3	2025	/**
AnnaBridge	189:f392fc9709a3	2026	* @brief Check if LSE ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	2027	* @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
AnnaBridge	189:f392fc9709a3	2028	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2029	*/
AnnaBridge	189:f392fc9709a3	2030	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
AnnaBridge	189:f392fc9709a3	2031	{
AnnaBridge	189:f392fc9709a3	2032	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF));
AnnaBridge	189:f392fc9709a3	2033	}
AnnaBridge	189:f392fc9709a3	2034
AnnaBridge	189:f392fc9709a3	2035	/**
AnnaBridge	189:f392fc9709a3	2036	* @brief Check if MSI ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	2037	* @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
AnnaBridge	189:f392fc9709a3	2038	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2039	*/
AnnaBridge	189:f392fc9709a3	2040	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
AnnaBridge	189:f392fc9709a3	2041	{
AnnaBridge	189:f392fc9709a3	2042	return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF));
AnnaBridge	189:f392fc9709a3	2043	}
AnnaBridge	189:f392fc9709a3	2044
AnnaBridge	189:f392fc9709a3	2045	/**
AnnaBridge	189:f392fc9709a3	2046	* @brief Check if HSI ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	2047	* @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
AnnaBridge	189:f392fc9709a3	2048	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2049	*/
AnnaBridge	189:f392fc9709a3	2050	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
AnnaBridge	189:f392fc9709a3	2051	{
AnnaBridge	189:f392fc9709a3	2052	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF));
AnnaBridge	189:f392fc9709a3	2053	}
AnnaBridge	189:f392fc9709a3	2054
AnnaBridge	189:f392fc9709a3	2055	/**
AnnaBridge	189:f392fc9709a3	2056	* @brief Check if HSE ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	2057	* @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
AnnaBridge	189:f392fc9709a3	2058	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2059	*/
AnnaBridge	189:f392fc9709a3	2060	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
AnnaBridge	189:f392fc9709a3	2061	{
AnnaBridge	189:f392fc9709a3	2062	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF));
AnnaBridge	189:f392fc9709a3	2063	}
AnnaBridge	189:f392fc9709a3	2064
AnnaBridge	189:f392fc9709a3	2065	/**
AnnaBridge	189:f392fc9709a3	2066	* @brief Check if PLL ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	2067	* @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
AnnaBridge	189:f392fc9709a3	2068	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2069	*/
AnnaBridge	189:f392fc9709a3	2070	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
AnnaBridge	189:f392fc9709a3	2071	{
AnnaBridge	189:f392fc9709a3	2072	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF));
AnnaBridge	189:f392fc9709a3	2073	}
AnnaBridge	189:f392fc9709a3	2074
AnnaBridge	189:f392fc9709a3	2075	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	2076	/**
AnnaBridge	189:f392fc9709a3	2077	* @brief Check if HSI48 ready interrupt occurred or not
AnnaBridge	189:f392fc9709a3	2078	* @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
AnnaBridge	189:f392fc9709a3	2079	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2080	*/
AnnaBridge	189:f392fc9709a3	2081	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
AnnaBridge	189:f392fc9709a3	2082	{
AnnaBridge	189:f392fc9709a3	2083	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF));
AnnaBridge	189:f392fc9709a3	2084	}
AnnaBridge	189:f392fc9709a3	2085	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	2086
AnnaBridge	189:f392fc9709a3	2087	#if defined(RCC_HSECSS_SUPPORT)
AnnaBridge	189:f392fc9709a3	2088	/**
AnnaBridge	189:f392fc9709a3	2089	* @brief Check if Clock security system interrupt occurred or not
AnnaBridge	189:f392fc9709a3	2090	* @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
AnnaBridge	189:f392fc9709a3	2091	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2092	*/
AnnaBridge	189:f392fc9709a3	2093	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
AnnaBridge	189:f392fc9709a3	2094	{
AnnaBridge	189:f392fc9709a3	2095	return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF));
AnnaBridge	189:f392fc9709a3	2096	}
AnnaBridge	189:f392fc9709a3	2097	#endif /* RCC_HSECSS_SUPPORT */
AnnaBridge	189:f392fc9709a3	2098
AnnaBridge	189:f392fc9709a3	2099	/**
AnnaBridge	189:f392fc9709a3	2100	* @brief Check if LSE Clock security system interrupt occurred or not
AnnaBridge	189:f392fc9709a3	2101	* @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
AnnaBridge	189:f392fc9709a3	2102	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2103	*/
AnnaBridge	189:f392fc9709a3	2104	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
AnnaBridge	189:f392fc9709a3	2105	{
AnnaBridge	189:f392fc9709a3	2106	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF));
AnnaBridge	189:f392fc9709a3	2107	}
AnnaBridge	189:f392fc9709a3	2108
AnnaBridge	189:f392fc9709a3	2109	/**
AnnaBridge	189:f392fc9709a3	2110	* @brief Check if HSI Divider is enabled (it divides by 4)
AnnaBridge	189:f392fc9709a3	2111	* @rmtoll CR HSIDIVF LL_RCC_IsActiveFlag_HSIDIV
AnnaBridge	189:f392fc9709a3	2112	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2113	*/
AnnaBridge	189:f392fc9709a3	2114	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIDIV(void)
AnnaBridge	189:f392fc9709a3	2115	{
AnnaBridge	189:f392fc9709a3	2116	return (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF));
AnnaBridge	189:f392fc9709a3	2117	}
AnnaBridge	189:f392fc9709a3	2118
AnnaBridge	189:f392fc9709a3	2119	#if defined(RCC_CSR_FWRSTF)
AnnaBridge	189:f392fc9709a3	2120	/**
AnnaBridge	189:f392fc9709a3	2121	* @brief Check if RCC flag FW reset is set or not.
AnnaBridge	189:f392fc9709a3	2122	* @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST
AnnaBridge	189:f392fc9709a3	2123	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2124	*/
AnnaBridge	189:f392fc9709a3	2125	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
AnnaBridge	189:f392fc9709a3	2126	{
AnnaBridge	189:f392fc9709a3	2127	return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF));
AnnaBridge	189:f392fc9709a3	2128	}
AnnaBridge	189:f392fc9709a3	2129	#endif /* RCC_CSR_FWRSTF */
AnnaBridge	189:f392fc9709a3	2130
AnnaBridge	189:f392fc9709a3	2131	/**
AnnaBridge	189:f392fc9709a3	2132	* @brief Check if RCC flag Independent Watchdog reset is set or not.
AnnaBridge	189:f392fc9709a3	2133	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
AnnaBridge	189:f392fc9709a3	2134	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2135	*/
AnnaBridge	189:f392fc9709a3	2136	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
AnnaBridge	189:f392fc9709a3	2137	{
AnnaBridge	189:f392fc9709a3	2138	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
AnnaBridge	189:f392fc9709a3	2139	}
AnnaBridge	189:f392fc9709a3	2140
AnnaBridge	189:f392fc9709a3	2141	/**
AnnaBridge	189:f392fc9709a3	2142	* @brief Check if RCC flag Low Power reset is set or not.
AnnaBridge	189:f392fc9709a3	2143	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
AnnaBridge	189:f392fc9709a3	2144	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2145	*/
AnnaBridge	189:f392fc9709a3	2146	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
AnnaBridge	189:f392fc9709a3	2147	{
AnnaBridge	189:f392fc9709a3	2148	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
AnnaBridge	189:f392fc9709a3	2149	}
AnnaBridge	189:f392fc9709a3	2150
AnnaBridge	189:f392fc9709a3	2151	/**
AnnaBridge	189:f392fc9709a3	2152	* @brief Check if RCC flag is set or not.
AnnaBridge	189:f392fc9709a3	2153	* @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
AnnaBridge	189:f392fc9709a3	2154	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2155	*/
AnnaBridge	189:f392fc9709a3	2156	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
AnnaBridge	189:f392fc9709a3	2157	{
AnnaBridge	189:f392fc9709a3	2158	return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
AnnaBridge	189:f392fc9709a3	2159	}
AnnaBridge	189:f392fc9709a3	2160
AnnaBridge	189:f392fc9709a3	2161	/**
AnnaBridge	189:f392fc9709a3	2162	* @brief Check if RCC flag Pin reset is set or not.
AnnaBridge	189:f392fc9709a3	2163	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
AnnaBridge	189:f392fc9709a3	2164	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2165	*/
AnnaBridge	189:f392fc9709a3	2166	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
AnnaBridge	189:f392fc9709a3	2167	{
AnnaBridge	189:f392fc9709a3	2168	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
AnnaBridge	189:f392fc9709a3	2169	}
AnnaBridge	189:f392fc9709a3	2170
AnnaBridge	189:f392fc9709a3	2171	/**
AnnaBridge	189:f392fc9709a3	2172	* @brief Check if RCC flag POR/PDR reset is set or not.
AnnaBridge	189:f392fc9709a3	2173	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
AnnaBridge	189:f392fc9709a3	2174	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2175	*/
AnnaBridge	189:f392fc9709a3	2176	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
AnnaBridge	189:f392fc9709a3	2177	{
AnnaBridge	189:f392fc9709a3	2178	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
AnnaBridge	189:f392fc9709a3	2179	}
AnnaBridge	189:f392fc9709a3	2180
AnnaBridge	189:f392fc9709a3	2181	/**
AnnaBridge	189:f392fc9709a3	2182	* @brief Check if RCC flag Software reset is set or not.
AnnaBridge	189:f392fc9709a3	2183	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
AnnaBridge	189:f392fc9709a3	2184	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2185	*/
AnnaBridge	189:f392fc9709a3	2186	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
AnnaBridge	189:f392fc9709a3	2187	{
AnnaBridge	189:f392fc9709a3	2188	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
AnnaBridge	189:f392fc9709a3	2189	}
AnnaBridge	189:f392fc9709a3	2190
AnnaBridge	189:f392fc9709a3	2191	/**
AnnaBridge	189:f392fc9709a3	2192	* @brief Check if RCC flag Window Watchdog reset is set or not.
AnnaBridge	189:f392fc9709a3	2193	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
AnnaBridge	189:f392fc9709a3	2194	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2195	*/
AnnaBridge	189:f392fc9709a3	2196	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
AnnaBridge	189:f392fc9709a3	2197	{
AnnaBridge	189:f392fc9709a3	2198	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
AnnaBridge	189:f392fc9709a3	2199	}
AnnaBridge	189:f392fc9709a3	2200
AnnaBridge	189:f392fc9709a3	2201	/**
AnnaBridge	189:f392fc9709a3	2202	* @brief Set RMVF bit to clear the reset flags.
AnnaBridge	189:f392fc9709a3	2203	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
AnnaBridge	189:f392fc9709a3	2204	* @retval None
AnnaBridge	189:f392fc9709a3	2205	*/
AnnaBridge	189:f392fc9709a3	2206	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
AnnaBridge	189:f392fc9709a3	2207	{
AnnaBridge	189:f392fc9709a3	2208	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
AnnaBridge	189:f392fc9709a3	2209	}
AnnaBridge	189:f392fc9709a3	2210
AnnaBridge	189:f392fc9709a3	2211	/**
AnnaBridge	189:f392fc9709a3	2212	* @}
AnnaBridge	189:f392fc9709a3	2213	*/
AnnaBridge	189:f392fc9709a3	2214
AnnaBridge	189:f392fc9709a3	2215	/** @defgroup RCC_LL_EF_IT_Management IT Management
AnnaBridge	189:f392fc9709a3	2216	* @{
AnnaBridge	189:f392fc9709a3	2217	*/
AnnaBridge	189:f392fc9709a3	2218
AnnaBridge	189:f392fc9709a3	2219	/**
AnnaBridge	189:f392fc9709a3	2220	* @brief Enable LSI ready interrupt
AnnaBridge	189:f392fc9709a3	2221	* @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
AnnaBridge	189:f392fc9709a3	2222	* @retval None
AnnaBridge	189:f392fc9709a3	2223	*/
AnnaBridge	189:f392fc9709a3	2224	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
AnnaBridge	189:f392fc9709a3	2225	{
AnnaBridge	189:f392fc9709a3	2226	SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
AnnaBridge	189:f392fc9709a3	2227	}
AnnaBridge	189:f392fc9709a3	2228
AnnaBridge	189:f392fc9709a3	2229	/**
AnnaBridge	189:f392fc9709a3	2230	* @brief Enable LSE ready interrupt
AnnaBridge	189:f392fc9709a3	2231	* @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
AnnaBridge	189:f392fc9709a3	2232	* @retval None
AnnaBridge	189:f392fc9709a3	2233	*/
AnnaBridge	189:f392fc9709a3	2234	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
AnnaBridge	189:f392fc9709a3	2235	{
AnnaBridge	189:f392fc9709a3	2236	SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
AnnaBridge	189:f392fc9709a3	2237	}
AnnaBridge	189:f392fc9709a3	2238
AnnaBridge	189:f392fc9709a3	2239	/**
AnnaBridge	189:f392fc9709a3	2240	* @brief Enable MSI ready interrupt
AnnaBridge	189:f392fc9709a3	2241	* @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
AnnaBridge	189:f392fc9709a3	2242	* @retval None
AnnaBridge	189:f392fc9709a3	2243	*/
AnnaBridge	189:f392fc9709a3	2244	__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
AnnaBridge	189:f392fc9709a3	2245	{
AnnaBridge	189:f392fc9709a3	2246	SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
AnnaBridge	189:f392fc9709a3	2247	}
AnnaBridge	189:f392fc9709a3	2248
AnnaBridge	189:f392fc9709a3	2249	/**
AnnaBridge	189:f392fc9709a3	2250	* @brief Enable HSI ready interrupt
AnnaBridge	189:f392fc9709a3	2251	* @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
AnnaBridge	189:f392fc9709a3	2252	* @retval None
AnnaBridge	189:f392fc9709a3	2253	*/
AnnaBridge	189:f392fc9709a3	2254	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
AnnaBridge	189:f392fc9709a3	2255	{
AnnaBridge	189:f392fc9709a3	2256	SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
AnnaBridge	189:f392fc9709a3	2257	}
AnnaBridge	189:f392fc9709a3	2258
AnnaBridge	189:f392fc9709a3	2259	/**
AnnaBridge	189:f392fc9709a3	2260	* @brief Enable HSE ready interrupt
AnnaBridge	189:f392fc9709a3	2261	* @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
AnnaBridge	189:f392fc9709a3	2262	* @retval None
AnnaBridge	189:f392fc9709a3	2263	*/
AnnaBridge	189:f392fc9709a3	2264	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
AnnaBridge	189:f392fc9709a3	2265	{
AnnaBridge	189:f392fc9709a3	2266	SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
AnnaBridge	189:f392fc9709a3	2267	}
AnnaBridge	189:f392fc9709a3	2268
AnnaBridge	189:f392fc9709a3	2269	/**
AnnaBridge	189:f392fc9709a3	2270	* @brief Enable PLL ready interrupt
AnnaBridge	189:f392fc9709a3	2271	* @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
AnnaBridge	189:f392fc9709a3	2272	* @retval None
AnnaBridge	189:f392fc9709a3	2273	*/
AnnaBridge	189:f392fc9709a3	2274	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
AnnaBridge	189:f392fc9709a3	2275	{
AnnaBridge	189:f392fc9709a3	2276	SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
AnnaBridge	189:f392fc9709a3	2277	}
AnnaBridge	189:f392fc9709a3	2278
AnnaBridge	189:f392fc9709a3	2279	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	2280	/**
AnnaBridge	189:f392fc9709a3	2281	* @brief Enable HSI48 ready interrupt
AnnaBridge	189:f392fc9709a3	2282	* @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
AnnaBridge	189:f392fc9709a3	2283	* @retval None
AnnaBridge	189:f392fc9709a3	2284	*/
AnnaBridge	189:f392fc9709a3	2285	__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
AnnaBridge	189:f392fc9709a3	2286	{
AnnaBridge	189:f392fc9709a3	2287	SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
AnnaBridge	189:f392fc9709a3	2288	}
AnnaBridge	189:f392fc9709a3	2289	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	2290
AnnaBridge	189:f392fc9709a3	2291	/**
AnnaBridge	189:f392fc9709a3	2292	* @brief Enable LSE clock security system interrupt
AnnaBridge	189:f392fc9709a3	2293	* @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
AnnaBridge	189:f392fc9709a3	2294	* @retval None
AnnaBridge	189:f392fc9709a3	2295	*/
AnnaBridge	189:f392fc9709a3	2296	__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
AnnaBridge	189:f392fc9709a3	2297	{
AnnaBridge	189:f392fc9709a3	2298	SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
AnnaBridge	189:f392fc9709a3	2299	}
AnnaBridge	189:f392fc9709a3	2300
AnnaBridge	189:f392fc9709a3	2301	/**
AnnaBridge	189:f392fc9709a3	2302	* @brief Disable LSI ready interrupt
AnnaBridge	189:f392fc9709a3	2303	* @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
AnnaBridge	189:f392fc9709a3	2304	* @retval None
AnnaBridge	189:f392fc9709a3	2305	*/
AnnaBridge	189:f392fc9709a3	2306	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
AnnaBridge	189:f392fc9709a3	2307	{
AnnaBridge	189:f392fc9709a3	2308	CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
AnnaBridge	189:f392fc9709a3	2309	}
AnnaBridge	189:f392fc9709a3	2310
AnnaBridge	189:f392fc9709a3	2311	/**
AnnaBridge	189:f392fc9709a3	2312	* @brief Disable LSE ready interrupt
AnnaBridge	189:f392fc9709a3	2313	* @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
AnnaBridge	189:f392fc9709a3	2314	* @retval None
AnnaBridge	189:f392fc9709a3	2315	*/
AnnaBridge	189:f392fc9709a3	2316	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
AnnaBridge	189:f392fc9709a3	2317	{
AnnaBridge	189:f392fc9709a3	2318	CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
AnnaBridge	189:f392fc9709a3	2319	}
AnnaBridge	189:f392fc9709a3	2320
AnnaBridge	189:f392fc9709a3	2321	/**
AnnaBridge	189:f392fc9709a3	2322	* @brief Disable MSI ready interrupt
AnnaBridge	189:f392fc9709a3	2323	* @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
AnnaBridge	189:f392fc9709a3	2324	* @retval None
AnnaBridge	189:f392fc9709a3	2325	*/
AnnaBridge	189:f392fc9709a3	2326	__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
AnnaBridge	189:f392fc9709a3	2327	{
AnnaBridge	189:f392fc9709a3	2328	CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
AnnaBridge	189:f392fc9709a3	2329	}
AnnaBridge	189:f392fc9709a3	2330
AnnaBridge	189:f392fc9709a3	2331	/**
AnnaBridge	189:f392fc9709a3	2332	* @brief Disable HSI ready interrupt
AnnaBridge	189:f392fc9709a3	2333	* @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
AnnaBridge	189:f392fc9709a3	2334	* @retval None
AnnaBridge	189:f392fc9709a3	2335	*/
AnnaBridge	189:f392fc9709a3	2336	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
AnnaBridge	189:f392fc9709a3	2337	{
AnnaBridge	189:f392fc9709a3	2338	CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
AnnaBridge	189:f392fc9709a3	2339	}
AnnaBridge	189:f392fc9709a3	2340
AnnaBridge	189:f392fc9709a3	2341	/**
AnnaBridge	189:f392fc9709a3	2342	* @brief Disable HSE ready interrupt
AnnaBridge	189:f392fc9709a3	2343	* @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
AnnaBridge	189:f392fc9709a3	2344	* @retval None
AnnaBridge	189:f392fc9709a3	2345	*/
AnnaBridge	189:f392fc9709a3	2346	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
AnnaBridge	189:f392fc9709a3	2347	{
AnnaBridge	189:f392fc9709a3	2348	CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
AnnaBridge	189:f392fc9709a3	2349	}
AnnaBridge	189:f392fc9709a3	2350
AnnaBridge	189:f392fc9709a3	2351	/**
AnnaBridge	189:f392fc9709a3	2352	* @brief Disable PLL ready interrupt
AnnaBridge	189:f392fc9709a3	2353	* @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
AnnaBridge	189:f392fc9709a3	2354	* @retval None
AnnaBridge	189:f392fc9709a3	2355	*/
AnnaBridge	189:f392fc9709a3	2356	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
AnnaBridge	189:f392fc9709a3	2357	{
AnnaBridge	189:f392fc9709a3	2358	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
AnnaBridge	189:f392fc9709a3	2359	}
AnnaBridge	189:f392fc9709a3	2360
AnnaBridge	189:f392fc9709a3	2361	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	2362	/**
AnnaBridge	189:f392fc9709a3	2363	* @brief Disable HSI48 ready interrupt
AnnaBridge	189:f392fc9709a3	2364	* @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
AnnaBridge	189:f392fc9709a3	2365	* @retval None
AnnaBridge	189:f392fc9709a3	2366	*/
AnnaBridge	189:f392fc9709a3	2367	__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
AnnaBridge	189:f392fc9709a3	2368	{
AnnaBridge	189:f392fc9709a3	2369	CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
AnnaBridge	189:f392fc9709a3	2370	}
AnnaBridge	189:f392fc9709a3	2371	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	2372
AnnaBridge	189:f392fc9709a3	2373	/**
AnnaBridge	189:f392fc9709a3	2374	* @brief Disable LSE clock security system interrupt
AnnaBridge	189:f392fc9709a3	2375	* @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
AnnaBridge	189:f392fc9709a3	2376	* @retval None
AnnaBridge	189:f392fc9709a3	2377	*/
AnnaBridge	189:f392fc9709a3	2378	__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
AnnaBridge	189:f392fc9709a3	2379	{
AnnaBridge	189:f392fc9709a3	2380	CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
AnnaBridge	189:f392fc9709a3	2381	}
AnnaBridge	189:f392fc9709a3	2382
AnnaBridge	189:f392fc9709a3	2383	/**
AnnaBridge	189:f392fc9709a3	2384	* @brief Checks if LSI ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2385	* @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
AnnaBridge	189:f392fc9709a3	2386	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2387	*/
AnnaBridge	189:f392fc9709a3	2388	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
AnnaBridge	189:f392fc9709a3	2389	{
AnnaBridge	189:f392fc9709a3	2390	return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE));
AnnaBridge	189:f392fc9709a3	2391	}
AnnaBridge	189:f392fc9709a3	2392
AnnaBridge	189:f392fc9709a3	2393	/**
AnnaBridge	189:f392fc9709a3	2394	* @brief Checks if LSE ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2395	* @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
AnnaBridge	189:f392fc9709a3	2396	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2397	*/
AnnaBridge	189:f392fc9709a3	2398	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
AnnaBridge	189:f392fc9709a3	2399	{
AnnaBridge	189:f392fc9709a3	2400	return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE));
AnnaBridge	189:f392fc9709a3	2401	}
AnnaBridge	189:f392fc9709a3	2402
AnnaBridge	189:f392fc9709a3	2403	/**
AnnaBridge	189:f392fc9709a3	2404	* @brief Checks if MSI ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2405	* @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
AnnaBridge	189:f392fc9709a3	2406	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2407	*/
AnnaBridge	189:f392fc9709a3	2408	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
AnnaBridge	189:f392fc9709a3	2409	{
AnnaBridge	189:f392fc9709a3	2410	return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE));
AnnaBridge	189:f392fc9709a3	2411	}
AnnaBridge	189:f392fc9709a3	2412
AnnaBridge	189:f392fc9709a3	2413	/**
AnnaBridge	189:f392fc9709a3	2414	* @brief Checks if HSI ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2415	* @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
AnnaBridge	189:f392fc9709a3	2416	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2417	*/
AnnaBridge	189:f392fc9709a3	2418	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
AnnaBridge	189:f392fc9709a3	2419	{
AnnaBridge	189:f392fc9709a3	2420	return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE));
AnnaBridge	189:f392fc9709a3	2421	}
AnnaBridge	189:f392fc9709a3	2422
AnnaBridge	189:f392fc9709a3	2423	/**
AnnaBridge	189:f392fc9709a3	2424	* @brief Checks if HSE ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2425	* @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
AnnaBridge	189:f392fc9709a3	2426	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2427	*/
AnnaBridge	189:f392fc9709a3	2428	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
AnnaBridge	189:f392fc9709a3	2429	{
AnnaBridge	189:f392fc9709a3	2430	return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE));
AnnaBridge	189:f392fc9709a3	2431	}
AnnaBridge	189:f392fc9709a3	2432
AnnaBridge	189:f392fc9709a3	2433	/**
AnnaBridge	189:f392fc9709a3	2434	* @brief Checks if PLL ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2435	* @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
AnnaBridge	189:f392fc9709a3	2436	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2437	*/
AnnaBridge	189:f392fc9709a3	2438	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
AnnaBridge	189:f392fc9709a3	2439	{
AnnaBridge	189:f392fc9709a3	2440	return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE));
AnnaBridge	189:f392fc9709a3	2441	}
AnnaBridge	189:f392fc9709a3	2442
AnnaBridge	189:f392fc9709a3	2443	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	189:f392fc9709a3	2444	/**
AnnaBridge	189:f392fc9709a3	2445	* @brief Checks if HSI48 ready interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2446	* @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
AnnaBridge	189:f392fc9709a3	2447	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2448	*/
AnnaBridge	189:f392fc9709a3	2449	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
AnnaBridge	189:f392fc9709a3	2450	{
AnnaBridge	189:f392fc9709a3	2451	return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE));
AnnaBridge	189:f392fc9709a3	2452	}
AnnaBridge	189:f392fc9709a3	2453	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	189:f392fc9709a3	2454
AnnaBridge	189:f392fc9709a3	2455	/**
AnnaBridge	189:f392fc9709a3	2456	* @brief Checks if LSECSS interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	2457	* @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
AnnaBridge	189:f392fc9709a3	2458	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	2459	*/
AnnaBridge	189:f392fc9709a3	2460	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
AnnaBridge	189:f392fc9709a3	2461	{
AnnaBridge	189:f392fc9709a3	2462	return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE));
AnnaBridge	189:f392fc9709a3	2463	}
AnnaBridge	189:f392fc9709a3	2464
AnnaBridge	189:f392fc9709a3	2465	/**
AnnaBridge	189:f392fc9709a3	2466	* @}
AnnaBridge	189:f392fc9709a3	2467	*/
AnnaBridge	189:f392fc9709a3	2468
AnnaBridge	189:f392fc9709a3	2469	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	2470	/** @defgroup RCC_LL_EF_Init De-initialization function
AnnaBridge	189:f392fc9709a3	2471	* @{
AnnaBridge	189:f392fc9709a3	2472	*/
AnnaBridge	189:f392fc9709a3	2473	ErrorStatus LL_RCC_DeInit(void);
AnnaBridge	189:f392fc9709a3	2474	/**
AnnaBridge	189:f392fc9709a3	2475	* @}
AnnaBridge	189:f392fc9709a3	2476	*/
AnnaBridge	189:f392fc9709a3	2477
AnnaBridge	189:f392fc9709a3	2478	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
AnnaBridge	189:f392fc9709a3	2479	* @{
AnnaBridge	189:f392fc9709a3	2480	*/
AnnaBridge	189:f392fc9709a3	2481	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
AnnaBridge	189:f392fc9709a3	2482	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
AnnaBridge	189:f392fc9709a3	2483	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
AnnaBridge	189:f392fc9709a3	2484	uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
AnnaBridge	189:f392fc9709a3	2485	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
AnnaBridge	189:f392fc9709a3	2486	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	189:f392fc9709a3	2487	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
AnnaBridge	189:f392fc9709a3	2488	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	189:f392fc9709a3	2489	/**
AnnaBridge	189:f392fc9709a3	2490	* @}
AnnaBridge	189:f392fc9709a3	2491	*/
AnnaBridge	189:f392fc9709a3	2492	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	2493
AnnaBridge	189:f392fc9709a3	2494	/**
AnnaBridge	189:f392fc9709a3	2495	* @}
AnnaBridge	189:f392fc9709a3	2496	*/
AnnaBridge	189:f392fc9709a3	2497
AnnaBridge	189:f392fc9709a3	2498	/**
AnnaBridge	189:f392fc9709a3	2499	* @}
AnnaBridge	189:f392fc9709a3	2500	*/
AnnaBridge	189:f392fc9709a3	2501
AnnaBridge	189:f392fc9709a3	2502	#endif /* RCC */
AnnaBridge	189:f392fc9709a3	2503
AnnaBridge	189:f392fc9709a3	2504	/**
AnnaBridge	189:f392fc9709a3	2505	* @}
AnnaBridge	189:f392fc9709a3	2506	*/
AnnaBridge	189:f392fc9709a3	2507
AnnaBridge	189:f392fc9709a3	2508	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	2509	}
AnnaBridge	189:f392fc9709a3	2510	#endif
AnnaBridge	189:f392fc9709a3	2511
AnnaBridge	189:f392fc9709a3	2512	#endif /* __STM32L0xx_LL_RCC_H */
AnnaBridge	189:f392fc9709a3	2513
AnnaBridge	189:f392fc9709a3	2514	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/