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cmsis/BUILD/mbed/TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/stm32l0xx_ll_pwr.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l0xx_ll_pwr.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of PWR LL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L0xx_LL_PWR_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L0xx_LL_PWR_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l0xx.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32L0xx_LL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | #if defined(PWR) |
| AnnaBridge | 189:f392fc9709a3 | 52 | |
| AnnaBridge | 189:f392fc9709a3 | 53 | /** @defgroup PWR_LL PWR |
| AnnaBridge | 189:f392fc9709a3 | 54 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 55 | */ |
| AnnaBridge | 189:f392fc9709a3 | 56 | |
| AnnaBridge | 189:f392fc9709a3 | 57 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 58 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 59 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 60 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 61 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 62 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 63 | /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 64 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 65 | */ |
| AnnaBridge | 189:f392fc9709a3 | 66 | |
| AnnaBridge | 189:f392fc9709a3 | 67 | /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines |
| AnnaBridge | 189:f392fc9709a3 | 68 | * @brief Flags defines which can be used with LL_PWR_WriteReg function |
| AnnaBridge | 189:f392fc9709a3 | 69 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 70 | */ |
| AnnaBridge | 189:f392fc9709a3 | 71 | #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ |
| AnnaBridge | 189:f392fc9709a3 | 72 | #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ |
| AnnaBridge | 189:f392fc9709a3 | 73 | /** |
| AnnaBridge | 189:f392fc9709a3 | 74 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 75 | */ |
| AnnaBridge | 189:f392fc9709a3 | 76 | |
| AnnaBridge | 189:f392fc9709a3 | 77 | /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines |
| AnnaBridge | 189:f392fc9709a3 | 78 | * @brief Flags defines which can be used with LL_PWR_ReadReg function |
| AnnaBridge | 189:f392fc9709a3 | 79 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 80 | */ |
| AnnaBridge | 189:f392fc9709a3 | 81 | #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ |
| AnnaBridge | 189:f392fc9709a3 | 82 | #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ |
| AnnaBridge | 189:f392fc9709a3 | 83 | #if defined(PWR_PVD_SUPPORT) |
| AnnaBridge | 189:f392fc9709a3 | 84 | #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ |
| AnnaBridge | 189:f392fc9709a3 | 85 | #endif /* PWR_PVD_SUPPORT */ |
| AnnaBridge | 189:f392fc9709a3 | 86 | #if defined(PWR_CSR_VREFINTRDYF) |
| AnnaBridge | 189:f392fc9709a3 | 87 | #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ |
| AnnaBridge | 189:f392fc9709a3 | 88 | #endif /* PWR_CSR_VREFINTRDYF */ |
| AnnaBridge | 189:f392fc9709a3 | 89 | #define LL_PWR_CSR_VOS PWR_CSR_VOSF /*!< Voltage scaling select flag */ |
| AnnaBridge | 189:f392fc9709a3 | 90 | #define LL_PWR_CSR_REGLPF PWR_CSR_REGLPF /*!< Regulator low power flag */ |
| AnnaBridge | 189:f392fc9709a3 | 91 | #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 92 | #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 93 | #if defined(PWR_CSR_EWUP3) |
| AnnaBridge | 189:f392fc9709a3 | 94 | #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 95 | #endif /* PWR_CSR_EWUP3 */ |
| AnnaBridge | 189:f392fc9709a3 | 96 | /** |
| AnnaBridge | 189:f392fc9709a3 | 97 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 98 | */ |
| AnnaBridge | 189:f392fc9709a3 | 99 | |
| AnnaBridge | 189:f392fc9709a3 | 100 | /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage |
| AnnaBridge | 189:f392fc9709a3 | 101 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 102 | */ |
| AnnaBridge | 189:f392fc9709a3 | 103 | #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0) /*!< 1.8V (range 1) */ |
| AnnaBridge | 189:f392fc9709a3 | 104 | #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1) /*!< 1.5V (range 2) */ |
| AnnaBridge | 189:f392fc9709a3 | 105 | #define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /*!< 1.2V (range 3) */ |
| AnnaBridge | 189:f392fc9709a3 | 106 | /** |
| AnnaBridge | 189:f392fc9709a3 | 107 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 108 | */ |
| AnnaBridge | 189:f392fc9709a3 | 109 | |
| AnnaBridge | 189:f392fc9709a3 | 110 | /** @defgroup PWR_LL_EC_MODE_PWR Mode Power |
| AnnaBridge | 189:f392fc9709a3 | 111 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 112 | */ |
| AnnaBridge | 189:f392fc9709a3 | 113 | #define LL_PWR_MODE_STOP 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ |
| AnnaBridge | 189:f392fc9709a3 | 114 | #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ |
| AnnaBridge | 189:f392fc9709a3 | 115 | /** |
| AnnaBridge | 189:f392fc9709a3 | 116 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 117 | */ |
| AnnaBridge | 189:f392fc9709a3 | 118 | |
| AnnaBridge | 189:f392fc9709a3 | 119 | /** @defgroup PWR_LL_EC_REGU_MODE_LP_MODES Regulator Mode In Low Power Modes |
| AnnaBridge | 189:f392fc9709a3 | 120 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 121 | */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | #define LL_PWR_REGU_LPMODES_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep/sleep/low-power run mode */ |
| AnnaBridge | 189:f392fc9709a3 | 123 | #define LL_PWR_REGU_LPMODES_LOW_POWER (PWR_CR_LPSDSR) /*!< Voltage regulator in low-power mode during deepsleep/sleep/low-power run mode */ |
| AnnaBridge | 189:f392fc9709a3 | 124 | /** |
| AnnaBridge | 189:f392fc9709a3 | 125 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 126 | */ |
| AnnaBridge | 189:f392fc9709a3 | 127 | #if defined(PWR_CR_LPDS) |
| AnnaBridge | 189:f392fc9709a3 | 128 | /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode |
| AnnaBridge | 189:f392fc9709a3 | 129 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 130 | */ |
| AnnaBridge | 189:f392fc9709a3 | 131 | #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep mode when PWR_CR_LPSDSR = 0 */ |
| AnnaBridge | 189:f392fc9709a3 | 132 | #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode when PWR_CR_LPSDSR = 0 */ |
| AnnaBridge | 189:f392fc9709a3 | 133 | /** |
| AnnaBridge | 189:f392fc9709a3 | 134 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 135 | */ |
| AnnaBridge | 189:f392fc9709a3 | 136 | #endif /* PWR_CR_LPDS */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | |
| AnnaBridge | 189:f392fc9709a3 | 138 | #if defined(PWR_PVD_SUPPORT) |
| AnnaBridge | 189:f392fc9709a3 | 139 | /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level |
| AnnaBridge | 189:f392fc9709a3 | 140 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 141 | */ |
| AnnaBridge | 189:f392fc9709a3 | 142 | #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 1.9 V */ |
| AnnaBridge | 189:f392fc9709a3 | 143 | #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.1 V */ |
| AnnaBridge | 189:f392fc9709a3 | 144 | #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.3 V */ |
| AnnaBridge | 189:f392fc9709a3 | 145 | #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ |
| AnnaBridge | 189:f392fc9709a3 | 146 | #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.7 V */ |
| AnnaBridge | 189:f392fc9709a3 | 147 | #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.9 V */ |
| AnnaBridge | 189:f392fc9709a3 | 148 | #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 3.1 V */ |
| AnnaBridge | 189:f392fc9709a3 | 149 | #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< External input analog voltage (Compare internally to VREFINT) */ |
| AnnaBridge | 189:f392fc9709a3 | 150 | /** |
| AnnaBridge | 189:f392fc9709a3 | 151 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 152 | */ |
| AnnaBridge | 189:f392fc9709a3 | 153 | #endif /* PWR_PVD_SUPPORT */ |
| AnnaBridge | 189:f392fc9709a3 | 154 | /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins |
| AnnaBridge | 189:f392fc9709a3 | 155 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 156 | */ |
| AnnaBridge | 189:f392fc9709a3 | 157 | #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ |
| AnnaBridge | 189:f392fc9709a3 | 158 | #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ |
| AnnaBridge | 189:f392fc9709a3 | 159 | #if defined(PWR_CSR_EWUP3) |
| AnnaBridge | 189:f392fc9709a3 | 160 | #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ |
| AnnaBridge | 189:f392fc9709a3 | 161 | #endif /* PWR_CSR_EWUP3 */ |
| AnnaBridge | 189:f392fc9709a3 | 162 | /** |
| AnnaBridge | 189:f392fc9709a3 | 163 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 164 | */ |
| AnnaBridge | 189:f392fc9709a3 | 165 | |
| AnnaBridge | 189:f392fc9709a3 | 166 | /** |
| AnnaBridge | 189:f392fc9709a3 | 167 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 168 | */ |
| AnnaBridge | 189:f392fc9709a3 | 169 | |
| AnnaBridge | 189:f392fc9709a3 | 170 | |
| AnnaBridge | 189:f392fc9709a3 | 171 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 172 | /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 173 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 174 | */ |
| AnnaBridge | 189:f392fc9709a3 | 175 | |
| AnnaBridge | 189:f392fc9709a3 | 176 | /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros |
| AnnaBridge | 189:f392fc9709a3 | 177 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 178 | */ |
| AnnaBridge | 189:f392fc9709a3 | 179 | |
| AnnaBridge | 189:f392fc9709a3 | 180 | /** |
| AnnaBridge | 189:f392fc9709a3 | 181 | * @brief Write a value in PWR register |
| AnnaBridge | 189:f392fc9709a3 | 182 | * @param __REG__ Register to be written |
| AnnaBridge | 189:f392fc9709a3 | 183 | * @param __VALUE__ Value to be written in the register |
| AnnaBridge | 189:f392fc9709a3 | 184 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 185 | */ |
| AnnaBridge | 189:f392fc9709a3 | 186 | #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) |
| AnnaBridge | 189:f392fc9709a3 | 187 | |
| AnnaBridge | 189:f392fc9709a3 | 188 | /** |
| AnnaBridge | 189:f392fc9709a3 | 189 | * @brief Read a value in PWR register |
| AnnaBridge | 189:f392fc9709a3 | 190 | * @param __REG__ Register to be read |
| AnnaBridge | 189:f392fc9709a3 | 191 | * @retval Register value |
| AnnaBridge | 189:f392fc9709a3 | 192 | */ |
| AnnaBridge | 189:f392fc9709a3 | 193 | #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) |
| AnnaBridge | 189:f392fc9709a3 | 194 | /** |
| AnnaBridge | 189:f392fc9709a3 | 195 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 196 | */ |
| AnnaBridge | 189:f392fc9709a3 | 197 | |
| AnnaBridge | 189:f392fc9709a3 | 198 | /** |
| AnnaBridge | 189:f392fc9709a3 | 199 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 200 | */ |
| AnnaBridge | 189:f392fc9709a3 | 201 | |
| AnnaBridge | 189:f392fc9709a3 | 202 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 203 | /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 204 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 205 | */ |
| AnnaBridge | 189:f392fc9709a3 | 206 | |
| AnnaBridge | 189:f392fc9709a3 | 207 | /** @defgroup PWR_LL_EF_Configuration Configuration |
| AnnaBridge | 189:f392fc9709a3 | 208 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 209 | */ |
| AnnaBridge | 189:f392fc9709a3 | 210 | /** |
| AnnaBridge | 189:f392fc9709a3 | 211 | * @brief Switch the regulator from main mode to low-power mode |
| AnnaBridge | 189:f392fc9709a3 | 212 | * @rmtoll CR LPRUN LL_PWR_EnableLowPowerRunMode |
| AnnaBridge | 189:f392fc9709a3 | 213 | * @note Remind to set the regulator to low power before enabling |
| AnnaBridge | 189:f392fc9709a3 | 214 | * LowPower run mode (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER). |
| AnnaBridge | 189:f392fc9709a3 | 215 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 216 | */ |
| AnnaBridge | 189:f392fc9709a3 | 217 | __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 218 | { |
| AnnaBridge | 189:f392fc9709a3 | 219 | SET_BIT(PWR->CR, PWR_CR_LPRUN); |
| AnnaBridge | 189:f392fc9709a3 | 220 | } |
| AnnaBridge | 189:f392fc9709a3 | 221 | |
| AnnaBridge | 189:f392fc9709a3 | 222 | /** |
| AnnaBridge | 189:f392fc9709a3 | 223 | * @brief Switch the regulator from low-power mode to main mode |
| AnnaBridge | 189:f392fc9709a3 | 224 | * @rmtoll CR LPRUN LL_PWR_DisableLowPowerRunMode |
| AnnaBridge | 189:f392fc9709a3 | 225 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 226 | */ |
| AnnaBridge | 189:f392fc9709a3 | 227 | __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 228 | { |
| AnnaBridge | 189:f392fc9709a3 | 229 | CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); |
| AnnaBridge | 189:f392fc9709a3 | 230 | } |
| AnnaBridge | 189:f392fc9709a3 | 231 | |
| AnnaBridge | 189:f392fc9709a3 | 232 | /** |
| AnnaBridge | 189:f392fc9709a3 | 233 | * @brief Check if the regulator is in low-power mode |
| AnnaBridge | 189:f392fc9709a3 | 234 | * @rmtoll CR LPRUN LL_PWR_IsEnabledLowPowerRunMode |
| AnnaBridge | 189:f392fc9709a3 | 235 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 236 | */ |
| AnnaBridge | 189:f392fc9709a3 | 237 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 238 | { |
| AnnaBridge | 189:f392fc9709a3 | 239 | return (READ_BIT(PWR->CR, PWR_CR_LPRUN) == (PWR_CR_LPRUN)); |
| AnnaBridge | 189:f392fc9709a3 | 240 | } |
| AnnaBridge | 189:f392fc9709a3 | 241 | |
| AnnaBridge | 189:f392fc9709a3 | 242 | /** |
| AnnaBridge | 189:f392fc9709a3 | 243 | * @brief Set voltage regulator to low-power and switch from |
| AnnaBridge | 189:f392fc9709a3 | 244 | * run main mode to run low-power mode. |
| AnnaBridge | 189:f392fc9709a3 | 245 | * @rmtoll CR LPSDSR LL_PWR_EnterLowPowerRunMode\n |
| AnnaBridge | 189:f392fc9709a3 | 246 | * CR LPRUN LL_PWR_EnterLowPowerRunMode |
| AnnaBridge | 189:f392fc9709a3 | 247 | * @note This "high level" function is introduced to provide functional |
| AnnaBridge | 189:f392fc9709a3 | 248 | * compatibility with other families. Notice that the two registers |
| AnnaBridge | 189:f392fc9709a3 | 249 | * have to be written sequentially, so this function is not atomic. |
| AnnaBridge | 189:f392fc9709a3 | 250 | * To assure atomicity you can call separately the following functions: |
| AnnaBridge | 189:f392fc9709a3 | 251 | * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_LOW_POWER); |
| AnnaBridge | 189:f392fc9709a3 | 252 | * - @ref LL_PWR_EnableLowPowerRunMode(); |
| AnnaBridge | 189:f392fc9709a3 | 253 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 254 | */ |
| AnnaBridge | 189:f392fc9709a3 | 255 | __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 256 | { |
| AnnaBridge | 189:f392fc9709a3 | 257 | SET_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_LOW_POWER) */ |
| AnnaBridge | 189:f392fc9709a3 | 258 | SET_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_EnableLowPowerRunMode() */ |
| AnnaBridge | 189:f392fc9709a3 | 259 | } |
| AnnaBridge | 189:f392fc9709a3 | 260 | |
| AnnaBridge | 189:f392fc9709a3 | 261 | /** |
| AnnaBridge | 189:f392fc9709a3 | 262 | * @brief Set voltage regulator to main and switch from |
| AnnaBridge | 189:f392fc9709a3 | 263 | * run main mode to low-power mode. |
| AnnaBridge | 189:f392fc9709a3 | 264 | * @rmtoll CR LPSDSR LL_PWR_ExitLowPowerRunMode\n |
| AnnaBridge | 189:f392fc9709a3 | 265 | * CR LPRUN LL_PWR_ExitLowPowerRunMode |
| AnnaBridge | 189:f392fc9709a3 | 266 | * @note This "high level" function is introduced to provide functional |
| AnnaBridge | 189:f392fc9709a3 | 267 | * compatibility with other families. Notice that the two registers |
| AnnaBridge | 189:f392fc9709a3 | 268 | * have to be written sequentially, so this function is not atomic. |
| AnnaBridge | 189:f392fc9709a3 | 269 | * To assure atomicity you can call separately the following functions: |
| AnnaBridge | 189:f392fc9709a3 | 270 | * - @ref LL_PWR_DisableLowPowerRunMode(); |
| AnnaBridge | 189:f392fc9709a3 | 271 | * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_MAIN); |
| AnnaBridge | 189:f392fc9709a3 | 272 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 273 | */ |
| AnnaBridge | 189:f392fc9709a3 | 274 | __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 275 | { |
| AnnaBridge | 189:f392fc9709a3 | 276 | CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_DisableLowPowerRunMode() */ |
| AnnaBridge | 189:f392fc9709a3 | 277 | CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_MAIN) */ |
| AnnaBridge | 189:f392fc9709a3 | 278 | } |
| AnnaBridge | 189:f392fc9709a3 | 279 | /** |
| AnnaBridge | 189:f392fc9709a3 | 280 | * @brief Set the main internal regulator output voltage |
| AnnaBridge | 189:f392fc9709a3 | 281 | * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling |
| AnnaBridge | 189:f392fc9709a3 | 282 | * @param VoltageScaling This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 283 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 |
| AnnaBridge | 189:f392fc9709a3 | 284 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 |
| AnnaBridge | 189:f392fc9709a3 | 285 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 |
| AnnaBridge | 189:f392fc9709a3 | 286 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 287 | */ |
| AnnaBridge | 189:f392fc9709a3 | 288 | __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) |
| AnnaBridge | 189:f392fc9709a3 | 289 | { |
| AnnaBridge | 189:f392fc9709a3 | 290 | MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling); |
| AnnaBridge | 189:f392fc9709a3 | 291 | } |
| AnnaBridge | 189:f392fc9709a3 | 292 | |
| AnnaBridge | 189:f392fc9709a3 | 293 | /** |
| AnnaBridge | 189:f392fc9709a3 | 294 | * @brief Get the main internal regulator output voltage |
| AnnaBridge | 189:f392fc9709a3 | 295 | * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling |
| AnnaBridge | 189:f392fc9709a3 | 296 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 297 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 |
| AnnaBridge | 189:f392fc9709a3 | 298 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 |
| AnnaBridge | 189:f392fc9709a3 | 299 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 |
| AnnaBridge | 189:f392fc9709a3 | 300 | */ |
| AnnaBridge | 189:f392fc9709a3 | 301 | __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) |
| AnnaBridge | 189:f392fc9709a3 | 302 | { |
| AnnaBridge | 189:f392fc9709a3 | 303 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS)); |
| AnnaBridge | 189:f392fc9709a3 | 304 | } |
| AnnaBridge | 189:f392fc9709a3 | 305 | |
| AnnaBridge | 189:f392fc9709a3 | 306 | /** |
| AnnaBridge | 189:f392fc9709a3 | 307 | * @brief Enable access to the backup domain |
| AnnaBridge | 189:f392fc9709a3 | 308 | * @rmtoll CR DBP LL_PWR_EnableBkUpAccess |
| AnnaBridge | 189:f392fc9709a3 | 309 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 310 | */ |
| AnnaBridge | 189:f392fc9709a3 | 311 | __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) |
| AnnaBridge | 189:f392fc9709a3 | 312 | { |
| AnnaBridge | 189:f392fc9709a3 | 313 | SET_BIT(PWR->CR, PWR_CR_DBP); |
| AnnaBridge | 189:f392fc9709a3 | 314 | } |
| AnnaBridge | 189:f392fc9709a3 | 315 | |
| AnnaBridge | 189:f392fc9709a3 | 316 | /** |
| AnnaBridge | 189:f392fc9709a3 | 317 | * @brief Disable access to the backup domain |
| AnnaBridge | 189:f392fc9709a3 | 318 | * @rmtoll CR DBP LL_PWR_DisableBkUpAccess |
| AnnaBridge | 189:f392fc9709a3 | 319 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 320 | */ |
| AnnaBridge | 189:f392fc9709a3 | 321 | __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) |
| AnnaBridge | 189:f392fc9709a3 | 322 | { |
| AnnaBridge | 189:f392fc9709a3 | 323 | CLEAR_BIT(PWR->CR, PWR_CR_DBP); |
| AnnaBridge | 189:f392fc9709a3 | 324 | } |
| AnnaBridge | 189:f392fc9709a3 | 325 | |
| AnnaBridge | 189:f392fc9709a3 | 326 | /** |
| AnnaBridge | 189:f392fc9709a3 | 327 | * @brief Check if the backup domain is enabled |
| AnnaBridge | 189:f392fc9709a3 | 328 | * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess |
| AnnaBridge | 189:f392fc9709a3 | 329 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 330 | */ |
| AnnaBridge | 189:f392fc9709a3 | 331 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) |
| AnnaBridge | 189:f392fc9709a3 | 332 | { |
| AnnaBridge | 189:f392fc9709a3 | 333 | return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); |
| AnnaBridge | 189:f392fc9709a3 | 334 | } |
| AnnaBridge | 189:f392fc9709a3 | 335 | |
| AnnaBridge | 189:f392fc9709a3 | 336 | /** |
| AnnaBridge | 189:f392fc9709a3 | 337 | * @brief Set voltage regulator mode during low power modes |
| AnnaBridge | 189:f392fc9709a3 | 338 | * @rmtoll CR LPSDSR LL_PWR_SetRegulModeLP |
| AnnaBridge | 189:f392fc9709a3 | 339 | * @param RegulMode This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 340 | * @arg @ref LL_PWR_REGU_LPMODES_MAIN |
| AnnaBridge | 189:f392fc9709a3 | 341 | * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER |
| AnnaBridge | 189:f392fc9709a3 | 342 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 343 | */ |
| AnnaBridge | 189:f392fc9709a3 | 344 | __STATIC_INLINE void LL_PWR_SetRegulModeLP(uint32_t RegulMode) |
| AnnaBridge | 189:f392fc9709a3 | 345 | { |
| AnnaBridge | 189:f392fc9709a3 | 346 | MODIFY_REG(PWR->CR, PWR_CR_LPSDSR, RegulMode); |
| AnnaBridge | 189:f392fc9709a3 | 347 | } |
| AnnaBridge | 189:f392fc9709a3 | 348 | |
| AnnaBridge | 189:f392fc9709a3 | 349 | /** |
| AnnaBridge | 189:f392fc9709a3 | 350 | * @brief Get voltage regulator mode during low power modes |
| AnnaBridge | 189:f392fc9709a3 | 351 | * @rmtoll CR LPSDSR LL_PWR_GetRegulModeLP |
| AnnaBridge | 189:f392fc9709a3 | 352 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 353 | * @arg @ref LL_PWR_REGU_LPMODES_MAIN |
| AnnaBridge | 189:f392fc9709a3 | 354 | * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER |
| AnnaBridge | 189:f392fc9709a3 | 355 | */ |
| AnnaBridge | 189:f392fc9709a3 | 356 | __STATIC_INLINE uint32_t LL_PWR_GetRegulModeLP(void) |
| AnnaBridge | 189:f392fc9709a3 | 357 | { |
| AnnaBridge | 189:f392fc9709a3 | 358 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPSDSR)); |
| AnnaBridge | 189:f392fc9709a3 | 359 | } |
| AnnaBridge | 189:f392fc9709a3 | 360 | |
| AnnaBridge | 189:f392fc9709a3 | 361 | #if defined(PWR_CR_LPDS) |
| AnnaBridge | 189:f392fc9709a3 | 362 | /** |
| AnnaBridge | 189:f392fc9709a3 | 363 | * @brief Set voltage regulator mode during deep sleep mode |
| AnnaBridge | 189:f392fc9709a3 | 364 | * @rmtoll CR LPDS LL_PWR_SetRegulModeDS |
| AnnaBridge | 189:f392fc9709a3 | 365 | * @param RegulMode This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 366 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
| AnnaBridge | 189:f392fc9709a3 | 367 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
| AnnaBridge | 189:f392fc9709a3 | 368 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 369 | */ |
| AnnaBridge | 189:f392fc9709a3 | 370 | __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) |
| AnnaBridge | 189:f392fc9709a3 | 371 | { |
| AnnaBridge | 189:f392fc9709a3 | 372 | MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); |
| AnnaBridge | 189:f392fc9709a3 | 373 | } |
| AnnaBridge | 189:f392fc9709a3 | 374 | |
| AnnaBridge | 189:f392fc9709a3 | 375 | /** |
| AnnaBridge | 189:f392fc9709a3 | 376 | * @brief Get voltage regulator mode during deep sleep mode |
| AnnaBridge | 189:f392fc9709a3 | 377 | * @rmtoll CR LPDS LL_PWR_GetRegulModeDS |
| AnnaBridge | 189:f392fc9709a3 | 378 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 379 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
| AnnaBridge | 189:f392fc9709a3 | 380 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
| AnnaBridge | 189:f392fc9709a3 | 381 | */ |
| AnnaBridge | 189:f392fc9709a3 | 382 | __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) |
| AnnaBridge | 189:f392fc9709a3 | 383 | { |
| AnnaBridge | 189:f392fc9709a3 | 384 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); |
| AnnaBridge | 189:f392fc9709a3 | 385 | } |
| AnnaBridge | 189:f392fc9709a3 | 386 | #endif /* PWR_CR_LPDS */ |
| AnnaBridge | 189:f392fc9709a3 | 387 | |
| AnnaBridge | 189:f392fc9709a3 | 388 | /** |
| AnnaBridge | 189:f392fc9709a3 | 389 | * @brief Set power down mode when CPU enters deepsleep |
| AnnaBridge | 189:f392fc9709a3 | 390 | * @rmtoll CR PDDS LL_PWR_SetPowerMode |
| AnnaBridge | 189:f392fc9709a3 | 391 | * @param PDMode This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 392 | * @arg @ref LL_PWR_MODE_STOP |
| AnnaBridge | 189:f392fc9709a3 | 393 | * @arg @ref LL_PWR_MODE_STANDBY |
| AnnaBridge | 189:f392fc9709a3 | 394 | * @note Set the regulator to low power (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER) |
| AnnaBridge | 189:f392fc9709a3 | 395 | * before setting MODE_STOP. If the regulator remains in "main mode", |
| AnnaBridge | 189:f392fc9709a3 | 396 | * it consumes more power without providing any additional feature. |
| AnnaBridge | 189:f392fc9709a3 | 397 | * In MODE_STANDBY the regulator is automatically off. |
| AnnaBridge | 189:f392fc9709a3 | 398 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 399 | */ |
| AnnaBridge | 189:f392fc9709a3 | 400 | __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) |
| AnnaBridge | 189:f392fc9709a3 | 401 | { |
| AnnaBridge | 189:f392fc9709a3 | 402 | MODIFY_REG(PWR->CR, PWR_CR_PDDS, PDMode); |
| AnnaBridge | 189:f392fc9709a3 | 403 | } |
| AnnaBridge | 189:f392fc9709a3 | 404 | |
| AnnaBridge | 189:f392fc9709a3 | 405 | /** |
| AnnaBridge | 189:f392fc9709a3 | 406 | * @brief Get power down mode when CPU enters deepsleep |
| AnnaBridge | 189:f392fc9709a3 | 407 | * @rmtoll CR PDDS LL_PWR_GetPowerMode |
| AnnaBridge | 189:f392fc9709a3 | 408 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 409 | * @arg @ref LL_PWR_MODE_STOP |
| AnnaBridge | 189:f392fc9709a3 | 410 | * @arg @ref LL_PWR_MODE_STANDBY |
| AnnaBridge | 189:f392fc9709a3 | 411 | */ |
| AnnaBridge | 189:f392fc9709a3 | 412 | __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) |
| AnnaBridge | 189:f392fc9709a3 | 413 | { |
| AnnaBridge | 189:f392fc9709a3 | 414 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PDDS)); |
| AnnaBridge | 189:f392fc9709a3 | 415 | } |
| AnnaBridge | 189:f392fc9709a3 | 416 | |
| AnnaBridge | 189:f392fc9709a3 | 417 | #if defined(PWR_PVD_SUPPORT) |
| AnnaBridge | 189:f392fc9709a3 | 418 | /** |
| AnnaBridge | 189:f392fc9709a3 | 419 | * @brief Configure the voltage threshold detected by the Power Voltage Detector |
| AnnaBridge | 189:f392fc9709a3 | 420 | * @rmtoll CR PLS LL_PWR_SetPVDLevel |
| AnnaBridge | 189:f392fc9709a3 | 421 | * @param PVDLevel This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 422 | * @arg @ref LL_PWR_PVDLEVEL_0 |
| AnnaBridge | 189:f392fc9709a3 | 423 | * @arg @ref LL_PWR_PVDLEVEL_1 |
| AnnaBridge | 189:f392fc9709a3 | 424 | * @arg @ref LL_PWR_PVDLEVEL_2 |
| AnnaBridge | 189:f392fc9709a3 | 425 | * @arg @ref LL_PWR_PVDLEVEL_3 |
| AnnaBridge | 189:f392fc9709a3 | 426 | * @arg @ref LL_PWR_PVDLEVEL_4 |
| AnnaBridge | 189:f392fc9709a3 | 427 | * @arg @ref LL_PWR_PVDLEVEL_5 |
| AnnaBridge | 189:f392fc9709a3 | 428 | * @arg @ref LL_PWR_PVDLEVEL_6 |
| AnnaBridge | 189:f392fc9709a3 | 429 | * @arg @ref LL_PWR_PVDLEVEL_7 |
| AnnaBridge | 189:f392fc9709a3 | 430 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 431 | */ |
| AnnaBridge | 189:f392fc9709a3 | 432 | __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) |
| AnnaBridge | 189:f392fc9709a3 | 433 | { |
| AnnaBridge | 189:f392fc9709a3 | 434 | MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); |
| AnnaBridge | 189:f392fc9709a3 | 435 | } |
| AnnaBridge | 189:f392fc9709a3 | 436 | |
| AnnaBridge | 189:f392fc9709a3 | 437 | /** |
| AnnaBridge | 189:f392fc9709a3 | 438 | * @brief Get the voltage threshold detection |
| AnnaBridge | 189:f392fc9709a3 | 439 | * @rmtoll CR PLS LL_PWR_GetPVDLevel |
| AnnaBridge | 189:f392fc9709a3 | 440 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 441 | * @arg @ref LL_PWR_PVDLEVEL_0 |
| AnnaBridge | 189:f392fc9709a3 | 442 | * @arg @ref LL_PWR_PVDLEVEL_1 |
| AnnaBridge | 189:f392fc9709a3 | 443 | * @arg @ref LL_PWR_PVDLEVEL_2 |
| AnnaBridge | 189:f392fc9709a3 | 444 | * @arg @ref LL_PWR_PVDLEVEL_3 |
| AnnaBridge | 189:f392fc9709a3 | 445 | * @arg @ref LL_PWR_PVDLEVEL_4 |
| AnnaBridge | 189:f392fc9709a3 | 446 | * @arg @ref LL_PWR_PVDLEVEL_5 |
| AnnaBridge | 189:f392fc9709a3 | 447 | * @arg @ref LL_PWR_PVDLEVEL_6 |
| AnnaBridge | 189:f392fc9709a3 | 448 | * @arg @ref LL_PWR_PVDLEVEL_7 |
| AnnaBridge | 189:f392fc9709a3 | 449 | */ |
| AnnaBridge | 189:f392fc9709a3 | 450 | __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) |
| AnnaBridge | 189:f392fc9709a3 | 451 | { |
| AnnaBridge | 189:f392fc9709a3 | 452 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); |
| AnnaBridge | 189:f392fc9709a3 | 453 | } |
| AnnaBridge | 189:f392fc9709a3 | 454 | |
| AnnaBridge | 189:f392fc9709a3 | 455 | /** |
| AnnaBridge | 189:f392fc9709a3 | 456 | * @brief Enable Power Voltage Detector |
| AnnaBridge | 189:f392fc9709a3 | 457 | * @rmtoll CR PVDE LL_PWR_EnablePVD |
| AnnaBridge | 189:f392fc9709a3 | 458 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 459 | */ |
| AnnaBridge | 189:f392fc9709a3 | 460 | __STATIC_INLINE void LL_PWR_EnablePVD(void) |
| AnnaBridge | 189:f392fc9709a3 | 461 | { |
| AnnaBridge | 189:f392fc9709a3 | 462 | SET_BIT(PWR->CR, PWR_CR_PVDE); |
| AnnaBridge | 189:f392fc9709a3 | 463 | } |
| AnnaBridge | 189:f392fc9709a3 | 464 | |
| AnnaBridge | 189:f392fc9709a3 | 465 | /** |
| AnnaBridge | 189:f392fc9709a3 | 466 | * @brief Disable Power Voltage Detector |
| AnnaBridge | 189:f392fc9709a3 | 467 | * @rmtoll CR PVDE LL_PWR_DisablePVD |
| AnnaBridge | 189:f392fc9709a3 | 468 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 469 | */ |
| AnnaBridge | 189:f392fc9709a3 | 470 | __STATIC_INLINE void LL_PWR_DisablePVD(void) |
| AnnaBridge | 189:f392fc9709a3 | 471 | { |
| AnnaBridge | 189:f392fc9709a3 | 472 | CLEAR_BIT(PWR->CR, PWR_CR_PVDE); |
| AnnaBridge | 189:f392fc9709a3 | 473 | } |
| AnnaBridge | 189:f392fc9709a3 | 474 | |
| AnnaBridge | 189:f392fc9709a3 | 475 | /** |
| AnnaBridge | 189:f392fc9709a3 | 476 | * @brief Check if Power Voltage Detector is enabled |
| AnnaBridge | 189:f392fc9709a3 | 477 | * @rmtoll CR PVDE LL_PWR_IsEnabledPVD |
| AnnaBridge | 189:f392fc9709a3 | 478 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 479 | */ |
| AnnaBridge | 189:f392fc9709a3 | 480 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) |
| AnnaBridge | 189:f392fc9709a3 | 481 | { |
| AnnaBridge | 189:f392fc9709a3 | 482 | return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); |
| AnnaBridge | 189:f392fc9709a3 | 483 | } |
| AnnaBridge | 189:f392fc9709a3 | 484 | #endif /* PWR_PVD_SUPPORT */ |
| AnnaBridge | 189:f392fc9709a3 | 485 | |
| AnnaBridge | 189:f392fc9709a3 | 486 | /** |
| AnnaBridge | 189:f392fc9709a3 | 487 | * @brief Enable the WakeUp PINx functionality |
| AnnaBridge | 189:f392fc9709a3 | 488 | * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 489 | * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 490 | * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin |
| AnnaBridge | 189:f392fc9709a3 | 491 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 492 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 189:f392fc9709a3 | 493 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
| AnnaBridge | 189:f392fc9709a3 | 494 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
| AnnaBridge | 189:f392fc9709a3 | 495 | * |
| AnnaBridge | 189:f392fc9709a3 | 496 | * (*) not available on all devices |
| AnnaBridge | 189:f392fc9709a3 | 497 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 498 | */ |
| AnnaBridge | 189:f392fc9709a3 | 499 | __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) |
| AnnaBridge | 189:f392fc9709a3 | 500 | { |
| AnnaBridge | 189:f392fc9709a3 | 501 | SET_BIT(PWR->CSR, WakeUpPin); |
| AnnaBridge | 189:f392fc9709a3 | 502 | } |
| AnnaBridge | 189:f392fc9709a3 | 503 | |
| AnnaBridge | 189:f392fc9709a3 | 504 | /** |
| AnnaBridge | 189:f392fc9709a3 | 505 | * @brief Disable the WakeUp PINx functionality |
| AnnaBridge | 189:f392fc9709a3 | 506 | * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 507 | * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 508 | * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin |
| AnnaBridge | 189:f392fc9709a3 | 509 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 510 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 189:f392fc9709a3 | 511 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
| AnnaBridge | 189:f392fc9709a3 | 512 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
| AnnaBridge | 189:f392fc9709a3 | 513 | * |
| AnnaBridge | 189:f392fc9709a3 | 514 | * (*) not available on all devices |
| AnnaBridge | 189:f392fc9709a3 | 515 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 516 | */ |
| AnnaBridge | 189:f392fc9709a3 | 517 | __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) |
| AnnaBridge | 189:f392fc9709a3 | 518 | { |
| AnnaBridge | 189:f392fc9709a3 | 519 | CLEAR_BIT(PWR->CSR, WakeUpPin); |
| AnnaBridge | 189:f392fc9709a3 | 520 | } |
| AnnaBridge | 189:f392fc9709a3 | 521 | |
| AnnaBridge | 189:f392fc9709a3 | 522 | /** |
| AnnaBridge | 189:f392fc9709a3 | 523 | * @brief Check if the WakeUp PINx functionality is enabled |
| AnnaBridge | 189:f392fc9709a3 | 524 | * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 525 | * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n |
| AnnaBridge | 189:f392fc9709a3 | 526 | * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin |
| AnnaBridge | 189:f392fc9709a3 | 527 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 528 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 189:f392fc9709a3 | 529 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
| AnnaBridge | 189:f392fc9709a3 | 530 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
| AnnaBridge | 189:f392fc9709a3 | 531 | * |
| AnnaBridge | 189:f392fc9709a3 | 532 | * (*) not available on all devices |
| AnnaBridge | 189:f392fc9709a3 | 533 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 534 | */ |
| AnnaBridge | 189:f392fc9709a3 | 535 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) |
| AnnaBridge | 189:f392fc9709a3 | 536 | { |
| AnnaBridge | 189:f392fc9709a3 | 537 | return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); |
| AnnaBridge | 189:f392fc9709a3 | 538 | } |
| AnnaBridge | 189:f392fc9709a3 | 539 | |
| AnnaBridge | 189:f392fc9709a3 | 540 | /** |
| AnnaBridge | 189:f392fc9709a3 | 541 | * @brief Enable ultra low-power mode by enabling VREFINT switch off in low-power modes |
| AnnaBridge | 189:f392fc9709a3 | 542 | * @rmtoll CR ULP LL_PWR_EnableUltraLowPower |
| AnnaBridge | 189:f392fc9709a3 | 543 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 544 | */ |
| AnnaBridge | 189:f392fc9709a3 | 545 | __STATIC_INLINE void LL_PWR_EnableUltraLowPower(void) |
| AnnaBridge | 189:f392fc9709a3 | 546 | { |
| AnnaBridge | 189:f392fc9709a3 | 547 | SET_BIT(PWR->CR, PWR_CR_ULP); |
| AnnaBridge | 189:f392fc9709a3 | 548 | } |
| AnnaBridge | 189:f392fc9709a3 | 549 | |
| AnnaBridge | 189:f392fc9709a3 | 550 | /** |
| AnnaBridge | 189:f392fc9709a3 | 551 | * @brief Disable ultra low-power mode by disabling VREFINT switch off in low-power modes |
| AnnaBridge | 189:f392fc9709a3 | 552 | * @rmtoll CR ULP LL_PWR_DisableUltraLowPower |
| AnnaBridge | 189:f392fc9709a3 | 553 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 554 | */ |
| AnnaBridge | 189:f392fc9709a3 | 555 | __STATIC_INLINE void LL_PWR_DisableUltraLowPower(void) |
| AnnaBridge | 189:f392fc9709a3 | 556 | { |
| AnnaBridge | 189:f392fc9709a3 | 557 | CLEAR_BIT(PWR->CR, PWR_CR_ULP); |
| AnnaBridge | 189:f392fc9709a3 | 558 | } |
| AnnaBridge | 189:f392fc9709a3 | 559 | |
| AnnaBridge | 189:f392fc9709a3 | 560 | /** |
| AnnaBridge | 189:f392fc9709a3 | 561 | * @brief Check if ultra low-power mode is enabled by checking if VREFINT switch off in low-power modes is enabled |
| AnnaBridge | 189:f392fc9709a3 | 562 | * @rmtoll CR ULP LL_PWR_IsEnabledUltraLowPower |
| AnnaBridge | 189:f392fc9709a3 | 563 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 564 | */ |
| AnnaBridge | 189:f392fc9709a3 | 565 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPower(void) |
| AnnaBridge | 189:f392fc9709a3 | 566 | { |
| AnnaBridge | 189:f392fc9709a3 | 567 | return (READ_BIT(PWR->CR, PWR_CR_ULP) == (PWR_CR_ULP)); |
| AnnaBridge | 189:f392fc9709a3 | 568 | } |
| AnnaBridge | 189:f392fc9709a3 | 569 | |
| AnnaBridge | 189:f392fc9709a3 | 570 | /** |
| AnnaBridge | 189:f392fc9709a3 | 571 | * @brief Enable fast wakeup by ignoring VREFINT startup time when exiting from low-power mode |
| AnnaBridge | 189:f392fc9709a3 | 572 | * @rmtoll CR FWU LL_PWR_EnableFastWakeUp |
| AnnaBridge | 189:f392fc9709a3 | 573 | * @note Works in conjunction with ultra low power mode. |
| AnnaBridge | 189:f392fc9709a3 | 574 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 575 | */ |
| AnnaBridge | 189:f392fc9709a3 | 576 | __STATIC_INLINE void LL_PWR_EnableFastWakeUp(void) |
| AnnaBridge | 189:f392fc9709a3 | 577 | { |
| AnnaBridge | 189:f392fc9709a3 | 578 | SET_BIT(PWR->CR, PWR_CR_FWU); |
| AnnaBridge | 189:f392fc9709a3 | 579 | } |
| AnnaBridge | 189:f392fc9709a3 | 580 | |
| AnnaBridge | 189:f392fc9709a3 | 581 | /** |
| AnnaBridge | 189:f392fc9709a3 | 582 | * @brief Disable fast wakeup by waiting VREFINT startup time when exiting from low-power mode |
| AnnaBridge | 189:f392fc9709a3 | 583 | * @rmtoll CR FWU LL_PWR_DisableFastWakeUp |
| AnnaBridge | 189:f392fc9709a3 | 584 | * @note Works in conjunction with ultra low power mode. |
| AnnaBridge | 189:f392fc9709a3 | 585 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 586 | */ |
| AnnaBridge | 189:f392fc9709a3 | 587 | __STATIC_INLINE void LL_PWR_DisableFastWakeUp(void) |
| AnnaBridge | 189:f392fc9709a3 | 588 | { |
| AnnaBridge | 189:f392fc9709a3 | 589 | CLEAR_BIT(PWR->CR, PWR_CR_FWU); |
| AnnaBridge | 189:f392fc9709a3 | 590 | } |
| AnnaBridge | 189:f392fc9709a3 | 591 | |
| AnnaBridge | 189:f392fc9709a3 | 592 | /** |
| AnnaBridge | 189:f392fc9709a3 | 593 | * @brief Check if fast wakeup is enabled by checking if VREFINT startup time when exiting from low-power mode is ignored |
| AnnaBridge | 189:f392fc9709a3 | 594 | * @rmtoll CR FWU LL_PWR_IsEnabledFastWakeUp |
| AnnaBridge | 189:f392fc9709a3 | 595 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 596 | */ |
| AnnaBridge | 189:f392fc9709a3 | 597 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledFastWakeUp(void) |
| AnnaBridge | 189:f392fc9709a3 | 598 | { |
| AnnaBridge | 189:f392fc9709a3 | 599 | return (READ_BIT(PWR->CR, PWR_CR_FWU) == (PWR_CR_FWU)); |
| AnnaBridge | 189:f392fc9709a3 | 600 | } |
| AnnaBridge | 189:f392fc9709a3 | 601 | |
| AnnaBridge | 189:f392fc9709a3 | 602 | /** |
| AnnaBridge | 189:f392fc9709a3 | 603 | * @brief Enable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode |
| AnnaBridge | 189:f392fc9709a3 | 604 | * @rmtoll CR DS_EE_KOFF LL_PWR_EnableNVMKeptOff |
| AnnaBridge | 189:f392fc9709a3 | 605 | * @note When enabled, after entering low-power mode (Stop or Standby only), if RUN_PD of FLASH_ACR register |
| AnnaBridge | 189:f392fc9709a3 | 606 | * is also set, the Flash memory will not be woken up when exiting from deepsleep mode. |
| AnnaBridge | 189:f392fc9709a3 | 607 | * When enabled, the EEPROM will not be woken up when exiting from low-power mode (if the bit RUN_PD is set) |
| AnnaBridge | 189:f392fc9709a3 | 608 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 609 | */ |
| AnnaBridge | 189:f392fc9709a3 | 610 | __STATIC_INLINE void LL_PWR_EnableNVMKeptOff(void) |
| AnnaBridge | 189:f392fc9709a3 | 611 | { |
| AnnaBridge | 189:f392fc9709a3 | 612 | SET_BIT(PWR->CR, PWR_CR_DSEEKOFF); |
| AnnaBridge | 189:f392fc9709a3 | 613 | } |
| AnnaBridge | 189:f392fc9709a3 | 614 | |
| AnnaBridge | 189:f392fc9709a3 | 615 | /** |
| AnnaBridge | 189:f392fc9709a3 | 616 | * @brief Disable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode |
| AnnaBridge | 189:f392fc9709a3 | 617 | * @rmtoll CR DS_EE_KOFF LL_PWR_DisableNVMKeptOff |
| AnnaBridge | 189:f392fc9709a3 | 618 | * @note When disabled, Flash memory is woken up when exiting from deepsleep mode even if the bit RUN_PD is set |
| AnnaBridge | 189:f392fc9709a3 | 619 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 620 | */ |
| AnnaBridge | 189:f392fc9709a3 | 621 | __STATIC_INLINE void LL_PWR_DisableNVMKeptOff(void) |
| AnnaBridge | 189:f392fc9709a3 | 622 | { |
| AnnaBridge | 189:f392fc9709a3 | 623 | CLEAR_BIT(PWR->CR, PWR_CR_DSEEKOFF); |
| AnnaBridge | 189:f392fc9709a3 | 624 | } |
| AnnaBridge | 189:f392fc9709a3 | 625 | |
| AnnaBridge | 189:f392fc9709a3 | 626 | /** |
| AnnaBridge | 189:f392fc9709a3 | 627 | * @brief Check if non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode is enabled |
| AnnaBridge | 189:f392fc9709a3 | 628 | * @rmtoll CR DS_EE_KOFF LL_PWR_IsEnabledNVMKeptOff |
| AnnaBridge | 189:f392fc9709a3 | 629 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 630 | */ |
| AnnaBridge | 189:f392fc9709a3 | 631 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledNVMKeptOff(void) |
| AnnaBridge | 189:f392fc9709a3 | 632 | { |
| AnnaBridge | 189:f392fc9709a3 | 633 | return (READ_BIT(PWR->CR, PWR_CR_DSEEKOFF) == (PWR_CR_DSEEKOFF)); |
| AnnaBridge | 189:f392fc9709a3 | 634 | } |
| AnnaBridge | 189:f392fc9709a3 | 635 | |
| AnnaBridge | 189:f392fc9709a3 | 636 | /** |
| AnnaBridge | 189:f392fc9709a3 | 637 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 638 | */ |
| AnnaBridge | 189:f392fc9709a3 | 639 | |
| AnnaBridge | 189:f392fc9709a3 | 640 | /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management |
| AnnaBridge | 189:f392fc9709a3 | 641 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 642 | */ |
| AnnaBridge | 189:f392fc9709a3 | 643 | |
| AnnaBridge | 189:f392fc9709a3 | 644 | /** |
| AnnaBridge | 189:f392fc9709a3 | 645 | * @brief Get Wake-up Flag |
| AnnaBridge | 189:f392fc9709a3 | 646 | * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU |
| AnnaBridge | 189:f392fc9709a3 | 647 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 648 | */ |
| AnnaBridge | 189:f392fc9709a3 | 649 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) |
| AnnaBridge | 189:f392fc9709a3 | 650 | { |
| AnnaBridge | 189:f392fc9709a3 | 651 | return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); |
| AnnaBridge | 189:f392fc9709a3 | 652 | } |
| AnnaBridge | 189:f392fc9709a3 | 653 | |
| AnnaBridge | 189:f392fc9709a3 | 654 | /** |
| AnnaBridge | 189:f392fc9709a3 | 655 | * @brief Get Standby Flag |
| AnnaBridge | 189:f392fc9709a3 | 656 | * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB |
| AnnaBridge | 189:f392fc9709a3 | 657 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 658 | */ |
| AnnaBridge | 189:f392fc9709a3 | 659 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) |
| AnnaBridge | 189:f392fc9709a3 | 660 | { |
| AnnaBridge | 189:f392fc9709a3 | 661 | return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); |
| AnnaBridge | 189:f392fc9709a3 | 662 | } |
| AnnaBridge | 189:f392fc9709a3 | 663 | |
| AnnaBridge | 189:f392fc9709a3 | 664 | #if defined(PWR_PVD_SUPPORT) |
| AnnaBridge | 189:f392fc9709a3 | 665 | /** |
| AnnaBridge | 189:f392fc9709a3 | 666 | * @brief Indicate whether VDD voltage is below the selected PVD threshold |
| AnnaBridge | 189:f392fc9709a3 | 667 | * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO |
| AnnaBridge | 189:f392fc9709a3 | 668 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 669 | */ |
| AnnaBridge | 189:f392fc9709a3 | 670 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) |
| AnnaBridge | 189:f392fc9709a3 | 671 | { |
| AnnaBridge | 189:f392fc9709a3 | 672 | return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); |
| AnnaBridge | 189:f392fc9709a3 | 673 | } |
| AnnaBridge | 189:f392fc9709a3 | 674 | #endif /* PWR_PVD_SUPPORT */ |
| AnnaBridge | 189:f392fc9709a3 | 675 | |
| AnnaBridge | 189:f392fc9709a3 | 676 | #if defined(PWR_CSR_VREFINTRDYF) |
| AnnaBridge | 189:f392fc9709a3 | 677 | /** |
| AnnaBridge | 189:f392fc9709a3 | 678 | * @brief Get Internal Reference VrefInt Flag |
| AnnaBridge | 189:f392fc9709a3 | 679 | * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY |
| AnnaBridge | 189:f392fc9709a3 | 680 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 681 | */ |
| AnnaBridge | 189:f392fc9709a3 | 682 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) |
| AnnaBridge | 189:f392fc9709a3 | 683 | { |
| AnnaBridge | 189:f392fc9709a3 | 684 | return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); |
| AnnaBridge | 189:f392fc9709a3 | 685 | } |
| AnnaBridge | 189:f392fc9709a3 | 686 | #endif /* PWR_CSR_VREFINTRDYF */ |
| AnnaBridge | 189:f392fc9709a3 | 687 | /** |
| AnnaBridge | 189:f392fc9709a3 | 688 | * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level |
| AnnaBridge | 189:f392fc9709a3 | 689 | * @rmtoll CSR VOSF LL_PWR_IsActiveFlag_VOSF |
| AnnaBridge | 189:f392fc9709a3 | 690 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 691 | */ |
| AnnaBridge | 189:f392fc9709a3 | 692 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSF(void) |
| AnnaBridge | 189:f392fc9709a3 | 693 | { |
| AnnaBridge | 189:f392fc9709a3 | 694 | return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS)); |
| AnnaBridge | 189:f392fc9709a3 | 695 | } |
| AnnaBridge | 189:f392fc9709a3 | 696 | /** |
| AnnaBridge | 189:f392fc9709a3 | 697 | * @brief Indicate whether the regulator is ready in main mode or is in low-power mode |
| AnnaBridge | 189:f392fc9709a3 | 698 | * @rmtoll CSR REGLPF LL_PWR_IsActiveFlag_REGLPF |
| AnnaBridge | 189:f392fc9709a3 | 699 | * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. |
| AnnaBridge | 189:f392fc9709a3 | 700 | * @retval State of bit (1 or 0). |
| AnnaBridge | 189:f392fc9709a3 | 701 | */ |
| AnnaBridge | 189:f392fc9709a3 | 702 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) |
| AnnaBridge | 189:f392fc9709a3 | 703 | { |
| AnnaBridge | 189:f392fc9709a3 | 704 | return (READ_BIT(PWR->CSR, PWR_CSR_REGLPF) == (PWR_CSR_REGLPF)); |
| AnnaBridge | 189:f392fc9709a3 | 705 | } |
| AnnaBridge | 189:f392fc9709a3 | 706 | /** |
| AnnaBridge | 189:f392fc9709a3 | 707 | * @brief Clear Standby Flag |
| AnnaBridge | 189:f392fc9709a3 | 708 | * @rmtoll CR CSBF LL_PWR_ClearFlag_SB |
| AnnaBridge | 189:f392fc9709a3 | 709 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 710 | */ |
| AnnaBridge | 189:f392fc9709a3 | 711 | __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) |
| AnnaBridge | 189:f392fc9709a3 | 712 | { |
| AnnaBridge | 189:f392fc9709a3 | 713 | SET_BIT(PWR->CR, PWR_CR_CSBF); |
| AnnaBridge | 189:f392fc9709a3 | 714 | } |
| AnnaBridge | 189:f392fc9709a3 | 715 | |
| AnnaBridge | 189:f392fc9709a3 | 716 | /** |
| AnnaBridge | 189:f392fc9709a3 | 717 | * @brief Clear Wake-up Flags |
| AnnaBridge | 189:f392fc9709a3 | 718 | * @rmtoll CR CWUF LL_PWR_ClearFlag_WU |
| AnnaBridge | 189:f392fc9709a3 | 719 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 720 | */ |
| AnnaBridge | 189:f392fc9709a3 | 721 | __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) |
| AnnaBridge | 189:f392fc9709a3 | 722 | { |
| AnnaBridge | 189:f392fc9709a3 | 723 | SET_BIT(PWR->CR, PWR_CR_CWUF); |
| AnnaBridge | 189:f392fc9709a3 | 724 | } |
| AnnaBridge | 189:f392fc9709a3 | 725 | #if defined(USE_FULL_LL_DRIVER) |
| AnnaBridge | 189:f392fc9709a3 | 726 | /** @defgroup PWR_LL_EF_Init De-initialization function |
| AnnaBridge | 189:f392fc9709a3 | 727 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 728 | */ |
| AnnaBridge | 189:f392fc9709a3 | 729 | ErrorStatus LL_PWR_DeInit(void); |
| AnnaBridge | 189:f392fc9709a3 | 730 | /** |
| AnnaBridge | 189:f392fc9709a3 | 731 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 732 | */ |
| AnnaBridge | 189:f392fc9709a3 | 733 | #endif /* USE_FULL_LL_DRIVER */ |
| AnnaBridge | 189:f392fc9709a3 | 734 | |
| AnnaBridge | 189:f392fc9709a3 | 735 | /** |
| AnnaBridge | 189:f392fc9709a3 | 736 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 737 | */ |
| AnnaBridge | 189:f392fc9709a3 | 738 | |
| AnnaBridge | 189:f392fc9709a3 | 739 | /** |
| AnnaBridge | 189:f392fc9709a3 | 740 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 741 | */ |
| AnnaBridge | 189:f392fc9709a3 | 742 | |
| AnnaBridge | 189:f392fc9709a3 | 743 | /** |
| AnnaBridge | 189:f392fc9709a3 | 744 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 745 | */ |
| AnnaBridge | 189:f392fc9709a3 | 746 | |
| AnnaBridge | 189:f392fc9709a3 | 747 | #endif /* defined(PWR) */ |
| AnnaBridge | 189:f392fc9709a3 | 748 | |
| AnnaBridge | 189:f392fc9709a3 | 749 | /** |
| AnnaBridge | 189:f392fc9709a3 | 750 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 751 | */ |
| AnnaBridge | 189:f392fc9709a3 | 752 | |
| AnnaBridge | 189:f392fc9709a3 | 753 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 754 | } |
| AnnaBridge | 189:f392fc9709a3 | 755 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 756 | |
| AnnaBridge | 189:f392fc9709a3 | 757 | #endif /* __STM32L0xx_LL_PWR_H */ |
| AnnaBridge | 189:f392fc9709a3 | 758 | |
| AnnaBridge | 189:f392fc9709a3 | 759 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
