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cmsis/BUILD/mbed/TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/stm32l0xx_ll_dac.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l0xx_ll_dac.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of DAC LL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L0xx_LL_DAC_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L0xx_LL_DAC_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	45	#include "stm32l0xx.h"
AnnaBridge	189:f392fc9709a3	46
AnnaBridge	189:f392fc9709a3	47	/** @addtogroup STM32L0xx_LL_Driver
AnnaBridge	189:f392fc9709a3	48	* @{
AnnaBridge	189:f392fc9709a3	49	*/
AnnaBridge	189:f392fc9709a3	50
AnnaBridge	189:f392fc9709a3	51	#if defined (DAC1)
AnnaBridge	189:f392fc9709a3	52
AnnaBridge	189:f392fc9709a3	53	/** @defgroup DAC_LL DAC
AnnaBridge	189:f392fc9709a3	54	* @{
AnnaBridge	189:f392fc9709a3	55	*/
AnnaBridge	189:f392fc9709a3	56
AnnaBridge	189:f392fc9709a3	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	59
AnnaBridge	189:f392fc9709a3	60	/* Private constants ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	61	/** @defgroup DAC_LL_Private_Constants DAC Private Constants
AnnaBridge	189:f392fc9709a3	62	* @{
AnnaBridge	189:f392fc9709a3	63	*/
AnnaBridge	189:f392fc9709a3	64
AnnaBridge	189:f392fc9709a3	65	/* Internal masks for DAC channels definition */
AnnaBridge	189:f392fc9709a3	66	/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
AnnaBridge	189:f392fc9709a3	67	/* - channel bits position into register CR */
AnnaBridge	189:f392fc9709a3	68	/* - channel bits position into register SWTRIG */
AnnaBridge	189:f392fc9709a3	69	/* - channel register offset of data holding register DHRx */
AnnaBridge	189:f392fc9709a3	70	/* - channel register offset of data output register DORx */
AnnaBridge	189:f392fc9709a3	71	#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
AnnaBridge	189:f392fc9709a3	72	#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
AnnaBridge	189:f392fc9709a3	73	#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET \| DAC_CR_CH2_BITOFFSET)
AnnaBridge	189:f392fc9709a3	74
AnnaBridge	189:f392fc9709a3	75	#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
AnnaBridge	189:f392fc9709a3	76	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	77	#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
AnnaBridge	189:f392fc9709a3	78	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 \| DAC_SWTR_CH2)
AnnaBridge	189:f392fc9709a3	79	#else
AnnaBridge	189:f392fc9709a3	80	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
AnnaBridge	189:f392fc9709a3	81	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	82
AnnaBridge	189:f392fc9709a3	83	#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
AnnaBridge	189:f392fc9709a3	84	#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
AnnaBridge	189:f392fc9709a3	85	#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
AnnaBridge	189:f392fc9709a3	86	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	87	#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
AnnaBridge	189:f392fc9709a3	88	#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
AnnaBridge	189:f392fc9709a3	89	#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
AnnaBridge	189:f392fc9709a3	90	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	91	#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
AnnaBridge	189:f392fc9709a3	92	#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
AnnaBridge	189:f392fc9709a3	93	#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
AnnaBridge	189:f392fc9709a3	94	#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK \| DAC_REG_DHR12LX_REGOFFSET_MASK \| DAC_REG_DHR8RX_REGOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	95
AnnaBridge	189:f392fc9709a3	96	#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
AnnaBridge	189:f392fc9709a3	97	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	98	#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
AnnaBridge	189:f392fc9709a3	99	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DOR2_REGOFFSET)
AnnaBridge	189:f392fc9709a3	100	#else
AnnaBridge	189:f392fc9709a3	101	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
AnnaBridge	189:f392fc9709a3	102	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	103
AnnaBridge	189:f392fc9709a3	104	#define DAC_REG_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */
AnnaBridge	189:f392fc9709a3	105
AnnaBridge	189:f392fc9709a3	106	#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
AnnaBridge	189:f392fc9709a3	107	#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
AnnaBridge	189:f392fc9709a3	108	#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
AnnaBridge	189:f392fc9709a3	109	#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */
AnnaBridge	189:f392fc9709a3	110
AnnaBridge	189:f392fc9709a3	111	/* DAC registers bits positions */
AnnaBridge	189:f392fc9709a3	112	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	113	#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
AnnaBridge	189:f392fc9709a3	114	#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
AnnaBridge	189:f392fc9709a3	115	#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
AnnaBridge	189:f392fc9709a3	116	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	117
AnnaBridge	189:f392fc9709a3	118	/* Miscellaneous data */
AnnaBridge	189:f392fc9709a3	119	#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
AnnaBridge	189:f392fc9709a3	120
AnnaBridge	189:f392fc9709a3	121	/**
AnnaBridge	189:f392fc9709a3	122	* @}
AnnaBridge	189:f392fc9709a3	123	*/
AnnaBridge	189:f392fc9709a3	124
AnnaBridge	189:f392fc9709a3	125
AnnaBridge	189:f392fc9709a3	126	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	127	/** @defgroup DAC_LL_Private_Macros DAC Private Macros
AnnaBridge	189:f392fc9709a3	128	* @{
AnnaBridge	189:f392fc9709a3	129	*/
AnnaBridge	189:f392fc9709a3	130
AnnaBridge	189:f392fc9709a3	131	/**
AnnaBridge	189:f392fc9709a3	132	* @brief Driver macro reserved for internal use: set a pointer to
AnnaBridge	189:f392fc9709a3	133	* a register from a register basis from which an offset
AnnaBridge	189:f392fc9709a3	134	* is applied.
AnnaBridge	189:f392fc9709a3	135	* @param __REG__ Register basis from which the offset is applied.
AnnaBridge	189:f392fc9709a3	136	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
AnnaBridge	189:f392fc9709a3	137	* @retval Pointer to register address
AnnaBridge	189:f392fc9709a3	138	*/
AnnaBridge	189:f392fc9709a3	139	#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
AnnaBridge	189:f392fc9709a3	140	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
AnnaBridge	189:f392fc9709a3	141
AnnaBridge	189:f392fc9709a3	142	/**
AnnaBridge	189:f392fc9709a3	143	* @}
AnnaBridge	189:f392fc9709a3	144	*/
AnnaBridge	189:f392fc9709a3	145
AnnaBridge	189:f392fc9709a3	146
AnnaBridge	189:f392fc9709a3	147	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	148	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	149	/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
AnnaBridge	189:f392fc9709a3	150	* @{
AnnaBridge	189:f392fc9709a3	151	*/
AnnaBridge	189:f392fc9709a3	152
AnnaBridge	189:f392fc9709a3	153	/**
AnnaBridge	189:f392fc9709a3	154	* @brief Structure definition of some features of DAC instance.
AnnaBridge	189:f392fc9709a3	155	*/
AnnaBridge	189:f392fc9709a3	156	typedef struct
AnnaBridge	189:f392fc9709a3	157	{
AnnaBridge	189:f392fc9709a3	158	uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
AnnaBridge	189:f392fc9709a3	159	This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
AnnaBridge	189:f392fc9709a3	160
AnnaBridge	189:f392fc9709a3	161	This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
AnnaBridge	189:f392fc9709a3	162
AnnaBridge	189:f392fc9709a3	163	uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	164	This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
AnnaBridge	189:f392fc9709a3	165
AnnaBridge	189:f392fc9709a3	166	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
AnnaBridge	189:f392fc9709a3	167
AnnaBridge	189:f392fc9709a3	168	uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	169	If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
AnnaBridge	189:f392fc9709a3	170	If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
AnnaBridge	189:f392fc9709a3	171	@note If waveform automatic generation mode is disabled, this parameter is discarded.
AnnaBridge	189:f392fc9709a3	172
AnnaBridge	189:f392fc9709a3	173	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
AnnaBridge	189:f392fc9709a3	174
AnnaBridge	189:f392fc9709a3	175	uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	176	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
AnnaBridge	189:f392fc9709a3	177
AnnaBridge	189:f392fc9709a3	178	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
AnnaBridge	189:f392fc9709a3	179
AnnaBridge	189:f392fc9709a3	180	} LL_DAC_InitTypeDef;
AnnaBridge	189:f392fc9709a3	181
AnnaBridge	189:f392fc9709a3	182	/**
AnnaBridge	189:f392fc9709a3	183	* @}
AnnaBridge	189:f392fc9709a3	184	*/
AnnaBridge	189:f392fc9709a3	185	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	186
AnnaBridge	189:f392fc9709a3	187	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	188	/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
AnnaBridge	189:f392fc9709a3	189	* @{
AnnaBridge	189:f392fc9709a3	190	*/
AnnaBridge	189:f392fc9709a3	191
AnnaBridge	189:f392fc9709a3	192	/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
AnnaBridge	189:f392fc9709a3	193	* @brief Flags defines which can be used with LL_DAC_ReadReg function
AnnaBridge	189:f392fc9709a3	194	* @{
AnnaBridge	189:f392fc9709a3	195	*/
AnnaBridge	189:f392fc9709a3	196	/* DAC channel 1 flags */
AnnaBridge	189:f392fc9709a3	197	#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /!< DAC channel 1 flag DMA underrun /
AnnaBridge	189:f392fc9709a3	198
AnnaBridge	189:f392fc9709a3	199	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	200	/* DAC channel 2 flags */
AnnaBridge	189:f392fc9709a3	201	#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /!< DAC channel 2 flag DMA underrun /
AnnaBridge	189:f392fc9709a3	202	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	203	/**
AnnaBridge	189:f392fc9709a3	204	* @}
AnnaBridge	189:f392fc9709a3	205	*/
AnnaBridge	189:f392fc9709a3	206
AnnaBridge	189:f392fc9709a3	207	/** @defgroup DAC_LL_EC_IT DAC interruptions
AnnaBridge	189:f392fc9709a3	208	* @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
AnnaBridge	189:f392fc9709a3	209	* @{
AnnaBridge	189:f392fc9709a3	210	*/
AnnaBridge	189:f392fc9709a3	211	#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /!< DAC channel 1 interruption DMA underrun /
AnnaBridge	189:f392fc9709a3	212	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	213	#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /!< DAC channel 2 interruption DMA underrun /
AnnaBridge	189:f392fc9709a3	214	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	215	/**
AnnaBridge	189:f392fc9709a3	216	* @}
AnnaBridge	189:f392fc9709a3	217	*/
AnnaBridge	189:f392fc9709a3	218
AnnaBridge	189:f392fc9709a3	219	/** @defgroup DAC_LL_EC_CHANNEL DAC channels
AnnaBridge	189:f392fc9709a3	220	* @{
AnnaBridge	189:f392fc9709a3	221	*/
AnnaBridge	189:f392fc9709a3	222	#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DHR12R1_REGOFFSET \| DAC_REG_DHR12L1_REGOFFSET \| DAC_REG_DHR8R1_REGOFFSET \| DAC_CR_CH1_BITOFFSET \| DAC_SWTR_CH1) /!< DAC channel 1 /
AnnaBridge	189:f392fc9709a3	223	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	224	#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET \| DAC_REG_DHR12R2_REGOFFSET \| DAC_REG_DHR12L2_REGOFFSET \| DAC_REG_DHR8R2_REGOFFSET \| DAC_CR_CH2_BITOFFSET \| DAC_SWTR_CH2) /!< DAC channel 2 /
AnnaBridge	189:f392fc9709a3	225	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	226	/**
AnnaBridge	189:f392fc9709a3	227	* @}
AnnaBridge	189:f392fc9709a3	228	*/
AnnaBridge	189:f392fc9709a3	229
AnnaBridge	189:f392fc9709a3	230	/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
AnnaBridge	189:f392fc9709a3	231	* @{
AnnaBridge	189:f392fc9709a3	232	*/
AnnaBridge	189:f392fc9709a3	233	#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger internal (SW start) /
AnnaBridge	189:f392fc9709a3	234	#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /!< DAC channel conversion trigger from external IP: TIM2 TRGO. /
AnnaBridge	189:f392fc9709a3	235	#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM3 TRGO. /
AnnaBridge	189:f392fc9709a3	236	#define LL_DAC_TRIG_EXT_TIM3_CH3 ( DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: TIM3 CH3 event. /
AnnaBridge	189:f392fc9709a3	237	#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /!< DAC channel conversion trigger from external IP: TIM6 TRGO. /
AnnaBridge	189:f392fc9709a3	238	#define LL_DAC_TRIG_EXT_TIM7_TRGO (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM7 TRGO. /
AnnaBridge	189:f392fc9709a3	239	#define LL_DAC_TRIG_EXT_TIM21_TRGO ( DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM21 TRGO. /
AnnaBridge	189:f392fc9709a3	240	#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: external interrupt line 9. /
AnnaBridge	189:f392fc9709a3	241	/**
AnnaBridge	189:f392fc9709a3	242	* @}
AnnaBridge	189:f392fc9709a3	243	*/
AnnaBridge	189:f392fc9709a3	244
AnnaBridge	189:f392fc9709a3	245	/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
AnnaBridge	189:f392fc9709a3	246	* @{
AnnaBridge	189:f392fc9709a3	247	*/
AnnaBridge	189:f392fc9709a3	248	#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /!< DAC channel wave auto generation mode disabled. /
AnnaBridge	189:f392fc9709a3	249	#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /!< DAC channel wave auto generation mode enabled, set generated noise waveform. /
AnnaBridge	189:f392fc9709a3	250	#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /!< DAC channel wave auto generation mode enabled, set generated triangle waveform. /
AnnaBridge	189:f392fc9709a3	251	/**
AnnaBridge	189:f392fc9709a3	252	* @}
AnnaBridge	189:f392fc9709a3	253	*/
AnnaBridge	189:f392fc9709a3	254
AnnaBridge	189:f392fc9709a3	255	/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
AnnaBridge	189:f392fc9709a3	256	* @{
AnnaBridge	189:f392fc9709a3	257	*/
AnnaBridge	189:f392fc9709a3	258	#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	259	#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	260	#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	261	#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	262	#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	263	#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	264	#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	265	#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	266	#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	267	#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	268	#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	269	#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	270	/**
AnnaBridge	189:f392fc9709a3	271	* @}
AnnaBridge	189:f392fc9709a3	272	*/
AnnaBridge	189:f392fc9709a3	273
AnnaBridge	189:f392fc9709a3	274	/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
AnnaBridge	189:f392fc9709a3	275	* @{
AnnaBridge	189:f392fc9709a3	276	*/
AnnaBridge	189:f392fc9709a3	277	#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	278	#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	279	#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	280	#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	281	#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	282	#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	283	#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	284	#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	285	#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	286	#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	287	#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	288	#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	189:f392fc9709a3	289	/**
AnnaBridge	189:f392fc9709a3	290	* @}
AnnaBridge	189:f392fc9709a3	291	*/
AnnaBridge	189:f392fc9709a3	292
AnnaBridge	189:f392fc9709a3	293	/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
AnnaBridge	189:f392fc9709a3	294	* @{
AnnaBridge	189:f392fc9709a3	295	*/
AnnaBridge	189:f392fc9709a3	296	#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption /
AnnaBridge	189:f392fc9709a3	297	#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption /
AnnaBridge	189:f392fc9709a3	298	/**
AnnaBridge	189:f392fc9709a3	299	* @}
AnnaBridge	189:f392fc9709a3	300	*/
AnnaBridge	189:f392fc9709a3	301
AnnaBridge	189:f392fc9709a3	302
AnnaBridge	189:f392fc9709a3	303	/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
AnnaBridge	189:f392fc9709a3	304	* @{
AnnaBridge	189:f392fc9709a3	305	*/
AnnaBridge	189:f392fc9709a3	306	#define LL_DAC_RESOLUTION_12B 0x00000000U /!< DAC channel resolution 12 bits /
AnnaBridge	189:f392fc9709a3	307	#define LL_DAC_RESOLUTION_8B 0x00000002U /!< DAC channel resolution 8 bits /
AnnaBridge	189:f392fc9709a3	308	/**
AnnaBridge	189:f392fc9709a3	309	* @}
AnnaBridge	189:f392fc9709a3	310	*/
AnnaBridge	189:f392fc9709a3	311
AnnaBridge	189:f392fc9709a3	312	/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
AnnaBridge	189:f392fc9709a3	313	* @{
AnnaBridge	189:f392fc9709a3	314	*/
AnnaBridge	189:f392fc9709a3	315	/* List of DAC registers intended to be used (most commonly) with */
AnnaBridge	189:f392fc9709a3	316	/* DMA transfer. */
AnnaBridge	189:f392fc9709a3	317	/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
AnnaBridge	189:f392fc9709a3	318	#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 12 bits right aligned /
AnnaBridge	189:f392fc9709a3	319	#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 12 bits left aligned /
AnnaBridge	189:f392fc9709a3	320	#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 8 bits right aligned /
AnnaBridge	189:f392fc9709a3	321	/**
AnnaBridge	189:f392fc9709a3	322	* @}
AnnaBridge	189:f392fc9709a3	323	*/
AnnaBridge	189:f392fc9709a3	324
AnnaBridge	189:f392fc9709a3	325	/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
AnnaBridge	189:f392fc9709a3	326	* @note Only DAC IP HW delays are defined in DAC LL driver driver,
AnnaBridge	189:f392fc9709a3	327	* not timeout values.
AnnaBridge	189:f392fc9709a3	328	* For details on delays values, refer to descriptions in source code
AnnaBridge	189:f392fc9709a3	329	* above each literal definition.
AnnaBridge	189:f392fc9709a3	330	* @{
AnnaBridge	189:f392fc9709a3	331	*/
AnnaBridge	189:f392fc9709a3	332
AnnaBridge	189:f392fc9709a3	333	/* Delay for DAC channel voltage settling time from DAC channel startup */
AnnaBridge	189:f392fc9709a3	334	/* (transition from disable to enable). */
AnnaBridge	189:f392fc9709a3	335	/* Note: DAC channel startup time depends on board application environment: */
AnnaBridge	189:f392fc9709a3	336	/* impedance connected to DAC channel output. */
AnnaBridge	189:f392fc9709a3	337	/* The delay below is specified under conditions: */
AnnaBridge	189:f392fc9709a3	338	/* - voltage maximum transition (lowest to highest value) */
AnnaBridge	189:f392fc9709a3	339	/* - until voltage reaches final value +-1LSB */
AnnaBridge	189:f392fc9709a3	340	/* - DAC channel output buffer enabled */
AnnaBridge	189:f392fc9709a3	341	/* - load impedance of 5kOhm (min), 50pF (max) */
AnnaBridge	189:f392fc9709a3	342	/* Literal set to maximum value (refer to device datasheet, */
AnnaBridge	189:f392fc9709a3	343	/* parameter "tWAKEUP"). */
AnnaBridge	189:f392fc9709a3	344	/* Unit: us */
AnnaBridge	189:f392fc9709a3	345	#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) /
AnnaBridge	189:f392fc9709a3	346
AnnaBridge	189:f392fc9709a3	347	/* Delay for DAC channel voltage settling time. */
AnnaBridge	189:f392fc9709a3	348	/* Note: DAC channel startup time depends on board application environment: */
AnnaBridge	189:f392fc9709a3	349	/* impedance connected to DAC channel output. */
AnnaBridge	189:f392fc9709a3	350	/* The delay below is specified under conditions: */
AnnaBridge	189:f392fc9709a3	351	/* - voltage maximum transition (lowest to highest value) */
AnnaBridge	189:f392fc9709a3	352	/* - until voltage reaches final value +-1LSB */
AnnaBridge	189:f392fc9709a3	353	/* - DAC channel output buffer enabled */
AnnaBridge	189:f392fc9709a3	354	/* - load impedance of 5kOhm min, 50pF max */
AnnaBridge	189:f392fc9709a3	355	/* Literal set to maximum value (refer to device datasheet, */
AnnaBridge	189:f392fc9709a3	356	/* parameter "tSETTLING"). */
AnnaBridge	189:f392fc9709a3	357	/* Unit: us */
AnnaBridge	189:f392fc9709a3	358	#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /!< Delay for DAC channel voltage settling time /
AnnaBridge	189:f392fc9709a3	359	/**
AnnaBridge	189:f392fc9709a3	360	* @}
AnnaBridge	189:f392fc9709a3	361	*/
AnnaBridge	189:f392fc9709a3	362
AnnaBridge	189:f392fc9709a3	363	/**
AnnaBridge	189:f392fc9709a3	364	* @}
AnnaBridge	189:f392fc9709a3	365	*/
AnnaBridge	189:f392fc9709a3	366
AnnaBridge	189:f392fc9709a3	367	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	368	/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
AnnaBridge	189:f392fc9709a3	369	* @{
AnnaBridge	189:f392fc9709a3	370	*/
AnnaBridge	189:f392fc9709a3	371
AnnaBridge	189:f392fc9709a3	372	/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
AnnaBridge	189:f392fc9709a3	373	* @{
AnnaBridge	189:f392fc9709a3	374	*/
AnnaBridge	189:f392fc9709a3	375
AnnaBridge	189:f392fc9709a3	376	/**
AnnaBridge	189:f392fc9709a3	377	* @brief Write a value in DAC register
AnnaBridge	189:f392fc9709a3	378	* @param __INSTANCE__ DAC Instance
AnnaBridge	189:f392fc9709a3	379	* @param __REG__ Register to be written
AnnaBridge	189:f392fc9709a3	380	* @param __VALUE__ Value to be written in the register
AnnaBridge	189:f392fc9709a3	381	* @retval None
AnnaBridge	189:f392fc9709a3	382	*/
AnnaBridge	189:f392fc9709a3	383	#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	189:f392fc9709a3	384
AnnaBridge	189:f392fc9709a3	385	/**
AnnaBridge	189:f392fc9709a3	386	* @brief Read a value in DAC register
AnnaBridge	189:f392fc9709a3	387	* @param __INSTANCE__ DAC Instance
AnnaBridge	189:f392fc9709a3	388	* @param __REG__ Register to be read
AnnaBridge	189:f392fc9709a3	389	* @retval Register value
AnnaBridge	189:f392fc9709a3	390	*/
AnnaBridge	189:f392fc9709a3	391	#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	189:f392fc9709a3	392
AnnaBridge	189:f392fc9709a3	393	/**
AnnaBridge	189:f392fc9709a3	394	* @}
AnnaBridge	189:f392fc9709a3	395	*/
AnnaBridge	189:f392fc9709a3	396
AnnaBridge	189:f392fc9709a3	397	/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
AnnaBridge	189:f392fc9709a3	398	* @{
AnnaBridge	189:f392fc9709a3	399	*/
AnnaBridge	189:f392fc9709a3	400
AnnaBridge	189:f392fc9709a3	401	/**
AnnaBridge	189:f392fc9709a3	402	* @brief Helper macro to get DAC channel number in decimal format
AnnaBridge	189:f392fc9709a3	403	* from literals LL_DAC_CHANNEL_x.
AnnaBridge	189:f392fc9709a3	404	* Example:
AnnaBridge	189:f392fc9709a3	405	* __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
AnnaBridge	189:f392fc9709a3	406	* will return decimal number "1".
AnnaBridge	189:f392fc9709a3	407	* @note The input can be a value from functions where a channel
AnnaBridge	189:f392fc9709a3	408	* number is returned.
AnnaBridge	189:f392fc9709a3	409	* @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	410	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	411	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	412	*
AnnaBridge	189:f392fc9709a3	413	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	414	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	415	* @retval 1...2 (value "2" depending on DAC channel 2 availability)
AnnaBridge	189:f392fc9709a3	416	*/
AnnaBridge	189:f392fc9709a3	417	#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
AnnaBridge	189:f392fc9709a3	418	((__CHANNEL__) & DAC_SWTR_CHX_MASK)
AnnaBridge	189:f392fc9709a3	419
AnnaBridge	189:f392fc9709a3	420	/**
AnnaBridge	189:f392fc9709a3	421	* @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
AnnaBridge	189:f392fc9709a3	422	* from number in decimal format.
AnnaBridge	189:f392fc9709a3	423	* Example:
AnnaBridge	189:f392fc9709a3	424	* __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
AnnaBridge	189:f392fc9709a3	425	* will return a data equivalent to "LL_DAC_CHANNEL_1".
AnnaBridge	189:f392fc9709a3	426	* @note If the input parameter does not correspond to a DAC channel,
AnnaBridge	189:f392fc9709a3	427	* this macro returns value '0'.
AnnaBridge	189:f392fc9709a3	428	* @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
AnnaBridge	189:f392fc9709a3	429	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	430	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	431	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	432	*
AnnaBridge	189:f392fc9709a3	433	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	434	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	435	*/
AnnaBridge	189:f392fc9709a3	436	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	437	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
AnnaBridge	189:f392fc9709a3	438	(((__DECIMAL_NB__) == 1U) \
AnnaBridge	189:f392fc9709a3	439	? ( \
AnnaBridge	189:f392fc9709a3	440	LL_DAC_CHANNEL_1 \
AnnaBridge	189:f392fc9709a3	441	) \
AnnaBridge	189:f392fc9709a3	442	: \
AnnaBridge	189:f392fc9709a3	443	(((__DECIMAL_NB__) == 2U) \
AnnaBridge	189:f392fc9709a3	444	? ( \
AnnaBridge	189:f392fc9709a3	445	LL_DAC_CHANNEL_2 \
AnnaBridge	189:f392fc9709a3	446	) \
AnnaBridge	189:f392fc9709a3	447	: \
AnnaBridge	189:f392fc9709a3	448	( \
AnnaBridge	189:f392fc9709a3	449	0 \
AnnaBridge	189:f392fc9709a3	450	) \
AnnaBridge	189:f392fc9709a3	451	) \
AnnaBridge	189:f392fc9709a3	452	)
AnnaBridge	189:f392fc9709a3	453	#else
AnnaBridge	189:f392fc9709a3	454	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
AnnaBridge	189:f392fc9709a3	455	(((__DECIMAL_NB__) == 1U) \
AnnaBridge	189:f392fc9709a3	456	? ( \
AnnaBridge	189:f392fc9709a3	457	LL_DAC_CHANNEL_1 \
AnnaBridge	189:f392fc9709a3	458	) \
AnnaBridge	189:f392fc9709a3	459	: \
AnnaBridge	189:f392fc9709a3	460	( \
AnnaBridge	189:f392fc9709a3	461	0 \
AnnaBridge	189:f392fc9709a3	462	) \
AnnaBridge	189:f392fc9709a3	463	)
AnnaBridge	189:f392fc9709a3	464	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	465
AnnaBridge	189:f392fc9709a3	466	/**
AnnaBridge	189:f392fc9709a3	467	* @brief Helper macro to define the DAC conversion data full-scale digital
AnnaBridge	189:f392fc9709a3	468	* value corresponding to the selected DAC resolution.
AnnaBridge	189:f392fc9709a3	469	* @note DAC conversion data full-scale corresponds to voltage range
AnnaBridge	189:f392fc9709a3	470	* determined by analog voltage references Vref+ and Vref-
AnnaBridge	189:f392fc9709a3	471	* (refer to reference manual).
AnnaBridge	189:f392fc9709a3	472	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	473	* @arg @ref LL_DAC_RESOLUTION_12B
AnnaBridge	189:f392fc9709a3	474	* @arg @ref LL_DAC_RESOLUTION_8B
AnnaBridge	189:f392fc9709a3	475	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
AnnaBridge	189:f392fc9709a3	476	*/
AnnaBridge	189:f392fc9709a3	477	#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
AnnaBridge	189:f392fc9709a3	478	((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
AnnaBridge	189:f392fc9709a3	479
AnnaBridge	189:f392fc9709a3	480	/**
AnnaBridge	189:f392fc9709a3	481	* @brief Helper macro to calculate the DAC conversion data (unit: digital
AnnaBridge	189:f392fc9709a3	482	* value) corresponding to a voltage (unit: mVolt).
AnnaBridge	189:f392fc9709a3	483	* @note This helper macro is intended to provide input data in voltage
AnnaBridge	189:f392fc9709a3	484	* rather than digital value,
AnnaBridge	189:f392fc9709a3	485	* to be used with LL DAC functions such as
AnnaBridge	189:f392fc9709a3	486	* @ref LL_DAC_ConvertData12RightAligned().
AnnaBridge	189:f392fc9709a3	487	* @note Analog reference voltage (Vref+) must be either known from
AnnaBridge	189:f392fc9709a3	488	* user board environment or can be calculated using ADC measurement
AnnaBridge	189:f392fc9709a3	489	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
AnnaBridge	189:f392fc9709a3	490	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
AnnaBridge	189:f392fc9709a3	491	* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
AnnaBridge	189:f392fc9709a3	492	* (unit: mVolt).
AnnaBridge	189:f392fc9709a3	493	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	494	* @arg @ref LL_DAC_RESOLUTION_12B
AnnaBridge	189:f392fc9709a3	495	* @arg @ref LL_DAC_RESOLUTION_8B
AnnaBridge	189:f392fc9709a3	496	* @retval DAC conversion data (unit: digital value)
AnnaBridge	189:f392fc9709a3	497	*/
AnnaBridge	189:f392fc9709a3	498	#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
AnnaBridge	189:f392fc9709a3	499	__DAC_VOLTAGE__,\
AnnaBridge	189:f392fc9709a3	500	__DAC_RESOLUTION__) \
AnnaBridge	189:f392fc9709a3	501	((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
AnnaBridge	189:f392fc9709a3	502	/ (__VREFANALOG_VOLTAGE__) \
AnnaBridge	189:f392fc9709a3	503	)
AnnaBridge	189:f392fc9709a3	504
AnnaBridge	189:f392fc9709a3	505	/**
AnnaBridge	189:f392fc9709a3	506	* @}
AnnaBridge	189:f392fc9709a3	507	*/
AnnaBridge	189:f392fc9709a3	508
AnnaBridge	189:f392fc9709a3	509	/**
AnnaBridge	189:f392fc9709a3	510	* @}
AnnaBridge	189:f392fc9709a3	511	*/
AnnaBridge	189:f392fc9709a3	512
AnnaBridge	189:f392fc9709a3	513
AnnaBridge	189:f392fc9709a3	514	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	515	/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
AnnaBridge	189:f392fc9709a3	516	* @{
AnnaBridge	189:f392fc9709a3	517	*/
AnnaBridge	189:f392fc9709a3	518	/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
AnnaBridge	189:f392fc9709a3	519	* @{
AnnaBridge	189:f392fc9709a3	520	*/
AnnaBridge	189:f392fc9709a3	521
AnnaBridge	189:f392fc9709a3	522	/**
AnnaBridge	189:f392fc9709a3	523	* @brief Set the conversion trigger source for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	524	* @note For conversion trigger source to be effective, DAC trigger
AnnaBridge	189:f392fc9709a3	525	* must be enabled using function @ref LL_DAC_EnableTrigger().
AnnaBridge	189:f392fc9709a3	526	* @note To set conversion trigger source, DAC channel must be disabled.
AnnaBridge	189:f392fc9709a3	527	* Otherwise, the setting is discarded.
AnnaBridge	189:f392fc9709a3	528	* @note Availability of parameters of trigger sources from timer
AnnaBridge	189:f392fc9709a3	529	* depends on timers availability on the selected device.
AnnaBridge	189:f392fc9709a3	530	* @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
AnnaBridge	189:f392fc9709a3	531	* CR TSEL2 LL_DAC_SetTriggerSource
AnnaBridge	189:f392fc9709a3	532	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	533	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	534	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	535	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	536	*
AnnaBridge	189:f392fc9709a3	537	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	538	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	539	* @param TriggerSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	540	* @arg @ref LL_DAC_TRIG_SOFTWARE
AnnaBridge	189:f392fc9709a3	541	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
AnnaBridge	189:f392fc9709a3	542	* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
AnnaBridge	189:f392fc9709a3	543	* @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3
AnnaBridge	189:f392fc9709a3	544	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
AnnaBridge	189:f392fc9709a3	545	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
AnnaBridge	189:f392fc9709a3	546	* @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO
AnnaBridge	189:f392fc9709a3	547	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
AnnaBridge	189:f392fc9709a3	548	* @retval None
AnnaBridge	189:f392fc9709a3	549	*/
AnnaBridge	189:f392fc9709a3	550	__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
AnnaBridge	189:f392fc9709a3	551	{
AnnaBridge	189:f392fc9709a3	552	MODIFY_REG(DACx->CR,
AnnaBridge	189:f392fc9709a3	553	DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	554	TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	555	}
AnnaBridge	189:f392fc9709a3	556
AnnaBridge	189:f392fc9709a3	557	/**
AnnaBridge	189:f392fc9709a3	558	* @brief Get the conversion trigger source for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	559	* @note For conversion trigger source to be effective, DAC trigger
AnnaBridge	189:f392fc9709a3	560	* must be enabled using function @ref LL_DAC_EnableTrigger().
AnnaBridge	189:f392fc9709a3	561	* @note Availability of parameters of trigger sources from timer
AnnaBridge	189:f392fc9709a3	562	* depends on timers availability on the selected device.
AnnaBridge	189:f392fc9709a3	563	* @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
AnnaBridge	189:f392fc9709a3	564	* CR TSEL2 LL_DAC_GetTriggerSource
AnnaBridge	189:f392fc9709a3	565	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	566	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	567	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	568	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	569	*
AnnaBridge	189:f392fc9709a3	570	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	571	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	572	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	573	* @arg @ref LL_DAC_TRIG_SOFTWARE
AnnaBridge	189:f392fc9709a3	574	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
AnnaBridge	189:f392fc9709a3	575	* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
AnnaBridge	189:f392fc9709a3	576	* @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3
AnnaBridge	189:f392fc9709a3	577	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
AnnaBridge	189:f392fc9709a3	578	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
AnnaBridge	189:f392fc9709a3	579	* @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO
AnnaBridge	189:f392fc9709a3	580	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
AnnaBridge	189:f392fc9709a3	581	*/
AnnaBridge	189:f392fc9709a3	582	__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	583	{
AnnaBridge	189:f392fc9709a3	584	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	585	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	586	);
AnnaBridge	189:f392fc9709a3	587	}
AnnaBridge	189:f392fc9709a3	588
AnnaBridge	189:f392fc9709a3	589	/**
AnnaBridge	189:f392fc9709a3	590	* @brief Set the waveform automatic generation mode
AnnaBridge	189:f392fc9709a3	591	* for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	592	* @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
AnnaBridge	189:f392fc9709a3	593	* CR WAVE2 LL_DAC_SetWaveAutoGeneration
AnnaBridge	189:f392fc9709a3	594	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	595	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	596	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	597	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	598	*
AnnaBridge	189:f392fc9709a3	599	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	600	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	601	* @param WaveAutoGeneration This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	602	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
AnnaBridge	189:f392fc9709a3	603	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
AnnaBridge	189:f392fc9709a3	604	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
AnnaBridge	189:f392fc9709a3	605	* @retval None
AnnaBridge	189:f392fc9709a3	606	*/
AnnaBridge	189:f392fc9709a3	607	__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
AnnaBridge	189:f392fc9709a3	608	{
AnnaBridge	189:f392fc9709a3	609	MODIFY_REG(DACx->CR,
AnnaBridge	189:f392fc9709a3	610	DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	611	WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	612	}
AnnaBridge	189:f392fc9709a3	613
AnnaBridge	189:f392fc9709a3	614	/**
AnnaBridge	189:f392fc9709a3	615	* @brief Get the waveform automatic generation mode
AnnaBridge	189:f392fc9709a3	616	* for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	617	* @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
AnnaBridge	189:f392fc9709a3	618	* CR WAVE2 LL_DAC_GetWaveAutoGeneration
AnnaBridge	189:f392fc9709a3	619	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	620	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	621	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	622	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	623	*
AnnaBridge	189:f392fc9709a3	624	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	625	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	626	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	627	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
AnnaBridge	189:f392fc9709a3	628	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
AnnaBridge	189:f392fc9709a3	629	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
AnnaBridge	189:f392fc9709a3	630	*/
AnnaBridge	189:f392fc9709a3	631	__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	632	{
AnnaBridge	189:f392fc9709a3	633	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	634	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	635	);
AnnaBridge	189:f392fc9709a3	636	}
AnnaBridge	189:f392fc9709a3	637
AnnaBridge	189:f392fc9709a3	638	/**
AnnaBridge	189:f392fc9709a3	639	* @brief Set the noise waveform generation for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	640	* Noise mode and parameters LFSR (linear feedback shift register).
AnnaBridge	189:f392fc9709a3	641	* @note For wave generation to be effective, DAC channel
AnnaBridge	189:f392fc9709a3	642	* wave generation mode must be enabled using
AnnaBridge	189:f392fc9709a3	643	* function @ref LL_DAC_SetWaveAutoGeneration().
AnnaBridge	189:f392fc9709a3	644	* @note This setting can be set when the selected DAC channel is disabled
AnnaBridge	189:f392fc9709a3	645	* (otherwise, the setting operation is ignored).
AnnaBridge	189:f392fc9709a3	646	* @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
AnnaBridge	189:f392fc9709a3	647	* CR MAMP2 LL_DAC_SetWaveNoiseLFSR
AnnaBridge	189:f392fc9709a3	648	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	649	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	650	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	651	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	652	*
AnnaBridge	189:f392fc9709a3	653	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	654	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	655	* @param NoiseLFSRMask This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	656	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
AnnaBridge	189:f392fc9709a3	657	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
AnnaBridge	189:f392fc9709a3	658	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
AnnaBridge	189:f392fc9709a3	659	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
AnnaBridge	189:f392fc9709a3	660	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
AnnaBridge	189:f392fc9709a3	661	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
AnnaBridge	189:f392fc9709a3	662	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
AnnaBridge	189:f392fc9709a3	663	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
AnnaBridge	189:f392fc9709a3	664	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
AnnaBridge	189:f392fc9709a3	665	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
AnnaBridge	189:f392fc9709a3	666	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
AnnaBridge	189:f392fc9709a3	667	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
AnnaBridge	189:f392fc9709a3	668	* @retval None
AnnaBridge	189:f392fc9709a3	669	*/
AnnaBridge	189:f392fc9709a3	670	__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
AnnaBridge	189:f392fc9709a3	671	{
AnnaBridge	189:f392fc9709a3	672	MODIFY_REG(DACx->CR,
AnnaBridge	189:f392fc9709a3	673	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	674	NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	675	}
AnnaBridge	189:f392fc9709a3	676
AnnaBridge	189:f392fc9709a3	677	/**
AnnaBridge	189:f392fc9709a3	678	* @brief Set the noise waveform generation for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	679	* Noise mode and parameters LFSR (linear feedback shift register).
AnnaBridge	189:f392fc9709a3	680	* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
AnnaBridge	189:f392fc9709a3	681	* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
AnnaBridge	189:f392fc9709a3	682	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	683	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	684	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	685	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	686	*
AnnaBridge	189:f392fc9709a3	687	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	688	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	689	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	690	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
AnnaBridge	189:f392fc9709a3	691	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
AnnaBridge	189:f392fc9709a3	692	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
AnnaBridge	189:f392fc9709a3	693	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
AnnaBridge	189:f392fc9709a3	694	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
AnnaBridge	189:f392fc9709a3	695	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
AnnaBridge	189:f392fc9709a3	696	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
AnnaBridge	189:f392fc9709a3	697	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
AnnaBridge	189:f392fc9709a3	698	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
AnnaBridge	189:f392fc9709a3	699	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
AnnaBridge	189:f392fc9709a3	700	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
AnnaBridge	189:f392fc9709a3	701	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
AnnaBridge	189:f392fc9709a3	702	*/
AnnaBridge	189:f392fc9709a3	703	__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	704	{
AnnaBridge	189:f392fc9709a3	705	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	706	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	707	);
AnnaBridge	189:f392fc9709a3	708	}
AnnaBridge	189:f392fc9709a3	709
AnnaBridge	189:f392fc9709a3	710	/**
AnnaBridge	189:f392fc9709a3	711	* @brief Set the triangle waveform generation for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	712	* triangle mode and amplitude.
AnnaBridge	189:f392fc9709a3	713	* @note For wave generation to be effective, DAC channel
AnnaBridge	189:f392fc9709a3	714	* wave generation mode must be enabled using
AnnaBridge	189:f392fc9709a3	715	* function @ref LL_DAC_SetWaveAutoGeneration().
AnnaBridge	189:f392fc9709a3	716	* @note This setting can be set when the selected DAC channel is disabled
AnnaBridge	189:f392fc9709a3	717	* (otherwise, the setting operation is ignored).
AnnaBridge	189:f392fc9709a3	718	* @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
AnnaBridge	189:f392fc9709a3	719	* CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
AnnaBridge	189:f392fc9709a3	720	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	721	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	722	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	723	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	724	*
AnnaBridge	189:f392fc9709a3	725	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	726	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	727	* @param TriangleAmplitude This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	728	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
AnnaBridge	189:f392fc9709a3	729	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
AnnaBridge	189:f392fc9709a3	730	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
AnnaBridge	189:f392fc9709a3	731	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
AnnaBridge	189:f392fc9709a3	732	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
AnnaBridge	189:f392fc9709a3	733	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
AnnaBridge	189:f392fc9709a3	734	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
AnnaBridge	189:f392fc9709a3	735	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
AnnaBridge	189:f392fc9709a3	736	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
AnnaBridge	189:f392fc9709a3	737	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
AnnaBridge	189:f392fc9709a3	738	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
AnnaBridge	189:f392fc9709a3	739	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
AnnaBridge	189:f392fc9709a3	740	* @retval None
AnnaBridge	189:f392fc9709a3	741	*/
AnnaBridge	189:f392fc9709a3	742	__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
AnnaBridge	189:f392fc9709a3	743	{
AnnaBridge	189:f392fc9709a3	744	MODIFY_REG(DACx->CR,
AnnaBridge	189:f392fc9709a3	745	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	746	TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	747	}
AnnaBridge	189:f392fc9709a3	748
AnnaBridge	189:f392fc9709a3	749	/**
AnnaBridge	189:f392fc9709a3	750	* @brief Set the triangle waveform generation for the selected DAC channel:
AnnaBridge	189:f392fc9709a3	751	* triangle mode and amplitude.
AnnaBridge	189:f392fc9709a3	752	* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
AnnaBridge	189:f392fc9709a3	753	* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
AnnaBridge	189:f392fc9709a3	754	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	755	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	756	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	757	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	758	*
AnnaBridge	189:f392fc9709a3	759	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	760	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	761	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	762	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
AnnaBridge	189:f392fc9709a3	763	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
AnnaBridge	189:f392fc9709a3	764	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
AnnaBridge	189:f392fc9709a3	765	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
AnnaBridge	189:f392fc9709a3	766	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
AnnaBridge	189:f392fc9709a3	767	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
AnnaBridge	189:f392fc9709a3	768	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
AnnaBridge	189:f392fc9709a3	769	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
AnnaBridge	189:f392fc9709a3	770	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
AnnaBridge	189:f392fc9709a3	771	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
AnnaBridge	189:f392fc9709a3	772	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
AnnaBridge	189:f392fc9709a3	773	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
AnnaBridge	189:f392fc9709a3	774	*/
AnnaBridge	189:f392fc9709a3	775	__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	776	{
AnnaBridge	189:f392fc9709a3	777	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	778	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	779	);
AnnaBridge	189:f392fc9709a3	780	}
AnnaBridge	189:f392fc9709a3	781
AnnaBridge	189:f392fc9709a3	782	/**
AnnaBridge	189:f392fc9709a3	783	* @brief Set the output buffer for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	784	* @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
AnnaBridge	189:f392fc9709a3	785	* CR BOFF2 LL_DAC_SetOutputBuffer
AnnaBridge	189:f392fc9709a3	786	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	787	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	788	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	789	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	790	*
AnnaBridge	189:f392fc9709a3	791	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	792	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	793	* @param OutputBuffer This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	794	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
AnnaBridge	189:f392fc9709a3	795	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
AnnaBridge	189:f392fc9709a3	796	* @retval None
AnnaBridge	189:f392fc9709a3	797	*/
AnnaBridge	189:f392fc9709a3	798	__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
AnnaBridge	189:f392fc9709a3	799	{
AnnaBridge	189:f392fc9709a3	800	MODIFY_REG(DACx->CR,
AnnaBridge	189:f392fc9709a3	801	DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	189:f392fc9709a3	802	OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	803	}
AnnaBridge	189:f392fc9709a3	804
AnnaBridge	189:f392fc9709a3	805	/**
AnnaBridge	189:f392fc9709a3	806	* @brief Get the output buffer state for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	807	* @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
AnnaBridge	189:f392fc9709a3	808	* CR BOFF2 LL_DAC_GetOutputBuffer
AnnaBridge	189:f392fc9709a3	809	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	810	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	811	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	812	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	813	*
AnnaBridge	189:f392fc9709a3	814	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	815	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	816	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	817	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
AnnaBridge	189:f392fc9709a3	818	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
AnnaBridge	189:f392fc9709a3	819	*/
AnnaBridge	189:f392fc9709a3	820	__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	821	{
AnnaBridge	189:f392fc9709a3	822	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	823	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	189:f392fc9709a3	824	);
AnnaBridge	189:f392fc9709a3	825	}
AnnaBridge	189:f392fc9709a3	826
AnnaBridge	189:f392fc9709a3	827	/**
AnnaBridge	189:f392fc9709a3	828	* @}
AnnaBridge	189:f392fc9709a3	829	*/
AnnaBridge	189:f392fc9709a3	830
AnnaBridge	189:f392fc9709a3	831	/** @defgroup DAC_LL_EF_DMA_Management DMA Management
AnnaBridge	189:f392fc9709a3	832	* @{
AnnaBridge	189:f392fc9709a3	833	*/
AnnaBridge	189:f392fc9709a3	834
AnnaBridge	189:f392fc9709a3	835	/**
AnnaBridge	189:f392fc9709a3	836	* @brief Enable DAC DMA transfer request of the selected channel.
AnnaBridge	189:f392fc9709a3	837	* @note To configure DMA source address (peripheral address),
AnnaBridge	189:f392fc9709a3	838	* use function @ref LL_DAC_DMA_GetRegAddr().
AnnaBridge	189:f392fc9709a3	839	* @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
AnnaBridge	189:f392fc9709a3	840	* CR DMAEN2 LL_DAC_EnableDMAReq
AnnaBridge	189:f392fc9709a3	841	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	842	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	843	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	844	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	845	*
AnnaBridge	189:f392fc9709a3	846	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	847	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	848	* @retval None
AnnaBridge	189:f392fc9709a3	849	*/
AnnaBridge	189:f392fc9709a3	850	__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	851	{
AnnaBridge	189:f392fc9709a3	852	SET_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	853	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	854	}
AnnaBridge	189:f392fc9709a3	855
AnnaBridge	189:f392fc9709a3	856	/**
AnnaBridge	189:f392fc9709a3	857	* @brief Disable DAC DMA transfer request of the selected channel.
AnnaBridge	189:f392fc9709a3	858	* @note To configure DMA source address (peripheral address),
AnnaBridge	189:f392fc9709a3	859	* use function @ref LL_DAC_DMA_GetRegAddr().
AnnaBridge	189:f392fc9709a3	860	* @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
AnnaBridge	189:f392fc9709a3	861	* CR DMAEN2 LL_DAC_DisableDMAReq
AnnaBridge	189:f392fc9709a3	862	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	863	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	864	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	865	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	866	*
AnnaBridge	189:f392fc9709a3	867	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	868	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	869	* @retval None
AnnaBridge	189:f392fc9709a3	870	*/
AnnaBridge	189:f392fc9709a3	871	__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	872	{
AnnaBridge	189:f392fc9709a3	873	CLEAR_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	874	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	875	}
AnnaBridge	189:f392fc9709a3	876
AnnaBridge	189:f392fc9709a3	877	/**
AnnaBridge	189:f392fc9709a3	878	* @brief Get DAC DMA transfer request state of the selected channel.
AnnaBridge	189:f392fc9709a3	879	* (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
AnnaBridge	189:f392fc9709a3	880	* @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
AnnaBridge	189:f392fc9709a3	881	* CR DMAEN2 LL_DAC_IsDMAReqEnabled
AnnaBridge	189:f392fc9709a3	882	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	883	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	884	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	885	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	886	*
AnnaBridge	189:f392fc9709a3	887	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	888	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	889	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	890	*/
AnnaBridge	189:f392fc9709a3	891	__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	892	{
AnnaBridge	189:f392fc9709a3	893	return (READ_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	894	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	895	== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
AnnaBridge	189:f392fc9709a3	896	}
AnnaBridge	189:f392fc9709a3	897
AnnaBridge	189:f392fc9709a3	898	/**
AnnaBridge	189:f392fc9709a3	899	* @brief Function to help to configure DMA transfer to DAC: retrieve the
AnnaBridge	189:f392fc9709a3	900	* DAC register address from DAC instance and a list of DAC registers
AnnaBridge	189:f392fc9709a3	901	* intended to be used (most commonly) with DMA transfer.
AnnaBridge	189:f392fc9709a3	902	* @note These DAC registers are data holding registers:
AnnaBridge	189:f392fc9709a3	903	* when DAC conversion is requested, DAC generates a DMA transfer
AnnaBridge	189:f392fc9709a3	904	* request to have data available in DAC data holding registers.
AnnaBridge	189:f392fc9709a3	905	* @note This macro is intended to be used with LL DMA driver, refer to
AnnaBridge	189:f392fc9709a3	906	* function "LL_DMA_ConfigAddresses()".
AnnaBridge	189:f392fc9709a3	907	* Example:
AnnaBridge	189:f392fc9709a3	908	* LL_DMA_ConfigAddresses(DMA1,
AnnaBridge	189:f392fc9709a3	909	* LL_DMA_CHANNEL_1,
AnnaBridge	189:f392fc9709a3	910	* (uint32_t)&< array or variable >,
AnnaBridge	189:f392fc9709a3	911	* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
AnnaBridge	189:f392fc9709a3	912	* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
AnnaBridge	189:f392fc9709a3	913	* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	189:f392fc9709a3	914	* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	189:f392fc9709a3	915	* DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	189:f392fc9709a3	916	* DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	189:f392fc9709a3	917	* DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	189:f392fc9709a3	918	* DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
AnnaBridge	189:f392fc9709a3	919	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	920	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	921	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	922	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	923	*
AnnaBridge	189:f392fc9709a3	924	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	925	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	926	* @param Register This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	927	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
AnnaBridge	189:f392fc9709a3	928	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
AnnaBridge	189:f392fc9709a3	929	* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
AnnaBridge	189:f392fc9709a3	930	* @retval DAC register address
AnnaBridge	189:f392fc9709a3	931	*/
AnnaBridge	189:f392fc9709a3	932	__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
AnnaBridge	189:f392fc9709a3	933	{
AnnaBridge	189:f392fc9709a3	934	/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
AnnaBridge	189:f392fc9709a3	935	/* DAC channel selected. */
AnnaBridge	189:f392fc9709a3	936	return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> Register) & DAC_REG_REGOFFSET_MASK_POSBIT0))));
AnnaBridge	189:f392fc9709a3	937	}
AnnaBridge	189:f392fc9709a3	938	/**
AnnaBridge	189:f392fc9709a3	939	* @}
AnnaBridge	189:f392fc9709a3	940	*/
AnnaBridge	189:f392fc9709a3	941
AnnaBridge	189:f392fc9709a3	942	/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
AnnaBridge	189:f392fc9709a3	943	* @{
AnnaBridge	189:f392fc9709a3	944	*/
AnnaBridge	189:f392fc9709a3	945
AnnaBridge	189:f392fc9709a3	946	/**
AnnaBridge	189:f392fc9709a3	947	* @brief Enable DAC selected channel.
AnnaBridge	189:f392fc9709a3	948	* @rmtoll CR EN1 LL_DAC_Enable\n
AnnaBridge	189:f392fc9709a3	949	* CR EN2 LL_DAC_Enable
AnnaBridge	189:f392fc9709a3	950	* @note After enable from off state, DAC channel requires a delay
AnnaBridge	189:f392fc9709a3	951	* for output voltage to reach accuracy +/- 1 LSB.
AnnaBridge	189:f392fc9709a3	952	* Refer to device datasheet, parameter "tWAKEUP".
AnnaBridge	189:f392fc9709a3	953	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	954	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	955	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	956	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	957	*
AnnaBridge	189:f392fc9709a3	958	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	959	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	960	* @retval None
AnnaBridge	189:f392fc9709a3	961	*/
AnnaBridge	189:f392fc9709a3	962	__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	963	{
AnnaBridge	189:f392fc9709a3	964	SET_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	965	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	966	}
AnnaBridge	189:f392fc9709a3	967
AnnaBridge	189:f392fc9709a3	968	/**
AnnaBridge	189:f392fc9709a3	969	* @brief Disable DAC selected channel.
AnnaBridge	189:f392fc9709a3	970	* @rmtoll CR EN1 LL_DAC_Disable\n
AnnaBridge	189:f392fc9709a3	971	* CR EN2 LL_DAC_Disable
AnnaBridge	189:f392fc9709a3	972	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	973	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	974	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	975	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	976	*
AnnaBridge	189:f392fc9709a3	977	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	978	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	979	* @retval None
AnnaBridge	189:f392fc9709a3	980	*/
AnnaBridge	189:f392fc9709a3	981	__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	982	{
AnnaBridge	189:f392fc9709a3	983	CLEAR_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	984	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	985	}
AnnaBridge	189:f392fc9709a3	986
AnnaBridge	189:f392fc9709a3	987	/**
AnnaBridge	189:f392fc9709a3	988	* @brief Get DAC enable state of the selected channel.
AnnaBridge	189:f392fc9709a3	989	* (0: DAC channel is disabled, 1: DAC channel is enabled)
AnnaBridge	189:f392fc9709a3	990	* @rmtoll CR EN1 LL_DAC_IsEnabled\n
AnnaBridge	189:f392fc9709a3	991	* CR EN2 LL_DAC_IsEnabled
AnnaBridge	189:f392fc9709a3	992	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	993	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	994	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	995	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	996	*
AnnaBridge	189:f392fc9709a3	997	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	998	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	999	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1000	*/
AnnaBridge	189:f392fc9709a3	1001	__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1002	{
AnnaBridge	189:f392fc9709a3	1003	return (READ_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	1004	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	1005	== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
AnnaBridge	189:f392fc9709a3	1006	}
AnnaBridge	189:f392fc9709a3	1007
AnnaBridge	189:f392fc9709a3	1008	/**
AnnaBridge	189:f392fc9709a3	1009	* @brief Enable DAC trigger of the selected channel.
AnnaBridge	189:f392fc9709a3	1010	* @note - If DAC trigger is disabled, DAC conversion is performed
AnnaBridge	189:f392fc9709a3	1011	* automatically once the data holding register is updated,
AnnaBridge	189:f392fc9709a3	1012	* using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
AnnaBridge	189:f392fc9709a3	1013	* @ref LL_DAC_ConvertData12RightAligned(), ...
AnnaBridge	189:f392fc9709a3	1014	* - If DAC trigger is enabled, DAC conversion is performed
AnnaBridge	189:f392fc9709a3	1015	* only when a hardware of software trigger event is occurring.
AnnaBridge	189:f392fc9709a3	1016	* Select trigger source using
AnnaBridge	189:f392fc9709a3	1017	* function @ref LL_DAC_SetTriggerSource().
AnnaBridge	189:f392fc9709a3	1018	* @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
AnnaBridge	189:f392fc9709a3	1019	* CR TEN2 LL_DAC_EnableTrigger
AnnaBridge	189:f392fc9709a3	1020	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1021	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1022	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1023	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1024	*
AnnaBridge	189:f392fc9709a3	1025	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1026	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1027	* @retval None
AnnaBridge	189:f392fc9709a3	1028	*/
AnnaBridge	189:f392fc9709a3	1029	__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1030	{
AnnaBridge	189:f392fc9709a3	1031	SET_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	1032	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1033	}
AnnaBridge	189:f392fc9709a3	1034
AnnaBridge	189:f392fc9709a3	1035	/**
AnnaBridge	189:f392fc9709a3	1036	* @brief Disable DAC trigger of the selected channel.
AnnaBridge	189:f392fc9709a3	1037	* @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
AnnaBridge	189:f392fc9709a3	1038	* CR TEN2 LL_DAC_DisableTrigger
AnnaBridge	189:f392fc9709a3	1039	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1040	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1041	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1042	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1043	*
AnnaBridge	189:f392fc9709a3	1044	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1045	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1046	* @retval None
AnnaBridge	189:f392fc9709a3	1047	*/
AnnaBridge	189:f392fc9709a3	1048	__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1049	{
AnnaBridge	189:f392fc9709a3	1050	CLEAR_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	1051	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	189:f392fc9709a3	1052	}
AnnaBridge	189:f392fc9709a3	1053
AnnaBridge	189:f392fc9709a3	1054	/**
AnnaBridge	189:f392fc9709a3	1055	* @brief Get DAC trigger state of the selected channel.
AnnaBridge	189:f392fc9709a3	1056	* (0: DAC trigger is disabled, 1: DAC trigger is enabled)
AnnaBridge	189:f392fc9709a3	1057	* @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
AnnaBridge	189:f392fc9709a3	1058	* CR TEN2 LL_DAC_IsTriggerEnabled
AnnaBridge	189:f392fc9709a3	1059	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1060	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1061	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1062	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1063	*
AnnaBridge	189:f392fc9709a3	1064	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1065	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1066	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1067	*/
AnnaBridge	189:f392fc9709a3	1068	__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1069	{
AnnaBridge	189:f392fc9709a3	1070	return (READ_BIT(DACx->CR,
AnnaBridge	189:f392fc9709a3	1071	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	189:f392fc9709a3	1072	== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
AnnaBridge	189:f392fc9709a3	1073	}
AnnaBridge	189:f392fc9709a3	1074
AnnaBridge	189:f392fc9709a3	1075	/**
AnnaBridge	189:f392fc9709a3	1076	* @brief Trig DAC conversion by software for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1077	* @note Preliminarily, DAC trigger must be set to software trigger
AnnaBridge	189:f392fc9709a3	1078	* using function @ref LL_DAC_SetTriggerSource()
AnnaBridge	189:f392fc9709a3	1079	* with parameter "LL_DAC_TRIGGER_SOFTWARE".
AnnaBridge	189:f392fc9709a3	1080	* and DAC trigger must be enabled using
AnnaBridge	189:f392fc9709a3	1081	* function @ref LL_DAC_EnableTrigger().
AnnaBridge	189:f392fc9709a3	1082	* @note For devices featuring DAC with 2 channels: this function
AnnaBridge	189:f392fc9709a3	1083	* can perform a SW start of both DAC channels simultaneously.
AnnaBridge	189:f392fc9709a3	1084	* Two channels can be selected as parameter.
AnnaBridge	189:f392fc9709a3	1085	* Example: (LL_DAC_CHANNEL_1 \| LL_DAC_CHANNEL_2)
AnnaBridge	189:f392fc9709a3	1086	* @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
AnnaBridge	189:f392fc9709a3	1087	* SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
AnnaBridge	189:f392fc9709a3	1088	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1089	* @param DAC_Channel This parameter can a combination of the following values:
AnnaBridge	189:f392fc9709a3	1090	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1091	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1092	*
AnnaBridge	189:f392fc9709a3	1093	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1094	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1095	* @retval None
AnnaBridge	189:f392fc9709a3	1096	*/
AnnaBridge	189:f392fc9709a3	1097	__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1098	{
AnnaBridge	189:f392fc9709a3	1099	SET_BIT(DACx->SWTRIGR,
AnnaBridge	189:f392fc9709a3	1100	(DAC_Channel & DAC_SWTR_CHX_MASK));
AnnaBridge	189:f392fc9709a3	1101	}
AnnaBridge	189:f392fc9709a3	1102
AnnaBridge	189:f392fc9709a3	1103	/**
AnnaBridge	189:f392fc9709a3	1104	* @brief Set the data to be loaded in the data holding register
AnnaBridge	189:f392fc9709a3	1105	* in format 12 bits left alignment (LSB aligned on bit 0),
AnnaBridge	189:f392fc9709a3	1106	* for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1107	* @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
AnnaBridge	189:f392fc9709a3	1108	* DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
AnnaBridge	189:f392fc9709a3	1109	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1110	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1111	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1112	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1113	*
AnnaBridge	189:f392fc9709a3	1114	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1115	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1116	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1117	* @retval None
AnnaBridge	189:f392fc9709a3	1118	*/
AnnaBridge	189:f392fc9709a3	1119	__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge	189:f392fc9709a3	1120	{
AnnaBridge	189:f392fc9709a3	1121	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
AnnaBridge	189:f392fc9709a3	1122
AnnaBridge	189:f392fc9709a3	1123	MODIFY_REG(*preg,
AnnaBridge	189:f392fc9709a3	1124	DAC_DHR12R1_DACC1DHR,
AnnaBridge	189:f392fc9709a3	1125	Data);
AnnaBridge	189:f392fc9709a3	1126	}
AnnaBridge	189:f392fc9709a3	1127
AnnaBridge	189:f392fc9709a3	1128	/**
AnnaBridge	189:f392fc9709a3	1129	* @brief Set the data to be loaded in the data holding register
AnnaBridge	189:f392fc9709a3	1130	* in format 12 bits left alignment (MSB aligned on bit 15),
AnnaBridge	189:f392fc9709a3	1131	* for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1132	* @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
AnnaBridge	189:f392fc9709a3	1133	* DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
AnnaBridge	189:f392fc9709a3	1134	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1135	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1136	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1137	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1138	*
AnnaBridge	189:f392fc9709a3	1139	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1140	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1141	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1142	* @retval None
AnnaBridge	189:f392fc9709a3	1143	*/
AnnaBridge	189:f392fc9709a3	1144	__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge	189:f392fc9709a3	1145	{
AnnaBridge	189:f392fc9709a3	1146	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
AnnaBridge	189:f392fc9709a3	1147
AnnaBridge	189:f392fc9709a3	1148	MODIFY_REG(*preg,
AnnaBridge	189:f392fc9709a3	1149	DAC_DHR12L1_DACC1DHR,
AnnaBridge	189:f392fc9709a3	1150	Data);
AnnaBridge	189:f392fc9709a3	1151	}
AnnaBridge	189:f392fc9709a3	1152
AnnaBridge	189:f392fc9709a3	1153	/**
AnnaBridge	189:f392fc9709a3	1154	* @brief Set the data to be loaded in the data holding register
AnnaBridge	189:f392fc9709a3	1155	* in format 8 bits left alignment (LSB aligned on bit 0),
AnnaBridge	189:f392fc9709a3	1156	* for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1157	* @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
AnnaBridge	189:f392fc9709a3	1158	* DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
AnnaBridge	189:f392fc9709a3	1159	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1160	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1161	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1162	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1163	*
AnnaBridge	189:f392fc9709a3	1164	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1165	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1166	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	1167	* @retval None
AnnaBridge	189:f392fc9709a3	1168	*/
AnnaBridge	189:f392fc9709a3	1169	__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge	189:f392fc9709a3	1170	{
AnnaBridge	189:f392fc9709a3	1171	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
AnnaBridge	189:f392fc9709a3	1172
AnnaBridge	189:f392fc9709a3	1173	MODIFY_REG(*preg,
AnnaBridge	189:f392fc9709a3	1174	DAC_DHR8R1_DACC1DHR,
AnnaBridge	189:f392fc9709a3	1175	Data);
AnnaBridge	189:f392fc9709a3	1176	}
AnnaBridge	189:f392fc9709a3	1177
AnnaBridge	189:f392fc9709a3	1178	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1179	/**
AnnaBridge	189:f392fc9709a3	1180	* @brief Set the data to be loaded in the data holding register
AnnaBridge	189:f392fc9709a3	1181	* in format 12 bits left alignment (LSB aligned on bit 0),
AnnaBridge	189:f392fc9709a3	1182	* for both DAC channels.
AnnaBridge	189:f392fc9709a3	1183	* @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
AnnaBridge	189:f392fc9709a3	1184	* DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
AnnaBridge	189:f392fc9709a3	1185	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1186	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1187	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1188	* @retval None
AnnaBridge	189:f392fc9709a3	1189	*/
AnnaBridge	189:f392fc9709a3	1190	__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge	189:f392fc9709a3	1191	{
AnnaBridge	189:f392fc9709a3	1192	MODIFY_REG(DACx->DHR12RD,
AnnaBridge	189:f392fc9709a3	1193	(DAC_DHR12RD_DACC2DHR \| DAC_DHR12RD_DACC1DHR),
AnnaBridge	189:f392fc9709a3	1194	((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
AnnaBridge	189:f392fc9709a3	1195	}
AnnaBridge	189:f392fc9709a3	1196
AnnaBridge	189:f392fc9709a3	1197	/**
AnnaBridge	189:f392fc9709a3	1198	* @brief Set the data to be loaded in the data holding register
AnnaBridge	189:f392fc9709a3	1199	* in format 12 bits left alignment (MSB aligned on bit 15),
AnnaBridge	189:f392fc9709a3	1200	* for both DAC channels.
AnnaBridge	189:f392fc9709a3	1201	* @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
AnnaBridge	189:f392fc9709a3	1202	* DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
AnnaBridge	189:f392fc9709a3	1203	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1204	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1205	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1206	* @retval None
AnnaBridge	189:f392fc9709a3	1207	*/
AnnaBridge	189:f392fc9709a3	1208	__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge	189:f392fc9709a3	1209	{
AnnaBridge	189:f392fc9709a3	1210	/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
AnnaBridge	189:f392fc9709a3	1211	/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
AnnaBridge	189:f392fc9709a3	1212	/* the 4 LSB must be taken into account for the shift value. */
AnnaBridge	189:f392fc9709a3	1213	MODIFY_REG(DACx->DHR12LD,
AnnaBridge	189:f392fc9709a3	1214	(DAC_DHR12LD_DACC2DHR \| DAC_DHR12LD_DACC1DHR),
AnnaBridge	189:f392fc9709a3	1215	((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) \| DataChannel1));
AnnaBridge	189:f392fc9709a3	1216	}
AnnaBridge	189:f392fc9709a3	1217
AnnaBridge	189:f392fc9709a3	1218	/**
AnnaBridge	189:f392fc9709a3	1219	* @brief Set the data to be loaded in the data holding register
AnnaBridge	189:f392fc9709a3	1220	* in format 8 bits left alignment (LSB aligned on bit 0),
AnnaBridge	189:f392fc9709a3	1221	* for both DAC channels.
AnnaBridge	189:f392fc9709a3	1222	* @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
AnnaBridge	189:f392fc9709a3	1223	* DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
AnnaBridge	189:f392fc9709a3	1224	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1225	* @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	1226	* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	189:f392fc9709a3	1227	* @retval None
AnnaBridge	189:f392fc9709a3	1228	*/
AnnaBridge	189:f392fc9709a3	1229	__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge	189:f392fc9709a3	1230	{
AnnaBridge	189:f392fc9709a3	1231	MODIFY_REG(DACx->DHR8RD,
AnnaBridge	189:f392fc9709a3	1232	(DAC_DHR8RD_DACC2DHR \| DAC_DHR8RD_DACC1DHR),
AnnaBridge	189:f392fc9709a3	1233	((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
AnnaBridge	189:f392fc9709a3	1234	}
AnnaBridge	189:f392fc9709a3	1235
AnnaBridge	189:f392fc9709a3	1236	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1237	/**
AnnaBridge	189:f392fc9709a3	1238	* @brief Retrieve output data currently generated for the selected DAC channel.
AnnaBridge	189:f392fc9709a3	1239	* @note Whatever alignment and resolution settings
AnnaBridge	189:f392fc9709a3	1240	* (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
AnnaBridge	189:f392fc9709a3	1241	* @ref LL_DAC_ConvertData12RightAligned(), ...),
AnnaBridge	189:f392fc9709a3	1242	* output data format is 12 bits right aligned (LSB aligned on bit 0).
AnnaBridge	189:f392fc9709a3	1243	* @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
AnnaBridge	189:f392fc9709a3	1244	* DOR2 DACC2DOR LL_DAC_RetrieveOutputData
AnnaBridge	189:f392fc9709a3	1245	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1246	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1247	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	189:f392fc9709a3	1248	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	189:f392fc9709a3	1249	*
AnnaBridge	189:f392fc9709a3	1250	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	189:f392fc9709a3	1251	* Refer to device datasheet for channels availability.
AnnaBridge	189:f392fc9709a3	1252	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	189:f392fc9709a3	1253	*/
AnnaBridge	189:f392fc9709a3	1254	__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	189:f392fc9709a3	1255	{
AnnaBridge	189:f392fc9709a3	1256	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
AnnaBridge	189:f392fc9709a3	1257
AnnaBridge	189:f392fc9709a3	1258	return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
AnnaBridge	189:f392fc9709a3	1259	}
AnnaBridge	189:f392fc9709a3	1260
AnnaBridge	189:f392fc9709a3	1261	/**
AnnaBridge	189:f392fc9709a3	1262	* @}
AnnaBridge	189:f392fc9709a3	1263	*/
AnnaBridge	189:f392fc9709a3	1264
AnnaBridge	189:f392fc9709a3	1265	/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	189:f392fc9709a3	1266	* @{
AnnaBridge	189:f392fc9709a3	1267	*/
AnnaBridge	189:f392fc9709a3	1268	/**
AnnaBridge	189:f392fc9709a3	1269	* @brief Get DAC underrun flag for DAC channel 1
AnnaBridge	189:f392fc9709a3	1270	* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
AnnaBridge	189:f392fc9709a3	1271	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1272	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1273	*/
AnnaBridge	189:f392fc9709a3	1274	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1275	{
AnnaBridge	189:f392fc9709a3	1276	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
AnnaBridge	189:f392fc9709a3	1277	}
AnnaBridge	189:f392fc9709a3	1278
AnnaBridge	189:f392fc9709a3	1279	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1280	/**
AnnaBridge	189:f392fc9709a3	1281	* @brief Get DAC underrun flag for DAC channel 2
AnnaBridge	189:f392fc9709a3	1282	* @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
AnnaBridge	189:f392fc9709a3	1283	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1284	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1285	*/
AnnaBridge	189:f392fc9709a3	1286	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1287	{
AnnaBridge	189:f392fc9709a3	1288	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
AnnaBridge	189:f392fc9709a3	1289	}
AnnaBridge	189:f392fc9709a3	1290	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1291
AnnaBridge	189:f392fc9709a3	1292	/**
AnnaBridge	189:f392fc9709a3	1293	* @brief Clear DAC underrun flag for DAC channel 1
AnnaBridge	189:f392fc9709a3	1294	* @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
AnnaBridge	189:f392fc9709a3	1295	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1296	* @retval None
AnnaBridge	189:f392fc9709a3	1297	*/
AnnaBridge	189:f392fc9709a3	1298	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1299	{
AnnaBridge	189:f392fc9709a3	1300	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
AnnaBridge	189:f392fc9709a3	1301	}
AnnaBridge	189:f392fc9709a3	1302
AnnaBridge	189:f392fc9709a3	1303	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1304	/**
AnnaBridge	189:f392fc9709a3	1305	* @brief Clear DAC underrun flag for DAC channel 2
AnnaBridge	189:f392fc9709a3	1306	* @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
AnnaBridge	189:f392fc9709a3	1307	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1308	* @retval None
AnnaBridge	189:f392fc9709a3	1309	*/
AnnaBridge	189:f392fc9709a3	1310	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1311	{
AnnaBridge	189:f392fc9709a3	1312	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
AnnaBridge	189:f392fc9709a3	1313	}
AnnaBridge	189:f392fc9709a3	1314	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1315
AnnaBridge	189:f392fc9709a3	1316	/**
AnnaBridge	189:f392fc9709a3	1317	* @}
AnnaBridge	189:f392fc9709a3	1318	*/
AnnaBridge	189:f392fc9709a3	1319
AnnaBridge	189:f392fc9709a3	1320	/** @defgroup DAC_LL_EF_IT_Management IT management
AnnaBridge	189:f392fc9709a3	1321	* @{
AnnaBridge	189:f392fc9709a3	1322	*/
AnnaBridge	189:f392fc9709a3	1323
AnnaBridge	189:f392fc9709a3	1324	/**
AnnaBridge	189:f392fc9709a3	1325	* @brief Enable DMA underrun interrupt for DAC channel 1
AnnaBridge	189:f392fc9709a3	1326	* @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
AnnaBridge	189:f392fc9709a3	1327	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1328	* @retval None
AnnaBridge	189:f392fc9709a3	1329	*/
AnnaBridge	189:f392fc9709a3	1330	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1331	{
AnnaBridge	189:f392fc9709a3	1332	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
AnnaBridge	189:f392fc9709a3	1333	}
AnnaBridge	189:f392fc9709a3	1334
AnnaBridge	189:f392fc9709a3	1335	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1336	/**
AnnaBridge	189:f392fc9709a3	1337	* @brief Enable DMA underrun interrupt for DAC channel 2
AnnaBridge	189:f392fc9709a3	1338	* @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
AnnaBridge	189:f392fc9709a3	1339	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1340	* @retval None
AnnaBridge	189:f392fc9709a3	1341	*/
AnnaBridge	189:f392fc9709a3	1342	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1343	{
AnnaBridge	189:f392fc9709a3	1344	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
AnnaBridge	189:f392fc9709a3	1345	}
AnnaBridge	189:f392fc9709a3	1346	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1347
AnnaBridge	189:f392fc9709a3	1348	/**
AnnaBridge	189:f392fc9709a3	1349	* @brief Disable DMA underrun interrupt for DAC channel 1
AnnaBridge	189:f392fc9709a3	1350	* @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
AnnaBridge	189:f392fc9709a3	1351	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1352	* @retval None
AnnaBridge	189:f392fc9709a3	1353	*/
AnnaBridge	189:f392fc9709a3	1354	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1355	{
AnnaBridge	189:f392fc9709a3	1356	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
AnnaBridge	189:f392fc9709a3	1357	}
AnnaBridge	189:f392fc9709a3	1358
AnnaBridge	189:f392fc9709a3	1359	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1360	/**
AnnaBridge	189:f392fc9709a3	1361	* @brief Disable DMA underrun interrupt for DAC channel 2
AnnaBridge	189:f392fc9709a3	1362	* @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
AnnaBridge	189:f392fc9709a3	1363	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1364	* @retval None
AnnaBridge	189:f392fc9709a3	1365	*/
AnnaBridge	189:f392fc9709a3	1366	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1367	{
AnnaBridge	189:f392fc9709a3	1368	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
AnnaBridge	189:f392fc9709a3	1369	}
AnnaBridge	189:f392fc9709a3	1370	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1371
AnnaBridge	189:f392fc9709a3	1372	/**
AnnaBridge	189:f392fc9709a3	1373	* @brief Get DMA underrun interrupt for DAC channel 1
AnnaBridge	189:f392fc9709a3	1374	* @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
AnnaBridge	189:f392fc9709a3	1375	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1376	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1377	*/
AnnaBridge	189:f392fc9709a3	1378	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1379	{
AnnaBridge	189:f392fc9709a3	1380	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
AnnaBridge	189:f392fc9709a3	1381	}
AnnaBridge	189:f392fc9709a3	1382
AnnaBridge	189:f392fc9709a3	1383	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	189:f392fc9709a3	1384	/**
AnnaBridge	189:f392fc9709a3	1385	* @brief Get DMA underrun interrupt for DAC channel 2
AnnaBridge	189:f392fc9709a3	1386	* @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
AnnaBridge	189:f392fc9709a3	1387	* @param DACx DAC instance
AnnaBridge	189:f392fc9709a3	1388	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1389	*/
AnnaBridge	189:f392fc9709a3	1390	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	189:f392fc9709a3	1391	{
AnnaBridge	189:f392fc9709a3	1392	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
AnnaBridge	189:f392fc9709a3	1393	}
AnnaBridge	189:f392fc9709a3	1394	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	189:f392fc9709a3	1395
AnnaBridge	189:f392fc9709a3	1396	/**
AnnaBridge	189:f392fc9709a3	1397	* @}
AnnaBridge	189:f392fc9709a3	1398	*/
AnnaBridge	189:f392fc9709a3	1399
AnnaBridge	189:f392fc9709a3	1400	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	1401	/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	189:f392fc9709a3	1402	* @{
AnnaBridge	189:f392fc9709a3	1403	*/
AnnaBridge	189:f392fc9709a3	1404
AnnaBridge	189:f392fc9709a3	1405	ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
AnnaBridge	189:f392fc9709a3	1406	ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
AnnaBridge	189:f392fc9709a3	1407	void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
AnnaBridge	189:f392fc9709a3	1408
AnnaBridge	189:f392fc9709a3	1409	/**
AnnaBridge	189:f392fc9709a3	1410	* @}
AnnaBridge	189:f392fc9709a3	1411	*/
AnnaBridge	189:f392fc9709a3	1412	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	1413
AnnaBridge	189:f392fc9709a3	1414	/**
AnnaBridge	189:f392fc9709a3	1415	* @}
AnnaBridge	189:f392fc9709a3	1416	*/
AnnaBridge	189:f392fc9709a3	1417
AnnaBridge	189:f392fc9709a3	1418	/**
AnnaBridge	189:f392fc9709a3	1419	* @}
AnnaBridge	189:f392fc9709a3	1420	*/
AnnaBridge	189:f392fc9709a3	1421
AnnaBridge	189:f392fc9709a3	1422	#endif /* DAC1 */
AnnaBridge	189:f392fc9709a3	1423
AnnaBridge	189:f392fc9709a3	1424	/**
AnnaBridge	189:f392fc9709a3	1425	* @}
AnnaBridge	189:f392fc9709a3	1426	*/
AnnaBridge	189:f392fc9709a3	1427
AnnaBridge	189:f392fc9709a3	1428	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	1429	}
AnnaBridge	189:f392fc9709a3	1430	#endif
AnnaBridge	189:f392fc9709a3	1431
AnnaBridge	189:f392fc9709a3	1432	#endif /* __STM32L0xx_LL_DAC_H */
AnnaBridge	189:f392fc9709a3	1433
AnnaBridge	189:f392fc9709a3	1434	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/