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cmsis/BUILD/mbed/TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/stm32l0xx_ll_cortex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /**
AnnaBridge 189:f392fc9709a3 2 ******************************************************************************
AnnaBridge 189:f392fc9709a3 3 * @file stm32l0xx_ll_cortex.h
AnnaBridge 189:f392fc9709a3 4 * @author MCD Application Team
AnnaBridge 189:f392fc9709a3 5 * @brief Header file of CORTEX LL module.
AnnaBridge 189:f392fc9709a3 6 @verbatim
AnnaBridge 189:f392fc9709a3 7 ==============================================================================
AnnaBridge 189:f392fc9709a3 8 ##### How to use this driver #####
AnnaBridge 189:f392fc9709a3 9 ==============================================================================
AnnaBridge 189:f392fc9709a3 10 [..]
AnnaBridge 189:f392fc9709a3 11 The LL CORTEX driver contains a set of generic APIs that can be
AnnaBridge 189:f392fc9709a3 12 used by user:
AnnaBridge 189:f392fc9709a3 13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
AnnaBridge 189:f392fc9709a3 14 functions
AnnaBridge 189:f392fc9709a3 15 (+) Low power mode configuration (SCB register of Cortex-MCU)
AnnaBridge 189:f392fc9709a3 16 (+) MPU API to configure and enable regions
AnnaBridge 189:f392fc9709a3 17 (+) API to access to MCU info (CPUID register)
AnnaBridge 189:f392fc9709a3 18
AnnaBridge 189:f392fc9709a3 19 @endverbatim
AnnaBridge 189:f392fc9709a3 20 ******************************************************************************
AnnaBridge 189:f392fc9709a3 21 * @attention
AnnaBridge 189:f392fc9709a3 22 *
AnnaBridge 189:f392fc9709a3 23 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 189:f392fc9709a3 24 *
AnnaBridge 189:f392fc9709a3 25 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 26 * are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 27 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 189:f392fc9709a3 28 * this list of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 29 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 189:f392fc9709a3 30 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 189:f392fc9709a3 31 * and/or other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 32 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 189:f392fc9709a3 33 * may be used to endorse or promote products derived from this software
AnnaBridge 189:f392fc9709a3 34 * without specific prior written permission.
AnnaBridge 189:f392fc9709a3 35 *
AnnaBridge 189:f392fc9709a3 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 189:f392fc9709a3 37 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 189:f392fc9709a3 38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 189:f392fc9709a3 39 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 189:f392fc9709a3 40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 189:f392fc9709a3 41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 189:f392fc9709a3 42 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 189:f392fc9709a3 43 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 189:f392fc9709a3 44 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 189:f392fc9709a3 45 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 46 *
AnnaBridge 189:f392fc9709a3 47 ******************************************************************************
AnnaBridge 189:f392fc9709a3 48 */
AnnaBridge 189:f392fc9709a3 49
AnnaBridge 189:f392fc9709a3 50 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 189:f392fc9709a3 51 #ifndef __STM32L0xx_LL_CORTEX_H
AnnaBridge 189:f392fc9709a3 52 #define __STM32L0xx_LL_CORTEX_H
AnnaBridge 189:f392fc9709a3 53
AnnaBridge 189:f392fc9709a3 54 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 55 extern "C" {
AnnaBridge 189:f392fc9709a3 56 #endif
AnnaBridge 189:f392fc9709a3 57
AnnaBridge 189:f392fc9709a3 58 /* Includes ------------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 59 #include "stm32l0xx.h"
AnnaBridge 189:f392fc9709a3 60
AnnaBridge 189:f392fc9709a3 61 /** @addtogroup STM32L0xx_LL_Driver
AnnaBridge 189:f392fc9709a3 62 * @{
AnnaBridge 189:f392fc9709a3 63 */
AnnaBridge 189:f392fc9709a3 64
AnnaBridge 189:f392fc9709a3 65 /** @defgroup CORTEX_LL CORTEX
AnnaBridge 189:f392fc9709a3 66 * @{
AnnaBridge 189:f392fc9709a3 67 */
AnnaBridge 189:f392fc9709a3 68
AnnaBridge 189:f392fc9709a3 69 /* Private types -------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 70 /* Private variables ---------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 71
AnnaBridge 189:f392fc9709a3 72 /* Private constants ---------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 73
AnnaBridge 189:f392fc9709a3 74 /* Private macros ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 75
AnnaBridge 189:f392fc9709a3 76 /* Exported types ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 77 /* Exported constants --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 78 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
AnnaBridge 189:f392fc9709a3 79 * @{
AnnaBridge 189:f392fc9709a3 80 */
AnnaBridge 189:f392fc9709a3 81
AnnaBridge 189:f392fc9709a3 82 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
AnnaBridge 189:f392fc9709a3 83 * @{
AnnaBridge 189:f392fc9709a3 84 */
AnnaBridge 189:f392fc9709a3 85 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/
AnnaBridge 189:f392fc9709a3 86 #define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */
AnnaBridge 189:f392fc9709a3 87 /**
AnnaBridge 189:f392fc9709a3 88 * @}
AnnaBridge 189:f392fc9709a3 89 */
AnnaBridge 189:f392fc9709a3 90
AnnaBridge 189:f392fc9709a3 91 #if __MPU_PRESENT
AnnaBridge 189:f392fc9709a3 92
AnnaBridge 189:f392fc9709a3 93 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
AnnaBridge 189:f392fc9709a3 94 * @{
AnnaBridge 189:f392fc9709a3 95 */
AnnaBridge 189:f392fc9709a3 96 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< Disable NMI and privileged SW access */
AnnaBridge 189:f392fc9709a3 97 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
AnnaBridge 189:f392fc9709a3 98 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
AnnaBridge 189:f392fc9709a3 99 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
AnnaBridge 189:f392fc9709a3 100 /**
AnnaBridge 189:f392fc9709a3 101 * @}
AnnaBridge 189:f392fc9709a3 102 */
AnnaBridge 189:f392fc9709a3 103
AnnaBridge 189:f392fc9709a3 104 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
AnnaBridge 189:f392fc9709a3 105 * @{
AnnaBridge 189:f392fc9709a3 106 */
AnnaBridge 189:f392fc9709a3 107 #define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U) /*!< REGION Number 0 */
AnnaBridge 189:f392fc9709a3 108 #define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U) /*!< REGION Number 1 */
AnnaBridge 189:f392fc9709a3 109 #define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U) /*!< REGION Number 2 */
AnnaBridge 189:f392fc9709a3 110 #define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U) /*!< REGION Number 3 */
AnnaBridge 189:f392fc9709a3 111 #define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U) /*!< REGION Number 4 */
AnnaBridge 189:f392fc9709a3 112 #define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U) /*!< REGION Number 5 */
AnnaBridge 189:f392fc9709a3 113 #define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U) /*!< REGION Number 6 */
AnnaBridge 189:f392fc9709a3 114 #define LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U) /*!< REGION Number 7 */
AnnaBridge 189:f392fc9709a3 115 /**
AnnaBridge 189:f392fc9709a3 116 * @}
AnnaBridge 189:f392fc9709a3 117 */
AnnaBridge 189:f392fc9709a3 118
AnnaBridge 189:f392fc9709a3 119 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
AnnaBridge 189:f392fc9709a3 120 * @{
AnnaBridge 189:f392fc9709a3 121 */
AnnaBridge 189:f392fc9709a3 122 #define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 123 #define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 124 #define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 125 #define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 126 #define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 127 #define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 128 #define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 129 #define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 130 #define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 131 #define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 132 #define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 133 #define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 134 #define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 135 #define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 136 #define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 137 #define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 138 #define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 139 #define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 140 #define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 141 #define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 142 #define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 143 #define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 144 #define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 145 #define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 146 #define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 147 #define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 148 #define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 149 #define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */
AnnaBridge 189:f392fc9709a3 150 /**
AnnaBridge 189:f392fc9709a3 151 * @}
AnnaBridge 189:f392fc9709a3 152 */
AnnaBridge 189:f392fc9709a3 153
AnnaBridge 189:f392fc9709a3 154 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
AnnaBridge 189:f392fc9709a3 155 * @{
AnnaBridge 189:f392fc9709a3 156 */
AnnaBridge 189:f392fc9709a3 157 #define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/
AnnaBridge 189:f392fc9709a3 158 #define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/
AnnaBridge 189:f392fc9709a3 159 #define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */
AnnaBridge 189:f392fc9709a3 160 #define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */
AnnaBridge 189:f392fc9709a3 161 #define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/
AnnaBridge 189:f392fc9709a3 162 #define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */
AnnaBridge 189:f392fc9709a3 163 /**
AnnaBridge 189:f392fc9709a3 164 * @}
AnnaBridge 189:f392fc9709a3 165 */
AnnaBridge 189:f392fc9709a3 166
AnnaBridge 189:f392fc9709a3 167 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
AnnaBridge 189:f392fc9709a3 168 * @{
AnnaBridge 189:f392fc9709a3 169 */
AnnaBridge 189:f392fc9709a3 170 #define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */
AnnaBridge 189:f392fc9709a3 171 #define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */
AnnaBridge 189:f392fc9709a3 172 #define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */
AnnaBridge 189:f392fc9709a3 173 #define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */
AnnaBridge 189:f392fc9709a3 174 /**
AnnaBridge 189:f392fc9709a3 175 * @}
AnnaBridge 189:f392fc9709a3 176 */
AnnaBridge 189:f392fc9709a3 177
AnnaBridge 189:f392fc9709a3 178 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
AnnaBridge 189:f392fc9709a3 179 * @{
AnnaBridge 189:f392fc9709a3 180 */
AnnaBridge 189:f392fc9709a3 181 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U) /*!< Instruction fetches enabled */
AnnaBridge 189:f392fc9709a3 182 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
AnnaBridge 189:f392fc9709a3 183 /**
AnnaBridge 189:f392fc9709a3 184 * @}
AnnaBridge 189:f392fc9709a3 185 */
AnnaBridge 189:f392fc9709a3 186
AnnaBridge 189:f392fc9709a3 187 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
AnnaBridge 189:f392fc9709a3 188 * @{
AnnaBridge 189:f392fc9709a3 189 */
AnnaBridge 189:f392fc9709a3 190 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
AnnaBridge 189:f392fc9709a3 191 #define LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U) /*!< Not Shareable memory attribute */
AnnaBridge 189:f392fc9709a3 192 /**
AnnaBridge 189:f392fc9709a3 193 * @}
AnnaBridge 189:f392fc9709a3 194 */
AnnaBridge 189:f392fc9709a3 195
AnnaBridge 189:f392fc9709a3 196 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
AnnaBridge 189:f392fc9709a3 197 * @{
AnnaBridge 189:f392fc9709a3 198 */
AnnaBridge 189:f392fc9709a3 199 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
AnnaBridge 189:f392fc9709a3 200 #define LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */
AnnaBridge 189:f392fc9709a3 201 /**
AnnaBridge 189:f392fc9709a3 202 * @}
AnnaBridge 189:f392fc9709a3 203 */
AnnaBridge 189:f392fc9709a3 204
AnnaBridge 189:f392fc9709a3 205 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
AnnaBridge 189:f392fc9709a3 206 * @{
AnnaBridge 189:f392fc9709a3 207 */
AnnaBridge 189:f392fc9709a3 208 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
AnnaBridge 189:f392fc9709a3 209 #define LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U) /*!< Not Bufferable memory attribute */
AnnaBridge 189:f392fc9709a3 210 /**
AnnaBridge 189:f392fc9709a3 211 * @}
AnnaBridge 189:f392fc9709a3 212 */
AnnaBridge 189:f392fc9709a3 213 #endif /* __MPU_PRESENT */
AnnaBridge 189:f392fc9709a3 214 /**
AnnaBridge 189:f392fc9709a3 215 * @}
AnnaBridge 189:f392fc9709a3 216 */
AnnaBridge 189:f392fc9709a3 217
AnnaBridge 189:f392fc9709a3 218 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 219
AnnaBridge 189:f392fc9709a3 220 /* Exported functions --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 221 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
AnnaBridge 189:f392fc9709a3 222 * @{
AnnaBridge 189:f392fc9709a3 223 */
AnnaBridge 189:f392fc9709a3 224
AnnaBridge 189:f392fc9709a3 225 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
AnnaBridge 189:f392fc9709a3 226 * @{
AnnaBridge 189:f392fc9709a3 227 */
AnnaBridge 189:f392fc9709a3 228
AnnaBridge 189:f392fc9709a3 229 /**
AnnaBridge 189:f392fc9709a3 230 * @brief This function checks if the Systick counter flag is active or not.
AnnaBridge 189:f392fc9709a3 231 * @note It can be used in timeout function on application side.
AnnaBridge 189:f392fc9709a3 232 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
AnnaBridge 189:f392fc9709a3 233 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 234 */
AnnaBridge 189:f392fc9709a3 235 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
AnnaBridge 189:f392fc9709a3 236 {
AnnaBridge 189:f392fc9709a3 237 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
AnnaBridge 189:f392fc9709a3 238 }
AnnaBridge 189:f392fc9709a3 239
AnnaBridge 189:f392fc9709a3 240 /**
AnnaBridge 189:f392fc9709a3 241 * @brief Configures the SysTick clock source
AnnaBridge 189:f392fc9709a3 242 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
AnnaBridge 189:f392fc9709a3 243 * @param Source This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 244 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 189:f392fc9709a3 245 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 189:f392fc9709a3 246 * @retval None
AnnaBridge 189:f392fc9709a3 247 */
AnnaBridge 189:f392fc9709a3 248 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
AnnaBridge 189:f392fc9709a3 249 {
AnnaBridge 189:f392fc9709a3 250 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
AnnaBridge 189:f392fc9709a3 251 {
AnnaBridge 189:f392fc9709a3 252 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 189:f392fc9709a3 253 }
AnnaBridge 189:f392fc9709a3 254 else
AnnaBridge 189:f392fc9709a3 255 {
AnnaBridge 189:f392fc9709a3 256 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 189:f392fc9709a3 257 }
AnnaBridge 189:f392fc9709a3 258 }
AnnaBridge 189:f392fc9709a3 259
AnnaBridge 189:f392fc9709a3 260 /**
AnnaBridge 189:f392fc9709a3 261 * @brief Get the SysTick clock source
AnnaBridge 189:f392fc9709a3 262 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
AnnaBridge 189:f392fc9709a3 263 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 264 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 189:f392fc9709a3 265 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 189:f392fc9709a3 266 */
AnnaBridge 189:f392fc9709a3 267 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
AnnaBridge 189:f392fc9709a3 268 {
AnnaBridge 189:f392fc9709a3 269 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 189:f392fc9709a3 270 }
AnnaBridge 189:f392fc9709a3 271
AnnaBridge 189:f392fc9709a3 272 /**
AnnaBridge 189:f392fc9709a3 273 * @brief Enable SysTick exception request
AnnaBridge 189:f392fc9709a3 274 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
AnnaBridge 189:f392fc9709a3 275 * @retval None
AnnaBridge 189:f392fc9709a3 276 */
AnnaBridge 189:f392fc9709a3 277 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
AnnaBridge 189:f392fc9709a3 278 {
AnnaBridge 189:f392fc9709a3 279 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 189:f392fc9709a3 280 }
AnnaBridge 189:f392fc9709a3 281
AnnaBridge 189:f392fc9709a3 282 /**
AnnaBridge 189:f392fc9709a3 283 * @brief Disable SysTick exception request
AnnaBridge 189:f392fc9709a3 284 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
AnnaBridge 189:f392fc9709a3 285 * @retval None
AnnaBridge 189:f392fc9709a3 286 */
AnnaBridge 189:f392fc9709a3 287 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
AnnaBridge 189:f392fc9709a3 288 {
AnnaBridge 189:f392fc9709a3 289 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 189:f392fc9709a3 290 }
AnnaBridge 189:f392fc9709a3 291
AnnaBridge 189:f392fc9709a3 292 /**
AnnaBridge 189:f392fc9709a3 293 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
AnnaBridge 189:f392fc9709a3 294 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
AnnaBridge 189:f392fc9709a3 295 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 296 */
AnnaBridge 189:f392fc9709a3 297 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
AnnaBridge 189:f392fc9709a3 298 {
AnnaBridge 189:f392fc9709a3 299 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
AnnaBridge 189:f392fc9709a3 300 }
AnnaBridge 189:f392fc9709a3 301
AnnaBridge 189:f392fc9709a3 302 /**
AnnaBridge 189:f392fc9709a3 303 * @}
AnnaBridge 189:f392fc9709a3 304 */
AnnaBridge 189:f392fc9709a3 305
AnnaBridge 189:f392fc9709a3 306 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
AnnaBridge 189:f392fc9709a3 307 * @{
AnnaBridge 189:f392fc9709a3 308 */
AnnaBridge 189:f392fc9709a3 309
AnnaBridge 189:f392fc9709a3 310 /**
AnnaBridge 189:f392fc9709a3 311 * @brief Processor uses sleep as its low power mode
AnnaBridge 189:f392fc9709a3 312 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
AnnaBridge 189:f392fc9709a3 313 * @retval None
AnnaBridge 189:f392fc9709a3 314 */
AnnaBridge 189:f392fc9709a3 315 __STATIC_INLINE void LL_LPM_EnableSleep(void)
AnnaBridge 189:f392fc9709a3 316 {
AnnaBridge 189:f392fc9709a3 317 /* Clear SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 318 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 189:f392fc9709a3 319 }
AnnaBridge 189:f392fc9709a3 320
AnnaBridge 189:f392fc9709a3 321 /**
AnnaBridge 189:f392fc9709a3 322 * @brief Processor uses deep sleep as its low power mode
AnnaBridge 189:f392fc9709a3 323 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
AnnaBridge 189:f392fc9709a3 324 * @retval None
AnnaBridge 189:f392fc9709a3 325 */
AnnaBridge 189:f392fc9709a3 326 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
AnnaBridge 189:f392fc9709a3 327 {
AnnaBridge 189:f392fc9709a3 328 /* Set SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 329 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 189:f392fc9709a3 330 }
AnnaBridge 189:f392fc9709a3 331
AnnaBridge 189:f392fc9709a3 332 /**
AnnaBridge 189:f392fc9709a3 333 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
AnnaBridge 189:f392fc9709a3 334 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
AnnaBridge 189:f392fc9709a3 335 * empty main application.
AnnaBridge 189:f392fc9709a3 336 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
AnnaBridge 189:f392fc9709a3 337 * @retval None
AnnaBridge 189:f392fc9709a3 338 */
AnnaBridge 189:f392fc9709a3 339 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
AnnaBridge 189:f392fc9709a3 340 {
AnnaBridge 189:f392fc9709a3 341 /* Set SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 342 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 189:f392fc9709a3 343 }
AnnaBridge 189:f392fc9709a3 344
AnnaBridge 189:f392fc9709a3 345 /**
AnnaBridge 189:f392fc9709a3 346 * @brief Do not sleep when returning to Thread mode.
AnnaBridge 189:f392fc9709a3 347 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
AnnaBridge 189:f392fc9709a3 348 * @retval None
AnnaBridge 189:f392fc9709a3 349 */
AnnaBridge 189:f392fc9709a3 350 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
AnnaBridge 189:f392fc9709a3 351 {
AnnaBridge 189:f392fc9709a3 352 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 353 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 189:f392fc9709a3 354 }
AnnaBridge 189:f392fc9709a3 355
AnnaBridge 189:f392fc9709a3 356 /**
AnnaBridge 189:f392fc9709a3 357 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
AnnaBridge 189:f392fc9709a3 358 * processor.
AnnaBridge 189:f392fc9709a3 359 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
AnnaBridge 189:f392fc9709a3 360 * @retval None
AnnaBridge 189:f392fc9709a3 361 */
AnnaBridge 189:f392fc9709a3 362 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
AnnaBridge 189:f392fc9709a3 363 {
AnnaBridge 189:f392fc9709a3 364 /* Set SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 365 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 189:f392fc9709a3 366 }
AnnaBridge 189:f392fc9709a3 367
AnnaBridge 189:f392fc9709a3 368 /**
AnnaBridge 189:f392fc9709a3 369 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
AnnaBridge 189:f392fc9709a3 370 * excluded
AnnaBridge 189:f392fc9709a3 371 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
AnnaBridge 189:f392fc9709a3 372 * @retval None
AnnaBridge 189:f392fc9709a3 373 */
AnnaBridge 189:f392fc9709a3 374 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
AnnaBridge 189:f392fc9709a3 375 {
AnnaBridge 189:f392fc9709a3 376 /* Clear SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 377 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 189:f392fc9709a3 378 }
AnnaBridge 189:f392fc9709a3 379
AnnaBridge 189:f392fc9709a3 380 /**
AnnaBridge 189:f392fc9709a3 381 * @}
AnnaBridge 189:f392fc9709a3 382 */
AnnaBridge 189:f392fc9709a3 383
AnnaBridge 189:f392fc9709a3 384 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
AnnaBridge 189:f392fc9709a3 385 * @{
AnnaBridge 189:f392fc9709a3 386 */
AnnaBridge 189:f392fc9709a3 387
AnnaBridge 189:f392fc9709a3 388 /**
AnnaBridge 189:f392fc9709a3 389 * @brief Get Implementer code
AnnaBridge 189:f392fc9709a3 390 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
AnnaBridge 189:f392fc9709a3 391 * @retval Value should be equal to 0x41 for ARM
AnnaBridge 189:f392fc9709a3 392 */
AnnaBridge 189:f392fc9709a3 393 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
AnnaBridge 189:f392fc9709a3 394 {
AnnaBridge 189:f392fc9709a3 395 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
AnnaBridge 189:f392fc9709a3 396 }
AnnaBridge 189:f392fc9709a3 397
AnnaBridge 189:f392fc9709a3 398 /**
AnnaBridge 189:f392fc9709a3 399 * @brief Get Variant number (The r value in the rnpn product revision identifier)
AnnaBridge 189:f392fc9709a3 400 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
AnnaBridge 189:f392fc9709a3 401 * @retval Value between 0 and 255 (0x0: revision 0)
AnnaBridge 189:f392fc9709a3 402 */
AnnaBridge 189:f392fc9709a3 403 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
AnnaBridge 189:f392fc9709a3 404 {
AnnaBridge 189:f392fc9709a3 405 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
AnnaBridge 189:f392fc9709a3 406 }
AnnaBridge 189:f392fc9709a3 407
AnnaBridge 189:f392fc9709a3 408 /**
AnnaBridge 189:f392fc9709a3 409 * @brief Get Architecture number
AnnaBridge 189:f392fc9709a3 410 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
AnnaBridge 189:f392fc9709a3 411 * @retval Value should be equal to 0xC for Cortex-M0+ devices
AnnaBridge 189:f392fc9709a3 412 */
AnnaBridge 189:f392fc9709a3 413 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
AnnaBridge 189:f392fc9709a3 414 {
AnnaBridge 189:f392fc9709a3 415 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
AnnaBridge 189:f392fc9709a3 416 }
AnnaBridge 189:f392fc9709a3 417
AnnaBridge 189:f392fc9709a3 418 /**
AnnaBridge 189:f392fc9709a3 419 * @brief Get Part number
AnnaBridge 189:f392fc9709a3 420 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
AnnaBridge 189:f392fc9709a3 421 * @retval Value should be equal to 0xC60 for Cortex-M0+
AnnaBridge 189:f392fc9709a3 422 */
AnnaBridge 189:f392fc9709a3 423 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
AnnaBridge 189:f392fc9709a3 424 {
AnnaBridge 189:f392fc9709a3 425 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
AnnaBridge 189:f392fc9709a3 426 }
AnnaBridge 189:f392fc9709a3 427
AnnaBridge 189:f392fc9709a3 428 /**
AnnaBridge 189:f392fc9709a3 429 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
AnnaBridge 189:f392fc9709a3 430 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
AnnaBridge 189:f392fc9709a3 431 * @retval Value between 0 and 255 (0x1: patch 1)
AnnaBridge 189:f392fc9709a3 432 */
AnnaBridge 189:f392fc9709a3 433 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
AnnaBridge 189:f392fc9709a3 434 {
AnnaBridge 189:f392fc9709a3 435 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
AnnaBridge 189:f392fc9709a3 436 }
AnnaBridge 189:f392fc9709a3 437
AnnaBridge 189:f392fc9709a3 438 /**
AnnaBridge 189:f392fc9709a3 439 * @}
AnnaBridge 189:f392fc9709a3 440 */
AnnaBridge 189:f392fc9709a3 441
AnnaBridge 189:f392fc9709a3 442 #if __MPU_PRESENT
AnnaBridge 189:f392fc9709a3 443 /** @defgroup CORTEX_LL_EF_MPU MPU
AnnaBridge 189:f392fc9709a3 444 * @{
AnnaBridge 189:f392fc9709a3 445 */
AnnaBridge 189:f392fc9709a3 446
AnnaBridge 189:f392fc9709a3 447 /**
AnnaBridge 189:f392fc9709a3 448 * @brief Enable MPU with input options
AnnaBridge 189:f392fc9709a3 449 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
AnnaBridge 189:f392fc9709a3 450 * @param Options This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 451 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
AnnaBridge 189:f392fc9709a3 452 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
AnnaBridge 189:f392fc9709a3 453 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
AnnaBridge 189:f392fc9709a3 454 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
AnnaBridge 189:f392fc9709a3 455 * @retval None
AnnaBridge 189:f392fc9709a3 456 */
AnnaBridge 189:f392fc9709a3 457 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
AnnaBridge 189:f392fc9709a3 458 {
AnnaBridge 189:f392fc9709a3 459 /* Enable the MPU*/
AnnaBridge 189:f392fc9709a3 460 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
AnnaBridge 189:f392fc9709a3 461 /* Ensure MPU settings take effects */
AnnaBridge 189:f392fc9709a3 462 __DSB();
AnnaBridge 189:f392fc9709a3 463 /* Sequence instruction fetches using update settings */
AnnaBridge 189:f392fc9709a3 464 __ISB();
AnnaBridge 189:f392fc9709a3 465 }
AnnaBridge 189:f392fc9709a3 466
AnnaBridge 189:f392fc9709a3 467 /**
AnnaBridge 189:f392fc9709a3 468 * @brief Disable MPU
AnnaBridge 189:f392fc9709a3 469 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
AnnaBridge 189:f392fc9709a3 470 * @retval None
AnnaBridge 189:f392fc9709a3 471 */
AnnaBridge 189:f392fc9709a3 472 __STATIC_INLINE void LL_MPU_Disable(void)
AnnaBridge 189:f392fc9709a3 473 {
AnnaBridge 189:f392fc9709a3 474 /* Make sure outstanding transfers are done */
AnnaBridge 189:f392fc9709a3 475 __DMB();
AnnaBridge 189:f392fc9709a3 476 /* Disable MPU*/
AnnaBridge 189:f392fc9709a3 477 WRITE_REG(MPU->CTRL, 0U);
AnnaBridge 189:f392fc9709a3 478 }
AnnaBridge 189:f392fc9709a3 479
AnnaBridge 189:f392fc9709a3 480 /**
AnnaBridge 189:f392fc9709a3 481 * @brief Check if MPU is enabled or not
AnnaBridge 189:f392fc9709a3 482 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
AnnaBridge 189:f392fc9709a3 483 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 484 */
AnnaBridge 189:f392fc9709a3 485 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
AnnaBridge 189:f392fc9709a3 486 {
AnnaBridge 189:f392fc9709a3 487 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
AnnaBridge 189:f392fc9709a3 488 }
AnnaBridge 189:f392fc9709a3 489
AnnaBridge 189:f392fc9709a3 490 /**
AnnaBridge 189:f392fc9709a3 491 * @brief Enable a MPU region
AnnaBridge 189:f392fc9709a3 492 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
AnnaBridge 189:f392fc9709a3 493 * @param Region This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 494 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 189:f392fc9709a3 495 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 189:f392fc9709a3 496 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 189:f392fc9709a3 497 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 189:f392fc9709a3 498 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 189:f392fc9709a3 499 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 189:f392fc9709a3 500 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 189:f392fc9709a3 501 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 189:f392fc9709a3 502 * @retval None
AnnaBridge 189:f392fc9709a3 503 */
AnnaBridge 189:f392fc9709a3 504 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
AnnaBridge 189:f392fc9709a3 505 {
AnnaBridge 189:f392fc9709a3 506 /* Set Region number */
AnnaBridge 189:f392fc9709a3 507 WRITE_REG(MPU->RNR, Region);
AnnaBridge 189:f392fc9709a3 508 /* Enable the MPU region */
AnnaBridge 189:f392fc9709a3 509 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 189:f392fc9709a3 510 }
AnnaBridge 189:f392fc9709a3 511
AnnaBridge 189:f392fc9709a3 512 /**
AnnaBridge 189:f392fc9709a3 513 * @brief Configure and enable a region
AnnaBridge 189:f392fc9709a3 514 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 515 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 516 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 517 * MPU_RASR XN LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 518 * MPU_RASR AP LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 519 * MPU_RASR S LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 520 * MPU_RASR C LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 521 * MPU_RASR B LL_MPU_ConfigRegion\n
AnnaBridge 189:f392fc9709a3 522 * MPU_RASR SIZE LL_MPU_ConfigRegion
AnnaBridge 189:f392fc9709a3 523 * @param Region This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 524 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 189:f392fc9709a3 525 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 189:f392fc9709a3 526 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 189:f392fc9709a3 527 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 189:f392fc9709a3 528 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 189:f392fc9709a3 529 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 189:f392fc9709a3 530 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 189:f392fc9709a3 531 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 189:f392fc9709a3 532 * @param Address Value of region base address
AnnaBridge 189:f392fc9709a3 533 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge 189:f392fc9709a3 534 * @param Attributes This parameter can be a combination of the following values:
AnnaBridge 189:f392fc9709a3 535 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
AnnaBridge 189:f392fc9709a3 536 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
AnnaBridge 189:f392fc9709a3 537 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
AnnaBridge 189:f392fc9709a3 538 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
AnnaBridge 189:f392fc9709a3 539 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
AnnaBridge 189:f392fc9709a3 540 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
AnnaBridge 189:f392fc9709a3 541 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
AnnaBridge 189:f392fc9709a3 542 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
AnnaBridge 189:f392fc9709a3 543 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
AnnaBridge 189:f392fc9709a3 544 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
AnnaBridge 189:f392fc9709a3 545 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
AnnaBridge 189:f392fc9709a3 546 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
AnnaBridge 189:f392fc9709a3 547 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
AnnaBridge 189:f392fc9709a3 548 * @retval None
AnnaBridge 189:f392fc9709a3 549 */
AnnaBridge 189:f392fc9709a3 550 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
AnnaBridge 189:f392fc9709a3 551 {
AnnaBridge 189:f392fc9709a3 552 /* Set Region number */
AnnaBridge 189:f392fc9709a3 553 WRITE_REG(MPU->RNR, Region);
AnnaBridge 189:f392fc9709a3 554 /* Set base address */
AnnaBridge 189:f392fc9709a3 555 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
AnnaBridge 189:f392fc9709a3 556 /* Configure MPU */
AnnaBridge 189:f392fc9709a3 557 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
AnnaBridge 189:f392fc9709a3 558 }
AnnaBridge 189:f392fc9709a3 559
AnnaBridge 189:f392fc9709a3 560 /**
AnnaBridge 189:f392fc9709a3 561 * @brief Disable a region
AnnaBridge 189:f392fc9709a3 562 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
AnnaBridge 189:f392fc9709a3 563 * MPU_RASR ENABLE LL_MPU_DisableRegion
AnnaBridge 189:f392fc9709a3 564 * @param Region This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 565 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 189:f392fc9709a3 566 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 189:f392fc9709a3 567 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 189:f392fc9709a3 568 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 189:f392fc9709a3 569 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 189:f392fc9709a3 570 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 189:f392fc9709a3 571 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 189:f392fc9709a3 572 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 189:f392fc9709a3 573 * @retval None
AnnaBridge 189:f392fc9709a3 574 */
AnnaBridge 189:f392fc9709a3 575 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
AnnaBridge 189:f392fc9709a3 576 {
AnnaBridge 189:f392fc9709a3 577 /* Set Region number */
AnnaBridge 189:f392fc9709a3 578 WRITE_REG(MPU->RNR, Region);
AnnaBridge 189:f392fc9709a3 579 /* Disable the MPU region */
AnnaBridge 189:f392fc9709a3 580 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 189:f392fc9709a3 581 }
AnnaBridge 189:f392fc9709a3 582
AnnaBridge 189:f392fc9709a3 583 /**
AnnaBridge 189:f392fc9709a3 584 * @}
AnnaBridge 189:f392fc9709a3 585 */
AnnaBridge 189:f392fc9709a3 586
AnnaBridge 189:f392fc9709a3 587 #endif /* __MPU_PRESENT */
AnnaBridge 189:f392fc9709a3 588 /**
AnnaBridge 189:f392fc9709a3 589 * @}
AnnaBridge 189:f392fc9709a3 590 */
AnnaBridge 189:f392fc9709a3 591
AnnaBridge 189:f392fc9709a3 592 /**
AnnaBridge 189:f392fc9709a3 593 * @}
AnnaBridge 189:f392fc9709a3 594 */
AnnaBridge 189:f392fc9709a3 595
AnnaBridge 189:f392fc9709a3 596 /**
AnnaBridge 189:f392fc9709a3 597 * @}
AnnaBridge 189:f392fc9709a3 598 */
AnnaBridge 189:f392fc9709a3 599
AnnaBridge 189:f392fc9709a3 600 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 601 }
AnnaBridge 189:f392fc9709a3 602 #endif
AnnaBridge 189:f392fc9709a3 603
AnnaBridge 189:f392fc9709a3 604 #endif /* __STM32L0xx_LL_CORTEX_H */
AnnaBridge 189:f392fc9709a3 605
AnnaBridge 189:f392fc9709a3 606 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/