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cmsis/BUILD/mbed/TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/stm32l0xx_hal_tsc.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l0xx_hal_tsc.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief This file contains all the functions prototypes for the TSC firmware |
| AnnaBridge | 189:f392fc9709a3 | 6 | * library. |
| AnnaBridge | 189:f392fc9709a3 | 7 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 8 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 9 | * |
| AnnaBridge | 189:f392fc9709a3 | 10 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 11 | * |
| AnnaBridge | 189:f392fc9709a3 | 12 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 13 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 14 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 15 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 16 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 17 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 18 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 19 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 20 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 21 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 22 | * |
| AnnaBridge | 189:f392fc9709a3 | 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 24 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 27 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 28 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 29 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 30 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 32 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 33 | * |
| AnnaBridge | 189:f392fc9709a3 | 34 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 35 | */ |
| AnnaBridge | 189:f392fc9709a3 | 36 | |
| AnnaBridge | 189:f392fc9709a3 | 37 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 38 | #ifndef __STM32L0xx_TSC_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | #define __STM32L0xx_TSC_H |
| AnnaBridge | 189:f392fc9709a3 | 40 | |
| AnnaBridge | 189:f392fc9709a3 | 41 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 42 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 43 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 44 | |
| AnnaBridge | 189:f392fc9709a3 | 45 | #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 48 | #include "stm32l0xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 49 | |
| AnnaBridge | 189:f392fc9709a3 | 50 | /** @addtogroup STM32L0xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 51 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 52 | */ |
| AnnaBridge | 189:f392fc9709a3 | 53 | |
| AnnaBridge | 189:f392fc9709a3 | 54 | /** @defgroup TSC TSC |
| AnnaBridge | 189:f392fc9709a3 | 55 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 56 | */ |
| AnnaBridge | 189:f392fc9709a3 | 57 | |
| AnnaBridge | 189:f392fc9709a3 | 58 | /** @defgroup TSC_Exported_Types TSC Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 59 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 60 | */ |
| AnnaBridge | 189:f392fc9709a3 | 61 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 62 | |
| AnnaBridge | 189:f392fc9709a3 | 63 | /** |
| AnnaBridge | 189:f392fc9709a3 | 64 | * @brief TSC state structure definition |
| AnnaBridge | 189:f392fc9709a3 | 65 | */ |
| AnnaBridge | 189:f392fc9709a3 | 66 | typedef enum |
| AnnaBridge | 189:f392fc9709a3 | 67 | { |
| AnnaBridge | 189:f392fc9709a3 | 68 | HAL_TSC_STATE_RESET = 0x00U, /*!< TSC registers have their reset value */ |
| AnnaBridge | 189:f392fc9709a3 | 69 | HAL_TSC_STATE_READY = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */ |
| AnnaBridge | 189:f392fc9709a3 | 70 | HAL_TSC_STATE_BUSY = 0x02U, /*!< TSC initialization or acquisition is on-going */ |
| AnnaBridge | 189:f392fc9709a3 | 71 | HAL_TSC_STATE_ERROR = 0x03U /*!< Acquisition is completed with max count error */ |
| AnnaBridge | 189:f392fc9709a3 | 72 | } HAL_TSC_StateTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 73 | |
| AnnaBridge | 189:f392fc9709a3 | 74 | /** |
| AnnaBridge | 189:f392fc9709a3 | 75 | * @brief TSC group status structure definition |
| AnnaBridge | 189:f392fc9709a3 | 76 | */ |
| AnnaBridge | 189:f392fc9709a3 | 77 | typedef enum |
| AnnaBridge | 189:f392fc9709a3 | 78 | { |
| AnnaBridge | 189:f392fc9709a3 | 79 | TSC_GROUP_ONGOING = 0x00U, /*!< Acquisition on group is on-going or not started */ |
| AnnaBridge | 189:f392fc9709a3 | 80 | TSC_GROUP_COMPLETED = 0x01U /*!< Acquisition on group is completed with success (no max count error) */ |
| AnnaBridge | 189:f392fc9709a3 | 81 | } TSC_GroupStatusTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 82 | |
| AnnaBridge | 189:f392fc9709a3 | 83 | /** |
| AnnaBridge | 189:f392fc9709a3 | 84 | * @brief TSC init structure definition |
| AnnaBridge | 189:f392fc9709a3 | 85 | */ |
| AnnaBridge | 189:f392fc9709a3 | 86 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 87 | { |
| AnnaBridge | 189:f392fc9709a3 | 88 | uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length */ |
| AnnaBridge | 189:f392fc9709a3 | 89 | uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length */ |
| AnnaBridge | 189:f392fc9709a3 | 90 | uint32_t SpreadSpectrum; /*!< Spread spectrum activation */ |
| AnnaBridge | 189:f392fc9709a3 | 91 | uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation */ |
| AnnaBridge | 189:f392fc9709a3 | 92 | uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler */ |
| AnnaBridge | 189:f392fc9709a3 | 93 | uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler */ |
| AnnaBridge | 189:f392fc9709a3 | 94 | uint32_t MaxCountValue; /*!< Max count value */ |
| AnnaBridge | 189:f392fc9709a3 | 95 | uint32_t IODefaultMode; /*!< IO default mode */ |
| AnnaBridge | 189:f392fc9709a3 | 96 | uint32_t SynchroPinPolarity; /*!< Synchro pin polarity */ |
| AnnaBridge | 189:f392fc9709a3 | 97 | uint32_t AcquisitionMode; /*!< Acquisition mode */ |
| AnnaBridge | 189:f392fc9709a3 | 98 | uint32_t MaxCountInterrupt; /*!< Max count interrupt activation */ |
| AnnaBridge | 189:f392fc9709a3 | 99 | uint32_t ChannelIOs; /*!< Channel IOs mask */ |
| AnnaBridge | 189:f392fc9709a3 | 100 | uint32_t ShieldIOs; /*!< Shield IOs mask */ |
| AnnaBridge | 189:f392fc9709a3 | 101 | uint32_t SamplingIOs; /*!< Sampling IOs mask */ |
| AnnaBridge | 189:f392fc9709a3 | 102 | } TSC_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 103 | |
| AnnaBridge | 189:f392fc9709a3 | 104 | /** |
| AnnaBridge | 189:f392fc9709a3 | 105 | * @brief TSC IOs configuration structure definition |
| AnnaBridge | 189:f392fc9709a3 | 106 | */ |
| AnnaBridge | 189:f392fc9709a3 | 107 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 108 | { |
| AnnaBridge | 189:f392fc9709a3 | 109 | uint32_t ChannelIOs; /*!< Channel IOs mask */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | uint32_t ShieldIOs; /*!< Shield IOs mask */ |
| AnnaBridge | 189:f392fc9709a3 | 111 | uint32_t SamplingIOs; /*!< Sampling IOs mask */ |
| AnnaBridge | 189:f392fc9709a3 | 112 | } TSC_IOConfigTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 113 | |
| AnnaBridge | 189:f392fc9709a3 | 114 | /** |
| AnnaBridge | 189:f392fc9709a3 | 115 | * @brief TSC handle Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 116 | */ |
| AnnaBridge | 189:f392fc9709a3 | 117 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 118 | { |
| AnnaBridge | 189:f392fc9709a3 | 119 | TSC_TypeDef *Instance; /*!< Register base address */ |
| AnnaBridge | 189:f392fc9709a3 | 120 | TSC_InitTypeDef Init; /*!< Initialization parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | HAL_LockTypeDef Lock; /*!< Lock feature */ |
| AnnaBridge | 189:f392fc9709a3 | 123 | } TSC_HandleTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 124 | |
| AnnaBridge | 189:f392fc9709a3 | 125 | |
| AnnaBridge | 189:f392fc9709a3 | 126 | /** |
| AnnaBridge | 189:f392fc9709a3 | 127 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 128 | */ |
| AnnaBridge | 189:f392fc9709a3 | 129 | |
| AnnaBridge | 189:f392fc9709a3 | 130 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 131 | |
| AnnaBridge | 189:f392fc9709a3 | 132 | /** @defgroup TSC_Exported_Constants TSC Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 133 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 134 | */ |
| AnnaBridge | 189:f392fc9709a3 | 135 | |
| AnnaBridge | 189:f392fc9709a3 | 136 | |
| AnnaBridge | 189:f392fc9709a3 | 137 | #define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 138 | #define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 139 | #define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 140 | #define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 141 | #define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 142 | #define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 143 | #define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 144 | #define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 145 | #define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 146 | #define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 147 | #define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 148 | #define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 149 | #define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 150 | #define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 151 | #define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 152 | #define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15U << 28U)) |
| AnnaBridge | 189:f392fc9709a3 | 153 | |
| AnnaBridge | 189:f392fc9709a3 | 154 | #define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 155 | #define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 156 | #define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 157 | #define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 158 | #define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 159 | #define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 160 | #define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 161 | #define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 162 | #define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 163 | #define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 164 | #define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 165 | #define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 166 | #define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 167 | #define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 168 | #define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 169 | #define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15U << 24U)) |
| AnnaBridge | 189:f392fc9709a3 | 170 | |
| AnnaBridge | 189:f392fc9709a3 | 171 | #define TSC_SS_PRESC_DIV1 ((uint32_t)0U) |
| AnnaBridge | 189:f392fc9709a3 | 172 | #define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC) |
| AnnaBridge | 189:f392fc9709a3 | 173 | |
| AnnaBridge | 189:f392fc9709a3 | 174 | #define TSC_PG_PRESC_DIV1 ((uint32_t)(0U << 12U)) |
| AnnaBridge | 189:f392fc9709a3 | 175 | #define TSC_PG_PRESC_DIV2 ((uint32_t)(1U << 12U)) |
| AnnaBridge | 189:f392fc9709a3 | 176 | #define TSC_PG_PRESC_DIV4 ((uint32_t)(2U << 12U)) |
| AnnaBridge | 189:f392fc9709a3 | 177 | #define TSC_PG_PRESC_DIV8 ((uint32_t)(3U << 12U)) |
| AnnaBridge | 189:f392fc9709a3 | 178 | #define TSC_PG_PRESC_DIV16 ((uint32_t)(4U << 12U)) |
| AnnaBridge | 189:f392fc9709a3 | 179 | #define TSC_PG_PRESC_DIV32 ((uint32_t)(5U << 12U)) |
| AnnaBridge | 189:f392fc9709a3 | 180 | #define TSC_PG_PRESC_DIV64 ((uint32_t)(6U << 12U)) |
| AnnaBridge | 189:f392fc9709a3 | 181 | #define TSC_PG_PRESC_DIV128 ((uint32_t)(7U << 12U)) |
| AnnaBridge | 189:f392fc9709a3 | 182 | #define TSC_MCV_255 ((uint32_t)(0U << 5U)) |
| AnnaBridge | 189:f392fc9709a3 | 183 | #define TSC_MCV_511 ((uint32_t)(1U << 5U)) |
| AnnaBridge | 189:f392fc9709a3 | 184 | #define TSC_MCV_1023 ((uint32_t)(2U << 5U)) |
| AnnaBridge | 189:f392fc9709a3 | 185 | #define TSC_MCV_2047 ((uint32_t)(3U << 5U)) |
| AnnaBridge | 189:f392fc9709a3 | 186 | #define TSC_MCV_4095 ((uint32_t)(4U << 5U)) |
| AnnaBridge | 189:f392fc9709a3 | 187 | #define TSC_MCV_8191 ((uint32_t)(5U << 5U)) |
| AnnaBridge | 189:f392fc9709a3 | 188 | #define TSC_MCV_16383 ((uint32_t)(6U << 5U)) |
| AnnaBridge | 189:f392fc9709a3 | 189 | |
| AnnaBridge | 189:f392fc9709a3 | 190 | #define TSC_IODEF_OUT_PP_LOW ((uint32_t)0U) |
| AnnaBridge | 189:f392fc9709a3 | 191 | #define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF) |
| AnnaBridge | 189:f392fc9709a3 | 192 | |
| AnnaBridge | 189:f392fc9709a3 | 193 | #define TSC_SYNC_POLARITY_FALLING ((uint32_t)0U) |
| AnnaBridge | 189:f392fc9709a3 | 194 | #define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL) |
| AnnaBridge | 189:f392fc9709a3 | 195 | |
| AnnaBridge | 189:f392fc9709a3 | 196 | #define TSC_ACQ_MODE_NORMAL ((uint32_t)0U) |
| AnnaBridge | 189:f392fc9709a3 | 197 | #define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM) |
| AnnaBridge | 189:f392fc9709a3 | 198 | |
| AnnaBridge | 189:f392fc9709a3 | 199 | #define TSC_IOMODE_UNUSED ((uint32_t)0U) |
| AnnaBridge | 189:f392fc9709a3 | 200 | #define TSC_IOMODE_CHANNEL ((uint32_t)1U) |
| AnnaBridge | 189:f392fc9709a3 | 201 | #define TSC_IOMODE_SHIELD ((uint32_t)2U) |
| AnnaBridge | 189:f392fc9709a3 | 202 | #define TSC_IOMODE_SAMPLING ((uint32_t)3U) |
| AnnaBridge | 189:f392fc9709a3 | 203 | |
| AnnaBridge | 189:f392fc9709a3 | 204 | /** @defgroup TSC_interrupts_definition TSC Interrupts Definition |
| AnnaBridge | 189:f392fc9709a3 | 205 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 206 | */ |
| AnnaBridge | 189:f392fc9709a3 | 207 | #define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE) |
| AnnaBridge | 189:f392fc9709a3 | 208 | #define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE) |
| AnnaBridge | 189:f392fc9709a3 | 209 | /** |
| AnnaBridge | 189:f392fc9709a3 | 210 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 211 | */ |
| AnnaBridge | 189:f392fc9709a3 | 212 | |
| AnnaBridge | 189:f392fc9709a3 | 213 | /** @defgroup TSC_flags_definition TSC Flags Definition |
| AnnaBridge | 189:f392fc9709a3 | 214 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 215 | */ |
| AnnaBridge | 189:f392fc9709a3 | 216 | #define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF) |
| AnnaBridge | 189:f392fc9709a3 | 217 | #define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF) |
| AnnaBridge | 189:f392fc9709a3 | 218 | /** |
| AnnaBridge | 189:f392fc9709a3 | 219 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 220 | */ |
| AnnaBridge | 189:f392fc9709a3 | 221 | |
| AnnaBridge | 189:f392fc9709a3 | 222 | #define TSC_NB_OF_GROUPS (8) |
| AnnaBridge | 189:f392fc9709a3 | 223 | |
| AnnaBridge | 189:f392fc9709a3 | 224 | #define TSC_GROUP1 ((uint32_t)0x00000001U) |
| AnnaBridge | 189:f392fc9709a3 | 225 | #define TSC_GROUP2 ((uint32_t)0x00000002U) |
| AnnaBridge | 189:f392fc9709a3 | 226 | #define TSC_GROUP3 ((uint32_t)0x00000004U) |
| AnnaBridge | 189:f392fc9709a3 | 227 | #define TSC_GROUP4 ((uint32_t)0x00000008U) |
| AnnaBridge | 189:f392fc9709a3 | 228 | #define TSC_GROUP5 ((uint32_t)0x00000010U) |
| AnnaBridge | 189:f392fc9709a3 | 229 | #define TSC_GROUP6 ((uint32_t)0x00000020U) |
| AnnaBridge | 189:f392fc9709a3 | 230 | #define TSC_GROUP7 ((uint32_t)0x00000040U) |
| AnnaBridge | 189:f392fc9709a3 | 231 | #define TSC_GROUP8 ((uint32_t)0x00000080U) |
| AnnaBridge | 189:f392fc9709a3 | 232 | #define TSC_ALL_GROUPS ((uint32_t)0x000000FFU) |
| AnnaBridge | 189:f392fc9709a3 | 233 | |
| AnnaBridge | 189:f392fc9709a3 | 234 | #define TSC_GROUP1_IDX ((uint32_t)0U) |
| AnnaBridge | 189:f392fc9709a3 | 235 | #define TSC_GROUP2_IDX ((uint32_t)1U) |
| AnnaBridge | 189:f392fc9709a3 | 236 | #define TSC_GROUP3_IDX ((uint32_t)2U) |
| AnnaBridge | 189:f392fc9709a3 | 237 | #define TSC_GROUP4_IDX ((uint32_t)3U) |
| AnnaBridge | 189:f392fc9709a3 | 238 | #define TSC_GROUP5_IDX ((uint32_t)4U) |
| AnnaBridge | 189:f392fc9709a3 | 239 | #define TSC_GROUP6_IDX ((uint32_t)5U) |
| AnnaBridge | 189:f392fc9709a3 | 240 | #define TSC_GROUP7_IDX ((uint32_t)6U) |
| AnnaBridge | 189:f392fc9709a3 | 241 | #define TSC_GROUP8_IDX ((uint32_t)7U) |
| AnnaBridge | 189:f392fc9709a3 | 242 | |
| AnnaBridge | 189:f392fc9709a3 | 243 | #define TSC_GROUP1_IO1 ((uint32_t)0x00000001U) |
| AnnaBridge | 189:f392fc9709a3 | 244 | #define TSC_GROUP1_IO2 ((uint32_t)0x00000002U) |
| AnnaBridge | 189:f392fc9709a3 | 245 | #define TSC_GROUP1_IO3 ((uint32_t)0x00000004U) |
| AnnaBridge | 189:f392fc9709a3 | 246 | #define TSC_GROUP1_IO4 ((uint32_t)0x00000008U) |
| AnnaBridge | 189:f392fc9709a3 | 247 | #define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000FU) |
| AnnaBridge | 189:f392fc9709a3 | 248 | |
| AnnaBridge | 189:f392fc9709a3 | 249 | #define TSC_GROUP2_IO1 ((uint32_t)0x00000010U) |
| AnnaBridge | 189:f392fc9709a3 | 250 | #define TSC_GROUP2_IO2 ((uint32_t)0x00000020U) |
| AnnaBridge | 189:f392fc9709a3 | 251 | #define TSC_GROUP2_IO3 ((uint32_t)0x00000040U) |
| AnnaBridge | 189:f392fc9709a3 | 252 | #define TSC_GROUP2_IO4 ((uint32_t)0x00000080U) |
| AnnaBridge | 189:f392fc9709a3 | 253 | #define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0U) |
| AnnaBridge | 189:f392fc9709a3 | 254 | |
| AnnaBridge | 189:f392fc9709a3 | 255 | #define TSC_GROUP3_IO1 ((uint32_t)0x00000100U) |
| AnnaBridge | 189:f392fc9709a3 | 256 | #define TSC_GROUP3_IO2 ((uint32_t)0x00000200U) |
| AnnaBridge | 189:f392fc9709a3 | 257 | #define TSC_GROUP3_IO3 ((uint32_t)0x00000400U) |
| AnnaBridge | 189:f392fc9709a3 | 258 | #define TSC_GROUP3_IO4 ((uint32_t)0x00000800U) |
| AnnaBridge | 189:f392fc9709a3 | 259 | #define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00U) |
| AnnaBridge | 189:f392fc9709a3 | 260 | |
| AnnaBridge | 189:f392fc9709a3 | 261 | #define TSC_GROUP4_IO1 ((uint32_t)0x00001000U) |
| AnnaBridge | 189:f392fc9709a3 | 262 | #define TSC_GROUP4_IO2 ((uint32_t)0x00002000U) |
| AnnaBridge | 189:f392fc9709a3 | 263 | #define TSC_GROUP4_IO3 ((uint32_t)0x00004000U) |
| AnnaBridge | 189:f392fc9709a3 | 264 | #define TSC_GROUP4_IO4 ((uint32_t)0x00008000U) |
| AnnaBridge | 189:f392fc9709a3 | 265 | #define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000U) |
| AnnaBridge | 189:f392fc9709a3 | 266 | |
| AnnaBridge | 189:f392fc9709a3 | 267 | #define TSC_GROUP5_IO1 ((uint32_t)0x00010000U) |
| AnnaBridge | 189:f392fc9709a3 | 268 | #define TSC_GROUP5_IO2 ((uint32_t)0x00020000U) |
| AnnaBridge | 189:f392fc9709a3 | 269 | #define TSC_GROUP5_IO3 ((uint32_t)0x00040000U) |
| AnnaBridge | 189:f392fc9709a3 | 270 | #define TSC_GROUP5_IO4 ((uint32_t)0x00080000U) |
| AnnaBridge | 189:f392fc9709a3 | 271 | #define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000U) |
| AnnaBridge | 189:f392fc9709a3 | 272 | |
| AnnaBridge | 189:f392fc9709a3 | 273 | #define TSC_GROUP6_IO1 ((uint32_t)0x00100000U) |
| AnnaBridge | 189:f392fc9709a3 | 274 | #define TSC_GROUP6_IO2 ((uint32_t)0x00200000U) |
| AnnaBridge | 189:f392fc9709a3 | 275 | #define TSC_GROUP6_IO3 ((uint32_t)0x00400000U) |
| AnnaBridge | 189:f392fc9709a3 | 276 | #define TSC_GROUP6_IO4 ((uint32_t)0x00800000U) |
| AnnaBridge | 189:f392fc9709a3 | 277 | #define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000U) |
| AnnaBridge | 189:f392fc9709a3 | 278 | |
| AnnaBridge | 189:f392fc9709a3 | 279 | #define TSC_GROUP7_IO1 ((uint32_t)0x01000000U) |
| AnnaBridge | 189:f392fc9709a3 | 280 | #define TSC_GROUP7_IO2 ((uint32_t)0x02000000U) |
| AnnaBridge | 189:f392fc9709a3 | 281 | #define TSC_GROUP7_IO3 ((uint32_t)0x04000000U) |
| AnnaBridge | 189:f392fc9709a3 | 282 | #define TSC_GROUP7_IO4 ((uint32_t)0x08000000U) |
| AnnaBridge | 189:f392fc9709a3 | 283 | #define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000U) |
| AnnaBridge | 189:f392fc9709a3 | 284 | |
| AnnaBridge | 189:f392fc9709a3 | 285 | #define TSC_GROUP8_IO1 ((uint32_t)0x10000000U) |
| AnnaBridge | 189:f392fc9709a3 | 286 | #define TSC_GROUP8_IO2 ((uint32_t)0x20000000U) |
| AnnaBridge | 189:f392fc9709a3 | 287 | #define TSC_GROUP8_IO3 ((uint32_t)0x40000000U) |
| AnnaBridge | 189:f392fc9709a3 | 288 | #define TSC_GROUP8_IO4 ((uint32_t)0x80000000U) |
| AnnaBridge | 189:f392fc9709a3 | 289 | #define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000U) |
| AnnaBridge | 189:f392fc9709a3 | 290 | |
| AnnaBridge | 189:f392fc9709a3 | 291 | #define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFFU) |
| AnnaBridge | 189:f392fc9709a3 | 292 | |
| AnnaBridge | 189:f392fc9709a3 | 293 | /** |
| AnnaBridge | 189:f392fc9709a3 | 294 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 295 | */ |
| AnnaBridge | 189:f392fc9709a3 | 296 | |
| AnnaBridge | 189:f392fc9709a3 | 297 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 298 | |
| AnnaBridge | 189:f392fc9709a3 | 299 | /** @defgroup TSC_Exported_Macros TSC Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 300 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 301 | */ |
| AnnaBridge | 189:f392fc9709a3 | 302 | |
| AnnaBridge | 189:f392fc9709a3 | 303 | /** @brief Reset TSC handle state |
| AnnaBridge | 189:f392fc9709a3 | 304 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 305 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 306 | */ |
| AnnaBridge | 189:f392fc9709a3 | 307 | #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) |
| AnnaBridge | 189:f392fc9709a3 | 308 | |
| AnnaBridge | 189:f392fc9709a3 | 309 | /** |
| AnnaBridge | 189:f392fc9709a3 | 310 | * @brief Enable the TSC peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 311 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 312 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 313 | */ |
| AnnaBridge | 189:f392fc9709a3 | 314 | #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) |
| AnnaBridge | 189:f392fc9709a3 | 315 | |
| AnnaBridge | 189:f392fc9709a3 | 316 | /** |
| AnnaBridge | 189:f392fc9709a3 | 317 | * @brief Disable the TSC peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 318 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 319 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 320 | */ |
| AnnaBridge | 189:f392fc9709a3 | 321 | #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE)) |
| AnnaBridge | 189:f392fc9709a3 | 322 | |
| AnnaBridge | 189:f392fc9709a3 | 323 | /** |
| AnnaBridge | 189:f392fc9709a3 | 324 | * @brief Start acquisition |
| AnnaBridge | 189:f392fc9709a3 | 325 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 326 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 327 | */ |
| AnnaBridge | 189:f392fc9709a3 | 328 | #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) |
| AnnaBridge | 189:f392fc9709a3 | 329 | |
| AnnaBridge | 189:f392fc9709a3 | 330 | /** |
| AnnaBridge | 189:f392fc9709a3 | 331 | * @brief Stop acquisition |
| AnnaBridge | 189:f392fc9709a3 | 332 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 333 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 334 | */ |
| AnnaBridge | 189:f392fc9709a3 | 335 | #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START)) |
| AnnaBridge | 189:f392fc9709a3 | 336 | |
| AnnaBridge | 189:f392fc9709a3 | 337 | /** |
| AnnaBridge | 189:f392fc9709a3 | 338 | * @brief Set IO default mode to output push-pull low |
| AnnaBridge | 189:f392fc9709a3 | 339 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 340 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 341 | */ |
| AnnaBridge | 189:f392fc9709a3 | 342 | #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF)) |
| AnnaBridge | 189:f392fc9709a3 | 343 | |
| AnnaBridge | 189:f392fc9709a3 | 344 | /** |
| AnnaBridge | 189:f392fc9709a3 | 345 | * @brief Set IO default mode to input floating |
| AnnaBridge | 189:f392fc9709a3 | 346 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 347 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 348 | */ |
| AnnaBridge | 189:f392fc9709a3 | 349 | #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) |
| AnnaBridge | 189:f392fc9709a3 | 350 | |
| AnnaBridge | 189:f392fc9709a3 | 351 | /** |
| AnnaBridge | 189:f392fc9709a3 | 352 | * @brief Set synchronization polarity to falling edge |
| AnnaBridge | 189:f392fc9709a3 | 353 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 354 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 355 | */ |
| AnnaBridge | 189:f392fc9709a3 | 356 | #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL)) |
| AnnaBridge | 189:f392fc9709a3 | 357 | |
| AnnaBridge | 189:f392fc9709a3 | 358 | /** |
| AnnaBridge | 189:f392fc9709a3 | 359 | * @brief Set synchronization polarity to rising edge and high level |
| AnnaBridge | 189:f392fc9709a3 | 360 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 361 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 362 | */ |
| AnnaBridge | 189:f392fc9709a3 | 363 | #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) |
| AnnaBridge | 189:f392fc9709a3 | 364 | |
| AnnaBridge | 189:f392fc9709a3 | 365 | /** |
| AnnaBridge | 189:f392fc9709a3 | 366 | * @brief Enable TSC interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 367 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 368 | * @param __INTERRUPT__: TSC interrupt |
| AnnaBridge | 189:f392fc9709a3 | 369 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 370 | */ |
| AnnaBridge | 189:f392fc9709a3 | 371 | #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 372 | |
| AnnaBridge | 189:f392fc9709a3 | 373 | /** |
| AnnaBridge | 189:f392fc9709a3 | 374 | * @brief Disable TSC interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 375 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 376 | * @param __INTERRUPT__: TSC interrupt |
| AnnaBridge | 189:f392fc9709a3 | 377 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 378 | */ |
| AnnaBridge | 189:f392fc9709a3 | 379 | #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__))) |
| AnnaBridge | 189:f392fc9709a3 | 380 | |
| AnnaBridge | 189:f392fc9709a3 | 381 | /** @brief Check if the specified TSC interrupt source is enabled or disabled. |
| AnnaBridge | 189:f392fc9709a3 | 382 | * @param __HANDLE__: TSC Handle |
| AnnaBridge | 189:f392fc9709a3 | 383 | * @param __INTERRUPT__: TSC interrupt |
| AnnaBridge | 189:f392fc9709a3 | 384 | * @retval SET or RESET |
| AnnaBridge | 189:f392fc9709a3 | 385 | */ |
| AnnaBridge | 189:f392fc9709a3 | 386 | #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| AnnaBridge | 189:f392fc9709a3 | 387 | |
| AnnaBridge | 189:f392fc9709a3 | 388 | /** |
| AnnaBridge | 189:f392fc9709a3 | 389 | * @brief Get the selected TSC's flag status. |
| AnnaBridge | 189:f392fc9709a3 | 390 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 391 | * @param __FLAG__: TSC flag |
| AnnaBridge | 189:f392fc9709a3 | 392 | * @retval SET or RESET |
| AnnaBridge | 189:f392fc9709a3 | 393 | */ |
| AnnaBridge | 189:f392fc9709a3 | 394 | #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) |
| AnnaBridge | 189:f392fc9709a3 | 395 | |
| AnnaBridge | 189:f392fc9709a3 | 396 | /** |
| AnnaBridge | 189:f392fc9709a3 | 397 | * @brief Clear the TSC's pending flag. |
| AnnaBridge | 189:f392fc9709a3 | 398 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 399 | * @param __FLAG__: TSC flag |
| AnnaBridge | 189:f392fc9709a3 | 400 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 401 | */ |
| AnnaBridge | 189:f392fc9709a3 | 402 | #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) |
| AnnaBridge | 189:f392fc9709a3 | 403 | |
| AnnaBridge | 189:f392fc9709a3 | 404 | /** |
| AnnaBridge | 189:f392fc9709a3 | 405 | * @brief Enable schmitt trigger hysteresis on a group of IOs |
| AnnaBridge | 189:f392fc9709a3 | 406 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 407 | * @param __GX_IOY_MASK__: IOs mask |
| AnnaBridge | 189:f392fc9709a3 | 408 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 409 | */ |
| AnnaBridge | 189:f392fc9709a3 | 410 | #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) |
| AnnaBridge | 189:f392fc9709a3 | 411 | |
| AnnaBridge | 189:f392fc9709a3 | 412 | /** |
| AnnaBridge | 189:f392fc9709a3 | 413 | * @brief Disable schmitt trigger hysteresis on a group of IOs |
| AnnaBridge | 189:f392fc9709a3 | 414 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 415 | * @param __GX_IOY_MASK__: IOs mask |
| AnnaBridge | 189:f392fc9709a3 | 416 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 417 | */ |
| AnnaBridge | 189:f392fc9709a3 | 418 | #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__))) |
| AnnaBridge | 189:f392fc9709a3 | 419 | |
| AnnaBridge | 189:f392fc9709a3 | 420 | /** |
| AnnaBridge | 189:f392fc9709a3 | 421 | * @brief Open analog switch on a group of IOs |
| AnnaBridge | 189:f392fc9709a3 | 422 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 423 | * @param __GX_IOY_MASK__: IOs mask |
| AnnaBridge | 189:f392fc9709a3 | 424 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 425 | */ |
| AnnaBridge | 189:f392fc9709a3 | 426 | #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__))) |
| AnnaBridge | 189:f392fc9709a3 | 427 | |
| AnnaBridge | 189:f392fc9709a3 | 428 | /** |
| AnnaBridge | 189:f392fc9709a3 | 429 | * @brief Close analog switch on a group of IOs |
| AnnaBridge | 189:f392fc9709a3 | 430 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 431 | * @param __GX_IOY_MASK__: IOs mask |
| AnnaBridge | 189:f392fc9709a3 | 432 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 433 | */ |
| AnnaBridge | 189:f392fc9709a3 | 434 | #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) |
| AnnaBridge | 189:f392fc9709a3 | 435 | |
| AnnaBridge | 189:f392fc9709a3 | 436 | /** |
| AnnaBridge | 189:f392fc9709a3 | 437 | * @brief Enable a group of IOs in channel mode |
| AnnaBridge | 189:f392fc9709a3 | 438 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 439 | * @param __GX_IOY_MASK__: IOs mask |
| AnnaBridge | 189:f392fc9709a3 | 440 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 441 | */ |
| AnnaBridge | 189:f392fc9709a3 | 442 | #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) |
| AnnaBridge | 189:f392fc9709a3 | 443 | |
| AnnaBridge | 189:f392fc9709a3 | 444 | /** |
| AnnaBridge | 189:f392fc9709a3 | 445 | * @brief Disable a group of channel IOs |
| AnnaBridge | 189:f392fc9709a3 | 446 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 447 | * @param __GX_IOY_MASK__: IOs mask |
| AnnaBridge | 189:f392fc9709a3 | 448 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 449 | */ |
| AnnaBridge | 189:f392fc9709a3 | 450 | #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__))) |
| AnnaBridge | 189:f392fc9709a3 | 451 | |
| AnnaBridge | 189:f392fc9709a3 | 452 | /** |
| AnnaBridge | 189:f392fc9709a3 | 453 | * @brief Enable a group of IOs in sampling mode |
| AnnaBridge | 189:f392fc9709a3 | 454 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 455 | * @param __GX_IOY_MASK__: IOs mask |
| AnnaBridge | 189:f392fc9709a3 | 456 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 457 | */ |
| AnnaBridge | 189:f392fc9709a3 | 458 | #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) |
| AnnaBridge | 189:f392fc9709a3 | 459 | |
| AnnaBridge | 189:f392fc9709a3 | 460 | /** |
| AnnaBridge | 189:f392fc9709a3 | 461 | * @brief Disable a group of sampling IOs |
| AnnaBridge | 189:f392fc9709a3 | 462 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 463 | * @param __GX_IOY_MASK__: IOs mask |
| AnnaBridge | 189:f392fc9709a3 | 464 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 465 | */ |
| AnnaBridge | 189:f392fc9709a3 | 466 | #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__))) |
| AnnaBridge | 189:f392fc9709a3 | 467 | |
| AnnaBridge | 189:f392fc9709a3 | 468 | /** |
| AnnaBridge | 189:f392fc9709a3 | 469 | * @brief Enable acquisition groups |
| AnnaBridge | 189:f392fc9709a3 | 470 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 471 | * @param __GX_MASK__: Groups mask |
| AnnaBridge | 189:f392fc9709a3 | 472 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 473 | */ |
| AnnaBridge | 189:f392fc9709a3 | 474 | #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) |
| AnnaBridge | 189:f392fc9709a3 | 475 | |
| AnnaBridge | 189:f392fc9709a3 | 476 | /** |
| AnnaBridge | 189:f392fc9709a3 | 477 | * @brief Disable acquisition groups |
| AnnaBridge | 189:f392fc9709a3 | 478 | * @param __HANDLE__: TSC handle |
| AnnaBridge | 189:f392fc9709a3 | 479 | * @param __GX_MASK__: Groups mask |
| AnnaBridge | 189:f392fc9709a3 | 480 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 481 | */ |
| AnnaBridge | 189:f392fc9709a3 | 482 | #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__))) |
| AnnaBridge | 189:f392fc9709a3 | 483 | |
| AnnaBridge | 189:f392fc9709a3 | 484 | /** @brief Gets acquisition group status |
| AnnaBridge | 189:f392fc9709a3 | 485 | * @param __HANDLE__: TSC Handle |
| AnnaBridge | 189:f392fc9709a3 | 486 | * @param __GX_INDEX__: Group index |
| AnnaBridge | 189:f392fc9709a3 | 487 | * @retval SET or RESET |
| AnnaBridge | 189:f392fc9709a3 | 488 | */ |
| AnnaBridge | 189:f392fc9709a3 | 489 | #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ |
| AnnaBridge | 189:f392fc9709a3 | 490 | ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) |
| AnnaBridge | 189:f392fc9709a3 | 491 | |
| AnnaBridge | 189:f392fc9709a3 | 492 | /** |
| AnnaBridge | 189:f392fc9709a3 | 493 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 494 | */ |
| AnnaBridge | 189:f392fc9709a3 | 495 | |
| AnnaBridge | 189:f392fc9709a3 | 496 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 497 | |
| AnnaBridge | 189:f392fc9709a3 | 498 | /** @defgroup TSC_Private_Macros TSC Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 499 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 500 | */ |
| AnnaBridge | 189:f392fc9709a3 | 501 | #define IS_TSC_ALL_INSTANCE(PERIPH) ((PERIPH) == TSC) |
| AnnaBridge | 189:f392fc9709a3 | 502 | |
| AnnaBridge | 189:f392fc9709a3 | 503 | #define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 504 | ((VAL) == TSC_CTPH_2CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 505 | ((VAL) == TSC_CTPH_3CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 506 | ((VAL) == TSC_CTPH_4CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 507 | ((VAL) == TSC_CTPH_5CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 508 | ((VAL) == TSC_CTPH_6CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 509 | ((VAL) == TSC_CTPH_7CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 510 | ((VAL) == TSC_CTPH_8CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 511 | ((VAL) == TSC_CTPH_9CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 512 | ((VAL) == TSC_CTPH_10CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 513 | ((VAL) == TSC_CTPH_11CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 514 | ((VAL) == TSC_CTPH_12CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 515 | ((VAL) == TSC_CTPH_13CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 516 | ((VAL) == TSC_CTPH_14CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 517 | ((VAL) == TSC_CTPH_15CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 518 | ((VAL) == TSC_CTPH_16CYCLES)) |
| AnnaBridge | 189:f392fc9709a3 | 519 | #define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 520 | ((VAL) == TSC_CTPL_2CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 521 | ((VAL) == TSC_CTPL_3CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 522 | ((VAL) == TSC_CTPL_4CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 523 | ((VAL) == TSC_CTPL_5CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 524 | ((VAL) == TSC_CTPL_6CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 525 | ((VAL) == TSC_CTPL_7CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 526 | ((VAL) == TSC_CTPL_8CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 527 | ((VAL) == TSC_CTPL_9CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 528 | ((VAL) == TSC_CTPL_10CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 529 | ((VAL) == TSC_CTPL_11CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 530 | ((VAL) == TSC_CTPL_12CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 531 | ((VAL) == TSC_CTPL_13CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 532 | ((VAL) == TSC_CTPL_14CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 533 | ((VAL) == TSC_CTPL_15CYCLES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 534 | ((VAL) == TSC_CTPL_16CYCLES)) |
| AnnaBridge | 189:f392fc9709a3 | 535 | |
| AnnaBridge | 189:f392fc9709a3 | 536 | #define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 537 | |
| AnnaBridge | 189:f392fc9709a3 | 538 | #define IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U))) |
| AnnaBridge | 189:f392fc9709a3 | 539 | #define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2)) |
| AnnaBridge | 189:f392fc9709a3 | 540 | #define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 541 | ((VAL) == TSC_PG_PRESC_DIV2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 542 | ((VAL) == TSC_PG_PRESC_DIV4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 543 | ((VAL) == TSC_PG_PRESC_DIV8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 544 | ((VAL) == TSC_PG_PRESC_DIV16) || \ |
| AnnaBridge | 189:f392fc9709a3 | 545 | ((VAL) == TSC_PG_PRESC_DIV32) || \ |
| AnnaBridge | 189:f392fc9709a3 | 546 | ((VAL) == TSC_PG_PRESC_DIV64) || \ |
| AnnaBridge | 189:f392fc9709a3 | 547 | ((VAL) == TSC_PG_PRESC_DIV128)) |
| AnnaBridge | 189:f392fc9709a3 | 548 | |
| AnnaBridge | 189:f392fc9709a3 | 549 | #define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \ |
| AnnaBridge | 189:f392fc9709a3 | 550 | ((VAL) == TSC_MCV_511) || \ |
| AnnaBridge | 189:f392fc9709a3 | 551 | ((VAL) == TSC_MCV_1023) || \ |
| AnnaBridge | 189:f392fc9709a3 | 552 | ((VAL) == TSC_MCV_2047) || \ |
| AnnaBridge | 189:f392fc9709a3 | 553 | ((VAL) == TSC_MCV_4095) || \ |
| AnnaBridge | 189:f392fc9709a3 | 554 | ((VAL) == TSC_MCV_8191) || \ |
| AnnaBridge | 189:f392fc9709a3 | 555 | ((VAL) == TSC_MCV_16383)) |
| AnnaBridge | 189:f392fc9709a3 | 556 | #define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT)) |
| AnnaBridge | 189:f392fc9709a3 | 557 | #define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING)) |
| AnnaBridge | 189:f392fc9709a3 | 558 | #define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO)) |
| AnnaBridge | 189:f392fc9709a3 | 559 | #define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \ |
| AnnaBridge | 189:f392fc9709a3 | 560 | ((VAL) == TSC_IOMODE_CHANNEL) || \ |
| AnnaBridge | 189:f392fc9709a3 | 561 | ((VAL) == TSC_IOMODE_SHIELD) || \ |
| AnnaBridge | 189:f392fc9709a3 | 562 | ((VAL) == TSC_IOMODE_SAMPLING)) |
| AnnaBridge | 189:f392fc9709a3 | 563 | #define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 564 | |
| AnnaBridge | 189:f392fc9709a3 | 565 | #define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS))) |
| AnnaBridge | 189:f392fc9709a3 | 566 | |
| AnnaBridge | 189:f392fc9709a3 | 567 | /** |
| AnnaBridge | 189:f392fc9709a3 | 568 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 569 | */ |
| AnnaBridge | 189:f392fc9709a3 | 570 | |
| AnnaBridge | 189:f392fc9709a3 | 571 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 572 | |
| AnnaBridge | 189:f392fc9709a3 | 573 | /** @defgroup TSC_Exported_Functions TSC Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 574 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 575 | */ |
| AnnaBridge | 189:f392fc9709a3 | 576 | |
| AnnaBridge | 189:f392fc9709a3 | 577 | /** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 189:f392fc9709a3 | 578 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 579 | */ |
| AnnaBridge | 189:f392fc9709a3 | 580 | /* Initialization and de-initialization functions *****************************/ |
| AnnaBridge | 189:f392fc9709a3 | 581 | HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc); |
| AnnaBridge | 189:f392fc9709a3 | 582 | HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); |
| AnnaBridge | 189:f392fc9709a3 | 583 | void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc); |
| AnnaBridge | 189:f392fc9709a3 | 584 | void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc); |
| AnnaBridge | 189:f392fc9709a3 | 585 | /** |
| AnnaBridge | 189:f392fc9709a3 | 586 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 587 | */ |
| AnnaBridge | 189:f392fc9709a3 | 588 | |
| AnnaBridge | 189:f392fc9709a3 | 589 | /** @defgroup HAL_TSC_Exported_Functions_Group2 IO operation functions |
| AnnaBridge | 189:f392fc9709a3 | 590 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 591 | */ |
| AnnaBridge | 189:f392fc9709a3 | 592 | /* IO operation functions *****************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 593 | HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc); |
| AnnaBridge | 189:f392fc9709a3 | 594 | HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc); |
| AnnaBridge | 189:f392fc9709a3 | 595 | HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc); |
| AnnaBridge | 189:f392fc9709a3 | 596 | HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc); |
| AnnaBridge | 189:f392fc9709a3 | 597 | HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc); |
| AnnaBridge | 189:f392fc9709a3 | 598 | TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index); |
| AnnaBridge | 189:f392fc9709a3 | 599 | uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index); |
| AnnaBridge | 189:f392fc9709a3 | 600 | |
| AnnaBridge | 189:f392fc9709a3 | 601 | /** |
| AnnaBridge | 189:f392fc9709a3 | 602 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 603 | */ |
| AnnaBridge | 189:f392fc9709a3 | 604 | /** @defgroup HAL_TSC_Exported_Functions_Group3 Peripheral Control functions |
| AnnaBridge | 189:f392fc9709a3 | 605 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 606 | */ |
| AnnaBridge | 189:f392fc9709a3 | 607 | /* Peripheral Control functions ***********************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 608 | HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config); |
| AnnaBridge | 189:f392fc9709a3 | 609 | HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice); |
| AnnaBridge | 189:f392fc9709a3 | 610 | |
| AnnaBridge | 189:f392fc9709a3 | 611 | /** |
| AnnaBridge | 189:f392fc9709a3 | 612 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 613 | */ |
| AnnaBridge | 189:f392fc9709a3 | 614 | /** @defgroup HAL_TSC_Exported_Functions_Group4 State callback and error Functions |
| AnnaBridge | 189:f392fc9709a3 | 615 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 616 | */ |
| AnnaBridge | 189:f392fc9709a3 | 617 | /* Peripheral State and Error functions ***************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 618 | HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc); |
| AnnaBridge | 189:f392fc9709a3 | 619 | void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc); |
| AnnaBridge | 189:f392fc9709a3 | 620 | |
| AnnaBridge | 189:f392fc9709a3 | 621 | /* Callback functions *********************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 622 | void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc); |
| AnnaBridge | 189:f392fc9709a3 | 623 | void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc); |
| AnnaBridge | 189:f392fc9709a3 | 624 | |
| AnnaBridge | 189:f392fc9709a3 | 625 | /** |
| AnnaBridge | 189:f392fc9709a3 | 626 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 627 | */ |
| AnnaBridge | 189:f392fc9709a3 | 628 | |
| AnnaBridge | 189:f392fc9709a3 | 629 | /** |
| AnnaBridge | 189:f392fc9709a3 | 630 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 631 | */ |
| AnnaBridge | 189:f392fc9709a3 | 632 | |
| AnnaBridge | 189:f392fc9709a3 | 633 | /* Define the private group ***********************************/ |
| AnnaBridge | 189:f392fc9709a3 | 634 | /**************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 635 | /** @defgroup TSC_Private TSC Private |
| AnnaBridge | 189:f392fc9709a3 | 636 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 637 | */ |
| AnnaBridge | 189:f392fc9709a3 | 638 | /** |
| AnnaBridge | 189:f392fc9709a3 | 639 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 640 | */ |
| AnnaBridge | 189:f392fc9709a3 | 641 | /**************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 642 | |
| AnnaBridge | 189:f392fc9709a3 | 643 | /** |
| AnnaBridge | 189:f392fc9709a3 | 644 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 645 | */ |
| AnnaBridge | 189:f392fc9709a3 | 646 | |
| AnnaBridge | 189:f392fc9709a3 | 647 | /** |
| AnnaBridge | 189:f392fc9709a3 | 648 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 649 | */ |
| AnnaBridge | 189:f392fc9709a3 | 650 | |
| AnnaBridge | 189:f392fc9709a3 | 651 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 652 | } |
| AnnaBridge | 189:f392fc9709a3 | 653 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 654 | |
| AnnaBridge | 189:f392fc9709a3 | 655 | #endif /*__STM32L0xx_TSC_H */ |
| AnnaBridge | 189:f392fc9709a3 | 656 | #endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */ |
| AnnaBridge | 189:f392fc9709a3 | 657 | |
| AnnaBridge | 189:f392fc9709a3 | 658 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| AnnaBridge | 189:f392fc9709a3 | 659 |
