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mbed library sources. Supersedes mbed-src.

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cmsis/BUILD/mbed/TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/stm32l0xx_hal_tim_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l0xx_hal_tim_ex.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of TIM HAL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L0xx_HAL_TIM_EX_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L0xx_HAL_TIM_EX_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	45	#include "stm32l0xx_hal_def.h"
AnnaBridge	189:f392fc9709a3	46
AnnaBridge	189:f392fc9709a3	47	/** @addtogroup STM32L0xx_HAL_Driver
AnnaBridge	189:f392fc9709a3	48	* @{
AnnaBridge	189:f392fc9709a3	49	*/
AnnaBridge	189:f392fc9709a3	50
AnnaBridge	189:f392fc9709a3	51	/** @defgroup TIMEx TIMEx
AnnaBridge	189:f392fc9709a3	52	* @{
AnnaBridge	189:f392fc9709a3	53	*/
AnnaBridge	189:f392fc9709a3	54
AnnaBridge	189:f392fc9709a3	55	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	56	/** @defgroup TIM_Exported_Types TIM Exported Types
AnnaBridge	189:f392fc9709a3	57	* @{
AnnaBridge	189:f392fc9709a3	58	*/
AnnaBridge	189:f392fc9709a3	59	/**
AnnaBridge	189:f392fc9709a3	60	* @brief TIM Master configuration Structure definition
AnnaBridge	189:f392fc9709a3	61	*/
AnnaBridge	189:f392fc9709a3	62	typedef struct {
AnnaBridge	189:f392fc9709a3	63	uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
AnnaBridge	189:f392fc9709a3	64	This parameter can be a value of @ref TIM_Master_Mode_Selection */
AnnaBridge	189:f392fc9709a3	65	uint32_t MasterSlaveMode; /*!< Master/slave mode selection
AnnaBridge	189:f392fc9709a3	66	This parameter can be a value of @ref TIM_Master_Slave_Mode */
AnnaBridge	189:f392fc9709a3	67	}TIM_MasterConfigTypeDef;
AnnaBridge	189:f392fc9709a3	68
AnnaBridge	189:f392fc9709a3	69	/**
AnnaBridge	189:f392fc9709a3	70	* @}
AnnaBridge	189:f392fc9709a3	71	*/
AnnaBridge	189:f392fc9709a3	72
AnnaBridge	189:f392fc9709a3	73	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	74	/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
AnnaBridge	189:f392fc9709a3	75	* @{
AnnaBridge	189:f392fc9709a3	76	*/
AnnaBridge	189:f392fc9709a3	77
AnnaBridge	189:f392fc9709a3	78	/** @defgroup TIMEx_Trigger_Selection Trigger selection
AnnaBridge	189:f392fc9709a3	79	* @{
AnnaBridge	189:f392fc9709a3	80	*/
AnnaBridge	189:f392fc9709a3	81	#define TIM_TRGO_RESET ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	82	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
AnnaBridge	189:f392fc9709a3	83	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
AnnaBridge	189:f392fc9709a3	84	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
AnnaBridge	189:f392fc9709a3	85	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
AnnaBridge	189:f392fc9709a3	86	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
AnnaBridge	189:f392fc9709a3	87	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
AnnaBridge	189:f392fc9709a3	88	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
AnnaBridge	189:f392fc9709a3	89
AnnaBridge	189:f392fc9709a3	90	#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) \|\| \
AnnaBridge	189:f392fc9709a3	91	((__SOURCE__) == TIM_TRGO_ENABLE) \|\| \
AnnaBridge	189:f392fc9709a3	92	((__SOURCE__) == TIM_TRGO_UPDATE) \|\| \
AnnaBridge	189:f392fc9709a3	93	((__SOURCE__) == TIM_TRGO_OC1) \|\| \
AnnaBridge	189:f392fc9709a3	94	((__SOURCE__) == TIM_TRGO_OC1REF) \|\| \
AnnaBridge	189:f392fc9709a3	95	((__SOURCE__) == TIM_TRGO_OC2REF) \|\| \
AnnaBridge	189:f392fc9709a3	96	((__SOURCE__) == TIM_TRGO_OC3REF) \|\| \
AnnaBridge	189:f392fc9709a3	97	((__SOURCE__) == TIM_TRGO_OC4REF))
AnnaBridge	189:f392fc9709a3	98
AnnaBridge	189:f392fc9709a3	99	/**
AnnaBridge	189:f392fc9709a3	100	* @}
AnnaBridge	189:f392fc9709a3	101	*/
AnnaBridge	189:f392fc9709a3	102
AnnaBridge	189:f392fc9709a3	103	/** @defgroup TIMEx_Remap Remaping
AnnaBridge	189:f392fc9709a3	104	* @{
AnnaBridge	189:f392fc9709a3	105	*/
AnnaBridge	189:f392fc9709a3	106	#if defined (STM32L071xx) \|\| defined (STM32L072xx) \|\| defined (STM32L073xx) \
AnnaBridge	189:f392fc9709a3	107	\|\| defined (STM32L081xx) \|\| defined (STM32L082xx) \|\| defined (STM32L083xx)
AnnaBridge	189:f392fc9709a3	108
AnnaBridge	189:f392fc9709a3	109	#define TIM2_ETR_GPIO ((uint32_t)0x0U)
AnnaBridge	189:f392fc9709a3	110	#define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2
AnnaBridge	189:f392fc9709a3	111	#define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 \| TIM2_OR_ETR_RMP_0)
AnnaBridge	189:f392fc9709a3	112	#define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 \| TIM2_OR_ETR_RMP_0)
AnnaBridge	189:f392fc9709a3	113	#define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 \| TIM2_OR_ETR_RMP_1)
AnnaBridge	189:f392fc9709a3	114	#define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP
AnnaBridge	189:f392fc9709a3	115
AnnaBridge	189:f392fc9709a3	116	#elif defined (STM32L011xx) \|\| defined (STM32L021xx) \|\| defined (STM32L031xx) \|\| defined (STM32L041xx)
AnnaBridge	189:f392fc9709a3	117
AnnaBridge	189:f392fc9709a3	118	#define TIM2_ETR_GPIO ((uint32_t)0x0U)
AnnaBridge	189:f392fc9709a3	119	#define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 \| TIM2_OR_ETR_RMP_0)
AnnaBridge	189:f392fc9709a3	120	#define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 \| TIM2_OR_ETR_RMP_0)
AnnaBridge	189:f392fc9709a3	121	#define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 \| TIM2_OR_ETR_RMP_1)
AnnaBridge	189:f392fc9709a3	122	#define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP
AnnaBridge	189:f392fc9709a3	123
AnnaBridge	189:f392fc9709a3	124	#else
AnnaBridge	189:f392fc9709a3	125
AnnaBridge	189:f392fc9709a3	126	#define TIM2_ETR_GPIO ((uint32_t)0x0U)
AnnaBridge	189:f392fc9709a3	127	#define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2
AnnaBridge	189:f392fc9709a3	128	#define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 \| TIM2_OR_ETR_RMP_0)
AnnaBridge	189:f392fc9709a3	129	#define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 \| TIM2_OR_ETR_RMP_1)
AnnaBridge	189:f392fc9709a3	130	#define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP
AnnaBridge	189:f392fc9709a3	131
AnnaBridge	189:f392fc9709a3	132	#endif
AnnaBridge	189:f392fc9709a3	133
AnnaBridge	189:f392fc9709a3	134
AnnaBridge	189:f392fc9709a3	135
AnnaBridge	189:f392fc9709a3	136	#define TIM2_TI4_GPIO ((uint32_t)0x0U)
AnnaBridge	189:f392fc9709a3	137	#define TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_0
AnnaBridge	189:f392fc9709a3	138	#define TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_1
AnnaBridge	189:f392fc9709a3	139
AnnaBridge	189:f392fc9709a3	140	#define TIM21_ETR_GPIO ((uint32_t)0x0U)
AnnaBridge	189:f392fc9709a3	141	#define TIM21_ETR_COMP2_OUT TIM21_OR_ETR_RMP_0
AnnaBridge	189:f392fc9709a3	142	#define TIM21_ETR_COMP1_OUT TIM21_OR_ETR_RMP_1
AnnaBridge	189:f392fc9709a3	143	#define TIM21_ETR_LSE TIM21_OR_ETR_RMP
AnnaBridge	189:f392fc9709a3	144	#define TIM21_TI1_GPIO ((uint32_t)0x0U)
AnnaBridge	189:f392fc9709a3	145	#define TIM21_TI1_MCO TIM21_OR_TI1_RMP
AnnaBridge	189:f392fc9709a3	146	#define TIM21_TI1_RTC_WKUT_IT TIM21_OR_TI1_RMP_0
AnnaBridge	189:f392fc9709a3	147	#define TIM21_TI1_HSE_RTC TIM21_OR_TI1_RMP_1
AnnaBridge	189:f392fc9709a3	148	#define TIM21_TI1_MSI (TIM21_OR_TI1_RMP_0 \| TIM21_OR_TI1_RMP_1)
AnnaBridge	189:f392fc9709a3	149	#define TIM21_TI1_LSE TIM21_OR_TI1_RMP_2
AnnaBridge	189:f392fc9709a3	150	#define TIM21_TI1_LSI (TIM21_OR_TI1_RMP_2 \| TIM21_OR_TI1_RMP_0)
AnnaBridge	189:f392fc9709a3	151	#define TIM21_TI1_COMP1_OUT (TIM21_OR_TI1_RMP_2 \| TIM21_OR_TI1_RMP_1)
AnnaBridge	189:f392fc9709a3	152	#define TIM21_TI2_GPIO ((uint32_t)0x0U)
AnnaBridge	189:f392fc9709a3	153	#define TIM21_TI2_COMP2_OUT TIM21_OR_TI2_RMP
AnnaBridge	189:f392fc9709a3	154
AnnaBridge	189:f392fc9709a3	155	#if !defined(STM32L011xx) && !defined(STM32L021xx)
AnnaBridge	189:f392fc9709a3	156	#define TIM22_ETR_GPIO ((uint32_t)0x0U)
AnnaBridge	189:f392fc9709a3	157	#define TIM22_ETR_COMP2_OUT TIM22_OR_ETR_RMP_0
AnnaBridge	189:f392fc9709a3	158	#define TIM22_ETR_COMP1_OUT TIM22_OR_ETR_RMP_1
AnnaBridge	189:f392fc9709a3	159	#define TIM22_ETR_LSE TIM22_OR_ETR_RMP
AnnaBridge	189:f392fc9709a3	160	#define TIM22_TI1_GPIO1 ((uint32_t)0x0U)
AnnaBridge	189:f392fc9709a3	161	#define TIM22_TI1_COMP2_OUT TIM22_OR_TI1_RMP_0
AnnaBridge	189:f392fc9709a3	162	#define TIM22_TI1_COMP1_OUT TIM22_OR_TI1_RMP_1
AnnaBridge	189:f392fc9709a3	163	#define TIM22_TI1_GPIO2 TIM22_OR_TI1_RMP
AnnaBridge	189:f392fc9709a3	164	#endif
AnnaBridge	189:f392fc9709a3	165
AnnaBridge	189:f392fc9709a3	166	#if defined (STM32L071xx) \|\| defined (STM32L072xx) \|\| defined (STM32L073xx) \
AnnaBridge	189:f392fc9709a3	167	\|\| defined (STM32L081xx) \|\| defined (STM32L082xx) \|\| defined (STM32L083xx)
AnnaBridge	189:f392fc9709a3	168
AnnaBridge	189:f392fc9709a3	169	#define TIM3_TI4_GPIO_DEF ((uint32_t)0x0U)
AnnaBridge	189:f392fc9709a3	170	#define TIM3_TI4_GPIOC9_AF2 TIM3_OR_TI4_RMP
AnnaBridge	189:f392fc9709a3	171	#define TIM3_TI2_GPIO_DEF ((uint32_t)0x0U)
AnnaBridge	189:f392fc9709a3	172	#define TIM3_TI2_GPIOB5_AF4 TIM3_OR_TI2_RMP
AnnaBridge	189:f392fc9709a3	173	#define TIM3_TI1_USB_SOF ((uint32_t)0x0U)
AnnaBridge	189:f392fc9709a3	174	#define TIM3_TI1_GPIO TIM3_OR_TI1_RMP
AnnaBridge	189:f392fc9709a3	175	#define TIM3_ETR_GPIO ((uint32_t)0x0U)
AnnaBridge	189:f392fc9709a3	176	#define TIM3_ETR_HSI TIM3_OR_ETR_RMP_1
AnnaBridge	189:f392fc9709a3	177
AnnaBridge	189:f392fc9709a3	178	#endif /defined (STM32L07Xxx) or defined (STM32L08Xxx) /
AnnaBridge	189:f392fc9709a3	179
AnnaBridge	189:f392fc9709a3	180
AnnaBridge	189:f392fc9709a3	181	#if defined (STM32L071xx) \|\| defined (STM32L072xx) \|\| defined (STM32L073xx) \
AnnaBridge	189:f392fc9709a3	182	\|\| defined (STM32L081xx) \|\| defined (STM32L082xx) \|\| defined (STM32L083xx)
AnnaBridge	189:f392fc9709a3	183
AnnaBridge	189:f392fc9709a3	184
AnnaBridge	189:f392fc9709a3	185	#define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \
AnnaBridge	189:f392fc9709a3	186	((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP \| TIM2_OR_ETR_RMP))) \|\| \
AnnaBridge	189:f392fc9709a3	187	(((__INSTANCE__) == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP \| TIM22_OR_ETR_RMP))) \|\| \
AnnaBridge	189:f392fc9709a3	188	(((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP \| TIM21_OR_TI1_RMP \| TIM21_OR_TI2_RMP))) \|\| \
AnnaBridge	189:f392fc9709a3	189	(((__INSTANCE__) == TIM3) && ((__TIM_REMAP__) <= (TIM3_OR_ETR_RMP \| TIM3_OR_TI1_RMP \| TIM3_OR_TI2_RMP \| TIM3_OR_TI4_RMP))))
AnnaBridge	189:f392fc9709a3	190
AnnaBridge	189:f392fc9709a3	191	#define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	192	((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	193	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
AnnaBridge	189:f392fc9709a3	194	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
AnnaBridge	189:f392fc9709a3	195	((__CHANNEL__) == TIM_CHANNEL_4))) \|\| \
AnnaBridge	189:f392fc9709a3	196	(((__INSTANCE__) == TIM3) && (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	197	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
AnnaBridge	189:f392fc9709a3	198	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
AnnaBridge	189:f392fc9709a3	199	((__CHANNEL__) == TIM_CHANNEL_4))) \|\| \
AnnaBridge	189:f392fc9709a3	200	(((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	201	((__CHANNEL__) == TIM_CHANNEL_2))) \|\| \
AnnaBridge	189:f392fc9709a3	202	(((__INSTANCE__) == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	203	((__CHANNEL__) == TIM_CHANNEL_2))))
AnnaBridge	189:f392fc9709a3	204
AnnaBridge	189:f392fc9709a3	205	#elif defined (STM32L011xx) \|\| defined (STM32L021xx)
AnnaBridge	189:f392fc9709a3	206
AnnaBridge	189:f392fc9709a3	207	#define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \
AnnaBridge	189:f392fc9709a3	208	((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP \| TIM2_OR_ETR_RMP))) \|\| \
AnnaBridge	189:f392fc9709a3	209	(((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP \| TIM21_OR_TI1_RMP \| TIM21_OR_TI2_RMP))))
AnnaBridge	189:f392fc9709a3	210
AnnaBridge	189:f392fc9709a3	211	#define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	212	((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	213	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
AnnaBridge	189:f392fc9709a3	214	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
AnnaBridge	189:f392fc9709a3	215	((__CHANNEL__) == TIM_CHANNEL_4))) \|\| \
AnnaBridge	189:f392fc9709a3	216	(((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	217	((__CHANNEL__) == TIM_CHANNEL_2))))
AnnaBridge	189:f392fc9709a3	218
AnnaBridge	189:f392fc9709a3	219	#else
AnnaBridge	189:f392fc9709a3	220
AnnaBridge	189:f392fc9709a3	221	#define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \
AnnaBridge	189:f392fc9709a3	222	((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP \| TIM2_OR_ETR_RMP))) \|\| \
AnnaBridge	189:f392fc9709a3	223	(((__INSTANCE__) == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP \| TIM22_OR_ETR_RMP))) \|\| \
AnnaBridge	189:f392fc9709a3	224	(((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP \| TIM21_OR_TI1_RMP \| TIM21_OR_TI2_RMP))))
AnnaBridge	189:f392fc9709a3	225
AnnaBridge	189:f392fc9709a3	226	#define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	227	((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	228	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
AnnaBridge	189:f392fc9709a3	229	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
AnnaBridge	189:f392fc9709a3	230	((__CHANNEL__) == TIM_CHANNEL_4))) \|\| \
AnnaBridge	189:f392fc9709a3	231	(((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	232	((__CHANNEL__) == TIM_CHANNEL_2))) \|\| \
AnnaBridge	189:f392fc9709a3	233	(((__INSTANCE__) == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	234	((__CHANNEL__) == TIM_CHANNEL_2))))
AnnaBridge	189:f392fc9709a3	235
AnnaBridge	189:f392fc9709a3	236	#endif /defined (STM32L07Xxx) or defined (STM32L08Xxx) /
AnnaBridge	189:f392fc9709a3	237
AnnaBridge	189:f392fc9709a3	238
AnnaBridge	189:f392fc9709a3	239	/**
AnnaBridge	189:f392fc9709a3	240	* @}
AnnaBridge	189:f392fc9709a3	241	*/
AnnaBridge	189:f392fc9709a3	242
AnnaBridge	189:f392fc9709a3	243	/**
AnnaBridge	189:f392fc9709a3	244	* @}
AnnaBridge	189:f392fc9709a3	245	*/
AnnaBridge	189:f392fc9709a3	246
AnnaBridge	189:f392fc9709a3	247
AnnaBridge	189:f392fc9709a3	248	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	249	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	250	/* Control functions ***********************************************************/
AnnaBridge	189:f392fc9709a3	251
AnnaBridge	189:f392fc9709a3	252	/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
AnnaBridge	189:f392fc9709a3	253	* @{
AnnaBridge	189:f392fc9709a3	254	*/
AnnaBridge	189:f392fc9709a3	255
AnnaBridge	189:f392fc9709a3	256	/** @defgroup TIMEx_Exported_Functions_Group1 TIMEx Peripheral Control functions
AnnaBridge	189:f392fc9709a3	257	* @{
AnnaBridge	189:f392fc9709a3	258	*/
AnnaBridge	189:f392fc9709a3	259
AnnaBridge	189:f392fc9709a3	260	HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
AnnaBridge	189:f392fc9709a3	261	HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef htim, TIM_MasterConfigTypeDef sMasterConfig);
AnnaBridge	189:f392fc9709a3	262
AnnaBridge	189:f392fc9709a3	263	/**
AnnaBridge	189:f392fc9709a3	264	* @}
AnnaBridge	189:f392fc9709a3	265	*/
AnnaBridge	189:f392fc9709a3	266
AnnaBridge	189:f392fc9709a3	267	/**
AnnaBridge	189:f392fc9709a3	268	* @}
AnnaBridge	189:f392fc9709a3	269	*/
AnnaBridge	189:f392fc9709a3	270
AnnaBridge	189:f392fc9709a3	271	/**
AnnaBridge	189:f392fc9709a3	272	* @}
AnnaBridge	189:f392fc9709a3	273	*/
AnnaBridge	189:f392fc9709a3	274
AnnaBridge	189:f392fc9709a3	275	/**
AnnaBridge	189:f392fc9709a3	276	* @}
AnnaBridge	189:f392fc9709a3	277	*/
AnnaBridge	189:f392fc9709a3	278	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	279	}
AnnaBridge	189:f392fc9709a3	280	#endif
AnnaBridge	189:f392fc9709a3	281
AnnaBridge	189:f392fc9709a3	282	#endif /* __STM32L0xx_HAL_TIM_EX_H */
AnnaBridge	189:f392fc9709a3	283
AnnaBridge	189:f392fc9709a3	284	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
AnnaBridge	189:f392fc9709a3	285