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cmsis/BUILD/mbed/TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/stm32l0xx_hal_tim.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l0xx_hal_tim.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of TIM HAL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L0xx_HAL_TIM_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L0xx_HAL_TIM_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	45	#include "stm32l0xx_hal_def.h"
AnnaBridge	189:f392fc9709a3	46
AnnaBridge	189:f392fc9709a3	47	/** @addtogroup STM32L0xx_HAL_Driver
AnnaBridge	189:f392fc9709a3	48	* @{
AnnaBridge	189:f392fc9709a3	49	*/
AnnaBridge	189:f392fc9709a3	50
AnnaBridge	189:f392fc9709a3	51	/** @defgroup TIM TIM (Timer)
AnnaBridge	189:f392fc9709a3	52	* @{
AnnaBridge	189:f392fc9709a3	53	*/
AnnaBridge	189:f392fc9709a3	54
AnnaBridge	189:f392fc9709a3	55	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	56
AnnaBridge	189:f392fc9709a3	57	/** @defgroup TIM_Exported_Types TIM Exported Types
AnnaBridge	189:f392fc9709a3	58	* @{
AnnaBridge	189:f392fc9709a3	59	*/
AnnaBridge	189:f392fc9709a3	60
AnnaBridge	189:f392fc9709a3	61	/** @defgroup TIM_Base_Configuration TIM base configuration structure
AnnaBridge	189:f392fc9709a3	62	* @{
AnnaBridge	189:f392fc9709a3	63	*/
AnnaBridge	189:f392fc9709a3	64	/**
AnnaBridge	189:f392fc9709a3	65	* @brief TIM Time base Configuration Structure definition
AnnaBridge	189:f392fc9709a3	66	*/
AnnaBridge	189:f392fc9709a3	67	typedef struct
AnnaBridge	189:f392fc9709a3	68	{
AnnaBridge	189:f392fc9709a3	69	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge	189:f392fc9709a3	70	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge	189:f392fc9709a3	71
AnnaBridge	189:f392fc9709a3	72	uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge	189:f392fc9709a3	73	This parameter can be a value of @ref TIM_Counter_Mode */
AnnaBridge	189:f392fc9709a3	74
AnnaBridge	189:f392fc9709a3	75	uint32_t Period; /*!< Specifies the period value to be loaded into the active
AnnaBridge	189:f392fc9709a3	76	Auto-Reload Register at the next update event.
AnnaBridge	189:f392fc9709a3	77	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
AnnaBridge	189:f392fc9709a3	78
AnnaBridge	189:f392fc9709a3	79	uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge	189:f392fc9709a3	80	This parameter can be a value of @ref TIM_ClockDivision */
AnnaBridge	189:f392fc9709a3	81	} TIM_Base_InitTypeDef;
AnnaBridge	189:f392fc9709a3	82	/**
AnnaBridge	189:f392fc9709a3	83	* @}
AnnaBridge	189:f392fc9709a3	84	*/
AnnaBridge	189:f392fc9709a3	85
AnnaBridge	189:f392fc9709a3	86	/** @defgroup TIM_Output_Configuration TIM output compare configuration structure
AnnaBridge	189:f392fc9709a3	87	* @{
AnnaBridge	189:f392fc9709a3	88	*/
AnnaBridge	189:f392fc9709a3	89
AnnaBridge	189:f392fc9709a3	90	/**
AnnaBridge	189:f392fc9709a3	91	* @brief TIM Output Compare Configuration Structure definition
AnnaBridge	189:f392fc9709a3	92	*/
AnnaBridge	189:f392fc9709a3	93
AnnaBridge	189:f392fc9709a3	94	typedef struct
AnnaBridge	189:f392fc9709a3	95	{
AnnaBridge	189:f392fc9709a3	96	uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge	189:f392fc9709a3	97	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge	189:f392fc9709a3	98
AnnaBridge	189:f392fc9709a3	99	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge	189:f392fc9709a3	100	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge	189:f392fc9709a3	101
AnnaBridge	189:f392fc9709a3	102	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	189:f392fc9709a3	103	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge	189:f392fc9709a3	104
AnnaBridge	189:f392fc9709a3	105	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
AnnaBridge	189:f392fc9709a3	106	This parameter can be a value of @ref TIM_Output_Fast_State
AnnaBridge	189:f392fc9709a3	107	@note This parameter is valid only in PWM1 and PWM2 mode. */
AnnaBridge	189:f392fc9709a3	108
AnnaBridge	189:f392fc9709a3	109	} TIM_OC_InitTypeDef;
AnnaBridge	189:f392fc9709a3	110	/**
AnnaBridge	189:f392fc9709a3	111	* @}
AnnaBridge	189:f392fc9709a3	112	*/
AnnaBridge	189:f392fc9709a3	113
AnnaBridge	189:f392fc9709a3	114	/** @defgroup TIM_OnePulse_Configuration TIM One Pulse configuration structure
AnnaBridge	189:f392fc9709a3	115	* @{
AnnaBridge	189:f392fc9709a3	116	*/
AnnaBridge	189:f392fc9709a3	117	/**
AnnaBridge	189:f392fc9709a3	118	* @brief TIM One Pulse Mode Configuration Structure definition
AnnaBridge	189:f392fc9709a3	119	*/
AnnaBridge	189:f392fc9709a3	120	typedef struct
AnnaBridge	189:f392fc9709a3	121	{
AnnaBridge	189:f392fc9709a3	122	uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge	189:f392fc9709a3	123	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge	189:f392fc9709a3	124
AnnaBridge	189:f392fc9709a3	125	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge	189:f392fc9709a3	126	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge	189:f392fc9709a3	127
AnnaBridge	189:f392fc9709a3	128	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	189:f392fc9709a3	129	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge	189:f392fc9709a3	130
AnnaBridge	189:f392fc9709a3	131
AnnaBridge	189:f392fc9709a3	132	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	189:f392fc9709a3	133	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge	189:f392fc9709a3	134
AnnaBridge	189:f392fc9709a3	135	uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge	189:f392fc9709a3	136	This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge	189:f392fc9709a3	137
AnnaBridge	189:f392fc9709a3	138	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	189:f392fc9709a3	139	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	140	} TIM_OnePulse_InitTypeDef;
AnnaBridge	189:f392fc9709a3	141	/**
AnnaBridge	189:f392fc9709a3	142	* @}
AnnaBridge	189:f392fc9709a3	143	*/
AnnaBridge	189:f392fc9709a3	144
AnnaBridge	189:f392fc9709a3	145	/** @defgroup TIM_Input_Capture TIM input capture configuration structure
AnnaBridge	189:f392fc9709a3	146	* @{
AnnaBridge	189:f392fc9709a3	147	*/
AnnaBridge	189:f392fc9709a3	148	/**
AnnaBridge	189:f392fc9709a3	149	* @brief TIM Input Capture Configuration Structure definition
AnnaBridge	189:f392fc9709a3	150	*/
AnnaBridge	189:f392fc9709a3	151
AnnaBridge	189:f392fc9709a3	152	typedef struct
AnnaBridge	189:f392fc9709a3	153	{
AnnaBridge	189:f392fc9709a3	154	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	189:f392fc9709a3	155	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge	189:f392fc9709a3	156
AnnaBridge	189:f392fc9709a3	157	uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge	189:f392fc9709a3	158	This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge	189:f392fc9709a3	159
AnnaBridge	189:f392fc9709a3	160	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	189:f392fc9709a3	161	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge	189:f392fc9709a3	162
AnnaBridge	189:f392fc9709a3	163	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	189:f392fc9709a3	164	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	165	} TIM_IC_InitTypeDef;
AnnaBridge	189:f392fc9709a3	166	/**
AnnaBridge	189:f392fc9709a3	167	* @}
AnnaBridge	189:f392fc9709a3	168	*/
AnnaBridge	189:f392fc9709a3	169
AnnaBridge	189:f392fc9709a3	170	/** @defgroup TIM_Encoder TIM encoder configuration structure
AnnaBridge	189:f392fc9709a3	171	* @{
AnnaBridge	189:f392fc9709a3	172	*/
AnnaBridge	189:f392fc9709a3	173	/**
AnnaBridge	189:f392fc9709a3	174	* @brief TIM Encoder Configuration Structure definition
AnnaBridge	189:f392fc9709a3	175	*/
AnnaBridge	189:f392fc9709a3	176
AnnaBridge	189:f392fc9709a3	177	typedef struct
AnnaBridge	189:f392fc9709a3	178	{
AnnaBridge	189:f392fc9709a3	179	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
AnnaBridge	189:f392fc9709a3	180	This parameter can be a value of @ref TIM_Encoder_Mode */
AnnaBridge	189:f392fc9709a3	181
AnnaBridge	189:f392fc9709a3	182	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	189:f392fc9709a3	183	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge	189:f392fc9709a3	184
AnnaBridge	189:f392fc9709a3	185	uint32_t IC1Selection; /*!< Specifies the input.
AnnaBridge	189:f392fc9709a3	186	This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge	189:f392fc9709a3	187
AnnaBridge	189:f392fc9709a3	188	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	189:f392fc9709a3	189	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge	189:f392fc9709a3	190
AnnaBridge	189:f392fc9709a3	191	uint32_t IC1Filter; /*!< Specifies the input capture filter.
AnnaBridge	189:f392fc9709a3	192	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	193
AnnaBridge	189:f392fc9709a3	194	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	189:f392fc9709a3	195	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge	189:f392fc9709a3	196
AnnaBridge	189:f392fc9709a3	197	uint32_t IC2Selection; /*!< Specifies the input.
AnnaBridge	189:f392fc9709a3	198	This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge	189:f392fc9709a3	199
AnnaBridge	189:f392fc9709a3	200	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	189:f392fc9709a3	201	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge	189:f392fc9709a3	202
AnnaBridge	189:f392fc9709a3	203	uint32_t IC2Filter; /*!< Specifies the input capture filter.
AnnaBridge	189:f392fc9709a3	204	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	205	} TIM_Encoder_InitTypeDef;
AnnaBridge	189:f392fc9709a3	206	/**
AnnaBridge	189:f392fc9709a3	207	* @}
AnnaBridge	189:f392fc9709a3	208	*/
AnnaBridge	189:f392fc9709a3	209
AnnaBridge	189:f392fc9709a3	210	/** @defgroup TIM_Clock_Configuration TIM clock configuration structure
AnnaBridge	189:f392fc9709a3	211	* @{
AnnaBridge	189:f392fc9709a3	212	*/
AnnaBridge	189:f392fc9709a3	213	/**
AnnaBridge	189:f392fc9709a3	214	* @brief Clock Configuration Handle Structure definition
AnnaBridge	189:f392fc9709a3	215	*/
AnnaBridge	189:f392fc9709a3	216	typedef struct
AnnaBridge	189:f392fc9709a3	217	{
AnnaBridge	189:f392fc9709a3	218	uint32_t ClockSource; /*!< TIM clock sources.
AnnaBridge	189:f392fc9709a3	219	This parameter can be a value of @ref TIM_Clock_Source */
AnnaBridge	189:f392fc9709a3	220	uint32_t ClockPolarity; /*!< TIM clock polarity.
AnnaBridge	189:f392fc9709a3	221	This parameter can be a value of @ref TIM_Clock_Polarity */
AnnaBridge	189:f392fc9709a3	222	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
AnnaBridge	189:f392fc9709a3	223	This parameter can be a value of @ref TIM_Clock_Prescaler */
AnnaBridge	189:f392fc9709a3	224	uint32_t ClockFilter; /*!< TIM clock filter.
AnnaBridge	189:f392fc9709a3	225	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	226	}TIM_ClockConfigTypeDef;
AnnaBridge	189:f392fc9709a3	227	/**
AnnaBridge	189:f392fc9709a3	228	* @}
AnnaBridge	189:f392fc9709a3	229	*/
AnnaBridge	189:f392fc9709a3	230
AnnaBridge	189:f392fc9709a3	231	/** @defgroup TIM_Clear_Input_Configuration TIM clear input configuration structure
AnnaBridge	189:f392fc9709a3	232	* @{
AnnaBridge	189:f392fc9709a3	233	*/
AnnaBridge	189:f392fc9709a3	234	/**
AnnaBridge	189:f392fc9709a3	235	* @brief Clear Input Configuration Handle Structure definition
AnnaBridge	189:f392fc9709a3	236	*/
AnnaBridge	189:f392fc9709a3	237	typedef struct
AnnaBridge	189:f392fc9709a3	238	{
AnnaBridge	189:f392fc9709a3	239	uint32_t ClearInputState; /*!< TIM clear Input state.
AnnaBridge	189:f392fc9709a3	240	This parameter can be ENABLE or DISABLE */
AnnaBridge	189:f392fc9709a3	241	uint32_t ClearInputSource; /*!< TIM clear Input sources.
AnnaBridge	189:f392fc9709a3	242	This parameter can be a value of @ref TIM_ClearInput_Source */
AnnaBridge	189:f392fc9709a3	243	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
AnnaBridge	189:f392fc9709a3	244	This parameter can be a value of @ref TIM_ClearInput_Polarity */
AnnaBridge	189:f392fc9709a3	245	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
AnnaBridge	189:f392fc9709a3	246	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
AnnaBridge	189:f392fc9709a3	247	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
AnnaBridge	189:f392fc9709a3	248	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	249	}TIM_ClearInputConfigTypeDef;
AnnaBridge	189:f392fc9709a3	250	/**
AnnaBridge	189:f392fc9709a3	251	* @}
AnnaBridge	189:f392fc9709a3	252	*/
AnnaBridge	189:f392fc9709a3	253
AnnaBridge	189:f392fc9709a3	254	/** @defgroup TIM_Slave_Configuratio TIM slave configuration structure
AnnaBridge	189:f392fc9709a3	255	* @{
AnnaBridge	189:f392fc9709a3	256	*/
AnnaBridge	189:f392fc9709a3	257	/**
AnnaBridge	189:f392fc9709a3	258	* @brief TIM Slave configuration Structure definition
AnnaBridge	189:f392fc9709a3	259	*/
AnnaBridge	189:f392fc9709a3	260	typedef struct {
AnnaBridge	189:f392fc9709a3	261	uint32_t SlaveMode; /*!< Slave mode selection.
AnnaBridge	189:f392fc9709a3	262	This parameter can be a value of @ref TIM_Slave_Mode */
AnnaBridge	189:f392fc9709a3	263	uint32_t InputTrigger; /*!< Input Trigger source.
AnnaBridge	189:f392fc9709a3	264	This parameter can be a value of @ref TIM_Trigger_Selection */
AnnaBridge	189:f392fc9709a3	265	uint32_t TriggerPolarity; /*!< Input Trigger polarity.
AnnaBridge	189:f392fc9709a3	266	This parameter can be a value of @ref TIM_Trigger_Polarity */
AnnaBridge	189:f392fc9709a3	267	uint32_t TriggerPrescaler; /*!< Input trigger prescaler.
AnnaBridge	189:f392fc9709a3	268	This parameter can be a value of @ref TIM_Trigger_Prescaler */
AnnaBridge	189:f392fc9709a3	269	uint32_t TriggerFilter; /*!< Input trigger filter.
AnnaBridge	189:f392fc9709a3	270	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge	189:f392fc9709a3	271
AnnaBridge	189:f392fc9709a3	272	}TIM_SlaveConfigTypeDef;
AnnaBridge	189:f392fc9709a3	273	/**
AnnaBridge	189:f392fc9709a3	274	* @}
AnnaBridge	189:f392fc9709a3	275	*/
AnnaBridge	189:f392fc9709a3	276
AnnaBridge	189:f392fc9709a3	277	/** @defgroup TIM_State_Definition TIM state definition
AnnaBridge	189:f392fc9709a3	278	* @{
AnnaBridge	189:f392fc9709a3	279	*/
AnnaBridge	189:f392fc9709a3	280	/**
AnnaBridge	189:f392fc9709a3	281	* @brief HAL State structures definition
AnnaBridge	189:f392fc9709a3	282	*/
AnnaBridge	189:f392fc9709a3	283	typedef enum
AnnaBridge	189:f392fc9709a3	284	{
AnnaBridge	189:f392fc9709a3	285	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
AnnaBridge	189:f392fc9709a3	286	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
AnnaBridge	189:f392fc9709a3	287	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
AnnaBridge	189:f392fc9709a3	288	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
AnnaBridge	189:f392fc9709a3	289	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
AnnaBridge	189:f392fc9709a3	290	}HAL_TIM_StateTypeDef;
AnnaBridge	189:f392fc9709a3	291	/**
AnnaBridge	189:f392fc9709a3	292	* @}
AnnaBridge	189:f392fc9709a3	293	*/
AnnaBridge	189:f392fc9709a3	294
AnnaBridge	189:f392fc9709a3	295	/** @defgroup TIM_Active_Channel TIM active channel definition
AnnaBridge	189:f392fc9709a3	296	* @{
AnnaBridge	189:f392fc9709a3	297	*/
AnnaBridge	189:f392fc9709a3	298	/**
AnnaBridge	189:f392fc9709a3	299	* @brief HAL Active channel structures definition
AnnaBridge	189:f392fc9709a3	300	*/
AnnaBridge	189:f392fc9709a3	301	typedef enum
AnnaBridge	189:f392fc9709a3	302	{
AnnaBridge	189:f392fc9709a3	303	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
AnnaBridge	189:f392fc9709a3	304	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
AnnaBridge	189:f392fc9709a3	305	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
AnnaBridge	189:f392fc9709a3	306	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
AnnaBridge	189:f392fc9709a3	307	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
AnnaBridge	189:f392fc9709a3	308	}HAL_TIM_ActiveChannel;
AnnaBridge	189:f392fc9709a3	309	/**
AnnaBridge	189:f392fc9709a3	310	* @}
AnnaBridge	189:f392fc9709a3	311	*/
AnnaBridge	189:f392fc9709a3	312
AnnaBridge	189:f392fc9709a3	313	/** @defgroup TIM_Handle TIM handler
AnnaBridge	189:f392fc9709a3	314	* @{
AnnaBridge	189:f392fc9709a3	315	*/
AnnaBridge	189:f392fc9709a3	316	/**
AnnaBridge	189:f392fc9709a3	317	* @brief TIM Time Base Handle Structure definition
AnnaBridge	189:f392fc9709a3	318	*/
AnnaBridge	189:f392fc9709a3	319	typedef struct
AnnaBridge	189:f392fc9709a3	320	{
AnnaBridge	189:f392fc9709a3	321	TIM_TypeDef Instance; /!< Register base address */
AnnaBridge	189:f392fc9709a3	322	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
AnnaBridge	189:f392fc9709a3	323	HAL_TIM_ActiveChannel Channel; /!< Active channel /
AnnaBridge	189:f392fc9709a3	324	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
AnnaBridge	189:f392fc9709a3	325	This array is accessed by a @ref DMA_Handle_index */
AnnaBridge	189:f392fc9709a3	326	HAL_LockTypeDef Lock; /!< Locking object /
AnnaBridge	189:f392fc9709a3	327	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
AnnaBridge	189:f392fc9709a3	328	}TIM_HandleTypeDef;
AnnaBridge	189:f392fc9709a3	329	/**
AnnaBridge	189:f392fc9709a3	330	* @}
AnnaBridge	189:f392fc9709a3	331	*/
AnnaBridge	189:f392fc9709a3	332
AnnaBridge	189:f392fc9709a3	333	/**
AnnaBridge	189:f392fc9709a3	334	* @}
AnnaBridge	189:f392fc9709a3	335	*/
AnnaBridge	189:f392fc9709a3	336	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	337	/** @defgroup TIM_Exported_Constants TIM Exported Constants
AnnaBridge	189:f392fc9709a3	338	* @{
AnnaBridge	189:f392fc9709a3	339	*/
AnnaBridge	189:f392fc9709a3	340
AnnaBridge	189:f392fc9709a3	341
AnnaBridge	189:f392fc9709a3	342	#define IS_TIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0xFFFFU)
AnnaBridge	189:f392fc9709a3	343
AnnaBridge	189:f392fc9709a3	344	#define IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFU)
AnnaBridge	189:f392fc9709a3	345
AnnaBridge	189:f392fc9709a3	346
AnnaBridge	189:f392fc9709a3	347	/** @defgroup TIM_Input_Channel_Polarity Input channel polarity
AnnaBridge	189:f392fc9709a3	348	* @{
AnnaBridge	189:f392fc9709a3	349	*/
AnnaBridge	189:f392fc9709a3	350	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /!< Polarity for TIx source /
AnnaBridge	189:f392fc9709a3	351	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
AnnaBridge	189:f392fc9709a3	352	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
AnnaBridge	189:f392fc9709a3	353	/**
AnnaBridge	189:f392fc9709a3	354	* @}
AnnaBridge	189:f392fc9709a3	355	*/
AnnaBridge	189:f392fc9709a3	356
AnnaBridge	189:f392fc9709a3	357	/** @defgroup TIM_ETR_Polarity ETR polarity
AnnaBridge	189:f392fc9709a3	358	* @{
AnnaBridge	189:f392fc9709a3	359	*/
AnnaBridge	189:f392fc9709a3	360	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
AnnaBridge	189:f392fc9709a3	361	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /!< Polarity for ETR source /
AnnaBridge	189:f392fc9709a3	362	/**
AnnaBridge	189:f392fc9709a3	363	* @}
AnnaBridge	189:f392fc9709a3	364	*/
AnnaBridge	189:f392fc9709a3	365
AnnaBridge	189:f392fc9709a3	366	/** @defgroup TIM_ETR_Prescaler ETR prescaler
AnnaBridge	189:f392fc9709a3	367	* @{
AnnaBridge	189:f392fc9709a3	368	*/
AnnaBridge	189:f392fc9709a3	369	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /!< No prescaler is used /
AnnaBridge	189:f392fc9709a3	370	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
AnnaBridge	189:f392fc9709a3	371	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
AnnaBridge	189:f392fc9709a3	372	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
AnnaBridge	189:f392fc9709a3	373	/**
AnnaBridge	189:f392fc9709a3	374	* @}
AnnaBridge	189:f392fc9709a3	375	*/
AnnaBridge	189:f392fc9709a3	376
AnnaBridge	189:f392fc9709a3	377	/** @defgroup TIM_Counter_Mode Counter mode
AnnaBridge	189:f392fc9709a3	378	* @{
AnnaBridge	189:f392fc9709a3	379	*/
AnnaBridge	189:f392fc9709a3	380	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	381	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
AnnaBridge	189:f392fc9709a3	382	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
AnnaBridge	189:f392fc9709a3	383	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
AnnaBridge	189:f392fc9709a3	384	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
AnnaBridge	189:f392fc9709a3	385	/**
AnnaBridge	189:f392fc9709a3	386	* @}
AnnaBridge	189:f392fc9709a3	387	*/
AnnaBridge	189:f392fc9709a3	388	#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) \|\| \
AnnaBridge	189:f392fc9709a3	389	((__MODE__) == TIM_COUNTERMODE_DOWN) \|\| \
AnnaBridge	189:f392fc9709a3	390	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
AnnaBridge	189:f392fc9709a3	391	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
AnnaBridge	189:f392fc9709a3	392	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
AnnaBridge	189:f392fc9709a3	393
AnnaBridge	189:f392fc9709a3	394
AnnaBridge	189:f392fc9709a3	395
AnnaBridge	189:f392fc9709a3	396
AnnaBridge	189:f392fc9709a3	397	/** @defgroup TIM_ClockDivision Clock division
AnnaBridge	189:f392fc9709a3	398	* @{
AnnaBridge	189:f392fc9709a3	399	*/
AnnaBridge	189:f392fc9709a3	400	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	401	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
AnnaBridge	189:f392fc9709a3	402	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
AnnaBridge	189:f392fc9709a3	403	/**
AnnaBridge	189:f392fc9709a3	404	* @}
AnnaBridge	189:f392fc9709a3	405	*/
AnnaBridge	189:f392fc9709a3	406	#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) \|\| \
AnnaBridge	189:f392fc9709a3	407	((__DIV__) == TIM_CLOCKDIVISION_DIV2) \|\| \
AnnaBridge	189:f392fc9709a3	408	((__DIV__) == TIM_CLOCKDIVISION_DIV4))
AnnaBridge	189:f392fc9709a3	409
AnnaBridge	189:f392fc9709a3	410
AnnaBridge	189:f392fc9709a3	411	/** @defgroup TIM_Output_Compare_and_PWM_modes Output compare and PWM modes
AnnaBridge	189:f392fc9709a3	412	* @{
AnnaBridge	189:f392fc9709a3	413	*/
AnnaBridge	189:f392fc9709a3	414	#define TIM_OCMODE_TIMING ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	415	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
AnnaBridge	189:f392fc9709a3	416	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
AnnaBridge	189:f392fc9709a3	417	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
AnnaBridge	189:f392fc9709a3	418	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
AnnaBridge	189:f392fc9709a3	419	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
AnnaBridge	189:f392fc9709a3	420	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
AnnaBridge	189:f392fc9709a3	421	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
AnnaBridge	189:f392fc9709a3	422	/**
AnnaBridge	189:f392fc9709a3	423	* @}
AnnaBridge	189:f392fc9709a3	424	*/
AnnaBridge	189:f392fc9709a3	425
AnnaBridge	189:f392fc9709a3	426	#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) \|\| \
AnnaBridge	189:f392fc9709a3	427	((__MODE__) == TIM_OCMODE_PWM2))
AnnaBridge	189:f392fc9709a3	428
AnnaBridge	189:f392fc9709a3	429	#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) \|\| \
AnnaBridge	189:f392fc9709a3	430	((__MODE__) == TIM_OCMODE_ACTIVE) \|\| \
AnnaBridge	189:f392fc9709a3	431	((__MODE__) == TIM_OCMODE_INACTIVE) \|\| \
AnnaBridge	189:f392fc9709a3	432	((__MODE__) == TIM_OCMODE_TOGGLE) \|\| \
AnnaBridge	189:f392fc9709a3	433	((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
AnnaBridge	189:f392fc9709a3	434	((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
AnnaBridge	189:f392fc9709a3	435
AnnaBridge	189:f392fc9709a3	436
AnnaBridge	189:f392fc9709a3	437	/** @defgroup TIM_Output_Compare_State Output compare state
AnnaBridge	189:f392fc9709a3	438	* @{
AnnaBridge	189:f392fc9709a3	439	*/
AnnaBridge	189:f392fc9709a3	440	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	441	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
AnnaBridge	189:f392fc9709a3	442	/**
AnnaBridge	189:f392fc9709a3	443	* @}
AnnaBridge	189:f392fc9709a3	444	*/
AnnaBridge	189:f392fc9709a3	445
AnnaBridge	189:f392fc9709a3	446	/** @defgroup TIM_Output_Fast_State Output fast state
AnnaBridge	189:f392fc9709a3	447	* @{
AnnaBridge	189:f392fc9709a3	448	*/
AnnaBridge	189:f392fc9709a3	449	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	450	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
AnnaBridge	189:f392fc9709a3	451	/**
AnnaBridge	189:f392fc9709a3	452	* @}
AnnaBridge	189:f392fc9709a3	453	*/
AnnaBridge	189:f392fc9709a3	454	#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) \|\| \
AnnaBridge	189:f392fc9709a3	455	((__STATE__) == TIM_OCFAST_ENABLE))
AnnaBridge	189:f392fc9709a3	456
AnnaBridge	189:f392fc9709a3	457	/** @defgroup TIM_Output_Compare_N_State Output compare N state
AnnaBridge	189:f392fc9709a3	458	* @{
AnnaBridge	189:f392fc9709a3	459	*/
AnnaBridge	189:f392fc9709a3	460	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	461	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
AnnaBridge	189:f392fc9709a3	462	/**
AnnaBridge	189:f392fc9709a3	463	* @}
AnnaBridge	189:f392fc9709a3	464	*/
AnnaBridge	189:f392fc9709a3	465
AnnaBridge	189:f392fc9709a3	466	/** @defgroup TIM_Output_Compare_Polarity Output compare polarity
AnnaBridge	189:f392fc9709a3	467	* @{
AnnaBridge	189:f392fc9709a3	468	*/
AnnaBridge	189:f392fc9709a3	469	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	470	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
AnnaBridge	189:f392fc9709a3	471	/**
AnnaBridge	189:f392fc9709a3	472	* @}
AnnaBridge	189:f392fc9709a3	473	*/
AnnaBridge	189:f392fc9709a3	474	#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) \|\| \
AnnaBridge	189:f392fc9709a3	475	((__POLARITY__) == TIM_OCPOLARITY_LOW))
AnnaBridge	189:f392fc9709a3	476
AnnaBridge	189:f392fc9709a3	477	/** @defgroup TIM_Channel TIM channels
AnnaBridge	189:f392fc9709a3	478	* @{
AnnaBridge	189:f392fc9709a3	479	*/
AnnaBridge	189:f392fc9709a3	480	#define TIM_CHANNEL_1 ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	481	#define TIM_CHANNEL_2 ((uint32_t)0x0004U)
AnnaBridge	189:f392fc9709a3	482	#define TIM_CHANNEL_3 ((uint32_t)0x0008U)
AnnaBridge	189:f392fc9709a3	483	#define TIM_CHANNEL_4 ((uint32_t)0x000CU)
AnnaBridge	189:f392fc9709a3	484	#define TIM_CHANNEL_ALL ((uint32_t)0x0018U)
AnnaBridge	189:f392fc9709a3	485	/**
AnnaBridge	189:f392fc9709a3	486	* @}
AnnaBridge	189:f392fc9709a3	487	*/
AnnaBridge	189:f392fc9709a3	488
AnnaBridge	189:f392fc9709a3	489	#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	490	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
AnnaBridge	189:f392fc9709a3	491	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
AnnaBridge	189:f392fc9709a3	492	((__CHANNEL__) == TIM_CHANNEL_4) \|\| \
AnnaBridge	189:f392fc9709a3	493	((__CHANNEL__) == TIM_CHANNEL_ALL))
AnnaBridge	189:f392fc9709a3	494
AnnaBridge	189:f392fc9709a3	495	#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	496	((__CHANNEL__) == TIM_CHANNEL_2))
AnnaBridge	189:f392fc9709a3	497
AnnaBridge	189:f392fc9709a3	498
AnnaBridge	189:f392fc9709a3	499	/** @defgroup TIM_Input_Capture_Polarity Input capture polarity
AnnaBridge	189:f392fc9709a3	500	* @{
AnnaBridge	189:f392fc9709a3	501	*/
AnnaBridge	189:f392fc9709a3	502	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
AnnaBridge	189:f392fc9709a3	503	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
AnnaBridge	189:f392fc9709a3	504	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
AnnaBridge	189:f392fc9709a3	505	/**
AnnaBridge	189:f392fc9709a3	506	* @}
AnnaBridge	189:f392fc9709a3	507	*/
AnnaBridge	189:f392fc9709a3	508	#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) \|\| \
AnnaBridge	189:f392fc9709a3	509	((__POLARITY__) == TIM_ICPOLARITY_FALLING) \|\| \
AnnaBridge	189:f392fc9709a3	510	((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
AnnaBridge	189:f392fc9709a3	511
AnnaBridge	189:f392fc9709a3	512
AnnaBridge	189:f392fc9709a3	513	/** @defgroup TIM_Input_Capture_Selection Input capture selection
AnnaBridge	189:f392fc9709a3	514	* @{
AnnaBridge	189:f392fc9709a3	515	*/
AnnaBridge	189:f392fc9709a3	516	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge	189:f392fc9709a3	517	connected to IC1, IC2, IC3 or IC4, respectively */
AnnaBridge	189:f392fc9709a3	518	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge	189:f392fc9709a3	519	connected to IC2, IC1, IC4 or IC3, respectively */
AnnaBridge	189:f392fc9709a3	520	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
AnnaBridge	189:f392fc9709a3	521
AnnaBridge	189:f392fc9709a3	522	#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) \|\| \
AnnaBridge	189:f392fc9709a3	523	((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) \|\| \
AnnaBridge	189:f392fc9709a3	524	((__SELECTION__) == TIM_ICSELECTION_TRC))
AnnaBridge	189:f392fc9709a3	525	/**
AnnaBridge	189:f392fc9709a3	526	* @}
AnnaBridge	189:f392fc9709a3	527	*/
AnnaBridge	189:f392fc9709a3	528
AnnaBridge	189:f392fc9709a3	529	/** @defgroup TIM_Input_Capture_Prescaler Input capture prescaler
AnnaBridge	189:f392fc9709a3	530	* @{
AnnaBridge	189:f392fc9709a3	531	*/
AnnaBridge	189:f392fc9709a3	532	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /!< Capture performed each time an edge is detected on the capture input /
AnnaBridge	189:f392fc9709a3	533	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
AnnaBridge	189:f392fc9709a3	534	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
AnnaBridge	189:f392fc9709a3	535	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
AnnaBridge	189:f392fc9709a3	536	/**
AnnaBridge	189:f392fc9709a3	537	* @}
AnnaBridge	189:f392fc9709a3	538	*/
AnnaBridge	189:f392fc9709a3	539	#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) \|\| \
AnnaBridge	189:f392fc9709a3	540	((__PRESCALER__) == TIM_ICPSC_DIV2) \|\| \
AnnaBridge	189:f392fc9709a3	541	((__PRESCALER__) == TIM_ICPSC_DIV4) \|\| \
AnnaBridge	189:f392fc9709a3	542	((__PRESCALER__) == TIM_ICPSC_DIV8))
AnnaBridge	189:f392fc9709a3	543
AnnaBridge	189:f392fc9709a3	544	/** @defgroup TIM_One_Pulse_Mode One pulse mode
AnnaBridge	189:f392fc9709a3	545	* @{
AnnaBridge	189:f392fc9709a3	546	*/
AnnaBridge	189:f392fc9709a3	547	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
AnnaBridge	189:f392fc9709a3	548	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	549	/**
AnnaBridge	189:f392fc9709a3	550	* @}
AnnaBridge	189:f392fc9709a3	551	*/
AnnaBridge	189:f392fc9709a3	552	#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) \|\| \
AnnaBridge	189:f392fc9709a3	553	((__MODE__) == TIM_OPMODE_REPETITIVE))
AnnaBridge	189:f392fc9709a3	554
AnnaBridge	189:f392fc9709a3	555	/** @defgroup TIM_Encoder_Mode Encoder_Mode
AnnaBridge	189:f392fc9709a3	556	* @{
AnnaBridge	189:f392fc9709a3	557	*/
AnnaBridge	189:f392fc9709a3	558	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
AnnaBridge	189:f392fc9709a3	559	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
AnnaBridge	189:f392fc9709a3	560	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
AnnaBridge	189:f392fc9709a3	561	/**
AnnaBridge	189:f392fc9709a3	562	* @}
AnnaBridge	189:f392fc9709a3	563	*/
AnnaBridge	189:f392fc9709a3	564	#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) \|\| \
AnnaBridge	189:f392fc9709a3	565	((__MODE__) == TIM_ENCODERMODE_TI2) \|\| \
AnnaBridge	189:f392fc9709a3	566	((__MODE__) == TIM_ENCODERMODE_TI12))
AnnaBridge	189:f392fc9709a3	567
AnnaBridge	189:f392fc9709a3	568	/** @defgroup TIM_Interrupt_definition Interrupt definition
AnnaBridge	189:f392fc9709a3	569	* @{
AnnaBridge	189:f392fc9709a3	570	*/
AnnaBridge	189:f392fc9709a3	571	#define TIM_IT_UPDATE (TIM_DIER_UIE)
AnnaBridge	189:f392fc9709a3	572	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
AnnaBridge	189:f392fc9709a3	573	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
AnnaBridge	189:f392fc9709a3	574	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
AnnaBridge	189:f392fc9709a3	575	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
AnnaBridge	189:f392fc9709a3	576	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
AnnaBridge	189:f392fc9709a3	577	/**
AnnaBridge	189:f392fc9709a3	578	* @}
AnnaBridge	189:f392fc9709a3	579	*/
AnnaBridge	189:f392fc9709a3	580
AnnaBridge	189:f392fc9709a3	581	/** @defgroup TIM_DMA_sources DMA sources
AnnaBridge	189:f392fc9709a3	582	* @{
AnnaBridge	189:f392fc9709a3	583	*/
AnnaBridge	189:f392fc9709a3	584	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
AnnaBridge	189:f392fc9709a3	585	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
AnnaBridge	189:f392fc9709a3	586	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
AnnaBridge	189:f392fc9709a3	587	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
AnnaBridge	189:f392fc9709a3	588	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
AnnaBridge	189:f392fc9709a3	589	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
AnnaBridge	189:f392fc9709a3	590	/**
AnnaBridge	189:f392fc9709a3	591	* @}
AnnaBridge	189:f392fc9709a3	592	*/
AnnaBridge	189:f392fc9709a3	593	#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
AnnaBridge	189:f392fc9709a3	594
AnnaBridge	189:f392fc9709a3	595
AnnaBridge	189:f392fc9709a3	596
AnnaBridge	189:f392fc9709a3	597	/** @defgroup TIM_Event_Source Event sources
AnnaBridge	189:f392fc9709a3	598	* @{
AnnaBridge	189:f392fc9709a3	599	*/
AnnaBridge	189:f392fc9709a3	600	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
AnnaBridge	189:f392fc9709a3	601	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
AnnaBridge	189:f392fc9709a3	602	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
AnnaBridge	189:f392fc9709a3	603	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
AnnaBridge	189:f392fc9709a3	604	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
AnnaBridge	189:f392fc9709a3	605	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
AnnaBridge	189:f392fc9709a3	606	/**
AnnaBridge	189:f392fc9709a3	607	* @}
AnnaBridge	189:f392fc9709a3	608	*/
AnnaBridge	189:f392fc9709a3	609	#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
AnnaBridge	189:f392fc9709a3	610
AnnaBridge	189:f392fc9709a3	611
AnnaBridge	189:f392fc9709a3	612	/** @defgroup TIM_Flag_definition Flag definition
AnnaBridge	189:f392fc9709a3	613	* @{
AnnaBridge	189:f392fc9709a3	614	*/
AnnaBridge	189:f392fc9709a3	615	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
AnnaBridge	189:f392fc9709a3	616	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
AnnaBridge	189:f392fc9709a3	617	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
AnnaBridge	189:f392fc9709a3	618	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
AnnaBridge	189:f392fc9709a3	619	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
AnnaBridge	189:f392fc9709a3	620	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
AnnaBridge	189:f392fc9709a3	621	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
AnnaBridge	189:f392fc9709a3	622	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
AnnaBridge	189:f392fc9709a3	623	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
AnnaBridge	189:f392fc9709a3	624	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
AnnaBridge	189:f392fc9709a3	625	/**
AnnaBridge	189:f392fc9709a3	626	* @}
AnnaBridge	189:f392fc9709a3	627	*/
AnnaBridge	189:f392fc9709a3	628
AnnaBridge	189:f392fc9709a3	629	/** @defgroup TIM_Clock_Source Clock source
AnnaBridge	189:f392fc9709a3	630	* @{
AnnaBridge	189:f392fc9709a3	631	*/
AnnaBridge	189:f392fc9709a3	632	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
AnnaBridge	189:f392fc9709a3	633	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
AnnaBridge	189:f392fc9709a3	634	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	635	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
AnnaBridge	189:f392fc9709a3	636	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
AnnaBridge	189:f392fc9709a3	637	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
AnnaBridge	189:f392fc9709a3	638	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
AnnaBridge	189:f392fc9709a3	639	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
AnnaBridge	189:f392fc9709a3	640	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
AnnaBridge	189:f392fc9709a3	641	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
AnnaBridge	189:f392fc9709a3	642	/**
AnnaBridge	189:f392fc9709a3	643	* @}
AnnaBridge	189:f392fc9709a3	644	*/
AnnaBridge	189:f392fc9709a3	645
AnnaBridge	189:f392fc9709a3	646	#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
AnnaBridge	189:f392fc9709a3	647	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
AnnaBridge	189:f392fc9709a3	648	((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) \|\| \
AnnaBridge	189:f392fc9709a3	649	((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \|\| \
AnnaBridge	189:f392fc9709a3	650	((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) \|\| \
AnnaBridge	189:f392fc9709a3	651	((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) \|\| \
AnnaBridge	189:f392fc9709a3	652	((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) \|\| \
AnnaBridge	189:f392fc9709a3	653	((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \|\| \
AnnaBridge	189:f392fc9709a3	654	((__CLOCK__) == TIM_CLOCKSOURCE_TI2) \|\| \
AnnaBridge	189:f392fc9709a3	655	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
AnnaBridge	189:f392fc9709a3	656
AnnaBridge	189:f392fc9709a3	657
AnnaBridge	189:f392fc9709a3	658	/** @defgroup TIM_Clock_Polarity Clock polarity
AnnaBridge	189:f392fc9709a3	659	* @{
AnnaBridge	189:f392fc9709a3	660	*/
AnnaBridge	189:f392fc9709a3	661	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
AnnaBridge	189:f392fc9709a3	662	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
AnnaBridge	189:f392fc9709a3	663	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
AnnaBridge	189:f392fc9709a3	664	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
AnnaBridge	189:f392fc9709a3	665	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
AnnaBridge	189:f392fc9709a3	666	/**
AnnaBridge	189:f392fc9709a3	667	* @}
AnnaBridge	189:f392fc9709a3	668	*/
AnnaBridge	189:f392fc9709a3	669	#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
AnnaBridge	189:f392fc9709a3	670	((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
AnnaBridge	189:f392fc9709a3	671	((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \|\| \
AnnaBridge	189:f392fc9709a3	672	((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) \|\| \
AnnaBridge	189:f392fc9709a3	673	((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
AnnaBridge	189:f392fc9709a3	674
AnnaBridge	189:f392fc9709a3	675	/** @defgroup TIM_Clock_Prescaler Clock prescaler
AnnaBridge	189:f392fc9709a3	676	* @{
AnnaBridge	189:f392fc9709a3	677	*/
AnnaBridge	189:f392fc9709a3	678	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
AnnaBridge	189:f392fc9709a3	679	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
AnnaBridge	189:f392fc9709a3	680	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
AnnaBridge	189:f392fc9709a3	681	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
AnnaBridge	189:f392fc9709a3	682	/**
AnnaBridge	189:f392fc9709a3	683	* @}
AnnaBridge	189:f392fc9709a3	684	*/
AnnaBridge	189:f392fc9709a3	685	#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) \|\| \
AnnaBridge	189:f392fc9709a3	686	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) \|\| \
AnnaBridge	189:f392fc9709a3	687	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) \|\| \
AnnaBridge	189:f392fc9709a3	688	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
AnnaBridge	189:f392fc9709a3	689
AnnaBridge	189:f392fc9709a3	690
AnnaBridge	189:f392fc9709a3	691	/* Check clock filter */
AnnaBridge	189:f392fc9709a3	692	#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
AnnaBridge	189:f392fc9709a3	693
AnnaBridge	189:f392fc9709a3	694	/** @defgroup TIM_ClearInput_Source Clear input source
AnnaBridge	189:f392fc9709a3	695	* @{
AnnaBridge	189:f392fc9709a3	696	*/
AnnaBridge	189:f392fc9709a3	697	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U)
AnnaBridge	189:f392fc9709a3	698	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	699	/**
AnnaBridge	189:f392fc9709a3	700	* @}
AnnaBridge	189:f392fc9709a3	701	*/
AnnaBridge	189:f392fc9709a3	702
AnnaBridge	189:f392fc9709a3	703	#define IS_TIM_CLEARINPUT_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
AnnaBridge	189:f392fc9709a3	704	((__SOURCE__) == TIM_CLEARINPUTSOURCE_ETR))
AnnaBridge	189:f392fc9709a3	705
AnnaBridge	189:f392fc9709a3	706
AnnaBridge	189:f392fc9709a3	707	/** @defgroup TIM_ClearInput_Polarity Clear input polarity
AnnaBridge	189:f392fc9709a3	708	* @{
AnnaBridge	189:f392fc9709a3	709	*/
AnnaBridge	189:f392fc9709a3	710	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
AnnaBridge	189:f392fc9709a3	711	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
AnnaBridge	189:f392fc9709a3	712	/**
AnnaBridge	189:f392fc9709a3	713	* @}
AnnaBridge	189:f392fc9709a3	714	*/
AnnaBridge	189:f392fc9709a3	715	#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
AnnaBridge	189:f392fc9709a3	716	((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
AnnaBridge	189:f392fc9709a3	717
AnnaBridge	189:f392fc9709a3	718
AnnaBridge	189:f392fc9709a3	719	/** @defgroup TIM_ClearInput_Prescaler Clear input prescaler
AnnaBridge	189:f392fc9709a3	720	* @{
AnnaBridge	189:f392fc9709a3	721	*/
AnnaBridge	189:f392fc9709a3	722	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
AnnaBridge	189:f392fc9709a3	723	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
AnnaBridge	189:f392fc9709a3	724	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
AnnaBridge	189:f392fc9709a3	725	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
AnnaBridge	189:f392fc9709a3	726	/**
AnnaBridge	189:f392fc9709a3	727	* @}
AnnaBridge	189:f392fc9709a3	728	*/
AnnaBridge	189:f392fc9709a3	729	#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
AnnaBridge	189:f392fc9709a3	730	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
AnnaBridge	189:f392fc9709a3	731	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
AnnaBridge	189:f392fc9709a3	732	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
AnnaBridge	189:f392fc9709a3	733
AnnaBridge	189:f392fc9709a3	734
AnnaBridge	189:f392fc9709a3	735	/* Check IC filter */
AnnaBridge	189:f392fc9709a3	736	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
AnnaBridge	189:f392fc9709a3	737
AnnaBridge	189:f392fc9709a3	738
AnnaBridge	189:f392fc9709a3	739	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
AnnaBridge	189:f392fc9709a3	740	* @{
AnnaBridge	189:f392fc9709a3	741	*/
AnnaBridge	189:f392fc9709a3	742	#define TIM_TRGO_RESET ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	743	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
AnnaBridge	189:f392fc9709a3	744	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
AnnaBridge	189:f392fc9709a3	745	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
AnnaBridge	189:f392fc9709a3	746	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
AnnaBridge	189:f392fc9709a3	747	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
AnnaBridge	189:f392fc9709a3	748	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
AnnaBridge	189:f392fc9709a3	749	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
AnnaBridge	189:f392fc9709a3	750	/**
AnnaBridge	189:f392fc9709a3	751	* @}
AnnaBridge	189:f392fc9709a3	752	*/
AnnaBridge	189:f392fc9709a3	753	#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) \|\| \
AnnaBridge	189:f392fc9709a3	754	((__SOURCE__) == TIM_TRGO_ENABLE) \|\| \
AnnaBridge	189:f392fc9709a3	755	((__SOURCE__) == TIM_TRGO_UPDATE) \|\| \
AnnaBridge	189:f392fc9709a3	756	((__SOURCE__) == TIM_TRGO_OC1) \|\| \
AnnaBridge	189:f392fc9709a3	757	((__SOURCE__) == TIM_TRGO_OC1REF) \|\| \
AnnaBridge	189:f392fc9709a3	758	((__SOURCE__) == TIM_TRGO_OC2REF) \|\| \
AnnaBridge	189:f392fc9709a3	759	((__SOURCE__) == TIM_TRGO_OC3REF) \|\| \
AnnaBridge	189:f392fc9709a3	760	((__SOURCE__) == TIM_TRGO_OC4REF))
AnnaBridge	189:f392fc9709a3	761
AnnaBridge	189:f392fc9709a3	762
AnnaBridge	189:f392fc9709a3	763
AnnaBridge	189:f392fc9709a3	764	/** @defgroup TIM_Slave_Mode Slave mode
AnnaBridge	189:f392fc9709a3	765	* @{
AnnaBridge	189:f392fc9709a3	766	*/
AnnaBridge	189:f392fc9709a3	767	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	768	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004U)
AnnaBridge	189:f392fc9709a3	769	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005U)
AnnaBridge	189:f392fc9709a3	770	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006U)
AnnaBridge	189:f392fc9709a3	771	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007U)
AnnaBridge	189:f392fc9709a3	772	/**
AnnaBridge	189:f392fc9709a3	773	* @}
AnnaBridge	189:f392fc9709a3	774	*/
AnnaBridge	189:f392fc9709a3	775	#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) \|\| \
AnnaBridge	189:f392fc9709a3	776	((__MODE__) == TIM_SLAVEMODE_GATED) \|\| \
AnnaBridge	189:f392fc9709a3	777	((__MODE__) == TIM_SLAVEMODE_RESET) \|\| \
AnnaBridge	189:f392fc9709a3	778	((__MODE__) == TIM_SLAVEMODE_TRIGGER) \|\| \
AnnaBridge	189:f392fc9709a3	779	((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
AnnaBridge	189:f392fc9709a3	780
AnnaBridge	189:f392fc9709a3	781	/** @defgroup TIM_Master_Slave_Mode Master slave mode
AnnaBridge	189:f392fc9709a3	782	* @{
AnnaBridge	189:f392fc9709a3	783	*/
AnnaBridge	189:f392fc9709a3	784
AnnaBridge	189:f392fc9709a3	785	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080U)
AnnaBridge	189:f392fc9709a3	786	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	787	/**
AnnaBridge	189:f392fc9709a3	788	* @}
AnnaBridge	189:f392fc9709a3	789	*/
AnnaBridge	189:f392fc9709a3	790	#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
AnnaBridge	189:f392fc9709a3	791	((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
AnnaBridge	189:f392fc9709a3	792
AnnaBridge	189:f392fc9709a3	793	/** @defgroup TIM_Trigger_Selection Trigger selection
AnnaBridge	189:f392fc9709a3	794	* @{
AnnaBridge	189:f392fc9709a3	795	*/
AnnaBridge	189:f392fc9709a3	796	#define TIM_TS_ITR0 ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	797	#define TIM_TS_ITR1 ((uint32_t)0x0010U)
AnnaBridge	189:f392fc9709a3	798	#define TIM_TS_ITR2 ((uint32_t)0x0020U)
AnnaBridge	189:f392fc9709a3	799	#define TIM_TS_ITR3 ((uint32_t)0x0030U)
AnnaBridge	189:f392fc9709a3	800	#define TIM_TS_TI1F_ED ((uint32_t)0x0040U)
AnnaBridge	189:f392fc9709a3	801	#define TIM_TS_TI1FP1 ((uint32_t)0x0050U)
AnnaBridge	189:f392fc9709a3	802	#define TIM_TS_TI2FP2 ((uint32_t)0x0060U)
AnnaBridge	189:f392fc9709a3	803	#define TIM_TS_ETRF ((uint32_t)0x0070U)
AnnaBridge	189:f392fc9709a3	804	#define TIM_TS_NONE ((uint32_t)0xFFFFU)
AnnaBridge	189:f392fc9709a3	805	/**
AnnaBridge	189:f392fc9709a3	806	* @}
AnnaBridge	189:f392fc9709a3	807	*/
AnnaBridge	189:f392fc9709a3	808	#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
AnnaBridge	189:f392fc9709a3	809	((__SELECTION__) == TIM_TS_ITR1) \|\| \
AnnaBridge	189:f392fc9709a3	810	((__SELECTION__) == TIM_TS_ITR2) \|\| \
AnnaBridge	189:f392fc9709a3	811	((__SELECTION__) == TIM_TS_ITR3) \|\| \
AnnaBridge	189:f392fc9709a3	812	((__SELECTION__) == TIM_TS_TI1F_ED) \|\| \
AnnaBridge	189:f392fc9709a3	813	((__SELECTION__) == TIM_TS_TI1FP1) \|\| \
AnnaBridge	189:f392fc9709a3	814	((__SELECTION__) == TIM_TS_TI2FP2) \|\| \
AnnaBridge	189:f392fc9709a3	815	((__SELECTION__) == TIM_TS_ETRF))
AnnaBridge	189:f392fc9709a3	816	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
AnnaBridge	189:f392fc9709a3	817	((__SELECTION__) == TIM_TS_ITR1) \|\| \
AnnaBridge	189:f392fc9709a3	818	((__SELECTION__) == TIM_TS_ITR2) \|\| \
AnnaBridge	189:f392fc9709a3	819	((__SELECTION__) == TIM_TS_ITR3) \|\| \
AnnaBridge	189:f392fc9709a3	820	((__SELECTION__) == TIM_TS_NONE))
AnnaBridge	189:f392fc9709a3	821
AnnaBridge	189:f392fc9709a3	822
AnnaBridge	189:f392fc9709a3	823	/** @defgroup TIM_Trigger_Polarity Trigger polarity
AnnaBridge	189:f392fc9709a3	824	* @{
AnnaBridge	189:f392fc9709a3	825	*/
AnnaBridge	189:f392fc9709a3	826	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
AnnaBridge	189:f392fc9709a3	827	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
AnnaBridge	189:f392fc9709a3	828	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
AnnaBridge	189:f392fc9709a3	829	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
AnnaBridge	189:f392fc9709a3	830	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
AnnaBridge	189:f392fc9709a3	831	/**
AnnaBridge	189:f392fc9709a3	832	* @}
AnnaBridge	189:f392fc9709a3	833	*/
AnnaBridge	189:f392fc9709a3	834	#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
AnnaBridge	189:f392fc9709a3	835	((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
AnnaBridge	189:f392fc9709a3	836	((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
AnnaBridge	189:f392fc9709a3	837	((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
AnnaBridge	189:f392fc9709a3	838	((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
AnnaBridge	189:f392fc9709a3	839
AnnaBridge	189:f392fc9709a3	840
AnnaBridge	189:f392fc9709a3	841	/** @defgroup TIM_Trigger_Prescaler Trigger prescaler
AnnaBridge	189:f392fc9709a3	842	* @{
AnnaBridge	189:f392fc9709a3	843	*/
AnnaBridge	189:f392fc9709a3	844	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
AnnaBridge	189:f392fc9709a3	845	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
AnnaBridge	189:f392fc9709a3	846	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
AnnaBridge	189:f392fc9709a3	847	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
AnnaBridge	189:f392fc9709a3	848	/**
AnnaBridge	189:f392fc9709a3	849	* @}
AnnaBridge	189:f392fc9709a3	850	*/
AnnaBridge	189:f392fc9709a3	851	#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
AnnaBridge	189:f392fc9709a3	852	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
AnnaBridge	189:f392fc9709a3	853	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
AnnaBridge	189:f392fc9709a3	854	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
AnnaBridge	189:f392fc9709a3	855
AnnaBridge	189:f392fc9709a3	856
AnnaBridge	189:f392fc9709a3	857	/* Check trigger filter */
AnnaBridge	189:f392fc9709a3	858	#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
AnnaBridge	189:f392fc9709a3	859
AnnaBridge	189:f392fc9709a3	860
AnnaBridge	189:f392fc9709a3	861	/** @defgroup TIM_TI1_Selection TI1 selection
AnnaBridge	189:f392fc9709a3	862	* @{
AnnaBridge	189:f392fc9709a3	863	*/
AnnaBridge	189:f392fc9709a3	864	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	865	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
AnnaBridge	189:f392fc9709a3	866	/**
AnnaBridge	189:f392fc9709a3	867	* @}
AnnaBridge	189:f392fc9709a3	868	*/
AnnaBridge	189:f392fc9709a3	869	#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) \|\| \
AnnaBridge	189:f392fc9709a3	870	((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
AnnaBridge	189:f392fc9709a3	871
AnnaBridge	189:f392fc9709a3	872
AnnaBridge	189:f392fc9709a3	873	/** @defgroup TIM_DMA_Base_address DMA base address
AnnaBridge	189:f392fc9709a3	874	* @{
AnnaBridge	189:f392fc9709a3	875	*/
AnnaBridge	189:f392fc9709a3	876	#define TIM_DMABASE_CR1 (0x00000000U)
AnnaBridge	189:f392fc9709a3	877	#define TIM_DMABASE_CR2 (0x00000001U)
AnnaBridge	189:f392fc9709a3	878	#define TIM_DMABASE_SMCR (0x00000002U)
AnnaBridge	189:f392fc9709a3	879	#define TIM_DMABASE_DIER (0x00000003U)
AnnaBridge	189:f392fc9709a3	880	#define TIM_DMABASE_SR (0x00000004U)
AnnaBridge	189:f392fc9709a3	881	#define TIM_DMABASE_EGR (0x00000005U)
AnnaBridge	189:f392fc9709a3	882	#define TIM_DMABASE_CCMR1 (0x00000006U)
AnnaBridge	189:f392fc9709a3	883	#define TIM_DMABASE_CCMR2 (0x00000007U)
AnnaBridge	189:f392fc9709a3	884	#define TIM_DMABASE_CCER (0x00000008U)
AnnaBridge	189:f392fc9709a3	885	#define TIM_DMABASE_CNT (0x00000009U)
AnnaBridge	189:f392fc9709a3	886	#define TIM_DMABASE_PSC (0x0000000AU)
AnnaBridge	189:f392fc9709a3	887	#define TIM_DMABASE_ARR (0x0000000BU)
AnnaBridge	189:f392fc9709a3	888	#define TIM_DMABASE_CCR1 (0x0000000DU)
AnnaBridge	189:f392fc9709a3	889	#define TIM_DMABASE_CCR2 (0x0000000EU)
AnnaBridge	189:f392fc9709a3	890	#define TIM_DMABASE_CCR3 (0x0000000FU)
AnnaBridge	189:f392fc9709a3	891	#define TIM_DMABASE_CCR4 (0x00000010U)
AnnaBridge	189:f392fc9709a3	892	#define TIM_DMABASE_DCR (0x00000012U)
AnnaBridge	189:f392fc9709a3	893	#define TIM_DMABASE_OR (0x00000013U)
AnnaBridge	189:f392fc9709a3	894	/**
AnnaBridge	189:f392fc9709a3	895	* @}
AnnaBridge	189:f392fc9709a3	896	*/
AnnaBridge	189:f392fc9709a3	897	#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) \|\| \
AnnaBridge	189:f392fc9709a3	898	((__BASE__) == TIM_DMABASE_CR2) \|\| \
AnnaBridge	189:f392fc9709a3	899	((__BASE__) == TIM_DMABASE_SMCR) \|\| \
AnnaBridge	189:f392fc9709a3	900	((__BASE__) == TIM_DMABASE_DIER) \|\| \
AnnaBridge	189:f392fc9709a3	901	((__BASE__) == TIM_DMABASE_SR) \|\| \
AnnaBridge	189:f392fc9709a3	902	((__BASE__) == TIM_DMABASE_EGR) \|\| \
AnnaBridge	189:f392fc9709a3	903	((__BASE__) == TIM_DMABASE_CCMR1) \|\| \
AnnaBridge	189:f392fc9709a3	904	((__BASE__) == TIM_DMABASE_CCMR2 ) \|\| \
AnnaBridge	189:f392fc9709a3	905	((__BASE__) == TIM_DMABASE_CCER) \|\| \
AnnaBridge	189:f392fc9709a3	906	((__BASE__) == TIM_DMABASE_CNT) \|\| \
AnnaBridge	189:f392fc9709a3	907	((__BASE__) == TIM_DMABASE_PSC) \|\| \
AnnaBridge	189:f392fc9709a3	908	((__BASE__) == TIM_DMABASE_ARR) \|\| \
AnnaBridge	189:f392fc9709a3	909	((__BASE__) == TIM_DMABASE_CCR1) \|\| \
AnnaBridge	189:f392fc9709a3	910	((__BASE__) == TIM_DMABASE_CCR2) \|\| \
AnnaBridge	189:f392fc9709a3	911	((__BASE__) == TIM_DMABASE_CCR3) \|\| \
AnnaBridge	189:f392fc9709a3	912	((__BASE__) == TIM_DMABASE_CCR4) \|\| \
AnnaBridge	189:f392fc9709a3	913	((__BASE__) == TIM_DMABASE_DCR) \|\| \
AnnaBridge	189:f392fc9709a3	914	((__BASE__) == TIM_DMABASE_OR))
AnnaBridge	189:f392fc9709a3	915
AnnaBridge	189:f392fc9709a3	916
AnnaBridge	189:f392fc9709a3	917	/** @defgroup TIM_DMA_Burst_Length DMA burst length
AnnaBridge	189:f392fc9709a3	918	* @{
AnnaBridge	189:f392fc9709a3	919	*/
AnnaBridge	189:f392fc9709a3	920	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
AnnaBridge	189:f392fc9709a3	921	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
AnnaBridge	189:f392fc9709a3	922	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
AnnaBridge	189:f392fc9709a3	923	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
AnnaBridge	189:f392fc9709a3	924	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
AnnaBridge	189:f392fc9709a3	925	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
AnnaBridge	189:f392fc9709a3	926	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
AnnaBridge	189:f392fc9709a3	927	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
AnnaBridge	189:f392fc9709a3	928	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
AnnaBridge	189:f392fc9709a3	929	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
AnnaBridge	189:f392fc9709a3	930	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
AnnaBridge	189:f392fc9709a3	931	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
AnnaBridge	189:f392fc9709a3	932	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
AnnaBridge	189:f392fc9709a3	933	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
AnnaBridge	189:f392fc9709a3	934	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
AnnaBridge	189:f392fc9709a3	935	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
AnnaBridge	189:f392fc9709a3	936	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
AnnaBridge	189:f392fc9709a3	937	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
AnnaBridge	189:f392fc9709a3	938	/**
AnnaBridge	189:f392fc9709a3	939	* @}
AnnaBridge	189:f392fc9709a3	940	*/
AnnaBridge	189:f392fc9709a3	941	#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER ) \|\| \
AnnaBridge	189:f392fc9709a3	942	((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	943	((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	944	((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	945	((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	946	((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	947	((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	948	((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	949	((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS ) \|\| \
AnnaBridge	189:f392fc9709a3	950	((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	951	((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS ) \|\| \
AnnaBridge	189:f392fc9709a3	952	((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	953	((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	954	((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	955	((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	956	((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	957	((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
AnnaBridge	189:f392fc9709a3	958	((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS ))
AnnaBridge	189:f392fc9709a3	959
AnnaBridge	189:f392fc9709a3	960
AnnaBridge	189:f392fc9709a3	961	/* Check IC filter */
AnnaBridge	189:f392fc9709a3	962	#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
AnnaBridge	189:f392fc9709a3	963
AnnaBridge	189:f392fc9709a3	964	/** @defgroup DMA_Handle_index DMA handle index
AnnaBridge	189:f392fc9709a3	965	* @{
AnnaBridge	189:f392fc9709a3	966	*/
AnnaBridge	189:f392fc9709a3	967	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /!< Index of the DMA handle used for Update DMA requests /
AnnaBridge	189:f392fc9709a3	968	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
AnnaBridge	189:f392fc9709a3	969	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
AnnaBridge	189:f392fc9709a3	970	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
AnnaBridge	189:f392fc9709a3	971	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
AnnaBridge	189:f392fc9709a3	972	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x5U) /!< Index of the DMA handle used for Trigger DMA requests /
AnnaBridge	189:f392fc9709a3	973	/**
AnnaBridge	189:f392fc9709a3	974	* @}
AnnaBridge	189:f392fc9709a3	975	*/
AnnaBridge	189:f392fc9709a3	976
AnnaBridge	189:f392fc9709a3	977	/** @defgroup Channel_CC_State Channel state
AnnaBridge	189:f392fc9709a3	978	* @{
AnnaBridge	189:f392fc9709a3	979	*/
AnnaBridge	189:f392fc9709a3	980	#define TIM_CCx_ENABLE ((uint32_t)0x0001U)
AnnaBridge	189:f392fc9709a3	981	#define TIM_CCx_DISABLE ((uint32_t)0x0000U)
AnnaBridge	189:f392fc9709a3	982	/**
AnnaBridge	189:f392fc9709a3	983	* @}
AnnaBridge	189:f392fc9709a3	984	*/
AnnaBridge	189:f392fc9709a3	985
AnnaBridge	189:f392fc9709a3	986	/**
AnnaBridge	189:f392fc9709a3	987	* @}
AnnaBridge	189:f392fc9709a3	988	*/
AnnaBridge	189:f392fc9709a3	989
AnnaBridge	189:f392fc9709a3	990	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	991	/** @defgroup TIM_Exported_Macro TIM Exported Macro
AnnaBridge	189:f392fc9709a3	992	* @{
AnnaBridge	189:f392fc9709a3	993	*/
AnnaBridge	189:f392fc9709a3	994
AnnaBridge	189:f392fc9709a3	995	/** @brief Reset UART handle state
AnnaBridge	189:f392fc9709a3	996	* @param __HANDLE__ : TIM handle
AnnaBridge	189:f392fc9709a3	997	* @retval None
AnnaBridge	189:f392fc9709a3	998	*/
AnnaBridge	189:f392fc9709a3	999	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
AnnaBridge	189:f392fc9709a3	1000
AnnaBridge	189:f392fc9709a3	1001	/**
AnnaBridge	189:f392fc9709a3	1002	* @brief Enable the TIM peripheral.
AnnaBridge	189:f392fc9709a3	1003	* @param __HANDLE__ : TIM handle
AnnaBridge	189:f392fc9709a3	1004	* @retval None
AnnaBridge	189:f392fc9709a3	1005	*/
AnnaBridge	189:f392fc9709a3	1006	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
AnnaBridge	189:f392fc9709a3	1007
AnnaBridge	189:f392fc9709a3	1008	/* The counter of a timer instance is disabled only if all the CCx channels have
AnnaBridge	189:f392fc9709a3	1009	been disabled */
AnnaBridge	189:f392fc9709a3	1010	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
AnnaBridge	189:f392fc9709a3	1011
AnnaBridge	189:f392fc9709a3	1012	/**
AnnaBridge	189:f392fc9709a3	1013	* @brief Disable the TIM peripheral.
AnnaBridge	189:f392fc9709a3	1014	* @param __HANDLE__ : TIM handle
AnnaBridge	189:f392fc9709a3	1015	* @retval None
AnnaBridge	189:f392fc9709a3	1016	*/
AnnaBridge	189:f392fc9709a3	1017	#define __HAL_TIM_DISABLE(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	1018	do { \
AnnaBridge	189:f392fc9709a3	1019	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
AnnaBridge	189:f392fc9709a3	1020	{ \
AnnaBridge	189:f392fc9709a3	1021	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
AnnaBridge	189:f392fc9709a3	1022	} \
AnnaBridge	189:f392fc9709a3	1023	} while(0)
AnnaBridge	189:f392fc9709a3	1024
AnnaBridge	189:f392fc9709a3	1025	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	1026	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
AnnaBridge	189:f392fc9709a3	1027	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	1028	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
AnnaBridge	189:f392fc9709a3	1029	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge	189:f392fc9709a3	1030	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
AnnaBridge	189:f392fc9709a3	1031
AnnaBridge	189:f392fc9709a3	1032	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge	189:f392fc9709a3	1033	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	1034
AnnaBridge	189:f392fc9709a3	1035	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
AnnaBridge	189:f392fc9709a3	1036	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
AnnaBridge	189:f392fc9709a3	1037
AnnaBridge	189:f392fc9709a3	1038	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge	189:f392fc9709a3	1039	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
AnnaBridge	189:f392fc9709a3	1040	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
AnnaBridge	189:f392fc9709a3	1041	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
AnnaBridge	189:f392fc9709a3	1042	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
AnnaBridge	189:f392fc9709a3	1043
AnnaBridge	189:f392fc9709a3	1044	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	1045	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
AnnaBridge	189:f392fc9709a3	1046	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
AnnaBridge	189:f392fc9709a3	1047	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
AnnaBridge	189:f392fc9709a3	1048	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
AnnaBridge	189:f392fc9709a3	1049
AnnaBridge	189:f392fc9709a3	1050	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge	189:f392fc9709a3	1051	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
AnnaBridge	189:f392fc9709a3	1052	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
AnnaBridge	189:f392fc9709a3	1053	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
AnnaBridge	189:f392fc9709a3	1054	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
AnnaBridge	189:f392fc9709a3	1055
AnnaBridge	189:f392fc9709a3	1056	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	1057	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
AnnaBridge	189:f392fc9709a3	1058	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
AnnaBridge	189:f392fc9709a3	1059	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
AnnaBridge	189:f392fc9709a3	1060	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
AnnaBridge	189:f392fc9709a3	1061
AnnaBridge	189:f392fc9709a3	1062	/**
AnnaBridge	189:f392fc9709a3	1063	* @brief Sets the TIM Capture Compare Register value on runtime without
AnnaBridge	189:f392fc9709a3	1064	* calling another time ConfigChannel function.
AnnaBridge	189:f392fc9709a3	1065	* @param __HANDLE__ : TIM handle.
AnnaBridge	189:f392fc9709a3	1066	* @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge	189:f392fc9709a3	1067	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1068	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge	189:f392fc9709a3	1069	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge	189:f392fc9709a3	1070	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge	189:f392fc9709a3	1071	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge	189:f392fc9709a3	1072	* @param __COMPARE__: specifies the Capture Compare register new value.
AnnaBridge	189:f392fc9709a3	1073	* @retval None
AnnaBridge	189:f392fc9709a3	1074	*/
AnnaBridge	189:f392fc9709a3	1075	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
AnnaBridge	189:f392fc9709a3	1076	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
AnnaBridge	189:f392fc9709a3	1077
AnnaBridge	189:f392fc9709a3	1078	/**
AnnaBridge	189:f392fc9709a3	1079	* @brief Gets the TIM Capture Compare Register value on runtime
AnnaBridge	189:f392fc9709a3	1080	* @param __HANDLE__ : TIM handle.
AnnaBridge	189:f392fc9709a3	1081	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
AnnaBridge	189:f392fc9709a3	1082	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1083	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
AnnaBridge	189:f392fc9709a3	1084	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
AnnaBridge	189:f392fc9709a3	1085	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
AnnaBridge	189:f392fc9709a3	1086	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
AnnaBridge	189:f392fc9709a3	1087	* @retval None
AnnaBridge	189:f392fc9709a3	1088	*/
AnnaBridge	189:f392fc9709a3	1089	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	1090	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
AnnaBridge	189:f392fc9709a3	1091
AnnaBridge	189:f392fc9709a3	1092	/**
AnnaBridge	189:f392fc9709a3	1093	* @brief Sets the TIM Counter Register value on runtime.
AnnaBridge	189:f392fc9709a3	1094	* @param __HANDLE__ : TIM handle.
AnnaBridge	189:f392fc9709a3	1095	* @param __COUNTER__: specifies the Counter register new value.
AnnaBridge	189:f392fc9709a3	1096	* @retval None
AnnaBridge	189:f392fc9709a3	1097	*/
AnnaBridge	189:f392fc9709a3	1098	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
AnnaBridge	189:f392fc9709a3	1099
AnnaBridge	189:f392fc9709a3	1100	/**
AnnaBridge	189:f392fc9709a3	1101	* @brief Gets the TIM Counter Register value on runtime.
AnnaBridge	189:f392fc9709a3	1102	* @param __HANDLE__ : TIM handle.
AnnaBridge	189:f392fc9709a3	1103	* @retval None
AnnaBridge	189:f392fc9709a3	1104	*/
AnnaBridge	189:f392fc9709a3	1105	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
AnnaBridge	189:f392fc9709a3	1106
AnnaBridge	189:f392fc9709a3	1107	/**
AnnaBridge	189:f392fc9709a3	1108	* @brief Sets the TIM Autoreload Register value on runtime without calling
AnnaBridge	189:f392fc9709a3	1109	* another time any Init function.
AnnaBridge	189:f392fc9709a3	1110	* @param __HANDLE__ : TIM handle.
AnnaBridge	189:f392fc9709a3	1111	* @param __AUTORELOAD__: specifies the Counter register new value.
AnnaBridge	189:f392fc9709a3	1112	* @retval None
AnnaBridge	189:f392fc9709a3	1113	*/
AnnaBridge	189:f392fc9709a3	1114	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
AnnaBridge	189:f392fc9709a3	1115	do{ \
AnnaBridge	189:f392fc9709a3	1116	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
AnnaBridge	189:f392fc9709a3	1117	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
AnnaBridge	189:f392fc9709a3	1118	} while(0)
AnnaBridge	189:f392fc9709a3	1119	/**
AnnaBridge	189:f392fc9709a3	1120	* @brief Gets the TIM Autoreload Register value on runtime
AnnaBridge	189:f392fc9709a3	1121	* @param __HANDLE__ : TIM handle.
AnnaBridge	189:f392fc9709a3	1122	* @retval None
AnnaBridge	189:f392fc9709a3	1123	*/
AnnaBridge	189:f392fc9709a3	1124	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
AnnaBridge	189:f392fc9709a3	1125
AnnaBridge	189:f392fc9709a3	1126	/**
AnnaBridge	189:f392fc9709a3	1127	* @brief Sets the TIM Clock Division value on runtime without calling
AnnaBridge	189:f392fc9709a3	1128	* another time any Init function.
AnnaBridge	189:f392fc9709a3	1129	* @param __HANDLE__ : TIM handle.
AnnaBridge	189:f392fc9709a3	1130	* @param __CKD__: specifies the clock division value.
AnnaBridge	189:f392fc9709a3	1131	* This parameter can be one of the following value:
AnnaBridge	189:f392fc9709a3	1132	* @arg TIM_CLOCKDIVISION_DIV1
AnnaBridge	189:f392fc9709a3	1133	* @arg TIM_CLOCKDIVISION_DIV2
AnnaBridge	189:f392fc9709a3	1134	* @arg TIM_CLOCKDIVISION_DIV4
AnnaBridge	189:f392fc9709a3	1135	* @retval None
AnnaBridge	189:f392fc9709a3	1136	*/
AnnaBridge	189:f392fc9709a3	1137	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
AnnaBridge	189:f392fc9709a3	1138	do{ \
AnnaBridge	189:f392fc9709a3	1139	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
AnnaBridge	189:f392fc9709a3	1140	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
AnnaBridge	189:f392fc9709a3	1141	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
AnnaBridge	189:f392fc9709a3	1142	} while(0)
AnnaBridge	189:f392fc9709a3	1143	/**
AnnaBridge	189:f392fc9709a3	1144	* @brief Gets the TIM Clock Division value on runtime
AnnaBridge	189:f392fc9709a3	1145	* @param __HANDLE__ : TIM handle.
AnnaBridge	189:f392fc9709a3	1146	* @retval None
AnnaBridge	189:f392fc9709a3	1147	*/
AnnaBridge	189:f392fc9709a3	1148	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
AnnaBridge	189:f392fc9709a3	1149
AnnaBridge	189:f392fc9709a3	1150	/**
AnnaBridge	189:f392fc9709a3	1151	* @brief Sets the TIM Input Capture prescaler on runtime without calling
AnnaBridge	189:f392fc9709a3	1152	* another time HAL_TIM_IC_ConfigChannel() function.
AnnaBridge	189:f392fc9709a3	1153	* @param __HANDLE__ : TIM handle.
AnnaBridge	189:f392fc9709a3	1154	* @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge	189:f392fc9709a3	1155	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1156	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge	189:f392fc9709a3	1157	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge	189:f392fc9709a3	1158	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge	189:f392fc9709a3	1159	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge	189:f392fc9709a3	1160	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
AnnaBridge	189:f392fc9709a3	1161	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1162	* @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge	189:f392fc9709a3	1163	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge	189:f392fc9709a3	1164	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge	189:f392fc9709a3	1165	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
AnnaBridge	189:f392fc9709a3	1166	* @retval None
AnnaBridge	189:f392fc9709a3	1167	*/
AnnaBridge	189:f392fc9709a3	1168	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge	189:f392fc9709a3	1169	do{ \
AnnaBridge	189:f392fc9709a3	1170	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
AnnaBridge	189:f392fc9709a3	1171	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
AnnaBridge	189:f392fc9709a3	1172	} while(0)
AnnaBridge	189:f392fc9709a3	1173
AnnaBridge	189:f392fc9709a3	1174	/**
AnnaBridge	189:f392fc9709a3	1175	* @brief Gets the TIM Input Capture prescaler on runtime
AnnaBridge	189:f392fc9709a3	1176	* @param __HANDLE__ : TIM handle.
AnnaBridge	189:f392fc9709a3	1177	* @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge	189:f392fc9709a3	1178	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1179	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
AnnaBridge	189:f392fc9709a3	1180	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
AnnaBridge	189:f392fc9709a3	1181	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
AnnaBridge	189:f392fc9709a3	1182	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
AnnaBridge	189:f392fc9709a3	1183	* @retval None
AnnaBridge	189:f392fc9709a3	1184	*/
AnnaBridge	189:f392fc9709a3	1185	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
AnnaBridge	189:f392fc9709a3	1186	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
AnnaBridge	189:f392fc9709a3	1187	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
AnnaBridge	189:f392fc9709a3	1188	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
AnnaBridge	189:f392fc9709a3	1189	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
AnnaBridge	189:f392fc9709a3	1190
AnnaBridge	189:f392fc9709a3	1191
AnnaBridge	189:f392fc9709a3	1192	/**
AnnaBridge	189:f392fc9709a3	1193	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
AnnaBridge	189:f392fc9709a3	1194	* @param __HANDLE__: TIM handle.
AnnaBridge	189:f392fc9709a3	1195	* @note When the URS bit of the TIMx_CR1 register is set, only counter
AnnaBridge	189:f392fc9709a3	1196	* overflow/underflow generates an update interrupt or DMA request (if
AnnaBridge	189:f392fc9709a3	1197	* enabled)
AnnaBridge	189:f392fc9709a3	1198	* @retval None
AnnaBridge	189:f392fc9709a3	1199	*/
AnnaBridge	189:f392fc9709a3	1200	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	1201	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
AnnaBridge	189:f392fc9709a3	1202
AnnaBridge	189:f392fc9709a3	1203	/**
AnnaBridge	189:f392fc9709a3	1204	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
AnnaBridge	189:f392fc9709a3	1205	* @param __HANDLE__: TIM handle.
AnnaBridge	189:f392fc9709a3	1206	* @note When the URS bit of the TIMx_CR1 register is reset, any of the
AnnaBridge	189:f392fc9709a3	1207	* following events generate an update interrupt or DMA request (if
AnnaBridge	189:f392fc9709a3	1208	* enabled):
AnnaBridge	189:f392fc9709a3	1209	* Counter overflow/underflow
AnnaBridge	189:f392fc9709a3	1210	* Setting the UG bit
AnnaBridge	189:f392fc9709a3	1211	* Update generation through the slave mode controller
AnnaBridge	189:f392fc9709a3	1212	* @retval None
AnnaBridge	189:f392fc9709a3	1213	*/
AnnaBridge	189:f392fc9709a3	1214	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	1215	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
AnnaBridge	189:f392fc9709a3	1216
AnnaBridge	189:f392fc9709a3	1217	/**
AnnaBridge	189:f392fc9709a3	1218	* @brief Sets the TIM Capture x input polarity on runtime.
AnnaBridge	189:f392fc9709a3	1219	* @param __HANDLE__: TIM handle.
AnnaBridge	189:f392fc9709a3	1220	* @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge	189:f392fc9709a3	1221	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1222	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge	189:f392fc9709a3	1223	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge	189:f392fc9709a3	1224	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge	189:f392fc9709a3	1225	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge	189:f392fc9709a3	1226	* @param __POLARITY__: Polarity for TIx source
AnnaBridge	189:f392fc9709a3	1227	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
AnnaBridge	189:f392fc9709a3	1228	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
AnnaBridge	189:f392fc9709a3	1229	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
AnnaBridge	189:f392fc9709a3	1230	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
AnnaBridge	189:f392fc9709a3	1231	* @retval None
AnnaBridge	189:f392fc9709a3	1232	*/
AnnaBridge	189:f392fc9709a3	1233	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge	189:f392fc9709a3	1234	do{ \
AnnaBridge	189:f392fc9709a3	1235	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
AnnaBridge	189:f392fc9709a3	1236	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
AnnaBridge	189:f392fc9709a3	1237	}while(0)
AnnaBridge	189:f392fc9709a3	1238
AnnaBridge	189:f392fc9709a3	1239	/**
AnnaBridge	189:f392fc9709a3	1240	* @}
AnnaBridge	189:f392fc9709a3	1241	*/
AnnaBridge	189:f392fc9709a3	1242
AnnaBridge	189:f392fc9709a3	1243	/* Include TIM HAL Extension module */
AnnaBridge	189:f392fc9709a3	1244	#include "stm32l0xx_hal_tim_ex.h"
AnnaBridge	189:f392fc9709a3	1245
AnnaBridge	189:f392fc9709a3	1246	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1247	/** @defgroup TIM_Exported_Functions TIM Exported Functions
AnnaBridge	189:f392fc9709a3	1248	* @{
AnnaBridge	189:f392fc9709a3	1249	*/
AnnaBridge	189:f392fc9709a3	1250
AnnaBridge	189:f392fc9709a3	1251	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1252	/* Time Base functions ********************************************************/
AnnaBridge	189:f392fc9709a3	1253
AnnaBridge	189:f392fc9709a3	1254	/** @defgroup TIM_Exported_Functions_Group1 Timer Base functions
AnnaBridge	189:f392fc9709a3	1255	* @brief Time Base functions
AnnaBridge	189:f392fc9709a3	1256	* @{
AnnaBridge	189:f392fc9709a3	1257	*/
AnnaBridge	189:f392fc9709a3	1258	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1259	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1260	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1261	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1262	/* Blocking mode: Polling */
AnnaBridge	189:f392fc9709a3	1263	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1264	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1265	/* Non-Blocking mode: Interrupt */
AnnaBridge	189:f392fc9709a3	1266	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1267	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1268	/* Non-Blocking mode: DMA */
AnnaBridge	189:f392fc9709a3	1269	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
AnnaBridge	189:f392fc9709a3	1270	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1271
AnnaBridge	189:f392fc9709a3	1272	/**
AnnaBridge	189:f392fc9709a3	1273	* @}
AnnaBridge	189:f392fc9709a3	1274	*/
AnnaBridge	189:f392fc9709a3	1275
AnnaBridge	189:f392fc9709a3	1276
AnnaBridge	189:f392fc9709a3	1277	/* Timer Output Compare functions **********************************************/
AnnaBridge	189:f392fc9709a3	1278
AnnaBridge	189:f392fc9709a3	1279	/** @defgroup TIM_Exported_Functions_Group2 Timer Output Compare functions
AnnaBridge	189:f392fc9709a3	1280	* @brief Timer Output Compare functions
AnnaBridge	189:f392fc9709a3	1281	* @{
AnnaBridge	189:f392fc9709a3	1282	*/
AnnaBridge	189:f392fc9709a3	1283
AnnaBridge	189:f392fc9709a3	1284	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1285	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1286	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1287	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1288	/* Blocking mode: Polling */
AnnaBridge	189:f392fc9709a3	1289	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1290	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1291	/* Non-Blocking mode: Interrupt */
AnnaBridge	189:f392fc9709a3	1292	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1293	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1294	/* Non-Blocking mode: DMA */
AnnaBridge	189:f392fc9709a3	1295	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
AnnaBridge	189:f392fc9709a3	1296	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1297	/**
AnnaBridge	189:f392fc9709a3	1298	* @}
AnnaBridge	189:f392fc9709a3	1299	*/
AnnaBridge	189:f392fc9709a3	1300
AnnaBridge	189:f392fc9709a3	1301
AnnaBridge	189:f392fc9709a3	1302	/* Timer PWM functions *********************************************************/
AnnaBridge	189:f392fc9709a3	1303
AnnaBridge	189:f392fc9709a3	1304	/** @defgroup TIM_Exported_Functions_Group3 Timer PWM functions
AnnaBridge	189:f392fc9709a3	1305	* @brief Timer PWM functions
AnnaBridge	189:f392fc9709a3	1306	* @{
AnnaBridge	189:f392fc9709a3	1307	*/
AnnaBridge	189:f392fc9709a3	1308	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1309	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1310	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1311	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1312	/* Blocking mode: Polling */
AnnaBridge	189:f392fc9709a3	1313	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1314	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1315	/* Non-Blocking mode: Interrupt */
AnnaBridge	189:f392fc9709a3	1316	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1317	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1318	/* Non-Blocking mode: DMA */
AnnaBridge	189:f392fc9709a3	1319	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
AnnaBridge	189:f392fc9709a3	1320	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1321	/**
AnnaBridge	189:f392fc9709a3	1322	* @}
AnnaBridge	189:f392fc9709a3	1323	*/
AnnaBridge	189:f392fc9709a3	1324
AnnaBridge	189:f392fc9709a3	1325	/* Timer Input Capture functions ***********************************************/
AnnaBridge	189:f392fc9709a3	1326
AnnaBridge	189:f392fc9709a3	1327	/** @defgroup TIM_Exported_Functions_Group4 Timer Input Capture functions
AnnaBridge	189:f392fc9709a3	1328	* @brief Timer Input Capture functions
AnnaBridge	189:f392fc9709a3	1329	* @{
AnnaBridge	189:f392fc9709a3	1330	*/
AnnaBridge	189:f392fc9709a3	1331	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1332	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1333	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1334	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1335	/* Blocking mode: Polling */
AnnaBridge	189:f392fc9709a3	1336	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1337	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1338	/* Non-Blocking mode: Interrupt */
AnnaBridge	189:f392fc9709a3	1339	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1340	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1341	/* Non-Blocking mode: DMA */
AnnaBridge	189:f392fc9709a3	1342	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
AnnaBridge	189:f392fc9709a3	1343	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1344	/**
AnnaBridge	189:f392fc9709a3	1345	* @}
AnnaBridge	189:f392fc9709a3	1346	*/
AnnaBridge	189:f392fc9709a3	1347
AnnaBridge	189:f392fc9709a3	1348	/* Timer One Pulse functions ***************************************************/
AnnaBridge	189:f392fc9709a3	1349
AnnaBridge	189:f392fc9709a3	1350	/** @defgroup TIM_Exported_Functions_Group5 Timer One Pulse functions
AnnaBridge	189:f392fc9709a3	1351	* @brief Timer One Pulse functions
AnnaBridge	189:f392fc9709a3	1352	* @{
AnnaBridge	189:f392fc9709a3	1353	*/
AnnaBridge	189:f392fc9709a3	1354	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
AnnaBridge	189:f392fc9709a3	1355	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1356	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1357	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1358	/* Blocking mode: Polling */
AnnaBridge	189:f392fc9709a3	1359	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	189:f392fc9709a3	1360	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	189:f392fc9709a3	1361
AnnaBridge	189:f392fc9709a3	1362	/* Non-Blocking mode: Interrupt */
AnnaBridge	189:f392fc9709a3	1363	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	189:f392fc9709a3	1364	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge	189:f392fc9709a3	1365
AnnaBridge	189:f392fc9709a3	1366	/**
AnnaBridge	189:f392fc9709a3	1367	* @}
AnnaBridge	189:f392fc9709a3	1368	*/
AnnaBridge	189:f392fc9709a3	1369
AnnaBridge	189:f392fc9709a3	1370	/* Timer Encoder functions *****************************************************/
AnnaBridge	189:f392fc9709a3	1371
AnnaBridge	189:f392fc9709a3	1372	/** @defgroup TIM_Exported_Functions_Group6 Timer Encoder functions
AnnaBridge	189:f392fc9709a3	1373	* @brief Timer Encoder functions
AnnaBridge	189:f392fc9709a3	1374	* @{
AnnaBridge	189:f392fc9709a3	1375	*/
AnnaBridge	189:f392fc9709a3	1376	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
AnnaBridge	189:f392fc9709a3	1377	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1378	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1379	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1380	/* Blocking mode: Polling */
AnnaBridge	189:f392fc9709a3	1381	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1382	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1383	/* Non-Blocking mode: Interrupt */
AnnaBridge	189:f392fc9709a3	1384	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1385	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1386	/* Non-Blocking mode: DMA */
AnnaBridge	189:f392fc9709a3	1387	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
AnnaBridge	189:f392fc9709a3	1388	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1389
AnnaBridge	189:f392fc9709a3	1390	/**
AnnaBridge	189:f392fc9709a3	1391	* @}
AnnaBridge	189:f392fc9709a3	1392	*/
AnnaBridge	189:f392fc9709a3	1393
AnnaBridge	189:f392fc9709a3	1394	/* Interrupt Handler functions **********************************************/
AnnaBridge	189:f392fc9709a3	1395
AnnaBridge	189:f392fc9709a3	1396	/** @defgroup TIM_Exported_Functions_Group7 Timer IRQ handler management
AnnaBridge	189:f392fc9709a3	1397	* @brief Interrupt Handler functions
AnnaBridge	189:f392fc9709a3	1398	* @{
AnnaBridge	189:f392fc9709a3	1399	*/
AnnaBridge	189:f392fc9709a3	1400	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1401	/**
AnnaBridge	189:f392fc9709a3	1402	* @}
AnnaBridge	189:f392fc9709a3	1403	*/
AnnaBridge	189:f392fc9709a3	1404
AnnaBridge	189:f392fc9709a3	1405	/* Control functions *********************************************************/
AnnaBridge	189:f392fc9709a3	1406
AnnaBridge	189:f392fc9709a3	1407	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
AnnaBridge	189:f392fc9709a3	1408	* @brief Control functions
AnnaBridge	189:f392fc9709a3	1409	* @{
AnnaBridge	189:f392fc9709a3	1410	*/
AnnaBridge	189:f392fc9709a3	1411	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1412	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1413	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1414	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
AnnaBridge	189:f392fc9709a3	1415	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1416	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
AnnaBridge	189:f392fc9709a3	1417	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
AnnaBridge	189:f392fc9709a3	1418	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
AnnaBridge	189:f392fc9709a3	1419	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
AnnaBridge	189:f392fc9709a3	1420	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge	189:f392fc9709a3	1421	uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge	189:f392fc9709a3	1422	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge	189:f392fc9709a3	1423	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge	189:f392fc9709a3	1424	uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge	189:f392fc9709a3	1425	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge	189:f392fc9709a3	1426	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
AnnaBridge	189:f392fc9709a3	1427	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge	189:f392fc9709a3	1428
AnnaBridge	189:f392fc9709a3	1429	/**
AnnaBridge	189:f392fc9709a3	1430	* @}
AnnaBridge	189:f392fc9709a3	1431	*/
AnnaBridge	189:f392fc9709a3	1432
AnnaBridge	189:f392fc9709a3	1433	/* Callback in non blocking modes (Interrupt and DMA) *************************/
AnnaBridge	189:f392fc9709a3	1434
AnnaBridge	189:f392fc9709a3	1435	/** @defgroup TIM_Exported_Functions_Group9 Timer Callbacks functions
AnnaBridge	189:f392fc9709a3	1436	* @brief Callback functions
AnnaBridge	189:f392fc9709a3	1437	* @{
AnnaBridge	189:f392fc9709a3	1438	*/
AnnaBridge	189:f392fc9709a3	1439	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1440	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1441	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1442	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1443	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1444	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1445	/**
AnnaBridge	189:f392fc9709a3	1446	* @}
AnnaBridge	189:f392fc9709a3	1447	*/
AnnaBridge	189:f392fc9709a3	1448
AnnaBridge	189:f392fc9709a3	1449
AnnaBridge	189:f392fc9709a3	1450	/* Peripheral State functions **************************************************/
AnnaBridge	189:f392fc9709a3	1451
AnnaBridge	189:f392fc9709a3	1452	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
AnnaBridge	189:f392fc9709a3	1453	* @brief Peripheral State functions
AnnaBridge	189:f392fc9709a3	1454	* @{
AnnaBridge	189:f392fc9709a3	1455	*/
AnnaBridge	189:f392fc9709a3	1456	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1457	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1458	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1459	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1460	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1461	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
AnnaBridge	189:f392fc9709a3	1462	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
AnnaBridge	189:f392fc9709a3	1463	void TIM_DMAError(DMA_HandleTypeDef *hdma);
AnnaBridge	189:f392fc9709a3	1464	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
AnnaBridge	189:f392fc9709a3	1465
AnnaBridge	189:f392fc9709a3	1466	/**
AnnaBridge	189:f392fc9709a3	1467	* @}
AnnaBridge	189:f392fc9709a3	1468	*/
AnnaBridge	189:f392fc9709a3	1469
AnnaBridge	189:f392fc9709a3	1470	/**
AnnaBridge	189:f392fc9709a3	1471	* @}
AnnaBridge	189:f392fc9709a3	1472	*/
AnnaBridge	189:f392fc9709a3	1473
AnnaBridge	189:f392fc9709a3	1474	/* Define the private group ***********************************/
AnnaBridge	189:f392fc9709a3	1475	/**************************************************************/
AnnaBridge	189:f392fc9709a3	1476	/** @defgroup TIM_Private TIM Private
AnnaBridge	189:f392fc9709a3	1477	* @{
AnnaBridge	189:f392fc9709a3	1478	*/
AnnaBridge	189:f392fc9709a3	1479	/**
AnnaBridge	189:f392fc9709a3	1480	* @}
AnnaBridge	189:f392fc9709a3	1481	*/
AnnaBridge	189:f392fc9709a3	1482	/**************************************************************/
AnnaBridge	189:f392fc9709a3	1483
AnnaBridge	189:f392fc9709a3	1484	/**
AnnaBridge	189:f392fc9709a3	1485	* @}
AnnaBridge	189:f392fc9709a3	1486	*/
AnnaBridge	189:f392fc9709a3	1487
AnnaBridge	189:f392fc9709a3	1488	/**
AnnaBridge	189:f392fc9709a3	1489	* @}
AnnaBridge	189:f392fc9709a3	1490	*/
AnnaBridge	189:f392fc9709a3	1491
AnnaBridge	189:f392fc9709a3	1492	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	1493	}
AnnaBridge	189:f392fc9709a3	1494	#endif
AnnaBridge	189:f392fc9709a3	1495
AnnaBridge	189:f392fc9709a3	1496	#endif /* __STM32L0xx_HAL_TIM_H */
AnnaBridge	189:f392fc9709a3	1497
AnnaBridge	189:f392fc9709a3	1498	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
AnnaBridge	189:f392fc9709a3	1499