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cmsis/BUILD/mbed/TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/stm32l0xx_hal_spi.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l0xx_hal_spi.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of SPI HAL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L0xx_HAL_SPI_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L0xx_HAL_SPI_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l0xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32L0xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | /** @defgroup SPI SPI |
| AnnaBridge | 189:f392fc9709a3 | 52 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 53 | */ |
| AnnaBridge | 189:f392fc9709a3 | 54 | |
| AnnaBridge | 189:f392fc9709a3 | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 56 | /** @defgroup SPI_Exported_Types SPI Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 57 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 58 | */ |
| AnnaBridge | 189:f392fc9709a3 | 59 | |
| AnnaBridge | 189:f392fc9709a3 | 60 | /** |
| AnnaBridge | 189:f392fc9709a3 | 61 | * @brief SPI Configuration Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 62 | */ |
| AnnaBridge | 189:f392fc9709a3 | 63 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 64 | { |
| AnnaBridge | 189:f392fc9709a3 | 65 | uint32_t Mode; /*!< Specifies the SPI operating mode. |
| AnnaBridge | 189:f392fc9709a3 | 66 | This parameter can be a value of @ref SPI_mode */ |
| AnnaBridge | 189:f392fc9709a3 | 67 | |
| AnnaBridge | 189:f392fc9709a3 | 68 | uint32_t Direction; /*!< Specifies the SPI Directional mode state. |
| AnnaBridge | 189:f392fc9709a3 | 69 | This parameter can be a value of @ref SPI_Direction_mode */ |
| AnnaBridge | 189:f392fc9709a3 | 70 | |
| AnnaBridge | 189:f392fc9709a3 | 71 | uint32_t DataSize; /*!< Specifies the SPI data size. |
| AnnaBridge | 189:f392fc9709a3 | 72 | This parameter can be a value of @ref SPI_data_size */ |
| AnnaBridge | 189:f392fc9709a3 | 73 | |
| AnnaBridge | 189:f392fc9709a3 | 74 | uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. |
| AnnaBridge | 189:f392fc9709a3 | 75 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
| AnnaBridge | 189:f392fc9709a3 | 76 | |
| AnnaBridge | 189:f392fc9709a3 | 77 | uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. |
| AnnaBridge | 189:f392fc9709a3 | 78 | This parameter can be a value of @ref SPI_Clock_Phase */ |
| AnnaBridge | 189:f392fc9709a3 | 79 | |
| AnnaBridge | 189:f392fc9709a3 | 80 | uint32_t NSS; /*!< Specifies whether the NSS signal is managed by |
| AnnaBridge | 189:f392fc9709a3 | 81 | hardware (NSS pin) or by software using the SSI bit. |
| AnnaBridge | 189:f392fc9709a3 | 82 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
| AnnaBridge | 189:f392fc9709a3 | 83 | |
| AnnaBridge | 189:f392fc9709a3 | 84 | uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
| AnnaBridge | 189:f392fc9709a3 | 85 | used to configure the transmit and receive SCK clock. |
| AnnaBridge | 189:f392fc9709a3 | 86 | This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| AnnaBridge | 189:f392fc9709a3 | 87 | @note The communication clock is derived from the master |
| AnnaBridge | 189:f392fc9709a3 | 88 | clock. The slave clock does not need to be set */ |
| AnnaBridge | 189:f392fc9709a3 | 89 | |
| AnnaBridge | 189:f392fc9709a3 | 90 | uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
| AnnaBridge | 189:f392fc9709a3 | 91 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
| AnnaBridge | 189:f392fc9709a3 | 92 | |
| AnnaBridge | 189:f392fc9709a3 | 93 | uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. |
| AnnaBridge | 189:f392fc9709a3 | 94 | This parameter can be a value of @ref SPI_TI_mode */ |
| AnnaBridge | 189:f392fc9709a3 | 95 | |
| AnnaBridge | 189:f392fc9709a3 | 96 | uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. |
| AnnaBridge | 189:f392fc9709a3 | 97 | This parameter can be a value of @ref SPI_CRC_Calculation */ |
| AnnaBridge | 189:f392fc9709a3 | 98 | |
| AnnaBridge | 189:f392fc9709a3 | 99 | uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. |
| AnnaBridge | 189:f392fc9709a3 | 100 | This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ |
| AnnaBridge | 189:f392fc9709a3 | 101 | |
| AnnaBridge | 189:f392fc9709a3 | 102 | }SPI_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 103 | |
| AnnaBridge | 189:f392fc9709a3 | 104 | /** |
| AnnaBridge | 189:f392fc9709a3 | 105 | * @brief HAL SPI State structure definition |
| AnnaBridge | 189:f392fc9709a3 | 106 | */ |
| AnnaBridge | 189:f392fc9709a3 | 107 | typedef enum |
| AnnaBridge | 189:f392fc9709a3 | 108 | { |
| AnnaBridge | 189:f392fc9709a3 | 109 | HAL_SPI_STATE_RESET = 0x00U, /*!< SPI not yet initialized or disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | HAL_SPI_STATE_READY = 0x01U, /*!< SPI initialized and ready for use */ |
| AnnaBridge | 189:f392fc9709a3 | 111 | HAL_SPI_STATE_BUSY = 0x02U, /*!< SPI process is ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 112 | HAL_SPI_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 113 | HAL_SPI_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 114 | HAL_SPI_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 115 | HAL_SPI_STATE_ERROR = 0x03U /*!< SPI error state */ |
| AnnaBridge | 189:f392fc9709a3 | 116 | |
| AnnaBridge | 189:f392fc9709a3 | 117 | }HAL_SPI_StateTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 118 | |
| AnnaBridge | 189:f392fc9709a3 | 119 | /** |
| AnnaBridge | 189:f392fc9709a3 | 120 | * @brief SPI handle Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 121 | */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | typedef struct __SPI_HandleTypeDef |
| AnnaBridge | 189:f392fc9709a3 | 123 | { |
| AnnaBridge | 189:f392fc9709a3 | 124 | SPI_TypeDef *Instance; /*!< SPI registers base address */ |
| AnnaBridge | 189:f392fc9709a3 | 125 | |
| AnnaBridge | 189:f392fc9709a3 | 126 | SPI_InitTypeDef Init; /*!< SPI communication parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 127 | |
| AnnaBridge | 189:f392fc9709a3 | 128 | uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ |
| AnnaBridge | 189:f392fc9709a3 | 129 | |
| AnnaBridge | 189:f392fc9709a3 | 130 | uint16_t TxXferSize; /*!< SPI Tx transfer size */ |
| AnnaBridge | 189:f392fc9709a3 | 131 | |
| AnnaBridge | 189:f392fc9709a3 | 132 | __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ |
| AnnaBridge | 189:f392fc9709a3 | 133 | |
| AnnaBridge | 189:f392fc9709a3 | 134 | uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ |
| AnnaBridge | 189:f392fc9709a3 | 135 | |
| AnnaBridge | 189:f392fc9709a3 | 136 | uint16_t RxXferSize; /*!< SPI Rx transfer size */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | |
| AnnaBridge | 189:f392fc9709a3 | 138 | __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ |
| AnnaBridge | 189:f392fc9709a3 | 139 | |
| AnnaBridge | 189:f392fc9709a3 | 140 | DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 141 | |
| AnnaBridge | 189:f392fc9709a3 | 142 | DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 143 | |
| AnnaBridge | 189:f392fc9709a3 | 144 | void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */ |
| AnnaBridge | 189:f392fc9709a3 | 145 | |
| AnnaBridge | 189:f392fc9709a3 | 146 | void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */ |
| AnnaBridge | 189:f392fc9709a3 | 147 | |
| AnnaBridge | 189:f392fc9709a3 | 148 | HAL_LockTypeDef Lock; /*!< SPI locking object */ |
| AnnaBridge | 189:f392fc9709a3 | 149 | |
| AnnaBridge | 189:f392fc9709a3 | 150 | __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ |
| AnnaBridge | 189:f392fc9709a3 | 151 | |
| AnnaBridge | 189:f392fc9709a3 | 152 | __IO uint32_t ErrorCode; /*!< SPI Error code */ |
| AnnaBridge | 189:f392fc9709a3 | 153 | |
| AnnaBridge | 189:f392fc9709a3 | 154 | }SPI_HandleTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 155 | /** |
| AnnaBridge | 189:f392fc9709a3 | 156 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 157 | */ |
| AnnaBridge | 189:f392fc9709a3 | 158 | |
| AnnaBridge | 189:f392fc9709a3 | 159 | |
| AnnaBridge | 189:f392fc9709a3 | 160 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 161 | |
| AnnaBridge | 189:f392fc9709a3 | 162 | /** @defgroup SPI_Exported_Constants SPI Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 163 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 164 | */ |
| AnnaBridge | 189:f392fc9709a3 | 165 | |
| AnnaBridge | 189:f392fc9709a3 | 166 | /** |
| AnnaBridge | 189:f392fc9709a3 | 167 | * @defgroup SPI_ErrorCode SPI Error Code |
| AnnaBridge | 189:f392fc9709a3 | 168 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 169 | */ |
| AnnaBridge | 189:f392fc9709a3 | 170 | #define HAL_SPI_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ |
| AnnaBridge | 189:f392fc9709a3 | 171 | #define HAL_SPI_ERROR_MODF ((uint32_t)0x01U) /*!< MODF error */ |
| AnnaBridge | 189:f392fc9709a3 | 172 | #define HAL_SPI_ERROR_CRC ((uint32_t)0x02U) /*!< CRC error */ |
| AnnaBridge | 189:f392fc9709a3 | 173 | #define HAL_SPI_ERROR_OVR ((uint32_t)0x04U) /*!< OVR error */ |
| AnnaBridge | 189:f392fc9709a3 | 174 | #define HAL_SPI_ERROR_FRE ((uint32_t)0x08U) /*!< FRE error */ |
| AnnaBridge | 189:f392fc9709a3 | 175 | #define HAL_SPI_ERROR_DMA ((uint32_t)0x10U) /*!< DMA transfer error */ |
| AnnaBridge | 189:f392fc9709a3 | 176 | #define HAL_SPI_ERROR_FLAG ((uint32_t)0x20U) /*!< Flag: RXNE,TXE, BSY */ |
| AnnaBridge | 189:f392fc9709a3 | 177 | /** |
| AnnaBridge | 189:f392fc9709a3 | 178 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 179 | */ |
| AnnaBridge | 189:f392fc9709a3 | 180 | |
| AnnaBridge | 189:f392fc9709a3 | 181 | /** @defgroup SPI_mode SPI mode |
| AnnaBridge | 189:f392fc9709a3 | 182 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 183 | */ |
| AnnaBridge | 189:f392fc9709a3 | 184 | #define SPI_MODE_SLAVE ((uint32_t)0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 185 | #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
| AnnaBridge | 189:f392fc9709a3 | 186 | |
| AnnaBridge | 189:f392fc9709a3 | 187 | /** |
| AnnaBridge | 189:f392fc9709a3 | 188 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 189 | */ |
| AnnaBridge | 189:f392fc9709a3 | 190 | |
| AnnaBridge | 189:f392fc9709a3 | 191 | /** @defgroup SPI_Direction_mode SPI Direction mode |
| AnnaBridge | 189:f392fc9709a3 | 192 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 193 | */ |
| AnnaBridge | 189:f392fc9709a3 | 194 | #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 195 | #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
| AnnaBridge | 189:f392fc9709a3 | 196 | #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
| AnnaBridge | 189:f392fc9709a3 | 197 | |
| AnnaBridge | 189:f392fc9709a3 | 198 | /** |
| AnnaBridge | 189:f392fc9709a3 | 199 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 200 | */ |
| AnnaBridge | 189:f392fc9709a3 | 201 | |
| AnnaBridge | 189:f392fc9709a3 | 202 | /** @defgroup SPI_data_size SPI data size |
| AnnaBridge | 189:f392fc9709a3 | 203 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 204 | */ |
| AnnaBridge | 189:f392fc9709a3 | 205 | #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 206 | #define SPI_DATASIZE_16BIT SPI_CR1_DFF |
| AnnaBridge | 189:f392fc9709a3 | 207 | |
| AnnaBridge | 189:f392fc9709a3 | 208 | /** |
| AnnaBridge | 189:f392fc9709a3 | 209 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 210 | */ |
| AnnaBridge | 189:f392fc9709a3 | 211 | |
| AnnaBridge | 189:f392fc9709a3 | 212 | /** @defgroup SPI_Clock_Polarity SPI Clock Polarity |
| AnnaBridge | 189:f392fc9709a3 | 213 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 214 | */ |
| AnnaBridge | 189:f392fc9709a3 | 215 | #define SPI_POLARITY_LOW ((uint32_t)0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 216 | #define SPI_POLARITY_HIGH SPI_CR1_CPOL |
| AnnaBridge | 189:f392fc9709a3 | 217 | |
| AnnaBridge | 189:f392fc9709a3 | 218 | /** |
| AnnaBridge | 189:f392fc9709a3 | 219 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 220 | */ |
| AnnaBridge | 189:f392fc9709a3 | 221 | |
| AnnaBridge | 189:f392fc9709a3 | 222 | /** @defgroup SPI_Clock_Phase SPI Clock Phase |
| AnnaBridge | 189:f392fc9709a3 | 223 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 224 | */ |
| AnnaBridge | 189:f392fc9709a3 | 225 | #define SPI_PHASE_1EDGE ((uint32_t)0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 226 | #define SPI_PHASE_2EDGE SPI_CR1_CPHA |
| AnnaBridge | 189:f392fc9709a3 | 227 | |
| AnnaBridge | 189:f392fc9709a3 | 228 | /** |
| AnnaBridge | 189:f392fc9709a3 | 229 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 230 | */ |
| AnnaBridge | 189:f392fc9709a3 | 231 | |
| AnnaBridge | 189:f392fc9709a3 | 232 | /** @defgroup SPI_Slave_Select_management SPI Slave Select management |
| AnnaBridge | 189:f392fc9709a3 | 233 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 234 | */ |
| AnnaBridge | 189:f392fc9709a3 | 235 | #define SPI_NSS_SOFT SPI_CR1_SSM |
| AnnaBridge | 189:f392fc9709a3 | 236 | #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 237 | #define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16U)) |
| AnnaBridge | 189:f392fc9709a3 | 238 | |
| AnnaBridge | 189:f392fc9709a3 | 239 | /** |
| AnnaBridge | 189:f392fc9709a3 | 240 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 241 | */ |
| AnnaBridge | 189:f392fc9709a3 | 242 | |
| AnnaBridge | 189:f392fc9709a3 | 243 | /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler |
| AnnaBridge | 189:f392fc9709a3 | 244 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 245 | */ |
| AnnaBridge | 189:f392fc9709a3 | 246 | #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 247 | #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) |
| AnnaBridge | 189:f392fc9709a3 | 248 | #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) |
| AnnaBridge | 189:f392fc9709a3 | 249 | #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) |
| AnnaBridge | 189:f392fc9709a3 | 250 | #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2) |
| AnnaBridge | 189:f392fc9709a3 | 251 | #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0) |
| AnnaBridge | 189:f392fc9709a3 | 252 | #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1) |
| AnnaBridge | 189:f392fc9709a3 | 253 | #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) |
| AnnaBridge | 189:f392fc9709a3 | 254 | |
| AnnaBridge | 189:f392fc9709a3 | 255 | /** |
| AnnaBridge | 189:f392fc9709a3 | 256 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 257 | */ |
| AnnaBridge | 189:f392fc9709a3 | 258 | |
| AnnaBridge | 189:f392fc9709a3 | 259 | /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission |
| AnnaBridge | 189:f392fc9709a3 | 260 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 261 | */ |
| AnnaBridge | 189:f392fc9709a3 | 262 | #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 263 | #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
| AnnaBridge | 189:f392fc9709a3 | 264 | |
| AnnaBridge | 189:f392fc9709a3 | 265 | /** |
| AnnaBridge | 189:f392fc9709a3 | 266 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 267 | */ |
| AnnaBridge | 189:f392fc9709a3 | 268 | |
| AnnaBridge | 189:f392fc9709a3 | 269 | /** @defgroup SPI_TI_mode SPI TI mode |
| AnnaBridge | 189:f392fc9709a3 | 270 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 271 | */ |
| AnnaBridge | 189:f392fc9709a3 | 272 | #define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 273 | #define SPI_TIMODE_ENABLE SPI_CR2_FRF |
| AnnaBridge | 189:f392fc9709a3 | 274 | |
| AnnaBridge | 189:f392fc9709a3 | 275 | /** |
| AnnaBridge | 189:f392fc9709a3 | 276 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 277 | */ |
| AnnaBridge | 189:f392fc9709a3 | 278 | |
| AnnaBridge | 189:f392fc9709a3 | 279 | /** @defgroup SPI_CRC_Calculation SPI CRC Calculation |
| AnnaBridge | 189:f392fc9709a3 | 280 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 281 | */ |
| AnnaBridge | 189:f392fc9709a3 | 282 | #define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 283 | #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
| AnnaBridge | 189:f392fc9709a3 | 284 | |
| AnnaBridge | 189:f392fc9709a3 | 285 | /** |
| AnnaBridge | 189:f392fc9709a3 | 286 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 287 | */ |
| AnnaBridge | 189:f392fc9709a3 | 288 | |
| AnnaBridge | 189:f392fc9709a3 | 289 | /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition |
| AnnaBridge | 189:f392fc9709a3 | 290 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 291 | */ |
| AnnaBridge | 189:f392fc9709a3 | 292 | #define SPI_IT_TXE SPI_CR2_TXEIE |
| AnnaBridge | 189:f392fc9709a3 | 293 | #define SPI_IT_RXNE SPI_CR2_RXNEIE |
| AnnaBridge | 189:f392fc9709a3 | 294 | #define SPI_IT_ERR SPI_CR2_ERRIE |
| AnnaBridge | 189:f392fc9709a3 | 295 | /** |
| AnnaBridge | 189:f392fc9709a3 | 296 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 297 | */ |
| AnnaBridge | 189:f392fc9709a3 | 298 | |
| AnnaBridge | 189:f392fc9709a3 | 299 | /** @defgroup SPI_Flag_definition SPI Flag definition |
| AnnaBridge | 189:f392fc9709a3 | 300 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 301 | */ |
| AnnaBridge | 189:f392fc9709a3 | 302 | #define SPI_FLAG_RXNE SPI_SR_RXNE |
| AnnaBridge | 189:f392fc9709a3 | 303 | #define SPI_FLAG_TXE SPI_SR_TXE |
| AnnaBridge | 189:f392fc9709a3 | 304 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR |
| AnnaBridge | 189:f392fc9709a3 | 305 | #define SPI_FLAG_MODF SPI_SR_MODF |
| AnnaBridge | 189:f392fc9709a3 | 306 | #define SPI_FLAG_OVR SPI_SR_OVR |
| AnnaBridge | 189:f392fc9709a3 | 307 | #define SPI_FLAG_BSY SPI_SR_BSY |
| AnnaBridge | 189:f392fc9709a3 | 308 | #define SPI_FLAG_FRE SPI_SR_FRE |
| AnnaBridge | 189:f392fc9709a3 | 309 | |
| AnnaBridge | 189:f392fc9709a3 | 310 | /** |
| AnnaBridge | 189:f392fc9709a3 | 311 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 312 | */ |
| AnnaBridge | 189:f392fc9709a3 | 313 | |
| AnnaBridge | 189:f392fc9709a3 | 314 | /** |
| AnnaBridge | 189:f392fc9709a3 | 315 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 316 | */ |
| AnnaBridge | 189:f392fc9709a3 | 317 | |
| AnnaBridge | 189:f392fc9709a3 | 318 | |
| AnnaBridge | 189:f392fc9709a3 | 319 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 320 | /** @defgroup SPI_Exported_Macros SPI Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 321 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 322 | */ |
| AnnaBridge | 189:f392fc9709a3 | 323 | |
| AnnaBridge | 189:f392fc9709a3 | 324 | /** @brief Reset SPI handle state |
| AnnaBridge | 189:f392fc9709a3 | 325 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 189:f392fc9709a3 | 326 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 327 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 328 | */ |
| AnnaBridge | 189:f392fc9709a3 | 329 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
| AnnaBridge | 189:f392fc9709a3 | 330 | |
| AnnaBridge | 189:f392fc9709a3 | 331 | /** @brief Enable the specified SPI interrupts. |
| AnnaBridge | 189:f392fc9709a3 | 332 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 189:f392fc9709a3 | 333 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 334 | * @param __INTERRUPT__: specifies the interrupt source to enable. |
| AnnaBridge | 189:f392fc9709a3 | 335 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 336 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 337 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 338 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 339 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 340 | */ |
| AnnaBridge | 189:f392fc9709a3 | 341 | #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 342 | |
| AnnaBridge | 189:f392fc9709a3 | 343 | /** @brief Disable the specified SPI interrupts. |
| AnnaBridge | 189:f392fc9709a3 | 344 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 189:f392fc9709a3 | 345 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 346 | * @param __INTERRUPT__: specifies the interrupt source to disable. |
| AnnaBridge | 189:f392fc9709a3 | 347 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 348 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 349 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 350 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 351 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 352 | */ |
| AnnaBridge | 189:f392fc9709a3 | 353 | #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 354 | |
| AnnaBridge | 189:f392fc9709a3 | 355 | /** @brief Check if the specified SPI interrupt source is enabled or disabled. |
| AnnaBridge | 189:f392fc9709a3 | 356 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 189:f392fc9709a3 | 357 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 358 | * @param __INTERRUPT__: specifies the SPI interrupt source to check. |
| AnnaBridge | 189:f392fc9709a3 | 359 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 360 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 361 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 362 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 189:f392fc9709a3 | 363 | * @retval The new state of __IT__ (TRUE or FALSE). |
| AnnaBridge | 189:f392fc9709a3 | 364 | */ |
| AnnaBridge | 189:f392fc9709a3 | 365 | #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| AnnaBridge | 189:f392fc9709a3 | 366 | |
| AnnaBridge | 189:f392fc9709a3 | 367 | /** @brief Check whether the specified SPI flag is set or not. |
| AnnaBridge | 189:f392fc9709a3 | 368 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 189:f392fc9709a3 | 369 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 370 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 189:f392fc9709a3 | 371 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 372 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
| AnnaBridge | 189:f392fc9709a3 | 373 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
| AnnaBridge | 189:f392fc9709a3 | 374 | * @arg SPI_FLAG_CRCERR: CRC error flag |
| AnnaBridge | 189:f392fc9709a3 | 375 | * @arg SPI_FLAG_MODF: Mode fault flag |
| AnnaBridge | 189:f392fc9709a3 | 376 | * @arg SPI_FLAG_OVR: Overrun flag |
| AnnaBridge | 189:f392fc9709a3 | 377 | * @arg SPI_FLAG_BSY: Busy flag |
| AnnaBridge | 189:f392fc9709a3 | 378 | * @arg SPI_FLAG_FRE: Frame format error flag |
| AnnaBridge | 189:f392fc9709a3 | 379 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 189:f392fc9709a3 | 380 | */ |
| AnnaBridge | 189:f392fc9709a3 | 381 | #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 189:f392fc9709a3 | 382 | |
| AnnaBridge | 189:f392fc9709a3 | 383 | /** @brief Clear the SPI CRCERR pending flag. |
| AnnaBridge | 189:f392fc9709a3 | 384 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 189:f392fc9709a3 | 385 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 386 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 387 | */ |
| AnnaBridge | 189:f392fc9709a3 | 388 | #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) |
| AnnaBridge | 189:f392fc9709a3 | 389 | |
| AnnaBridge | 189:f392fc9709a3 | 390 | /** @brief Clear the SPI MODF pending flag. |
| AnnaBridge | 189:f392fc9709a3 | 391 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 189:f392fc9709a3 | 392 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 393 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 394 | */ |
| AnnaBridge | 189:f392fc9709a3 | 395 | #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ |
| AnnaBridge | 189:f392fc9709a3 | 396 | do{ \ |
| AnnaBridge | 189:f392fc9709a3 | 397 | __IO uint32_t tmpreg_modf; \ |
| AnnaBridge | 189:f392fc9709a3 | 398 | tmpreg_modf = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 189:f392fc9709a3 | 399 | (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ |
| AnnaBridge | 189:f392fc9709a3 | 400 | UNUSED(tmpreg_modf); \ |
| AnnaBridge | 189:f392fc9709a3 | 401 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 402 | |
| AnnaBridge | 189:f392fc9709a3 | 403 | /** @brief Clear the SPI OVR pending flag. |
| AnnaBridge | 189:f392fc9709a3 | 404 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 189:f392fc9709a3 | 405 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 406 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 407 | */ |
| AnnaBridge | 189:f392fc9709a3 | 408 | #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ |
| AnnaBridge | 189:f392fc9709a3 | 409 | do{ \ |
| AnnaBridge | 189:f392fc9709a3 | 410 | __IO uint32_t tmpreg_ovr; \ |
| AnnaBridge | 189:f392fc9709a3 | 411 | tmpreg_ovr = (__HANDLE__)->Instance->DR; \ |
| AnnaBridge | 189:f392fc9709a3 | 412 | tmpreg_ovr = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 189:f392fc9709a3 | 413 | UNUSED(tmpreg_ovr); \ |
| AnnaBridge | 189:f392fc9709a3 | 414 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 415 | |
| AnnaBridge | 189:f392fc9709a3 | 416 | /** @brief Clear the SPI FRE pending flag. |
| AnnaBridge | 189:f392fc9709a3 | 417 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 189:f392fc9709a3 | 418 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 419 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 420 | */ |
| AnnaBridge | 189:f392fc9709a3 | 421 | #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ |
| AnnaBridge | 189:f392fc9709a3 | 422 | do{ \ |
| AnnaBridge | 189:f392fc9709a3 | 423 | __IO uint32_t tmpreg_fre; \ |
| AnnaBridge | 189:f392fc9709a3 | 424 | tmpreg_fre = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 189:f392fc9709a3 | 425 | UNUSED(tmpreg_fre); \ |
| AnnaBridge | 189:f392fc9709a3 | 426 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 427 | |
| AnnaBridge | 189:f392fc9709a3 | 428 | /** @brief Enables the SPI. |
| AnnaBridge | 189:f392fc9709a3 | 429 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 430 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 431 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 432 | */ |
| AnnaBridge | 189:f392fc9709a3 | 433 | #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
| AnnaBridge | 189:f392fc9709a3 | 434 | |
| AnnaBridge | 189:f392fc9709a3 | 435 | /** @brief Disables the SPI. |
| AnnaBridge | 189:f392fc9709a3 | 436 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 437 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 438 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 439 | */ |
| AnnaBridge | 189:f392fc9709a3 | 440 | #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
| AnnaBridge | 189:f392fc9709a3 | 441 | /** |
| AnnaBridge | 189:f392fc9709a3 | 442 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 443 | */ |
| AnnaBridge | 189:f392fc9709a3 | 444 | |
| AnnaBridge | 189:f392fc9709a3 | 445 | |
| AnnaBridge | 189:f392fc9709a3 | 446 | /* Private macros -----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 447 | /** @defgroup SPI_Private_Macros SPI Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 448 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 449 | */ |
| AnnaBridge | 189:f392fc9709a3 | 450 | |
| AnnaBridge | 189:f392fc9709a3 | 451 | /** @brief Checks if SPI Mode parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 452 | * @param __MODE__: specifies the SPI Mode. |
| AnnaBridge | 189:f392fc9709a3 | 453 | * This parameter can be a value of @ref SPI_mode |
| AnnaBridge | 189:f392fc9709a3 | 454 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 455 | */ |
| AnnaBridge | 189:f392fc9709a3 | 456 | #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER)) |
| AnnaBridge | 189:f392fc9709a3 | 457 | |
| AnnaBridge | 189:f392fc9709a3 | 458 | /** @brief Checks if SPI Direction Mode parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 459 | * @param __MODE__: specifies the SPI Direction Mode. |
| AnnaBridge | 189:f392fc9709a3 | 460 | * This parameter can be a value of @ref SPI_Direction_mode |
| AnnaBridge | 189:f392fc9709a3 | 461 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 462 | */ |
| AnnaBridge | 189:f392fc9709a3 | 463 | #define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 464 | ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ |
| AnnaBridge | 189:f392fc9709a3 | 465 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
| AnnaBridge | 189:f392fc9709a3 | 466 | |
| AnnaBridge | 189:f392fc9709a3 | 467 | /** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. |
| AnnaBridge | 189:f392fc9709a3 | 468 | * @param __MODE__: specifies the SPI Direction Mode. |
| AnnaBridge | 189:f392fc9709a3 | 469 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 470 | */ |
| AnnaBridge | 189:f392fc9709a3 | 471 | #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
| AnnaBridge | 189:f392fc9709a3 | 472 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
| AnnaBridge | 189:f392fc9709a3 | 473 | |
| AnnaBridge | 189:f392fc9709a3 | 474 | /** @brief Checks if SPI Direction Mode parameter is 2 lines. |
| AnnaBridge | 189:f392fc9709a3 | 475 | * @param __MODE__: specifies the SPI Direction Mode. |
| AnnaBridge | 189:f392fc9709a3 | 476 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 477 | */ |
| AnnaBridge | 189:f392fc9709a3 | 478 | #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) |
| AnnaBridge | 189:f392fc9709a3 | 479 | |
| AnnaBridge | 189:f392fc9709a3 | 480 | /** @brief Checks if SPI Data Size parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 481 | * @param __DATASIZE__: specifies the SPI Data Size. |
| AnnaBridge | 189:f392fc9709a3 | 482 | * This parameter can be a value of @ref SPI_data_size |
| AnnaBridge | 189:f392fc9709a3 | 483 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 484 | */ |
| AnnaBridge | 189:f392fc9709a3 | 485 | #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 486 | ((__DATASIZE__) == SPI_DATASIZE_8BIT)) |
| AnnaBridge | 189:f392fc9709a3 | 487 | |
| AnnaBridge | 189:f392fc9709a3 | 488 | /** @brief Checks if SPI Serial clock steady state parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 489 | * @param __CPOL__: specifies the SPI serial clock steady state. |
| AnnaBridge | 189:f392fc9709a3 | 490 | * This parameter can be a value of @ref SPI_Clock_Polarity |
| AnnaBridge | 189:f392fc9709a3 | 491 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 492 | */ |
| AnnaBridge | 189:f392fc9709a3 | 493 | #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ |
| AnnaBridge | 189:f392fc9709a3 | 494 | ((__CPOL__) == SPI_POLARITY_HIGH)) |
| AnnaBridge | 189:f392fc9709a3 | 495 | |
| AnnaBridge | 189:f392fc9709a3 | 496 | /** @brief Checks if SPI Clock Phase parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 497 | * @param __CPHA__: specifies the SPI Clock Phase. |
| AnnaBridge | 189:f392fc9709a3 | 498 | * This parameter can be a value of @ref SPI_Clock_Phase |
| AnnaBridge | 189:f392fc9709a3 | 499 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 500 | */ |
| AnnaBridge | 189:f392fc9709a3 | 501 | #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 502 | ((__CPHA__) == SPI_PHASE_2EDGE)) |
| AnnaBridge | 189:f392fc9709a3 | 503 | |
| AnnaBridge | 189:f392fc9709a3 | 504 | /** @brief Checks if SPI Slave select parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 505 | * @param __NSS__: specifies the SPI Slave Slelect management parameter. |
| AnnaBridge | 189:f392fc9709a3 | 506 | * This parameter can be a value of @ref SPI_Slave_Select_management |
| AnnaBridge | 189:f392fc9709a3 | 507 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 508 | */ |
| AnnaBridge | 189:f392fc9709a3 | 509 | #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 510 | ((__NSS__) == SPI_NSS_HARD_INPUT) || \ |
| AnnaBridge | 189:f392fc9709a3 | 511 | ((__NSS__) == SPI_NSS_HARD_OUTPUT)) |
| AnnaBridge | 189:f392fc9709a3 | 512 | |
| AnnaBridge | 189:f392fc9709a3 | 513 | /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 514 | * @param __PRESCALER__: specifies the SPI Baudrate prescaler. |
| AnnaBridge | 189:f392fc9709a3 | 515 | * This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| AnnaBridge | 189:f392fc9709a3 | 516 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 517 | */ |
| AnnaBridge | 189:f392fc9709a3 | 518 | #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 519 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 520 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 521 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ |
| AnnaBridge | 189:f392fc9709a3 | 522 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ |
| AnnaBridge | 189:f392fc9709a3 | 523 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ |
| AnnaBridge | 189:f392fc9709a3 | 524 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ |
| AnnaBridge | 189:f392fc9709a3 | 525 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) |
| AnnaBridge | 189:f392fc9709a3 | 526 | |
| AnnaBridge | 189:f392fc9709a3 | 527 | /** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 528 | * @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). |
| AnnaBridge | 189:f392fc9709a3 | 529 | * This parameter can be a value of @ref SPI_MSB_LSB_transmission |
| AnnaBridge | 189:f392fc9709a3 | 530 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 531 | */ |
| AnnaBridge | 189:f392fc9709a3 | 532 | #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ |
| AnnaBridge | 189:f392fc9709a3 | 533 | ((__BIT__) == SPI_FIRSTBIT_LSB)) |
| AnnaBridge | 189:f392fc9709a3 | 534 | |
| AnnaBridge | 189:f392fc9709a3 | 535 | /** @brief Checks if SPI TI mode parameter is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 536 | * @param __MODE__: specifies the SPI TI mode. |
| AnnaBridge | 189:f392fc9709a3 | 537 | * This parameter can be a value of @ref SPI_TI_mode |
| AnnaBridge | 189:f392fc9709a3 | 538 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 539 | */ |
| AnnaBridge | 189:f392fc9709a3 | 540 | #define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 541 | ((__MODE__) == SPI_TIMODE_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 542 | /** @brief Checks if SPI CRC calculation enabled state is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 543 | * @param __CALCULATION__: specifies the SPI CRC calculation enable state. |
| AnnaBridge | 189:f392fc9709a3 | 544 | * This parameter can be a value of @ref SPI_CRC_Calculation |
| AnnaBridge | 189:f392fc9709a3 | 545 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 546 | */ |
| AnnaBridge | 189:f392fc9709a3 | 547 | #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 548 | ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 549 | |
| AnnaBridge | 189:f392fc9709a3 | 550 | /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. |
| AnnaBridge | 189:f392fc9709a3 | 551 | * @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation. |
| AnnaBridge | 189:f392fc9709a3 | 552 | * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 |
| AnnaBridge | 189:f392fc9709a3 | 553 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 554 | */ |
| AnnaBridge | 189:f392fc9709a3 | 555 | #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU)) |
| AnnaBridge | 189:f392fc9709a3 | 556 | /** @brief Sets the SPI transmit-only mode. |
| AnnaBridge | 189:f392fc9709a3 | 557 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 558 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 559 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 560 | */ |
| AnnaBridge | 189:f392fc9709a3 | 561 | #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
| AnnaBridge | 189:f392fc9709a3 | 562 | |
| AnnaBridge | 189:f392fc9709a3 | 563 | /** @brief Sets the SPI receive-only mode. |
| AnnaBridge | 189:f392fc9709a3 | 564 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 565 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 566 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 567 | */ |
| AnnaBridge | 189:f392fc9709a3 | 568 | #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
| AnnaBridge | 189:f392fc9709a3 | 569 | |
| AnnaBridge | 189:f392fc9709a3 | 570 | /** @brief Resets the CRC calculation of the SPI. |
| AnnaBridge | 189:f392fc9709a3 | 571 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 189:f392fc9709a3 | 572 | * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
| AnnaBridge | 189:f392fc9709a3 | 573 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 574 | */ |
| AnnaBridge | 189:f392fc9709a3 | 575 | #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 576 | SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0) |
| AnnaBridge | 189:f392fc9709a3 | 577 | /** |
| AnnaBridge | 189:f392fc9709a3 | 578 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 579 | */ |
| AnnaBridge | 189:f392fc9709a3 | 580 | |
| AnnaBridge | 189:f392fc9709a3 | 581 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 582 | /** @defgroup SPI_Exported_Functions SPI Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 583 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 584 | */ |
| AnnaBridge | 189:f392fc9709a3 | 585 | |
| AnnaBridge | 189:f392fc9709a3 | 586 | /* Initialization/de-initialization functions **********************************/ |
| AnnaBridge | 189:f392fc9709a3 | 587 | /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 189:f392fc9709a3 | 588 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 589 | */ |
| AnnaBridge | 189:f392fc9709a3 | 590 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 591 | HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 592 | void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 593 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 594 | /** |
| AnnaBridge | 189:f392fc9709a3 | 595 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 596 | */ |
| AnnaBridge | 189:f392fc9709a3 | 597 | |
| AnnaBridge | 189:f392fc9709a3 | 598 | /* I/O operation functions *****************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 599 | /** @defgroup SPI_Exported_Functions_Group2 IO operation functions |
| AnnaBridge | 189:f392fc9709a3 | 600 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 601 | */ |
| AnnaBridge | 189:f392fc9709a3 | 602 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 603 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 604 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 605 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 189:f392fc9709a3 | 606 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 189:f392fc9709a3 | 607 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
| AnnaBridge | 189:f392fc9709a3 | 608 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 189:f392fc9709a3 | 609 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 189:f392fc9709a3 | 610 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
| AnnaBridge | 189:f392fc9709a3 | 611 | HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 612 | HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 613 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 614 | |
| AnnaBridge | 189:f392fc9709a3 | 615 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 616 | void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 617 | void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 618 | void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 619 | void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 620 | void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 621 | void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 622 | void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 623 | /** |
| AnnaBridge | 189:f392fc9709a3 | 624 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 625 | */ |
| AnnaBridge | 189:f392fc9709a3 | 626 | |
| AnnaBridge | 189:f392fc9709a3 | 627 | |
| AnnaBridge | 189:f392fc9709a3 | 628 | /* Peripheral State and Control functions **************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 629 | /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions |
| AnnaBridge | 189:f392fc9709a3 | 630 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 631 | */ |
| AnnaBridge | 189:f392fc9709a3 | 632 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 633 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 189:f392fc9709a3 | 634 | |
| AnnaBridge | 189:f392fc9709a3 | 635 | /** |
| AnnaBridge | 189:f392fc9709a3 | 636 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 637 | */ |
| AnnaBridge | 189:f392fc9709a3 | 638 | |
| AnnaBridge | 189:f392fc9709a3 | 639 | /** |
| AnnaBridge | 189:f392fc9709a3 | 640 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 641 | */ |
| AnnaBridge | 189:f392fc9709a3 | 642 | |
| AnnaBridge | 189:f392fc9709a3 | 643 | /* Private group definition ------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 644 | /** @defgroup SPI_Private_Macros SPI Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 645 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 646 | */ |
| AnnaBridge | 189:f392fc9709a3 | 647 | /** |
| AnnaBridge | 189:f392fc9709a3 | 648 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 649 | */ |
| AnnaBridge | 189:f392fc9709a3 | 650 | |
| AnnaBridge | 189:f392fc9709a3 | 651 | /* Define the private group ***********************************/ |
| AnnaBridge | 189:f392fc9709a3 | 652 | /**************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 653 | /** @defgroup SPI_Private SPI Private |
| AnnaBridge | 189:f392fc9709a3 | 654 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 655 | */ |
| AnnaBridge | 189:f392fc9709a3 | 656 | /** |
| AnnaBridge | 189:f392fc9709a3 | 657 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 658 | */ |
| AnnaBridge | 189:f392fc9709a3 | 659 | /**************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 660 | |
| AnnaBridge | 189:f392fc9709a3 | 661 | /** |
| AnnaBridge | 189:f392fc9709a3 | 662 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 663 | */ |
| AnnaBridge | 189:f392fc9709a3 | 664 | |
| AnnaBridge | 189:f392fc9709a3 | 665 | /** |
| AnnaBridge | 189:f392fc9709a3 | 666 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 667 | */ |
| AnnaBridge | 189:f392fc9709a3 | 668 | |
| AnnaBridge | 189:f392fc9709a3 | 669 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 670 | } |
| AnnaBridge | 189:f392fc9709a3 | 671 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 672 | |
| AnnaBridge | 189:f392fc9709a3 | 673 | #endif /* __STM32L0xx_HAL_SPI_H */ |
| AnnaBridge | 189:f392fc9709a3 | 674 | |
| AnnaBridge | 189:f392fc9709a3 | 675 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| AnnaBridge | 189:f392fc9709a3 | 676 |
