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cmsis/BUILD/mbed/TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/stm32l0xx_hal_flash_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l0xx_hal_flash_ex.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of Flash HAL Extended module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32L0xx_HAL_FLASH_EX_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32L0xx_HAL_FLASH_EX_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32l0xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32L0xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | /** @addtogroup FLASHEx |
| AnnaBridge | 189:f392fc9709a3 | 52 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 53 | */ |
| AnnaBridge | 189:f392fc9709a3 | 54 | |
| AnnaBridge | 189:f392fc9709a3 | 55 | /** @addtogroup FLASHEx_Private_Constants |
| AnnaBridge | 189:f392fc9709a3 | 56 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 57 | */ |
| AnnaBridge | 189:f392fc9709a3 | 58 | #define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE |
| AnnaBridge | 189:f392fc9709a3 | 59 | |
| AnnaBridge | 189:f392fc9709a3 | 60 | #define FLASH_NBPAGES_MAX (FLASH_SIZE / FLASH_PAGE_SIZE) |
| AnnaBridge | 189:f392fc9709a3 | 61 | |
| AnnaBridge | 189:f392fc9709a3 | 62 | #define WRP_MASK_LOW (0x0000FFFFU) |
| AnnaBridge | 189:f392fc9709a3 | 63 | #define WRP_MASK_HIGH (0xFFFF0000U) |
| AnnaBridge | 189:f392fc9709a3 | 64 | |
| AnnaBridge | 189:f392fc9709a3 | 65 | /** |
| AnnaBridge | 189:f392fc9709a3 | 66 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 67 | */ |
| AnnaBridge | 189:f392fc9709a3 | 68 | |
| AnnaBridge | 189:f392fc9709a3 | 69 | /** @addtogroup FLASHEx_Private_Macros |
| AnnaBridge | 189:f392fc9709a3 | 70 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 71 | */ |
| AnnaBridge | 189:f392fc9709a3 | 72 | |
| AnnaBridge | 189:f392fc9709a3 | 73 | #define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES)) |
| AnnaBridge | 189:f392fc9709a3 | 74 | |
| AnnaBridge | 189:f392fc9709a3 | 75 | #define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | \ |
| AnnaBridge | 189:f392fc9709a3 | 76 | OPTIONBYTE_USER | OPTIONBYTE_BOR | OPTIONBYTE_BOOT_BIT1))) |
| AnnaBridge | 189:f392fc9709a3 | 77 | |
| AnnaBridge | 189:f392fc9709a3 | 78 | #define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 79 | ((__VALUE__) == OB_WRPSTATE_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 80 | |
| AnnaBridge | 189:f392fc9709a3 | 81 | #define IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U)) |
| AnnaBridge | 189:f392fc9709a3 | 82 | |
| AnnaBridge | 189:f392fc9709a3 | 83 | #define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 84 | ((__LEVEL__) == OB_RDP_LEVEL_1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 85 | ((__LEVEL__) == OB_RDP_LEVEL_2)) |
| AnnaBridge | 189:f392fc9709a3 | 86 | |
| AnnaBridge | 189:f392fc9709a3 | 87 | #define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \ |
| AnnaBridge | 189:f392fc9709a3 | 88 | ((__LEVEL__) == OB_BOR_LEVEL1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 89 | ((__LEVEL__) == OB_BOR_LEVEL2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 90 | ((__LEVEL__) == OB_BOR_LEVEL3) || \ |
| AnnaBridge | 189:f392fc9709a3 | 91 | ((__LEVEL__) == OB_BOR_LEVEL4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 92 | ((__LEVEL__) == OB_BOR_LEVEL5)) |
| AnnaBridge | 189:f392fc9709a3 | 93 | |
| AnnaBridge | 189:f392fc9709a3 | 94 | #define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW)) |
| AnnaBridge | 189:f392fc9709a3 | 95 | |
| AnnaBridge | 189:f392fc9709a3 | 96 | #define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST)) |
| AnnaBridge | 189:f392fc9709a3 | 97 | |
| AnnaBridge | 189:f392fc9709a3 | 98 | #define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST)) |
| AnnaBridge | 189:f392fc9709a3 | 99 | |
| AnnaBridge | 189:f392fc9709a3 | 100 | #if defined(FLASH_OPTR_WPRMOD) && defined(FLASH_OPTR_BFB2) |
| AnnaBridge | 189:f392fc9709a3 | 101 | |
| AnnaBridge | 189:f392fc9709a3 | 102 | #define IS_OBEX(__VALUE__) (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)) |
| AnnaBridge | 189:f392fc9709a3 | 103 | |
| AnnaBridge | 189:f392fc9709a3 | 104 | #elif defined(FLASH_OPTR_WPRMOD) && !defined(FLASH_OPTR_BFB2) |
| AnnaBridge | 189:f392fc9709a3 | 105 | |
| AnnaBridge | 189:f392fc9709a3 | 106 | #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP) |
| AnnaBridge | 189:f392fc9709a3 | 107 | |
| AnnaBridge | 189:f392fc9709a3 | 108 | #elif !defined(FLASH_OPTR_WPRMOD) && defined(FLASH_OPTR_BFB2) |
| AnnaBridge | 189:f392fc9709a3 | 109 | |
| AnnaBridge | 189:f392fc9709a3 | 110 | #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG) |
| AnnaBridge | 189:f392fc9709a3 | 111 | |
| AnnaBridge | 189:f392fc9709a3 | 112 | #endif /* FLASH_OPTR_WPRMOD && FLASH_OPTR_BFB2 */ |
| AnnaBridge | 189:f392fc9709a3 | 113 | |
| AnnaBridge | 189:f392fc9709a3 | 114 | #if defined(FLASH_OPTR_WPRMOD) |
| AnnaBridge | 189:f392fc9709a3 | 115 | |
| AnnaBridge | 189:f392fc9709a3 | 116 | #define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 117 | ((__VALUE__) == OB_PCROP_STATE_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 118 | |
| AnnaBridge | 189:f392fc9709a3 | 119 | #define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U)) |
| AnnaBridge | 189:f392fc9709a3 | 120 | #endif /* FLASH_OPTR_WPRMOD */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | |
| AnnaBridge | 189:f392fc9709a3 | 122 | #if defined(FLASH_OPTR_BFB2) |
| AnnaBridge | 189:f392fc9709a3 | 123 | |
| AnnaBridge | 189:f392fc9709a3 | 124 | #define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1)) |
| AnnaBridge | 189:f392fc9709a3 | 125 | |
| AnnaBridge | 189:f392fc9709a3 | 126 | #endif /* FLASH_OPTR_BFB2 */ |
| AnnaBridge | 189:f392fc9709a3 | 127 | |
| AnnaBridge | 189:f392fc9709a3 | 128 | #define IS_OB_BOOT1(__BOOT_BIT1__) (((__BOOT_BIT1__) == OB_BOOT_BIT1_RESET) || ((__BOOT_BIT1__) == OB_BOOT_BIT1_SET)) |
| AnnaBridge | 189:f392fc9709a3 | 129 | #define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 130 | ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \ |
| AnnaBridge | 189:f392fc9709a3 | 131 | ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD)) |
| AnnaBridge | 189:f392fc9709a3 | 132 | |
| AnnaBridge | 189:f392fc9709a3 | 133 | |
| AnnaBridge | 189:f392fc9709a3 | 134 | /** @defgroup FLASHEx_Address FLASHEx Address |
| AnnaBridge | 189:f392fc9709a3 | 135 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 136 | */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | |
| AnnaBridge | 189:f392fc9709a3 | 138 | #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
| AnnaBridge | 189:f392fc9709a3 | 139 | |
| AnnaBridge | 189:f392fc9709a3 | 140 | #define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END)) |
| AnnaBridge | 189:f392fc9709a3 | 141 | #define IS_FLASH_DATA_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK1_END)) |
| AnnaBridge | 189:f392fc9709a3 | 142 | #define IS_FLASH_DATA_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BANK2_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END)) |
| AnnaBridge | 189:f392fc9709a3 | 143 | #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE))) |
| AnnaBridge | 189:f392fc9709a3 | 144 | #define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + (FLASH_SIZE >> 1)))) |
| AnnaBridge | 189:f392fc9709a3 | 145 | #define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE))) |
| AnnaBridge | 189:f392fc9709a3 | 146 | #else |
| AnnaBridge | 189:f392fc9709a3 | 147 | #define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_END)) |
| AnnaBridge | 189:f392fc9709a3 | 148 | #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE))) |
| AnnaBridge | 189:f392fc9709a3 | 149 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 150 | |
| AnnaBridge | 189:f392fc9709a3 | 151 | #define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX)) |
| AnnaBridge | 189:f392fc9709a3 | 152 | |
| AnnaBridge | 189:f392fc9709a3 | 153 | /** |
| AnnaBridge | 189:f392fc9709a3 | 154 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 155 | */ |
| AnnaBridge | 189:f392fc9709a3 | 156 | |
| AnnaBridge | 189:f392fc9709a3 | 157 | /** |
| AnnaBridge | 189:f392fc9709a3 | 158 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 159 | */ |
| AnnaBridge | 189:f392fc9709a3 | 160 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 161 | |
| AnnaBridge | 189:f392fc9709a3 | 162 | /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 163 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 164 | */ |
| AnnaBridge | 189:f392fc9709a3 | 165 | |
| AnnaBridge | 189:f392fc9709a3 | 166 | /** |
| AnnaBridge | 189:f392fc9709a3 | 167 | * @brief FLASH Erase structure definition |
| AnnaBridge | 189:f392fc9709a3 | 168 | */ |
| AnnaBridge | 189:f392fc9709a3 | 169 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 170 | { |
| AnnaBridge | 189:f392fc9709a3 | 171 | uint32_t TypeErase; /*!< TypeErase: Page Erase only. |
| AnnaBridge | 189:f392fc9709a3 | 172 | This parameter can be a value of @ref FLASHEx_Type_Erase */ |
| AnnaBridge | 189:f392fc9709a3 | 173 | |
| AnnaBridge | 189:f392fc9709a3 | 174 | uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased |
| AnnaBridge | 189:f392fc9709a3 | 175 | This parameter must be a value belonging to FLASH Programm address (depending on the devices) */ |
| AnnaBridge | 189:f392fc9709a3 | 176 | |
| AnnaBridge | 189:f392fc9709a3 | 177 | uint32_t NbPages; /*!< NbPages: Number of pages to be erased. |
| AnnaBridge | 189:f392fc9709a3 | 178 | This parameter must be a value between 1 and (max number of pages - value of Initial page)*/ |
| AnnaBridge | 189:f392fc9709a3 | 179 | |
| AnnaBridge | 189:f392fc9709a3 | 180 | } FLASH_EraseInitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 181 | |
| AnnaBridge | 189:f392fc9709a3 | 182 | /** |
| AnnaBridge | 189:f392fc9709a3 | 183 | * @brief FLASH Option Bytes PROGRAM structure definition |
| AnnaBridge | 189:f392fc9709a3 | 184 | */ |
| AnnaBridge | 189:f392fc9709a3 | 185 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 186 | { |
| AnnaBridge | 189:f392fc9709a3 | 187 | uint32_t OptionType; /*!< OptionType: Option byte to be configured. |
| AnnaBridge | 189:f392fc9709a3 | 188 | This parameter can be a value of @ref FLASHEx_Option_Type */ |
| AnnaBridge | 189:f392fc9709a3 | 189 | |
| AnnaBridge | 189:f392fc9709a3 | 190 | uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. |
| AnnaBridge | 189:f392fc9709a3 | 191 | This parameter can be a value of @ref FLASHEx_WRP_State */ |
| AnnaBridge | 189:f392fc9709a3 | 192 | |
| AnnaBridge | 189:f392fc9709a3 | 193 | uint32_t WRPSector; /*!< WRPSector: This bitfield specifies the sector (s) which are write protected. |
| AnnaBridge | 189:f392fc9709a3 | 194 | This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection */ |
| AnnaBridge | 189:f392fc9709a3 | 195 | |
| AnnaBridge | 189:f392fc9709a3 | 196 | #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) |
| AnnaBridge | 189:f392fc9709a3 | 197 | uint32_t WRPSector2; /*!< WRPSector2 : This bitfield specifies the sector(s) upper Sector31 which are write protected. |
| AnnaBridge | 189:f392fc9709a3 | 198 | This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */ |
| AnnaBridge | 189:f392fc9709a3 | 199 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 200 | |
| AnnaBridge | 189:f392fc9709a3 | 201 | uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level. |
| AnnaBridge | 189:f392fc9709a3 | 202 | This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ |
| AnnaBridge | 189:f392fc9709a3 | 203 | |
| AnnaBridge | 189:f392fc9709a3 | 204 | uint8_t BORLevel; /*!< BORLevel: Set the BOR Level. |
| AnnaBridge | 189:f392fc9709a3 | 205 | This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */ |
| AnnaBridge | 189:f392fc9709a3 | 206 | |
| AnnaBridge | 189:f392fc9709a3 | 207 | uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. |
| AnnaBridge | 189:f392fc9709a3 | 208 | This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, |
| AnnaBridge | 189:f392fc9709a3 | 209 | @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/ |
| AnnaBridge | 189:f392fc9709a3 | 210 | |
| AnnaBridge | 189:f392fc9709a3 | 211 | uint8_t BOOTBit1Config; /*!< BOOT1Config: Together with input pad Boot0, this bit selects the boot source, flash, ram or system memory |
| AnnaBridge | 189:f392fc9709a3 | 212 | This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOTBit1 */ |
| AnnaBridge | 189:f392fc9709a3 | 213 | } FLASH_OBProgramInitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 214 | |
| AnnaBridge | 189:f392fc9709a3 | 215 | #if defined(FLASH_OPTR_WPRMOD) || defined(FLASH_OPTR_BFB2) |
| AnnaBridge | 189:f392fc9709a3 | 216 | /** |
| AnnaBridge | 189:f392fc9709a3 | 217 | * @brief FLASH Advanced Option Bytes Program structure definition |
| AnnaBridge | 189:f392fc9709a3 | 218 | */ |
| AnnaBridge | 189:f392fc9709a3 | 219 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 220 | { |
| AnnaBridge | 189:f392fc9709a3 | 221 | uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension . |
| AnnaBridge | 189:f392fc9709a3 | 222 | This parameter can be a value of @ref FLASHEx_OptionAdv_Type */ |
| AnnaBridge | 189:f392fc9709a3 | 223 | |
| AnnaBridge | 189:f392fc9709a3 | 224 | #if defined(FLASH_OPTR_WPRMOD) |
| AnnaBridge | 189:f392fc9709a3 | 225 | uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation. |
| AnnaBridge | 189:f392fc9709a3 | 226 | This parameter can be a value of @ref FLASHEx_PCROP_State */ |
| AnnaBridge | 189:f392fc9709a3 | 227 | |
| AnnaBridge | 189:f392fc9709a3 | 228 | uint32_t PCROPSector; /*!< PCROPSector : This bitfield specifies the sector(s) which are read/write protected. |
| AnnaBridge | 189:f392fc9709a3 | 229 | This parameter can be a combination of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ |
| AnnaBridge | 189:f392fc9709a3 | 230 | |
| AnnaBridge | 189:f392fc9709a3 | 231 | #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
| AnnaBridge | 189:f392fc9709a3 | 232 | uint32_t PCROPSector2; /*!< PCROPSector : This bitfield specifies the sector(s) upper Sector31 which are read/write protected. |
| AnnaBridge | 189:f392fc9709a3 | 233 | This parameter can be a combination of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */ |
| AnnaBridge | 189:f392fc9709a3 | 234 | #endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ |
| AnnaBridge | 189:f392fc9709a3 | 235 | #endif /* FLASH_OPTR_WPRMOD */ |
| AnnaBridge | 189:f392fc9709a3 | 236 | |
| AnnaBridge | 189:f392fc9709a3 | 237 | #if defined(FLASH_OPTR_BFB2) |
| AnnaBridge | 189:f392fc9709a3 | 238 | uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config |
| AnnaBridge | 189:f392fc9709a3 | 239 | This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */ |
| AnnaBridge | 189:f392fc9709a3 | 240 | #endif /* FLASH_OPTR_BFB2*/ |
| AnnaBridge | 189:f392fc9709a3 | 241 | } FLASH_AdvOBProgramInitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 242 | |
| AnnaBridge | 189:f392fc9709a3 | 243 | /** |
| AnnaBridge | 189:f392fc9709a3 | 244 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 245 | */ |
| AnnaBridge | 189:f392fc9709a3 | 246 | #endif /* FLASH_OPTR_WPRMOD || FLASH_OPTR_BFB2 */ |
| AnnaBridge | 189:f392fc9709a3 | 247 | |
| AnnaBridge | 189:f392fc9709a3 | 248 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 249 | |
| AnnaBridge | 189:f392fc9709a3 | 250 | |
| AnnaBridge | 189:f392fc9709a3 | 251 | /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 252 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 253 | */ |
| AnnaBridge | 189:f392fc9709a3 | 254 | |
| AnnaBridge | 189:f392fc9709a3 | 255 | /** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase |
| AnnaBridge | 189:f392fc9709a3 | 256 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 257 | */ |
| AnnaBridge | 189:f392fc9709a3 | 258 | #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00U) /*!<Page erase only*/ |
| AnnaBridge | 189:f392fc9709a3 | 259 | |
| AnnaBridge | 189:f392fc9709a3 | 260 | /** |
| AnnaBridge | 189:f392fc9709a3 | 261 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 262 | */ |
| AnnaBridge | 189:f392fc9709a3 | 263 | |
| AnnaBridge | 189:f392fc9709a3 | 264 | /** @defgroup FLASHEx_Option_Type FLASHEx Option Type |
| AnnaBridge | 189:f392fc9709a3 | 265 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 266 | */ |
| AnnaBridge | 189:f392fc9709a3 | 267 | #define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!<WRP option byte configuration*/ |
| AnnaBridge | 189:f392fc9709a3 | 268 | #define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!<RDP option byte configuration*/ |
| AnnaBridge | 189:f392fc9709a3 | 269 | #define OPTIONBYTE_USER ((uint32_t)0x04U) /*!<USER option byte configuration*/ |
| AnnaBridge | 189:f392fc9709a3 | 270 | #define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!<BOR option byte configuration*/ |
| AnnaBridge | 189:f392fc9709a3 | 271 | #define OPTIONBYTE_BOOT_BIT1 ((uint32_t)0x10U) /*!< BOOT PIN1 option byte configuration*/ |
| AnnaBridge | 189:f392fc9709a3 | 272 | |
| AnnaBridge | 189:f392fc9709a3 | 273 | /** |
| AnnaBridge | 189:f392fc9709a3 | 274 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 275 | */ |
| AnnaBridge | 189:f392fc9709a3 | 276 | |
| AnnaBridge | 189:f392fc9709a3 | 277 | /** @defgroup FLASHEx_WRP_State FLASHEx WRP State |
| AnnaBridge | 189:f392fc9709a3 | 278 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 279 | */ |
| AnnaBridge | 189:f392fc9709a3 | 280 | #define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!<Disable the write protection of the desired sectors*/ |
| AnnaBridge | 189:f392fc9709a3 | 281 | #define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!<Enable the write protection of the desired sectors*/ |
| AnnaBridge | 189:f392fc9709a3 | 282 | |
| AnnaBridge | 189:f392fc9709a3 | 283 | /** |
| AnnaBridge | 189:f392fc9709a3 | 284 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 285 | */ |
| AnnaBridge | 189:f392fc9709a3 | 286 | |
| AnnaBridge | 189:f392fc9709a3 | 287 | #if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx) |
| AnnaBridge | 189:f392fc9709a3 | 288 | /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection |
| AnnaBridge | 189:f392fc9709a3 | 289 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 290 | */ |
| AnnaBridge | 189:f392fc9709a3 | 291 | #define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */ |
| AnnaBridge | 189:f392fc9709a3 | 292 | #define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */ |
| AnnaBridge | 189:f392fc9709a3 | 293 | #define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */ |
| AnnaBridge | 189:f392fc9709a3 | 294 | #define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */ |
| AnnaBridge | 189:f392fc9709a3 | 295 | #define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */ |
| AnnaBridge | 189:f392fc9709a3 | 296 | #define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */ |
| AnnaBridge | 189:f392fc9709a3 | 297 | #define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */ |
| AnnaBridge | 189:f392fc9709a3 | 298 | #define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */ |
| AnnaBridge | 189:f392fc9709a3 | 299 | #define OB_WRP_AllPages ((uint32_t)0x000000FFU) /*!< Write protection of all Sectors */ |
| AnnaBridge | 189:f392fc9709a3 | 300 | /** |
| AnnaBridge | 189:f392fc9709a3 | 301 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 302 | */ |
| AnnaBridge | 189:f392fc9709a3 | 303 | #elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) |
| AnnaBridge | 189:f392fc9709a3 | 304 | /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection |
| AnnaBridge | 189:f392fc9709a3 | 305 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 306 | */ |
| AnnaBridge | 189:f392fc9709a3 | 307 | #define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */ |
| AnnaBridge | 189:f392fc9709a3 | 308 | #define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */ |
| AnnaBridge | 189:f392fc9709a3 | 309 | #define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */ |
| AnnaBridge | 189:f392fc9709a3 | 310 | #define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */ |
| AnnaBridge | 189:f392fc9709a3 | 311 | #define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */ |
| AnnaBridge | 189:f392fc9709a3 | 312 | #define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */ |
| AnnaBridge | 189:f392fc9709a3 | 313 | #define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */ |
| AnnaBridge | 189:f392fc9709a3 | 314 | #define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */ |
| AnnaBridge | 189:f392fc9709a3 | 315 | #define OB_WRP_Pages256to287 ((uint32_t)0x00000100U) /* Write protection of Sector8 */ |
| AnnaBridge | 189:f392fc9709a3 | 316 | #define OB_WRP_Pages288to319 ((uint32_t)0x00000200U) /* Write protection of Sector9 */ |
| AnnaBridge | 189:f392fc9709a3 | 317 | #define OB_WRP_Pages320to351 ((uint32_t)0x00000400U) /* Write protection of Sector10 */ |
| AnnaBridge | 189:f392fc9709a3 | 318 | #define OB_WRP_Pages352to383 ((uint32_t)0x00000800U) /* Write protection of Sector11 */ |
| AnnaBridge | 189:f392fc9709a3 | 319 | #define OB_WRP_Pages384to415 ((uint32_t)0x00001000U) /* Write protection of Sector12 */ |
| AnnaBridge | 189:f392fc9709a3 | 320 | #define OB_WRP_Pages416to447 ((uint32_t)0x00002000U) /* Write protection of Sector13 */ |
| AnnaBridge | 189:f392fc9709a3 | 321 | #define OB_WRP_Pages448to479 ((uint32_t)0x00004000U) /* Write protection of Sector14 */ |
| AnnaBridge | 189:f392fc9709a3 | 322 | #define OB_WRP_Pages480to511 ((uint32_t)0x00008000U) /* Write protection of Sector15 */ |
| AnnaBridge | 189:f392fc9709a3 | 323 | #define OB_WRP_AllPages ((uint32_t)0x0000FFFFU) /*!< Write protection of all Sectors */ |
| AnnaBridge | 189:f392fc9709a3 | 324 | /** |
| AnnaBridge | 189:f392fc9709a3 | 325 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 326 | */ |
| AnnaBridge | 189:f392fc9709a3 | 327 | |
| AnnaBridge | 189:f392fc9709a3 | 328 | #elif defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
| AnnaBridge | 189:f392fc9709a3 | 329 | /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write ProtectionP |
| AnnaBridge | 189:f392fc9709a3 | 330 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 331 | */ |
| AnnaBridge | 189:f392fc9709a3 | 332 | #define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */ |
| AnnaBridge | 189:f392fc9709a3 | 333 | #define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */ |
| AnnaBridge | 189:f392fc9709a3 | 334 | #define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */ |
| AnnaBridge | 189:f392fc9709a3 | 335 | #define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */ |
| AnnaBridge | 189:f392fc9709a3 | 336 | #define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */ |
| AnnaBridge | 189:f392fc9709a3 | 337 | #define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */ |
| AnnaBridge | 189:f392fc9709a3 | 338 | #define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */ |
| AnnaBridge | 189:f392fc9709a3 | 339 | #define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */ |
| AnnaBridge | 189:f392fc9709a3 | 340 | #define OB_WRP_Pages256to287 ((uint32_t)0x00000100U) /* Write protection of Sector8 */ |
| AnnaBridge | 189:f392fc9709a3 | 341 | #define OB_WRP_Pages288to319 ((uint32_t)0x00000200U) /* Write protection of Sector9 */ |
| AnnaBridge | 189:f392fc9709a3 | 342 | #define OB_WRP_Pages320to351 ((uint32_t)0x00000400U) /* Write protection of Sector10 */ |
| AnnaBridge | 189:f392fc9709a3 | 343 | #define OB_WRP_Pages352to383 ((uint32_t)0x00000800U) /* Write protection of Sector11 */ |
| AnnaBridge | 189:f392fc9709a3 | 344 | #define OB_WRP_Pages384to415 ((uint32_t)0x00001000U) /* Write protection of Sector12 */ |
| AnnaBridge | 189:f392fc9709a3 | 345 | #define OB_WRP_Pages416to447 ((uint32_t)0x00002000U) /* Write protection of Sector13 */ |
| AnnaBridge | 189:f392fc9709a3 | 346 | #define OB_WRP_Pages448to479 ((uint32_t)0x00004000U) /* Write protection of Sector14 */ |
| AnnaBridge | 189:f392fc9709a3 | 347 | #define OB_WRP_Pages480to511 ((uint32_t)0x00008000U) /* Write protection of Sector15 */ |
| AnnaBridge | 189:f392fc9709a3 | 348 | #define OB_WRP_Pages512to543 ((uint32_t)0x00010000U) /* Write protection of Sector16 */ |
| AnnaBridge | 189:f392fc9709a3 | 349 | #define OB_WRP_Pages544to575 ((uint32_t)0x00020000U) /* Write protection of Sector17 */ |
| AnnaBridge | 189:f392fc9709a3 | 350 | #define OB_WRP_Pages576to607 ((uint32_t)0x00040000U) /* Write protection of Sector18 */ |
| AnnaBridge | 189:f392fc9709a3 | 351 | #define OB_WRP_Pages608to639 ((uint32_t)0x00080000U) /* Write protection of Sector19 */ |
| AnnaBridge | 189:f392fc9709a3 | 352 | #define OB_WRP_Pages640to671 ((uint32_t)0x00100000U) /* Write protection of Sector20 */ |
| AnnaBridge | 189:f392fc9709a3 | 353 | #define OB_WRP_Pages672to703 ((uint32_t)0x00200000U) /* Write protection of Sector21 */ |
| AnnaBridge | 189:f392fc9709a3 | 354 | #define OB_WRP_Pages704to735 ((uint32_t)0x00400000U) /* Write protection of Sector22 */ |
| AnnaBridge | 189:f392fc9709a3 | 355 | #define OB_WRP_Pages736to767 ((uint32_t)0x00800000U) /* Write protection of Sector23 */ |
| AnnaBridge | 189:f392fc9709a3 | 356 | #define OB_WRP_Pages768to799 ((uint32_t)0x01000000U) /* Write protection of Sector24 */ |
| AnnaBridge | 189:f392fc9709a3 | 357 | #define OB_WRP_Pages800to831 ((uint32_t)0x02000000U) /* Write protection of Sector25 */ |
| AnnaBridge | 189:f392fc9709a3 | 358 | #define OB_WRP_Pages832to863 ((uint32_t)0x04000000U) /* Write protection of Sector26 */ |
| AnnaBridge | 189:f392fc9709a3 | 359 | #define OB_WRP_Pages864to895 ((uint32_t)0x08000000U) /* Write protection of Sector27 */ |
| AnnaBridge | 189:f392fc9709a3 | 360 | #define OB_WRP_Pages896to927 ((uint32_t)0x10000000U) /* Write protection of Sector28 */ |
| AnnaBridge | 189:f392fc9709a3 | 361 | #define OB_WRP_Pages928to959 ((uint32_t)0x20000000U) /* Write protection of Sector29 */ |
| AnnaBridge | 189:f392fc9709a3 | 362 | #define OB_WRP_Pages960to991 ((uint32_t)0x40000000U) /* Write protection of Sector30 */ |
| AnnaBridge | 189:f392fc9709a3 | 363 | #define OB_WRP_Pages992to1023 ((uint32_t)0x80000000U) /* Write protection of Sector31 */ |
| AnnaBridge | 189:f392fc9709a3 | 364 | #define OB_WRP_AllPages ((uint32_t)0xFFFFFFFFU) /*!<Write protection of all Sectors */ |
| AnnaBridge | 189:f392fc9709a3 | 365 | /** |
| AnnaBridge | 189:f392fc9709a3 | 366 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 367 | */ |
| AnnaBridge | 189:f392fc9709a3 | 368 | |
| AnnaBridge | 189:f392fc9709a3 | 369 | /** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASH Option Bytes Write Protection |
| AnnaBridge | 189:f392fc9709a3 | 370 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 371 | */ |
| AnnaBridge | 189:f392fc9709a3 | 372 | #define OB_WRP2_Pages1024to1055 ((uint32_t)0x00000001U) /* Write protection of Sector32 */ |
| AnnaBridge | 189:f392fc9709a3 | 373 | #define OB_WRP2_Pages1056to1087 ((uint32_t)0x00000002U) /* Write protection of Sector33 */ |
| AnnaBridge | 189:f392fc9709a3 | 374 | #define OB_WRP2_Pages1088to1119 ((uint32_t)0x00000004U) /* Write protection of Sector34 */ |
| AnnaBridge | 189:f392fc9709a3 | 375 | #define OB_WRP2_Pages1120to1151 ((uint32_t)0x00000008U) /* Write protection of Sector35 */ |
| AnnaBridge | 189:f392fc9709a3 | 376 | #define OB_WRP2_Pages1152to1183 ((uint32_t)0x00000010U) /* Write protection of Sector36 */ |
| AnnaBridge | 189:f392fc9709a3 | 377 | #define OB_WRP2_Pages1184to1215 ((uint32_t)0x00000020U) /* Write protection of Sector37 */ |
| AnnaBridge | 189:f392fc9709a3 | 378 | #define OB_WRP2_Pages1216to1247 ((uint32_t)0x00000040U) /* Write protection of Sector38 */ |
| AnnaBridge | 189:f392fc9709a3 | 379 | #define OB_WRP2_Pages1248to1279 ((uint32_t)0x00000080U) /* Write protection of Sector39 */ |
| AnnaBridge | 189:f392fc9709a3 | 380 | #define OB_WRP2_Pages1280to1311 ((uint32_t)0x00000100U) /* Write protection of Sector40 */ |
| AnnaBridge | 189:f392fc9709a3 | 381 | #define OB_WRP2_Pages1312to1343 ((uint32_t)0x00000200U) /* Write protection of Sector41 */ |
| AnnaBridge | 189:f392fc9709a3 | 382 | #define OB_WRP2_Pages1344to1375 ((uint32_t)0x00000400U) /* Write protection of Sector42 */ |
| AnnaBridge | 189:f392fc9709a3 | 383 | #define OB_WRP2_Pages1376to1407 ((uint32_t)0x00000800U) /* Write protection of Sector43 */ |
| AnnaBridge | 189:f392fc9709a3 | 384 | #define OB_WRP2_Pages1408to1439 ((uint32_t)0x00001000U) /* Write protection of Sector44 */ |
| AnnaBridge | 189:f392fc9709a3 | 385 | #define OB_WRP2_Pages1440to1471 ((uint32_t)0x00002000U) /* Write protection of Sector45 */ |
| AnnaBridge | 189:f392fc9709a3 | 386 | #define OB_WRP2_Pages1472to1503 ((uint32_t)0x00004000U) /* Write protection of Sector46 */ |
| AnnaBridge | 189:f392fc9709a3 | 387 | #define OB_WRP2_Pages1504to1535 ((uint32_t)0x00008000U) /* Write protection of Sector47 */ |
| AnnaBridge | 189:f392fc9709a3 | 388 | #define OB_WRP2_AllPages ((uint32_t)0x0000FFFFU) /*!< Write protection of all Sectors WRP2 */ |
| AnnaBridge | 189:f392fc9709a3 | 389 | /** |
| AnnaBridge | 189:f392fc9709a3 | 390 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 391 | */ |
| AnnaBridge | 189:f392fc9709a3 | 392 | #endif /* STM32L071xx || STM32L072xx || (STM32L073xx) || (STM32L081xx) || (STM32L082xx) || (STM32L083xx) */ |
| AnnaBridge | 189:f392fc9709a3 | 393 | |
| AnnaBridge | 189:f392fc9709a3 | 394 | /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection |
| AnnaBridge | 189:f392fc9709a3 | 395 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 396 | */ |
| AnnaBridge | 189:f392fc9709a3 | 397 | #define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) |
| AnnaBridge | 189:f392fc9709a3 | 398 | #define OB_RDP_LEVEL_1 ((uint8_t)0xBBU) |
| AnnaBridge | 189:f392fc9709a3 | 399 | #define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2 |
| AnnaBridge | 189:f392fc9709a3 | 400 | it is no more possible to go back to level 1 or 0 */ |
| AnnaBridge | 189:f392fc9709a3 | 401 | |
| AnnaBridge | 189:f392fc9709a3 | 402 | /** |
| AnnaBridge | 189:f392fc9709a3 | 403 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 404 | */ |
| AnnaBridge | 189:f392fc9709a3 | 405 | |
| AnnaBridge | 189:f392fc9709a3 | 406 | /** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level |
| AnnaBridge | 189:f392fc9709a3 | 407 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 408 | */ |
| AnnaBridge | 189:f392fc9709a3 | 409 | |
| AnnaBridge | 189:f392fc9709a3 | 410 | #define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD |
| AnnaBridge | 189:f392fc9709a3 | 411 | power supply reaches the PDR(Power Down Reset) threshold (1.5V) */ |
| AnnaBridge | 189:f392fc9709a3 | 412 | #define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */ |
| AnnaBridge | 189:f392fc9709a3 | 413 | #define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */ |
| AnnaBridge | 189:f392fc9709a3 | 414 | #define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */ |
| AnnaBridge | 189:f392fc9709a3 | 415 | #define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */ |
| AnnaBridge | 189:f392fc9709a3 | 416 | #define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */ |
| AnnaBridge | 189:f392fc9709a3 | 417 | |
| AnnaBridge | 189:f392fc9709a3 | 418 | /** |
| AnnaBridge | 189:f392fc9709a3 | 419 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 420 | */ |
| AnnaBridge | 189:f392fc9709a3 | 421 | |
| AnnaBridge | 189:f392fc9709a3 | 422 | /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog |
| AnnaBridge | 189:f392fc9709a3 | 423 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 424 | */ |
| AnnaBridge | 189:f392fc9709a3 | 425 | |
| AnnaBridge | 189:f392fc9709a3 | 426 | #define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */ |
| AnnaBridge | 189:f392fc9709a3 | 427 | #define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */ |
| AnnaBridge | 189:f392fc9709a3 | 428 | |
| AnnaBridge | 189:f392fc9709a3 | 429 | /** |
| AnnaBridge | 189:f392fc9709a3 | 430 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 431 | */ |
| AnnaBridge | 189:f392fc9709a3 | 432 | |
| AnnaBridge | 189:f392fc9709a3 | 433 | /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP |
| AnnaBridge | 189:f392fc9709a3 | 434 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 435 | */ |
| AnnaBridge | 189:f392fc9709a3 | 436 | |
| AnnaBridge | 189:f392fc9709a3 | 437 | #define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */ |
| AnnaBridge | 189:f392fc9709a3 | 438 | #define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */ |
| AnnaBridge | 189:f392fc9709a3 | 439 | /** |
| AnnaBridge | 189:f392fc9709a3 | 440 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 441 | */ |
| AnnaBridge | 189:f392fc9709a3 | 442 | |
| AnnaBridge | 189:f392fc9709a3 | 443 | /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY |
| AnnaBridge | 189:f392fc9709a3 | 444 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 445 | */ |
| AnnaBridge | 189:f392fc9709a3 | 446 | |
| AnnaBridge | 189:f392fc9709a3 | 447 | #define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */ |
| AnnaBridge | 189:f392fc9709a3 | 448 | #define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */ |
| AnnaBridge | 189:f392fc9709a3 | 449 | |
| AnnaBridge | 189:f392fc9709a3 | 450 | /** |
| AnnaBridge | 189:f392fc9709a3 | 451 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 452 | */ |
| AnnaBridge | 189:f392fc9709a3 | 453 | |
| AnnaBridge | 189:f392fc9709a3 | 454 | #if defined(FLASH_OPTR_WPRMOD) |
| AnnaBridge | 189:f392fc9709a3 | 455 | |
| AnnaBridge | 189:f392fc9709a3 | 456 | /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type |
| AnnaBridge | 189:f392fc9709a3 | 457 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 458 | */ |
| AnnaBridge | 189:f392fc9709a3 | 459 | |
| AnnaBridge | 189:f392fc9709a3 | 460 | #define OPTIONBYTE_PCROP ((uint32_t)0x01U) /*!<PCROP option byte configuration*/ |
| AnnaBridge | 189:f392fc9709a3 | 461 | |
| AnnaBridge | 189:f392fc9709a3 | 462 | /** |
| AnnaBridge | 189:f392fc9709a3 | 463 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 464 | */ |
| AnnaBridge | 189:f392fc9709a3 | 465 | |
| AnnaBridge | 189:f392fc9709a3 | 466 | #endif /* FLASH_OPTR_WPRMOD */ |
| AnnaBridge | 189:f392fc9709a3 | 467 | |
| AnnaBridge | 189:f392fc9709a3 | 468 | #if defined(FLASH_OPTR_BFB2) |
| AnnaBridge | 189:f392fc9709a3 | 469 | |
| AnnaBridge | 189:f392fc9709a3 | 470 | /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type |
| AnnaBridge | 189:f392fc9709a3 | 471 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 472 | */ |
| AnnaBridge | 189:f392fc9709a3 | 473 | |
| AnnaBridge | 189:f392fc9709a3 | 474 | #define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02U) /*!<BOOTConfig option byte configuration*/ |
| AnnaBridge | 189:f392fc9709a3 | 475 | |
| AnnaBridge | 189:f392fc9709a3 | 476 | /** |
| AnnaBridge | 189:f392fc9709a3 | 477 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 478 | */ |
| AnnaBridge | 189:f392fc9709a3 | 479 | |
| AnnaBridge | 189:f392fc9709a3 | 480 | #endif /* FLASH_OPTR_BFB2 */ |
| AnnaBridge | 189:f392fc9709a3 | 481 | |
| AnnaBridge | 189:f392fc9709a3 | 482 | #if defined(FLASH_OPTR_WPRMOD) |
| AnnaBridge | 189:f392fc9709a3 | 483 | |
| AnnaBridge | 189:f392fc9709a3 | 484 | /** @defgroup FLASHEx_PCROP_State FLASHEx PCROP State |
| AnnaBridge | 189:f392fc9709a3 | 485 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 486 | */ |
| AnnaBridge | 189:f392fc9709a3 | 487 | #define OB_PCROP_STATE_DISABLE ((uint32_t)0x00U) /*!<Disable PCROP for selected sectors */ |
| AnnaBridge | 189:f392fc9709a3 | 488 | #define OB_PCROP_STATE_ENABLE ((uint32_t)0x01U) /*!<Enable PCROP for selected sectors */ |
| AnnaBridge | 189:f392fc9709a3 | 489 | |
| AnnaBridge | 189:f392fc9709a3 | 490 | /** |
| AnnaBridge | 189:f392fc9709a3 | 491 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 492 | */ |
| AnnaBridge | 189:f392fc9709a3 | 493 | |
| AnnaBridge | 189:f392fc9709a3 | 494 | /** @defgroup FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode |
| AnnaBridge | 189:f392fc9709a3 | 495 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 496 | */ |
| AnnaBridge | 189:f392fc9709a3 | 497 | #define OB_PCROP_DESELECTED ((uint16_t)0x0000U) /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */ |
| AnnaBridge | 189:f392fc9709a3 | 498 | #define OB_PCROP_SELECTED ((uint16_t)FLASH_OPTR_WPRMOD) /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i */ |
| AnnaBridge | 189:f392fc9709a3 | 499 | |
| AnnaBridge | 189:f392fc9709a3 | 500 | /** |
| AnnaBridge | 189:f392fc9709a3 | 501 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 502 | */ |
| AnnaBridge | 189:f392fc9709a3 | 503 | #endif /* FLASH_OPTR_WPRMOD */ |
| AnnaBridge | 189:f392fc9709a3 | 504 | |
| AnnaBridge | 189:f392fc9709a3 | 505 | #if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx) |
| AnnaBridge | 189:f392fc9709a3 | 506 | /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASHEx Option Bytes PC Read/Write Protection |
| AnnaBridge | 189:f392fc9709a3 | 507 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 508 | */ |
| AnnaBridge | 189:f392fc9709a3 | 509 | #define OB_PCROP_Pages0to31 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */ |
| AnnaBridge | 189:f392fc9709a3 | 510 | #define OB_PCROP_Pages32to63 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */ |
| AnnaBridge | 189:f392fc9709a3 | 511 | #define OB_PCROP_Pages64to95 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */ |
| AnnaBridge | 189:f392fc9709a3 | 512 | #define OB_PCROP_Pages96to127 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */ |
| AnnaBridge | 189:f392fc9709a3 | 513 | #define OB_PCROP_Pages128to159 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */ |
| AnnaBridge | 189:f392fc9709a3 | 514 | #define OB_PCROP_Pages160to191 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */ |
| AnnaBridge | 189:f392fc9709a3 | 515 | #define OB_PCROP_Pages192to223 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */ |
| AnnaBridge | 189:f392fc9709a3 | 516 | #define OB_PCROP_Pages224to255 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */ |
| AnnaBridge | 189:f392fc9709a3 | 517 | #define OB_PCROP_AllPages ((uint32_t)0x000000FFU) /*!< PC Read/Write protection of all Sectors */ |
| AnnaBridge | 189:f392fc9709a3 | 518 | /** |
| AnnaBridge | 189:f392fc9709a3 | 519 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 520 | */ |
| AnnaBridge | 189:f392fc9709a3 | 521 | #elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) |
| AnnaBridge | 189:f392fc9709a3 | 522 | /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASHEx Option Bytes PC Read/Write Protection |
| AnnaBridge | 189:f392fc9709a3 | 523 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 524 | */ |
| AnnaBridge | 189:f392fc9709a3 | 525 | #define OB_PCROP_Pages0to31 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */ |
| AnnaBridge | 189:f392fc9709a3 | 526 | #define OB_PCROP_Pages32to63 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */ |
| AnnaBridge | 189:f392fc9709a3 | 527 | #define OB_PCROP_Pages64to95 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */ |
| AnnaBridge | 189:f392fc9709a3 | 528 | #define OB_PCROP_Pages96to127 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */ |
| AnnaBridge | 189:f392fc9709a3 | 529 | #define OB_PCROP_Pages128to159 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */ |
| AnnaBridge | 189:f392fc9709a3 | 530 | #define OB_PCROP_Pages160to191 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */ |
| AnnaBridge | 189:f392fc9709a3 | 531 | #define OB_PCROP_Pages192to223 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */ |
| AnnaBridge | 189:f392fc9709a3 | 532 | #define OB_PCROP_Pages224to255 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */ |
| AnnaBridge | 189:f392fc9709a3 | 533 | #define OB_PCROP_Pages256to287 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector8 */ |
| AnnaBridge | 189:f392fc9709a3 | 534 | #define OB_PCROP_Pages288to319 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector9 */ |
| AnnaBridge | 189:f392fc9709a3 | 535 | #define OB_PCROP_Pages320to351 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector10 */ |
| AnnaBridge | 189:f392fc9709a3 | 536 | #define OB_PCROP_Pages352to383 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector11 */ |
| AnnaBridge | 189:f392fc9709a3 | 537 | #define OB_PCROP_Pages384to415 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector12 */ |
| AnnaBridge | 189:f392fc9709a3 | 538 | #define OB_PCROP_Pages416to447 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector13 */ |
| AnnaBridge | 189:f392fc9709a3 | 539 | #define OB_PCROP_Pages448to479 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector14 */ |
| AnnaBridge | 189:f392fc9709a3 | 540 | #define OB_PCROP_Pages480to511 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector15 */ |
| AnnaBridge | 189:f392fc9709a3 | 541 | #define OB_PCROP_AllPages ((uint32_t)0x0000FFFFU) /*!< PC Read/Write protection of all Sectors */ |
| AnnaBridge | 189:f392fc9709a3 | 542 | /** |
| AnnaBridge | 189:f392fc9709a3 | 543 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 544 | */ |
| AnnaBridge | 189:f392fc9709a3 | 545 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 546 | |
| AnnaBridge | 189:f392fc9709a3 | 547 | #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
| AnnaBridge | 189:f392fc9709a3 | 548 | /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC Read/Write Protection |
| AnnaBridge | 189:f392fc9709a3 | 549 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 550 | */ |
| AnnaBridge | 189:f392fc9709a3 | 551 | #define OB_PCROP_Pages0to31 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */ |
| AnnaBridge | 189:f392fc9709a3 | 552 | #define OB_PCROP_Pages32to63 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */ |
| AnnaBridge | 189:f392fc9709a3 | 553 | #define OB_PCROP_Pages64to95 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */ |
| AnnaBridge | 189:f392fc9709a3 | 554 | #define OB_PCROP_Pages96to127 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */ |
| AnnaBridge | 189:f392fc9709a3 | 555 | #define OB_PCROP_Pages128to159 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */ |
| AnnaBridge | 189:f392fc9709a3 | 556 | #define OB_PCROP_Pages160to191 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */ |
| AnnaBridge | 189:f392fc9709a3 | 557 | #define OB_PCROP_Pages192to223 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */ |
| AnnaBridge | 189:f392fc9709a3 | 558 | #define OB_PCROP_Pages224to255 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */ |
| AnnaBridge | 189:f392fc9709a3 | 559 | #define OB_PCROP_Pages256to287 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector8 */ |
| AnnaBridge | 189:f392fc9709a3 | 560 | #define OB_PCROP_Pages288to319 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector9 */ |
| AnnaBridge | 189:f392fc9709a3 | 561 | #define OB_PCROP_Pages320to351 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector10 */ |
| AnnaBridge | 189:f392fc9709a3 | 562 | #define OB_PCROP_Pages352to383 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector11 */ |
| AnnaBridge | 189:f392fc9709a3 | 563 | #define OB_PCROP_Pages384to415 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector12 */ |
| AnnaBridge | 189:f392fc9709a3 | 564 | #define OB_PCROP_Pages416to447 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector13 */ |
| AnnaBridge | 189:f392fc9709a3 | 565 | #define OB_PCROP_Pages448to479 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector14 */ |
| AnnaBridge | 189:f392fc9709a3 | 566 | #define OB_PCROP_Pages480to511 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector15 */ |
| AnnaBridge | 189:f392fc9709a3 | 567 | #define OB_PCROP_Pages512to543 ((uint32_t)0x00010000U) /* PC Read/Write protection of Sector16 */ |
| AnnaBridge | 189:f392fc9709a3 | 568 | #define OB_PCROP_Pages544to575 ((uint32_t)0x00020000U) /* PC Read/Write protection of Sector17 */ |
| AnnaBridge | 189:f392fc9709a3 | 569 | #define OB_PCROP_Pages576to607 ((uint32_t)0x00040000U) /* PC Read/Write protection of Sector18 */ |
| AnnaBridge | 189:f392fc9709a3 | 570 | #define OB_PCROP_Pages608to639 ((uint32_t)0x00080000U) /* PC Read/Write protection of Sector19 */ |
| AnnaBridge | 189:f392fc9709a3 | 571 | #define OB_PCROP_Pages640to671 ((uint32_t)0x00100000U) /* PC Read/Write protection of Sector20 */ |
| AnnaBridge | 189:f392fc9709a3 | 572 | #define OB_PCROP_Pages672to703 ((uint32_t)0x00200000U) /* PC Read/Write protection of Sector21 */ |
| AnnaBridge | 189:f392fc9709a3 | 573 | #define OB_PCROP_Pages704to735 ((uint32_t)0x00400000U) /* PC Read/Write protection of Sector22 */ |
| AnnaBridge | 189:f392fc9709a3 | 574 | #define OB_PCROP_Pages736to767 ((uint32_t)0x00800000U) /* PC Read/Write protection of Sector23 */ |
| AnnaBridge | 189:f392fc9709a3 | 575 | #define OB_PCROP_Pages768to799 ((uint32_t)0x01000000U) /* PC Read/Write protection of Sector24 */ |
| AnnaBridge | 189:f392fc9709a3 | 576 | #define OB_PCROP_Pages800to831 ((uint32_t)0x02000000U) /* PC Read/Write protection of Sector25 */ |
| AnnaBridge | 189:f392fc9709a3 | 577 | #define OB_PCROP_Pages832to863 ((uint32_t)0x04000000U) /* PC Read/Write protection of Sector26 */ |
| AnnaBridge | 189:f392fc9709a3 | 578 | #define OB_PCROP_Pages864to895 ((uint32_t)0x08000000U) /* PC Read/Write protection of Sector27 */ |
| AnnaBridge | 189:f392fc9709a3 | 579 | #define OB_PCROP_Pages896to927 ((uint32_t)0x10000000U) /* PC Read/Write protection of Sector28 */ |
| AnnaBridge | 189:f392fc9709a3 | 580 | #define OB_PCROP_Pages928to959 ((uint32_t)0x20000000U) /* PC Read/Write protection of Sector29 */ |
| AnnaBridge | 189:f392fc9709a3 | 581 | #define OB_PCROP_Pages960to991 ((uint32_t)0x40000000U) /* PC Read/Write protection of Sector30 */ |
| AnnaBridge | 189:f392fc9709a3 | 582 | #define OB_PCROP_Pages992to1023 ((uint32_t)0x80000000U) /* PC Read/Write protection of Sector31 */ |
| AnnaBridge | 189:f392fc9709a3 | 583 | #define OB_PCROP_AllPages ((uint32_t)0xFFFFFFFFU) /*!<PC Read/Write protection of all Sectors */ |
| AnnaBridge | 189:f392fc9709a3 | 584 | /** |
| AnnaBridge | 189:f392fc9709a3 | 585 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 586 | */ |
| AnnaBridge | 189:f392fc9709a3 | 587 | |
| AnnaBridge | 189:f392fc9709a3 | 588 | /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASH Option Bytes PC Read/Write Protection (Sector 2) |
| AnnaBridge | 189:f392fc9709a3 | 589 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 590 | */ |
| AnnaBridge | 189:f392fc9709a3 | 591 | #define OB_PCROP2_Pages1024to1055 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector32 */ |
| AnnaBridge | 189:f392fc9709a3 | 592 | #define OB_PCROP2_Pages1056to1087 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector33 */ |
| AnnaBridge | 189:f392fc9709a3 | 593 | #define OB_PCROP2_Pages1088to1119 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector34 */ |
| AnnaBridge | 189:f392fc9709a3 | 594 | #define OB_PCROP2_Pages1120to1151 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector35 */ |
| AnnaBridge | 189:f392fc9709a3 | 595 | #define OB_PCROP2_Pages1152to1183 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector36 */ |
| AnnaBridge | 189:f392fc9709a3 | 596 | #define OB_PCROP2_Pages1184to1215 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector37 */ |
| AnnaBridge | 189:f392fc9709a3 | 597 | #define OB_PCROP2_Pages1216to1247 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector38 */ |
| AnnaBridge | 189:f392fc9709a3 | 598 | #define OB_PCROP2_Pages1248to1279 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector39 */ |
| AnnaBridge | 189:f392fc9709a3 | 599 | #define OB_PCROP2_Pages1280to1311 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector40 */ |
| AnnaBridge | 189:f392fc9709a3 | 600 | #define OB_PCROP2_Pages1312to1343 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector41 */ |
| AnnaBridge | 189:f392fc9709a3 | 601 | #define OB_PCROP2_Pages1344to1375 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector42 */ |
| AnnaBridge | 189:f392fc9709a3 | 602 | #define OB_PCROP2_Pages1376to1407 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector43 */ |
| AnnaBridge | 189:f392fc9709a3 | 603 | #define OB_PCROP2_Pages1408to1439 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector44 */ |
| AnnaBridge | 189:f392fc9709a3 | 604 | #define OB_PCROP2_Pages1440to1471 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector45 */ |
| AnnaBridge | 189:f392fc9709a3 | 605 | #define OB_PCROP2_Pages1472to1503 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector46 */ |
| AnnaBridge | 189:f392fc9709a3 | 606 | #define OB_PCROP2_Pages1504to1535 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector47 */ |
| AnnaBridge | 189:f392fc9709a3 | 607 | #define OB_PCROP2_AllPages ((uint32_t)0x0000FFFFU) /*!< PC Read/Write protection of all Sectors PCROP2 */ |
| AnnaBridge | 189:f392fc9709a3 | 608 | /** |
| AnnaBridge | 189:f392fc9709a3 | 609 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 610 | */ |
| AnnaBridge | 189:f392fc9709a3 | 611 | #endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ |
| AnnaBridge | 189:f392fc9709a3 | 612 | |
| AnnaBridge | 189:f392fc9709a3 | 613 | /** @defgroup FLASHEx_Option_Bytes_BOOTBit1 FLASH Option Bytes BOOT Bit1 Setup |
| AnnaBridge | 189:f392fc9709a3 | 614 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 615 | */ |
| AnnaBridge | 189:f392fc9709a3 | 616 | #define OB_BOOT_BIT1_RESET (uint8_t)(0x00U) /*!< BOOT Bit 1 Reset */ |
| AnnaBridge | 189:f392fc9709a3 | 617 | #define OB_BOOT_BIT1_SET (uint8_t)(0x01U) /*!< BOOT Bit 1 Set */ |
| AnnaBridge | 189:f392fc9709a3 | 618 | /** |
| AnnaBridge | 189:f392fc9709a3 | 619 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 620 | */ |
| AnnaBridge | 189:f392fc9709a3 | 621 | |
| AnnaBridge | 189:f392fc9709a3 | 622 | /** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data |
| AnnaBridge | 189:f392fc9709a3 | 623 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 624 | */ |
| AnnaBridge | 189:f392fc9709a3 | 625 | #define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00U) /*!<Program byte (8-bit) at a specified address.*/ |
| AnnaBridge | 189:f392fc9709a3 | 626 | #define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01U) /*!<Program a half-word (16-bit) at a specified address.*/ |
| AnnaBridge | 189:f392fc9709a3 | 627 | #define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/ |
| AnnaBridge | 189:f392fc9709a3 | 628 | |
| AnnaBridge | 189:f392fc9709a3 | 629 | /** |
| AnnaBridge | 189:f392fc9709a3 | 630 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 631 | */ |
| AnnaBridge | 189:f392fc9709a3 | 632 | |
| AnnaBridge | 189:f392fc9709a3 | 633 | #if defined(FLASH_OPTR_BFB2) |
| AnnaBridge | 189:f392fc9709a3 | 634 | |
| AnnaBridge | 189:f392fc9709a3 | 635 | /** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT |
| AnnaBridge | 189:f392fc9709a3 | 636 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 637 | */ |
| AnnaBridge | 189:f392fc9709a3 | 638 | |
| AnnaBridge | 189:f392fc9709a3 | 639 | #define OB_BOOT_BANK1 ((uint8_t)0x00U) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position |
| AnnaBridge | 189:f392fc9709a3 | 640 | and this parameter is selected the device will boot from Bank 1 (Default)*/ |
| AnnaBridge | 189:f392fc9709a3 | 641 | #define OB_BOOT_BANK2 ((uint8_t)(FLASH_OPTR_BFB2 >> 16)) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position |
| AnnaBridge | 189:f392fc9709a3 | 642 | and this parameter is selected the device will boot from Bank 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 643 | |
| AnnaBridge | 189:f392fc9709a3 | 644 | /** |
| AnnaBridge | 189:f392fc9709a3 | 645 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 646 | */ |
| AnnaBridge | 189:f392fc9709a3 | 647 | #endif /* FLASH_OPTR_BFB2 */ |
| AnnaBridge | 189:f392fc9709a3 | 648 | |
| AnnaBridge | 189:f392fc9709a3 | 649 | /** |
| AnnaBridge | 189:f392fc9709a3 | 650 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 651 | */ |
| AnnaBridge | 189:f392fc9709a3 | 652 | |
| AnnaBridge | 189:f392fc9709a3 | 653 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 654 | |
| AnnaBridge | 189:f392fc9709a3 | 655 | /** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 656 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 657 | */ |
| AnnaBridge | 189:f392fc9709a3 | 658 | |
| AnnaBridge | 189:f392fc9709a3 | 659 | /** |
| AnnaBridge | 189:f392fc9709a3 | 660 | * @brief Set the FLASH Latency. |
| AnnaBridge | 189:f392fc9709a3 | 661 | * @param __LATENCY__ FLASH Latency |
| AnnaBridge | 189:f392fc9709a3 | 662 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 663 | * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle |
| AnnaBridge | 189:f392fc9709a3 | 664 | * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle |
| AnnaBridge | 189:f392fc9709a3 | 665 | * @retval none |
| AnnaBridge | 189:f392fc9709a3 | 666 | */ |
| AnnaBridge | 189:f392fc9709a3 | 667 | #define __HAL_FLASH_SET_LATENCY(__LATENCY__) \ |
| AnnaBridge | 189:f392fc9709a3 | 668 | MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) |
| AnnaBridge | 189:f392fc9709a3 | 669 | |
| AnnaBridge | 189:f392fc9709a3 | 670 | /** |
| AnnaBridge | 189:f392fc9709a3 | 671 | * @brief Get the FLASH Latency. |
| AnnaBridge | 189:f392fc9709a3 | 672 | * @retval FLASH Latency |
| AnnaBridge | 189:f392fc9709a3 | 673 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 674 | * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle |
| AnnaBridge | 189:f392fc9709a3 | 675 | * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle |
| AnnaBridge | 189:f392fc9709a3 | 676 | */ |
| AnnaBridge | 189:f392fc9709a3 | 677 | #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) |
| AnnaBridge | 189:f392fc9709a3 | 678 | |
| AnnaBridge | 189:f392fc9709a3 | 679 | /** |
| AnnaBridge | 189:f392fc9709a3 | 680 | * @brief Enable the FLASH prefetch buffer. |
| AnnaBridge | 189:f392fc9709a3 | 681 | * @retval none |
| AnnaBridge | 189:f392fc9709a3 | 682 | */ |
| AnnaBridge | 189:f392fc9709a3 | 683 | #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) |
| AnnaBridge | 189:f392fc9709a3 | 684 | |
| AnnaBridge | 189:f392fc9709a3 | 685 | /** |
| AnnaBridge | 189:f392fc9709a3 | 686 | * @brief Disable the FLASH prefetch buffer. |
| AnnaBridge | 189:f392fc9709a3 | 687 | * @retval none |
| AnnaBridge | 189:f392fc9709a3 | 688 | */ |
| AnnaBridge | 189:f392fc9709a3 | 689 | #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) |
| AnnaBridge | 189:f392fc9709a3 | 690 | |
| AnnaBridge | 189:f392fc9709a3 | 691 | /** |
| AnnaBridge | 189:f392fc9709a3 | 692 | * @brief Enable the FLASH Buffer cache. |
| AnnaBridge | 189:f392fc9709a3 | 693 | * @retval none |
| AnnaBridge | 189:f392fc9709a3 | 694 | */ |
| AnnaBridge | 189:f392fc9709a3 | 695 | #define __HAL_FLASH_BUFFER_CACHE_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF) |
| AnnaBridge | 189:f392fc9709a3 | 696 | |
| AnnaBridge | 189:f392fc9709a3 | 697 | /** |
| AnnaBridge | 189:f392fc9709a3 | 698 | * @brief Disable the FLASH Buffer cache. |
| AnnaBridge | 189:f392fc9709a3 | 699 | * @retval none |
| AnnaBridge | 189:f392fc9709a3 | 700 | */ |
| AnnaBridge | 189:f392fc9709a3 | 701 | #define __HAL_FLASH_BUFFER_CACHE_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF) |
| AnnaBridge | 189:f392fc9709a3 | 702 | |
| AnnaBridge | 189:f392fc9709a3 | 703 | /** |
| AnnaBridge | 189:f392fc9709a3 | 704 | * @brief Enable the FLASH preread buffer. |
| AnnaBridge | 189:f392fc9709a3 | 705 | * @retval none |
| AnnaBridge | 189:f392fc9709a3 | 706 | */ |
| AnnaBridge | 189:f392fc9709a3 | 707 | #define __HAL_FLASH_PREREAD_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRE_READ) |
| AnnaBridge | 189:f392fc9709a3 | 708 | |
| AnnaBridge | 189:f392fc9709a3 | 709 | /** |
| AnnaBridge | 189:f392fc9709a3 | 710 | * @brief Disable the FLASH preread buffer. |
| AnnaBridge | 189:f392fc9709a3 | 711 | * @retval none |
| AnnaBridge | 189:f392fc9709a3 | 712 | */ |
| AnnaBridge | 189:f392fc9709a3 | 713 | #define __HAL_FLASH_PREREAD_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRE_READ) |
| AnnaBridge | 189:f392fc9709a3 | 714 | |
| AnnaBridge | 189:f392fc9709a3 | 715 | /** |
| AnnaBridge | 189:f392fc9709a3 | 716 | * @brief Enable the FLASH power down during Sleep mode |
| AnnaBridge | 189:f392fc9709a3 | 717 | * @retval none |
| AnnaBridge | 189:f392fc9709a3 | 718 | */ |
| AnnaBridge | 189:f392fc9709a3 | 719 | #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) |
| AnnaBridge | 189:f392fc9709a3 | 720 | |
| AnnaBridge | 189:f392fc9709a3 | 721 | /** |
| AnnaBridge | 189:f392fc9709a3 | 722 | * @brief Disable the FLASH power down during Sleep mode |
| AnnaBridge | 189:f392fc9709a3 | 723 | * @retval none |
| AnnaBridge | 189:f392fc9709a3 | 724 | */ |
| AnnaBridge | 189:f392fc9709a3 | 725 | #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) |
| AnnaBridge | 189:f392fc9709a3 | 726 | |
| AnnaBridge | 189:f392fc9709a3 | 727 | /** |
| AnnaBridge | 189:f392fc9709a3 | 728 | * @brief Enable the Flash Run power down mode. |
| AnnaBridge | 189:f392fc9709a3 | 729 | * @note Writing this bit to 0 this bit, automatically the keys are |
| AnnaBridge | 189:f392fc9709a3 | 730 | * loss and a new unlock sequence is necessary to re-write it to 1. |
| AnnaBridge | 189:f392fc9709a3 | 731 | */ |
| AnnaBridge | 189:f392fc9709a3 | 732 | #define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ |
| AnnaBridge | 189:f392fc9709a3 | 733 | FLASH->PDKEYR = FLASH_PDKEY2; \ |
| AnnaBridge | 189:f392fc9709a3 | 734 | SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ |
| AnnaBridge | 189:f392fc9709a3 | 735 | } while (0) |
| AnnaBridge | 189:f392fc9709a3 | 736 | |
| AnnaBridge | 189:f392fc9709a3 | 737 | /** |
| AnnaBridge | 189:f392fc9709a3 | 738 | * @brief Disable the Flash Run power down mode. |
| AnnaBridge | 189:f392fc9709a3 | 739 | * @note Writing this bit to 0 this bit, automatically the keys are |
| AnnaBridge | 189:f392fc9709a3 | 740 | * loss and a new unlock sequence is necessary to re-write it to 1. |
| AnnaBridge | 189:f392fc9709a3 | 741 | */ |
| AnnaBridge | 189:f392fc9709a3 | 742 | #define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ |
| AnnaBridge | 189:f392fc9709a3 | 743 | FLASH->PDKEYR = FLASH_PDKEY2; \ |
| AnnaBridge | 189:f392fc9709a3 | 744 | CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ |
| AnnaBridge | 189:f392fc9709a3 | 745 | } while (0) |
| AnnaBridge | 189:f392fc9709a3 | 746 | |
| AnnaBridge | 189:f392fc9709a3 | 747 | /** |
| AnnaBridge | 189:f392fc9709a3 | 748 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 749 | */ |
| AnnaBridge | 189:f392fc9709a3 | 750 | |
| AnnaBridge | 189:f392fc9709a3 | 751 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 752 | |
| AnnaBridge | 189:f392fc9709a3 | 753 | /** @addtogroup FLASHEx_Exported_Functions |
| AnnaBridge | 189:f392fc9709a3 | 754 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 755 | */ |
| AnnaBridge | 189:f392fc9709a3 | 756 | |
| AnnaBridge | 189:f392fc9709a3 | 757 | /** @addtogroup FLASHEx_Exported_Functions_Group1 |
| AnnaBridge | 189:f392fc9709a3 | 758 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 759 | */ |
| AnnaBridge | 189:f392fc9709a3 | 760 | |
| AnnaBridge | 189:f392fc9709a3 | 761 | HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); |
| AnnaBridge | 189:f392fc9709a3 | 762 | HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); |
| AnnaBridge | 189:f392fc9709a3 | 763 | |
| AnnaBridge | 189:f392fc9709a3 | 764 | /** |
| AnnaBridge | 189:f392fc9709a3 | 765 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 766 | */ |
| AnnaBridge | 189:f392fc9709a3 | 767 | |
| AnnaBridge | 189:f392fc9709a3 | 768 | /** @addtogroup FLASHEx_Exported_Functions_Group2 |
| AnnaBridge | 189:f392fc9709a3 | 769 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 770 | */ |
| AnnaBridge | 189:f392fc9709a3 | 771 | |
| AnnaBridge | 189:f392fc9709a3 | 772 | HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); |
| AnnaBridge | 189:f392fc9709a3 | 773 | void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); |
| AnnaBridge | 189:f392fc9709a3 | 774 | |
| AnnaBridge | 189:f392fc9709a3 | 775 | #if defined(FLASH_OPTR_WPRMOD) || defined(FLASH_OPTR_BFB2) |
| AnnaBridge | 189:f392fc9709a3 | 776 | |
| AnnaBridge | 189:f392fc9709a3 | 777 | HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); |
| AnnaBridge | 189:f392fc9709a3 | 778 | void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); |
| AnnaBridge | 189:f392fc9709a3 | 779 | |
| AnnaBridge | 189:f392fc9709a3 | 780 | #endif /* FLASH_OPTR_WPRMOD || FLASH_OPTR_BFB2 */ |
| AnnaBridge | 189:f392fc9709a3 | 781 | |
| AnnaBridge | 189:f392fc9709a3 | 782 | #if defined(FLASH_OPTR_WPRMOD) |
| AnnaBridge | 189:f392fc9709a3 | 783 | |
| AnnaBridge | 189:f392fc9709a3 | 784 | HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void); |
| AnnaBridge | 189:f392fc9709a3 | 785 | HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void); |
| AnnaBridge | 189:f392fc9709a3 | 786 | |
| AnnaBridge | 189:f392fc9709a3 | 787 | #endif /* FLASH_OPTR_WPRMOD */ |
| AnnaBridge | 189:f392fc9709a3 | 788 | |
| AnnaBridge | 189:f392fc9709a3 | 789 | /** |
| AnnaBridge | 189:f392fc9709a3 | 790 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 791 | */ |
| AnnaBridge | 189:f392fc9709a3 | 792 | |
| AnnaBridge | 189:f392fc9709a3 | 793 | /** @addtogroup FLASHEx_Exported_Functions_Group3 |
| AnnaBridge | 189:f392fc9709a3 | 794 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 795 | */ |
| AnnaBridge | 189:f392fc9709a3 | 796 | |
| AnnaBridge | 189:f392fc9709a3 | 797 | HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void); |
| AnnaBridge | 189:f392fc9709a3 | 798 | HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void); |
| AnnaBridge | 189:f392fc9709a3 | 799 | |
| AnnaBridge | 189:f392fc9709a3 | 800 | HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t Address); |
| AnnaBridge | 189:f392fc9709a3 | 801 | HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data); |
| AnnaBridge | 189:f392fc9709a3 | 802 | void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void); |
| AnnaBridge | 189:f392fc9709a3 | 803 | void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void); |
| AnnaBridge | 189:f392fc9709a3 | 804 | |
| AnnaBridge | 189:f392fc9709a3 | 805 | /** |
| AnnaBridge | 189:f392fc9709a3 | 806 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 807 | */ |
| AnnaBridge | 189:f392fc9709a3 | 808 | |
| AnnaBridge | 189:f392fc9709a3 | 809 | /** |
| AnnaBridge | 189:f392fc9709a3 | 810 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 811 | */ |
| AnnaBridge | 189:f392fc9709a3 | 812 | |
| AnnaBridge | 189:f392fc9709a3 | 813 | /** |
| AnnaBridge | 189:f392fc9709a3 | 814 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 815 | */ |
| AnnaBridge | 189:f392fc9709a3 | 816 | |
| AnnaBridge | 189:f392fc9709a3 | 817 | /** |
| AnnaBridge | 189:f392fc9709a3 | 818 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 819 | */ |
| AnnaBridge | 189:f392fc9709a3 | 820 | |
| AnnaBridge | 189:f392fc9709a3 | 821 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 822 | } |
| AnnaBridge | 189:f392fc9709a3 | 823 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 824 | |
| AnnaBridge | 189:f392fc9709a3 | 825 | #endif /* __STM32L0xx_HAL_FLASH_EX_H */ |
| AnnaBridge | 189:f392fc9709a3 | 826 | |
| AnnaBridge | 189:f392fc9709a3 | 827 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
