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mbed library sources. Supersedes mbed-src.

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cmsis/BUILD/mbed/TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/stm32l0xx_hal_adc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l0xx_hal_adc.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of ADC HAL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L0xx_HAL_ADC_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L0xx_HAL_ADC_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	45	#include "stm32l0xx_hal_def.h"
AnnaBridge	189:f392fc9709a3	46
AnnaBridge	189:f392fc9709a3	47	/* Include low level driver */
AnnaBridge	189:f392fc9709a3	48	#include "stm32l0xx_ll_adc.h"
AnnaBridge	189:f392fc9709a3	49
AnnaBridge	189:f392fc9709a3	50	/** @addtogroup STM32L0xx_HAL_Driver
AnnaBridge	189:f392fc9709a3	51	* @{
AnnaBridge	189:f392fc9709a3	52	*/
AnnaBridge	189:f392fc9709a3	53
AnnaBridge	189:f392fc9709a3	54	/** @addtogroup ADC
AnnaBridge	189:f392fc9709a3	55	* @{
AnnaBridge	189:f392fc9709a3	56	*/
AnnaBridge	189:f392fc9709a3	57
AnnaBridge	189:f392fc9709a3	58	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	59	/** @defgroup ADC_Exported_Types ADC Exported Types
AnnaBridge	189:f392fc9709a3	60	* @{
AnnaBridge	189:f392fc9709a3	61	*/
AnnaBridge	189:f392fc9709a3	62
AnnaBridge	189:f392fc9709a3	63	/**
AnnaBridge	189:f392fc9709a3	64	* @brief ADC group regular oversampling structure definition
AnnaBridge	189:f392fc9709a3	65	*/
AnnaBridge	189:f392fc9709a3	66	typedef struct
AnnaBridge	189:f392fc9709a3	67	{
AnnaBridge	189:f392fc9709a3	68	uint32_t Ratio; /*!< Configures the oversampling ratio.
AnnaBridge	189:f392fc9709a3	69	This parameter can be a value of @ref ADC_Oversampling_Ratio */
AnnaBridge	189:f392fc9709a3	70
AnnaBridge	189:f392fc9709a3	71	uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
AnnaBridge	189:f392fc9709a3	72	This parameter can be a value of @ref ADC_Right_Bit_Shift */
AnnaBridge	189:f392fc9709a3	73
AnnaBridge	189:f392fc9709a3	74	uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
AnnaBridge	189:f392fc9709a3	75	This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
AnnaBridge	189:f392fc9709a3	76	}ADC_OversamplingTypeDef;
AnnaBridge	189:f392fc9709a3	77
AnnaBridge	189:f392fc9709a3	78	/**
AnnaBridge	189:f392fc9709a3	79	* @brief Structure definition of ADC instance and ADC group regular.
AnnaBridge	189:f392fc9709a3	80	* @note Parameters of this structure are shared within 2 scopes:
AnnaBridge	189:f392fc9709a3	81	* - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
AnnaBridge	189:f392fc9709a3	82	* ScanConvMode, EOCSelection, LowPowerAutoWait.
AnnaBridge	189:f392fc9709a3	83	* - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
AnnaBridge	189:f392fc9709a3	84	* ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
AnnaBridge	189:f392fc9709a3	85	* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
AnnaBridge	189:f392fc9709a3	86	* ADC state can be either:
AnnaBridge	189:f392fc9709a3	87	* - For all parameters: ADC disabled
AnnaBridge	189:f392fc9709a3	88	* - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular.
AnnaBridge	189:f392fc9709a3	89	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
AnnaBridge	189:f392fc9709a3	90	* without error reporting (as it can be the expected behavior in case of intended action to update another parameter
AnnaBridge	189:f392fc9709a3	91	* (which fulfills the ADC state condition) on the fly).
AnnaBridge	189:f392fc9709a3	92	*/
AnnaBridge	189:f392fc9709a3	93	typedef struct
AnnaBridge	189:f392fc9709a3	94	{
AnnaBridge	189:f392fc9709a3	95	uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator) and clock prescaler.
AnnaBridge	189:f392fc9709a3	96	This parameter can be a value of @ref ADC_ClockPrescaler.
AnnaBridge	189:f392fc9709a3	97	Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
AnnaBridge	189:f392fc9709a3	98	if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
AnnaBridge	189:f392fc9709a3	99	must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
AnnaBridge	189:f392fc9709a3	100	Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level.
AnnaBridge	189:f392fc9709a3	101	Note: This parameter can be modified only if the ADC is disabled. */
AnnaBridge	189:f392fc9709a3	102
AnnaBridge	189:f392fc9709a3	103	uint32_t Resolution; /*!< Configure the ADC resolution.
AnnaBridge	189:f392fc9709a3	104	This parameter can be a value of @ref ADC_Resolution */
AnnaBridge	189:f392fc9709a3	105
AnnaBridge	189:f392fc9709a3	106	uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
AnnaBridge	189:f392fc9709a3	107	Refer to reference manual for alignments formats versus resolutions.
AnnaBridge	189:f392fc9709a3	108	This parameter can be a value of @ref ADC_Data_align */
AnnaBridge	189:f392fc9709a3	109
AnnaBridge	189:f392fc9709a3	110	uint32_t ScanConvMode; /*!< Configure the sequencer of regular group.
AnnaBridge	189:f392fc9709a3	111	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
AnnaBridge	189:f392fc9709a3	112	Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
AnnaBridge	189:f392fc9709a3	113	If only 1 channel is set: Conversion is performed in single mode.
AnnaBridge	189:f392fc9709a3	114	If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
AnnaBridge	189:f392fc9709a3	115	Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0).
AnnaBridge	189:f392fc9709a3	116	This parameter can be a value of @ref ADC_Scan_mode */
AnnaBridge	189:f392fc9709a3	117
AnnaBridge	189:f392fc9709a3	118	uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
AnnaBridge	189:f392fc9709a3	119	This parameter can be a value of @ref ADC_EOCSelection. */
AnnaBridge	189:f392fc9709a3	120
AnnaBridge	189:f392fc9709a3	121	uint32_t LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
AnnaBridge	189:f392fc9709a3	122	conversion (for ADC group regular) has been retrieved by user software,
AnnaBridge	189:f392fc9709a3	123	using function HAL_ADC_GetValue().
AnnaBridge	189:f392fc9709a3	124	This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
AnnaBridge	189:f392fc9709a3	125	for low frequency applications.
AnnaBridge	189:f392fc9709a3	126	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	189:f392fc9709a3	127	Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
AnnaBridge	189:f392fc9709a3	128	to free the IRQ vector sequencer.
AnnaBridge	189:f392fc9709a3	129	Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
AnnaBridge	189:f392fc9709a3	130	use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */
AnnaBridge	189:f392fc9709a3	131
AnnaBridge	189:f392fc9709a3	132	uint32_t LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
AnnaBridge	189:f392fc9709a3	133	This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
AnnaBridge	189:f392fc9709a3	134	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	189:f392fc9709a3	135	Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
AnnaBridge	189:f392fc9709a3	136
AnnaBridge	189:f392fc9709a3	137	uint32_t ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
AnnaBridge	189:f392fc9709a3	138	after the first ADC conversion start trigger occurred (software start or external trigger).
AnnaBridge	189:f392fc9709a3	139	This parameter can be set to ENABLE or DISABLE. */
AnnaBridge	189:f392fc9709a3	140
AnnaBridge	189:f392fc9709a3	141	uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
AnnaBridge	189:f392fc9709a3	142	(main sequence subdivided in successive parts).
AnnaBridge	189:f392fc9709a3	143	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
AnnaBridge	189:f392fc9709a3	144	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
AnnaBridge	189:f392fc9709a3	145	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	189:f392fc9709a3	146	Note: On this STM32 serie, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */
AnnaBridge	189:f392fc9709a3	147
AnnaBridge	189:f392fc9709a3	148	uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
AnnaBridge	189:f392fc9709a3	149	If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
AnnaBridge	189:f392fc9709a3	150	This parameter can be a value of @ref ADC_regular_external_trigger_source.
AnnaBridge	189:f392fc9709a3	151	Caution: external trigger source is common to all ADC instances. */
AnnaBridge	189:f392fc9709a3	152
AnnaBridge	189:f392fc9709a3	153	uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
AnnaBridge	189:f392fc9709a3	154	If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
AnnaBridge	189:f392fc9709a3	155	This parameter can be a value of @ref ADC_regular_external_trigger_edge */
AnnaBridge	189:f392fc9709a3	156
AnnaBridge	189:f392fc9709a3	157	uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
AnnaBridge	189:f392fc9709a3	158	or in continuous mode (DMA transfer unlimited, whatever number of conversions).
AnnaBridge	189:f392fc9709a3	159	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	189:f392fc9709a3	160	Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
AnnaBridge	189:f392fc9709a3	161
AnnaBridge	189:f392fc9709a3	162	uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
AnnaBridge	189:f392fc9709a3	163	This parameter can be a value of @ref ADC_Overrun.
AnnaBridge	189:f392fc9709a3	164	Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
AnnaBridge	189:f392fc9709a3	165	end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
AnnaBridge	189:f392fc9709a3	166	HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
AnnaBridge	189:f392fc9709a3	167	Note: Error reporting with respect to the conversion mode:
AnnaBridge	189:f392fc9709a3	168	- Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
AnnaBridge	189:f392fc9709a3	169	overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
AnnaBridge	189:f392fc9709a3	170	- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
AnnaBridge	189:f392fc9709a3	171
AnnaBridge	189:f392fc9709a3	172	uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz,
AnnaBridge	189:f392fc9709a3	173	it is mandatory to first enable the Low Frequency Mode.
AnnaBridge	189:f392fc9709a3	174	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	189:f392fc9709a3	175	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	189:f392fc9709a3	176
AnnaBridge	189:f392fc9709a3	177
AnnaBridge	189:f392fc9709a3	178	uint32_t SamplingTime; /*!< The sample time common to all channels.
AnnaBridge	189:f392fc9709a3	179	Unit: ADC clock cycles
AnnaBridge	189:f392fc9709a3	180	This parameter can be a value of @ref ADC_sampling_times
AnnaBridge	189:f392fc9709a3	181	Note: This parameter can be modified only if there is no conversion ongoing. */
AnnaBridge	189:f392fc9709a3	182
AnnaBridge	189:f392fc9709a3	183	uint32_t OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
AnnaBridge	189:f392fc9709a3	184	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	189:f392fc9709a3	185	Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
AnnaBridge	189:f392fc9709a3	186
AnnaBridge	189:f392fc9709a3	187
AnnaBridge	189:f392fc9709a3	188	ADC_OversamplingTypeDef Oversample; /*!< Specify the Oversampling parameters
AnnaBridge	189:f392fc9709a3	189	Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
AnnaBridge	189:f392fc9709a3	190	}ADC_InitTypeDef;
AnnaBridge	189:f392fc9709a3	191
AnnaBridge	189:f392fc9709a3	192	/**
AnnaBridge	189:f392fc9709a3	193	* @brief Structure definition of ADC channel for regular group
AnnaBridge	189:f392fc9709a3	194	* @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
AnnaBridge	189:f392fc9709a3	195	* ADC state can be either:
AnnaBridge	189:f392fc9709a3	196	* - For all parameters: ADC disabled or enabled without conversion on going on regular group.
AnnaBridge	189:f392fc9709a3	197	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
AnnaBridge	189:f392fc9709a3	198	* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
AnnaBridge	189:f392fc9709a3	199	*/
AnnaBridge	189:f392fc9709a3	200	typedef struct
AnnaBridge	189:f392fc9709a3	201	{
AnnaBridge	189:f392fc9709a3	202	uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
AnnaBridge	189:f392fc9709a3	203	This parameter can be a value of @ref ADC_channels
AnnaBridge	189:f392fc9709a3	204	Note: Depending on devices, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
AnnaBridge	189:f392fc9709a3	205
AnnaBridge	189:f392fc9709a3	206	uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
AnnaBridge	189:f392fc9709a3	207	On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number
AnnaBridge	189:f392fc9709a3	208	(channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
AnnaBridge	189:f392fc9709a3	209	Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
AnnaBridge	189:f392fc9709a3	210	This parameter can be a value of @ref ADC_rank */
AnnaBridge	189:f392fc9709a3	211	}ADC_ChannelConfTypeDef;
AnnaBridge	189:f392fc9709a3	212
AnnaBridge	189:f392fc9709a3	213	/**
AnnaBridge	189:f392fc9709a3	214	* @brief Structure definition of ADC analog watchdog
AnnaBridge	189:f392fc9709a3	215	* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
AnnaBridge	189:f392fc9709a3	216	* ADC state can be either:
AnnaBridge	189:f392fc9709a3	217	* - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC group regular
AnnaBridge	189:f392fc9709a3	218	* - For parameters 'HighThreshold' and 'LowThreshold': ADC enabled with conversion on going on regular group (AWD thresholds can be modify on the fly while ADC conversion is on going)
AnnaBridge	189:f392fc9709a3	219	*/
AnnaBridge	189:f392fc9709a3	220	typedef struct
AnnaBridge	189:f392fc9709a3	221	{
AnnaBridge	189:f392fc9709a3	222	uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all channels.
AnnaBridge	189:f392fc9709a3	223	This parameter can be a value of @ref ADC_analog_watchdog_mode */
AnnaBridge	189:f392fc9709a3	224
AnnaBridge	189:f392fc9709a3	225	uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
AnnaBridge	189:f392fc9709a3	226	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
AnnaBridge	189:f392fc9709a3	227	This parameter can be a value of @ref ADC_channels */
AnnaBridge	189:f392fc9709a3	228
AnnaBridge	189:f392fc9709a3	229	uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
AnnaBridge	189:f392fc9709a3	230	This parameter can be set to ENABLE or DISABLE */
AnnaBridge	189:f392fc9709a3	231	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
AnnaBridge	189:f392fc9709a3	232	Depending of ADC resolution selected (12, 10, 8 or 6 bits),
AnnaBridge	189:f392fc9709a3	233	this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
AnnaBridge	189:f392fc9709a3	234
AnnaBridge	189:f392fc9709a3	235	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
AnnaBridge	189:f392fc9709a3	236	Depending of ADC resolution selected (12, 10, 8 or 6 bits),
AnnaBridge	189:f392fc9709a3	237	this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
AnnaBridge	189:f392fc9709a3	238	}ADC_AnalogWDGConfTypeDef;
AnnaBridge	189:f392fc9709a3	239
AnnaBridge	189:f392fc9709a3	240	/**
AnnaBridge	189:f392fc9709a3	241	* @brief HAL ADC state machine: ADC states definition (bitfields)
AnnaBridge	189:f392fc9709a3	242	* @note ADC state machine is managed by bitfields, state must be compared
AnnaBridge	189:f392fc9709a3	243	* with bit by bit.
AnnaBridge	189:f392fc9709a3	244	* For example:
AnnaBridge	189:f392fc9709a3	245	* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
AnnaBridge	189:f392fc9709a3	246	* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
AnnaBridge	189:f392fc9709a3	247	*/
AnnaBridge	189:f392fc9709a3	248	/* States of ADC global scope */
AnnaBridge	189:f392fc9709a3	249	#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /!< ADC not yet initialized or disabled /
AnnaBridge	189:f392fc9709a3	250	#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /!< ADC peripheral ready for use /
AnnaBridge	189:f392fc9709a3	251	#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /!< ADC is busy due to an internal process (initialization, calibration) /
AnnaBridge	189:f392fc9709a3	252	#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /!< TimeOut occurrence /
AnnaBridge	189:f392fc9709a3	253
AnnaBridge	189:f392fc9709a3	254	/* States of ADC errors */
AnnaBridge	189:f392fc9709a3	255	#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /!< Internal error occurrence /
AnnaBridge	189:f392fc9709a3	256	#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /!< Configuration error occurrence /
AnnaBridge	189:f392fc9709a3	257	#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /!< DMA error occurrence /
AnnaBridge	189:f392fc9709a3	258
AnnaBridge	189:f392fc9709a3	259	/* States of ADC group regular */
AnnaBridge	189:f392fc9709a3	260	#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
AnnaBridge	189:f392fc9709a3	261	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
AnnaBridge	189:f392fc9709a3	262	#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /!< Conversion data available on group regular /
AnnaBridge	189:f392fc9709a3	263	#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /!< Overrun occurrence /
AnnaBridge	189:f392fc9709a3	264	#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /!< Not available on this STM32 serie: End Of Sampling flag raised /
AnnaBridge	189:f392fc9709a3	265
AnnaBridge	189:f392fc9709a3	266	/* States of ADC group injected */
AnnaBridge	189:f392fc9709a3	267	#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on this STM32 serie: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
AnnaBridge	189:f392fc9709a3	268	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
AnnaBridge	189:f392fc9709a3	269	#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /!< Not available on this STM32 serie: Conversion data available on group injected /
AnnaBridge	189:f392fc9709a3	270	#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /!< Not available on this STM32 serie: Injected queue overflow occurrence /
AnnaBridge	189:f392fc9709a3	271
AnnaBridge	189:f392fc9709a3	272	/* States of ADC analog watchdogs */
AnnaBridge	189:f392fc9709a3	273	#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /!< Out-of-window occurrence of ADC analog watchdog 1 /
AnnaBridge	189:f392fc9709a3	274	#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 2 /
AnnaBridge	189:f392fc9709a3	275	#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 3 /
AnnaBridge	189:f392fc9709a3	276
AnnaBridge	189:f392fc9709a3	277	/* States of ADC multi-mode */
AnnaBridge	189:f392fc9709a3	278	#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /!< Not available on this STM32 serie: ADC in multimode slave state, controlled by another ADC master (when feature available) /
AnnaBridge	189:f392fc9709a3	279
AnnaBridge	189:f392fc9709a3	280
AnnaBridge	189:f392fc9709a3	281
AnnaBridge	189:f392fc9709a3	282	/**
AnnaBridge	189:f392fc9709a3	283	* @brief ADC handle Structure definition
AnnaBridge	189:f392fc9709a3	284	*/
AnnaBridge	189:f392fc9709a3	285	typedef struct
AnnaBridge	189:f392fc9709a3	286	{
AnnaBridge	189:f392fc9709a3	287	ADC_TypeDef Instance; /!< Register base address */
AnnaBridge	189:f392fc9709a3	288
AnnaBridge	189:f392fc9709a3	289	ADC_InitTypeDef Init; /!< ADC required parameters /
AnnaBridge	189:f392fc9709a3	290
AnnaBridge	189:f392fc9709a3	291	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
AnnaBridge	189:f392fc9709a3	292
AnnaBridge	189:f392fc9709a3	293	HAL_LockTypeDef Lock; /!< ADC locking object /
AnnaBridge	189:f392fc9709a3	294
AnnaBridge	189:f392fc9709a3	295	__IO uint32_t State; /!< ADC communication state (bitmap of ADC states) /
AnnaBridge	189:f392fc9709a3	296
AnnaBridge	189:f392fc9709a3	297	__IO uint32_t ErrorCode; /!< ADC Error code /
AnnaBridge	189:f392fc9709a3	298	}ADC_HandleTypeDef;
AnnaBridge	189:f392fc9709a3	299	/**
AnnaBridge	189:f392fc9709a3	300	* @}
AnnaBridge	189:f392fc9709a3	301	*/
AnnaBridge	189:f392fc9709a3	302
AnnaBridge	189:f392fc9709a3	303
AnnaBridge	189:f392fc9709a3	304	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	305
AnnaBridge	189:f392fc9709a3	306	/** @defgroup ADC_Exported_Constants ADC Exported Constants
AnnaBridge	189:f392fc9709a3	307	* @{
AnnaBridge	189:f392fc9709a3	308	*/
AnnaBridge	189:f392fc9709a3	309
AnnaBridge	189:f392fc9709a3	310	/** @defgroup ADC_Error_Code ADC Error Code
AnnaBridge	189:f392fc9709a3	311	* @{
AnnaBridge	189:f392fc9709a3	312	*/
AnnaBridge	189:f392fc9709a3	313	#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /!< No error /
AnnaBridge	189:f392fc9709a3	314	#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error (problem of clocking,
AnnaBridge	189:f392fc9709a3	315	enable/disable, erroneous state, ...) */
AnnaBridge	189:f392fc9709a3	316	#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /!< Overrun error /
AnnaBridge	189:f392fc9709a3	317	#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /!< DMA transfer error /
AnnaBridge	189:f392fc9709a3	318	/**
AnnaBridge	189:f392fc9709a3	319	* @}
AnnaBridge	189:f392fc9709a3	320	*/
AnnaBridge	189:f392fc9709a3	321
AnnaBridge	189:f392fc9709a3	322	/** @defgroup ADC_TimeOut_Values ADC TimeOut Values
AnnaBridge	189:f392fc9709a3	323	* @{
AnnaBridge	189:f392fc9709a3	324	*/
AnnaBridge	189:f392fc9709a3	325
AnnaBridge	189:f392fc9709a3	326	/* Fixed timeout values for ADC calibration, enable settling time, disable */
AnnaBridge	189:f392fc9709a3	327	/* settling time. */
AnnaBridge	189:f392fc9709a3	328	/* Values defined to be higher than worst cases: low clocks freq, */
AnnaBridge	189:f392fc9709a3	329	/* maximum prescalers. */
AnnaBridge	189:f392fc9709a3	330	/* Unit: ms */
AnnaBridge	189:f392fc9709a3	331	#define ADC_ENABLE_TIMEOUT 10U
AnnaBridge	189:f392fc9709a3	332	#define ADC_DISABLE_TIMEOUT 10U
AnnaBridge	189:f392fc9709a3	333	#define ADC_STOP_CONVERSION_TIMEOUT 10U
AnnaBridge	189:f392fc9709a3	334
AnnaBridge	189:f392fc9709a3	335	/* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */
AnnaBridge	189:f392fc9709a3	336	/* the minimum number of CPU cycles to fulfill this delay */
AnnaBridge	189:f392fc9709a3	337	#define ADC_DELAY_10US_MIN_CPU_CYCLES 1800U
AnnaBridge	189:f392fc9709a3	338	/**
AnnaBridge	189:f392fc9709a3	339	* @}
AnnaBridge	189:f392fc9709a3	340	*/
AnnaBridge	189:f392fc9709a3	341
AnnaBridge	189:f392fc9709a3	342	/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
AnnaBridge	189:f392fc9709a3	343	* @{
AnnaBridge	189:f392fc9709a3	344	*/
AnnaBridge	189:f392fc9709a3	345	#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /!< ADC Asynchronous clock mode divided by 1 /
AnnaBridge	189:f392fc9709a3	346	#define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	189:f392fc9709a3	347	#define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	189:f392fc9709a3	348	#define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	189:f392fc9709a3	349	#define ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	189:f392fc9709a3	350	#define ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	189:f392fc9709a3	351	#define ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	189:f392fc9709a3	352	#define ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	189:f392fc9709a3	353	#define ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	189:f392fc9709a3	354	#define ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	189:f392fc9709a3	355	#define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	189:f392fc9709a3	356	#define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	189:f392fc9709a3	357
AnnaBridge	189:f392fc9709a3	358	#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 1
AnnaBridge	189:f392fc9709a3	359	This configuration must be enabled only if PCLK has a 50%
AnnaBridge	189:f392fc9709a3	360	duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
AnnaBridge	189:f392fc9709a3	361	must by 50% duty cycle)*/
AnnaBridge	189:f392fc9709a3	362	#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /!< Synchronous clock mode divided by 2 /
AnnaBridge	189:f392fc9709a3	363	#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /!< Synchronous clock mode divided by 4 /
AnnaBridge	189:f392fc9709a3	364
AnnaBridge	189:f392fc9709a3	365	/**
AnnaBridge	189:f392fc9709a3	366	* @}
AnnaBridge	189:f392fc9709a3	367	*/
AnnaBridge	189:f392fc9709a3	368
AnnaBridge	189:f392fc9709a3	369	/** @defgroup ADC_Resolution ADC Resolution
AnnaBridge	189:f392fc9709a3	370	* @{
AnnaBridge	189:f392fc9709a3	371	*/
AnnaBridge	189:f392fc9709a3	372	#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /!< ADC 12-bit resolution /
AnnaBridge	189:f392fc9709a3	373	#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /!< ADC 10-bit resolution /
AnnaBridge	189:f392fc9709a3	374	#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /!< ADC 8-bit resolution /
AnnaBridge	189:f392fc9709a3	375	#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /!< ADC 6-bit resolution /
AnnaBridge	189:f392fc9709a3	376	/**
AnnaBridge	189:f392fc9709a3	377	* @}
AnnaBridge	189:f392fc9709a3	378	*/
AnnaBridge	189:f392fc9709a3	379
AnnaBridge	189:f392fc9709a3	380	/** @defgroup ADC_Data_align ADC conversion data alignment
AnnaBridge	189:f392fc9709a3	381	* @{
AnnaBridge	189:f392fc9709a3	382	*/
AnnaBridge	189:f392fc9709a3	383	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	384	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
AnnaBridge	189:f392fc9709a3	385	/**
AnnaBridge	189:f392fc9709a3	386	* @}
AnnaBridge	189:f392fc9709a3	387	*/
AnnaBridge	189:f392fc9709a3	388
AnnaBridge	189:f392fc9709a3	389	/** @defgroup ADC_regular_external_trigger_edge ADC External Trigger Source Edge for Regular Group
AnnaBridge	189:f392fc9709a3	390	* @{
AnnaBridge	189:f392fc9709a3	391	*/
AnnaBridge	189:f392fc9709a3	392	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	393	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
AnnaBridge	189:f392fc9709a3	394	#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
AnnaBridge	189:f392fc9709a3	395	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
AnnaBridge	189:f392fc9709a3	396	/**
AnnaBridge	189:f392fc9709a3	397	* @}
AnnaBridge	189:f392fc9709a3	398	*/
AnnaBridge	189:f392fc9709a3	399
AnnaBridge	189:f392fc9709a3	400	/** @defgroup ADC_EOCSelection ADC EOC Selection
AnnaBridge	189:f392fc9709a3	401	* @{
AnnaBridge	189:f392fc9709a3	402	*/
AnnaBridge	189:f392fc9709a3	403	#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
AnnaBridge	189:f392fc9709a3	404	#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
AnnaBridge	189:f392fc9709a3	405	#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC \| ADC_ISR_EOS)) /!< reserved for future use /
AnnaBridge	189:f392fc9709a3	406	/**
AnnaBridge	189:f392fc9709a3	407	* @}
AnnaBridge	189:f392fc9709a3	408	*/
AnnaBridge	189:f392fc9709a3	409
AnnaBridge	189:f392fc9709a3	410	/** @defgroup ADC_Overrun ADC Overrun
AnnaBridge	189:f392fc9709a3	411	* @{
AnnaBridge	189:f392fc9709a3	412	*/
AnnaBridge	189:f392fc9709a3	413	#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	414	#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
AnnaBridge	189:f392fc9709a3	415	/**
AnnaBridge	189:f392fc9709a3	416	* @}
AnnaBridge	189:f392fc9709a3	417	*/
AnnaBridge	189:f392fc9709a3	418
AnnaBridge	189:f392fc9709a3	419
AnnaBridge	189:f392fc9709a3	420	/** @defgroup ADC_rank ADC rank
AnnaBridge	189:f392fc9709a3	421	* @{
AnnaBridge	189:f392fc9709a3	422	*/
AnnaBridge	189:f392fc9709a3	423	#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000U) /!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) /
AnnaBridge	189:f392fc9709a3	424	#define ADC_RANK_NONE ((uint32_t)0x00001001U) /!< Disable the selected rank (selected channel) from sequencer /
AnnaBridge	189:f392fc9709a3	425	/**
AnnaBridge	189:f392fc9709a3	426	* @}
AnnaBridge	189:f392fc9709a3	427	*/
AnnaBridge	189:f392fc9709a3	428
AnnaBridge	189:f392fc9709a3	429
AnnaBridge	189:f392fc9709a3	430	/** @defgroup ADC_channels ADC_Channels
AnnaBridge	189:f392fc9709a3	431	* @{
AnnaBridge	189:f392fc9709a3	432	*/
AnnaBridge	189:f392fc9709a3	433	#define ADC_CHANNEL_0 ((uint32_t)(ADC_CHSELR_CHSEL0))
AnnaBridge	189:f392fc9709a3	434	#define ADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) \| ADC_CFGR1_AWDCH_0)
AnnaBridge	189:f392fc9709a3	435	#define ADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) \| ADC_CFGR1_AWDCH_1)
AnnaBridge	189:f392fc9709a3	436	#define ADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)\| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
AnnaBridge	189:f392fc9709a3	437	#define ADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)\| ADC_CFGR1_AWDCH_2)
AnnaBridge	189:f392fc9709a3	438	#define ADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_0)
AnnaBridge	189:f392fc9709a3	439	#define ADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1)
AnnaBridge	189:f392fc9709a3	440	#define ADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
AnnaBridge	189:f392fc9709a3	441	#define ADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)\| ADC_CFGR1_AWDCH_3)
AnnaBridge	189:f392fc9709a3	442	#define ADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_0)
AnnaBridge	189:f392fc9709a3	443	#define ADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_1)
AnnaBridge	189:f392fc9709a3	444	#define ADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_1\| ADC_CFGR1_AWDCH_0)
AnnaBridge	189:f392fc9709a3	445	#define ADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2)
AnnaBridge	189:f392fc9709a3	446	#define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_0)
AnnaBridge	189:f392fc9709a3	447	#define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1)
AnnaBridge	189:f392fc9709a3	448	#define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1\| ADC_CFGR1_AWDCH_0)
AnnaBridge	189:f392fc9709a3	449	#if defined (STM32L053xx) \|\| defined (STM32L063xx) \|\| defined (STM32L073xx) \|\| defined (STM32L083xx)
AnnaBridge	189:f392fc9709a3	450	#define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)\| ADC_CFGR1_AWDCH_4)
AnnaBridge	189:f392fc9709a3	451	#endif
AnnaBridge	189:f392fc9709a3	452	#define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)\| ADC_CFGR1_AWDCH_4\| ADC_CFGR1_AWDCH_0)
AnnaBridge	189:f392fc9709a3	453	#define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)\| ADC_CFGR1_AWDCH_4\| ADC_CFGR1_AWDCH_1)
AnnaBridge	189:f392fc9709a3	454
AnnaBridge	189:f392fc9709a3	455	/* Internal channels */
AnnaBridge	189:f392fc9709a3	456	#if defined (STM32L053xx) \|\| defined (STM32L063xx) \|\| defined (STM32L073xx) \|\| defined (STM32L083xx)
AnnaBridge	189:f392fc9709a3	457	#define ADC_CHANNEL_VLCD ADC_CHANNEL_16
AnnaBridge	189:f392fc9709a3	458	#endif
AnnaBridge	189:f392fc9709a3	459	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
AnnaBridge	189:f392fc9709a3	460	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
AnnaBridge	189:f392fc9709a3	461	/**
AnnaBridge	189:f392fc9709a3	462	* @}
AnnaBridge	189:f392fc9709a3	463	*/
AnnaBridge	189:f392fc9709a3	464
AnnaBridge	189:f392fc9709a3	465	/** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks
AnnaBridge	189:f392fc9709a3	466	* @{
AnnaBridge	189:f392fc9709a3	467	*/
AnnaBridge	189:f392fc9709a3	468	#define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFFU)
AnnaBridge	189:f392fc9709a3	469	#define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000U)
AnnaBridge	189:f392fc9709a3	470	/**
AnnaBridge	189:f392fc9709a3	471	* @}
AnnaBridge	189:f392fc9709a3	472	*/
AnnaBridge	189:f392fc9709a3	473
AnnaBridge	189:f392fc9709a3	474	/** @defgroup ADC_sampling_times ADC Sampling Cycles
AnnaBridge	189:f392fc9709a3	475	* @{
AnnaBridge	189:f392fc9709a3	476	*/
AnnaBridge	189:f392fc9709a3	477	#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000U) /!< ADC sampling time 1.5 cycle /
AnnaBridge	189:f392fc9709a3	478	#define ADC_SAMPLETIME_3CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /!< ADC sampling time 3.5 CYCLES /
AnnaBridge	189:f392fc9709a3	479	#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /!< ADC sampling time 7.5 CYCLES /
AnnaBridge	189:f392fc9709a3	480	#define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 \| ADC_SMPR_SMPR_0)) /!< ADC sampling time 12.5 CYCLES /
AnnaBridge	189:f392fc9709a3	481	#define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /!< ADC sampling time 19.5 CYCLES /
AnnaBridge	189:f392fc9709a3	482	#define ADC_SAMPLETIME_39CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 \| ADC_SMPR_SMPR_0)) /!< ADC sampling time 39.5 CYCLES /
AnnaBridge	189:f392fc9709a3	483	#define ADC_SAMPLETIME_79CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 \| ADC_SMPR_SMPR_1)) /!< ADC sampling time 79.5 CYCLES /
AnnaBridge	189:f392fc9709a3	484	#define ADC_SAMPLETIME_160CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /!< ADC sampling time 160.5 CYCLES /
AnnaBridge	189:f392fc9709a3	485	/**
AnnaBridge	189:f392fc9709a3	486	* @}
AnnaBridge	189:f392fc9709a3	487	*/
AnnaBridge	189:f392fc9709a3	488
AnnaBridge	189:f392fc9709a3	489	/** @defgroup ADC_Scan_mode ADC Scan mode
AnnaBridge	189:f392fc9709a3	490	* @{
AnnaBridge	189:f392fc9709a3	491	*/
AnnaBridge	189:f392fc9709a3	492	/* Note: Scan mode values must be compatible with other STM32 devices having */
AnnaBridge	189:f392fc9709a3	493	/* a configurable sequencer. */
AnnaBridge	189:f392fc9709a3	494	/* Scan direction setting values are defined by taking in account */
AnnaBridge	189:f392fc9709a3	495	/* already defined values for other STM32 devices: */
AnnaBridge	189:f392fc9709a3	496	/* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */
AnnaBridge	189:f392fc9709a3	497	/* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */
AnnaBridge	189:f392fc9709a3	498	/* Scan direction forward is considered as default setting equivalent */
AnnaBridge	189:f392fc9709a3	499	/* to scan enable. */
AnnaBridge	189:f392fc9709a3	500	/* Scan direction backward is considered as additional setting. */
AnnaBridge	189:f392fc9709a3	501	/* In case of migration from another STM32 device, the user will be */
AnnaBridge	189:f392fc9709a3	502	/* warned of change of setting choices with assert check. */
AnnaBridge	189:f392fc9709a3	503	#define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001U) /!< Scan direction forward: from channel 0 to channel 18 /
AnnaBridge	189:f392fc9709a3	504	#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002U) /!< Scan direction backward: from channel 18 to channel 0 /
AnnaBridge	189:f392fc9709a3	505
AnnaBridge	189:f392fc9709a3	506	#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
AnnaBridge	189:f392fc9709a3	507	/**
AnnaBridge	189:f392fc9709a3	508	* @}
AnnaBridge	189:f392fc9709a3	509	*/
AnnaBridge	189:f392fc9709a3	510
AnnaBridge	189:f392fc9709a3	511	/** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio
AnnaBridge	189:f392fc9709a3	512	* @{
AnnaBridge	189:f392fc9709a3	513	*/
AnnaBridge	189:f392fc9709a3	514
AnnaBridge	189:f392fc9709a3	515	#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000U) /!< ADC Oversampling ratio 2x /
AnnaBridge	189:f392fc9709a3	516	#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004U) /!< ADC Oversampling ratio 4x /
AnnaBridge	189:f392fc9709a3	517	#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008U) /!< ADC Oversampling ratio 8x /
AnnaBridge	189:f392fc9709a3	518	#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000CU) /!< ADC Oversampling ratio 16x /
AnnaBridge	189:f392fc9709a3	519	#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010U) /!< ADC Oversampling ratio 32x /
AnnaBridge	189:f392fc9709a3	520	#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014U) /!< ADC Oversampling ratio 64x /
AnnaBridge	189:f392fc9709a3	521	#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018U) /!< ADC Oversampling ratio 128x /
AnnaBridge	189:f392fc9709a3	522	#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001CU) /!< ADC Oversampling ratio 256x /
AnnaBridge	189:f392fc9709a3	523	/**
AnnaBridge	189:f392fc9709a3	524	* @}
AnnaBridge	189:f392fc9709a3	525	*/
AnnaBridge	189:f392fc9709a3	526
AnnaBridge	189:f392fc9709a3	527	/** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift
AnnaBridge	189:f392fc9709a3	528	* @{
AnnaBridge	189:f392fc9709a3	529	*/
AnnaBridge	189:f392fc9709a3	530	#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000U) /!< ADC No bit shift for oversampling /
AnnaBridge	189:f392fc9709a3	531	#define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020U) /!< ADC 1 bit shift for oversampling /
AnnaBridge	189:f392fc9709a3	532	#define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040U) /!< ADC 2 bits shift for oversampling /
AnnaBridge	189:f392fc9709a3	533	#define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060U) /!< ADC 3 bits shift for oversampling /
AnnaBridge	189:f392fc9709a3	534	#define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080U) /!< ADC 4 bits shift for oversampling /
AnnaBridge	189:f392fc9709a3	535	#define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0U) /!< ADC 5 bits shift for oversampling /
AnnaBridge	189:f392fc9709a3	536	#define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0U) /!< ADC 6 bits shift for oversampling /
AnnaBridge	189:f392fc9709a3	537	#define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0U) /!< ADC 7 bits shift for oversampling /
AnnaBridge	189:f392fc9709a3	538	#define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100U) /!< ADC 8 bits shift for oversampling /
AnnaBridge	189:f392fc9709a3	539	/**
AnnaBridge	189:f392fc9709a3	540	* @}
AnnaBridge	189:f392fc9709a3	541	*/
AnnaBridge	189:f392fc9709a3	542
AnnaBridge	189:f392fc9709a3	543	/** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode
AnnaBridge	189:f392fc9709a3	544	* @{
AnnaBridge	189:f392fc9709a3	545	*/
AnnaBridge	189:f392fc9709a3	546	#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000U) /!< ADC No bit shift for oversampling /
AnnaBridge	189:f392fc9709a3	547	#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200U) /!< ADC No bit shift for oversampling /
AnnaBridge	189:f392fc9709a3	548	/**
AnnaBridge	189:f392fc9709a3	549	* @}
AnnaBridge	189:f392fc9709a3	550	*/
AnnaBridge	189:f392fc9709a3	551
AnnaBridge	189:f392fc9709a3	552	/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
AnnaBridge	189:f392fc9709a3	553	* @{
AnnaBridge	189:f392fc9709a3	554	*/
AnnaBridge	189:f392fc9709a3	555	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000U)
AnnaBridge	189:f392fc9709a3	556	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL \| ADC_CFGR1_AWDEN))
AnnaBridge	189:f392fc9709a3	557	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
AnnaBridge	189:f392fc9709a3	558	/**
AnnaBridge	189:f392fc9709a3	559	* @}
AnnaBridge	189:f392fc9709a3	560	*/
AnnaBridge	189:f392fc9709a3	561
AnnaBridge	189:f392fc9709a3	562	/** @defgroup ADC_conversion_type ADC Conversion Group
AnnaBridge	189:f392fc9709a3	563	* @{
AnnaBridge	189:f392fc9709a3	564	*/
AnnaBridge	189:f392fc9709a3	565	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_EOS))
AnnaBridge	189:f392fc9709a3	566	/**
AnnaBridge	189:f392fc9709a3	567	* @}
AnnaBridge	189:f392fc9709a3	568	*/
AnnaBridge	189:f392fc9709a3	569
AnnaBridge	189:f392fc9709a3	570	/** @defgroup ADC_Event_type ADC Event
AnnaBridge	189:f392fc9709a3	571	* @{
AnnaBridge	189:f392fc9709a3	572	*/
AnnaBridge	189:f392fc9709a3	573	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
AnnaBridge	189:f392fc9709a3	574	#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
AnnaBridge	189:f392fc9709a3	575	/**
AnnaBridge	189:f392fc9709a3	576	* @}
AnnaBridge	189:f392fc9709a3	577	*/
AnnaBridge	189:f392fc9709a3	578
AnnaBridge	189:f392fc9709a3	579	/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
AnnaBridge	189:f392fc9709a3	580	* @{
AnnaBridge	189:f392fc9709a3	581	*/
AnnaBridge	189:f392fc9709a3	582	#define ADC_IT_RDY ADC_IER_ADRDYIE /!< ADC Ready (ADRDY) interrupt source /
AnnaBridge	189:f392fc9709a3	583	#define ADC_IT_EOSMP ADC_IER_EOSMPIE /!< ADC End of Sampling interrupt source /
AnnaBridge	189:f392fc9709a3	584	#define ADC_IT_EOC ADC_IER_EOCIE /!< ADC End of Regular Conversion interrupt source /
AnnaBridge	189:f392fc9709a3	585	#define ADC_IT_EOS ADC_IER_EOSEQIE /!< ADC End of Regular sequence of Conversions interrupt source /
AnnaBridge	189:f392fc9709a3	586	#define ADC_IT_OVR ADC_IER_OVRIE /!< ADC overrun interrupt source /
AnnaBridge	189:f392fc9709a3	587	#define ADC_IT_AWD ADC_IER_AWDIE /!< ADC Analog watchdog 1 interrupt source /
AnnaBridge	189:f392fc9709a3	588	#define ADC_IT_EOCAL ADC_IER_EOCALIE /!< ADC End of Calibration interrupt source /
AnnaBridge	189:f392fc9709a3	589	/**
AnnaBridge	189:f392fc9709a3	590	* @}
AnnaBridge	189:f392fc9709a3	591	*/
AnnaBridge	189:f392fc9709a3	592
AnnaBridge	189:f392fc9709a3	593	/** @defgroup ADC_flags_definition ADC flags definition
AnnaBridge	189:f392fc9709a3	594	* @{
AnnaBridge	189:f392fc9709a3	595	*/
AnnaBridge	189:f392fc9709a3	596	#define ADC_FLAG_RDY ADC_ISR_ADRDY /!< ADC Ready flag /
AnnaBridge	189:f392fc9709a3	597	#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /!< ADC End of Sampling flag /
AnnaBridge	189:f392fc9709a3	598	#define ADC_FLAG_EOC ADC_ISR_EOC /!< ADC End of Regular Conversion flag /
AnnaBridge	189:f392fc9709a3	599	#define ADC_FLAG_EOS ADC_ISR_EOSEQ /!< ADC End of Regular sequence of Conversions flag /
AnnaBridge	189:f392fc9709a3	600	#define ADC_FLAG_OVR ADC_ISR_OVR /!< ADC overrun flag /
AnnaBridge	189:f392fc9709a3	601	#define ADC_FLAG_AWD ADC_ISR_AWD /!< ADC Analog watchdog flag /
AnnaBridge	189:f392fc9709a3	602	#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /!< ADC Enf Of Calibration flag /
AnnaBridge	189:f392fc9709a3	603
AnnaBridge	189:f392fc9709a3	604
AnnaBridge	189:f392fc9709a3	605	#define ADC_FLAG_ALL (ADC_FLAG_RDY \| ADC_FLAG_EOSMP \| ADC_FLAG_EOC \| ADC_FLAG_EOS \| \
AnnaBridge	189:f392fc9709a3	606	ADC_FLAG_OVR \| ADC_FLAG_AWD \| ADC_FLAG_EOCAL)
AnnaBridge	189:f392fc9709a3	607	/**
AnnaBridge	189:f392fc9709a3	608	* @}
AnnaBridge	189:f392fc9709a3	609	*/
AnnaBridge	189:f392fc9709a3	610
AnnaBridge	189:f392fc9709a3	611	/**
AnnaBridge	189:f392fc9709a3	612	* @}
AnnaBridge	189:f392fc9709a3	613	*/
AnnaBridge	189:f392fc9709a3	614
AnnaBridge	189:f392fc9709a3	615
AnnaBridge	189:f392fc9709a3	616	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	617
AnnaBridge	189:f392fc9709a3	618	/** @defgroup ADC_Exported_Macros ADC Exported Macros
AnnaBridge	189:f392fc9709a3	619	* @{
AnnaBridge	189:f392fc9709a3	620	*/
AnnaBridge	189:f392fc9709a3	621	/** @brief Reset ADC handle state
AnnaBridge	189:f392fc9709a3	622	* @param __HANDLE__: ADC handle
AnnaBridge	189:f392fc9709a3	623	* @retval None
AnnaBridge	189:f392fc9709a3	624	*/
AnnaBridge	189:f392fc9709a3	625	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
AnnaBridge	189:f392fc9709a3	626
AnnaBridge	189:f392fc9709a3	627	/**
AnnaBridge	189:f392fc9709a3	628	* @brief Enable the ADC peripheral
AnnaBridge	189:f392fc9709a3	629	* @param __HANDLE__: ADC handle
AnnaBridge	189:f392fc9709a3	630	* @retval None
AnnaBridge	189:f392fc9709a3	631	*/
AnnaBridge	189:f392fc9709a3	632	#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= ADC_CR_ADEN)
AnnaBridge	189:f392fc9709a3	633
AnnaBridge	189:f392fc9709a3	634	/**
AnnaBridge	189:f392fc9709a3	635	* @brief Verification of hardware constraints before ADC can be enabled
AnnaBridge	189:f392fc9709a3	636	* @param __HANDLE__: ADC handle
AnnaBridge	189:f392fc9709a3	637	* @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
AnnaBridge	189:f392fc9709a3	638	*/
AnnaBridge	189:f392fc9709a3	639	#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	640	(( ( ((__HANDLE__)->Instance->CR) & \
AnnaBridge	189:f392fc9709a3	641	(ADC_CR_ADCAL \| ADC_CR_ADSTP \| ADC_CR_ADSTART \| \
AnnaBridge	189:f392fc9709a3	642	ADC_CR_ADDIS \| ADC_CR_ADEN ) \
AnnaBridge	189:f392fc9709a3	643	) == RESET \
AnnaBridge	189:f392fc9709a3	644	) ? SET : RESET)
AnnaBridge	189:f392fc9709a3	645
AnnaBridge	189:f392fc9709a3	646	/**
AnnaBridge	189:f392fc9709a3	647	* @brief Disable the ADC peripheral
AnnaBridge	189:f392fc9709a3	648	* @param __HANDLE__: ADC handle
AnnaBridge	189:f392fc9709a3	649	* @retval None
AnnaBridge	189:f392fc9709a3	650	*/
AnnaBridge	189:f392fc9709a3	651	#define __HAL_ADC_DISABLE(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	652	do{ \
AnnaBridge	189:f392fc9709a3	653	(__HANDLE__)->Instance->CR \|= ADC_CR_ADDIS; \
AnnaBridge	189:f392fc9709a3	654	__HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP \| ADC_FLAG_RDY)); \
AnnaBridge	189:f392fc9709a3	655	} while(0)
AnnaBridge	189:f392fc9709a3	656
AnnaBridge	189:f392fc9709a3	657	/**
AnnaBridge	189:f392fc9709a3	658	* @brief Verification of hardware constraints before ADC can be disabled
AnnaBridge	189:f392fc9709a3	659	* @param __HANDLE__: ADC handle
AnnaBridge	189:f392fc9709a3	660	* @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
AnnaBridge	189:f392fc9709a3	661	*/
AnnaBridge	189:f392fc9709a3	662	#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	663	(( ( ((__HANDLE__)->Instance->CR) & \
AnnaBridge	189:f392fc9709a3	664	(ADC_CR_ADSTART \| ADC_CR_ADEN)) == ADC_CR_ADEN \
AnnaBridge	189:f392fc9709a3	665	) ? SET : RESET)
AnnaBridge	189:f392fc9709a3	666
AnnaBridge	189:f392fc9709a3	667	/**
AnnaBridge	189:f392fc9709a3	668	* @brief Verification of ADC state: enabled or disabled
AnnaBridge	189:f392fc9709a3	669	* @param __HANDLE__: ADC handle
AnnaBridge	189:f392fc9709a3	670	* @retval SET (ADC enabled) or RESET (ADC disabled)
AnnaBridge	189:f392fc9709a3	671	*/
AnnaBridge	189:f392fc9709a3	672	#define ADC_IS_ENABLE(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	673	(( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN \| ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
AnnaBridge	189:f392fc9709a3	674	((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
AnnaBridge	189:f392fc9709a3	675	) ? SET : RESET)
AnnaBridge	189:f392fc9709a3	676
AnnaBridge	189:f392fc9709a3	677	/**
AnnaBridge	189:f392fc9709a3	678	* @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution.
AnnaBridge	189:f392fc9709a3	679	* @param __HANDLE__: ADC handle
AnnaBridge	189:f392fc9709a3	680	* @retval None
AnnaBridge	189:f392fc9709a3	681	*/
AnnaBridge	189:f392fc9709a3	682	#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
AnnaBridge	189:f392fc9709a3	683	/**
AnnaBridge	189:f392fc9709a3	684	* @brief Test if conversion trigger of regular group is software start
AnnaBridge	189:f392fc9709a3	685	* or external trigger.
AnnaBridge	189:f392fc9709a3	686	* @param __HANDLE__: ADC handle
AnnaBridge	189:f392fc9709a3	687	* @retval SET (software start) or RESET (external trigger)
AnnaBridge	189:f392fc9709a3	688	*/
AnnaBridge	189:f392fc9709a3	689	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	690	(((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
AnnaBridge	189:f392fc9709a3	691
AnnaBridge	189:f392fc9709a3	692
AnnaBridge	189:f392fc9709a3	693
AnnaBridge	189:f392fc9709a3	694	/**
AnnaBridge	189:f392fc9709a3	695	* @brief Check if no conversion on going on regular group
AnnaBridge	189:f392fc9709a3	696	* @param __HANDLE__: ADC handle
AnnaBridge	189:f392fc9709a3	697	* @retval SET (conversion is on going) or RESET (no conversion is on going)
AnnaBridge	189:f392fc9709a3	698	*/
AnnaBridge	189:f392fc9709a3	699	#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	700	(( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
AnnaBridge	189:f392fc9709a3	701	) ? RESET : SET)
AnnaBridge	189:f392fc9709a3	702
AnnaBridge	189:f392fc9709a3	703	/**
AnnaBridge	189:f392fc9709a3	704	* @brief Enable ADC continuous conversion mode.
AnnaBridge	189:f392fc9709a3	705	* @param _CONTINUOUS_MODE_: Continuous mode.
AnnaBridge	189:f392fc9709a3	706	* @retval None
AnnaBridge	189:f392fc9709a3	707	*/
AnnaBridge	189:f392fc9709a3	708	#define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
AnnaBridge	189:f392fc9709a3	709
AnnaBridge	189:f392fc9709a3	710	/**
AnnaBridge	189:f392fc9709a3	711	* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
AnnaBridge	189:f392fc9709a3	712	* @param _SCAN_MODE_: Scan conversion mode.
AnnaBridge	189:f392fc9709a3	713	* @retval None
AnnaBridge	189:f392fc9709a3	714	*/
AnnaBridge	189:f392fc9709a3	715	#define ADC_SCANDIR(_SCAN_MODE_) \
AnnaBridge	189:f392fc9709a3	716	( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \
AnnaBridge	189:f392fc9709a3	717	)? (ADC_CFGR1_SCANDIR) : (0x00000000U) \
AnnaBridge	189:f392fc9709a3	718	)
AnnaBridge	189:f392fc9709a3	719
AnnaBridge	189:f392fc9709a3	720	/**
AnnaBridge	189:f392fc9709a3	721	* @brief Configures the number of discontinuous conversions for the regular group channels.
AnnaBridge	189:f392fc9709a3	722	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
AnnaBridge	189:f392fc9709a3	723	* @retval None
AnnaBridge	189:f392fc9709a3	724	*/
AnnaBridge	189:f392fc9709a3	725	#define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)
AnnaBridge	189:f392fc9709a3	726
AnnaBridge	189:f392fc9709a3	727	/**
AnnaBridge	189:f392fc9709a3	728	* @brief Enable the ADC DMA continuous request.
AnnaBridge	189:f392fc9709a3	729	* @param _DMAContReq_MODE_: DMA continuous request mode.
AnnaBridge	189:f392fc9709a3	730	* @retval None
AnnaBridge	189:f392fc9709a3	731	*/
AnnaBridge	189:f392fc9709a3	732	#define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1U)
AnnaBridge	189:f392fc9709a3	733
AnnaBridge	189:f392fc9709a3	734	/**
AnnaBridge	189:f392fc9709a3	735	* @brief Enable the ADC Auto Delay.
AnnaBridge	189:f392fc9709a3	736	* @param _AutoDelay_: Auto delay bit enable or disable.
AnnaBridge	189:f392fc9709a3	737	* @retval None
AnnaBridge	189:f392fc9709a3	738	*/
AnnaBridge	189:f392fc9709a3	739	#define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14U)
AnnaBridge	189:f392fc9709a3	740
AnnaBridge	189:f392fc9709a3	741	/**
AnnaBridge	189:f392fc9709a3	742	* @brief Enable the ADC LowPowerAutoPowerOff.
AnnaBridge	189:f392fc9709a3	743	* @param _AUTOFF_: AutoOff bit enable or disable.
AnnaBridge	189:f392fc9709a3	744	* @retval None
AnnaBridge	189:f392fc9709a3	745	*/
AnnaBridge	189:f392fc9709a3	746	#define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U)
AnnaBridge	189:f392fc9709a3	747
AnnaBridge	189:f392fc9709a3	748	/**
AnnaBridge	189:f392fc9709a3	749	* @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
AnnaBridge	189:f392fc9709a3	750	* @param _Threshold_: Threshold value
AnnaBridge	189:f392fc9709a3	751	* @retval None
AnnaBridge	189:f392fc9709a3	752	*/
AnnaBridge	189:f392fc9709a3	753	#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)
AnnaBridge	189:f392fc9709a3	754
AnnaBridge	189:f392fc9709a3	755	/**
AnnaBridge	189:f392fc9709a3	756	* @brief Enable the ADC Low Frequency mode.
AnnaBridge	189:f392fc9709a3	757	* @param _LOW_FREQUENCY_MODE_: Low Frequency mode.
AnnaBridge	189:f392fc9709a3	758	* @retval None
AnnaBridge	189:f392fc9709a3	759	*/
AnnaBridge	189:f392fc9709a3	760	#define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U)
AnnaBridge	189:f392fc9709a3	761
AnnaBridge	189:f392fc9709a3	762	/**
AnnaBridge	189:f392fc9709a3	763	* @brief Shift the offset in function of the selected ADC resolution.
AnnaBridge	189:f392fc9709a3	764	* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
AnnaBridge	189:f392fc9709a3	765	* If resolution 12 bits, no shift.
AnnaBridge	189:f392fc9709a3	766	* If resolution 10 bits, shift of 2 ranks on the right.
AnnaBridge	189:f392fc9709a3	767	* If resolution 8 bits, shift of 4 ranks on the right.
AnnaBridge	189:f392fc9709a3	768	* If resolution 6 bits, shift of 6 ranks on the right.
AnnaBridge	189:f392fc9709a3	769	* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
AnnaBridge	189:f392fc9709a3	770	* @param __HANDLE__: ADC handle.
AnnaBridge	189:f392fc9709a3	771	* @param _Offset_: Value to be shifted
AnnaBridge	189:f392fc9709a3	772	* @retval None
AnnaBridge	189:f392fc9709a3	773	*/
AnnaBridge	189:f392fc9709a3	774	#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
AnnaBridge	189:f392fc9709a3	775	((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3U)*2U))
AnnaBridge	189:f392fc9709a3	776
AnnaBridge	189:f392fc9709a3	777	/**
AnnaBridge	189:f392fc9709a3	778	* @brief Shift the AWD1 threshold in function of the selected ADC resolution.
AnnaBridge	189:f392fc9709a3	779	* Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0
AnnaBridge	189:f392fc9709a3	780	* If resolution 12 bits, no shift.
AnnaBridge	189:f392fc9709a3	781	* If resolution 10 bits, shift of 2 ranks on the right.
AnnaBridge	189:f392fc9709a3	782	* If resolution 8 bits, shift of 4 ranks on the right.
AnnaBridge	189:f392fc9709a3	783	* If resolution 6 bits, shift of 6 ranks on the right.
AnnaBridge	189:f392fc9709a3	784	* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
AnnaBridge	189:f392fc9709a3	785	* @param __HANDLE__: ADC handle.
AnnaBridge	189:f392fc9709a3	786	* @param _Threshold_: Value to be shifted
AnnaBridge	189:f392fc9709a3	787	* @retval None
AnnaBridge	189:f392fc9709a3	788	*/
AnnaBridge	189:f392fc9709a3	789	#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
AnnaBridge	189:f392fc9709a3	790	((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
AnnaBridge	189:f392fc9709a3	791
AnnaBridge	189:f392fc9709a3	792	/**
AnnaBridge	189:f392fc9709a3	793	* @brief Shift the value on the left, less significant are set to 0.
AnnaBridge	189:f392fc9709a3	794	* @param _Value_: Value to be shifted
AnnaBridge	189:f392fc9709a3	795	* @param _Shift_: Number of shift to be done
AnnaBridge	189:f392fc9709a3	796	* @retval None
AnnaBridge	189:f392fc9709a3	797	*/
AnnaBridge	189:f392fc9709a3	798	#define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_))
AnnaBridge	189:f392fc9709a3	799
AnnaBridge	189:f392fc9709a3	800
AnnaBridge	189:f392fc9709a3	801	/**
AnnaBridge	189:f392fc9709a3	802	* @brief Enable the ADC end of conversion interrupt.
AnnaBridge	189:f392fc9709a3	803	* @param __HANDLE__: ADC handle.
AnnaBridge	189:f392fc9709a3	804	* @param __INTERRUPT__: ADC Interrupt.
AnnaBridge	189:f392fc9709a3	805	* @retval None
AnnaBridge	189:f392fc9709a3	806	*/
AnnaBridge	189:f392fc9709a3	807	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
AnnaBridge	189:f392fc9709a3	808	(((__HANDLE__)->Instance->IER) \|= (__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	809
AnnaBridge	189:f392fc9709a3	810	/**
AnnaBridge	189:f392fc9709a3	811	* @brief Disable the ADC end of conversion interrupt.
AnnaBridge	189:f392fc9709a3	812	* @param __HANDLE__: ADC handle.
AnnaBridge	189:f392fc9709a3	813	* @param __INTERRUPT__: ADC interrupt.
AnnaBridge	189:f392fc9709a3	814	* @retval None
AnnaBridge	189:f392fc9709a3	815	*/
AnnaBridge	189:f392fc9709a3	816	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
AnnaBridge	189:f392fc9709a3	817	(((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	818
AnnaBridge	189:f392fc9709a3	819	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
AnnaBridge	189:f392fc9709a3	820	* @param __HANDLE__: ADC handle
AnnaBridge	189:f392fc9709a3	821	* @param __INTERRUPT__: ADC interrupt source to check
AnnaBridge	189:f392fc9709a3	822	* @arg ...
AnnaBridge	189:f392fc9709a3	823	* @arg ...
AnnaBridge	189:f392fc9709a3	824	* @retval State of interruption (TRUE or FALSE)
AnnaBridge	189:f392fc9709a3	825	*/
AnnaBridge	189:f392fc9709a3	826	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
AnnaBridge	189:f392fc9709a3	827	(((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	828
AnnaBridge	189:f392fc9709a3	829	/**
AnnaBridge	189:f392fc9709a3	830	* @brief Clear the ADC's pending flags
AnnaBridge	189:f392fc9709a3	831	* @param __HANDLE__: ADC handle.
AnnaBridge	189:f392fc9709a3	832	* @param __FLAG__: ADC flag.
AnnaBridge	189:f392fc9709a3	833	* @retval None
AnnaBridge	189:f392fc9709a3	834	*/
AnnaBridge	189:f392fc9709a3	835	/* Note: bit cleared bit by writing 1 */
AnnaBridge	189:f392fc9709a3	836	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
AnnaBridge	189:f392fc9709a3	837	(((__HANDLE__)->Instance->ISR) = (__FLAG__))
AnnaBridge	189:f392fc9709a3	838
AnnaBridge	189:f392fc9709a3	839	/**
AnnaBridge	189:f392fc9709a3	840	* @brief Get the selected ADC's flag status.
AnnaBridge	189:f392fc9709a3	841	* @param __HANDLE__: ADC handle.
AnnaBridge	189:f392fc9709a3	842	* @param __FLAG__: ADC flag.
AnnaBridge	189:f392fc9709a3	843	* @retval None
AnnaBridge	189:f392fc9709a3	844	*/
AnnaBridge	189:f392fc9709a3	845	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
AnnaBridge	189:f392fc9709a3	846	((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
AnnaBridge	189:f392fc9709a3	847
AnnaBridge	189:f392fc9709a3	848
AnnaBridge	189:f392fc9709a3	849	/**
AnnaBridge	189:f392fc9709a3	850	* @brief Simultaneously clears and sets specific bits of the handle State
AnnaBridge	189:f392fc9709a3	851	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
AnnaBridge	189:f392fc9709a3	852	* the first parameter is the ADC handle State, the second parameter is the
AnnaBridge	189:f392fc9709a3	853	* bit field to clear, the third and last parameter is the bit field to set.
AnnaBridge	189:f392fc9709a3	854	* @retval None
AnnaBridge	189:f392fc9709a3	855	*/
AnnaBridge	189:f392fc9709a3	856	#define ADC_STATE_CLR_SET MODIFY_REG
AnnaBridge	189:f392fc9709a3	857
AnnaBridge	189:f392fc9709a3	858	/**
AnnaBridge	189:f392fc9709a3	859	* @brief Clear ADC error code (set it to error code: "no error")
AnnaBridge	189:f392fc9709a3	860	* @param __HANDLE__: ADC handle
AnnaBridge	189:f392fc9709a3	861	* @retval None
AnnaBridge	189:f392fc9709a3	862	*/
AnnaBridge	189:f392fc9709a3	863	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	864	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
AnnaBridge	189:f392fc9709a3	865
AnnaBridge	189:f392fc9709a3	866
AnnaBridge	189:f392fc9709a3	867	/**
AnnaBridge	189:f392fc9709a3	868	* @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler
AnnaBridge	189:f392fc9709a3	869	* @param __HANDLE__: ADC handle
AnnaBridge	189:f392fc9709a3	870	* @retval None
AnnaBridge	189:f392fc9709a3	871	*/
AnnaBridge	189:f392fc9709a3	872
AnnaBridge	189:f392fc9709a3	873	#define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__) \
AnnaBridge	189:f392fc9709a3	874	do{ \
AnnaBridge	189:f392fc9709a3	875	if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) \|\| \
AnnaBridge	189:f392fc9709a3	876	(((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\| \
AnnaBridge	189:f392fc9709a3	877	(((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) \
AnnaBridge	189:f392fc9709a3	878	{ \
AnnaBridge	189:f392fc9709a3	879	(__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
AnnaBridge	189:f392fc9709a3	880	(__HANDLE__)->Instance->CFGR2 \|= (__HANDLE__)->Init.ClockPrescaler; \
AnnaBridge	189:f392fc9709a3	881	} \
AnnaBridge	189:f392fc9709a3	882	else \
AnnaBridge	189:f392fc9709a3	883	{ \
AnnaBridge	189:f392fc9709a3	884	/* CKMOD bits must be reset */ \
AnnaBridge	189:f392fc9709a3	885	(__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
AnnaBridge	189:f392fc9709a3	886	ADC->CCR &= ~(ADC_CCR_PRESC); \
AnnaBridge	189:f392fc9709a3	887	ADC->CCR \|= (__HANDLE__)->Init.ClockPrescaler; \
AnnaBridge	189:f392fc9709a3	888	} \
AnnaBridge	189:f392fc9709a3	889	} while(0)
AnnaBridge	189:f392fc9709a3	890
AnnaBridge	189:f392fc9709a3	891
AnnaBridge	189:f392fc9709a3	892	#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) \|\|\
AnnaBridge	189:f392fc9709a3	893	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) \|\|\
AnnaBridge	189:f392fc9709a3	894	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\|\
AnnaBridge	189:f392fc9709a3	895	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) \|\|\
AnnaBridge	189:f392fc9709a3	896	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) \|\|\
AnnaBridge	189:f392fc9709a3	897	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) \|\|\
AnnaBridge	189:f392fc9709a3	898	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) \|\|\
AnnaBridge	189:f392fc9709a3	899	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) \|\|\
AnnaBridge	189:f392fc9709a3	900	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) \|\|\
AnnaBridge	189:f392fc9709a3	901	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) \|\|\
AnnaBridge	189:f392fc9709a3	902	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) \|\|\
AnnaBridge	189:f392fc9709a3	903	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) \|\|\
AnnaBridge	189:f392fc9709a3	904	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) \|\|\
AnnaBridge	189:f392fc9709a3	905	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) \|\|\
AnnaBridge	189:f392fc9709a3	906	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) \|\|\
AnnaBridge	189:f392fc9709a3	907	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
AnnaBridge	189:f392fc9709a3	908
AnnaBridge	189:f392fc9709a3	909	#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) \|\| \
AnnaBridge	189:f392fc9709a3	910	((RESOLUTION) == ADC_RESOLUTION_10B) \|\| \
AnnaBridge	189:f392fc9709a3	911	((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
AnnaBridge	189:f392fc9709a3	912	((RESOLUTION) == ADC_RESOLUTION_6B))
AnnaBridge	189:f392fc9709a3	913
AnnaBridge	189:f392fc9709a3	914	#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
AnnaBridge	189:f392fc9709a3	915	((RESOLUTION) == ADC_RESOLUTION_6B))
AnnaBridge	189:f392fc9709a3	916
AnnaBridge	189:f392fc9709a3	917	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
AnnaBridge	189:f392fc9709a3	918	((ALIGN) == ADC_DATAALIGN_LEFT))
AnnaBridge	189:f392fc9709a3	919
AnnaBridge	189:f392fc9709a3	920	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
AnnaBridge	189:f392fc9709a3	921	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
AnnaBridge	189:f392fc9709a3	922	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
AnnaBridge	189:f392fc9709a3	923	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
AnnaBridge	189:f392fc9709a3	924
AnnaBridge	189:f392fc9709a3	925	#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) \|\| \
AnnaBridge	189:f392fc9709a3	926	((EOC_SELECTION) == ADC_EOC_SEQ_CONV) \|\| \
AnnaBridge	189:f392fc9709a3	927	((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV))
AnnaBridge	189:f392fc9709a3	928
AnnaBridge	189:f392fc9709a3	929	#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) \|\| \
AnnaBridge	189:f392fc9709a3	930	((OVR) == ADC_OVR_DATA_OVERWRITTEN))
AnnaBridge	189:f392fc9709a3	931
AnnaBridge	189:f392fc9709a3	932	#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) \|\| \
AnnaBridge	189:f392fc9709a3	933	((WATCHDOG) == ADC_RANK_NONE))
AnnaBridge	189:f392fc9709a3	934
AnnaBridge	189:f392fc9709a3	935	#if defined (STM32L053xx) \|\| defined (STM32L063xx) \|\| defined (STM32L073xx) \|\| defined (STM32L083xx)
AnnaBridge	189:f392fc9709a3	936	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
AnnaBridge	189:f392fc9709a3	937	((CHANNEL) == ADC_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	938	((CHANNEL) == ADC_CHANNEL_2) \|\| \
AnnaBridge	189:f392fc9709a3	939	((CHANNEL) == ADC_CHANNEL_3) \|\| \
AnnaBridge	189:f392fc9709a3	940	((CHANNEL) == ADC_CHANNEL_4) \|\| \
AnnaBridge	189:f392fc9709a3	941	((CHANNEL) == ADC_CHANNEL_5) \|\| \
AnnaBridge	189:f392fc9709a3	942	((CHANNEL) == ADC_CHANNEL_6) \|\| \
AnnaBridge	189:f392fc9709a3	943	((CHANNEL) == ADC_CHANNEL_7) \|\| \
AnnaBridge	189:f392fc9709a3	944	((CHANNEL) == ADC_CHANNEL_8) \|\| \
AnnaBridge	189:f392fc9709a3	945	((CHANNEL) == ADC_CHANNEL_9) \|\| \
AnnaBridge	189:f392fc9709a3	946	((CHANNEL) == ADC_CHANNEL_10) \|\| \
AnnaBridge	189:f392fc9709a3	947	((CHANNEL) == ADC_CHANNEL_11) \|\| \
AnnaBridge	189:f392fc9709a3	948	((CHANNEL) == ADC_CHANNEL_12) \|\| \
AnnaBridge	189:f392fc9709a3	949	((CHANNEL) == ADC_CHANNEL_13) \|\| \
AnnaBridge	189:f392fc9709a3	950	((CHANNEL) == ADC_CHANNEL_14) \|\| \
AnnaBridge	189:f392fc9709a3	951	((CHANNEL) == ADC_CHANNEL_15) \|\| \
AnnaBridge	189:f392fc9709a3	952	((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) \|\| \
AnnaBridge	189:f392fc9709a3	953	((CHANNEL) == ADC_CHANNEL_VREFINT) \|\| \
AnnaBridge	189:f392fc9709a3	954	((CHANNEL) == ADC_CHANNEL_VLCD))
AnnaBridge	189:f392fc9709a3	955	#else
AnnaBridge	189:f392fc9709a3	956	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
AnnaBridge	189:f392fc9709a3	957	((CHANNEL) == ADC_CHANNEL_1) \|\| \
AnnaBridge	189:f392fc9709a3	958	((CHANNEL) == ADC_CHANNEL_2) \|\| \
AnnaBridge	189:f392fc9709a3	959	((CHANNEL) == ADC_CHANNEL_3) \|\| \
AnnaBridge	189:f392fc9709a3	960	((CHANNEL) == ADC_CHANNEL_4) \|\| \
AnnaBridge	189:f392fc9709a3	961	((CHANNEL) == ADC_CHANNEL_5) \|\| \
AnnaBridge	189:f392fc9709a3	962	((CHANNEL) == ADC_CHANNEL_6) \|\| \
AnnaBridge	189:f392fc9709a3	963	((CHANNEL) == ADC_CHANNEL_7) \|\| \
AnnaBridge	189:f392fc9709a3	964	((CHANNEL) == ADC_CHANNEL_8) \|\| \
AnnaBridge	189:f392fc9709a3	965	((CHANNEL) == ADC_CHANNEL_9) \|\| \
AnnaBridge	189:f392fc9709a3	966	((CHANNEL) == ADC_CHANNEL_10) \|\| \
AnnaBridge	189:f392fc9709a3	967	((CHANNEL) == ADC_CHANNEL_11) \|\| \
AnnaBridge	189:f392fc9709a3	968	((CHANNEL) == ADC_CHANNEL_12) \|\| \
AnnaBridge	189:f392fc9709a3	969	((CHANNEL) == ADC_CHANNEL_13) \|\| \
AnnaBridge	189:f392fc9709a3	970	((CHANNEL) == ADC_CHANNEL_14) \|\| \
AnnaBridge	189:f392fc9709a3	971	((CHANNEL) == ADC_CHANNEL_15) \|\| \
AnnaBridge	189:f392fc9709a3	972	((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) \|\| \
AnnaBridge	189:f392fc9709a3	973	((CHANNEL) == ADC_CHANNEL_VREFINT))
AnnaBridge	189:f392fc9709a3	974	#endif
AnnaBridge	189:f392fc9709a3	975
AnnaBridge	189:f392fc9709a3	976	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) \|\| \
AnnaBridge	189:f392fc9709a3	977	((TIME) == ADC_SAMPLETIME_3CYCLES_5 ) \|\| \
AnnaBridge	189:f392fc9709a3	978	((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) \|\| \
AnnaBridge	189:f392fc9709a3	979	((TIME) == ADC_SAMPLETIME_12CYCLES_5 ) \|\| \
AnnaBridge	189:f392fc9709a3	980	((TIME) == ADC_SAMPLETIME_19CYCLES_5 ) \|\| \
AnnaBridge	189:f392fc9709a3	981	((TIME) == ADC_SAMPLETIME_39CYCLES_5 ) \|\| \
AnnaBridge	189:f392fc9709a3	982	((TIME) == ADC_SAMPLETIME_79CYCLES_5 ) \|\| \
AnnaBridge	189:f392fc9709a3	983	((TIME) == ADC_SAMPLETIME_160CYCLES_5))
AnnaBridge	189:f392fc9709a3	984
AnnaBridge	189:f392fc9709a3	985	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) \|\| \
AnnaBridge	189:f392fc9709a3	986	((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
AnnaBridge	189:f392fc9709a3	987
AnnaBridge	189:f392fc9709a3	988	#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) \|\| \
AnnaBridge	189:f392fc9709a3	989	((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) \|\| \
AnnaBridge	189:f392fc9709a3	990	((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) \|\| \
AnnaBridge	189:f392fc9709a3	991	((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) \|\| \
AnnaBridge	189:f392fc9709a3	992	((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) \|\| \
AnnaBridge	189:f392fc9709a3	993	((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) \|\| \
AnnaBridge	189:f392fc9709a3	994	((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) \|\| \
AnnaBridge	189:f392fc9709a3	995	((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
AnnaBridge	189:f392fc9709a3	996
AnnaBridge	189:f392fc9709a3	997	#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) \|\| \
AnnaBridge	189:f392fc9709a3	998	((SHIFT) == ADC_RIGHTBITSHIFT_1 ) \|\| \
AnnaBridge	189:f392fc9709a3	999	((SHIFT) == ADC_RIGHTBITSHIFT_2 ) \|\| \
AnnaBridge	189:f392fc9709a3	1000	((SHIFT) == ADC_RIGHTBITSHIFT_3 ) \|\| \
AnnaBridge	189:f392fc9709a3	1001	((SHIFT) == ADC_RIGHTBITSHIFT_4 ) \|\| \
AnnaBridge	189:f392fc9709a3	1002	((SHIFT) == ADC_RIGHTBITSHIFT_5 ) \|\| \
AnnaBridge	189:f392fc9709a3	1003	((SHIFT) == ADC_RIGHTBITSHIFT_6 ) \|\| \
AnnaBridge	189:f392fc9709a3	1004	((SHIFT) == ADC_RIGHTBITSHIFT_7 ) \|\| \
AnnaBridge	189:f392fc9709a3	1005	((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
AnnaBridge	189:f392fc9709a3	1006
AnnaBridge	189:f392fc9709a3	1007	#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) \|\| \
AnnaBridge	189:f392fc9709a3	1008	((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
AnnaBridge	189:f392fc9709a3	1009
AnnaBridge	189:f392fc9709a3	1010	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) \|\| \
AnnaBridge	189:f392fc9709a3	1011	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
AnnaBridge	189:f392fc9709a3	1012	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))
AnnaBridge	189:f392fc9709a3	1013
AnnaBridge	189:f392fc9709a3	1014	#define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)
AnnaBridge	189:f392fc9709a3	1015
AnnaBridge	189:f392fc9709a3	1016	#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) \|\| \
AnnaBridge	189:f392fc9709a3	1017	((EVENT) == ADC_OVR_EVENT))
AnnaBridge	189:f392fc9709a3	1018
AnnaBridge	189:f392fc9709a3	1019
AnnaBridge	189:f392fc9709a3	1020	/** @defgroup ADC_range_verification ADC Range Verification
AnnaBridge	189:f392fc9709a3	1021	* in function of ADC resolution selected (12, 10, 8 or 6 bits)
AnnaBridge	189:f392fc9709a3	1022	* @{
AnnaBridge	189:f392fc9709a3	1023	*/
AnnaBridge	189:f392fc9709a3	1024	#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
AnnaBridge	189:f392fc9709a3	1025	((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) \|\| \
AnnaBridge	189:f392fc9709a3	1026	(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) \|\| \
AnnaBridge	189:f392fc9709a3	1027	(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) \|\| \
AnnaBridge	189:f392fc9709a3	1028	(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003FU))))
AnnaBridge	189:f392fc9709a3	1029	/**
AnnaBridge	189:f392fc9709a3	1030	* @}
AnnaBridge	189:f392fc9709a3	1031	*/
AnnaBridge	189:f392fc9709a3	1032
AnnaBridge	189:f392fc9709a3	1033	/** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification
AnnaBridge	189:f392fc9709a3	1034	* @{
AnnaBridge	189:f392fc9709a3	1035	*/
AnnaBridge	189:f392fc9709a3	1036	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
AnnaBridge	189:f392fc9709a3	1037	/**
AnnaBridge	189:f392fc9709a3	1038	* @}
AnnaBridge	189:f392fc9709a3	1039	*/
AnnaBridge	189:f392fc9709a3	1040
AnnaBridge	189:f392fc9709a3	1041	/**
AnnaBridge	189:f392fc9709a3	1042	* @}
AnnaBridge	189:f392fc9709a3	1043	*/
AnnaBridge	189:f392fc9709a3	1044
AnnaBridge	189:f392fc9709a3	1045	/* Include ADC HAL Extended module */
AnnaBridge	189:f392fc9709a3	1046	#include "stm32l0xx_hal_adc_ex.h"
AnnaBridge	189:f392fc9709a3	1047
AnnaBridge	189:f392fc9709a3	1048	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1049	/** @addtogroup ADC_Exported_Functions
AnnaBridge	189:f392fc9709a3	1050	* @{
AnnaBridge	189:f392fc9709a3	1051	*/
AnnaBridge	189:f392fc9709a3	1052
AnnaBridge	189:f392fc9709a3	1053	/** @addtogroup ADC_Exported_Functions_Group1
AnnaBridge	189:f392fc9709a3	1054	* @brief Initialization and Configuration functions
AnnaBridge	189:f392fc9709a3	1055	* @{
AnnaBridge	189:f392fc9709a3	1056	*/
AnnaBridge	189:f392fc9709a3	1057	/* Initialization and de-initialization functions ****************************/
AnnaBridge	189:f392fc9709a3	1058	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1059	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
AnnaBridge	189:f392fc9709a3	1060	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1061	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1062	/**
AnnaBridge	189:f392fc9709a3	1063	* @}
AnnaBridge	189:f392fc9709a3	1064	*/
AnnaBridge	189:f392fc9709a3	1065
AnnaBridge	189:f392fc9709a3	1066	/** @addtogroup ADC_Exported_Functions_Group2
AnnaBridge	189:f392fc9709a3	1067	* @brief IO operation functions
AnnaBridge	189:f392fc9709a3	1068	* @{
AnnaBridge	189:f392fc9709a3	1069	*/
AnnaBridge	189:f392fc9709a3	1070	/* IO operation functions *****************************************************/
AnnaBridge	189:f392fc9709a3	1071
AnnaBridge	189:f392fc9709a3	1072	/* Blocking mode: Polling */
AnnaBridge	189:f392fc9709a3	1073	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1074	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1075	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
AnnaBridge	189:f392fc9709a3	1076	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
AnnaBridge	189:f392fc9709a3	1077
AnnaBridge	189:f392fc9709a3	1078	/* Non-blocking mode: Interruption */
AnnaBridge	189:f392fc9709a3	1079	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1080	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1081
AnnaBridge	189:f392fc9709a3	1082	/* Non-blocking mode: DMA */
AnnaBridge	189:f392fc9709a3	1083	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
AnnaBridge	189:f392fc9709a3	1084	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1085
AnnaBridge	189:f392fc9709a3	1086	/* ADC retrieve conversion value intended to be used with polling or interruption */
AnnaBridge	189:f392fc9709a3	1087	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1088
AnnaBridge	189:f392fc9709a3	1089	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
AnnaBridge	189:f392fc9709a3	1090	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1091	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1092	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1093	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1094	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
AnnaBridge	189:f392fc9709a3	1095	/**
AnnaBridge	189:f392fc9709a3	1096	* @}
AnnaBridge	189:f392fc9709a3	1097	*/
AnnaBridge	189:f392fc9709a3	1098
AnnaBridge	189:f392fc9709a3	1099	/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
AnnaBridge	189:f392fc9709a3	1100	* @brief Peripheral Control functions
AnnaBridge	189:f392fc9709a3	1101	* @{
AnnaBridge	189:f392fc9709a3	1102	*/
AnnaBridge	189:f392fc9709a3	1103	/* Peripheral Control functions ***********************************************/
AnnaBridge	189:f392fc9709a3	1104	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
AnnaBridge	189:f392fc9709a3	1105	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
AnnaBridge	189:f392fc9709a3	1106	/**
AnnaBridge	189:f392fc9709a3	1107	* @}
AnnaBridge	189:f392fc9709a3	1108	*/
AnnaBridge	189:f392fc9709a3	1109
AnnaBridge	189:f392fc9709a3	1110	/* Peripheral State functions *************************************************/
AnnaBridge	189:f392fc9709a3	1111	/** @addtogroup ADC_Exported_Functions_Group4
AnnaBridge	189:f392fc9709a3	1112	* @{
AnnaBridge	189:f392fc9709a3	1113	*/
AnnaBridge	189:f392fc9709a3	1114	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
AnnaBridge	189:f392fc9709a3	1115	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
AnnaBridge	189:f392fc9709a3	1116	/**
AnnaBridge	189:f392fc9709a3	1117	* @}
AnnaBridge	189:f392fc9709a3	1118	*/
AnnaBridge	189:f392fc9709a3	1119
AnnaBridge	189:f392fc9709a3	1120
AnnaBridge	189:f392fc9709a3	1121	/**
AnnaBridge	189:f392fc9709a3	1122	* @}
AnnaBridge	189:f392fc9709a3	1123	*/
AnnaBridge	189:f392fc9709a3	1124
AnnaBridge	189:f392fc9709a3	1125	/**
AnnaBridge	189:f392fc9709a3	1126	* @}
AnnaBridge	189:f392fc9709a3	1127	*/
AnnaBridge	189:f392fc9709a3	1128
AnnaBridge	189:f392fc9709a3	1129	/**
AnnaBridge	189:f392fc9709a3	1130	* @}
AnnaBridge	189:f392fc9709a3	1131	*/
AnnaBridge	189:f392fc9709a3	1132
AnnaBridge	189:f392fc9709a3	1133	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	1134	}
AnnaBridge	189:f392fc9709a3	1135	#endif
AnnaBridge	189:f392fc9709a3	1136
AnnaBridge	189:f392fc9709a3	1137
AnnaBridge	189:f392fc9709a3	1138	#endif /__STM32L0xx_HAL_ADC_H /
AnnaBridge	189:f392fc9709a3	1139
AnnaBridge	189:f392fc9709a3	1140	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/