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cmsis/BUILD/mbed/TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/stm32l0xx_hal.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32l0xx_hal.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief This file contains all the functions prototypes for the HAL |
| AnnaBridge | 189:f392fc9709a3 | 6 | * module driver. |
| AnnaBridge | 189:f392fc9709a3 | 7 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 8 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 9 | * |
| AnnaBridge | 189:f392fc9709a3 | 10 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 11 | * |
| AnnaBridge | 189:f392fc9709a3 | 12 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 13 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 14 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 15 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 16 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 17 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 18 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 19 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 20 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 21 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 22 | * |
| AnnaBridge | 189:f392fc9709a3 | 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 24 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 27 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 28 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 29 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 30 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 32 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 33 | * |
| AnnaBridge | 189:f392fc9709a3 | 34 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 35 | */ |
| AnnaBridge | 189:f392fc9709a3 | 36 | |
| AnnaBridge | 189:f392fc9709a3 | 37 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 38 | #ifndef __STM32L0xx_HAL_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | #define __STM32L0xx_HAL_H |
| AnnaBridge | 189:f392fc9709a3 | 40 | |
| AnnaBridge | 189:f392fc9709a3 | 41 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 42 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 43 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 44 | |
| AnnaBridge | 189:f392fc9709a3 | 45 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 46 | #include "stm32l0xx_hal_conf.h" |
| AnnaBridge | 189:f392fc9709a3 | 47 | |
| AnnaBridge | 189:f392fc9709a3 | 48 | /** @addtogroup STM32L0xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 49 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 50 | */ |
| AnnaBridge | 189:f392fc9709a3 | 51 | |
| AnnaBridge | 189:f392fc9709a3 | 52 | /** @defgroup HAL HAL |
| AnnaBridge | 189:f392fc9709a3 | 53 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 54 | */ |
| AnnaBridge | 189:f392fc9709a3 | 55 | /** @defgroup HAL_Exported_Constants HAL Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 56 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 57 | */ |
| AnnaBridge | 189:f392fc9709a3 | 58 | |
| AnnaBridge | 189:f392fc9709a3 | 59 | /** @defgroup SYSCFG_BootMode Boot Mode |
| AnnaBridge | 189:f392fc9709a3 | 60 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 61 | */ |
| AnnaBridge | 189:f392fc9709a3 | 62 | #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 63 | #define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_BOOT_MODE_0) |
| AnnaBridge | 189:f392fc9709a3 | 64 | #define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_CFGR1_BOOT_MODE) |
| AnnaBridge | 189:f392fc9709a3 | 65 | |
| AnnaBridge | 189:f392fc9709a3 | 66 | /** |
| AnnaBridge | 189:f392fc9709a3 | 67 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 68 | */ |
| AnnaBridge | 189:f392fc9709a3 | 69 | |
| AnnaBridge | 189:f392fc9709a3 | 70 | /** @defgroup DBGMCU_Low_Power_Config DBGMCU Low Power Configuration |
| AnnaBridge | 189:f392fc9709a3 | 71 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 72 | */ |
| AnnaBridge | 189:f392fc9709a3 | 73 | #define DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP |
| AnnaBridge | 189:f392fc9709a3 | 74 | #define DBGMCU_STOP DBGMCU_CR_DBG_STOP |
| AnnaBridge | 189:f392fc9709a3 | 75 | #define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY |
| AnnaBridge | 189:f392fc9709a3 | 76 | #define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00U) && ((__PERIPH__) != 0x00U)) |
| AnnaBridge | 189:f392fc9709a3 | 77 | |
| AnnaBridge | 189:f392fc9709a3 | 78 | |
| AnnaBridge | 189:f392fc9709a3 | 79 | /** |
| AnnaBridge | 189:f392fc9709a3 | 80 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 81 | */ |
| AnnaBridge | 189:f392fc9709a3 | 82 | |
| AnnaBridge | 189:f392fc9709a3 | 83 | #if defined (LCD_BASE) /* STM32L0x3xx only */ |
| AnnaBridge | 189:f392fc9709a3 | 84 | /** @defgroup SYSCFG_LCD_EXT_CAPA SYSCFG LCD External Capacitors |
| AnnaBridge | 189:f392fc9709a3 | 85 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 86 | */ |
| AnnaBridge | 189:f392fc9709a3 | 87 | #define SYSCFG_LCD_EXT_CAPA SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */ |
| AnnaBridge | 189:f392fc9709a3 | 88 | #define SYSCFG_VLCD_PB2_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_0 /*!< Connection on PB2 */ |
| AnnaBridge | 189:f392fc9709a3 | 89 | #define SYSCFG_VLCD_PB12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_1 /*!< Connection on PB12 */ |
| AnnaBridge | 189:f392fc9709a3 | 90 | #define SYSCFG_VLCD_PB0_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_2 /*!< Connection on PB0 */ |
| AnnaBridge | 189:f392fc9709a3 | 91 | #if defined (SYSCFG_CFGR2_CAPA_3) |
| AnnaBridge | 189:f392fc9709a3 | 92 | #define SYSCFG_VLCD_PE11_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_3 /*!< Connection on PE11 */ |
| AnnaBridge | 189:f392fc9709a3 | 93 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 94 | #if defined (SYSCFG_CFGR2_CAPA_4) |
| AnnaBridge | 189:f392fc9709a3 | 95 | #define SYSCFG_VLCD_PE12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_4 /*!< Connection on PE12 */ |
| AnnaBridge | 189:f392fc9709a3 | 96 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 97 | |
| AnnaBridge | 189:f392fc9709a3 | 98 | /** |
| AnnaBridge | 189:f392fc9709a3 | 99 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 100 | */ |
| AnnaBridge | 189:f392fc9709a3 | 101 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 102 | |
| AnnaBridge | 189:f392fc9709a3 | 103 | /** @defgroup SYSCFG_VREFINT_OUT_SELECT SYSCFG VREFINT Out Selection |
| AnnaBridge | 189:f392fc9709a3 | 104 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 105 | */ |
| AnnaBridge | 189:f392fc9709a3 | 106 | #define SYSCFG_VREFINT_OUT_NONE ((uint32_t)0x00000000U) /* no pad connected */ |
| AnnaBridge | 189:f392fc9709a3 | 107 | #define SYSCFG_VREFINT_OUT_PB0 SYSCFG_CFGR3_VREF_OUT_0 /* Selects PBO as output for the Vrefint */ |
| AnnaBridge | 189:f392fc9709a3 | 108 | #define SYSCFG_VREFINT_OUT_PB1 SYSCFG_CFGR3_VREF_OUT_1 /* Selects PB1 as output for the Vrefint */ |
| AnnaBridge | 189:f392fc9709a3 | 109 | #define SYSCFG_VREFINT_OUT_PB0_PB1 SYSCFG_CFGR3_VREF_OUT /* Selects PBO and PB1 as output for the Vrefint */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | |
| AnnaBridge | 189:f392fc9709a3 | 111 | #define IS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT) (((OUTPUT) == SYSCFG_VREFINT_OUT_NONE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 112 | ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0) || \ |
| AnnaBridge | 189:f392fc9709a3 | 113 | ((OUTPUT) == SYSCFG_VREFINT_OUT_PB1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 114 | ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0_PB1)) |
| AnnaBridge | 189:f392fc9709a3 | 115 | /** |
| AnnaBridge | 189:f392fc9709a3 | 116 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 117 | */ |
| AnnaBridge | 189:f392fc9709a3 | 118 | |
| AnnaBridge | 189:f392fc9709a3 | 119 | /** @defgroup SYSCFG_flags_definition SYSCFG Flags Definition |
| AnnaBridge | 189:f392fc9709a3 | 120 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 121 | */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | #define SYSCFG_FLAG_VREFINT_READY SYSCFG_CFGR3_VREFINT_RDYF |
| AnnaBridge | 189:f392fc9709a3 | 123 | |
| AnnaBridge | 189:f392fc9709a3 | 124 | #define IS_SYSCFG_FLAG(FLAG) ((FLAG) == SYSCFG_FLAG_VREFINT_READY)) |
| AnnaBridge | 189:f392fc9709a3 | 125 | |
| AnnaBridge | 189:f392fc9709a3 | 126 | /** |
| AnnaBridge | 189:f392fc9709a3 | 127 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 128 | */ |
| AnnaBridge | 189:f392fc9709a3 | 129 | |
| AnnaBridge | 189:f392fc9709a3 | 130 | /** @defgroup SYSCFG_FastModePlus_GPIO Fast Mode Plus on GPIO |
| AnnaBridge | 189:f392fc9709a3 | 131 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 132 | */ |
| AnnaBridge | 189:f392fc9709a3 | 133 | /** @brief Fast mode Plus driving capability on a specific GPIO |
| AnnaBridge | 189:f392fc9709a3 | 134 | */ |
| AnnaBridge | 189:f392fc9709a3 | 135 | #if defined (SYSCFG_CFGR2_I2C_PB6_FMP) |
| AnnaBridge | 189:f392fc9709a3 | 136 | #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /* Enable Fast Mode Plus on PB6 */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 138 | #if defined (SYSCFG_CFGR2_I2C_PB7_FMP) |
| AnnaBridge | 189:f392fc9709a3 | 139 | #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /* Enable Fast Mode Plus on PB7 */ |
| AnnaBridge | 189:f392fc9709a3 | 140 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 141 | #if defined (SYSCFG_CFGR2_I2C_PB8_FMP) |
| AnnaBridge | 189:f392fc9709a3 | 142 | #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /* Enable Fast Mode Plus on PB8 */ |
| AnnaBridge | 189:f392fc9709a3 | 143 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 144 | #if defined (SYSCFG_CFGR2_I2C_PB9_FMP) |
| AnnaBridge | 189:f392fc9709a3 | 145 | #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /* Enable Fast Mode Plus on PB9 */ |
| AnnaBridge | 189:f392fc9709a3 | 146 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 147 | |
| AnnaBridge | 189:f392fc9709a3 | 148 | #define IS_SYSCFG_FASTMODEPLUS(PIN) ((((PIN) & (SYSCFG_FASTMODEPLUS_PB6)) == SYSCFG_FASTMODEPLUS_PB6) || \ |
| AnnaBridge | 189:f392fc9709a3 | 149 | (((PIN) & (SYSCFG_FASTMODEPLUS_PB7)) == SYSCFG_FASTMODEPLUS_PB7) || \ |
| AnnaBridge | 189:f392fc9709a3 | 150 | (((PIN) & (SYSCFG_FASTMODEPLUS_PB8)) == SYSCFG_FASTMODEPLUS_PB8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 151 | (((PIN) & (SYSCFG_FASTMODEPLUS_PB9)) == SYSCFG_FASTMODEPLUS_PB9) ) |
| AnnaBridge | 189:f392fc9709a3 | 152 | /** |
| AnnaBridge | 189:f392fc9709a3 | 153 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 154 | */ |
| AnnaBridge | 189:f392fc9709a3 | 155 | /** |
| AnnaBridge | 189:f392fc9709a3 | 156 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 157 | */ |
| AnnaBridge | 189:f392fc9709a3 | 158 | |
| AnnaBridge | 189:f392fc9709a3 | 159 | /** @defgroup HAL_Exported_Macros HAL Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 160 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 161 | */ |
| AnnaBridge | 189:f392fc9709a3 | 162 | |
| AnnaBridge | 189:f392fc9709a3 | 163 | /** @brief Freeze/Unfreeze Peripherals in Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 164 | */ |
| AnnaBridge | 189:f392fc9709a3 | 165 | #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 166 | /** |
| AnnaBridge | 189:f392fc9709a3 | 167 | * @brief TIM2 Peripherals Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 168 | */ |
| AnnaBridge | 189:f392fc9709a3 | 169 | #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 170 | #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 171 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 172 | |
| AnnaBridge | 189:f392fc9709a3 | 173 | #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 174 | /** |
| AnnaBridge | 189:f392fc9709a3 | 175 | * @brief TIM3 Peripherals Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 176 | */ |
| AnnaBridge | 189:f392fc9709a3 | 177 | #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 178 | #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 179 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 180 | |
| AnnaBridge | 189:f392fc9709a3 | 181 | #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 182 | /** |
| AnnaBridge | 189:f392fc9709a3 | 183 | * @brief TIM6 Peripherals Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 184 | */ |
| AnnaBridge | 189:f392fc9709a3 | 185 | #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 186 | #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 187 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 188 | |
| AnnaBridge | 189:f392fc9709a3 | 189 | #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 190 | /** |
| AnnaBridge | 189:f392fc9709a3 | 191 | * @brief TIM7 Peripherals Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 192 | */ |
| AnnaBridge | 189:f392fc9709a3 | 193 | #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 194 | #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 195 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 196 | |
| AnnaBridge | 189:f392fc9709a3 | 197 | #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 198 | /** |
| AnnaBridge | 189:f392fc9709a3 | 199 | * @brief RTC Peripherals Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 200 | */ |
| AnnaBridge | 189:f392fc9709a3 | 201 | #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 202 | #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 203 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 204 | |
| AnnaBridge | 189:f392fc9709a3 | 205 | #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 206 | /** |
| AnnaBridge | 189:f392fc9709a3 | 207 | * @brief WWDG Peripherals Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 208 | */ |
| AnnaBridge | 189:f392fc9709a3 | 209 | #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 210 | #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 211 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 212 | |
| AnnaBridge | 189:f392fc9709a3 | 213 | #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 214 | /** |
| AnnaBridge | 189:f392fc9709a3 | 215 | * @brief IWDG Peripherals Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 216 | */ |
| AnnaBridge | 189:f392fc9709a3 | 217 | #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 218 | #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 219 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 220 | |
| AnnaBridge | 189:f392fc9709a3 | 221 | #if defined (DBGMCU_APB1_FZ_DBG_I2C1_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 222 | /** |
| AnnaBridge | 189:f392fc9709a3 | 223 | * @brief I2C1 Peripherals Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 224 | */ |
| AnnaBridge | 189:f392fc9709a3 | 225 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 226 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 227 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 228 | |
| AnnaBridge | 189:f392fc9709a3 | 229 | #if defined (DBGMCU_APB1_FZ_DBG_I2C2_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 230 | /** |
| AnnaBridge | 189:f392fc9709a3 | 231 | * @brief I2C2 Peripherals Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 232 | */ |
| AnnaBridge | 189:f392fc9709a3 | 233 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 234 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 235 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 236 | |
| AnnaBridge | 189:f392fc9709a3 | 237 | #if defined (DBGMCU_APB1_FZ_DBG_I2C3_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 238 | /** |
| AnnaBridge | 189:f392fc9709a3 | 239 | * @brief I2C3 Peripherals Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 240 | */ |
| AnnaBridge | 189:f392fc9709a3 | 241 | #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 242 | #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 243 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 244 | |
| AnnaBridge | 189:f392fc9709a3 | 245 | #if defined (DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 246 | /** |
| AnnaBridge | 189:f392fc9709a3 | 247 | * @brief LPTIMER Peripherals Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 248 | */ |
| AnnaBridge | 189:f392fc9709a3 | 249 | #define __HAL_DBGMCU_FREEZE_LPTIMER() SET_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 250 | #define __HAL_DBGMCU_UNFREEZE_LPTIMER() CLEAR_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 251 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 252 | |
| AnnaBridge | 189:f392fc9709a3 | 253 | #if defined (DBGMCU_APB2_FZ_DBG_TIM22_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 254 | /** |
| AnnaBridge | 189:f392fc9709a3 | 255 | * @brief TIM22 Peripherals Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 256 | */ |
| AnnaBridge | 189:f392fc9709a3 | 257 | #define __HAL_DBGMCU_FREEZE_TIM22() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 258 | #define __HAL_DBGMCU_UNFREEZE_TIM22() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 259 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 260 | |
| AnnaBridge | 189:f392fc9709a3 | 261 | #if defined (DBGMCU_APB2_FZ_DBG_TIM21_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 262 | /** |
| AnnaBridge | 189:f392fc9709a3 | 263 | * @brief TIM21 Peripherals Debug mode |
| AnnaBridge | 189:f392fc9709a3 | 264 | */ |
| AnnaBridge | 189:f392fc9709a3 | 265 | #define __HAL_DBGMCU_FREEZE_TIM21() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 266 | #define __HAL_DBGMCU_UNFREEZE_TIM21() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) |
| AnnaBridge | 189:f392fc9709a3 | 267 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 268 | |
| AnnaBridge | 189:f392fc9709a3 | 269 | /** @brief Main Flash memory mapped at 0x00000000 |
| AnnaBridge | 189:f392fc9709a3 | 270 | */ |
| AnnaBridge | 189:f392fc9709a3 | 271 | #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) |
| AnnaBridge | 189:f392fc9709a3 | 272 | |
| AnnaBridge | 189:f392fc9709a3 | 273 | /** @brief System Flash memory mapped at 0x00000000 |
| AnnaBridge | 189:f392fc9709a3 | 274 | */ |
| AnnaBridge | 189:f392fc9709a3 | 275 | #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) |
| AnnaBridge | 189:f392fc9709a3 | 276 | |
| AnnaBridge | 189:f392fc9709a3 | 277 | |
| AnnaBridge | 189:f392fc9709a3 | 278 | /** @brief Embedded SRAM mapped at 0x00000000 |
| AnnaBridge | 189:f392fc9709a3 | 279 | */ |
| AnnaBridge | 189:f392fc9709a3 | 280 | #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1) |
| AnnaBridge | 189:f392fc9709a3 | 281 | |
| AnnaBridge | 189:f392fc9709a3 | 282 | /** @brief Configuration of the DBG Low Power mode. |
| AnnaBridge | 189:f392fc9709a3 | 283 | * @param __DBGLPMODE__: bit field to indicate in wich Low Power mode DBG is still active. |
| AnnaBridge | 189:f392fc9709a3 | 284 | * This parameter can be a value of |
| AnnaBridge | 189:f392fc9709a3 | 285 | * - DBGMCU_SLEEP |
| AnnaBridge | 189:f392fc9709a3 | 286 | * - DBGMCU_STOP |
| AnnaBridge | 189:f392fc9709a3 | 287 | * - DBGMCU_STANDBY |
| AnnaBridge | 189:f392fc9709a3 | 288 | */ |
| AnnaBridge | 189:f392fc9709a3 | 289 | #define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \ |
| AnnaBridge | 189:f392fc9709a3 | 290 | MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \ |
| AnnaBridge | 189:f392fc9709a3 | 291 | } while (0) |
| AnnaBridge | 189:f392fc9709a3 | 292 | |
| AnnaBridge | 189:f392fc9709a3 | 293 | #if defined (LCD_BASE) /* STM32L0x3xx only */ |
| AnnaBridge | 189:f392fc9709a3 | 294 | |
| AnnaBridge | 189:f392fc9709a3 | 295 | /** @brief Macro to configure the VLCD Decoupling capacitance connection. |
| AnnaBridge | 189:f392fc9709a3 | 296 | * |
| AnnaBridge | 189:f392fc9709a3 | 297 | * @param __SYSCFG_VLCD_CAPA__: specifies the decoupling of LCD capacitance for rails connection on GPIO. |
| AnnaBridge | 189:f392fc9709a3 | 298 | * This parameter can be a combination of following values (when available): |
| AnnaBridge | 189:f392fc9709a3 | 299 | * @arg SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2 |
| AnnaBridge | 189:f392fc9709a3 | 300 | * @arg SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 |
| AnnaBridge | 189:f392fc9709a3 | 301 | * @arg SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 |
| AnnaBridge | 189:f392fc9709a3 | 302 | * @arg SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 |
| AnnaBridge | 189:f392fc9709a3 | 303 | * @arg SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12 |
| AnnaBridge | 189:f392fc9709a3 | 304 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 305 | */ |
| AnnaBridge | 189:f392fc9709a3 | 306 | #define __HAL_SYSCFG_VLCD_CAPA_CONFIG(__SYSCFG_VLCD_CAPA__) \ |
| AnnaBridge | 189:f392fc9709a3 | 307 | MODIFY_REG(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA, (uint32_t)(__SYSCFG_VLCD_CAPA__)) |
| AnnaBridge | 189:f392fc9709a3 | 308 | |
| AnnaBridge | 189:f392fc9709a3 | 309 | /** |
| AnnaBridge | 189:f392fc9709a3 | 310 | * @brief Returns the decoupling of LCD capacitance configured by user. |
| AnnaBridge | 189:f392fc9709a3 | 311 | * @retval The LCD capacitance connection as configured by user. The returned can be a combination of : |
| AnnaBridge | 189:f392fc9709a3 | 312 | * SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2 |
| AnnaBridge | 189:f392fc9709a3 | 313 | * SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 |
| AnnaBridge | 189:f392fc9709a3 | 314 | * SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 |
| AnnaBridge | 189:f392fc9709a3 | 315 | * SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 |
| AnnaBridge | 189:f392fc9709a3 | 316 | * SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12 |
| AnnaBridge | 189:f392fc9709a3 | 317 | */ |
| AnnaBridge | 189:f392fc9709a3 | 318 | #define __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG() READ_BIT(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA) |
| AnnaBridge | 189:f392fc9709a3 | 319 | |
| AnnaBridge | 189:f392fc9709a3 | 320 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 321 | |
| AnnaBridge | 189:f392fc9709a3 | 322 | /** |
| AnnaBridge | 189:f392fc9709a3 | 323 | * @brief Returns the boot mode as configured by user. |
| AnnaBridge | 189:f392fc9709a3 | 324 | * @retval The boot mode as configured by user. The returned can be a value of : |
| AnnaBridge | 189:f392fc9709a3 | 325 | * - SYSCFG_BOOT_MAINFLASH |
| AnnaBridge | 189:f392fc9709a3 | 326 | * - SYSCFG_BOOT_SYSTEMFLASH |
| AnnaBridge | 189:f392fc9709a3 | 327 | * - SYSCFG_BOOT_SRAM |
| AnnaBridge | 189:f392fc9709a3 | 328 | */ |
| AnnaBridge | 189:f392fc9709a3 | 329 | #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE) |
| AnnaBridge | 189:f392fc9709a3 | 330 | |
| AnnaBridge | 189:f392fc9709a3 | 331 | |
| AnnaBridge | 189:f392fc9709a3 | 332 | /** @brief Check whether the specified SYSCFG flag is set or not. |
| AnnaBridge | 189:f392fc9709a3 | 333 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 189:f392fc9709a3 | 334 | * The only parameter supported is SYSCFG_FLAG_VREFINT_READY |
| AnnaBridge | 189:f392fc9709a3 | 335 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 189:f392fc9709a3 | 336 | */ |
| AnnaBridge | 189:f392fc9709a3 | 337 | #define __HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 189:f392fc9709a3 | 338 | |
| AnnaBridge | 189:f392fc9709a3 | 339 | /** @brief Fast mode Plus driving capability enable macro |
| AnnaBridge | 189:f392fc9709a3 | 340 | * @param __FASTMODEPLUS__: This parameter can be a value of : |
| AnnaBridge | 189:f392fc9709a3 | 341 | * @arg SYSCFG_FASTMODEPLUS_PB6 |
| AnnaBridge | 189:f392fc9709a3 | 342 | * @arg SYSCFG_FASTMODEPLUS_PB7 |
| AnnaBridge | 189:f392fc9709a3 | 343 | * @arg SYSCFG_FASTMODEPLUS_PB8 |
| AnnaBridge | 189:f392fc9709a3 | 344 | * @arg SYSCFG_FASTMODEPLUS_PB9 |
| AnnaBridge | 189:f392fc9709a3 | 345 | */ |
| AnnaBridge | 189:f392fc9709a3 | 346 | #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ |
| AnnaBridge | 189:f392fc9709a3 | 347 | SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \ |
| AnnaBridge | 189:f392fc9709a3 | 348 | }while(0) |
| AnnaBridge | 189:f392fc9709a3 | 349 | /** @brief Fast mode Plus driving capability disable macro |
| AnnaBridge | 189:f392fc9709a3 | 350 | * @param __FASTMODEPLUS__: This parameter can be a value of : |
| AnnaBridge | 189:f392fc9709a3 | 351 | * @arg SYSCFG_FASTMODEPLUS_PB6 |
| AnnaBridge | 189:f392fc9709a3 | 352 | * @arg SYSCFG_FASTMODEPLUS_PB7 |
| AnnaBridge | 189:f392fc9709a3 | 353 | * @arg SYSCFG_FASTMODEPLUS_PB8 |
| AnnaBridge | 189:f392fc9709a3 | 354 | * @arg SYSCFG_FASTMODEPLUS_PB9 |
| AnnaBridge | 189:f392fc9709a3 | 355 | */ |
| AnnaBridge | 189:f392fc9709a3 | 356 | #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ |
| AnnaBridge | 189:f392fc9709a3 | 357 | CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \ |
| AnnaBridge | 189:f392fc9709a3 | 358 | }while(0) |
| AnnaBridge | 189:f392fc9709a3 | 359 | |
| AnnaBridge | 189:f392fc9709a3 | 360 | |
| AnnaBridge | 189:f392fc9709a3 | 361 | /** |
| AnnaBridge | 189:f392fc9709a3 | 362 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 363 | */ |
| AnnaBridge | 189:f392fc9709a3 | 364 | |
| AnnaBridge | 189:f392fc9709a3 | 365 | /** @defgroup HAL_Exported_Functions HAL Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 366 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 367 | */ |
| AnnaBridge | 189:f392fc9709a3 | 368 | /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 189:f392fc9709a3 | 369 | * @brief Initialization and de-initialization functions |
| AnnaBridge | 189:f392fc9709a3 | 370 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 371 | */ |
| AnnaBridge | 189:f392fc9709a3 | 372 | HAL_StatusTypeDef HAL_Init(void); |
| AnnaBridge | 189:f392fc9709a3 | 373 | HAL_StatusTypeDef HAL_DeInit(void); |
| AnnaBridge | 189:f392fc9709a3 | 374 | void HAL_MspInit(void); |
| AnnaBridge | 189:f392fc9709a3 | 375 | void HAL_MspDeInit(void); |
| AnnaBridge | 189:f392fc9709a3 | 376 | HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
| AnnaBridge | 189:f392fc9709a3 | 377 | |
| AnnaBridge | 189:f392fc9709a3 | 378 | /** |
| AnnaBridge | 189:f392fc9709a3 | 379 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 380 | */ |
| AnnaBridge | 189:f392fc9709a3 | 381 | |
| AnnaBridge | 189:f392fc9709a3 | 382 | /** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions |
| AnnaBridge | 189:f392fc9709a3 | 383 | * @brief Peripheral Control functions |
| AnnaBridge | 189:f392fc9709a3 | 384 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 385 | */ |
| AnnaBridge | 189:f392fc9709a3 | 386 | void HAL_IncTick(void); |
| AnnaBridge | 189:f392fc9709a3 | 387 | void HAL_Delay(__IO uint32_t Delay); |
| AnnaBridge | 189:f392fc9709a3 | 388 | uint32_t HAL_GetTick(void); |
| AnnaBridge | 189:f392fc9709a3 | 389 | void HAL_SuspendTick(void); |
| AnnaBridge | 189:f392fc9709a3 | 390 | void HAL_ResumeTick(void); |
| AnnaBridge | 189:f392fc9709a3 | 391 | uint32_t HAL_GetHalVersion(void); |
| AnnaBridge | 189:f392fc9709a3 | 392 | uint32_t HAL_GetREVID(void); |
| AnnaBridge | 189:f392fc9709a3 | 393 | uint32_t HAL_GetDEVID(void); |
| AnnaBridge | 189:f392fc9709a3 | 394 | void HAL_DBGMCU_EnableDBGSleepMode(void); |
| AnnaBridge | 189:f392fc9709a3 | 395 | void HAL_DBGMCU_DisableDBGSleepMode(void); |
| AnnaBridge | 189:f392fc9709a3 | 396 | void HAL_DBGMCU_EnableDBGStopMode(void); |
| AnnaBridge | 189:f392fc9709a3 | 397 | void HAL_DBGMCU_DisableDBGStopMode(void); |
| AnnaBridge | 189:f392fc9709a3 | 398 | void HAL_DBGMCU_EnableDBGStandbyMode(void); |
| AnnaBridge | 189:f392fc9709a3 | 399 | void HAL_DBGMCU_DisableDBGStandbyMode(void); |
| AnnaBridge | 189:f392fc9709a3 | 400 | void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph); |
| AnnaBridge | 189:f392fc9709a3 | 401 | void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph); |
| AnnaBridge | 189:f392fc9709a3 | 402 | uint32_t HAL_SYSCFG_GetBootMode(void); |
| AnnaBridge | 189:f392fc9709a3 | 403 | void HAL_SYSCFG_Enable_Lock_VREFINT(void); |
| AnnaBridge | 189:f392fc9709a3 | 404 | void HAL_SYSCFG_Disable_Lock_VREFINT(void); |
| AnnaBridge | 189:f392fc9709a3 | 405 | void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT); |
| AnnaBridge | 189:f392fc9709a3 | 406 | |
| AnnaBridge | 189:f392fc9709a3 | 407 | /** |
| AnnaBridge | 189:f392fc9709a3 | 408 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 409 | */ |
| AnnaBridge | 189:f392fc9709a3 | 410 | /** |
| AnnaBridge | 189:f392fc9709a3 | 411 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 412 | */ |
| AnnaBridge | 189:f392fc9709a3 | 413 | |
| AnnaBridge | 189:f392fc9709a3 | 414 | /* Define the private group ***********************************/ |
| AnnaBridge | 189:f392fc9709a3 | 415 | /**************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 416 | /** @defgroup HAL_Private HAL Private |
| AnnaBridge | 189:f392fc9709a3 | 417 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 418 | */ |
| AnnaBridge | 189:f392fc9709a3 | 419 | /** |
| AnnaBridge | 189:f392fc9709a3 | 420 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 421 | */ |
| AnnaBridge | 189:f392fc9709a3 | 422 | /**************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 423 | |
| AnnaBridge | 189:f392fc9709a3 | 424 | |
| AnnaBridge | 189:f392fc9709a3 | 425 | /** |
| AnnaBridge | 189:f392fc9709a3 | 426 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 427 | */ |
| AnnaBridge | 189:f392fc9709a3 | 428 | |
| AnnaBridge | 189:f392fc9709a3 | 429 | /** |
| AnnaBridge | 189:f392fc9709a3 | 430 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 431 | */ |
| AnnaBridge | 189:f392fc9709a3 | 432 | |
| AnnaBridge | 189:f392fc9709a3 | 433 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 434 | } |
| AnnaBridge | 189:f392fc9709a3 | 435 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 436 | |
| AnnaBridge | 189:f392fc9709a3 | 437 | #endif /* __STM32L0xx_HAL_H */ |
| AnnaBridge | 189:f392fc9709a3 | 438 | |
| AnnaBridge | 189:f392fc9709a3 | 439 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| AnnaBridge | 189:f392fc9709a3 | 440 |
