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mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

cmsis/BUILD/mbed/TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/mpu_armv8.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

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AnnaBridge 189:f392fc9709a3 1 /******************************************************************************
AnnaBridge 189:f392fc9709a3 2 * @file mpu_armv8.h
AnnaBridge 189:f392fc9709a3 3 * @brief CMSIS MPU API for Armv8-M MPU
AnnaBridge 189:f392fc9709a3 4 * @version V5.0.4
AnnaBridge 189:f392fc9709a3 5 * @date 10. January 2018
AnnaBridge 189:f392fc9709a3 6 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 7 /*
AnnaBridge 189:f392fc9709a3 8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
AnnaBridge 189:f392fc9709a3 9 *
AnnaBridge 189:f392fc9709a3 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 189:f392fc9709a3 11 *
AnnaBridge 189:f392fc9709a3 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 189:f392fc9709a3 13 * not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 14 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 15 *
AnnaBridge 189:f392fc9709a3 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 17 *
AnnaBridge 189:f392fc9709a3 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 189:f392fc9709a3 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 21 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 22 * limitations under the License.
AnnaBridge 189:f392fc9709a3 23 */
AnnaBridge 189:f392fc9709a3 24
AnnaBridge 189:f392fc9709a3 25 #if defined ( __ICCARM__ )
AnnaBridge 189:f392fc9709a3 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 189:f392fc9709a3 27 #elif defined (__clang__)
AnnaBridge 189:f392fc9709a3 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 189:f392fc9709a3 29 #endif
AnnaBridge 189:f392fc9709a3 30
AnnaBridge 189:f392fc9709a3 31 #ifndef ARM_MPU_ARMV8_H
AnnaBridge 189:f392fc9709a3 32 #define ARM_MPU_ARMV8_H
AnnaBridge 189:f392fc9709a3 33
AnnaBridge 189:f392fc9709a3 34 /** \brief Attribute for device memory (outer only) */
AnnaBridge 189:f392fc9709a3 35 #define ARM_MPU_ATTR_DEVICE ( 0U )
AnnaBridge 189:f392fc9709a3 36
AnnaBridge 189:f392fc9709a3 37 /** \brief Attribute for non-cacheable, normal memory */
AnnaBridge 189:f392fc9709a3 38 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 /** \brief Attribute for normal memory (outer and inner)
AnnaBridge 189:f392fc9709a3 41 * \param NT Non-Transient: Set to 1 for non-transient data.
AnnaBridge 189:f392fc9709a3 42 * \param WB Write-Back: Set to 1 to use write-back update policy.
AnnaBridge 189:f392fc9709a3 43 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
AnnaBridge 189:f392fc9709a3 44 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
AnnaBridge 189:f392fc9709a3 45 */
AnnaBridge 189:f392fc9709a3 46 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
AnnaBridge 189:f392fc9709a3 47 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
AnnaBridge 189:f392fc9709a3 48
AnnaBridge 189:f392fc9709a3 49 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
AnnaBridge 189:f392fc9709a3 50 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
AnnaBridge 189:f392fc9709a3 51
AnnaBridge 189:f392fc9709a3 52 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
AnnaBridge 189:f392fc9709a3 53 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
AnnaBridge 189:f392fc9709a3 54
AnnaBridge 189:f392fc9709a3 55 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
AnnaBridge 189:f392fc9709a3 56 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
AnnaBridge 189:f392fc9709a3 57
AnnaBridge 189:f392fc9709a3 58 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
AnnaBridge 189:f392fc9709a3 59 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
AnnaBridge 189:f392fc9709a3 60
AnnaBridge 189:f392fc9709a3 61 /** \brief Memory Attribute
AnnaBridge 189:f392fc9709a3 62 * \param O Outer memory attributes
AnnaBridge 189:f392fc9709a3 63 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
AnnaBridge 189:f392fc9709a3 64 */
AnnaBridge 189:f392fc9709a3 65 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
AnnaBridge 189:f392fc9709a3 66
AnnaBridge 189:f392fc9709a3 67 /** \brief Normal memory non-shareable */
AnnaBridge 189:f392fc9709a3 68 #define ARM_MPU_SH_NON (0U)
AnnaBridge 189:f392fc9709a3 69
AnnaBridge 189:f392fc9709a3 70 /** \brief Normal memory outer shareable */
AnnaBridge 189:f392fc9709a3 71 #define ARM_MPU_SH_OUTER (2U)
AnnaBridge 189:f392fc9709a3 72
AnnaBridge 189:f392fc9709a3 73 /** \brief Normal memory inner shareable */
AnnaBridge 189:f392fc9709a3 74 #define ARM_MPU_SH_INNER (3U)
AnnaBridge 189:f392fc9709a3 75
AnnaBridge 189:f392fc9709a3 76 /** \brief Memory access permissions
AnnaBridge 189:f392fc9709a3 77 * \param RO Read-Only: Set to 1 for read-only memory.
AnnaBridge 189:f392fc9709a3 78 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
AnnaBridge 189:f392fc9709a3 79 */
AnnaBridge 189:f392fc9709a3 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
AnnaBridge 189:f392fc9709a3 81
AnnaBridge 189:f392fc9709a3 82 /** \brief Region Base Address Register value
AnnaBridge 189:f392fc9709a3 83 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
AnnaBridge 189:f392fc9709a3 84 * \param SH Defines the Shareability domain for this memory region.
AnnaBridge 189:f392fc9709a3 85 * \param RO Read-Only: Set to 1 for a read-only memory region.
AnnaBridge 189:f392fc9709a3 86 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
AnnaBridge 189:f392fc9709a3 87 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
AnnaBridge 189:f392fc9709a3 88 */
AnnaBridge 189:f392fc9709a3 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
AnnaBridge 189:f392fc9709a3 90 ((BASE & MPU_RBAR_BASE_Msk) | \
AnnaBridge 189:f392fc9709a3 91 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
AnnaBridge 189:f392fc9709a3 92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
AnnaBridge 189:f392fc9709a3 93 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
AnnaBridge 189:f392fc9709a3 94
AnnaBridge 189:f392fc9709a3 95 /** \brief Region Limit Address Register value
AnnaBridge 189:f392fc9709a3 96 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
AnnaBridge 189:f392fc9709a3 97 * \param IDX The attribute index to be associated with this memory region.
AnnaBridge 189:f392fc9709a3 98 */
AnnaBridge 189:f392fc9709a3 99 #define ARM_MPU_RLAR(LIMIT, IDX) \
AnnaBridge 189:f392fc9709a3 100 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
AnnaBridge 189:f392fc9709a3 101 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
AnnaBridge 189:f392fc9709a3 102 (MPU_RLAR_EN_Msk))
AnnaBridge 189:f392fc9709a3 103
AnnaBridge 189:f392fc9709a3 104 /**
AnnaBridge 189:f392fc9709a3 105 * Struct for a single MPU Region
AnnaBridge 189:f392fc9709a3 106 */
AnnaBridge 189:f392fc9709a3 107 typedef struct {
AnnaBridge 189:f392fc9709a3 108 uint32_t RBAR; /*!< Region Base Address Register value */
AnnaBridge 189:f392fc9709a3 109 uint32_t RLAR; /*!< Region Limit Address Register value */
AnnaBridge 189:f392fc9709a3 110 } ARM_MPU_Region_t;
AnnaBridge 189:f392fc9709a3 111
AnnaBridge 189:f392fc9709a3 112 /** Enable the MPU.
AnnaBridge 189:f392fc9709a3 113 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 189:f392fc9709a3 114 */
AnnaBridge 189:f392fc9709a3 115 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
AnnaBridge 189:f392fc9709a3 116 {
AnnaBridge 189:f392fc9709a3 117 __DSB();
AnnaBridge 189:f392fc9709a3 118 __ISB();
AnnaBridge 189:f392fc9709a3 119 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 189:f392fc9709a3 120 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 189:f392fc9709a3 121 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 189:f392fc9709a3 122 #endif
AnnaBridge 189:f392fc9709a3 123 }
AnnaBridge 189:f392fc9709a3 124
AnnaBridge 189:f392fc9709a3 125 /** Disable the MPU.
AnnaBridge 189:f392fc9709a3 126 */
AnnaBridge 189:f392fc9709a3 127 __STATIC_INLINE void ARM_MPU_Disable(void)
AnnaBridge 189:f392fc9709a3 128 {
AnnaBridge 189:f392fc9709a3 129 __DSB();
AnnaBridge 189:f392fc9709a3 130 __ISB();
AnnaBridge 189:f392fc9709a3 131 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 189:f392fc9709a3 132 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 189:f392fc9709a3 133 #endif
AnnaBridge 189:f392fc9709a3 134 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 189:f392fc9709a3 135 }
AnnaBridge 189:f392fc9709a3 136
AnnaBridge 189:f392fc9709a3 137 #ifdef MPU_NS
AnnaBridge 189:f392fc9709a3 138 /** Enable the Non-secure MPU.
AnnaBridge 189:f392fc9709a3 139 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 189:f392fc9709a3 140 */
AnnaBridge 189:f392fc9709a3 141 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
AnnaBridge 189:f392fc9709a3 142 {
AnnaBridge 189:f392fc9709a3 143 __DSB();
AnnaBridge 189:f392fc9709a3 144 __ISB();
AnnaBridge 189:f392fc9709a3 145 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 189:f392fc9709a3 146 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 189:f392fc9709a3 147 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 189:f392fc9709a3 148 #endif
AnnaBridge 189:f392fc9709a3 149 }
AnnaBridge 189:f392fc9709a3 150
AnnaBridge 189:f392fc9709a3 151 /** Disable the Non-secure MPU.
AnnaBridge 189:f392fc9709a3 152 */
AnnaBridge 189:f392fc9709a3 153 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
AnnaBridge 189:f392fc9709a3 154 {
AnnaBridge 189:f392fc9709a3 155 __DSB();
AnnaBridge 189:f392fc9709a3 156 __ISB();
AnnaBridge 189:f392fc9709a3 157 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 189:f392fc9709a3 158 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 189:f392fc9709a3 159 #endif
AnnaBridge 189:f392fc9709a3 160 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 189:f392fc9709a3 161 }
AnnaBridge 189:f392fc9709a3 162 #endif
AnnaBridge 189:f392fc9709a3 163
AnnaBridge 189:f392fc9709a3 164 /** Set the memory attribute encoding to the given MPU.
AnnaBridge 189:f392fc9709a3 165 * \param mpu Pointer to the MPU to be configured.
AnnaBridge 189:f392fc9709a3 166 * \param idx The attribute index to be set [0-7]
AnnaBridge 189:f392fc9709a3 167 * \param attr The attribute value to be set.
AnnaBridge 189:f392fc9709a3 168 */
AnnaBridge 189:f392fc9709a3 169 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
AnnaBridge 189:f392fc9709a3 170 {
AnnaBridge 189:f392fc9709a3 171 const uint8_t reg = idx / 4U;
AnnaBridge 189:f392fc9709a3 172 const uint32_t pos = ((idx % 4U) * 8U);
AnnaBridge 189:f392fc9709a3 173 const uint32_t mask = 0xFFU << pos;
AnnaBridge 189:f392fc9709a3 174
AnnaBridge 189:f392fc9709a3 175 if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
AnnaBridge 189:f392fc9709a3 176 return; // invalid index
AnnaBridge 189:f392fc9709a3 177 }
AnnaBridge 189:f392fc9709a3 178
AnnaBridge 189:f392fc9709a3 179 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
AnnaBridge 189:f392fc9709a3 180 }
AnnaBridge 189:f392fc9709a3 181
AnnaBridge 189:f392fc9709a3 182 /** Set the memory attribute encoding.
AnnaBridge 189:f392fc9709a3 183 * \param idx The attribute index to be set [0-7]
AnnaBridge 189:f392fc9709a3 184 * \param attr The attribute value to be set.
AnnaBridge 189:f392fc9709a3 185 */
AnnaBridge 189:f392fc9709a3 186 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
AnnaBridge 189:f392fc9709a3 187 {
AnnaBridge 189:f392fc9709a3 188 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
AnnaBridge 189:f392fc9709a3 189 }
AnnaBridge 189:f392fc9709a3 190
AnnaBridge 189:f392fc9709a3 191 #ifdef MPU_NS
AnnaBridge 189:f392fc9709a3 192 /** Set the memory attribute encoding to the Non-secure MPU.
AnnaBridge 189:f392fc9709a3 193 * \param idx The attribute index to be set [0-7]
AnnaBridge 189:f392fc9709a3 194 * \param attr The attribute value to be set.
AnnaBridge 189:f392fc9709a3 195 */
AnnaBridge 189:f392fc9709a3 196 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
AnnaBridge 189:f392fc9709a3 197 {
AnnaBridge 189:f392fc9709a3 198 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
AnnaBridge 189:f392fc9709a3 199 }
AnnaBridge 189:f392fc9709a3 200 #endif
AnnaBridge 189:f392fc9709a3 201
AnnaBridge 189:f392fc9709a3 202 /** Clear and disable the given MPU region of the given MPU.
AnnaBridge 189:f392fc9709a3 203 * \param mpu Pointer to MPU to be used.
AnnaBridge 189:f392fc9709a3 204 * \param rnr Region number to be cleared.
AnnaBridge 189:f392fc9709a3 205 */
AnnaBridge 189:f392fc9709a3 206 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
AnnaBridge 189:f392fc9709a3 207 {
AnnaBridge 189:f392fc9709a3 208 mpu->RNR = rnr;
AnnaBridge 189:f392fc9709a3 209 mpu->RLAR = 0U;
AnnaBridge 189:f392fc9709a3 210 }
AnnaBridge 189:f392fc9709a3 211
AnnaBridge 189:f392fc9709a3 212 /** Clear and disable the given MPU region.
AnnaBridge 189:f392fc9709a3 213 * \param rnr Region number to be cleared.
AnnaBridge 189:f392fc9709a3 214 */
AnnaBridge 189:f392fc9709a3 215 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
AnnaBridge 189:f392fc9709a3 216 {
AnnaBridge 189:f392fc9709a3 217 ARM_MPU_ClrRegionEx(MPU, rnr);
AnnaBridge 189:f392fc9709a3 218 }
AnnaBridge 189:f392fc9709a3 219
AnnaBridge 189:f392fc9709a3 220 #ifdef MPU_NS
AnnaBridge 189:f392fc9709a3 221 /** Clear and disable the given Non-secure MPU region.
AnnaBridge 189:f392fc9709a3 222 * \param rnr Region number to be cleared.
AnnaBridge 189:f392fc9709a3 223 */
AnnaBridge 189:f392fc9709a3 224 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
AnnaBridge 189:f392fc9709a3 225 {
AnnaBridge 189:f392fc9709a3 226 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
AnnaBridge 189:f392fc9709a3 227 }
AnnaBridge 189:f392fc9709a3 228 #endif
AnnaBridge 189:f392fc9709a3 229
AnnaBridge 189:f392fc9709a3 230 /** Configure the given MPU region of the given MPU.
AnnaBridge 189:f392fc9709a3 231 * \param mpu Pointer to MPU to be used.
AnnaBridge 189:f392fc9709a3 232 * \param rnr Region number to be configured.
AnnaBridge 189:f392fc9709a3 233 * \param rbar Value for RBAR register.
AnnaBridge 189:f392fc9709a3 234 * \param rlar Value for RLAR register.
AnnaBridge 189:f392fc9709a3 235 */
AnnaBridge 189:f392fc9709a3 236 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 189:f392fc9709a3 237 {
AnnaBridge 189:f392fc9709a3 238 mpu->RNR = rnr;
AnnaBridge 189:f392fc9709a3 239 mpu->RBAR = rbar;
AnnaBridge 189:f392fc9709a3 240 mpu->RLAR = rlar;
AnnaBridge 189:f392fc9709a3 241 }
AnnaBridge 189:f392fc9709a3 242
AnnaBridge 189:f392fc9709a3 243 /** Configure the given MPU region.
AnnaBridge 189:f392fc9709a3 244 * \param rnr Region number to be configured.
AnnaBridge 189:f392fc9709a3 245 * \param rbar Value for RBAR register.
AnnaBridge 189:f392fc9709a3 246 * \param rlar Value for RLAR register.
AnnaBridge 189:f392fc9709a3 247 */
AnnaBridge 189:f392fc9709a3 248 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 189:f392fc9709a3 249 {
AnnaBridge 189:f392fc9709a3 250 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
AnnaBridge 189:f392fc9709a3 251 }
AnnaBridge 189:f392fc9709a3 252
AnnaBridge 189:f392fc9709a3 253 #ifdef MPU_NS
AnnaBridge 189:f392fc9709a3 254 /** Configure the given Non-secure MPU region.
AnnaBridge 189:f392fc9709a3 255 * \param rnr Region number to be configured.
AnnaBridge 189:f392fc9709a3 256 * \param rbar Value for RBAR register.
AnnaBridge 189:f392fc9709a3 257 * \param rlar Value for RLAR register.
AnnaBridge 189:f392fc9709a3 258 */
AnnaBridge 189:f392fc9709a3 259 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 189:f392fc9709a3 260 {
AnnaBridge 189:f392fc9709a3 261 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
AnnaBridge 189:f392fc9709a3 262 }
AnnaBridge 189:f392fc9709a3 263 #endif
AnnaBridge 189:f392fc9709a3 264
AnnaBridge 189:f392fc9709a3 265 /** Memcopy with strictly ordered memory access, e.g. for register targets.
AnnaBridge 189:f392fc9709a3 266 * \param dst Destination data is copied to.
AnnaBridge 189:f392fc9709a3 267 * \param src Source data is copied from.
AnnaBridge 189:f392fc9709a3 268 * \param len Amount of data words to be copied.
AnnaBridge 189:f392fc9709a3 269 */
AnnaBridge 189:f392fc9709a3 270 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
AnnaBridge 189:f392fc9709a3 271 {
AnnaBridge 189:f392fc9709a3 272 uint32_t i;
AnnaBridge 189:f392fc9709a3 273 for (i = 0U; i < len; ++i)
AnnaBridge 189:f392fc9709a3 274 {
AnnaBridge 189:f392fc9709a3 275 dst[i] = src[i];
AnnaBridge 189:f392fc9709a3 276 }
AnnaBridge 189:f392fc9709a3 277 }
AnnaBridge 189:f392fc9709a3 278
AnnaBridge 189:f392fc9709a3 279 /** Load the given number of MPU regions from a table to the given MPU.
AnnaBridge 189:f392fc9709a3 280 * \param mpu Pointer to the MPU registers to be used.
AnnaBridge 189:f392fc9709a3 281 * \param rnr First region number to be configured.
AnnaBridge 189:f392fc9709a3 282 * \param table Pointer to the MPU configuration table.
AnnaBridge 189:f392fc9709a3 283 * \param cnt Amount of regions to be configured.
AnnaBridge 189:f392fc9709a3 284 */
AnnaBridge 189:f392fc9709a3 285 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 189:f392fc9709a3 286 {
AnnaBridge 189:f392fc9709a3 287 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
AnnaBridge 189:f392fc9709a3 288 if (cnt == 1U) {
AnnaBridge 189:f392fc9709a3 289 mpu->RNR = rnr;
AnnaBridge 189:f392fc9709a3 290 orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
AnnaBridge 189:f392fc9709a3 291 } else {
AnnaBridge 189:f392fc9709a3 292 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
AnnaBridge 189:f392fc9709a3 293 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
AnnaBridge 189:f392fc9709a3 294
AnnaBridge 189:f392fc9709a3 295 mpu->RNR = rnrBase;
AnnaBridge 189:f392fc9709a3 296 while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
AnnaBridge 189:f392fc9709a3 297 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
AnnaBridge 189:f392fc9709a3 298 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
AnnaBridge 189:f392fc9709a3 299 table += c;
AnnaBridge 189:f392fc9709a3 300 cnt -= c;
AnnaBridge 189:f392fc9709a3 301 rnrOffset = 0U;
AnnaBridge 189:f392fc9709a3 302 rnrBase += MPU_TYPE_RALIASES;
AnnaBridge 189:f392fc9709a3 303 mpu->RNR = rnrBase;
AnnaBridge 189:f392fc9709a3 304 }
AnnaBridge 189:f392fc9709a3 305
AnnaBridge 189:f392fc9709a3 306 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
AnnaBridge 189:f392fc9709a3 307 }
AnnaBridge 189:f392fc9709a3 308 }
AnnaBridge 189:f392fc9709a3 309
AnnaBridge 189:f392fc9709a3 310 /** Load the given number of MPU regions from a table.
AnnaBridge 189:f392fc9709a3 311 * \param rnr First region number to be configured.
AnnaBridge 189:f392fc9709a3 312 * \param table Pointer to the MPU configuration table.
AnnaBridge 189:f392fc9709a3 313 * \param cnt Amount of regions to be configured.
AnnaBridge 189:f392fc9709a3 314 */
AnnaBridge 189:f392fc9709a3 315 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 189:f392fc9709a3 316 {
AnnaBridge 189:f392fc9709a3 317 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
AnnaBridge 189:f392fc9709a3 318 }
AnnaBridge 189:f392fc9709a3 319
AnnaBridge 189:f392fc9709a3 320 #ifdef MPU_NS
AnnaBridge 189:f392fc9709a3 321 /** Load the given number of MPU regions from a table to the Non-secure MPU.
AnnaBridge 189:f392fc9709a3 322 * \param rnr First region number to be configured.
AnnaBridge 189:f392fc9709a3 323 * \param table Pointer to the MPU configuration table.
AnnaBridge 189:f392fc9709a3 324 * \param cnt Amount of regions to be configured.
AnnaBridge 189:f392fc9709a3 325 */
AnnaBridge 189:f392fc9709a3 326 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 189:f392fc9709a3 327 {
AnnaBridge 189:f392fc9709a3 328 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
AnnaBridge 189:f392fc9709a3 329 }
AnnaBridge 189:f392fc9709a3 330 #endif
AnnaBridge 189:f392fc9709a3 331
AnnaBridge 189:f392fc9709a3 332 #endif
AnnaBridge 189:f392fc9709a3 333