mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_adc_ex.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_adc_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.1
<> 144:ef7eb2e8f9f7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the Analog to Digital Convertor (ADC)
<> 144:ef7eb2e8f9f7 9 * peripheral:
<> 144:ef7eb2e8f9f7 10 * + Calibration functions
<> 144:ef7eb2e8f9f7 11 * ++ Calibration start-up
<> 144:ef7eb2e8f9f7 12 * ++ Calibration value reading or setting
<> 144:ef7eb2e8f9f7 13 * + Operation functions
<> 144:ef7eb2e8f9f7 14 * ++ Start, stop, get result of conversions of injected
<> 144:ef7eb2e8f9f7 15 * groups, using 3 possible modes: polling or interruption.
<> 144:ef7eb2e8f9f7 16 * ++ Multimode feature when available
<> 144:ef7eb2e8f9f7 17 * + Control functions
<> 144:ef7eb2e8f9f7 18 * ++ Configure channels on injected group
<> 144:ef7eb2e8f9f7 19 * + State functions
<> 144:ef7eb2e8f9f7 20 * ++ Injected group queues management
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 @verbatim
<> 144:ef7eb2e8f9f7 23 ==============================================================================
<> 144:ef7eb2e8f9f7 24 ##### ADC specific features #####
<> 144:ef7eb2e8f9f7 25 ==============================================================================
<> 144:ef7eb2e8f9f7 26 [..]
<> 144:ef7eb2e8f9f7 27 (#) Interrupt generation at the end of injected conversion and in case of
<> 144:ef7eb2e8f9f7 28 injected queues overflow.
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 (#) External trigger (timer or EXTI) with configurable polarity for
<> 144:ef7eb2e8f9f7 31 injected groups.
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 (#) Multimode Dual mode when multimode feature is available.
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 (#) Configurable DMA data storage in Multimode Dual mode.
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 (#) Configurable delay between conversions in Dual interleaved mode.
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 (#) ADC calibration.
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) ADC channels selectable single/differential input.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 (#) ADC Injected sequencer&channels configuration context queue.
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 (#) ADC offset on injected groups.
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 (#) ADC oversampling.
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 51 ==============================================================================
<> 144:ef7eb2e8f9f7 52 [..]
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 (#) Configure the ADC parameters (conversion resolution, data alignment,
<> 144:ef7eb2e8f9f7 55 continuous mode, ...) using the HAL_ADC_Init() function.
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 (#) Activate the ADC peripheral using one of the start functions:
<> 144:ef7eb2e8f9f7 58 HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() for injected conversions
<> 144:ef7eb2e8f9f7 59 or
<> 144:ef7eb2e8f9f7 60 HAL_ADC_MultiModeStart_DMA() for multimode conversions when multimode
<> 144:ef7eb2e8f9f7 61 feature is available.
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 *** Channels to injected group configuration ***
<> 144:ef7eb2e8f9f7 65 =============================================
<> 144:ef7eb2e8f9f7 66 [..]
<> 144:ef7eb2e8f9f7 67 (+) To configure the ADC Injected channels group features, use
<> 144:ef7eb2e8f9f7 68 HAL_ADCEx_InjectedConfigChannel() functions.
<> 144:ef7eb2e8f9f7 69 (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue()
<> 144:ef7eb2e8f9f7 70 function.
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 *** Multimode ADCs configuration (when multimode feature is available) ***
<> 144:ef7eb2e8f9f7 74 ========================================================================
<> 144:ef7eb2e8f9f7 75 [..]
<> 144:ef7eb2e8f9f7 76 (+) Multimode feature is available and applicable to Master and
<> 144:ef7eb2e8f9f7 77 Slave ADCs.
<> 144:ef7eb2e8f9f7 78 (+) Refer to "Channels to regular group configuration" description to
<> 144:ef7eb2e8f9f7 79 configure the Master and Slave regular groups.
<> 144:ef7eb2e8f9f7 80 (+) Select the Multi mode ADC features (dual mode
<> 144:ef7eb2e8f9f7 81 simultaneous, interleaved, ...) and configure the DMA mode using
<> 144:ef7eb2e8f9f7 82 HAL_ADCEx_MultiModeConfigChannel() functions.
<> 144:ef7eb2e8f9f7 83 (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue()
<> 144:ef7eb2e8f9f7 84 function.
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 @endverbatim
<> 144:ef7eb2e8f9f7 88 ******************************************************************************
<> 144:ef7eb2e8f9f7 89 * @attention
<> 144:ef7eb2e8f9f7 90 *
<> 144:ef7eb2e8f9f7 91 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 92 *
<> 144:ef7eb2e8f9f7 93 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 94 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 95 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 96 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 97 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 98 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 99 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 100 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 101 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 102 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 103 *
<> 144:ef7eb2e8f9f7 104 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 105 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 106 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 107 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 108 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 109 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 110 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 111 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 112 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 113 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 114 *
<> 144:ef7eb2e8f9f7 115 ******************************************************************************
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 122 * @{
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /** @defgroup ADCEx ADCEx
<> 144:ef7eb2e8f9f7 126 * @brief ADC Extended HAL module driver
<> 144:ef7eb2e8f9f7 127 * @{
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 #ifdef HAL_ADC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 133 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 #define ADC_JSQR_FIELDS ((uint32_t)(ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
<> 144:ef7eb2e8f9f7 140 ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
<> 144:ef7eb2e8f9f7 141 ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
<> 144:ef7eb2e8f9f7 142 once the ADC is enabled */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 #define ADC_CFGR2_INJ_FIELDS ((uint32_t)(ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR |\
<> 144:ef7eb2e8f9f7 145 ADC_CFGR2_OVSS )) /*!< ADC_CFGR2 injected oversampling parameters that can be updated
<> 144:ef7eb2e8f9f7 146 when no conversion is on-going (neither regular nor injected) */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Fixed timeout value for ADC calibration. */
<> 144:ef7eb2e8f9f7 149 /* Values defined to be higher than worst cases: low clock frequency, */
<> 144:ef7eb2e8f9f7 150 /* maximum prescalers. */
<> 144:ef7eb2e8f9f7 151 /* Ex of profile low frequency : f_ADC at 0.14 MHz (minimum value */
<> 144:ef7eb2e8f9f7 152 /* according to Data sheet), calibration_time MAX = 112 / f_ADC */
<> 144:ef7eb2e8f9f7 153 /* 112 / 140,000 = 0.8 ms */
<> 144:ef7eb2e8f9f7 154 /* At maximum CPU speed (80 MHz), this means */
<> 144:ef7eb2e8f9f7 155 /* 0.8 ms * 80 MHz = 64000 CPU cycles */
<> 144:ef7eb2e8f9f7 156 #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 64000) /*!< ADC calibration time-out value */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /**
<> 144:ef7eb2e8f9f7 159 * @}
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 163 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 164 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 165 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
<> 144:ef7eb2e8f9f7 168 * @{
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
<> 144:ef7eb2e8f9f7 174 * @brief Extended IO operation functions
<> 144:ef7eb2e8f9f7 175 *
<> 144:ef7eb2e8f9f7 176 @verbatim
<> 144:ef7eb2e8f9f7 177 ===============================================================================
<> 144:ef7eb2e8f9f7 178 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 179 ===============================================================================
<> 144:ef7eb2e8f9f7 180 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 (+) Perform the ADC self-calibration for single or differential ending.
<> 144:ef7eb2e8f9f7 183 (+) Get calibration factors for single or differential ending.
<> 144:ef7eb2e8f9f7 184 (+) Set calibration factors for single or differential ending.
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 (+) Start conversion of injected group.
<> 144:ef7eb2e8f9f7 187 (+) Stop conversion of injected group.
<> 144:ef7eb2e8f9f7 188 (+) Poll for conversion complete on injected group.
<> 144:ef7eb2e8f9f7 189 (+) Get result of injected channel conversion.
<> 144:ef7eb2e8f9f7 190 (+) Start conversion of injected group and enable interruptions.
<> 144:ef7eb2e8f9f7 191 (+) Stop conversion of injected group and disable interruptions.
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 (+) When multimode feature is available, start multimode and enable DMA transfer.
<> 144:ef7eb2e8f9f7 194 (+) Stop multimode and disable ADC DMA transfer.
<> 144:ef7eb2e8f9f7 195 (+) Get result of multimode conversion.
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 @endverbatim
<> 144:ef7eb2e8f9f7 200 * @{
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /**
<> 144:ef7eb2e8f9f7 206 * @brief Perform an ADC automatic self-calibration
<> 144:ef7eb2e8f9f7 207 * Calibration prerequisite: ADC must be disabled (execute this
<> 144:ef7eb2e8f9f7 208 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
<> 144:ef7eb2e8f9f7 209 * @param hadc: ADC handle.
<> 144:ef7eb2e8f9f7 210 * @param SingleDiff: Selection of single-ended or differential input
<> 144:ef7eb2e8f9f7 211 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 212 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
<> 144:ef7eb2e8f9f7 213 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
<> 144:ef7eb2e8f9f7 214 * @retval HAL status
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
<> 144:ef7eb2e8f9f7 217 {
<> 144:ef7eb2e8f9f7 218 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 219 uint32_t WaitLoopIndex = 0;
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* Check the parameters */
<> 144:ef7eb2e8f9f7 222 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 223 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /* Process locked */
<> 144:ef7eb2e8f9f7 226 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Calibration prerequisite: ADC must be disabled. */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /* Disable the ADC (if not already disabled) */
<> 144:ef7eb2e8f9f7 231 tmp_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 234 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 /* Change ADC state */
<> 144:ef7eb2e8f9f7 237 /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_BUSY_INTERNAL bit */
<> 144:ef7eb2e8f9f7 238 ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_BUSY_INTERNAL);
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Select calibration mode single ended or differential ended */
<> 144:ef7eb2e8f9f7 241 MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALDIF, SingleDiff);
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /* Start ADC calibration */
<> 144:ef7eb2e8f9f7 244 SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL);
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /* Wait for calibration completion */
<> 144:ef7eb2e8f9f7 248 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
<> 144:ef7eb2e8f9f7 249 {
<> 144:ef7eb2e8f9f7 250 WaitLoopIndex++;
<> 144:ef7eb2e8f9f7 251 if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT)
<> 144:ef7eb2e8f9f7 252 {
<> 144:ef7eb2e8f9f7 253 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 254 /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_ERROR_INTERNAL bit */
<> 144:ef7eb2e8f9f7 255 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Process unlocked */
<> 144:ef7eb2e8f9f7 258 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
<> 144:ef7eb2e8f9f7 265 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267 else
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 272 tmp_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Process unlocked */
<> 144:ef7eb2e8f9f7 277 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Return function status */
<> 144:ef7eb2e8f9f7 280 return tmp_status;
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /**
<> 144:ef7eb2e8f9f7 287 * @brief Get the calibration factor from automatic conversion result.
<> 144:ef7eb2e8f9f7 288 * @param hadc: ADC handle.
<> 144:ef7eb2e8f9f7 289 * @param SingleDiff: Selection of single-ended or differential input
<> 144:ef7eb2e8f9f7 290 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 291 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
<> 144:ef7eb2e8f9f7 292 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
<> 144:ef7eb2e8f9f7 293 * @retval Converted value
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 /* Check the parameters */
<> 144:ef7eb2e8f9f7 298 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 299 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Return the selected ADC calibration value */
<> 144:ef7eb2e8f9f7 302 if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306 else
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @brief Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
<> 144:ef7eb2e8f9f7 316 * @param hadc: ADC handle.
<> 144:ef7eb2e8f9f7 317 * @param SingleDiff: Selection of single-ended or differential input.
<> 144:ef7eb2e8f9f7 318 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 319 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
<> 144:ef7eb2e8f9f7 320 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
<> 144:ef7eb2e8f9f7 321 * @param CalibrationFactor: Calibration factor (coded on 7 bits maximum)
<> 144:ef7eb2e8f9f7 322 * @retval HAL state
<> 144:ef7eb2e8f9f7 323 */
<> 144:ef7eb2e8f9f7 324 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* Check the parameters */
<> 144:ef7eb2e8f9f7 329 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 330 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
<> 144:ef7eb2e8f9f7 331 assert_param(IS_ADC_CALFACT(CalibrationFactor));
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Process locked */
<> 144:ef7eb2e8f9f7 334 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Verification of hardware constraints before modifying the calibration */
<> 144:ef7eb2e8f9f7 337 /* factors register: ADC must be enabled, no conversion on going. */
<> 144:ef7eb2e8f9f7 338 if ( (ADC_IS_ENABLE(hadc) != RESET) &&
<> 144:ef7eb2e8f9f7 339 (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) )
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 /* Set the selected ADC calibration value */
<> 144:ef7eb2e8f9f7 342 if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
<> 144:ef7eb2e8f9f7 343 {
<> 144:ef7eb2e8f9f7 344 MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D, ADC_CALFACT_DIFF_SET(CalibrationFactor));
<> 144:ef7eb2e8f9f7 345 }
<> 144:ef7eb2e8f9f7 346 else
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_S, CalibrationFactor);
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350 }
<> 144:ef7eb2e8f9f7 351 else
<> 144:ef7eb2e8f9f7 352 {
<> 144:ef7eb2e8f9f7 353 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 354 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 357 tmp_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 358 }
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* Process unlocked */
<> 144:ef7eb2e8f9f7 361 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Return function status */
<> 144:ef7eb2e8f9f7 364 return tmp_status;
<> 144:ef7eb2e8f9f7 365 }
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /**
<> 144:ef7eb2e8f9f7 370 * @brief Enable ADC, start conversion of injected group.
<> 144:ef7eb2e8f9f7 371 * @note Interruptions enabled in this function: None.
<> 144:ef7eb2e8f9f7 372 * @note Case of multimode enabled when multimode feature is available:
<> 144:ef7eb2e8f9f7 373 * HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
<> 144:ef7eb2e8f9f7 374 * then for ADC master.
<> 144:ef7eb2e8f9f7 375 * For ADC slave, ADC is enabled only (conversion is not started).
<> 144:ef7eb2e8f9f7 376 * For ADC master, ADC is enabled and multimode conversion is started.
<> 144:ef7eb2e8f9f7 377 * @param hadc: ADC handle.
<> 144:ef7eb2e8f9f7 378 * @retval HAL status
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 381 {
<> 144:ef7eb2e8f9f7 382 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /* Check the parameters */
<> 144:ef7eb2e8f9f7 385 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 390 }
<> 144:ef7eb2e8f9f7 391 else
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /* In case of software trigger detection enabled, JQDIS must be set
<> 144:ef7eb2e8f9f7 395 (which can be done only if ADSTART and JADSTART are both cleared).
<> 144:ef7eb2e8f9f7 396 If JQDIS is not set at that point, returns an error
<> 144:ef7eb2e8f9f7 397 - since software trigger detection is disabled. User needs to
<> 144:ef7eb2e8f9f7 398 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
<> 144:ef7eb2e8f9f7 399 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
<> 144:ef7eb2e8f9f7 400 the queue is empty */
<> 144:ef7eb2e8f9f7 401 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)
<> 144:ef7eb2e8f9f7 402 && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 405 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Process locked */
<> 144:ef7eb2e8f9f7 410 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 413 tmp_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 416 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 417 {
<> 144:ef7eb2e8f9f7 418 /* Check if a regular conversion is ongoing */
<> 144:ef7eb2e8f9f7 419 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 420 {
<> 144:ef7eb2e8f9f7 421 /* Reset ADC error code field related to injected conversions only */
<> 144:ef7eb2e8f9f7 422 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424 else
<> 144:ef7eb2e8f9f7 425 {
<> 144:ef7eb2e8f9f7 426 /* Set ADC error code to none */
<> 144:ef7eb2e8f9f7 427 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429 /* Update ADC state */
<> 144:ef7eb2e8f9f7 430 /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
<> 144:ef7eb2e8f9f7 431 ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
<> 144:ef7eb2e8f9f7 434 - by default if ADC is Master or Independent or if multimode feature is not available
<> 144:ef7eb2e8f9f7 435 - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
<> 144:ef7eb2e8f9f7 436 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 437 {
<> 144:ef7eb2e8f9f7 438 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 443 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 444 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Enable conversion of injected group, if automatic injected conversion */
<> 144:ef7eb2e8f9f7 447 /* is disabled. */
<> 144:ef7eb2e8f9f7 448 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 449 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 450 /* trigger event. */
<> 144:ef7eb2e8f9f7 451 /* Case of multimode enabled (when multimode feature is available): */
<> 144:ef7eb2e8f9f7 452 /* if ADC is slave, */
<> 144:ef7eb2e8f9f7 453 /* - ADC is enabled only (conversion is not started). */
<> 144:ef7eb2e8f9f7 454 /* - if multimode only concerns regular conversion, ADC is enabled */
<> 144:ef7eb2e8f9f7 455 /* and conversion is started. */
<> 144:ef7eb2e8f9f7 456 /* If ADC is master or independent, */
<> 144:ef7eb2e8f9f7 457 /* - ADC is enabled and conversion is started. */
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /* Are injected conversions that of a dual Slave ? */
<> 144:ef7eb2e8f9f7 460 if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
<> 144:ef7eb2e8f9f7 461 {
<> 144:ef7eb2e8f9f7 462 /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
<> 144:ef7eb2e8f9f7 463 set ADSTART only if JAUTO is cleared */
<> 144:ef7eb2e8f9f7 464 /* Process unlocked */
<> 144:ef7eb2e8f9f7 465 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 466 if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
<> 144:ef7eb2e8f9f7 467 {
<> 144:ef7eb2e8f9f7 468 SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
<> 144:ef7eb2e8f9f7 469 }
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471 else
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
<> 144:ef7eb2e8f9f7 474 ADSTART is not set */
<> 144:ef7eb2e8f9f7 475 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 476 /* Process unlocked */
<> 144:ef7eb2e8f9f7 477 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 478 }
<> 144:ef7eb2e8f9f7 479 }
<> 144:ef7eb2e8f9f7 480 else
<> 144:ef7eb2e8f9f7 481 {
<> 144:ef7eb2e8f9f7 482 /* Process unlocked */
<> 144:ef7eb2e8f9f7 483 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 484 } /* if (tmp_status == HAL_OK) */
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* Return function status */
<> 144:ef7eb2e8f9f7 488 return tmp_status;
<> 144:ef7eb2e8f9f7 489 } /* if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) */
<> 144:ef7eb2e8f9f7 490 }
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /**
<> 144:ef7eb2e8f9f7 495 * @brief Stop conversion of injected channels, disable ADC peripheral if no regular conversion is on going.
<> 144:ef7eb2e8f9f7 496 * @note If ADC must be disabled and if regular conversion
<> 144:ef7eb2e8f9f7 497 * is on going, function HAL_ADC_Stop() must be used.
<> 144:ef7eb2e8f9f7 498 * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
<> 144:ef7eb2e8f9f7 499 * @note In case of multimode enabled (when multimode feature is available),
<> 144:ef7eb2e8f9f7 500 * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
<> 144:ef7eb2e8f9f7 501 * For ADC master, conversion is stopped and ADC is disabled.
<> 144:ef7eb2e8f9f7 502 * For ADC slave, ADC is disabled only (conversion stop of ADC master
<> 144:ef7eb2e8f9f7 503 * has already stopped conversion of ADC slave).
<> 144:ef7eb2e8f9f7 504 * @param hadc: ADC handle.
<> 144:ef7eb2e8f9f7 505 * @retval None
<> 144:ef7eb2e8f9f7 506 */
<> 144:ef7eb2e8f9f7 507 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 508 {
<> 144:ef7eb2e8f9f7 509 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /* Check the parameters */
<> 144:ef7eb2e8f9f7 512 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Process locked */
<> 144:ef7eb2e8f9f7 515 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /* 1. Stop potential conversion on going on injected group only. */
<> 144:ef7eb2e8f9f7 518 tmp_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /* Disable ADC peripheral if injected conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 521 /* and if no conversion on regular group is on-going */
<> 144:ef7eb2e8f9f7 522 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 523 {
<> 144:ef7eb2e8f9f7 524 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 525 {
<> 144:ef7eb2e8f9f7 526 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 527 tmp_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 530 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 /* Change ADC state */
<> 144:ef7eb2e8f9f7 533 /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
<> 144:ef7eb2e8f9f7 534 ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 535 }
<> 144:ef7eb2e8f9f7 536 }
<> 144:ef7eb2e8f9f7 537 /* Conversion on injected group is stopped, but ADC not disabled since */
<> 144:ef7eb2e8f9f7 538 /* conversion on regular group is still running. */
<> 144:ef7eb2e8f9f7 539 else
<> 144:ef7eb2e8f9f7 540 {
<> 144:ef7eb2e8f9f7 541 /* Clear HAL_ADC_STATE_INJ_BUSY bit */
<> 144:ef7eb2e8f9f7 542 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 543 }
<> 144:ef7eb2e8f9f7 544 }
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /* Process unlocked */
<> 144:ef7eb2e8f9f7 547 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /* Return function status */
<> 144:ef7eb2e8f9f7 550 return tmp_status;
<> 144:ef7eb2e8f9f7 551 }
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /**
<> 144:ef7eb2e8f9f7 556 * @brief Wait for injected group conversion to be completed.
<> 144:ef7eb2e8f9f7 557 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 558 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 559 * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
<> 144:ef7eb2e8f9f7 560 * checked and cleared depending on AUTDLY bit status.
<> 144:ef7eb2e8f9f7 561 * @retval HAL status
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 566 uint32_t tmp_Flag_End = 0x00;
<> 144:ef7eb2e8f9f7 567 ADC_TypeDef *tmpADC_Master;
<> 144:ef7eb2e8f9f7 568 uint32_t tmp_cfgr = 0x00;
<> 144:ef7eb2e8f9f7 569 uint32_t tmp_cfgr_jqm_autdly = 0x00;
<> 144:ef7eb2e8f9f7 570 uint32_t tmp_jeos_raised = 0x01; /* by default, assume that JEOS is set,
<> 144:ef7eb2e8f9f7 571 tmp_jeos_raised will be corrected
<> 144:ef7eb2e8f9f7 572 accordingly during API execution */
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /* Check the parameters */
<> 144:ef7eb2e8f9f7 575 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* If end of sequence selected */
<> 144:ef7eb2e8f9f7 578 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 tmp_Flag_End = ADC_FLAG_JEOS;
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582 else /* end of conversion selected */
<> 144:ef7eb2e8f9f7 583 {
<> 144:ef7eb2e8f9f7 584 tmp_Flag_End = ADC_FLAG_JEOC;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /* Get timeout */
<> 144:ef7eb2e8f9f7 588 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 /* Wait until End of Conversion or Sequence flag is raised */
<> 144:ef7eb2e8f9f7 591 while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
<> 144:ef7eb2e8f9f7 592 {
<> 144:ef7eb2e8f9f7 593 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 594 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 595 {
<> 144:ef7eb2e8f9f7 596 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 597 {
<> 144:ef7eb2e8f9f7 598 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 599 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Process unlocked */
<> 144:ef7eb2e8f9f7 602 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606 }
<> 144:ef7eb2e8f9f7 607 }
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Next, to clear the polled flag as well as to update the handle State,
<> 144:ef7eb2e8f9f7 610 JEOS is checked and the relevant configuration registers are retrieved.
<> 144:ef7eb2e8f9f7 611 JQM, JAUTO and CONT bits will have to be read for the State update,
<> 144:ef7eb2e8f9f7 612 AUTDLY for JEOS clearing. */
<> 144:ef7eb2e8f9f7 613 /* 1. Check whether or not JEOS is set */
<> 144:ef7eb2e8f9f7 614 if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_JEOS))
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 tmp_jeos_raised = 0;
<> 144:ef7eb2e8f9f7 617 }
<> 144:ef7eb2e8f9f7 618 /* 2. Check whether or not hadc is the handle of a Slave ADC with dual
<> 144:ef7eb2e8f9f7 619 injected conversions enabled. */
<> 144:ef7eb2e8f9f7 620 if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 621 {
<> 144:ef7eb2e8f9f7 622 /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
<> 144:ef7eb2e8f9f7 623 check JQM and AUTDLY bits directly in ADC CFGR register */
<> 144:ef7eb2e8f9f7 624 tmp_cfgr_jqm_autdly = READ_REG(hadc->Instance->CFGR);
<> 144:ef7eb2e8f9f7 625 }
<> 144:ef7eb2e8f9f7 626 else
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
<> 144:ef7eb2e8f9f7 629 need to check JQM and AUTDLY bits of Master ADC CFGR register */
<> 144:ef7eb2e8f9f7 630 tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 631 tmp_cfgr_jqm_autdly = READ_REG(tmpADC_Master->CFGR);
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633 /* 3. Check whether or not hadc is the handle of a Slave ADC with dual
<> 144:ef7eb2e8f9f7 634 regular conversions enabled. */
<> 144:ef7eb2e8f9f7 635 if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
<> 144:ef7eb2e8f9f7 636 {
<> 144:ef7eb2e8f9f7 637 /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
<> 144:ef7eb2e8f9f7 638 check JAUTO and CONT bits directly in ADC CFGR register */
<> 144:ef7eb2e8f9f7 639 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
<> 144:ef7eb2e8f9f7 640 }
<> 144:ef7eb2e8f9f7 641 else
<> 144:ef7eb2e8f9f7 642 {
<> 144:ef7eb2e8f9f7 643 /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
<> 144:ef7eb2e8f9f7 644 check JAUTO and CONT bits of Master ADC CFGR register */
<> 144:ef7eb2e8f9f7 645 tmpADC_Master = ADC_MASTER_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 646 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /* Clear polled flag */
<> 144:ef7eb2e8f9f7 652 if (tmp_Flag_End == ADC_FLAG_JEOS)
<> 144:ef7eb2e8f9f7 653 {
<> 144:ef7eb2e8f9f7 654 /* Clear end of sequence JEOS flag of injected group if low power feature */
<> 144:ef7eb2e8f9f7 655 /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
<> 144:ef7eb2e8f9f7 656 /* For injected groups, no new conversion will start before JEOS is */
<> 144:ef7eb2e8f9f7 657 /* cleared. */
<> 144:ef7eb2e8f9f7 658 /* Note that 1. reading ADCx_JDRy clears JEOC. */
<> 144:ef7eb2e8f9f7 659 /* 2. in multimode with dual injected conversions enabled (when */
<> 144:ef7eb2e8f9f7 660 /* multimode feature is available), Master AUTDLY bit is */
<> 144:ef7eb2e8f9f7 661 /* checked. */
<> 144:ef7eb2e8f9f7 662 if (READ_BIT (tmp_cfgr_jqm_autdly, ADC_CFGR_AUTDLY) == RESET)
<> 144:ef7eb2e8f9f7 663 {
<> 144:ef7eb2e8f9f7 664 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
<> 144:ef7eb2e8f9f7 665 }
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667 else
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
<> 144:ef7eb2e8f9f7 670 }
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 674 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
<> 144:ef7eb2e8f9f7 675 /* Are injected conversions over ? This is the case if JEOS is set AND
<> 144:ef7eb2e8f9f7 676 - injected conversions are software-triggered when injected queue management is disabled
<> 144:ef7eb2e8f9f7 677 OR
<> 144:ef7eb2e8f9f7 678 - auto-injection is enabled, continuous mode is disabled,
<> 144:ef7eb2e8f9f7 679 and regular conversions are software-triggered */
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 if (tmp_jeos_raised)
<> 144:ef7eb2e8f9f7 682 {
<> 144:ef7eb2e8f9f7 683 if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm_autdly, ADC_CFGR_JQM) != ADC_CFGR_JQM))
<> 144:ef7eb2e8f9f7 684 && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) &&
<> 144:ef7eb2e8f9f7 685 (ADC_IS_SOFTWARE_START_REGULAR(hadc))) ))
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 /* Clear HAL_ADC_STATE_INJ_BUSY bit */
<> 144:ef7eb2e8f9f7 688 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 689 /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */
<> 144:ef7eb2e8f9f7 690 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 693 }
<> 144:ef7eb2e8f9f7 694 }
<> 144:ef7eb2e8f9f7 695 }
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Return API HAL status */
<> 144:ef7eb2e8f9f7 700 return HAL_OK;
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /**
<> 144:ef7eb2e8f9f7 706 * @brief Enable ADC, start conversion of injected group with interruption.
<> 144:ef7eb2e8f9f7 707 * @note Interruptions enabled in this function according to initialization
<> 144:ef7eb2e8f9f7 708 * setting : JEOC (end of conversion) or JEOS (end of sequence)
<> 144:ef7eb2e8f9f7 709 * @note Case of multimode enabled (when multimode feature is enabled):
<> 144:ef7eb2e8f9f7 710 * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
<> 144:ef7eb2e8f9f7 711 * then for ADC master.
<> 144:ef7eb2e8f9f7 712 * For ADC slave, ADC is enabled only (conversion is not started).
<> 144:ef7eb2e8f9f7 713 * For ADC master, ADC is enabled and multimode conversion is started.
<> 144:ef7eb2e8f9f7 714 * @param hadc: ADC handle.
<> 144:ef7eb2e8f9f7 715 * @retval HAL status.
<> 144:ef7eb2e8f9f7 716 */
<> 144:ef7eb2e8f9f7 717 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 718 {
<> 144:ef7eb2e8f9f7 719 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /* Check the parameters */
<> 144:ef7eb2e8f9f7 722 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
<> 144:ef7eb2e8f9f7 725 {
<> 144:ef7eb2e8f9f7 726 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 727 }
<> 144:ef7eb2e8f9f7 728 else
<> 144:ef7eb2e8f9f7 729 {
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /* In case of software trigger detection enabled, JQDIS must be set
<> 144:ef7eb2e8f9f7 732 (which can be done only if ADSTART and JADSTART are both cleared).
<> 144:ef7eb2e8f9f7 733 If JQDIS is not set at that point, returns an error
<> 144:ef7eb2e8f9f7 734 - since software trigger detection is disabled. User needs to
<> 144:ef7eb2e8f9f7 735 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
<> 144:ef7eb2e8f9f7 736 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
<> 144:ef7eb2e8f9f7 737 the queue is empty */
<> 144:ef7eb2e8f9f7 738 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)
<> 144:ef7eb2e8f9f7 739 && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))
<> 144:ef7eb2e8f9f7 740 {
<> 144:ef7eb2e8f9f7 741 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 742 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 743 }
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /* Process locked */
<> 144:ef7eb2e8f9f7 746 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 749 tmp_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 752 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 753 {
<> 144:ef7eb2e8f9f7 754 /* Check if a regular conversion is ongoing */
<> 144:ef7eb2e8f9f7 755 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 /* Reset ADC error code field related to injected conversions only */
<> 144:ef7eb2e8f9f7 758 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
<> 144:ef7eb2e8f9f7 759 }
<> 144:ef7eb2e8f9f7 760 else
<> 144:ef7eb2e8f9f7 761 {
<> 144:ef7eb2e8f9f7 762 /* Set ADC error code to none */
<> 144:ef7eb2e8f9f7 763 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 764 }
<> 144:ef7eb2e8f9f7 765 /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
<> 144:ef7eb2e8f9f7 766 ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
<> 144:ef7eb2e8f9f7 769 - by default if ADC is Master or Independent or if multimode feature is not available
<> 144:ef7eb2e8f9f7 770 - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
<> 144:ef7eb2e8f9f7 771 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 772 {
<> 144:ef7eb2e8f9f7 773 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 774 }
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 777 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 778 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /* Enable ADC Injected context queue overflow interrupt if this feature */
<> 144:ef7eb2e8f9f7 781 /* is enabled. */
<> 144:ef7eb2e8f9f7 782 if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
<> 144:ef7eb2e8f9f7 783 {
<> 144:ef7eb2e8f9f7 784 __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
<> 144:ef7eb2e8f9f7 785 }
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /* Enable ADC end of conversion interrupt */
<> 144:ef7eb2e8f9f7 788 switch(hadc->Init.EOCSelection)
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 case ADC_EOC_SEQ_CONV:
<> 144:ef7eb2e8f9f7 791 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
<> 144:ef7eb2e8f9f7 792 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
<> 144:ef7eb2e8f9f7 793 break;
<> 144:ef7eb2e8f9f7 794 /* case ADC_EOC_SINGLE_CONV */
<> 144:ef7eb2e8f9f7 795 default:
<> 144:ef7eb2e8f9f7 796 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
<> 144:ef7eb2e8f9f7 797 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
<> 144:ef7eb2e8f9f7 798 break;
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /* Enable conversion of injected group, if automatic injected conversion */
<> 144:ef7eb2e8f9f7 802 /* is disabled. */
<> 144:ef7eb2e8f9f7 803 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 804 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 805 /* trigger event. */
<> 144:ef7eb2e8f9f7 806 /* Case of multimode enabled (when multimode feature is available): */
<> 144:ef7eb2e8f9f7 807 /* if ADC is slave, */
<> 144:ef7eb2e8f9f7 808 /* - ADC is enabled only (conversion is not started), */
<> 144:ef7eb2e8f9f7 809 /* - if multimode only concerns regular conversion, ADC is enabled */
<> 144:ef7eb2e8f9f7 810 /* and conversion is started. */
<> 144:ef7eb2e8f9f7 811 /* If ADC is master or independent, */
<> 144:ef7eb2e8f9f7 812 /* - ADC is enabled and conversion is started. */
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Are injected conversions that of a dual Slave ? */
<> 144:ef7eb2e8f9f7 815 if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
<> 144:ef7eb2e8f9f7 816 {
<> 144:ef7eb2e8f9f7 817 /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
<> 144:ef7eb2e8f9f7 818 set ADSTART only if JAUTO is cleared */
<> 144:ef7eb2e8f9f7 819 /* Process unlocked */
<> 144:ef7eb2e8f9f7 820 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 821 if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
<> 144:ef7eb2e8f9f7 824 }
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826 else
<> 144:ef7eb2e8f9f7 827 {
<> 144:ef7eb2e8f9f7 828 /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
<> 144:ef7eb2e8f9f7 829 ADSTART is not set */
<> 144:ef7eb2e8f9f7 830 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 831 /* Process unlocked */
<> 144:ef7eb2e8f9f7 832 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835 else
<> 144:ef7eb2e8f9f7 836 {
<> 144:ef7eb2e8f9f7 837 /* Process unlocked */
<> 144:ef7eb2e8f9f7 838 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /* Return function status */
<> 144:ef7eb2e8f9f7 842 return tmp_status;
<> 144:ef7eb2e8f9f7 843 }
<> 144:ef7eb2e8f9f7 844 }
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /**
<> 144:ef7eb2e8f9f7 849 * @brief Stop conversion of injected channels, disable interruption of end-of-conversion.
<> 144:ef7eb2e8f9f7 850 * @note Disable ADC peripheral if no regular conversion
<> 144:ef7eb2e8f9f7 851 * is on going.
<> 144:ef7eb2e8f9f7 852 * @note If ADC must be disabled and if regular conversion
<> 144:ef7eb2e8f9f7 853 * is on going, function HAL_ADC_Stop must be used first.
<> 144:ef7eb2e8f9f7 854 * @note Case of multimode enabled (when multimode feature is available):
<> 144:ef7eb2e8f9f7 855 * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
<> 144:ef7eb2e8f9f7 856 * then for ADC slave.
<> 144:ef7eb2e8f9f7 857 * For ADC master, conversion is stopped and ADC is disabled.
<> 144:ef7eb2e8f9f7 858 * For ADC slave, ADC is disabled only (conversion stop of ADC master
<> 144:ef7eb2e8f9f7 859 * has already stopped conversion of ADC slave).
<> 144:ef7eb2e8f9f7 860 * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
<> 144:ef7eb2e8f9f7 861 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 862 * @retval None
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 865 {
<> 144:ef7eb2e8f9f7 866 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /* Check the parameters */
<> 144:ef7eb2e8f9f7 869 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /* Process locked */
<> 144:ef7eb2e8f9f7 872 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /* 1. Stop potential conversion on going on injected group only. */
<> 144:ef7eb2e8f9f7 875 tmp_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /* Disable ADC peripheral if injected conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 878 /* and if no conversion on the other group (regular group) is intended to */
<> 144:ef7eb2e8f9f7 879 /* continue. */
<> 144:ef7eb2e8f9f7 880 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 881 {
<> 144:ef7eb2e8f9f7 882 /* Disable ADC end of conversion interrupt for injected channels */
<> 144:ef7eb2e8f9f7 883 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 if ((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET))
<> 144:ef7eb2e8f9f7 886 {
<> 144:ef7eb2e8f9f7 887 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 888 tmp_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 891 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 892 {
<> 144:ef7eb2e8f9f7 893 /* Change ADC state */
<> 144:ef7eb2e8f9f7 894 /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
<> 144:ef7eb2e8f9f7 895 ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 896 }
<> 144:ef7eb2e8f9f7 897 }
<> 144:ef7eb2e8f9f7 898 /* Conversion on injected group is stopped, but ADC not disabled since */
<> 144:ef7eb2e8f9f7 899 /* conversion on regular group is still running. */
<> 144:ef7eb2e8f9f7 900 else
<> 144:ef7eb2e8f9f7 901 {
<> 144:ef7eb2e8f9f7 902 /* Clear HAL_ADC_STATE_INJ_BUSY bit */
<> 144:ef7eb2e8f9f7 903 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905 }
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /* Process unlocked */
<> 144:ef7eb2e8f9f7 908 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /* Return function status */
<> 144:ef7eb2e8f9f7 911 return tmp_status;
<> 144:ef7eb2e8f9f7 912 }
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 916 /**
<> 144:ef7eb2e8f9f7 917 * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
<> 144:ef7eb2e8f9f7 918 * @note Multimode must have been previously configured using
<> 144:ef7eb2e8f9f7 919 * HAL_ADCEx_MultiModeConfigChannel() function.
<> 144:ef7eb2e8f9f7 920 * Interruptions enabled in this function:
<> 144:ef7eb2e8f9f7 921 * overrun, DMA half transfer, DMA transfer complete.
<> 144:ef7eb2e8f9f7 922 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 923 * @note State field of Slave ADC handle is not updated in this configuration:
<> 144:ef7eb2e8f9f7 924 * user should not rely on it for information related to Slave regular
<> 144:ef7eb2e8f9f7 925 * conversions.
<> 144:ef7eb2e8f9f7 926 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
<> 144:ef7eb2e8f9f7 927 * @param pData: Destination Buffer address.
<> 144:ef7eb2e8f9f7 928 * @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes).
<> 144:ef7eb2e8f9f7 929 * @retval None
<> 144:ef7eb2e8f9f7 930 */
<> 144:ef7eb2e8f9f7 931 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
<> 144:ef7eb2e8f9f7 932 {
<> 144:ef7eb2e8f9f7 933 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 934 ADC_HandleTypeDef tmphadcSlave;
<> 144:ef7eb2e8f9f7 935 ADC_Common_TypeDef *tmpADC_Common;
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /* Check the parameters */
<> 144:ef7eb2e8f9f7 938 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 939 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 144:ef7eb2e8f9f7 940 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
<> 144:ef7eb2e8f9f7 941 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
<> 144:ef7eb2e8f9f7 944 {
<> 144:ef7eb2e8f9f7 945 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947 else
<> 144:ef7eb2e8f9f7 948 {
<> 144:ef7eb2e8f9f7 949 /* Process locked */
<> 144:ef7eb2e8f9f7 950 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 /* Set a temporary handle of the ADC slave associated to the ADC master */
<> 144:ef7eb2e8f9f7 953 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
<> 144:ef7eb2e8f9f7 954
<> 144:ef7eb2e8f9f7 955 if (tmphadcSlave.Instance == NULL)
<> 144:ef7eb2e8f9f7 956 {
<> 144:ef7eb2e8f9f7 957 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 958 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 /* Process unlocked */
<> 144:ef7eb2e8f9f7 961 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 964 }
<> 144:ef7eb2e8f9f7 965
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 /* Enable the ADC peripherals: master and slave (in case if not already */
<> 144:ef7eb2e8f9f7 968 /* enabled previously) */
<> 144:ef7eb2e8f9f7 969 tmp_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 970 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 971 {
<> 144:ef7eb2e8f9f7 972 tmp_status = ADC_Enable(&tmphadcSlave);
<> 144:ef7eb2e8f9f7 973 }
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 /* Start multimode conversion of ADCs pair */
<> 144:ef7eb2e8f9f7 976 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 977 {
<> 144:ef7eb2e8f9f7 978 /* Update Master State */
<> 144:ef7eb2e8f9f7 979 /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
<> 144:ef7eb2e8f9f7 980 ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 /* Set ADC error code to none */
<> 144:ef7eb2e8f9f7 984 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 985
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 /* Set the DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 988 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 /* Set the DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 991 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 994 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 /* Pointer to the common control register */
<> 144:ef7eb2e8f9f7 997 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
<> 144:ef7eb2e8f9f7 1001 /* start (in case of SW start): */
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 1004 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 1005 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Enable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 1008 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* Start the DMA channel */
<> 144:ef7eb2e8f9f7 1011 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 1014 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1015 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1016 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 1017 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 1018 /* trigger event. */
<> 144:ef7eb2e8f9f7 1019 SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 }
<> 144:ef7eb2e8f9f7 1022 else
<> 144:ef7eb2e8f9f7 1023 {
<> 144:ef7eb2e8f9f7 1024 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1025 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1026 }
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 /* Return function status */
<> 144:ef7eb2e8f9f7 1029 return tmp_status;
<> 144:ef7eb2e8f9f7 1030 }
<> 144:ef7eb2e8f9f7 1031 }
<> 144:ef7eb2e8f9f7 1032
<> 144:ef7eb2e8f9f7 1033 /**
<> 144:ef7eb2e8f9f7 1034 * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
<> 144:ef7eb2e8f9f7 1035 * @note Multimode is kept enabled after this function. MultiMode DMA bits
<> 144:ef7eb2e8f9f7 1036 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
<> 144:ef7eb2e8f9f7 1037 * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
<> 144:ef7eb2e8f9f7 1038 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
<> 144:ef7eb2e8f9f7 1039 * resort to HAL_ADCEx_DisableMultiMode() API.
<> 144:ef7eb2e8f9f7 1040 * @note In case of DMA configured in circular mode, function
<> 144:ef7eb2e8f9f7 1041 * HAL_ADC_Stop_DMA() must be called after this function with handle of
<> 144:ef7eb2e8f9f7 1042 * ADC slave, to properly disable the DMA channel.
<> 144:ef7eb2e8f9f7 1043 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
<> 144:ef7eb2e8f9f7 1044 * @retval None
<> 144:ef7eb2e8f9f7 1045 */
<> 144:ef7eb2e8f9f7 1046 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1047 {
<> 144:ef7eb2e8f9f7 1048 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1049 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 1050 ADC_HandleTypeDef tmphadcSlave;
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1053 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 /* Process locked */
<> 144:ef7eb2e8f9f7 1056 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 /* 1. Stop potential multimode conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 1060 tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 1063 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1064 {
<> 144:ef7eb2e8f9f7 1065 /* Set a temporary handle of the ADC slave associated to the ADC master */
<> 144:ef7eb2e8f9f7 1066 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
<> 144:ef7eb2e8f9f7 1067
<> 144:ef7eb2e8f9f7 1068 if (tmphadcSlave.Instance == NULL)
<> 144:ef7eb2e8f9f7 1069 {
<> 144:ef7eb2e8f9f7 1070 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1071 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 1072
<> 144:ef7eb2e8f9f7 1073 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1074 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1077 }
<> 144:ef7eb2e8f9f7 1078
<> 144:ef7eb2e8f9f7 1079 /* Procedure to disable the ADC peripheral: wait for conversions */
<> 144:ef7eb2e8f9f7 1080 /* effectively stopped (ADC master and ADC slave), then disable ADC */
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
<> 144:ef7eb2e8f9f7 1083 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1084
<> 144:ef7eb2e8f9f7 1085 while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
<> 144:ef7eb2e8f9f7 1086 ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
<> 144:ef7eb2e8f9f7 1087 {
<> 144:ef7eb2e8f9f7 1088 if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
<> 144:ef7eb2e8f9f7 1089 {
<> 144:ef7eb2e8f9f7 1090 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1091 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1094 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1097 }
<> 144:ef7eb2e8f9f7 1098 }
<> 144:ef7eb2e8f9f7 1099
<> 144:ef7eb2e8f9f7 1100 /* Disable the DMA channel (in case of DMA in circular mode or stop */
<> 144:ef7eb2e8f9f7 1101 /* while DMA transfer is on going) */
<> 144:ef7eb2e8f9f7 1102 /* Note: DMA channel of ADC slave should be stopped after this function */
<> 144:ef7eb2e8f9f7 1103 /* with HAL_ADC_Stop_DMA() API. */
<> 144:ef7eb2e8f9f7 1104 tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 /* Check if DMA channel effectively disabled */
<> 144:ef7eb2e8f9f7 1107 if (tmp_status == HAL_ERROR)
<> 144:ef7eb2e8f9f7 1108 {
<> 144:ef7eb2e8f9f7 1109 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1110 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 1111 }
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 1114 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 1115
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 /* 2. Disable the ADC peripherals: master and slave */
<> 144:ef7eb2e8f9f7 1119 /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
<> 144:ef7eb2e8f9f7 1120 /* memory a potential failing status. */
<> 144:ef7eb2e8f9f7 1121 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1122 {
<> 144:ef7eb2e8f9f7 1123 /* Check if ADC are effectively disabled */
<> 144:ef7eb2e8f9f7 1124 if ((ADC_Disable(hadc) == HAL_OK) &&
<> 144:ef7eb2e8f9f7 1125 (ADC_Disable(&tmphadcSlave) == HAL_OK) )
<> 144:ef7eb2e8f9f7 1126 {
<> 144:ef7eb2e8f9f7 1127 tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1128 }
<> 144:ef7eb2e8f9f7 1129 }
<> 144:ef7eb2e8f9f7 1130 else
<> 144:ef7eb2e8f9f7 1131 {
<> 144:ef7eb2e8f9f7 1132 ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 1133 ADC_Disable(&tmphadcSlave);
<> 144:ef7eb2e8f9f7 1134 }
<> 144:ef7eb2e8f9f7 1135 /* Change ADC state (ADC master) */
<> 144:ef7eb2e8f9f7 1136 /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
<> 144:ef7eb2e8f9f7 1137 ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 }
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1142 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 /* Return function status */
<> 144:ef7eb2e8f9f7 1145 return tmp_status;
<> 144:ef7eb2e8f9f7 1146 }
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 /**
<> 144:ef7eb2e8f9f7 1150 * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
<> 144:ef7eb2e8f9f7 1151 * @param hadc: ADC handle of ADC Master (handle of ADC Slave must not be used)
<> 144:ef7eb2e8f9f7 1152 * @retval The converted data values.
<> 144:ef7eb2e8f9f7 1153 */
<> 144:ef7eb2e8f9f7 1154 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1155 {
<> 144:ef7eb2e8f9f7 1156 ADC_Common_TypeDef *tmpADC_Common;
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1159 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /* Pointer to the common control register */
<> 144:ef7eb2e8f9f7 1162 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 1163
<> 144:ef7eb2e8f9f7 1164 /* Return the multi mode conversion value */
<> 144:ef7eb2e8f9f7 1165 return tmpADC_Common->CDR;
<> 144:ef7eb2e8f9f7 1166 }
<> 144:ef7eb2e8f9f7 1167 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 1168
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 /**
<> 144:ef7eb2e8f9f7 1171 * @brief Get ADC injected group conversion result.
<> 144:ef7eb2e8f9f7 1172 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1173 * @param InjectedRank: the converted ADC injected rank.
<> 144:ef7eb2e8f9f7 1174 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1175 * @arg @ref ADC_INJECTED_RANK_1 Injected Channel1 selected
<> 144:ef7eb2e8f9f7 1176 * @arg @ref ADC_INJECTED_RANK_2 Injected Channel2 selected
<> 144:ef7eb2e8f9f7 1177 * @arg @ref ADC_INJECTED_RANK_3 Injected Channel3 selected
<> 144:ef7eb2e8f9f7 1178 * @arg @ref ADC_INJECTED_RANK_4 Injected Channel4 selected
<> 144:ef7eb2e8f9f7 1179 * @note Reading JDRy register automatically clears JEOC flag. To reset JEOS
<> 144:ef7eb2e8f9f7 1180 * flag the user must resort to the macro
<> 144:ef7eb2e8f9f7 1181 * __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS).
<> 144:ef7eb2e8f9f7 1182 * @retval None
<> 144:ef7eb2e8f9f7 1183 */
<> 144:ef7eb2e8f9f7 1184 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
<> 144:ef7eb2e8f9f7 1185 {
<> 144:ef7eb2e8f9f7 1186 uint32_t tmp_jdr = 0;
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1189 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1190 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
<> 144:ef7eb2e8f9f7 1191
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /* Get ADC converted value */
<> 144:ef7eb2e8f9f7 1194 switch(InjectedRank)
<> 144:ef7eb2e8f9f7 1195 {
<> 144:ef7eb2e8f9f7 1196 case ADC_INJECTED_RANK_4:
<> 144:ef7eb2e8f9f7 1197 tmp_jdr = hadc->Instance->JDR4;
<> 144:ef7eb2e8f9f7 1198 break;
<> 144:ef7eb2e8f9f7 1199 case ADC_INJECTED_RANK_3:
<> 144:ef7eb2e8f9f7 1200 tmp_jdr = hadc->Instance->JDR3;
<> 144:ef7eb2e8f9f7 1201 break;
<> 144:ef7eb2e8f9f7 1202 case ADC_INJECTED_RANK_2:
<> 144:ef7eb2e8f9f7 1203 tmp_jdr = hadc->Instance->JDR2;
<> 144:ef7eb2e8f9f7 1204 break;
<> 144:ef7eb2e8f9f7 1205 case ADC_INJECTED_RANK_1:
<> 144:ef7eb2e8f9f7 1206 default:
<> 144:ef7eb2e8f9f7 1207 tmp_jdr = hadc->Instance->JDR1;
<> 144:ef7eb2e8f9f7 1208 break;
<> 144:ef7eb2e8f9f7 1209 }
<> 144:ef7eb2e8f9f7 1210
<> 144:ef7eb2e8f9f7 1211 /* Return ADC converted value */
<> 144:ef7eb2e8f9f7 1212 return tmp_jdr;
<> 144:ef7eb2e8f9f7 1213 }
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 /**
<> 144:ef7eb2e8f9f7 1216 * @brief Injected conversion complete callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1217 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1218 * @retval None
<> 144:ef7eb2e8f9f7 1219 */
<> 144:ef7eb2e8f9f7 1220 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1221 {
<> 144:ef7eb2e8f9f7 1222 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1223 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1226 function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1227 */
<> 144:ef7eb2e8f9f7 1228 }
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230
<> 144:ef7eb2e8f9f7 1231 /**
<> 144:ef7eb2e8f9f7 1232 * @brief Injected context queue overflow callback.
<> 144:ef7eb2e8f9f7 1233 * @note This callback is called if injected context queue is enabled
<> 144:ef7eb2e8f9f7 1234 (parameter "QueueInjectedContext" in injected channel configuration)
<> 144:ef7eb2e8f9f7 1235 and if a new injected context is set when queue is full (maximum 2
<> 144:ef7eb2e8f9f7 1236 contexts).
<> 144:ef7eb2e8f9f7 1237 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1238 * @retval None
<> 144:ef7eb2e8f9f7 1239 */
<> 144:ef7eb2e8f9f7 1240 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1241 {
<> 144:ef7eb2e8f9f7 1242 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1243 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1246 function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1247 */
<> 144:ef7eb2e8f9f7 1248 }
<> 144:ef7eb2e8f9f7 1249
<> 144:ef7eb2e8f9f7 1250 /**
<> 144:ef7eb2e8f9f7 1251 * @brief Analog watchdog 2 callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1252 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1253 * @retval None
<> 144:ef7eb2e8f9f7 1254 */
<> 144:ef7eb2e8f9f7 1255 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1256 {
<> 144:ef7eb2e8f9f7 1257 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1258 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1259
<> 144:ef7eb2e8f9f7 1260 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1261 function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1262 */
<> 144:ef7eb2e8f9f7 1263 }
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 /**
<> 144:ef7eb2e8f9f7 1266 * @brief Analog watchdog 3 callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1267 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1268 * @retval None
<> 144:ef7eb2e8f9f7 1269 */
<> 144:ef7eb2e8f9f7 1270 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1271 {
<> 144:ef7eb2e8f9f7 1272 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1273 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1276 function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1277 */
<> 144:ef7eb2e8f9f7 1278 }
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 /**
<> 144:ef7eb2e8f9f7 1282 * @brief End Of Sampling callback in non-blocking mode.
<> 144:ef7eb2e8f9f7 1283 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1284 * @retval None
<> 144:ef7eb2e8f9f7 1285 */
<> 144:ef7eb2e8f9f7 1286 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1287 {
<> 144:ef7eb2e8f9f7 1288 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1289 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1292 function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1293 */
<> 144:ef7eb2e8f9f7 1294 }
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 /**
<> 144:ef7eb2e8f9f7 1299 * @brief Stop ADC conversion of regular groups, disable ADC peripheral if no injected conversion is on-going.
<> 144:ef7eb2e8f9f7 1300 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1301 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1302 */
<> 144:ef7eb2e8f9f7 1303 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1304 {
<> 144:ef7eb2e8f9f7 1305 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1306
<> 144:ef7eb2e8f9f7 1307 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1308 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1309
<> 144:ef7eb2e8f9f7 1310 /* Process locked */
<> 144:ef7eb2e8f9f7 1311 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 /* 1. Stop potential regular conversion on going */
<> 144:ef7eb2e8f9f7 1314 tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /* Disable ADC peripheral if regular conversions are effectively stopped
<> 144:ef7eb2e8f9f7 1317 and if no injected conversions are on-going */
<> 144:ef7eb2e8f9f7 1318 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1319 {
<> 144:ef7eb2e8f9f7 1320 /* Clear HAL_ADC_STATE_REG_BUSY bit */
<> 144:ef7eb2e8f9f7 1321 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1322
<> 144:ef7eb2e8f9f7 1323 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1324 {
<> 144:ef7eb2e8f9f7 1325 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1326 tmp_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 1327
<> 144:ef7eb2e8f9f7 1328 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 1329 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1330 {
<> 144:ef7eb2e8f9f7 1331 /* Change ADC state */
<> 144:ef7eb2e8f9f7 1332 /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
<> 144:ef7eb2e8f9f7 1333 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1334 }
<> 144:ef7eb2e8f9f7 1335 }
<> 144:ef7eb2e8f9f7 1336 /* Conversion on injected group is stopped, but ADC not disabled since */
<> 144:ef7eb2e8f9f7 1337 /* conversion on regular group is still running. */
<> 144:ef7eb2e8f9f7 1338 else
<> 144:ef7eb2e8f9f7 1339 {
<> 144:ef7eb2e8f9f7 1340 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 1341 }
<> 144:ef7eb2e8f9f7 1342 }
<> 144:ef7eb2e8f9f7 1343
<> 144:ef7eb2e8f9f7 1344 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1345 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 /* Return function status */
<> 144:ef7eb2e8f9f7 1348 return tmp_status;
<> 144:ef7eb2e8f9f7 1349 }
<> 144:ef7eb2e8f9f7 1350
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 /**
<> 144:ef7eb2e8f9f7 1353 * @brief Stop ADC conversion of regular groups when interruptions are enabled, disable ADC peripheral if no injected conversion is on-going.
<> 144:ef7eb2e8f9f7 1354 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1355 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1356 */
<> 144:ef7eb2e8f9f7 1357 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1358 {
<> 144:ef7eb2e8f9f7 1359 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1360
<> 144:ef7eb2e8f9f7 1361 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1362 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 /* Process locked */
<> 144:ef7eb2e8f9f7 1365 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 /* 1. Stop potential regular conversion on going */
<> 144:ef7eb2e8f9f7 1368 tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 /* Disable ADC peripheral if conversions are effectively stopped
<> 144:ef7eb2e8f9f7 1371 and if no injected conversion is on-going */
<> 144:ef7eb2e8f9f7 1372 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1373 {
<> 144:ef7eb2e8f9f7 1374 /* Clear HAL_ADC_STATE_REG_BUSY bit */
<> 144:ef7eb2e8f9f7 1375 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1376
<> 144:ef7eb2e8f9f7 1377 /* Disable all regular-related interrupts */
<> 144:ef7eb2e8f9f7 1378 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 /* 2. Disable ADC peripheral if no injected conversions are on-going */
<> 144:ef7eb2e8f9f7 1381 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1382 {
<> 144:ef7eb2e8f9f7 1383 tmp_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 1384 /* if no issue reported */
<> 144:ef7eb2e8f9f7 1385 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1386 {
<> 144:ef7eb2e8f9f7 1387 /* Change ADC state */
<> 144:ef7eb2e8f9f7 1388 /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
<> 144:ef7eb2e8f9f7 1389 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1390 }
<> 144:ef7eb2e8f9f7 1391 }
<> 144:ef7eb2e8f9f7 1392 else
<> 144:ef7eb2e8f9f7 1393 {
<> 144:ef7eb2e8f9f7 1394 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 1395 }
<> 144:ef7eb2e8f9f7 1396 }
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1399 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1400
<> 144:ef7eb2e8f9f7 1401 /* Return function status */
<> 144:ef7eb2e8f9f7 1402 return tmp_status;
<> 144:ef7eb2e8f9f7 1403 }
<> 144:ef7eb2e8f9f7 1404
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 /**
<> 144:ef7eb2e8f9f7 1407 * @brief Stop ADC conversion of regular groups and disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
<> 144:ef7eb2e8f9f7 1408 * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
<> 144:ef7eb2e8f9f7 1409 * For multimode (when multimode feature is available),
<> 144:ef7eb2e8f9f7 1410 * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
<> 144:ef7eb2e8f9f7 1411 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1412 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1413 */
<> 144:ef7eb2e8f9f7 1414 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1415 {
<> 144:ef7eb2e8f9f7 1416 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1417
<> 144:ef7eb2e8f9f7 1418 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1419 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /* Process locked */
<> 144:ef7eb2e8f9f7 1422 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1423
<> 144:ef7eb2e8f9f7 1424 /* 1. Stop potential regular conversion on going */
<> 144:ef7eb2e8f9f7 1425 tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
<> 144:ef7eb2e8f9f7 1426
<> 144:ef7eb2e8f9f7 1427 /* Disable ADC peripheral if conversions are effectively stopped
<> 144:ef7eb2e8f9f7 1428 and if no injected conversion is on-going */
<> 144:ef7eb2e8f9f7 1429 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1430 {
<> 144:ef7eb2e8f9f7 1431 /* Clear HAL_ADC_STATE_REG_BUSY bit */
<> 144:ef7eb2e8f9f7 1432 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1433
<> 144:ef7eb2e8f9f7 1434 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
<> 144:ef7eb2e8f9f7 1435 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
<> 144:ef7eb2e8f9f7 1436
<> 144:ef7eb2e8f9f7 1437 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
<> 144:ef7eb2e8f9f7 1438 /* while DMA transfer is on going) */
<> 144:ef7eb2e8f9f7 1439 tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 /* Check if DMA channel effectively disabled */
<> 144:ef7eb2e8f9f7 1442 if (tmp_status != HAL_OK)
<> 144:ef7eb2e8f9f7 1443 {
<> 144:ef7eb2e8f9f7 1444 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1445 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 1446 }
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 1449 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 1450
<> 144:ef7eb2e8f9f7 1451 /* 2. Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1452 /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
<> 144:ef7eb2e8f9f7 1453 /* memory a potential failing status. */
<> 144:ef7eb2e8f9f7 1454 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1455 {
<> 144:ef7eb2e8f9f7 1456 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1457 {
<> 144:ef7eb2e8f9f7 1458 tmp_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 1459 }
<> 144:ef7eb2e8f9f7 1460 else
<> 144:ef7eb2e8f9f7 1461 {
<> 144:ef7eb2e8f9f7 1462 ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 1463 }
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 1466 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1467 {
<> 144:ef7eb2e8f9f7 1468 /* Change ADC state */
<> 144:ef7eb2e8f9f7 1469 /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
<> 144:ef7eb2e8f9f7 1470 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1471 }
<> 144:ef7eb2e8f9f7 1472 }
<> 144:ef7eb2e8f9f7 1473 else
<> 144:ef7eb2e8f9f7 1474 {
<> 144:ef7eb2e8f9f7 1475 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 1476 }
<> 144:ef7eb2e8f9f7 1477 }
<> 144:ef7eb2e8f9f7 1478
<> 144:ef7eb2e8f9f7 1479 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1480 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1481
<> 144:ef7eb2e8f9f7 1482 /* Return function status */
<> 144:ef7eb2e8f9f7 1483 return tmp_status;
<> 144:ef7eb2e8f9f7 1484 }
<> 144:ef7eb2e8f9f7 1485
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 1488 /**
<> 144:ef7eb2e8f9f7 1489 * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
<> 144:ef7eb2e8f9f7 1490 * @note Multimode is kept enabled after this function. Multimode DMA bits
<> 144:ef7eb2e8f9f7 1491 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
<> 144:ef7eb2e8f9f7 1492 * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
<> 144:ef7eb2e8f9f7 1493 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
<> 144:ef7eb2e8f9f7 1494 * resort to HAL_ADCEx_DisableMultiMode() API.
<> 144:ef7eb2e8f9f7 1495 * @note In case of DMA configured in circular mode, function
<> 144:ef7eb2e8f9f7 1496 * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
<> 144:ef7eb2e8f9f7 1497 * ADC slave, to properly disable the DMA channel.
<> 144:ef7eb2e8f9f7 1498 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
<> 144:ef7eb2e8f9f7 1499 * @retval None
<> 144:ef7eb2e8f9f7 1500 */
<> 144:ef7eb2e8f9f7 1501 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1502 {
<> 144:ef7eb2e8f9f7 1503 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1504 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 1505 ADC_HandleTypeDef tmphadcSlave;
<> 144:ef7eb2e8f9f7 1506
<> 144:ef7eb2e8f9f7 1507 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1508 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1509
<> 144:ef7eb2e8f9f7 1510 /* Process locked */
<> 144:ef7eb2e8f9f7 1511 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1512
<> 144:ef7eb2e8f9f7 1513
<> 144:ef7eb2e8f9f7 1514 /* 1. Stop potential multimode conversion on going, on regular groups */
<> 144:ef7eb2e8f9f7 1515 tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
<> 144:ef7eb2e8f9f7 1516
<> 144:ef7eb2e8f9f7 1517 /* Disable ADC peripheral if conversions are effectively stopped */
<> 144:ef7eb2e8f9f7 1518 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1519 {
<> 144:ef7eb2e8f9f7 1520 /* Clear HAL_ADC_STATE_REG_BUSY bit */
<> 144:ef7eb2e8f9f7 1521 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1522
<> 144:ef7eb2e8f9f7 1523 /* Set a temporary handle of the ADC slave associated to the ADC master */
<> 144:ef7eb2e8f9f7 1524 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
<> 144:ef7eb2e8f9f7 1525
<> 144:ef7eb2e8f9f7 1526 if (tmphadcSlave.Instance == NULL)
<> 144:ef7eb2e8f9f7 1527 {
<> 144:ef7eb2e8f9f7 1528 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1529 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 1530
<> 144:ef7eb2e8f9f7 1531 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1532 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1533
<> 144:ef7eb2e8f9f7 1534 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1535 }
<> 144:ef7eb2e8f9f7 1536
<> 144:ef7eb2e8f9f7 1537 /* Procedure to disable the ADC peripheral: wait for conversions */
<> 144:ef7eb2e8f9f7 1538 /* effectively stopped (ADC master and ADC slave), then disable ADC */
<> 144:ef7eb2e8f9f7 1539
<> 144:ef7eb2e8f9f7 1540 /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
<> 144:ef7eb2e8f9f7 1541 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1542
<> 144:ef7eb2e8f9f7 1543 while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
<> 144:ef7eb2e8f9f7 1544 ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
<> 144:ef7eb2e8f9f7 1545 {
<> 144:ef7eb2e8f9f7 1546 if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
<> 144:ef7eb2e8f9f7 1547 {
<> 144:ef7eb2e8f9f7 1548 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1549 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1550
<> 144:ef7eb2e8f9f7 1551 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1552 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1553
<> 144:ef7eb2e8f9f7 1554 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1555 }
<> 144:ef7eb2e8f9f7 1556 }
<> 144:ef7eb2e8f9f7 1557
<> 144:ef7eb2e8f9f7 1558 /* Disable the DMA channel (in case of DMA in circular mode or stop */
<> 144:ef7eb2e8f9f7 1559 /* while DMA transfer is on going) */
<> 144:ef7eb2e8f9f7 1560 /* Note: DMA channel of ADC slave should be stopped after this function */
<> 144:ef7eb2e8f9f7 1561 /* with HAL_ADCEx_RegularStop_DMA() API. */
<> 144:ef7eb2e8f9f7 1562 tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
<> 144:ef7eb2e8f9f7 1563
<> 144:ef7eb2e8f9f7 1564 /* Check if DMA channel effectively disabled */
<> 144:ef7eb2e8f9f7 1565 if (tmp_status != HAL_OK)
<> 144:ef7eb2e8f9f7 1566 {
<> 144:ef7eb2e8f9f7 1567 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1568 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 1569 }
<> 144:ef7eb2e8f9f7 1570
<> 144:ef7eb2e8f9f7 1571 /* Disable ADC overrun interrupt */
<> 144:ef7eb2e8f9f7 1572 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<> 144:ef7eb2e8f9f7 1573
<> 144:ef7eb2e8f9f7 1574
<> 144:ef7eb2e8f9f7 1575
<> 144:ef7eb2e8f9f7 1576 /* 2. Disable the ADC peripherals: master and slave if no injected */
<> 144:ef7eb2e8f9f7 1577 /* conversion is on-going. */
<> 144:ef7eb2e8f9f7 1578 /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
<> 144:ef7eb2e8f9f7 1579 /* memory a potential failing status. */
<> 144:ef7eb2e8f9f7 1580 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1581 {
<> 144:ef7eb2e8f9f7 1582 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1583 {
<> 144:ef7eb2e8f9f7 1584 tmp_status = ADC_Disable(hadc);
<> 144:ef7eb2e8f9f7 1585 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1586 {
<> 144:ef7eb2e8f9f7 1587 if (ADC_IS_CONVERSION_ONGOING_INJECTED(&tmphadcSlave) == RESET)
<> 144:ef7eb2e8f9f7 1588 {
<> 144:ef7eb2e8f9f7 1589 tmp_status = ADC_Disable(&tmphadcSlave);
<> 144:ef7eb2e8f9f7 1590 }
<> 144:ef7eb2e8f9f7 1591 }
<> 144:ef7eb2e8f9f7 1592 }
<> 144:ef7eb2e8f9f7 1593
<> 144:ef7eb2e8f9f7 1594 if (tmp_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1595 {
<> 144:ef7eb2e8f9f7 1596 /* Both Master and Slave ADC's could be disabled. Update Master State */
<> 144:ef7eb2e8f9f7 1597 /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
<> 144:ef7eb2e8f9f7 1598 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1599 }
<> 144:ef7eb2e8f9f7 1600 else
<> 144:ef7eb2e8f9f7 1601 {
<> 144:ef7eb2e8f9f7 1602 /* injected (Master or Slave) conversions are still on-going,
<> 144:ef7eb2e8f9f7 1603 no Master State change */
<> 144:ef7eb2e8f9f7 1604 }
<> 144:ef7eb2e8f9f7 1605
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 }
<> 144:ef7eb2e8f9f7 1608
<> 144:ef7eb2e8f9f7 1609
<> 144:ef7eb2e8f9f7 1610 }
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1613 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1614
<> 144:ef7eb2e8f9f7 1615 /* Return function status */
<> 144:ef7eb2e8f9f7 1616 return tmp_status;
<> 144:ef7eb2e8f9f7 1617 }
<> 144:ef7eb2e8f9f7 1618 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 1619
<> 144:ef7eb2e8f9f7 1620 /**
<> 144:ef7eb2e8f9f7 1621 * @}
<> 144:ef7eb2e8f9f7 1622 */
<> 144:ef7eb2e8f9f7 1623
<> 144:ef7eb2e8f9f7 1624 /** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 1625 * @brief Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 1626 *
<> 144:ef7eb2e8f9f7 1627 @verbatim
<> 144:ef7eb2e8f9f7 1628 ===============================================================================
<> 144:ef7eb2e8f9f7 1629 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1630 ===============================================================================
<> 144:ef7eb2e8f9f7 1631 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1632 (+) Configure channels on injected group
<> 144:ef7eb2e8f9f7 1633 (+) Configure multimode when multimode feature is available
<> 144:ef7eb2e8f9f7 1634 (+) Enable or Disable Injected Queue
<> 144:ef7eb2e8f9f7 1635 (+) Disable ADC voltage regulator
<> 144:ef7eb2e8f9f7 1636 (+) Enter ADC deep-power-down mode
<> 144:ef7eb2e8f9f7 1637
<> 144:ef7eb2e8f9f7 1638
<> 144:ef7eb2e8f9f7 1639 @endverbatim
<> 144:ef7eb2e8f9f7 1640 * @{
<> 144:ef7eb2e8f9f7 1641 */
<> 144:ef7eb2e8f9f7 1642
<> 144:ef7eb2e8f9f7 1643 /**
<> 144:ef7eb2e8f9f7 1644 * @brief Configure the ADC injected group and the selected channel to be linked to the injected group.
<> 144:ef7eb2e8f9f7 1645 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 1646 * This function initializes injected group, consecutive calls to this
<> 144:ef7eb2e8f9f7 1647 * function can be used to reconfigure some parameters of structure
<> 144:ef7eb2e8f9f7 1648 * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
<> 144:ef7eb2e8f9f7 1649 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 1650 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 1651 * "ADC_InjectionConfTypeDef".
<> 144:ef7eb2e8f9f7 1652 * @note In case of usage of internal measurement channels (Vbat/VrefInt/TempSensor),
<> 144:ef7eb2e8f9f7 1653 * The internal paths can be disabled using function HAL_ADC_DeInit().
<> 144:ef7eb2e8f9f7 1654 * @note To reset injected sequencer, function HAL_ADCEx_InjectedStop() can
<> 144:ef7eb2e8f9f7 1655 * be used.
<> 144:ef7eb2e8f9f7 1656 * @note Caution: For Injected Context Queue use, a context must be fully
<> 144:ef7eb2e8f9f7 1657 * defined before start of injected conversion. All channels are configured
<> 144:ef7eb2e8f9f7 1658 * consecutively for the same ADC instance. Therefore, the number of calls to
<> 144:ef7eb2e8f9f7 1659 * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
<> 144:ef7eb2e8f9f7 1660 * InjectedNbrOfConversion for each context.
<> 144:ef7eb2e8f9f7 1661 * - Example 1: If 1 context is intended to be used (or if there is no use of the
<> 144:ef7eb2e8f9f7 1662 * Injected Queue Context feature) and if the context contains 3 injected ranks
<> 144:ef7eb2e8f9f7 1663 * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
<> 144:ef7eb2e8f9f7 1664 * called once for each channel (i.e. 3 times) before starting a conversion.
<> 144:ef7eb2e8f9f7 1665 * This function must not be called to configure a 4th injected channel:
<> 144:ef7eb2e8f9f7 1666 * it would start a new context into context queue.
<> 144:ef7eb2e8f9f7 1667 * - Example 2: If 2 contexts are intended to be used and each of them contains
<> 144:ef7eb2e8f9f7 1668 * 3 injected ranks (InjectedNbrOfConversion = 3),
<> 144:ef7eb2e8f9f7 1669 * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
<> 144:ef7eb2e8f9f7 1670 * for each context (3 channels x 2 contexts = 6 calls). Conversion can
<> 144:ef7eb2e8f9f7 1671 * start once the 1st context is set, that is after the first three
<> 144:ef7eb2e8f9f7 1672 * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
<> 144:ef7eb2e8f9f7 1673 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1674 * @param sConfigInjected: Structure of ADC injected group and ADC channel for
<> 144:ef7eb2e8f9f7 1675 * injected group.
<> 144:ef7eb2e8f9f7 1676 * @retval None
<> 144:ef7eb2e8f9f7 1677 */
<> 144:ef7eb2e8f9f7 1678 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
<> 144:ef7eb2e8f9f7 1679 {
<> 144:ef7eb2e8f9f7 1680 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1681 ADC_Common_TypeDef *tmpADC_Common;
<> 144:ef7eb2e8f9f7 1682 uint32_t tmpOffsetShifted;
<> 144:ef7eb2e8f9f7 1683 uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 1684
<> 144:ef7eb2e8f9f7 1685
<> 144:ef7eb2e8f9f7 1686 uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0;
<> 144:ef7eb2e8f9f7 1687
<> 144:ef7eb2e8f9f7 1688 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1689 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1690 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
<> 144:ef7eb2e8f9f7 1691 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
<> 144:ef7eb2e8f9f7 1692 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
<> 144:ef7eb2e8f9f7 1693 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
<> 144:ef7eb2e8f9f7 1694 assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
<> 144:ef7eb2e8f9f7 1695 assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
<> 144:ef7eb2e8f9f7 1696 assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
<> 144:ef7eb2e8f9f7 1697 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
<> 144:ef7eb2e8f9f7 1698 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
<> 144:ef7eb2e8f9f7 1699
<> 144:ef7eb2e8f9f7 1700 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
<> 144:ef7eb2e8f9f7 1701 {
<> 144:ef7eb2e8f9f7 1702 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
<> 144:ef7eb2e8f9f7 1703 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
<> 144:ef7eb2e8f9f7 1704 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
<> 144:ef7eb2e8f9f7 1705 }
<> 144:ef7eb2e8f9f7 1706
<> 144:ef7eb2e8f9f7 1707
<> 144:ef7eb2e8f9f7 1708 /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
<> 144:ef7eb2e8f9f7 1709 ignored (considered as reset) */
<> 144:ef7eb2e8f9f7 1710 assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE)));
<> 144:ef7eb2e8f9f7 1711
<> 144:ef7eb2e8f9f7 1712 /* JDISCEN and JAUTO bits can't be set at the same time */
<> 144:ef7eb2e8f9f7 1713 assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
<> 144:ef7eb2e8f9f7 1714
<> 144:ef7eb2e8f9f7 1715 /* DISCEN and JAUTO bits can't be set at the same time */
<> 144:ef7eb2e8f9f7 1716 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
<> 144:ef7eb2e8f9f7 1717
<> 144:ef7eb2e8f9f7 1718 /* Verification of channel number */
<> 144:ef7eb2e8f9f7 1719 if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
<> 144:ef7eb2e8f9f7 1720 {
<> 144:ef7eb2e8f9f7 1721 assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel));
<> 144:ef7eb2e8f9f7 1722 }
<> 144:ef7eb2e8f9f7 1723 else
<> 144:ef7eb2e8f9f7 1724 {
<> 144:ef7eb2e8f9f7 1725 assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel));
<> 144:ef7eb2e8f9f7 1726 }
<> 144:ef7eb2e8f9f7 1727
<> 144:ef7eb2e8f9f7 1728
<> 144:ef7eb2e8f9f7 1729 /* Process locked */
<> 144:ef7eb2e8f9f7 1730 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1731
<> 144:ef7eb2e8f9f7 1732
<> 144:ef7eb2e8f9f7 1733
<> 144:ef7eb2e8f9f7 1734 /* Configuration of Injected group sequencer. */
<> 144:ef7eb2e8f9f7 1735 /* Hardware constraint: Must fully define injected context register JSQR */
<> 144:ef7eb2e8f9f7 1736 /* before make it entering into injected sequencer queue. */
<> 144:ef7eb2e8f9f7 1737 /* */
<> 144:ef7eb2e8f9f7 1738 /* - if scan mode is disabled: */
<> 144:ef7eb2e8f9f7 1739 /* * Injected channels sequence length is set to 0x00: 1 channel */
<> 144:ef7eb2e8f9f7 1740 /* converted (channel on injected rank 1) */
<> 144:ef7eb2e8f9f7 1741 /* Parameter "InjectedNbrOfConversion" is discarded. */
<> 144:ef7eb2e8f9f7 1742 /* * Injected context register JSQR setting is simple: register is fully */
<> 144:ef7eb2e8f9f7 1743 /* defined on one call of this function (for injected rank 1) and can */
<> 144:ef7eb2e8f9f7 1744 /* be entered into queue directly. */
<> 144:ef7eb2e8f9f7 1745 /* - if scan mode is enabled: */
<> 144:ef7eb2e8f9f7 1746 /* * Injected channels sequence length is set to parameter */
<> 144:ef7eb2e8f9f7 1747 /* "InjectedNbrOfConversion". */
<> 144:ef7eb2e8f9f7 1748 /* * Injected context register JSQR setting more complex: register is */
<> 144:ef7eb2e8f9f7 1749 /* fully defined over successive calls of this function, for each */
<> 144:ef7eb2e8f9f7 1750 /* injected channel rank. It is entered into queue only when all */
<> 144:ef7eb2e8f9f7 1751 /* injected ranks have been set. */
<> 144:ef7eb2e8f9f7 1752 /* Note: Scan mode is not present by hardware on this device, but used */
<> 144:ef7eb2e8f9f7 1753 /* by software for alignment over all STM32 devices. */
<> 144:ef7eb2e8f9f7 1754
<> 144:ef7eb2e8f9f7 1755 if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
<> 144:ef7eb2e8f9f7 1756 (sConfigInjected->InjectedNbrOfConversion == 1) )
<> 144:ef7eb2e8f9f7 1757 {
<> 144:ef7eb2e8f9f7 1758 /* Configuration of context register JSQR: */
<> 144:ef7eb2e8f9f7 1759 /* - number of ranks in injected group sequencer: fixed to 1st rank */
<> 144:ef7eb2e8f9f7 1760 /* (scan mode disabled, only rank 1 used) */
<> 144:ef7eb2e8f9f7 1761 /* - external trigger to start conversion */
<> 144:ef7eb2e8f9f7 1762 /* - external trigger polarity */
<> 144:ef7eb2e8f9f7 1763 /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
<> 144:ef7eb2e8f9f7 1764
<> 144:ef7eb2e8f9f7 1765 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
<> 144:ef7eb2e8f9f7 1766 {
<> 144:ef7eb2e8f9f7 1767 /* Enable external trigger if trigger selection is different of */
<> 144:ef7eb2e8f9f7 1768 /* software start. */
<> 144:ef7eb2e8f9f7 1769 /* Note: This configuration keeps the hardware feature of parameter */
<> 144:ef7eb2e8f9f7 1770 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
<> 144:ef7eb2e8f9f7 1771 /* software start. */
<> 144:ef7eb2e8f9f7 1772 if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 1773 && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
<> 144:ef7eb2e8f9f7 1774 {
<> 144:ef7eb2e8f9f7 1775 tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
<> 144:ef7eb2e8f9f7 1776 sConfigInjected->ExternalTrigInjecConv |
<> 144:ef7eb2e8f9f7 1777 sConfigInjected->ExternalTrigInjecConvEdge );
<> 144:ef7eb2e8f9f7 1778 }
<> 144:ef7eb2e8f9f7 1779 else
<> 144:ef7eb2e8f9f7 1780 {
<> 144:ef7eb2e8f9f7 1781 tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
<> 144:ef7eb2e8f9f7 1782 }
<> 144:ef7eb2e8f9f7 1783
<> 144:ef7eb2e8f9f7 1784
<> 144:ef7eb2e8f9f7 1785 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
<> 144:ef7eb2e8f9f7 1786 /* For debug and informative reasons, hadc handle saves JSQR setting */
<> 144:ef7eb2e8f9f7 1787 hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
<> 144:ef7eb2e8f9f7 1788
<> 144:ef7eb2e8f9f7 1789 }
<> 144:ef7eb2e8f9f7 1790 }
<> 144:ef7eb2e8f9f7 1791 else
<> 144:ef7eb2e8f9f7 1792 {
<> 144:ef7eb2e8f9f7 1793 /* Case of scan mode enabled, several channels to set into injected group */
<> 144:ef7eb2e8f9f7 1794 /* sequencer. */
<> 144:ef7eb2e8f9f7 1795 /* */
<> 144:ef7eb2e8f9f7 1796 /* Procedure to define injected context register JSQR over successive */
<> 144:ef7eb2e8f9f7 1797 /* calls of this function, for each injected channel rank: */
<> 144:ef7eb2e8f9f7 1798 /* 1. Start new context and set parameters related to all injected */
<> 144:ef7eb2e8f9f7 1799 /* channels: injected sequence length and trigger. */
<> 144:ef7eb2e8f9f7 1800
<> 144:ef7eb2e8f9f7 1801 /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
<> 144:ef7eb2e8f9f7 1802 /* call of the context under setting */
<> 144:ef7eb2e8f9f7 1803 if (hadc->InjectionConfig.ChannelCount == 0)
<> 144:ef7eb2e8f9f7 1804 {
<> 144:ef7eb2e8f9f7 1805 /* Initialize number of channels that will be configured on the context */
<> 144:ef7eb2e8f9f7 1806 /* being built */
<> 144:ef7eb2e8f9f7 1807 hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
<> 144:ef7eb2e8f9f7 1808 /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
<> 144:ef7eb2e8f9f7 1809 call, this context will be written in JSQR register at the last call.
<> 144:ef7eb2e8f9f7 1810 At this point, the context is merely reset */
<> 144:ef7eb2e8f9f7 1811 hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000;
<> 144:ef7eb2e8f9f7 1812
<> 144:ef7eb2e8f9f7 1813 /* Configuration of context register JSQR: */
<> 144:ef7eb2e8f9f7 1814 /* - number of ranks in injected group sequencer */
<> 144:ef7eb2e8f9f7 1815 /* - external trigger to start conversion */
<> 144:ef7eb2e8f9f7 1816 /* - external trigger polarity */
<> 144:ef7eb2e8f9f7 1817
<> 144:ef7eb2e8f9f7 1818 /* Enable external trigger if trigger selection is different of */
<> 144:ef7eb2e8f9f7 1819 /* software start. */
<> 144:ef7eb2e8f9f7 1820 /* Note: This configuration keeps the hardware feature of parameter */
<> 144:ef7eb2e8f9f7 1821 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
<> 144:ef7eb2e8f9f7 1822 /* software start. */
<> 144:ef7eb2e8f9f7 1823 if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 1824 && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
<> 144:ef7eb2e8f9f7 1825 {
<> 144:ef7eb2e8f9f7 1826 tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) |
<> 144:ef7eb2e8f9f7 1827 sConfigInjected->ExternalTrigInjecConv |
<> 144:ef7eb2e8f9f7 1828 sConfigInjected->ExternalTrigInjecConvEdge );
<> 144:ef7eb2e8f9f7 1829 }
<> 144:ef7eb2e8f9f7 1830 else
<> 144:ef7eb2e8f9f7 1831 {
<> 144:ef7eb2e8f9f7 1832 tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) );
<> 144:ef7eb2e8f9f7 1833 }
<> 144:ef7eb2e8f9f7 1834
<> 144:ef7eb2e8f9f7 1835
<> 144:ef7eb2e8f9f7 1836 } /* if (hadc->InjectionConfig.ChannelCount == 0) */
<> 144:ef7eb2e8f9f7 1837
<> 144:ef7eb2e8f9f7 1838
<> 144:ef7eb2e8f9f7 1839 /* 2. Continue setting of context under definition with parameter */
<> 144:ef7eb2e8f9f7 1840 /* related to each channel: channel rank sequence */
<> 144:ef7eb2e8f9f7 1841 /* Clear the old JSQx bits for the selected rank */
<> 144:ef7eb2e8f9f7 1842 tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
<> 144:ef7eb2e8f9f7 1843
<> 144:ef7eb2e8f9f7 1844 /* Set the JSQx bits for the selected rank */
<> 144:ef7eb2e8f9f7 1845 tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
<> 144:ef7eb2e8f9f7 1846
<> 144:ef7eb2e8f9f7 1847 /* Decrease channel count */
<> 144:ef7eb2e8f9f7 1848 hadc->InjectionConfig.ChannelCount--;
<> 144:ef7eb2e8f9f7 1849
<> 144:ef7eb2e8f9f7 1850
<> 144:ef7eb2e8f9f7 1851 /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
<> 144:ef7eb2e8f9f7 1852 call, aggregate the setting to those already built during the previous
<> 144:ef7eb2e8f9f7 1853 HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
<> 144:ef7eb2e8f9f7 1854 hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
<> 144:ef7eb2e8f9f7 1855
<> 144:ef7eb2e8f9f7 1856 /* 4. End of context setting: if this is the last channel set, then write context
<> 144:ef7eb2e8f9f7 1857 into register JSQR and make it enter into queue */
<> 144:ef7eb2e8f9f7 1858 if (hadc->InjectionConfig.ChannelCount == 0)
<> 144:ef7eb2e8f9f7 1859 {
<> 144:ef7eb2e8f9f7 1860 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
<> 144:ef7eb2e8f9f7 1861 }
<> 144:ef7eb2e8f9f7 1862
<> 144:ef7eb2e8f9f7 1863
<> 144:ef7eb2e8f9f7 1864 }
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 1867 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 1868 /* conversion on going on injected group: */
<> 144:ef7eb2e8f9f7 1869 /* - Injected context queue: Queue disable (active context is kept) or */
<> 144:ef7eb2e8f9f7 1870 /* enable (context decremented, up to 2 contexts queued) */
<> 144:ef7eb2e8f9f7 1871 /* - Injected discontinuous mode: can be enabled only if auto-injected */
<> 144:ef7eb2e8f9f7 1872 /* mode is disabled. */
<> 144:ef7eb2e8f9f7 1873 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1874 {
<> 144:ef7eb2e8f9f7 1875
<> 144:ef7eb2e8f9f7 1876 /* If auto-injected mode is disabled: no constraint */
<> 144:ef7eb2e8f9f7 1877 if (sConfigInjected->AutoInjectedConv == DISABLE)
<> 144:ef7eb2e8f9f7 1878 {
<> 144:ef7eb2e8f9f7 1879 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
<> 144:ef7eb2e8f9f7 1880 ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) |
<> 144:ef7eb2e8f9f7 1881 ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );
<> 144:ef7eb2e8f9f7 1882 }
<> 144:ef7eb2e8f9f7 1883 /* If auto-injected mode is enabled: Injected discontinuous setting is */
<> 144:ef7eb2e8f9f7 1884 /* discarded. */
<> 144:ef7eb2e8f9f7 1885 else
<> 144:ef7eb2e8f9f7 1886 {
<> 144:ef7eb2e8f9f7 1887 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
<> 144:ef7eb2e8f9f7 1888 ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) );
<> 144:ef7eb2e8f9f7 1889 }
<> 144:ef7eb2e8f9f7 1890
<> 144:ef7eb2e8f9f7 1891 }
<> 144:ef7eb2e8f9f7 1892
<> 144:ef7eb2e8f9f7 1893
<> 144:ef7eb2e8f9f7 1894 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 1895 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 1896 /* conversion on going on regular and injected groups: */
<> 144:ef7eb2e8f9f7 1897 /* - Automatic injected conversion: can be enabled if injected group */
<> 144:ef7eb2e8f9f7 1898 /* external triggers are disabled. */
<> 144:ef7eb2e8f9f7 1899 /* - Channel sampling time */
<> 144:ef7eb2e8f9f7 1900 /* - Channel offset */
<> 144:ef7eb2e8f9f7 1901 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1902 {
<> 144:ef7eb2e8f9f7 1903 /* If injected group external triggers are disabled (set to injected */
<> 144:ef7eb2e8f9f7 1904 /* software start): no constraint */
<> 144:ef7eb2e8f9f7 1905 if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 1906 || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
<> 144:ef7eb2e8f9f7 1907 {
<> 144:ef7eb2e8f9f7 1908 if (sConfigInjected->AutoInjectedConv == ENABLE)
<> 144:ef7eb2e8f9f7 1909 {
<> 144:ef7eb2e8f9f7 1910 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
<> 144:ef7eb2e8f9f7 1911 }
<> 144:ef7eb2e8f9f7 1912 else
<> 144:ef7eb2e8f9f7 1913 {
<> 144:ef7eb2e8f9f7 1914 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
<> 144:ef7eb2e8f9f7 1915 }
<> 144:ef7eb2e8f9f7 1916 }
<> 144:ef7eb2e8f9f7 1917 /* If Automatic injected conversion was intended to be set and could not */
<> 144:ef7eb2e8f9f7 1918 /* due to injected group external triggers enabled, error is reported. */
<> 144:ef7eb2e8f9f7 1919 else
<> 144:ef7eb2e8f9f7 1920 {
<> 144:ef7eb2e8f9f7 1921 if (sConfigInjected->AutoInjectedConv == ENABLE)
<> 144:ef7eb2e8f9f7 1922 {
<> 144:ef7eb2e8f9f7 1923 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1924 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 1925
<> 144:ef7eb2e8f9f7 1926 tmp_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1927 }
<> 144:ef7eb2e8f9f7 1928 else
<> 144:ef7eb2e8f9f7 1929 {
<> 144:ef7eb2e8f9f7 1930 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
<> 144:ef7eb2e8f9f7 1931 }
<> 144:ef7eb2e8f9f7 1932 }
<> 144:ef7eb2e8f9f7 1933
<> 144:ef7eb2e8f9f7 1934
<> 144:ef7eb2e8f9f7 1935
<> 144:ef7eb2e8f9f7 1936 if (sConfigInjected->InjecOversamplingMode == ENABLE)
<> 144:ef7eb2e8f9f7 1937 {
<> 144:ef7eb2e8f9f7 1938 assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
<> 144:ef7eb2e8f9f7 1939 assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
<> 144:ef7eb2e8f9f7 1940
<> 144:ef7eb2e8f9f7 1941 /* JOVSE must be reset in case of triggered regular mode */
<> 144:ef7eb2e8f9f7 1942 assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS)));
<> 144:ef7eb2e8f9f7 1943
<> 144:ef7eb2e8f9f7 1944 /* Configuration of Injected Oversampler: */
<> 144:ef7eb2e8f9f7 1945 /* - Oversampling Ratio */
<> 144:ef7eb2e8f9f7 1946 /* - Right bit shift */
<> 144:ef7eb2e8f9f7 1947
<> 144:ef7eb2e8f9f7 1948 /* Enable OverSampling mode */
<> 144:ef7eb2e8f9f7 1949
<> 144:ef7eb2e8f9f7 1950 MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_INJ_FIELDS,
<> 144:ef7eb2e8f9f7 1951 ADC_CFGR2_JOVSE |
<> 144:ef7eb2e8f9f7 1952 sConfigInjected->InjecOversampling.Ratio |
<> 144:ef7eb2e8f9f7 1953 sConfigInjected->InjecOversampling.RightBitShift );
<> 144:ef7eb2e8f9f7 1954 }
<> 144:ef7eb2e8f9f7 1955 else
<> 144:ef7eb2e8f9f7 1956 {
<> 144:ef7eb2e8f9f7 1957 /* Disable Regular OverSampling */
<> 144:ef7eb2e8f9f7 1958 CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
<> 144:ef7eb2e8f9f7 1959 }
<> 144:ef7eb2e8f9f7 1960
<> 144:ef7eb2e8f9f7 1961
<> 144:ef7eb2e8f9f7 1962 /* Sampling time configuration of the selected channel */
<> 144:ef7eb2e8f9f7 1963 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
<> 144:ef7eb2e8f9f7 1964 if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
<> 144:ef7eb2e8f9f7 1965 {
<> 144:ef7eb2e8f9f7 1966 /* Clear the old sample time and set the new one */
<> 144:ef7eb2e8f9f7 1967 ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
<> 144:ef7eb2e8f9f7 1968 }
<> 144:ef7eb2e8f9f7 1969 else /* if ADC_Channel_0 ... ADC_Channel_9 is selected */
<> 144:ef7eb2e8f9f7 1970 {
<> 144:ef7eb2e8f9f7 1971 /* Clear the old sample time and set the new one */
<> 144:ef7eb2e8f9f7 1972 ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
<> 144:ef7eb2e8f9f7 1973 }
<> 144:ef7eb2e8f9f7 1974
<> 144:ef7eb2e8f9f7 1975
<> 144:ef7eb2e8f9f7 1976 /* Configure the offset: offset enable/disable, channel, offset value */
<> 144:ef7eb2e8f9f7 1977
<> 144:ef7eb2e8f9f7 1978 /* Shift the offset with respect to the selected ADC resolution. */
<> 144:ef7eb2e8f9f7 1979 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
<> 144:ef7eb2e8f9f7 1980 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
<> 144:ef7eb2e8f9f7 1981
<> 144:ef7eb2e8f9f7 1982 switch (sConfigInjected->InjectedOffsetNumber)
<> 144:ef7eb2e8f9f7 1983 {
<> 144:ef7eb2e8f9f7 1984 case ADC_OFFSET_1:
<> 144:ef7eb2e8f9f7 1985 /* Configure offset register 1: */
<> 144:ef7eb2e8f9f7 1986 /* - Enable offset */
<> 144:ef7eb2e8f9f7 1987 /* - Set channel number */
<> 144:ef7eb2e8f9f7 1988 /* - Set offset value */
<> 144:ef7eb2e8f9f7 1989 MODIFY_REG(hadc->Instance->OFR1,
<> 144:ef7eb2e8f9f7 1990 ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN,
<> 144:ef7eb2e8f9f7 1991 ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
<> 144:ef7eb2e8f9f7 1992 break;
<> 144:ef7eb2e8f9f7 1993
<> 144:ef7eb2e8f9f7 1994 case ADC_OFFSET_2:
<> 144:ef7eb2e8f9f7 1995 /* Configure offset register 2: */
<> 144:ef7eb2e8f9f7 1996 /* - Enable offset */
<> 144:ef7eb2e8f9f7 1997 /* - Set channel number */
<> 144:ef7eb2e8f9f7 1998 /* - Set offset value */
<> 144:ef7eb2e8f9f7 1999 MODIFY_REG(hadc->Instance->OFR2,
<> 144:ef7eb2e8f9f7 2000 ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2_EN,
<> 144:ef7eb2e8f9f7 2001 ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
<> 144:ef7eb2e8f9f7 2002 break;
<> 144:ef7eb2e8f9f7 2003
<> 144:ef7eb2e8f9f7 2004 case ADC_OFFSET_3:
<> 144:ef7eb2e8f9f7 2005 /* Configure offset register 3: */
<> 144:ef7eb2e8f9f7 2006 /* - Enable offset */
<> 144:ef7eb2e8f9f7 2007 /* - Set channel number */
<> 144:ef7eb2e8f9f7 2008 /* - Set offset value */
<> 144:ef7eb2e8f9f7 2009 MODIFY_REG(hadc->Instance->OFR3,
<> 144:ef7eb2e8f9f7 2010 ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3_EN,
<> 144:ef7eb2e8f9f7 2011 ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
<> 144:ef7eb2e8f9f7 2012 break;
<> 144:ef7eb2e8f9f7 2013
<> 144:ef7eb2e8f9f7 2014 case ADC_OFFSET_4:
<> 144:ef7eb2e8f9f7 2015 /* Configure offset register 1: */
<> 144:ef7eb2e8f9f7 2016 /* - Enable offset */
<> 144:ef7eb2e8f9f7 2017 /* - Set channel number */
<> 144:ef7eb2e8f9f7 2018 /* - Set offset value */
<> 144:ef7eb2e8f9f7 2019 MODIFY_REG(hadc->Instance->OFR4,
<> 144:ef7eb2e8f9f7 2020 ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4_EN,
<> 144:ef7eb2e8f9f7 2021 ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);
<> 144:ef7eb2e8f9f7 2022 break;
<> 144:ef7eb2e8f9f7 2023
<> 144:ef7eb2e8f9f7 2024 /* Case ADC_OFFSET_NONE */
<> 144:ef7eb2e8f9f7 2025 default :
<> 144:ef7eb2e8f9f7 2026 /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled. */
<> 144:ef7eb2e8f9f7 2027 if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
<> 144:ef7eb2e8f9f7 2028 {
<> 144:ef7eb2e8f9f7 2029 /* Disable offset OFR1*/
<> 144:ef7eb2e8f9f7 2030 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
<> 144:ef7eb2e8f9f7 2031 }
<> 144:ef7eb2e8f9f7 2032 if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
<> 144:ef7eb2e8f9f7 2033 {
<> 144:ef7eb2e8f9f7 2034 /* Disable offset OFR2*/
<> 144:ef7eb2e8f9f7 2035 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
<> 144:ef7eb2e8f9f7 2036 }
<> 144:ef7eb2e8f9f7 2037 if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
<> 144:ef7eb2e8f9f7 2038 {
<> 144:ef7eb2e8f9f7 2039 /* Disable offset OFR3*/
<> 144:ef7eb2e8f9f7 2040 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
<> 144:ef7eb2e8f9f7 2041 }
<> 144:ef7eb2e8f9f7 2042 if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
<> 144:ef7eb2e8f9f7 2043 {
<> 144:ef7eb2e8f9f7 2044 /* Disable offset OFR4*/
<> 144:ef7eb2e8f9f7 2045 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
<> 144:ef7eb2e8f9f7 2046 }
<> 144:ef7eb2e8f9f7 2047 break;
<> 144:ef7eb2e8f9f7 2048 }
<> 144:ef7eb2e8f9f7 2049
<> 144:ef7eb2e8f9f7 2050 } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
<> 144:ef7eb2e8f9f7 2051
<> 144:ef7eb2e8f9f7 2052
<> 144:ef7eb2e8f9f7 2053 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 2054 /* Parameters that can be updated only when ADC is disabled: */
<> 144:ef7eb2e8f9f7 2055 /* - Single or differential mode */
<> 144:ef7eb2e8f9f7 2056 /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
<> 144:ef7eb2e8f9f7 2057 if (ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 2058 {
<> 144:ef7eb2e8f9f7 2059 /* Configuration of differential mode */
<> 144:ef7eb2e8f9f7 2060 if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
<> 144:ef7eb2e8f9f7 2061 {
<> 144:ef7eb2e8f9f7 2062 /* Disable differential mode (default mode: single-ended) */
<> 144:ef7eb2e8f9f7 2063 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
<> 144:ef7eb2e8f9f7 2064 }
<> 144:ef7eb2e8f9f7 2065 else
<> 144:ef7eb2e8f9f7 2066 {
<> 144:ef7eb2e8f9f7 2067 /* Enable differential mode */
<> 144:ef7eb2e8f9f7 2068 SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
<> 144:ef7eb2e8f9f7 2069
<> 144:ef7eb2e8f9f7 2070 /* Sampling time configuration of channel ADC_IN+1 (negative input).
<> 144:ef7eb2e8f9f7 2071 Starting from channel 9, SMPR2 register must be configured. */
<> 144:ef7eb2e8f9f7 2072 if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_9)
<> 144:ef7eb2e8f9f7 2073 {
<> 144:ef7eb2e8f9f7 2074 /* Clear the old sample time and set the new one */
<> 144:ef7eb2e8f9f7 2075 ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1);
<> 144:ef7eb2e8f9f7 2076 }
<> 144:ef7eb2e8f9f7 2077 else /* For channels 0 to 8 */
<> 144:ef7eb2e8f9f7 2078 {
<> 144:ef7eb2e8f9f7 2079 /* Clear the old sample time and set the new one */
<> 144:ef7eb2e8f9f7 2080 ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1);
<> 144:ef7eb2e8f9f7 2081 }
<> 144:ef7eb2e8f9f7 2082 }
<> 144:ef7eb2e8f9f7 2083
<> 144:ef7eb2e8f9f7 2084
<> 144:ef7eb2e8f9f7 2085 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
<> 144:ef7eb2e8f9f7 2086 /* internal measurement paths enable: If internal channel selected, */
<> 144:ef7eb2e8f9f7 2087 /* enable dedicated internal buffers and path. */
<> 144:ef7eb2e8f9f7 2088 /* Note: these internal measurement paths can be disabled using */
<> 144:ef7eb2e8f9f7 2089 /* HAL_ADC_DeInit(). */
<> 144:ef7eb2e8f9f7 2090
<> 144:ef7eb2e8f9f7 2091 /* Configuration of common ADC parameters */
<> 144:ef7eb2e8f9f7 2092
<> 144:ef7eb2e8f9f7 2093 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 2094
<> 144:ef7eb2e8f9f7 2095 /* If the requested internal measurement path has already been enabled, */
<> 144:ef7eb2e8f9f7 2096 /* bypass the configuration processing. */
<> 144:ef7eb2e8f9f7 2097 if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
<> 144:ef7eb2e8f9f7 2098 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
<> 144:ef7eb2e8f9f7 2099 ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) &&
<> 144:ef7eb2e8f9f7 2100 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
<> 144:ef7eb2e8f9f7 2101 ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
<> 144:ef7eb2e8f9f7 2102 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
<> 144:ef7eb2e8f9f7 2103 )
<> 144:ef7eb2e8f9f7 2104 {
<> 144:ef7eb2e8f9f7 2105 /* Configuration of common ADC parameters (continuation) */
<> 144:ef7eb2e8f9f7 2106 /* Software is allowed to change common parameters only when all ADCs */
<> 144:ef7eb2e8f9f7 2107 /* of the common group are disabled. */
<> 144:ef7eb2e8f9f7 2108 if ((ADC_IS_ENABLE(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 2109 (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
<> 144:ef7eb2e8f9f7 2110 {
<> 144:ef7eb2e8f9f7 2111 if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
<> 144:ef7eb2e8f9f7 2112 {
<> 144:ef7eb2e8f9f7 2113 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
<> 144:ef7eb2e8f9f7 2114 {
<> 144:ef7eb2e8f9f7 2115 SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
<> 144:ef7eb2e8f9f7 2116
<> 144:ef7eb2e8f9f7 2117 /* Delay for temperature sensor stabilization time */
<> 144:ef7eb2e8f9f7 2118 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 2119 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 2120 while(wait_loop_index != 0)
<> 144:ef7eb2e8f9f7 2121 {
<> 144:ef7eb2e8f9f7 2122 wait_loop_index--;
<> 144:ef7eb2e8f9f7 2123 }
<> 144:ef7eb2e8f9f7 2124 }
<> 144:ef7eb2e8f9f7 2125 }
<> 144:ef7eb2e8f9f7 2126 else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
<> 144:ef7eb2e8f9f7 2127 {
<> 144:ef7eb2e8f9f7 2128 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
<> 144:ef7eb2e8f9f7 2129 {
<> 144:ef7eb2e8f9f7 2130 SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
<> 144:ef7eb2e8f9f7 2131 }
<> 144:ef7eb2e8f9f7 2132 }
<> 144:ef7eb2e8f9f7 2133 else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
<> 144:ef7eb2e8f9f7 2134 {
<> 144:ef7eb2e8f9f7 2135 if (ADC_VREFINT_INSTANCE(hadc))
<> 144:ef7eb2e8f9f7 2136 {
<> 144:ef7eb2e8f9f7 2137 SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
<> 144:ef7eb2e8f9f7 2138 }
<> 144:ef7eb2e8f9f7 2139 }
<> 144:ef7eb2e8f9f7 2140 }
<> 144:ef7eb2e8f9f7 2141 /* If the requested internal measurement path has already been enabled */
<> 144:ef7eb2e8f9f7 2142 /* and other ADC of the common group are enabled, internal */
<> 144:ef7eb2e8f9f7 2143 /* measurement paths cannot be enabled. */
<> 144:ef7eb2e8f9f7 2144 else
<> 144:ef7eb2e8f9f7 2145 {
<> 144:ef7eb2e8f9f7 2146 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 2147 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 2148
<> 144:ef7eb2e8f9f7 2149 tmp_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2150 }
<> 144:ef7eb2e8f9f7 2151 }
<> 144:ef7eb2e8f9f7 2152
<> 144:ef7eb2e8f9f7 2153 } /* if (ADC_IS_ENABLE(hadc) == RESET) */
<> 144:ef7eb2e8f9f7 2154
<> 144:ef7eb2e8f9f7 2155 /* Process unlocked */
<> 144:ef7eb2e8f9f7 2156 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 2157
<> 144:ef7eb2e8f9f7 2158 /* Return function status */
<> 144:ef7eb2e8f9f7 2159 return tmp_status;
<> 144:ef7eb2e8f9f7 2160 }
<> 144:ef7eb2e8f9f7 2161
<> 144:ef7eb2e8f9f7 2162
<> 144:ef7eb2e8f9f7 2163
<> 144:ef7eb2e8f9f7 2164
<> 144:ef7eb2e8f9f7 2165 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 2166 /**
<> 144:ef7eb2e8f9f7 2167 * @brief Enable ADC multimode and configure multimode parameters
<> 144:ef7eb2e8f9f7 2168 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 2169 * This function initializes multimode parameters, following
<> 144:ef7eb2e8f9f7 2170 * calls to this function can be used to reconfigure some parameters
<> 144:ef7eb2e8f9f7 2171 * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
<> 144:ef7eb2e8f9f7 2172 * the ADCs.
<> 144:ef7eb2e8f9f7 2173 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 2174 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 2175 * "ADC_MultiModeTypeDef".
<> 144:ef7eb2e8f9f7 2176 * @note To move back configuration from multimode to single mode, ADC must
<> 144:ef7eb2e8f9f7 2177 * be reset (using function HAL_ADC_Init() ).
<> 144:ef7eb2e8f9f7 2178 * @param hadc: Master ADC handle
<> 144:ef7eb2e8f9f7 2179 * @param multimode : Structure of ADC multimode configuration
<> 144:ef7eb2e8f9f7 2180 * @retval HAL status
<> 144:ef7eb2e8f9f7 2181 */
<> 144:ef7eb2e8f9f7 2182 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
<> 144:ef7eb2e8f9f7 2183 {
<> 144:ef7eb2e8f9f7 2184 HAL_StatusTypeDef tmp_status = HAL_OK;
<> 144:ef7eb2e8f9f7 2185 ADC_Common_TypeDef *tmpADC_Common;
<> 144:ef7eb2e8f9f7 2186 ADC_HandleTypeDef tmphadcSlave;
<> 144:ef7eb2e8f9f7 2187
<> 144:ef7eb2e8f9f7 2188 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2189 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 2190 assert_param(IS_ADC_MULTIMODE(multimode->Mode));
<> 144:ef7eb2e8f9f7 2191 if(multimode->Mode != ADC_MODE_INDEPENDENT)
<> 144:ef7eb2e8f9f7 2192 {
<> 144:ef7eb2e8f9f7 2193 assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
<> 144:ef7eb2e8f9f7 2194 assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
<> 144:ef7eb2e8f9f7 2195 }
<> 144:ef7eb2e8f9f7 2196
<> 144:ef7eb2e8f9f7 2197 /* Process locked */
<> 144:ef7eb2e8f9f7 2198 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 2199
<> 144:ef7eb2e8f9f7 2200 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
<> 144:ef7eb2e8f9f7 2201
<> 144:ef7eb2e8f9f7 2202 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 2203 /* Parameters that can be updated when ADC is disabled or enabled without */
<> 144:ef7eb2e8f9f7 2204 /* conversion on going on regular group: */
<> 144:ef7eb2e8f9f7 2205 /* - Multimode DMA configuration */
<> 144:ef7eb2e8f9f7 2206 /* - Multimode DMA mode */
<> 144:ef7eb2e8f9f7 2207 if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<> 144:ef7eb2e8f9f7 2208 && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) )
<> 144:ef7eb2e8f9f7 2209 {
<> 144:ef7eb2e8f9f7 2210 /* Pointer to the common control register */
<> 144:ef7eb2e8f9f7 2211 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
<> 144:ef7eb2e8f9f7 2212
<> 144:ef7eb2e8f9f7 2213 /* If multimode is selected, configure all multimode paramaters. */
<> 144:ef7eb2e8f9f7 2214 /* Otherwise, reset multimode parameters (can be used in case of */
<> 144:ef7eb2e8f9f7 2215 /* transition from multimode to independent mode). */
<> 144:ef7eb2e8f9f7 2216 if(multimode->Mode != ADC_MODE_INDEPENDENT)
<> 144:ef7eb2e8f9f7 2217 {
<> 144:ef7eb2e8f9f7 2218 MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
<> 144:ef7eb2e8f9f7 2219 multimode->DMAAccessMode |
<> 144:ef7eb2e8f9f7 2220 ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests));
<> 144:ef7eb2e8f9f7 2221
<> 144:ef7eb2e8f9f7 2222 /* Parameters that can be updated only when ADC is disabled: */
<> 144:ef7eb2e8f9f7 2223 /* - Multimode mode selection */
<> 144:ef7eb2e8f9f7 2224 /* - Multimode delay */
<> 144:ef7eb2e8f9f7 2225 /* Note: Delay range depends on selected resolution: */
<> 144:ef7eb2e8f9f7 2226 /* from 1 to 12 clock cycles for 12 bits */
<> 144:ef7eb2e8f9f7 2227 /* from 1 to 10 clock cycles for 10 bits, */
<> 144:ef7eb2e8f9f7 2228 /* from 1 to 8 clock cycles for 8 bits */
<> 144:ef7eb2e8f9f7 2229 /* from 1 to 6 clock cycles for 6 bits */
<> 144:ef7eb2e8f9f7 2230 /* If a higher delay is selected, it will be clipped to maximum delay */
<> 144:ef7eb2e8f9f7 2231 /* range */
<> 144:ef7eb2e8f9f7 2232 if ((ADC_IS_ENABLE(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 2233 (ADC_IS_ENABLE(&tmphadcSlave) == RESET) )
<> 144:ef7eb2e8f9f7 2234 {
<> 144:ef7eb2e8f9f7 2235 MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY,
<> 144:ef7eb2e8f9f7 2236 multimode->Mode | multimode->TwoSamplingDelay );
<> 144:ef7eb2e8f9f7 2237 }
<> 144:ef7eb2e8f9f7 2238 }
<> 144:ef7eb2e8f9f7 2239 else /* ADC_MODE_INDEPENDENT */
<> 144:ef7eb2e8f9f7 2240 {
<> 144:ef7eb2e8f9f7 2241 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
<> 144:ef7eb2e8f9f7 2242
<> 144:ef7eb2e8f9f7 2243 /* Parameters that can be updated only when ADC is disabled: */
<> 144:ef7eb2e8f9f7 2244 /* - Multimode mode selection */
<> 144:ef7eb2e8f9f7 2245 /* - Multimode delay */
<> 144:ef7eb2e8f9f7 2246 if ((ADC_IS_ENABLE(hadc) == RESET) &&
<> 144:ef7eb2e8f9f7 2247 (ADC_IS_ENABLE(&tmphadcSlave) == RESET) )
<> 144:ef7eb2e8f9f7 2248 {
<> 144:ef7eb2e8f9f7 2249 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
<> 144:ef7eb2e8f9f7 2250 }
<> 144:ef7eb2e8f9f7 2251 }
<> 144:ef7eb2e8f9f7 2252 }
<> 144:ef7eb2e8f9f7 2253 /* If one of the ADC sharing the same common group is enabled, no update */
<> 144:ef7eb2e8f9f7 2254 /* could be done on neither of the multimode structure parameters. */
<> 144:ef7eb2e8f9f7 2255 else
<> 144:ef7eb2e8f9f7 2256 {
<> 144:ef7eb2e8f9f7 2257 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 2258 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 2259
<> 144:ef7eb2e8f9f7 2260 tmp_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2261 }
<> 144:ef7eb2e8f9f7 2262
<> 144:ef7eb2e8f9f7 2263
<> 144:ef7eb2e8f9f7 2264 /* Process unlocked */
<> 144:ef7eb2e8f9f7 2265 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 2266
<> 144:ef7eb2e8f9f7 2267 /* Return function status */
<> 144:ef7eb2e8f9f7 2268 return tmp_status;
<> 144:ef7eb2e8f9f7 2269 }
<> 144:ef7eb2e8f9f7 2270 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 2271
<> 144:ef7eb2e8f9f7 2272
<> 144:ef7eb2e8f9f7 2273 /**
<> 144:ef7eb2e8f9f7 2274 * @brief Enable Injected Queue
<> 144:ef7eb2e8f9f7 2275 * @note This function resets CFGR register JQDIS bit in order to enable the
<> 144:ef7eb2e8f9f7 2276 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
<> 144:ef7eb2e8f9f7 2277 * are both equal to 0 to ensure that no regular nor injected
<> 144:ef7eb2e8f9f7 2278 * conversion is ongoing.
<> 144:ef7eb2e8f9f7 2279 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2280 * @retval HAL status
<> 144:ef7eb2e8f9f7 2281 */
<> 144:ef7eb2e8f9f7 2282 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 2283 {
<> 144:ef7eb2e8f9f7 2284
<> 144:ef7eb2e8f9f7 2285 /* Parameter can be set only if no conversion is on-going */
<> 144:ef7eb2e8f9f7 2286 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 2287 {
<> 144:ef7eb2e8f9f7 2288 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
<> 144:ef7eb2e8f9f7 2289
<> 144:ef7eb2e8f9f7 2290 /* Update state, clear previous result related to injected queue overflow */
<> 144:ef7eb2e8f9f7 2291 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
<> 144:ef7eb2e8f9f7 2292
<> 144:ef7eb2e8f9f7 2293 return HAL_OK;
<> 144:ef7eb2e8f9f7 2294 }
<> 144:ef7eb2e8f9f7 2295 else
<> 144:ef7eb2e8f9f7 2296 {
<> 144:ef7eb2e8f9f7 2297 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2298 }
<> 144:ef7eb2e8f9f7 2299
<> 144:ef7eb2e8f9f7 2300 }
<> 144:ef7eb2e8f9f7 2301
<> 144:ef7eb2e8f9f7 2302 /**
<> 144:ef7eb2e8f9f7 2303 * @brief Disable Injected Queue
<> 144:ef7eb2e8f9f7 2304 * @note This function sets CFGR register JQDIS bit in order to disable the
<> 144:ef7eb2e8f9f7 2305 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
<> 144:ef7eb2e8f9f7 2306 * are both equal to 0 to ensure that no regular nor injected
<> 144:ef7eb2e8f9f7 2307 * conversion is ongoing.
<> 144:ef7eb2e8f9f7 2308 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2309 * @retval HAL status
<> 144:ef7eb2e8f9f7 2310 */
<> 144:ef7eb2e8f9f7 2311 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 2312 {
<> 144:ef7eb2e8f9f7 2313
<> 144:ef7eb2e8f9f7 2314 /* Parameter can be set only if no conversion is on-going */
<> 144:ef7eb2e8f9f7 2315 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
<> 144:ef7eb2e8f9f7 2316 {
<> 144:ef7eb2e8f9f7 2317 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
<> 144:ef7eb2e8f9f7 2318 return HAL_OK;
<> 144:ef7eb2e8f9f7 2319 }
<> 144:ef7eb2e8f9f7 2320 else
<> 144:ef7eb2e8f9f7 2321 {
<> 144:ef7eb2e8f9f7 2322 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2323 }
<> 144:ef7eb2e8f9f7 2324
<> 144:ef7eb2e8f9f7 2325 }
<> 144:ef7eb2e8f9f7 2326
<> 144:ef7eb2e8f9f7 2327
<> 144:ef7eb2e8f9f7 2328 /**
<> 144:ef7eb2e8f9f7 2329 * @brief Disable ADC voltage regulator.
<> 144:ef7eb2e8f9f7 2330 * @note Disabling voltage regulator allows to save power. This operation can
<> 144:ef7eb2e8f9f7 2331 * be carried out only when ADC is disabled.
<> 144:ef7eb2e8f9f7 2332 * @note To enable again the voltage regulator, the user is expected to
<> 144:ef7eb2e8f9f7 2333 * resort to HAL_ADC_Init() API.
<> 144:ef7eb2e8f9f7 2334 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2335 * @retval HAL status
<> 144:ef7eb2e8f9f7 2336 */
<> 144:ef7eb2e8f9f7 2337 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 2338 {
<> 144:ef7eb2e8f9f7 2339
<> 144:ef7eb2e8f9f7 2340 /* ADVREGEN can be written only when the ADC is disabled */
<> 144:ef7eb2e8f9f7 2341 if (ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 2342 {
<> 144:ef7eb2e8f9f7 2343 CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
<> 144:ef7eb2e8f9f7 2344 return HAL_OK;
<> 144:ef7eb2e8f9f7 2345 }
<> 144:ef7eb2e8f9f7 2346 else
<> 144:ef7eb2e8f9f7 2347 {
<> 144:ef7eb2e8f9f7 2348 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2349 }
<> 144:ef7eb2e8f9f7 2350 }
<> 144:ef7eb2e8f9f7 2351
<> 144:ef7eb2e8f9f7 2352 /**
<> 144:ef7eb2e8f9f7 2353 * @brief Enter ADC deep-power-down mode
<> 144:ef7eb2e8f9f7 2354 * @note This mode is achieved in setting DEEPPWD bit and allows to save power
<> 144:ef7eb2e8f9f7 2355 * in reducing leakage currents. It is particularly interesting before
<> 144:ef7eb2e8f9f7 2356 * entering stop modes.
<> 144:ef7eb2e8f9f7 2357 * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
<> 144:ef7eb2e8f9f7 2358 * ADC voltage regulator. This means that this API encompasses
<> 144:ef7eb2e8f9f7 2359 * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
<> 144:ef7eb2e8f9f7 2360 * calibration is lost.
<> 144:ef7eb2e8f9f7 2361 * @note To exit the ADC deep-power-down mode, the user is expected to
<> 144:ef7eb2e8f9f7 2362 * resort to HAL_ADC_Init() API as well as to relaunch a calibration
<> 144:ef7eb2e8f9f7 2363 * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
<> 144:ef7eb2e8f9f7 2364 * saved calibration factor.
<> 144:ef7eb2e8f9f7 2365 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 2366 * @retval HAL status
<> 144:ef7eb2e8f9f7 2367 */
<> 144:ef7eb2e8f9f7 2368 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 2369 {
<> 144:ef7eb2e8f9f7 2370
<> 144:ef7eb2e8f9f7 2371 /* DEEPPWD can be written only when the ADC is disabled */
<> 144:ef7eb2e8f9f7 2372 if (ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 2373 {
<> 144:ef7eb2e8f9f7 2374 SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
<> 144:ef7eb2e8f9f7 2375 return HAL_OK;
<> 144:ef7eb2e8f9f7 2376 }
<> 144:ef7eb2e8f9f7 2377 else
<> 144:ef7eb2e8f9f7 2378 {
<> 144:ef7eb2e8f9f7 2379 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2380 }
<> 144:ef7eb2e8f9f7 2381 }
<> 144:ef7eb2e8f9f7 2382
<> 144:ef7eb2e8f9f7 2383 /**
<> 144:ef7eb2e8f9f7 2384 * @}
<> 144:ef7eb2e8f9f7 2385 */
<> 144:ef7eb2e8f9f7 2386
<> 144:ef7eb2e8f9f7 2387 /**
<> 144:ef7eb2e8f9f7 2388 * @}
<> 144:ef7eb2e8f9f7 2389 */
<> 144:ef7eb2e8f9f7 2390
<> 144:ef7eb2e8f9f7 2391
<> 144:ef7eb2e8f9f7 2392
<> 144:ef7eb2e8f9f7 2393 #endif /* HAL_ADC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2394 /**
<> 144:ef7eb2e8f9f7 2395 * @}
<> 144:ef7eb2e8f9f7 2396 */
<> 144:ef7eb2e8f9f7 2397
<> 144:ef7eb2e8f9f7 2398 /**
<> 144:ef7eb2e8f9f7 2399 * @}
<> 144:ef7eb2e8f9f7 2400 */
<> 144:ef7eb2e8f9f7 2401
<> 144:ef7eb2e8f9f7 2402 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/