mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
113:b3775bf36a83 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_gpio.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.0
<> 144:ef7eb2e8f9f7 6 * @date 8-January-2016
<> 144:ef7eb2e8f9f7 7 * @brief GPIO HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the General Purpose Input/Output (GPIO) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### GPIO Peripheral features #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
<> 144:ef7eb2e8f9f7 19 configured by software in several modes:
<> 144:ef7eb2e8f9f7 20 (++) Input mode
<> 144:ef7eb2e8f9f7 21 (++) Analog mode
<> 144:ef7eb2e8f9f7 22 (++) Output mode
<> 144:ef7eb2e8f9f7 23 (++) Alternate function mode
<> 144:ef7eb2e8f9f7 24 (++) External interrupt/event lines
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 (+) During and just after reset, the alternate functions and external interrupt
<> 144:ef7eb2e8f9f7 27 lines are not active and the I/O ports are configured in input floating mode.
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
<> 144:ef7eb2e8f9f7 30 activated or not.
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
<> 144:ef7eb2e8f9f7 33 type and the IO speed can be selected depending on the VDD value.
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
<> 144:ef7eb2e8f9f7 36 multiplexer that allows only one peripheral alternate function (AF) connected
<> 144:ef7eb2e8f9f7 37 to an IO pin at a time. In this way, there can be no conflict between peripherals
<> 144:ef7eb2e8f9f7 38 sharing the same IO pin.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (+) All ports have external interrupt/event capability. To use external interrupt
<> 144:ef7eb2e8f9f7 41 lines, the port must be configured in input mode. All available GPIO pins are
<> 144:ef7eb2e8f9f7 42 connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (+) The external interrupt/event controller consists of up to 28 edge detectors
<> 144:ef7eb2e8f9f7 45 (16 lines are connected to GPIO) for generating event/interrupt requests (each
<> 144:ef7eb2e8f9f7 46 input line can be independently configured to select the type (interrupt or event)
<> 144:ef7eb2e8f9f7 47 and the corresponding trigger event (rising or falling or both). Each line can
<> 144:ef7eb2e8f9f7 48 also be masked independently.
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 51 ==============================================================================
<> 144:ef7eb2e8f9f7 52 [..]
<> 144:ef7eb2e8f9f7 53 (#) Enable the GPIO IOPORT clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
<> 144:ef7eb2e8f9f7 56 (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
<> 144:ef7eb2e8f9f7 57 (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
<> 144:ef7eb2e8f9f7 58 structure.
<> 144:ef7eb2e8f9f7 59 (++) In case of Output or alternate function mode selection: the speed is
<> 144:ef7eb2e8f9f7 60 configured through "Speed" member from GPIO_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 61 (++) In alternate mode is selection, the alternate function connected to the IO
<> 144:ef7eb2e8f9f7 62 is configured through "Alternate" member from GPIO_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 63 (++) Analog mode is required when a pin is to be used as ADC channel
<> 144:ef7eb2e8f9f7 64 or DAC output.
<> 144:ef7eb2e8f9f7 65 (++) In case of external interrupt/event selection the "Mode" member from
<> 144:ef7eb2e8f9f7 66 GPIO_InitTypeDef structure select the type (interrupt or event) and
<> 144:ef7eb2e8f9f7 67 the corresponding trigger event (rising or falling or both).
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
<> 144:ef7eb2e8f9f7 70 mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
<> 144:ef7eb2e8f9f7 71 HAL_NVIC_EnableIRQ().
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 (#) HAL_GPIO_DeInit allows to set register values to their reset value. This function
<> 144:ef7eb2e8f9f7 74 is also to be used when unconfiguring pin which was used as an external interrupt
<> 144:ef7eb2e8f9f7 75 or in event mode. That is the only way to reset the corresponding bit in
<> 144:ef7eb2e8f9f7 76 EXTI & SYSCFG registers.
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 (#) To set/reset the level of a pin configured in output mode use
<> 144:ef7eb2e8f9f7 81 HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 (#) During and just after reset, the alternate functions are not
<> 144:ef7eb2e8f9f7 86 active and the GPIO pins are configured in input floating mode (except JTAG
<> 144:ef7eb2e8f9f7 87 pins).
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
<> 144:ef7eb2e8f9f7 90 (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
<> 144:ef7eb2e8f9f7 91 priority over the GPIO function.
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
<> 144:ef7eb2e8f9f7 94 general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
<> 144:ef7eb2e8f9f7 95 The HSE has priority over the GPIO function.
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 @endverbatim
<> 144:ef7eb2e8f9f7 98 ******************************************************************************
<> 144:ef7eb2e8f9f7 99 * @attention
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 102 *
<> 144:ef7eb2e8f9f7 103 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 104 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 105 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 106 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 108 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 109 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 111 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 112 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 ******************************************************************************
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 #ifdef HAL_GPIO_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /** @addtogroup GPIO
<> 144:ef7eb2e8f9f7 138 * @brief GPIO HAL module driver
<> 144:ef7eb2e8f9f7 139 * @{
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /** @addtogroup GPIO_Private
<> 144:ef7eb2e8f9f7 143 * @{
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 #define GPIO_MODE ((uint32_t)0x00000003)
<> 144:ef7eb2e8f9f7 149 #define EXTI_MODE ((uint32_t)0x10000000)
<> 144:ef7eb2e8f9f7 150 #define GPIO_MODE_IT ((uint32_t)0x00010000)
<> 144:ef7eb2e8f9f7 151 #define GPIO_MODE_EVT ((uint32_t)0x00020000)
<> 144:ef7eb2e8f9f7 152 #define RISING_EDGE ((uint32_t)0x00100000)
<> 144:ef7eb2e8f9f7 153 #define FALLING_EDGE ((uint32_t)0x00200000)
<> 144:ef7eb2e8f9f7 154 #define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 #define GPIO_NUMBER ((uint32_t)16)
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /**
<> 144:ef7eb2e8f9f7 159 * @}
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161 /** @addtogroup GPIO_Exported_Functions
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /** @addtogroup GPIO_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 166 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 167 *
<> 144:ef7eb2e8f9f7 168 @verbatim
<> 144:ef7eb2e8f9f7 169 ===============================================================================
<> 144:ef7eb2e8f9f7 170 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 171 ===============================================================================
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 @endverbatim
<> 144:ef7eb2e8f9f7 174 * @{
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /**
<> 144:ef7eb2e8f9f7 178 * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
<> 144:ef7eb2e8f9f7 179 * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0XX family devices.
<> 144:ef7eb2e8f9f7 180 * Note that GPIOE is not available on all devices.
<> 144:ef7eb2e8f9f7 181 * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 182 * the configuration information for the specified GPIO peripheral.
<> 144:ef7eb2e8f9f7 183 * @retval None
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185 void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
<> 144:ef7eb2e8f9f7 186 {
<> 144:ef7eb2e8f9f7 187 uint32_t position = 0x00;
<> 144:ef7eb2e8f9f7 188 uint32_t iocurrent = 0x00;
<> 144:ef7eb2e8f9f7 189 uint32_t temp = 0x00;
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Check the parameters */
<> 144:ef7eb2e8f9f7 192 assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
<> 144:ef7eb2e8f9f7 193 assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
<> 144:ef7eb2e8f9f7 194 assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,(GPIO_Init->Pin)));
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* Configure the port pins */
<> 144:ef7eb2e8f9f7 197 while ((GPIO_Init->Pin) >> position)
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 /* Get the IO position */
<> 144:ef7eb2e8f9f7 200 iocurrent = (GPIO_Init->Pin) & (1 << position);
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 if(iocurrent)
<> 144:ef7eb2e8f9f7 203 {
<> 144:ef7eb2e8f9f7 204 /*--------------------- GPIO Mode Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 205 /* In case of Alternate function mode selection */
<> 144:ef7eb2e8f9f7 206 if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
<> 144:ef7eb2e8f9f7 207 {
<> 144:ef7eb2e8f9f7 208 /* Check if the Alternate function is compliant with the GPIO in use */
<> 144:ef7eb2e8f9f7 209 assert_param(IS_GPIO_AF_AVAILABLE(GPIOx,(GPIO_Init->Alternate)));
<> 144:ef7eb2e8f9f7 210 /* Configure Alternate function mapped with the current IO */
<> 144:ef7eb2e8f9f7 211 temp = GPIOx->AFR[position >> 3];
<> 144:ef7eb2e8f9f7 212 temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
<> 144:ef7eb2e8f9f7 213 temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)) ;
<> 144:ef7eb2e8f9f7 214 GPIOx->AFR[position >> 3] = temp;
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* In case of Output or Alternate function mode selection */
<> 144:ef7eb2e8f9f7 218 if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
<> 144:ef7eb2e8f9f7 219 (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 /* Check the Speed parameter */
<> 144:ef7eb2e8f9f7 222 assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
<> 144:ef7eb2e8f9f7 223 /* Configure the IO Speed */
<> 144:ef7eb2e8f9f7 224 temp = GPIOx->OSPEEDR;
<> 144:ef7eb2e8f9f7 225 temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2));
<> 144:ef7eb2e8f9f7 226 temp |= (GPIO_Init->Speed << (position * 2));
<> 144:ef7eb2e8f9f7 227 GPIOx->OSPEEDR = temp;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Configure the IO Output Type */
<> 144:ef7eb2e8f9f7 230 temp= GPIOx->OTYPER;
<> 144:ef7eb2e8f9f7 231 temp &= ~(GPIO_OTYPER_OT_0 << position) ;
<> 144:ef7eb2e8f9f7 232 temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
<> 144:ef7eb2e8f9f7 233 GPIOx->OTYPER = temp;
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
<> 144:ef7eb2e8f9f7 237 temp = GPIOx->MODER;
<> 144:ef7eb2e8f9f7 238 temp &= ~(GPIO_MODER_MODE0 << (position * 2));
<> 144:ef7eb2e8f9f7 239 temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
<> 144:ef7eb2e8f9f7 240 GPIOx->MODER = temp;
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Activate the Pull-up or Pull down resistor for the current IO */
<> 144:ef7eb2e8f9f7 243 temp = GPIOx->PUPDR;
<> 144:ef7eb2e8f9f7 244 temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
<> 144:ef7eb2e8f9f7 245 temp |= ((GPIO_Init->Pull) << (position * 2));
<> 144:ef7eb2e8f9f7 246 GPIOx->PUPDR = temp;
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /*--------------------- EXTI Mode Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 249 /* Configure the External Interrupt or event for the current IO */
<> 144:ef7eb2e8f9f7 250 if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
<> 144:ef7eb2e8f9f7 251 {
<> 144:ef7eb2e8f9f7 252 /* Enable SYSCFG Clock */
<> 144:ef7eb2e8f9f7 253 __HAL_RCC_SYSCFG_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 temp = SYSCFG->EXTICR[position >> 2];
<> 144:ef7eb2e8f9f7 256 temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
<> 144:ef7eb2e8f9f7 257 temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
<> 144:ef7eb2e8f9f7 258 SYSCFG->EXTICR[position >> 2] = temp;
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* Clear EXTI line configuration */
<> 144:ef7eb2e8f9f7 261 temp = EXTI->IMR;
<> 144:ef7eb2e8f9f7 262 temp &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 263 if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
<> 144:ef7eb2e8f9f7 264 {
<> 144:ef7eb2e8f9f7 265 temp |= iocurrent;
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267 EXTI->IMR = temp;
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 temp = EXTI->EMR;
<> 144:ef7eb2e8f9f7 270 temp &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 271 if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 temp |= iocurrent;
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275 EXTI->EMR = temp;
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* Clear Rising Falling edge configuration */
<> 144:ef7eb2e8f9f7 278 temp = EXTI->RTSR;
<> 144:ef7eb2e8f9f7 279 temp &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 280 if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 temp |= iocurrent;
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284 EXTI->RTSR = temp;
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 temp = EXTI->FTSR;
<> 144:ef7eb2e8f9f7 287 temp &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 288 if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
<> 144:ef7eb2e8f9f7 289 {
<> 144:ef7eb2e8f9f7 290 temp |= iocurrent;
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292 EXTI->FTSR = temp;
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295 position++;
<> 144:ef7eb2e8f9f7 296 }
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @brief De-initializes the GPIOx peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 301 * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0XX family devices.
<> 144:ef7eb2e8f9f7 302 * Note that GPIOE is not available on all devices.
<> 144:ef7eb2e8f9f7 303 * @param GPIO_Pin: specifies the port bit to be written.
<> 144:ef7eb2e8f9f7 304 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 305 * All port bits are not necessarily available on all GPIOs.
<> 144:ef7eb2e8f9f7 306 * @retval None
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308 void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 309 {
<> 144:ef7eb2e8f9f7 310 uint32_t position = 0x00;
<> 144:ef7eb2e8f9f7 311 uint32_t iocurrent = 0x00;
<> 144:ef7eb2e8f9f7 312 uint32_t tmp = 0x00;
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /* Check the parameters */
<> 144:ef7eb2e8f9f7 315 assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin));
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Configure the port pins */
<> 144:ef7eb2e8f9f7 318 while (GPIO_Pin >> position)
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 /* Get the IO position */
<> 144:ef7eb2e8f9f7 321 iocurrent = (GPIO_Pin) & (1 << position);
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 if(iocurrent)
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 /*------------------------- GPIO Mode Configuration --------------------*/
<> 144:ef7eb2e8f9f7 326 /* Configure IO Direction in Input Floting Mode */
<> 144:ef7eb2e8f9f7 327 GPIOx->MODER &= ~(GPIO_MODER_MODE0 << (position * 2));
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Configure the default Alternate Function in current IO */
<> 144:ef7eb2e8f9f7 330 GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /* Configure the default value for IO Speed */
<> 144:ef7eb2e8f9f7 333 GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2));
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* Configure the default value IO Output Type */
<> 144:ef7eb2e8f9f7 336 GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
<> 144:ef7eb2e8f9f7 339 GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /*------------------------- EXTI Mode Configuration --------------------*/
<> 144:ef7eb2e8f9f7 342 /* Clear the External Interrupt or Event for the current IO */
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 tmp = SYSCFG->EXTICR[position >> 2];
<> 144:ef7eb2e8f9f7 345 tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
<> 144:ef7eb2e8f9f7 346 if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
<> 144:ef7eb2e8f9f7 349 SYSCFG->EXTICR[position >> 2] &= ~tmp;
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Clear EXTI line configuration */
<> 144:ef7eb2e8f9f7 352 EXTI->IMR &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 353 EXTI->EMR &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Clear Rising Falling edge configuration */
<> 144:ef7eb2e8f9f7 356 EXTI->RTSR &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 357 EXTI->FTSR &= ~((uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 358 }
<> 144:ef7eb2e8f9f7 359 }
<> 144:ef7eb2e8f9f7 360 position++;
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /**
<> 144:ef7eb2e8f9f7 365 * @}
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /** @addtogroup GPIO_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 369 * @brief GPIO Read and Write
<> 144:ef7eb2e8f9f7 370 *
<> 144:ef7eb2e8f9f7 371 @verbatim
<> 144:ef7eb2e8f9f7 372 ===============================================================================
<> 144:ef7eb2e8f9f7 373 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 374 ===============================================================================
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 @endverbatim
<> 144:ef7eb2e8f9f7 377 * @{
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /**
<> 144:ef7eb2e8f9f7 381 * @brief Reads the specified input port pin.
<> 144:ef7eb2e8f9f7 382 * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices.
<> 144:ef7eb2e8f9f7 383 * Note that GPIOE is not available on all devices.
<> 144:ef7eb2e8f9f7 384 * @param GPIO_Pin: specifies the port bit to read.
<> 144:ef7eb2e8f9f7 385 * This parameter can be GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 386 * All port bits are not necessarily available on all GPIOs.
<> 144:ef7eb2e8f9f7 387 * @retval The input port pin value.
<> 144:ef7eb2e8f9f7 388 */
<> 144:ef7eb2e8f9f7 389 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 390 {
<> 144:ef7eb2e8f9f7 391 GPIO_PinState bitstatus;
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /* Check the parameters */
<> 144:ef7eb2e8f9f7 394 assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin));
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 bitstatus = GPIO_PIN_SET;
<> 144:ef7eb2e8f9f7 399 }
<> 144:ef7eb2e8f9f7 400 else
<> 144:ef7eb2e8f9f7 401 {
<> 144:ef7eb2e8f9f7 402 bitstatus = GPIO_PIN_RESET;
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404 return bitstatus;
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /**
<> 144:ef7eb2e8f9f7 408 * @brief Sets or clears the selected data port bit.
<> 144:ef7eb2e8f9f7 409 *
<> 144:ef7eb2e8f9f7 410 * @note This function uses GPIOx_BSRR register to allow atomic read/modify
<> 144:ef7eb2e8f9f7 411 * accesses. In this way, there is no risk of an IRQ occurring between
<> 144:ef7eb2e8f9f7 412 * the read and the modify access.
<> 144:ef7eb2e8f9f7 413 *
<> 144:ef7eb2e8f9f7 414 * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices.
<> 144:ef7eb2e8f9f7 415 * Note that GPIOE is not available on all devices.
<> 144:ef7eb2e8f9f7 416 * @param GPIO_Pin: specifies the port bit to be written.
<> 144:ef7eb2e8f9f7 417 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 418 * All port bits are not necessarily available on all GPIOs.
<> 144:ef7eb2e8f9f7 419 * @param PinState: specifies the value to be written to the selected bit.
<> 144:ef7eb2e8f9f7 420 * This parameter can be one of the GPIO_PinState enum values:
<> 144:ef7eb2e8f9f7 421 * GPIO_PIN_RESET: to clear the port pin
<> 144:ef7eb2e8f9f7 422 * GPIO_PIN_SET: to set the port pin
<> 144:ef7eb2e8f9f7 423 * @retval None
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 /* Check the parameters */
<> 144:ef7eb2e8f9f7 428 assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin));
<> 144:ef7eb2e8f9f7 429 assert_param(IS_GPIO_PIN_ACTION(PinState));
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 if(PinState != GPIO_PIN_RESET)
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 GPIOx->BSRR = GPIO_Pin;
<> 144:ef7eb2e8f9f7 434 }
<> 144:ef7eb2e8f9f7 435 else
<> 144:ef7eb2e8f9f7 436 {
<> 144:ef7eb2e8f9f7 437 GPIOx->BRR = GPIO_Pin ;
<> 144:ef7eb2e8f9f7 438 }
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /**
<> 144:ef7eb2e8f9f7 442 * @brief Toggles the specified GPIO pins.
<> 144:ef7eb2e8f9f7 443 * @param GPIOx: Where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices.
<> 144:ef7eb2e8f9f7 444 * Note that GPIOE is not available on all devices.
<> 144:ef7eb2e8f9f7 445 * All port bits are not necessarily available on all GPIOs.
<> 144:ef7eb2e8f9f7 446 * @param GPIO_Pin: Specifies the pins to be toggled.
<> 144:ef7eb2e8f9f7 447 * @retval None
<> 144:ef7eb2e8f9f7 448 */
<> 144:ef7eb2e8f9f7 449 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 450 {
<> 144:ef7eb2e8f9f7 451 /* Check the parameters */
<> 144:ef7eb2e8f9f7 452 assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin));
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 GPIOx->ODR ^= GPIO_Pin;
<> 144:ef7eb2e8f9f7 455 }
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /**
<> 144:ef7eb2e8f9f7 458 * @brief Locks GPIO Pins configuration registers.
<> 144:ef7eb2e8f9f7 459 * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
<> 144:ef7eb2e8f9f7 460 * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
<> 144:ef7eb2e8f9f7 461 * @note The configuration of the locked GPIO pins can no longer be modified
<> 144:ef7eb2e8f9f7 462 * until the next reset.
<> 144:ef7eb2e8f9f7 463 * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family.
<> 144:ef7eb2e8f9f7 464 * Note that GPIOE is not available on all devices.
<> 144:ef7eb2e8f9f7 465 * @param GPIO_Pin: specifies the port bit to be locked.
<> 144:ef7eb2e8f9f7 466 * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 467 * All port bits are not necessarily available on all GPIOs.
<> 144:ef7eb2e8f9f7 468 * @retval None
<> 144:ef7eb2e8f9f7 469 */
<> 144:ef7eb2e8f9f7 470 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 471 {
<> 144:ef7eb2e8f9f7 472 __IO uint32_t tmp = GPIO_LCKR_LCKK;
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /* Check the parameters */
<> 144:ef7eb2e8f9f7 475 assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin));
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* Apply lock key write sequence */
<> 144:ef7eb2e8f9f7 478 tmp |= GPIO_Pin;
<> 144:ef7eb2e8f9f7 479 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 480 GPIOx->LCKR = tmp;
<> 144:ef7eb2e8f9f7 481 /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 482 GPIOx->LCKR = GPIO_Pin;
<> 144:ef7eb2e8f9f7 483 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 484 GPIOx->LCKR = tmp;
<> 144:ef7eb2e8f9f7 485 /* Read LCKK bit*/
<> 144:ef7eb2e8f9f7 486 tmp = GPIOx->LCKR;
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 return HAL_OK;
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492 else
<> 144:ef7eb2e8f9f7 493 {
<> 144:ef7eb2e8f9f7 494 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 495 }
<> 144:ef7eb2e8f9f7 496 }
<> 144:ef7eb2e8f9f7 497 /**
<> 144:ef7eb2e8f9f7 498 * @brief This function handles EXTI interrupt request.
<> 144:ef7eb2e8f9f7 499 * @param GPIO_Pin: Specifies the pins connected to the EXTI line.
<> 144:ef7eb2e8f9f7 500 * @retval None
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 503 {
<> 144:ef7eb2e8f9f7 504 /* EXTI line interrupt detected */
<> 144:ef7eb2e8f9f7 505 if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
<> 144:ef7eb2e8f9f7 506 {
<> 144:ef7eb2e8f9f7 507 __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
<> 144:ef7eb2e8f9f7 508 HAL_GPIO_EXTI_Callback(GPIO_Pin);
<> 144:ef7eb2e8f9f7 509 }
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /**
<> 144:ef7eb2e8f9f7 513 * @brief EXTI line detection callbacks.
<> 144:ef7eb2e8f9f7 514 * @param GPIO_Pin: Specifies the pins connected to the EXTI line.
<> 144:ef7eb2e8f9f7 515 * @retval None
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 518 {
<> 144:ef7eb2e8f9f7 519 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 520 UNUSED(GPIO_Pin);
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 523 the HAL_GPIO_EXTI_Callback could be implemented in the user file
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525 }
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /**
<> 144:ef7eb2e8f9f7 528 * @}
<> 144:ef7eb2e8f9f7 529 */
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /**
<> 144:ef7eb2e8f9f7 533 * @}
<> 144:ef7eb2e8f9f7 534 */
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /**
<> 144:ef7eb2e8f9f7 537 * @}
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 #endif /* HAL_GPIO_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /**
<> 144:ef7eb2e8f9f7 543 * @}
<> 144:ef7eb2e8f9f7 544 */
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 547