mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
113:b3775bf36a83 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_cryp.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.0
<> 144:ef7eb2e8f9f7 6 * @date 8-January-2016
<> 144:ef7eb2e8f9f7 7 * @brief CRYP HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Cryptography (CRYP) peripheral:
<> 144:ef7eb2e8f9f7 11 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + Processing functions by algorithm using polling mode
<> 144:ef7eb2e8f9f7 13 * + Processing functions by algorithm using interrupt mode
<> 144:ef7eb2e8f9f7 14 * + Processing functions by algorithm using DMA mode
<> 144:ef7eb2e8f9f7 15 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 @verbatim
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 20 ==============================================================================
<> 144:ef7eb2e8f9f7 21 [..]
<> 144:ef7eb2e8f9f7 22 The CRYP HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
<> 144:ef7eb2e8f9f7 25 (##) Enable the CRYP interface clock using __HAL_RCC_AES_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 26 (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
<> 144:ef7eb2e8f9f7 27 (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 28 (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 29 (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
<> 144:ef7eb2e8f9f7 30 (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
<> 144:ef7eb2e8f9f7 31 (+) Enable the DMA1 interface clock using
<> 144:ef7eb2e8f9f7 32 (++) __HAL_RCC_DMA1_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 33 (+) Configure and enable two DMA Channels one for managing data transfer from
<> 144:ef7eb2e8f9f7 34 memory to peripheral (input channel) and another channel for managing data
<> 144:ef7eb2e8f9f7 35 transfer from peripheral to memory (output channel)
<> 144:ef7eb2e8f9f7 36 (+) Associate the initialized DMA handle to the CRYP DMA handle
<> 144:ef7eb2e8f9f7 37 using __HAL_LINKDMA()
<> 144:ef7eb2e8f9f7 38 (+) Configure the priority and enable the NVIC for the transfer complete
<> 144:ef7eb2e8f9f7 39 interrupt on the two DMA Streams. The output stream should have higher
<> 144:ef7eb2e8f9f7 40 priority than the input stream.
<> 144:ef7eb2e8f9f7 41 (++) HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 42 (++) HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
<> 144:ef7eb2e8f9f7 45 (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
<> 144:ef7eb2e8f9f7 46 (##) The encryption/decryption key.
<> 144:ef7eb2e8f9f7 47 (##) The initialization vector (counter). It is not used ECB mode.
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 (#)Three processing (encryption/decryption) functions are available:
<> 144:ef7eb2e8f9f7 50 (##) Polling mode: encryption and decryption APIs are blocking functions
<> 144:ef7eb2e8f9f7 51 i.e. they process the data and wait till the processing is finished
<> 144:ef7eb2e8f9f7 52 e.g. HAL_CRYP_AESCBC_Encrypt()
<> 144:ef7eb2e8f9f7 53 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
<> 144:ef7eb2e8f9f7 54 i.e. they process the data under interrupt
<> 144:ef7eb2e8f9f7 55 e.g. HAL_CRYP_AESCBC_Encrypt_IT()
<> 144:ef7eb2e8f9f7 56 (##) DMA mode: encryption and decryption APIs are not blocking functions
<> 144:ef7eb2e8f9f7 57 i.e. the data transfer is ensured by DMA
<> 144:ef7eb2e8f9f7 58 e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (#)When the processing function is called for the first time after HAL_CRYP_Init()
<> 144:ef7eb2e8f9f7 61 the CRYP peripheral is initialized and processes the buffer in input.
<> 144:ef7eb2e8f9f7 62 At second call, the processing function performs an append of the already
<> 144:ef7eb2e8f9f7 63 processed buffer.
<> 144:ef7eb2e8f9f7 64 When a new data block is to be processed, call HAL_CRYP_Init() then the
<> 144:ef7eb2e8f9f7 65 processing function.
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 @endverbatim
<> 144:ef7eb2e8f9f7 70 ******************************************************************************
<> 144:ef7eb2e8f9f7 71 * @attention
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 76 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 77 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 78 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 79 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 80 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 81 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 82 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 83 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 84 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 85 *
<> 144:ef7eb2e8f9f7 86 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 87 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 88 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 89 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 90 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 91 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 92 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 93 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 94 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 95 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 96 *
<> 144:ef7eb2e8f9f7 97 ******************************************************************************
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 #if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 101 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 102 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 #ifdef HAL_CRYP_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 105 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /** @addtogroup CRYP
<> 144:ef7eb2e8f9f7 110 * @brief CRYP HAL module driver.
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /** @addtogroup CRYP_Private CRYP Private
<> 144:ef7eb2e8f9f7 119 * @{
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 #define CRYP_ALGO_CHAIN_MASK (AES_CR_MODE | AES_CR_CHMOD)
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @}
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 130 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /** @addtogroup CRYP_Private
<> 144:ef7eb2e8f9f7 133 * @{
<> 144:ef7eb2e8f9f7 134 */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp);
<> 144:ef7eb2e8f9f7 137 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
<> 144:ef7eb2e8f9f7 138 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key);
<> 144:ef7eb2e8f9f7 139 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 140 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 141 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 142 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 143 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /**
<> 144:ef7eb2e8f9f7 146 * @}
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /** @addtogroup CRYP_Exported_Functions
<> 144:ef7eb2e8f9f7 152 * @{
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /** @addtogroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 156 * @brief Initialization and Configuration functions.
<> 144:ef7eb2e8f9f7 157 *
<> 144:ef7eb2e8f9f7 158 @verbatim
<> 144:ef7eb2e8f9f7 159 ==============================================================================
<> 144:ef7eb2e8f9f7 160 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 161 ==============================================================================
<> 144:ef7eb2e8f9f7 162 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 163 (+) Initialize the CRYP according to the specified parameters
<> 144:ef7eb2e8f9f7 164 in the CRYP_InitTypeDef and creates the associated handle
<> 144:ef7eb2e8f9f7 165 (+) DeInitialize the CRYP peripheral
<> 144:ef7eb2e8f9f7 166 (+) Initialize the CRYP MSP
<> 144:ef7eb2e8f9f7 167 (+) DeInitialize CRYP MSP
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 @endverbatim
<> 144:ef7eb2e8f9f7 170 * @{
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /**
<> 144:ef7eb2e8f9f7 174 * @brief Initializes the CRYP according to the specified
<> 144:ef7eb2e8f9f7 175 * parameters in the CRYP_InitTypeDef and creates the associated handle.
<> 144:ef7eb2e8f9f7 176 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 177 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 178 * @retval HAL status
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
<> 144:ef7eb2e8f9f7 181 {
<> 144:ef7eb2e8f9f7 182 /* Check the CRYP handle allocation */
<> 144:ef7eb2e8f9f7 183 if(hcryp == NULL)
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Check the parameters */
<> 144:ef7eb2e8f9f7 189 assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance));
<> 144:ef7eb2e8f9f7 190 assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 if(hcryp->State == HAL_CRYP_STATE_RESET)
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 195 hcryp->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 198 HAL_CRYP_MspInit(hcryp);
<> 144:ef7eb2e8f9f7 199 }
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Check if AES already enabled */
<> 144:ef7eb2e8f9f7 202 if (HAL_IS_BIT_CLR(hcryp->Instance->CR, AES_CR_EN))
<> 144:ef7eb2e8f9f7 203 {
<> 144:ef7eb2e8f9f7 204 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 205 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Set the data type*/
<> 144:ef7eb2e8f9f7 208 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Reset CrypInCount and CrypOutCount */
<> 144:ef7eb2e8f9f7 211 hcryp->CrypInCount = 0;
<> 144:ef7eb2e8f9f7 212 hcryp->CrypOutCount = 0;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 215 hcryp->State = HAL_CRYP_STATE_READY;
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Set the default CRYP phase */
<> 144:ef7eb2e8f9f7 218 hcryp->Phase = HAL_CRYP_PHASE_READY;
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* Return function status */
<> 144:ef7eb2e8f9f7 221 return HAL_OK;
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223 else
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 /* The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is */
<> 144:ef7eb2e8f9f7 226 /* enabled is forbidden to avoid unpredictable AES behavior.*/
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Return function status */
<> 144:ef7eb2e8f9f7 229 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @brief DeInitializes the CRYP peripheral.
<> 144:ef7eb2e8f9f7 236 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 237 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 238 * @retval HAL status
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 /* Check the CRYP handle allocation */
<> 144:ef7eb2e8f9f7 243 if(hcryp == NULL)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 249 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Set the default CRYP phase */
<> 144:ef7eb2e8f9f7 252 hcryp->Phase = HAL_CRYP_PHASE_READY;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Reset CrypInCount and CrypOutCount */
<> 144:ef7eb2e8f9f7 255 hcryp->CrypInCount = 0;
<> 144:ef7eb2e8f9f7 256 hcryp->CrypOutCount = 0;
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* Disable the CRYP Peripheral Clock */
<> 144:ef7eb2e8f9f7 259 __HAL_CRYP_DISABLE(hcryp);
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /* DeInit the low level hardware: CLOCK, NVIC.*/
<> 144:ef7eb2e8f9f7 262 HAL_CRYP_MspDeInit(hcryp);
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 265 hcryp->State = HAL_CRYP_STATE_RESET;
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /* Release Lock */
<> 144:ef7eb2e8f9f7 268 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* Return function status */
<> 144:ef7eb2e8f9f7 271 return HAL_OK;
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @brief Initializes the CRYP MSP.
<> 144:ef7eb2e8f9f7 276 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 277 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 278 * @retval None
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 283 UNUSED(hcryp);
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 286 the HAL_CRYP_MspInit can be implemented in the user file */
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @brief DeInitializes CRYP MSP.
<> 144:ef7eb2e8f9f7 291 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 292 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 293 * @retval None
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 298 UNUSED(hcryp);
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 301 the HAL_CRYP_MspDeInit can be implemented in the user file */
<> 144:ef7eb2e8f9f7 302 }
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /**
<> 144:ef7eb2e8f9f7 305 * @}
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /** @addtogroup CRYP_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 309 * @brief processing functions.
<> 144:ef7eb2e8f9f7 310 *
<> 144:ef7eb2e8f9f7 311 @verbatim
<> 144:ef7eb2e8f9f7 312 ==============================================================================
<> 144:ef7eb2e8f9f7 313 ##### AES processing functions #####
<> 144:ef7eb2e8f9f7 314 ==============================================================================
<> 144:ef7eb2e8f9f7 315 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 316 (+) Encrypt plaintext using AES algorithm in different chaining modes
<> 144:ef7eb2e8f9f7 317 (+) Decrypt cyphertext using AES algorithm in different chaining modes
<> 144:ef7eb2e8f9f7 318 [..] Three processing functions are available:
<> 144:ef7eb2e8f9f7 319 (+) Polling mode
<> 144:ef7eb2e8f9f7 320 (+) Interrupt mode
<> 144:ef7eb2e8f9f7 321 (+) DMA mode
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 @endverbatim
<> 144:ef7eb2e8f9f7 324 * @{
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /**
<> 144:ef7eb2e8f9f7 328 * @brief Initializes the CRYP peripheral in AES ECB encryption mode
<> 144:ef7eb2e8f9f7 329 * then encrypt pPlainData. The cypher data are available in pCypherData
<> 144:ef7eb2e8f9f7 330 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 331 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 332 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 333 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
<> 144:ef7eb2e8f9f7 334 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 335 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 336 * @retval HAL status
<> 144:ef7eb2e8f9f7 337 */
<> 144:ef7eb2e8f9f7 338 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 339 {
<> 144:ef7eb2e8f9f7 340 /* Process Locked */
<> 144:ef7eb2e8f9f7 341 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Check that data aligned on u32 and Size multiple of 16*/
<> 144:ef7eb2e8f9f7 344 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 345 {
<> 144:ef7eb2e8f9f7 346 /* Process Locked */
<> 144:ef7eb2e8f9f7 347 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Return function status */
<> 144:ef7eb2e8f9f7 350 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 351 }
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /* Check if HAL_CRYP_Init has been called */
<> 144:ef7eb2e8f9f7 354 if(hcryp->State != HAL_CRYP_STATE_RESET)
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 357 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 360 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 /* Set the key */
<> 144:ef7eb2e8f9f7 363 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 366 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /* Set the CRYP peripheral in AES ECB mode */
<> 144:ef7eb2e8f9f7 369 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Enable CRYP */
<> 144:ef7eb2e8f9f7 372 __HAL_CRYP_ENABLE(hcryp);
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Set the phase */
<> 144:ef7eb2e8f9f7 375 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Write Plain Data and Get Cypher Data */
<> 144:ef7eb2e8f9f7 379 if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 380 {
<> 144:ef7eb2e8f9f7 381 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 385 hcryp->State = HAL_CRYP_STATE_READY;
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 388 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /* Return function status */
<> 144:ef7eb2e8f9f7 391 return HAL_OK;
<> 144:ef7eb2e8f9f7 392 }
<> 144:ef7eb2e8f9f7 393 else
<> 144:ef7eb2e8f9f7 394 {
<> 144:ef7eb2e8f9f7 395 /* Process Locked */
<> 144:ef7eb2e8f9f7 396 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /* Return function status */
<> 144:ef7eb2e8f9f7 399 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /**
<> 144:ef7eb2e8f9f7 404 * @brief Initializes the CRYP peripheral in AES CBC encryption mode
<> 144:ef7eb2e8f9f7 405 * then encrypt pPlainData. The cypher data are available in pCypherData
<> 144:ef7eb2e8f9f7 406 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 407 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 408 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 409 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
<> 144:ef7eb2e8f9f7 410 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 411 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 412 * @retval HAL status
<> 144:ef7eb2e8f9f7 413 */
<> 144:ef7eb2e8f9f7 414 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 /* Process Locked */
<> 144:ef7eb2e8f9f7 417 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 420 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 /* Process Locked */
<> 144:ef7eb2e8f9f7 423 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Return function status */
<> 144:ef7eb2e8f9f7 426 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Check if HAL_CRYP_Init has been called */
<> 144:ef7eb2e8f9f7 430 if(hcryp->State != HAL_CRYP_STATE_RESET)
<> 144:ef7eb2e8f9f7 431 {
<> 144:ef7eb2e8f9f7 432 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 433 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 436 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 437 {
<> 144:ef7eb2e8f9f7 438 /* Set the key */
<> 144:ef7eb2e8f9f7 439 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 442 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Set the CRYP peripheral in AES CBC mode */
<> 144:ef7eb2e8f9f7 445 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Set the Initialization Vector */
<> 144:ef7eb2e8f9f7 448 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Enable CRYP */
<> 144:ef7eb2e8f9f7 451 __HAL_CRYP_ENABLE(hcryp);
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* Set the phase */
<> 144:ef7eb2e8f9f7 454 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 455 }
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /* Write Plain Data and Get Cypher Data */
<> 144:ef7eb2e8f9f7 458 if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 459 {
<> 144:ef7eb2e8f9f7 460 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 464 hcryp->State = HAL_CRYP_STATE_READY;
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 467 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Return function status */
<> 144:ef7eb2e8f9f7 470 return HAL_OK;
<> 144:ef7eb2e8f9f7 471 }
<> 144:ef7eb2e8f9f7 472 else
<> 144:ef7eb2e8f9f7 473 {
<> 144:ef7eb2e8f9f7 474 /* Process Locked */
<> 144:ef7eb2e8f9f7 475 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* Return function status */
<> 144:ef7eb2e8f9f7 478 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 479 }
<> 144:ef7eb2e8f9f7 480 }
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /**
<> 144:ef7eb2e8f9f7 483 * @brief Initializes the CRYP peripheral in AES CTR encryption mode
<> 144:ef7eb2e8f9f7 484 * then encrypt pPlainData. The cypher data are available in pCypherData
<> 144:ef7eb2e8f9f7 485 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 486 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 487 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 488 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
<> 144:ef7eb2e8f9f7 489 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 490 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 491 * @retval HAL status
<> 144:ef7eb2e8f9f7 492 */
<> 144:ef7eb2e8f9f7 493 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 494 {
<> 144:ef7eb2e8f9f7 495 /* Process Locked */
<> 144:ef7eb2e8f9f7 496 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 499 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 500 {
<> 144:ef7eb2e8f9f7 501 /* Process Locked */
<> 144:ef7eb2e8f9f7 502 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Return function status */
<> 144:ef7eb2e8f9f7 505 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Check if HAL_CRYP_Init has been called */
<> 144:ef7eb2e8f9f7 509 if(hcryp->State != HAL_CRYP_STATE_RESET)
<> 144:ef7eb2e8f9f7 510 {
<> 144:ef7eb2e8f9f7 511 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 512 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 515 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 /* Set the key */
<> 144:ef7eb2e8f9f7 518 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 521 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /* Set the CRYP peripheral in AES CTR mode */
<> 144:ef7eb2e8f9f7 524 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Set the Initialization Vector */
<> 144:ef7eb2e8f9f7 527 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Enable CRYP */
<> 144:ef7eb2e8f9f7 530 __HAL_CRYP_ENABLE(hcryp);
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* Set the phase */
<> 144:ef7eb2e8f9f7 533 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 534 }
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Write Plain Data and Get Cypher Data */
<> 144:ef7eb2e8f9f7 537 if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 538 {
<> 144:ef7eb2e8f9f7 539 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 540 }
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 543 hcryp->State = HAL_CRYP_STATE_READY;
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 546 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /* Return function status */
<> 144:ef7eb2e8f9f7 549 return HAL_OK;
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551 else
<> 144:ef7eb2e8f9f7 552 {
<> 144:ef7eb2e8f9f7 553 /* Release Lock */
<> 144:ef7eb2e8f9f7 554 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /* Return function status */
<> 144:ef7eb2e8f9f7 557 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 558 }
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /**
<> 144:ef7eb2e8f9f7 562 * @brief Initializes the CRYP peripheral in AES ECB decryption mode
<> 144:ef7eb2e8f9f7 563 * then decrypted pCypherData. The cypher data are available in pPlainData
<> 144:ef7eb2e8f9f7 564 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 565 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 566 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 567 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
<> 144:ef7eb2e8f9f7 568 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 569 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 570 * @retval HAL status
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 /* Process Locked */
<> 144:ef7eb2e8f9f7 575 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 578 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 /* Process Locked */
<> 144:ef7eb2e8f9f7 581 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* Return function status */
<> 144:ef7eb2e8f9f7 584 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /* Check if HAL_CRYP_Init has been called */
<> 144:ef7eb2e8f9f7 588 if(hcryp->State != HAL_CRYP_STATE_RESET)
<> 144:ef7eb2e8f9f7 589 {
<> 144:ef7eb2e8f9f7 590 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 591 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 594 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 595 {
<> 144:ef7eb2e8f9f7 596 /* Set the key */
<> 144:ef7eb2e8f9f7 597 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 600 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
<> 144:ef7eb2e8f9f7 603 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /* Enable CRYP */
<> 144:ef7eb2e8f9f7 606 __HAL_CRYP_ENABLE(hcryp);
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /* Set the phase */
<> 144:ef7eb2e8f9f7 609 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 610 }
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Write Cypher Data and Get Plain Data */
<> 144:ef7eb2e8f9f7 613 if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 614 {
<> 144:ef7eb2e8f9f7 615 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 616 }
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 619 hcryp->State = HAL_CRYP_STATE_READY;
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 622 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Return function status */
<> 144:ef7eb2e8f9f7 625 return HAL_OK;
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627 else
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 /* Release Lock */
<> 144:ef7eb2e8f9f7 630 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Return function status */
<> 144:ef7eb2e8f9f7 633 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635 }
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /**
<> 144:ef7eb2e8f9f7 638 * @brief Initializes the CRYP peripheral in AES ECB decryption mode
<> 144:ef7eb2e8f9f7 639 * then decrypted pCypherData. The cypher data are available in pPlainData
<> 144:ef7eb2e8f9f7 640 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 641 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 642 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 643 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
<> 144:ef7eb2e8f9f7 644 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 645 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 646 * @retval HAL status
<> 144:ef7eb2e8f9f7 647 */
<> 144:ef7eb2e8f9f7 648 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 /* Process Locked */
<> 144:ef7eb2e8f9f7 651 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 654 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 655 {
<> 144:ef7eb2e8f9f7 656 /* Process Locked */
<> 144:ef7eb2e8f9f7 657 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /* Return function status */
<> 144:ef7eb2e8f9f7 660 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /* Check if HAL_CRYP_Init has been called */
<> 144:ef7eb2e8f9f7 664 if(hcryp->State != HAL_CRYP_STATE_RESET)
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 667 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 670 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 /* Set the key */
<> 144:ef7eb2e8f9f7 673 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 676 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
<> 144:ef7eb2e8f9f7 679 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /* Set the Initialization Vector */
<> 144:ef7eb2e8f9f7 682 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* Enable CRYP */
<> 144:ef7eb2e8f9f7 685 __HAL_CRYP_ENABLE(hcryp);
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* Set the phase */
<> 144:ef7eb2e8f9f7 688 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /* Write Cypher Data and Get Plain Data */
<> 144:ef7eb2e8f9f7 692 if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 693 {
<> 144:ef7eb2e8f9f7 694 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 695 }
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 698 hcryp->State = HAL_CRYP_STATE_READY;
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 701 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /* Return function status */
<> 144:ef7eb2e8f9f7 704 return HAL_OK;
<> 144:ef7eb2e8f9f7 705 }
<> 144:ef7eb2e8f9f7 706 else
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 /* Release Lock */
<> 144:ef7eb2e8f9f7 709 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 /* Return function status */
<> 144:ef7eb2e8f9f7 712 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 713 }
<> 144:ef7eb2e8f9f7 714 }
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /**
<> 144:ef7eb2e8f9f7 717 * @brief Initializes the CRYP peripheral in AES CTR decryption mode
<> 144:ef7eb2e8f9f7 718 * then decrypted pCypherData. The cypher data are available in pPlainData
<> 144:ef7eb2e8f9f7 719 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 720 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 721 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 722 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
<> 144:ef7eb2e8f9f7 723 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 724 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 725 * @retval HAL status
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 728 {
<> 144:ef7eb2e8f9f7 729 /* Process Locked */
<> 144:ef7eb2e8f9f7 730 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 733 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 734 {
<> 144:ef7eb2e8f9f7 735 /* Process Locked */
<> 144:ef7eb2e8f9f7 736 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /* Return function status */
<> 144:ef7eb2e8f9f7 739 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 740 }
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 743 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->Phase == HAL_CRYP_PHASE_READY))
<> 144:ef7eb2e8f9f7 744 {
<> 144:ef7eb2e8f9f7 745 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 746 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Set the key */
<> 144:ef7eb2e8f9f7 749 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 752 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Set the CRYP peripheral in AES CTR decryption mode */
<> 144:ef7eb2e8f9f7 755 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /* Set the Initialization Vector */
<> 144:ef7eb2e8f9f7 758 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 /* Enable CRYP */
<> 144:ef7eb2e8f9f7 761 __HAL_CRYP_ENABLE(hcryp);
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /* Set the phase */
<> 144:ef7eb2e8f9f7 764 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 765 }
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /* Write Cypher Data and Get Plain Data */
<> 144:ef7eb2e8f9f7 768 if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 769 {
<> 144:ef7eb2e8f9f7 770 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 771 }
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 774 hcryp->State = HAL_CRYP_STATE_READY;
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 777 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 /* Return function status */
<> 144:ef7eb2e8f9f7 780 return HAL_OK;
<> 144:ef7eb2e8f9f7 781 }
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /**
<> 144:ef7eb2e8f9f7 784 * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
<> 144:ef7eb2e8f9f7 785 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 786 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 787 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 788 * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
<> 144:ef7eb2e8f9f7 789 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 790 * @retval HAL status
<> 144:ef7eb2e8f9f7 791 */
<> 144:ef7eb2e8f9f7 792 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
<> 144:ef7eb2e8f9f7 793 {
<> 144:ef7eb2e8f9f7 794 uint32_t inputaddr = 0;
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 797 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 798 {
<> 144:ef7eb2e8f9f7 799 /* Process Locked */
<> 144:ef7eb2e8f9f7 800 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /* Return function status */
<> 144:ef7eb2e8f9f7 803 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 804 }
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
<> 144:ef7eb2e8f9f7 807 {
<> 144:ef7eb2e8f9f7 808 /* Process Locked */
<> 144:ef7eb2e8f9f7 809 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /* Get the buffer addresses and sizes */
<> 144:ef7eb2e8f9f7 812 hcryp->CrypInCount = Size;
<> 144:ef7eb2e8f9f7 813 hcryp->pCrypInBuffPtr = pPlainData;
<> 144:ef7eb2e8f9f7 814 hcryp->pCrypOutBuffPtr = pCypherData;
<> 144:ef7eb2e8f9f7 815 hcryp->CrypOutCount = Size;
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 818 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 821 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 /* Set the key */
<> 144:ef7eb2e8f9f7 824 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 827 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /* Set the CRYP peripheral in AES ECB mode */
<> 144:ef7eb2e8f9f7 830 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /* Set the phase */
<> 144:ef7eb2e8f9f7 833 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Enable Interrupts */
<> 144:ef7eb2e8f9f7 837 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Enable CRYP */
<> 144:ef7eb2e8f9f7 840 __HAL_CRYP_ENABLE(hcryp);
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /* Get the last input data adress */
<> 144:ef7eb2e8f9f7 843 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /* Write the Input block in the Data Input register */
<> 144:ef7eb2e8f9f7 846 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 847 inputaddr+=4;
<> 144:ef7eb2e8f9f7 848 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 849 inputaddr+=4;
<> 144:ef7eb2e8f9f7 850 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 851 inputaddr+=4;
<> 144:ef7eb2e8f9f7 852 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 853 hcryp->pCrypInBuffPtr += 16;
<> 144:ef7eb2e8f9f7 854 hcryp->CrypInCount -= 16;
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* Return function status */
<> 144:ef7eb2e8f9f7 857 return HAL_OK;
<> 144:ef7eb2e8f9f7 858 }
<> 144:ef7eb2e8f9f7 859 else
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 /* Release Lock */
<> 144:ef7eb2e8f9f7 862 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /* Return function status */
<> 144:ef7eb2e8f9f7 865 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 866 }
<> 144:ef7eb2e8f9f7 867 }
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /**
<> 144:ef7eb2e8f9f7 870 * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
<> 144:ef7eb2e8f9f7 871 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 872 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 873 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 874 * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
<> 144:ef7eb2e8f9f7 875 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 876 * @retval HAL status
<> 144:ef7eb2e8f9f7 877 */
<> 144:ef7eb2e8f9f7 878 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
<> 144:ef7eb2e8f9f7 879 {
<> 144:ef7eb2e8f9f7 880 uint32_t inputaddr = 0;
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 883 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 884 {
<> 144:ef7eb2e8f9f7 885 /* Process Locked */
<> 144:ef7eb2e8f9f7 886 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /* Return function status */
<> 144:ef7eb2e8f9f7 889 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 890 }
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
<> 144:ef7eb2e8f9f7 893 {
<> 144:ef7eb2e8f9f7 894 /* Process Locked */
<> 144:ef7eb2e8f9f7 895 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /* Get the buffer addresses and sizes */
<> 144:ef7eb2e8f9f7 898 hcryp->CrypInCount = Size;
<> 144:ef7eb2e8f9f7 899 hcryp->pCrypInBuffPtr = pPlainData;
<> 144:ef7eb2e8f9f7 900 hcryp->pCrypOutBuffPtr = pCypherData;
<> 144:ef7eb2e8f9f7 901 hcryp->CrypOutCount = Size;
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 904 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 907 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 908 {
<> 144:ef7eb2e8f9f7 909 /* Set the key */
<> 144:ef7eb2e8f9f7 910 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 913 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* Set the CRYP peripheral in AES CBC mode */
<> 144:ef7eb2e8f9f7 916 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /* Set the Initialization Vector */
<> 144:ef7eb2e8f9f7 919 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Set the phase */
<> 144:ef7eb2e8f9f7 922 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 923 }
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /* Enable Interrupts */
<> 144:ef7eb2e8f9f7 926 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 /* Enable CRYP */
<> 144:ef7eb2e8f9f7 929 __HAL_CRYP_ENABLE(hcryp);
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /* Get the last input data adress */
<> 144:ef7eb2e8f9f7 932 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 /* Write the Input block in the Data Input register */
<> 144:ef7eb2e8f9f7 935 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 936 inputaddr+=4;
<> 144:ef7eb2e8f9f7 937 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 938 inputaddr+=4;
<> 144:ef7eb2e8f9f7 939 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 940 inputaddr+=4;
<> 144:ef7eb2e8f9f7 941 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 942 hcryp->pCrypInBuffPtr += 16;
<> 144:ef7eb2e8f9f7 943 hcryp->CrypInCount -= 16;
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 /* Return function status */
<> 144:ef7eb2e8f9f7 946 return HAL_OK;
<> 144:ef7eb2e8f9f7 947 }
<> 144:ef7eb2e8f9f7 948 else
<> 144:ef7eb2e8f9f7 949 {
<> 144:ef7eb2e8f9f7 950 /* Release Lock */
<> 144:ef7eb2e8f9f7 951 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /* Return function status */
<> 144:ef7eb2e8f9f7 954 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 955 }
<> 144:ef7eb2e8f9f7 956 }
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /**
<> 144:ef7eb2e8f9f7 959 * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
<> 144:ef7eb2e8f9f7 960 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 961 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 962 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 963 * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
<> 144:ef7eb2e8f9f7 964 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 965 * @retval HAL status
<> 144:ef7eb2e8f9f7 966 */
<> 144:ef7eb2e8f9f7 967 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
<> 144:ef7eb2e8f9f7 968 {
<> 144:ef7eb2e8f9f7 969 uint32_t inputaddr = 0;
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 972 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 973 {
<> 144:ef7eb2e8f9f7 974 /* Process Locked */
<> 144:ef7eb2e8f9f7 975 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /* Return function status */
<> 144:ef7eb2e8f9f7 978 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 979 }
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
<> 144:ef7eb2e8f9f7 982 {
<> 144:ef7eb2e8f9f7 983 /* Process Locked */
<> 144:ef7eb2e8f9f7 984 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 985
<> 144:ef7eb2e8f9f7 986 /* Get the buffer addresses and sizes */
<> 144:ef7eb2e8f9f7 987 hcryp->CrypInCount = Size;
<> 144:ef7eb2e8f9f7 988 hcryp->pCrypInBuffPtr = pPlainData;
<> 144:ef7eb2e8f9f7 989 hcryp->pCrypOutBuffPtr = pCypherData;
<> 144:ef7eb2e8f9f7 990 hcryp->CrypOutCount = Size;
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 993 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 996 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 997 {
<> 144:ef7eb2e8f9f7 998 /* Set the key */
<> 144:ef7eb2e8f9f7 999 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 1002 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 /* Set the CRYP peripheral in AES CTR mode */
<> 144:ef7eb2e8f9f7 1005 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Set the Initialization Vector */
<> 144:ef7eb2e8f9f7 1008 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* Set the phase */
<> 144:ef7eb2e8f9f7 1011 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1012 }
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 /* Enable Interrupts */
<> 144:ef7eb2e8f9f7 1015 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /* Enable CRYP */
<> 144:ef7eb2e8f9f7 1018 __HAL_CRYP_ENABLE(hcryp);
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* Get the last input data adress */
<> 144:ef7eb2e8f9f7 1021 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /* Write the Input block in the Data Input register */
<> 144:ef7eb2e8f9f7 1024 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1025 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1026 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1027 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1028 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1029 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1030 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1031 hcryp->pCrypInBuffPtr += 16;
<> 144:ef7eb2e8f9f7 1032 hcryp->CrypInCount -= 16;
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /* Return function status */
<> 144:ef7eb2e8f9f7 1035 return HAL_OK;
<> 144:ef7eb2e8f9f7 1036 }
<> 144:ef7eb2e8f9f7 1037 else
<> 144:ef7eb2e8f9f7 1038 {
<> 144:ef7eb2e8f9f7 1039 /* Release Lock */
<> 144:ef7eb2e8f9f7 1040 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1041
<> 144:ef7eb2e8f9f7 1042 /* Return function status */
<> 144:ef7eb2e8f9f7 1043 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1044 }
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /**
<> 144:ef7eb2e8f9f7 1048 * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
<> 144:ef7eb2e8f9f7 1049 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1050 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1051 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1052 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
<> 144:ef7eb2e8f9f7 1053 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1054 * @retval HAL status
<> 144:ef7eb2e8f9f7 1055 */
<> 144:ef7eb2e8f9f7 1056 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
<> 144:ef7eb2e8f9f7 1057 {
<> 144:ef7eb2e8f9f7 1058 uint32_t inputaddr = 0;
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 1061 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 1062 {
<> 144:ef7eb2e8f9f7 1063 /* Process Locked */
<> 144:ef7eb2e8f9f7 1064 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 /* Return function status */
<> 144:ef7eb2e8f9f7 1067 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1068 }
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
<> 144:ef7eb2e8f9f7 1071 {
<> 144:ef7eb2e8f9f7 1072 /* Process Locked */
<> 144:ef7eb2e8f9f7 1073 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* Get the buffer addresses and sizes */
<> 144:ef7eb2e8f9f7 1076 hcryp->CrypInCount = Size;
<> 144:ef7eb2e8f9f7 1077 hcryp->pCrypInBuffPtr = pCypherData;
<> 144:ef7eb2e8f9f7 1078 hcryp->pCrypOutBuffPtr = pPlainData;
<> 144:ef7eb2e8f9f7 1079 hcryp->CrypOutCount = Size;
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 1082 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1083
<> 144:ef7eb2e8f9f7 1084 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1085 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 1086 {
<> 144:ef7eb2e8f9f7 1087 /* Set the key */
<> 144:ef7eb2e8f9f7 1088 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 1091 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
<> 144:ef7eb2e8f9f7 1094 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 /* Set the phase */
<> 144:ef7eb2e8f9f7 1097 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1098 }
<> 144:ef7eb2e8f9f7 1099
<> 144:ef7eb2e8f9f7 1100 /* Enable Interrupts */
<> 144:ef7eb2e8f9f7 1101 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /* Enable CRYP */
<> 144:ef7eb2e8f9f7 1104 __HAL_CRYP_ENABLE(hcryp);
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 /* Get the last input data adress */
<> 144:ef7eb2e8f9f7 1107 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109 /* Write the Input block in the Data Input register */
<> 144:ef7eb2e8f9f7 1110 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1111 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1112 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1113 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1114 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1115 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1116 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1117 hcryp->pCrypInBuffPtr += 16;
<> 144:ef7eb2e8f9f7 1118 hcryp->CrypInCount -= 16;
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 /* Return function status */
<> 144:ef7eb2e8f9f7 1121 return HAL_OK;
<> 144:ef7eb2e8f9f7 1122 }
<> 144:ef7eb2e8f9f7 1123 else
<> 144:ef7eb2e8f9f7 1124 {
<> 144:ef7eb2e8f9f7 1125 /* Release Lock */
<> 144:ef7eb2e8f9f7 1126 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 /* Return function status */
<> 144:ef7eb2e8f9f7 1129 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1130 }
<> 144:ef7eb2e8f9f7 1131 }
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 /**
<> 144:ef7eb2e8f9f7 1134 * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.
<> 144:ef7eb2e8f9f7 1135 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1136 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1137 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1138 * @param Size: Length of the plaintext buffer, must be a multiple of 16
<> 144:ef7eb2e8f9f7 1139 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1140 * @retval HAL status
<> 144:ef7eb2e8f9f7 1141 */
<> 144:ef7eb2e8f9f7 1142 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
<> 144:ef7eb2e8f9f7 1143 {
<> 144:ef7eb2e8f9f7 1144 uint32_t inputaddr = 0;
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 1147 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 1148 {
<> 144:ef7eb2e8f9f7 1149 /* Process Locked */
<> 144:ef7eb2e8f9f7 1150 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 /* Return function status */
<> 144:ef7eb2e8f9f7 1153 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1154 }
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
<> 144:ef7eb2e8f9f7 1157 {
<> 144:ef7eb2e8f9f7 1158 /* Process Locked */
<> 144:ef7eb2e8f9f7 1159 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /* Get the buffer addresses and sizes */
<> 144:ef7eb2e8f9f7 1162 hcryp->CrypInCount = Size;
<> 144:ef7eb2e8f9f7 1163 hcryp->pCrypInBuffPtr = pCypherData;
<> 144:ef7eb2e8f9f7 1164 hcryp->pCrypOutBuffPtr = pPlainData;
<> 144:ef7eb2e8f9f7 1165 hcryp->CrypOutCount = Size;
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 1168 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1171 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 1172 {
<> 144:ef7eb2e8f9f7 1173 /* Set the key */
<> 144:ef7eb2e8f9f7 1174 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 1177 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
<> 144:ef7eb2e8f9f7 1180 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 /* Set the Initialization Vector */
<> 144:ef7eb2e8f9f7 1183 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 /* Set the phase */
<> 144:ef7eb2e8f9f7 1186 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1187 }
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /* Enable Interrupts */
<> 144:ef7eb2e8f9f7 1190 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
<> 144:ef7eb2e8f9f7 1191
<> 144:ef7eb2e8f9f7 1192 /* Enable CRYP */
<> 144:ef7eb2e8f9f7 1193 __HAL_CRYP_ENABLE(hcryp);
<> 144:ef7eb2e8f9f7 1194
<> 144:ef7eb2e8f9f7 1195 /* Get the last input data adress */
<> 144:ef7eb2e8f9f7 1196 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 /* Write the Input block in the Data Input register */
<> 144:ef7eb2e8f9f7 1199 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1200 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1201 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1202 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1203 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1204 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1205 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1206 hcryp->pCrypInBuffPtr += 16;
<> 144:ef7eb2e8f9f7 1207 hcryp->CrypInCount -= 16;
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /* Return function status */
<> 144:ef7eb2e8f9f7 1210 return HAL_OK;
<> 144:ef7eb2e8f9f7 1211 }
<> 144:ef7eb2e8f9f7 1212 else
<> 144:ef7eb2e8f9f7 1213 {
<> 144:ef7eb2e8f9f7 1214 /* Release Lock */
<> 144:ef7eb2e8f9f7 1215 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1216
<> 144:ef7eb2e8f9f7 1217 /* Return function status */
<> 144:ef7eb2e8f9f7 1218 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1219 }
<> 144:ef7eb2e8f9f7 1220 }
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 /**
<> 144:ef7eb2e8f9f7 1223 * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
<> 144:ef7eb2e8f9f7 1224 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1225 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1226 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1227 * @param Size: Length of the plaintext buffer, must be a multiple of 16
<> 144:ef7eb2e8f9f7 1228 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1229 * @retval HAL status
<> 144:ef7eb2e8f9f7 1230 */
<> 144:ef7eb2e8f9f7 1231 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
<> 144:ef7eb2e8f9f7 1232 {
<> 144:ef7eb2e8f9f7 1233 uint32_t inputaddr = 0;
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 1236 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 1237 {
<> 144:ef7eb2e8f9f7 1238 /* Process Locked */
<> 144:ef7eb2e8f9f7 1239 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 /* Return function status */
<> 144:ef7eb2e8f9f7 1242 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1243 }
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
<> 144:ef7eb2e8f9f7 1246 {
<> 144:ef7eb2e8f9f7 1247 /* Process Locked */
<> 144:ef7eb2e8f9f7 1248 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 1249
<> 144:ef7eb2e8f9f7 1250 /* Get the buffer addresses and sizes */
<> 144:ef7eb2e8f9f7 1251 hcryp->CrypInCount = Size;
<> 144:ef7eb2e8f9f7 1252 hcryp->pCrypInBuffPtr = pCypherData;
<> 144:ef7eb2e8f9f7 1253 hcryp->pCrypOutBuffPtr = pPlainData;
<> 144:ef7eb2e8f9f7 1254 hcryp->CrypOutCount = Size;
<> 144:ef7eb2e8f9f7 1255
<> 144:ef7eb2e8f9f7 1256 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 1257 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1260 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 1261 {
<> 144:ef7eb2e8f9f7 1262 /* Set the key */
<> 144:ef7eb2e8f9f7 1263 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 1266 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 /* Set the CRYP peripheral in AES CTR decryption mode */
<> 144:ef7eb2e8f9f7 1269 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
<> 144:ef7eb2e8f9f7 1270
<> 144:ef7eb2e8f9f7 1271 /* Set the Initialization Vector */
<> 144:ef7eb2e8f9f7 1272 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
<> 144:ef7eb2e8f9f7 1273
<> 144:ef7eb2e8f9f7 1274 /* Set the phase */
<> 144:ef7eb2e8f9f7 1275 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1276 }
<> 144:ef7eb2e8f9f7 1277
<> 144:ef7eb2e8f9f7 1278 /* Enable Interrupts */
<> 144:ef7eb2e8f9f7 1279 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 /* Enable CRYP */
<> 144:ef7eb2e8f9f7 1282 __HAL_CRYP_ENABLE(hcryp);
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 /* Get the last input data adress */
<> 144:ef7eb2e8f9f7 1285 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /* Write the Input block in the Data Input register */
<> 144:ef7eb2e8f9f7 1288 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1289 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1290 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1291 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1292 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1293 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1294 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1295 hcryp->pCrypInBuffPtr += 16;
<> 144:ef7eb2e8f9f7 1296 hcryp->CrypInCount -= 16;
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 /* Return function status */
<> 144:ef7eb2e8f9f7 1299 return HAL_OK;
<> 144:ef7eb2e8f9f7 1300 }
<> 144:ef7eb2e8f9f7 1301 else
<> 144:ef7eb2e8f9f7 1302 {
<> 144:ef7eb2e8f9f7 1303 /* Release Lock */
<> 144:ef7eb2e8f9f7 1304 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1305
<> 144:ef7eb2e8f9f7 1306 /* Return function status */
<> 144:ef7eb2e8f9f7 1307 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1308 }
<> 144:ef7eb2e8f9f7 1309 }
<> 144:ef7eb2e8f9f7 1310
<> 144:ef7eb2e8f9f7 1311 /**
<> 144:ef7eb2e8f9f7 1312 * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
<> 144:ef7eb2e8f9f7 1313 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1314 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1315 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1316 * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
<> 144:ef7eb2e8f9f7 1317 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1318 * @retval HAL status
<> 144:ef7eb2e8f9f7 1319 */
<> 144:ef7eb2e8f9f7 1320 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
<> 144:ef7eb2e8f9f7 1321 {
<> 144:ef7eb2e8f9f7 1322 uint32_t inputaddr = 0, outputaddr = 0;
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 1325 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 1326 {
<> 144:ef7eb2e8f9f7 1327 /* Process Locked */
<> 144:ef7eb2e8f9f7 1328 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /* Return function status */
<> 144:ef7eb2e8f9f7 1331 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1332 }
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334 /* Check if HAL_CRYP_Init has been called */
<> 144:ef7eb2e8f9f7 1335 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
<> 144:ef7eb2e8f9f7 1336 {
<> 144:ef7eb2e8f9f7 1337 /* Process Locked */
<> 144:ef7eb2e8f9f7 1338 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 1339
<> 144:ef7eb2e8f9f7 1340 inputaddr = (uint32_t)pPlainData;
<> 144:ef7eb2e8f9f7 1341 outputaddr = (uint32_t)pCypherData;
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 1344 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1345
<> 144:ef7eb2e8f9f7 1346 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1347 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 1348 {
<> 144:ef7eb2e8f9f7 1349 /* Set the key */
<> 144:ef7eb2e8f9f7 1350 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 /* Set the CRYP peripheral in AES ECB mode */
<> 144:ef7eb2e8f9f7 1353 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
<> 144:ef7eb2e8f9f7 1354
<> 144:ef7eb2e8f9f7 1355 /* Set the phase */
<> 144:ef7eb2e8f9f7 1356 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1357 }
<> 144:ef7eb2e8f9f7 1358 /* Set the input and output addresses and start DMA transfer */
<> 144:ef7eb2e8f9f7 1359 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
<> 144:ef7eb2e8f9f7 1360
<> 144:ef7eb2e8f9f7 1361 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1362 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 /* Return function status */
<> 144:ef7eb2e8f9f7 1365 return HAL_OK;
<> 144:ef7eb2e8f9f7 1366 }
<> 144:ef7eb2e8f9f7 1367 else
<> 144:ef7eb2e8f9f7 1368 {
<> 144:ef7eb2e8f9f7 1369 /* Release Lock */
<> 144:ef7eb2e8f9f7 1370 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1371
<> 144:ef7eb2e8f9f7 1372 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1373 }
<> 144:ef7eb2e8f9f7 1374 }
<> 144:ef7eb2e8f9f7 1375
<> 144:ef7eb2e8f9f7 1376 /**
<> 144:ef7eb2e8f9f7 1377 * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
<> 144:ef7eb2e8f9f7 1378 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1379 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1380 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1381 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
<> 144:ef7eb2e8f9f7 1382 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1383 * @retval HAL status
<> 144:ef7eb2e8f9f7 1384 */
<> 144:ef7eb2e8f9f7 1385 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
<> 144:ef7eb2e8f9f7 1386 {
<> 144:ef7eb2e8f9f7 1387 uint32_t inputaddr = 0, outputaddr = 0;
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 1390 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 1391 {
<> 144:ef7eb2e8f9f7 1392 /* Process Locked */
<> 144:ef7eb2e8f9f7 1393 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1394
<> 144:ef7eb2e8f9f7 1395 /* Return function status */
<> 144:ef7eb2e8f9f7 1396 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1397 }
<> 144:ef7eb2e8f9f7 1398
<> 144:ef7eb2e8f9f7 1399 /* Check if HAL_CRYP_Init has been called */
<> 144:ef7eb2e8f9f7 1400 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
<> 144:ef7eb2e8f9f7 1401 {
<> 144:ef7eb2e8f9f7 1402 /* Process Locked */
<> 144:ef7eb2e8f9f7 1403 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 1404
<> 144:ef7eb2e8f9f7 1405 inputaddr = (uint32_t)pPlainData;
<> 144:ef7eb2e8f9f7 1406 outputaddr = (uint32_t)pCypherData;
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 1409 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1412 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 1413 {
<> 144:ef7eb2e8f9f7 1414 /* Set the key */
<> 144:ef7eb2e8f9f7 1415 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 1416
<> 144:ef7eb2e8f9f7 1417 /* Set the CRYP peripheral in AES CBC mode */
<> 144:ef7eb2e8f9f7 1418 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
<> 144:ef7eb2e8f9f7 1419
<> 144:ef7eb2e8f9f7 1420 /* Set the Initialization Vector */
<> 144:ef7eb2e8f9f7 1421 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
<> 144:ef7eb2e8f9f7 1422
<> 144:ef7eb2e8f9f7 1423 /* Set the phase */
<> 144:ef7eb2e8f9f7 1424 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1425 }
<> 144:ef7eb2e8f9f7 1426 /* Set the input and output addresses and start DMA transfer */
<> 144:ef7eb2e8f9f7 1427 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
<> 144:ef7eb2e8f9f7 1428
<> 144:ef7eb2e8f9f7 1429 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1430 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 /* Return function status */
<> 144:ef7eb2e8f9f7 1433 return HAL_OK;
<> 144:ef7eb2e8f9f7 1434 }
<> 144:ef7eb2e8f9f7 1435 else
<> 144:ef7eb2e8f9f7 1436 {
<> 144:ef7eb2e8f9f7 1437 /* Release Lock */
<> 144:ef7eb2e8f9f7 1438 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1439
<> 144:ef7eb2e8f9f7 1440 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1441 }
<> 144:ef7eb2e8f9f7 1442 }
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 /**
<> 144:ef7eb2e8f9f7 1445 * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
<> 144:ef7eb2e8f9f7 1446 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1447 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1448 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1449 * @param Size: Length of the plaintext buffer, must be a multiple of 16.
<> 144:ef7eb2e8f9f7 1450 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1451 * @retval HAL status
<> 144:ef7eb2e8f9f7 1452 */
<> 144:ef7eb2e8f9f7 1453 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
<> 144:ef7eb2e8f9f7 1454 {
<> 144:ef7eb2e8f9f7 1455 uint32_t inputaddr = 0, outputaddr = 0;
<> 144:ef7eb2e8f9f7 1456
<> 144:ef7eb2e8f9f7 1457 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 1458 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 1459 {
<> 144:ef7eb2e8f9f7 1460 /* Process Locked */
<> 144:ef7eb2e8f9f7 1461 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1462
<> 144:ef7eb2e8f9f7 1463 /* Return function status */
<> 144:ef7eb2e8f9f7 1464 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1465 }
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 /* Check if HAL_CRYP_Init has been called */
<> 144:ef7eb2e8f9f7 1468 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
<> 144:ef7eb2e8f9f7 1469 {
<> 144:ef7eb2e8f9f7 1470 /* Process Locked */
<> 144:ef7eb2e8f9f7 1471 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 1472
<> 144:ef7eb2e8f9f7 1473 inputaddr = (uint32_t)pPlainData;
<> 144:ef7eb2e8f9f7 1474 outputaddr = (uint32_t)pCypherData;
<> 144:ef7eb2e8f9f7 1475
<> 144:ef7eb2e8f9f7 1476 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 1477 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1478
<> 144:ef7eb2e8f9f7 1479 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1480 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 1481 {
<> 144:ef7eb2e8f9f7 1482 /* Set the key */
<> 144:ef7eb2e8f9f7 1483 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 1484
<> 144:ef7eb2e8f9f7 1485 /* Set the CRYP peripheral in AES CTR mode */
<> 144:ef7eb2e8f9f7 1486 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
<> 144:ef7eb2e8f9f7 1487
<> 144:ef7eb2e8f9f7 1488 /* Set the Initialization Vector */
<> 144:ef7eb2e8f9f7 1489 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
<> 144:ef7eb2e8f9f7 1490
<> 144:ef7eb2e8f9f7 1491 /* Set the phase */
<> 144:ef7eb2e8f9f7 1492 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1493 }
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 /* Set the input and output addresses and start DMA transfer */
<> 144:ef7eb2e8f9f7 1496 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
<> 144:ef7eb2e8f9f7 1497
<> 144:ef7eb2e8f9f7 1498 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1499 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 /* Return function status */
<> 144:ef7eb2e8f9f7 1502 return HAL_OK;
<> 144:ef7eb2e8f9f7 1503 }
<> 144:ef7eb2e8f9f7 1504 else
<> 144:ef7eb2e8f9f7 1505 {
<> 144:ef7eb2e8f9f7 1506 /* Release Lock */
<> 144:ef7eb2e8f9f7 1507 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1508
<> 144:ef7eb2e8f9f7 1509 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1510 }
<> 144:ef7eb2e8f9f7 1511 }
<> 144:ef7eb2e8f9f7 1512
<> 144:ef7eb2e8f9f7 1513 /**
<> 144:ef7eb2e8f9f7 1514 * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
<> 144:ef7eb2e8f9f7 1515 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1516 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1517 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1518 * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
<> 144:ef7eb2e8f9f7 1519 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1520 * @retval HAL status
<> 144:ef7eb2e8f9f7 1521 */
<> 144:ef7eb2e8f9f7 1522 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
<> 144:ef7eb2e8f9f7 1523 {
<> 144:ef7eb2e8f9f7 1524 uint32_t inputaddr = 0, outputaddr = 0;
<> 144:ef7eb2e8f9f7 1525
<> 144:ef7eb2e8f9f7 1526 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 1527 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 1528 {
<> 144:ef7eb2e8f9f7 1529 /* Process Locked */
<> 144:ef7eb2e8f9f7 1530 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1531
<> 144:ef7eb2e8f9f7 1532 /* Return function status */
<> 144:ef7eb2e8f9f7 1533 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1534 }
<> 144:ef7eb2e8f9f7 1535
<> 144:ef7eb2e8f9f7 1536 /* Check if HAL_CRYP_Init has been called */
<> 144:ef7eb2e8f9f7 1537 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
<> 144:ef7eb2e8f9f7 1538 {
<> 144:ef7eb2e8f9f7 1539 /* Process Locked */
<> 144:ef7eb2e8f9f7 1540 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 1541
<> 144:ef7eb2e8f9f7 1542 inputaddr = (uint32_t)pCypherData;
<> 144:ef7eb2e8f9f7 1543 outputaddr = (uint32_t)pPlainData;
<> 144:ef7eb2e8f9f7 1544
<> 144:ef7eb2e8f9f7 1545 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 1546 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1549 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 1550 {
<> 144:ef7eb2e8f9f7 1551 /* Set the key */
<> 144:ef7eb2e8f9f7 1552 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 1553
<> 144:ef7eb2e8f9f7 1554 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 1555 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 1556
<> 144:ef7eb2e8f9f7 1557 /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
<> 144:ef7eb2e8f9f7 1558 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
<> 144:ef7eb2e8f9f7 1559
<> 144:ef7eb2e8f9f7 1560 /* Set the phase */
<> 144:ef7eb2e8f9f7 1561 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1562 }
<> 144:ef7eb2e8f9f7 1563
<> 144:ef7eb2e8f9f7 1564 /* Set the input and output addresses and start DMA transfer */
<> 144:ef7eb2e8f9f7 1565 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
<> 144:ef7eb2e8f9f7 1566
<> 144:ef7eb2e8f9f7 1567 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1568 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 /* Return function status */
<> 144:ef7eb2e8f9f7 1571 return HAL_OK;
<> 144:ef7eb2e8f9f7 1572 }
<> 144:ef7eb2e8f9f7 1573 else
<> 144:ef7eb2e8f9f7 1574 {
<> 144:ef7eb2e8f9f7 1575 /* Release Lock */
<> 144:ef7eb2e8f9f7 1576 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1577
<> 144:ef7eb2e8f9f7 1578 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1579 }
<> 144:ef7eb2e8f9f7 1580 }
<> 144:ef7eb2e8f9f7 1581
<> 144:ef7eb2e8f9f7 1582 /**
<> 144:ef7eb2e8f9f7 1583 * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
<> 144:ef7eb2e8f9f7 1584 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1585 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1586 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1587 * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
<> 144:ef7eb2e8f9f7 1588 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1589 * @retval HAL status
<> 144:ef7eb2e8f9f7 1590 */
<> 144:ef7eb2e8f9f7 1591 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
<> 144:ef7eb2e8f9f7 1592 {
<> 144:ef7eb2e8f9f7 1593 uint32_t inputaddr = 0, outputaddr = 0;
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 1596 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 1597 {
<> 144:ef7eb2e8f9f7 1598 /* Process Locked */
<> 144:ef7eb2e8f9f7 1599 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1600
<> 144:ef7eb2e8f9f7 1601 /* Return function status */
<> 144:ef7eb2e8f9f7 1602 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1603 }
<> 144:ef7eb2e8f9f7 1604
<> 144:ef7eb2e8f9f7 1605 /* Check if HAL_CRYP_Init has been called */
<> 144:ef7eb2e8f9f7 1606 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
<> 144:ef7eb2e8f9f7 1607 {
<> 144:ef7eb2e8f9f7 1608 /* Process Locked */
<> 144:ef7eb2e8f9f7 1609 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 1610
<> 144:ef7eb2e8f9f7 1611 inputaddr = (uint32_t)pCypherData;
<> 144:ef7eb2e8f9f7 1612 outputaddr = (uint32_t)pPlainData;
<> 144:ef7eb2e8f9f7 1613
<> 144:ef7eb2e8f9f7 1614 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 1615 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1616
<> 144:ef7eb2e8f9f7 1617 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1618 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 1619 {
<> 144:ef7eb2e8f9f7 1620 /* Set the key */
<> 144:ef7eb2e8f9f7 1621 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 1622
<> 144:ef7eb2e8f9f7 1623 /* Reset the CHMOD & MODE bits */
<> 144:ef7eb2e8f9f7 1624 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
<> 144:ef7eb2e8f9f7 1625
<> 144:ef7eb2e8f9f7 1626 /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
<> 144:ef7eb2e8f9f7 1627 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
<> 144:ef7eb2e8f9f7 1628
<> 144:ef7eb2e8f9f7 1629 /* Set the Initialization Vector */
<> 144:ef7eb2e8f9f7 1630 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
<> 144:ef7eb2e8f9f7 1631
<> 144:ef7eb2e8f9f7 1632 /* Set the phase */
<> 144:ef7eb2e8f9f7 1633 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1634 }
<> 144:ef7eb2e8f9f7 1635
<> 144:ef7eb2e8f9f7 1636 /* Set the input and output addresses and start DMA transfer */
<> 144:ef7eb2e8f9f7 1637 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
<> 144:ef7eb2e8f9f7 1638
<> 144:ef7eb2e8f9f7 1639 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1640 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1641
<> 144:ef7eb2e8f9f7 1642 /* Return function status */
<> 144:ef7eb2e8f9f7 1643 return HAL_OK;
<> 144:ef7eb2e8f9f7 1644 }
<> 144:ef7eb2e8f9f7 1645 else
<> 144:ef7eb2e8f9f7 1646 {
<> 144:ef7eb2e8f9f7 1647 /* Release Lock */
<> 144:ef7eb2e8f9f7 1648 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1649
<> 144:ef7eb2e8f9f7 1650 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1651 }
<> 144:ef7eb2e8f9f7 1652 }
<> 144:ef7eb2e8f9f7 1653
<> 144:ef7eb2e8f9f7 1654 /**
<> 144:ef7eb2e8f9f7 1655 * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
<> 144:ef7eb2e8f9f7 1656 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1657 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1658 * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1659 * @param Size: Length of the plaintext buffer, must be a multiple of 16
<> 144:ef7eb2e8f9f7 1660 * @param pPlainData: Pointer to the plaintext buffer (aligned on u32)
<> 144:ef7eb2e8f9f7 1661 * @retval HAL status
<> 144:ef7eb2e8f9f7 1662 */
<> 144:ef7eb2e8f9f7 1663 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
<> 144:ef7eb2e8f9f7 1664 {
<> 144:ef7eb2e8f9f7 1665 uint32_t inputaddr = 0, outputaddr = 0;
<> 144:ef7eb2e8f9f7 1666
<> 144:ef7eb2e8f9f7 1667 /* Check that data aligned on u32 */
<> 144:ef7eb2e8f9f7 1668 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
<> 144:ef7eb2e8f9f7 1669 {
<> 144:ef7eb2e8f9f7 1670 /* Process Locked */
<> 144:ef7eb2e8f9f7 1671 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1672
<> 144:ef7eb2e8f9f7 1673 /* Return function status */
<> 144:ef7eb2e8f9f7 1674 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1675 }
<> 144:ef7eb2e8f9f7 1676
<> 144:ef7eb2e8f9f7 1677 /* Check if HAL_CRYP_Init has been called */
<> 144:ef7eb2e8f9f7 1678 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
<> 144:ef7eb2e8f9f7 1679 {
<> 144:ef7eb2e8f9f7 1680 /* Process Locked */
<> 144:ef7eb2e8f9f7 1681 __HAL_LOCK(hcryp);
<> 144:ef7eb2e8f9f7 1682
<> 144:ef7eb2e8f9f7 1683 inputaddr = (uint32_t)pCypherData;
<> 144:ef7eb2e8f9f7 1684 outputaddr = (uint32_t)pPlainData;
<> 144:ef7eb2e8f9f7 1685
<> 144:ef7eb2e8f9f7 1686 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 1687 hcryp->State = HAL_CRYP_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1688
<> 144:ef7eb2e8f9f7 1689 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1690 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
<> 144:ef7eb2e8f9f7 1691 {
<> 144:ef7eb2e8f9f7 1692 /* Set the key */
<> 144:ef7eb2e8f9f7 1693 CRYP_SetKey(hcryp, hcryp->Init.pKey);
<> 144:ef7eb2e8f9f7 1694
<> 144:ef7eb2e8f9f7 1695 /* Set the CRYP peripheral in AES CTR mode */
<> 144:ef7eb2e8f9f7 1696 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
<> 144:ef7eb2e8f9f7 1697
<> 144:ef7eb2e8f9f7 1698 /* Set the Initialization Vector */
<> 144:ef7eb2e8f9f7 1699 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
<> 144:ef7eb2e8f9f7 1700
<> 144:ef7eb2e8f9f7 1701 /* Set the phase */
<> 144:ef7eb2e8f9f7 1702 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1703 }
<> 144:ef7eb2e8f9f7 1704
<> 144:ef7eb2e8f9f7 1705 /* Set the input and output addresses and start DMA transfer */
<> 144:ef7eb2e8f9f7 1706 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
<> 144:ef7eb2e8f9f7 1707
<> 144:ef7eb2e8f9f7 1708 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1709 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1710
<> 144:ef7eb2e8f9f7 1711 /* Return function status */
<> 144:ef7eb2e8f9f7 1712 return HAL_OK;
<> 144:ef7eb2e8f9f7 1713 }
<> 144:ef7eb2e8f9f7 1714 else
<> 144:ef7eb2e8f9f7 1715 {
<> 144:ef7eb2e8f9f7 1716 /* Release Lock */
<> 144:ef7eb2e8f9f7 1717 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1718
<> 144:ef7eb2e8f9f7 1719 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1720 }
<> 144:ef7eb2e8f9f7 1721 }
<> 144:ef7eb2e8f9f7 1722
<> 144:ef7eb2e8f9f7 1723 /**
<> 144:ef7eb2e8f9f7 1724 * @}
<> 144:ef7eb2e8f9f7 1725 */
<> 144:ef7eb2e8f9f7 1726
<> 144:ef7eb2e8f9f7 1727 /** @addtogroup CRYP_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 1728 * @brief DMA callback functions.
<> 144:ef7eb2e8f9f7 1729 *
<> 144:ef7eb2e8f9f7 1730 @verbatim
<> 144:ef7eb2e8f9f7 1731 ==============================================================================
<> 144:ef7eb2e8f9f7 1732 ##### DMA callback functions #####
<> 144:ef7eb2e8f9f7 1733 ==============================================================================
<> 144:ef7eb2e8f9f7 1734 [..] This section provides DMA callback functions:
<> 144:ef7eb2e8f9f7 1735 (+) DMA Input data transfer complete
<> 144:ef7eb2e8f9f7 1736 (+) DMA Output data transfer complete
<> 144:ef7eb2e8f9f7 1737 (+) DMA error
<> 144:ef7eb2e8f9f7 1738
<> 144:ef7eb2e8f9f7 1739 @endverbatim
<> 144:ef7eb2e8f9f7 1740 * @{
<> 144:ef7eb2e8f9f7 1741 */
<> 144:ef7eb2e8f9f7 1742
<> 144:ef7eb2e8f9f7 1743 /**
<> 144:ef7eb2e8f9f7 1744 * @brief CRYP error callback.
<> 144:ef7eb2e8f9f7 1745 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1746 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1747 * @retval None
<> 144:ef7eb2e8f9f7 1748 */
<> 144:ef7eb2e8f9f7 1749 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
<> 144:ef7eb2e8f9f7 1750 {
<> 144:ef7eb2e8f9f7 1751 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1752 UNUSED(hcryp);
<> 144:ef7eb2e8f9f7 1753
<> 144:ef7eb2e8f9f7 1754 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1755 the HAL_CRYP_ErrorCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 1756 */
<> 144:ef7eb2e8f9f7 1757 }
<> 144:ef7eb2e8f9f7 1758
<> 144:ef7eb2e8f9f7 1759 /**
<> 144:ef7eb2e8f9f7 1760 * @brief Input transfer completed callback.
<> 144:ef7eb2e8f9f7 1761 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1762 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1763 * @retval None
<> 144:ef7eb2e8f9f7 1764 */
<> 144:ef7eb2e8f9f7 1765 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
<> 144:ef7eb2e8f9f7 1766 {
<> 144:ef7eb2e8f9f7 1767 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1768 UNUSED(hcryp);
<> 144:ef7eb2e8f9f7 1769
<> 144:ef7eb2e8f9f7 1770 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1771 the HAL_CRYP_InCpltCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 1772 */
<> 144:ef7eb2e8f9f7 1773 }
<> 144:ef7eb2e8f9f7 1774
<> 144:ef7eb2e8f9f7 1775 /**
<> 144:ef7eb2e8f9f7 1776 * @brief Output transfer completed callback.
<> 144:ef7eb2e8f9f7 1777 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1778 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1779 * @retval None
<> 144:ef7eb2e8f9f7 1780 */
<> 144:ef7eb2e8f9f7 1781 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
<> 144:ef7eb2e8f9f7 1782 {
<> 144:ef7eb2e8f9f7 1783 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1784 UNUSED(hcryp);
<> 144:ef7eb2e8f9f7 1785
<> 144:ef7eb2e8f9f7 1786 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1787 the HAL_CRYP_OutCpltCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 1788 */
<> 144:ef7eb2e8f9f7 1789 }
<> 144:ef7eb2e8f9f7 1790
<> 144:ef7eb2e8f9f7 1791 /**
<> 144:ef7eb2e8f9f7 1792 * @}
<> 144:ef7eb2e8f9f7 1793 */
<> 144:ef7eb2e8f9f7 1794
<> 144:ef7eb2e8f9f7 1795 /** @addtogroup CRYP_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 1796 * @brief CRYP IRQ handler.
<> 144:ef7eb2e8f9f7 1797 *
<> 144:ef7eb2e8f9f7 1798 @verbatim
<> 144:ef7eb2e8f9f7 1799 ==============================================================================
<> 144:ef7eb2e8f9f7 1800 ##### CRYP IRQ handler management #####
<> 144:ef7eb2e8f9f7 1801 ==============================================================================
<> 144:ef7eb2e8f9f7 1802 [..] This section provides CRYP IRQ handler function.
<> 144:ef7eb2e8f9f7 1803
<> 144:ef7eb2e8f9f7 1804 @endverbatim
<> 144:ef7eb2e8f9f7 1805 * @{
<> 144:ef7eb2e8f9f7 1806 */
<> 144:ef7eb2e8f9f7 1807
<> 144:ef7eb2e8f9f7 1808 /**
<> 144:ef7eb2e8f9f7 1809 * @brief This function handles CRYP interrupt request.
<> 144:ef7eb2e8f9f7 1810 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1811 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1812 * @retval None
<> 144:ef7eb2e8f9f7 1813 */
<> 144:ef7eb2e8f9f7 1814 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
<> 144:ef7eb2e8f9f7 1815 {
<> 144:ef7eb2e8f9f7 1816 /* Check if error occurred*/
<> 144:ef7eb2e8f9f7 1817 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERR) != RESET)
<> 144:ef7eb2e8f9f7 1818 {
<> 144:ef7eb2e8f9f7 1819 if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_RDERR) != RESET)
<> 144:ef7eb2e8f9f7 1820 {
<> 144:ef7eb2e8f9f7 1821 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_RDERR);
<> 144:ef7eb2e8f9f7 1822 }
<> 144:ef7eb2e8f9f7 1823
<> 144:ef7eb2e8f9f7 1824 if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_WRERR) != RESET)
<> 144:ef7eb2e8f9f7 1825 {
<> 144:ef7eb2e8f9f7 1826 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_WRERR);
<> 144:ef7eb2e8f9f7 1827 }
<> 144:ef7eb2e8f9f7 1828
<> 144:ef7eb2e8f9f7 1829 if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_CCF) != RESET)
<> 144:ef7eb2e8f9f7 1830 {
<> 144:ef7eb2e8f9f7 1831 __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CLEARFLAG_CCF);
<> 144:ef7eb2e8f9f7 1832 }
<> 144:ef7eb2e8f9f7 1833
<> 144:ef7eb2e8f9f7 1834 hcryp->State= HAL_CRYP_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1835 /* Disable Computation Complete Interrupt */
<> 144:ef7eb2e8f9f7 1836 __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC);
<> 144:ef7eb2e8f9f7 1837 __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_ERR);
<> 144:ef7eb2e8f9f7 1838
<> 144:ef7eb2e8f9f7 1839 HAL_CRYP_ErrorCallback(hcryp);
<> 144:ef7eb2e8f9f7 1840
<> 144:ef7eb2e8f9f7 1841 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1842 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1843
<> 144:ef7eb2e8f9f7 1844 return;
<> 144:ef7eb2e8f9f7 1845 }
<> 144:ef7eb2e8f9f7 1846
<> 144:ef7eb2e8f9f7 1847 /* Check if computation complete interrupt was enabled*/
<> 144:ef7eb2e8f9f7 1848 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CC) != RESET)
<> 144:ef7eb2e8f9f7 1849 {
<> 144:ef7eb2e8f9f7 1850 /* Clear CCF Flag */
<> 144:ef7eb2e8f9f7 1851 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
<> 144:ef7eb2e8f9f7 1852
<> 144:ef7eb2e8f9f7 1853 CRYP_EncryptDecrypt_IT(hcryp);
<> 144:ef7eb2e8f9f7 1854 }
<> 144:ef7eb2e8f9f7 1855 }
<> 144:ef7eb2e8f9f7 1856
<> 144:ef7eb2e8f9f7 1857 /**
<> 144:ef7eb2e8f9f7 1858 * @}
<> 144:ef7eb2e8f9f7 1859 */
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 /** @addtogroup CRYP_Exported_Functions_Group5
<> 144:ef7eb2e8f9f7 1862 * @brief Peripheral State functions.
<> 144:ef7eb2e8f9f7 1863 *
<> 144:ef7eb2e8f9f7 1864 @verbatim
<> 144:ef7eb2e8f9f7 1865 ==============================================================================
<> 144:ef7eb2e8f9f7 1866 ##### Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1867 ==============================================================================
<> 144:ef7eb2e8f9f7 1868 [..]
<> 144:ef7eb2e8f9f7 1869 This subsection permits to get in run-time the status of the peripheral.
<> 144:ef7eb2e8f9f7 1870
<> 144:ef7eb2e8f9f7 1871 @endverbatim
<> 144:ef7eb2e8f9f7 1872 * @{
<> 144:ef7eb2e8f9f7 1873 */
<> 144:ef7eb2e8f9f7 1874
<> 144:ef7eb2e8f9f7 1875 /**
<> 144:ef7eb2e8f9f7 1876 * @brief Returns the CRYP state.
<> 144:ef7eb2e8f9f7 1877 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1878 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1879 * @retval HAL state
<> 144:ef7eb2e8f9f7 1880 */
<> 144:ef7eb2e8f9f7 1881 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
<> 144:ef7eb2e8f9f7 1882 {
<> 144:ef7eb2e8f9f7 1883 return hcryp->State;
<> 144:ef7eb2e8f9f7 1884 }
<> 144:ef7eb2e8f9f7 1885
<> 144:ef7eb2e8f9f7 1886 /**
<> 144:ef7eb2e8f9f7 1887 * @}
<> 144:ef7eb2e8f9f7 1888 */
<> 144:ef7eb2e8f9f7 1889
<> 144:ef7eb2e8f9f7 1890 /**
<> 144:ef7eb2e8f9f7 1891 * @}
<> 144:ef7eb2e8f9f7 1892 */
<> 144:ef7eb2e8f9f7 1893
<> 144:ef7eb2e8f9f7 1894 /** @addtogroup CRYP_Private
<> 144:ef7eb2e8f9f7 1895 * @{
<> 144:ef7eb2e8f9f7 1896 */
<> 144:ef7eb2e8f9f7 1897
<> 144:ef7eb2e8f9f7 1898 /**
<> 144:ef7eb2e8f9f7 1899 * @brief IT function called under interruption context to continue encryption or decryption
<> 144:ef7eb2e8f9f7 1900 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1901 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 1902 * @retval HAL status
<> 144:ef7eb2e8f9f7 1903 */
<> 144:ef7eb2e8f9f7 1904 static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp)
<> 144:ef7eb2e8f9f7 1905 {
<> 144:ef7eb2e8f9f7 1906 uint32_t inputaddr = 0, outputaddr = 0;
<> 144:ef7eb2e8f9f7 1907
<> 144:ef7eb2e8f9f7 1908 /* Get the last Output data adress */
<> 144:ef7eb2e8f9f7 1909 outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
<> 144:ef7eb2e8f9f7 1910
<> 144:ef7eb2e8f9f7 1911 /* Read the Output block from the Output Register */
<> 144:ef7eb2e8f9f7 1912 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
<> 144:ef7eb2e8f9f7 1913 outputaddr+=4;
<> 144:ef7eb2e8f9f7 1914 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
<> 144:ef7eb2e8f9f7 1915 outputaddr+=4;
<> 144:ef7eb2e8f9f7 1916 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
<> 144:ef7eb2e8f9f7 1917 outputaddr+=4;
<> 144:ef7eb2e8f9f7 1918 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
<> 144:ef7eb2e8f9f7 1919
<> 144:ef7eb2e8f9f7 1920 hcryp->pCrypOutBuffPtr += 16;
<> 144:ef7eb2e8f9f7 1921 hcryp->CrypOutCount -= 16;
<> 144:ef7eb2e8f9f7 1922
<> 144:ef7eb2e8f9f7 1923 /* Check if all input text is encrypted or decrypted */
<> 144:ef7eb2e8f9f7 1924 if(hcryp->CrypOutCount == 0)
<> 144:ef7eb2e8f9f7 1925 {
<> 144:ef7eb2e8f9f7 1926 /* Disable Computation Complete Interrupt */
<> 144:ef7eb2e8f9f7 1927 __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC);
<> 144:ef7eb2e8f9f7 1928 __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_ERR);
<> 144:ef7eb2e8f9f7 1929
<> 144:ef7eb2e8f9f7 1930 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1931 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 1932
<> 144:ef7eb2e8f9f7 1933 /* Change the CRYP state */
<> 144:ef7eb2e8f9f7 1934 hcryp->State = HAL_CRYP_STATE_READY;
<> 144:ef7eb2e8f9f7 1935
<> 144:ef7eb2e8f9f7 1936 /* Call computation complete callback */
<> 144:ef7eb2e8f9f7 1937 HAL_CRYPEx_ComputationCpltCallback(hcryp);
<> 144:ef7eb2e8f9f7 1938 }
<> 144:ef7eb2e8f9f7 1939 else /* Process the rest of input text */
<> 144:ef7eb2e8f9f7 1940 {
<> 144:ef7eb2e8f9f7 1941 /* Get the last Intput data adress */
<> 144:ef7eb2e8f9f7 1942 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
<> 144:ef7eb2e8f9f7 1943
<> 144:ef7eb2e8f9f7 1944 /* Write the Input block in the Data Input register */
<> 144:ef7eb2e8f9f7 1945 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1946 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1947 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1948 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1949 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1950 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1951 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 1952 hcryp->pCrypInBuffPtr += 16;
<> 144:ef7eb2e8f9f7 1953 hcryp->CrypInCount -= 16;
<> 144:ef7eb2e8f9f7 1954 }
<> 144:ef7eb2e8f9f7 1955 return HAL_OK;
<> 144:ef7eb2e8f9f7 1956 }
<> 144:ef7eb2e8f9f7 1957 /**
<> 144:ef7eb2e8f9f7 1958 * @brief DMA CRYP Input Data process complete callback.
<> 144:ef7eb2e8f9f7 1959 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 1960 * @retval None
<> 144:ef7eb2e8f9f7 1961 */
<> 144:ef7eb2e8f9f7 1962 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1963 {
<> 144:ef7eb2e8f9f7 1964 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1965
<> 144:ef7eb2e8f9f7 1966 /* Disable the DMA transfer for input request */
<> 144:ef7eb2e8f9f7 1967 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
<> 144:ef7eb2e8f9f7 1968
<> 144:ef7eb2e8f9f7 1969 /* Call input data transfer complete callback */
<> 144:ef7eb2e8f9f7 1970 HAL_CRYP_InCpltCallback(hcryp);
<> 144:ef7eb2e8f9f7 1971 }
<> 144:ef7eb2e8f9f7 1972
<> 144:ef7eb2e8f9f7 1973 /**
<> 144:ef7eb2e8f9f7 1974 * @brief DMA CRYP Output Data process complete callback.
<> 144:ef7eb2e8f9f7 1975 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 1976 * @retval None
<> 144:ef7eb2e8f9f7 1977 */
<> 144:ef7eb2e8f9f7 1978 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1979 {
<> 144:ef7eb2e8f9f7 1980 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1981
<> 144:ef7eb2e8f9f7 1982 /* Disable the DMA transfer for output request by resetting the DMAOUTEN bit
<> 144:ef7eb2e8f9f7 1983 in the DMACR register */
<> 144:ef7eb2e8f9f7 1984 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
<> 144:ef7eb2e8f9f7 1985
<> 144:ef7eb2e8f9f7 1986 /* Clear CCF Flag */
<> 144:ef7eb2e8f9f7 1987 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
<> 144:ef7eb2e8f9f7 1988
<> 144:ef7eb2e8f9f7 1989 /* Disable CRYP */
<> 144:ef7eb2e8f9f7 1990 __HAL_CRYP_DISABLE(hcryp);
<> 144:ef7eb2e8f9f7 1991
<> 144:ef7eb2e8f9f7 1992 /* Change the CRYP state to ready */
<> 144:ef7eb2e8f9f7 1993 hcryp->State = HAL_CRYP_STATE_READY;
<> 144:ef7eb2e8f9f7 1994
<> 144:ef7eb2e8f9f7 1995 /* Call output data transfer complete callback */
<> 144:ef7eb2e8f9f7 1996 HAL_CRYP_OutCpltCallback(hcryp);
<> 144:ef7eb2e8f9f7 1997 }
<> 144:ef7eb2e8f9f7 1998
<> 144:ef7eb2e8f9f7 1999 /**
<> 144:ef7eb2e8f9f7 2000 * @brief DMA CRYP communication error callback.
<> 144:ef7eb2e8f9f7 2001 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 2002 * @retval None
<> 144:ef7eb2e8f9f7 2003 */
<> 144:ef7eb2e8f9f7 2004 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2005 {
<> 144:ef7eb2e8f9f7 2006 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2007 hcryp->State= HAL_CRYP_STATE_ERROR;
<> 144:ef7eb2e8f9f7 2008 HAL_CRYP_ErrorCallback(hcryp);
<> 144:ef7eb2e8f9f7 2009 }
<> 144:ef7eb2e8f9f7 2010
<> 144:ef7eb2e8f9f7 2011 /**
<> 144:ef7eb2e8f9f7 2012 * @brief Writes the Key in Key registers.
<> 144:ef7eb2e8f9f7 2013 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2014 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 2015 * @param Key: Pointer to Key buffer
<> 144:ef7eb2e8f9f7 2016 * @note Key must be written as little endian.
<> 144:ef7eb2e8f9f7 2017 * If Key pointer points at address n,
<> 144:ef7eb2e8f9f7 2018 * n[15:0] contains key[96:127],
<> 144:ef7eb2e8f9f7 2019 * (n+4)[15:0] contains key[64:95],
<> 144:ef7eb2e8f9f7 2020 * (n+8)[15:0] contains key[32:63] and
<> 144:ef7eb2e8f9f7 2021 * (n+12)[15:0] contains key[0:31]
<> 144:ef7eb2e8f9f7 2022 * @retval None
<> 144:ef7eb2e8f9f7 2023 */
<> 144:ef7eb2e8f9f7 2024 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key)
<> 144:ef7eb2e8f9f7 2025 {
<> 144:ef7eb2e8f9f7 2026 uint32_t keyaddr = (uint32_t)Key;
<> 144:ef7eb2e8f9f7 2027
<> 144:ef7eb2e8f9f7 2028 hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
<> 144:ef7eb2e8f9f7 2029 keyaddr+=4;
<> 144:ef7eb2e8f9f7 2030 hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
<> 144:ef7eb2e8f9f7 2031 keyaddr+=4;
<> 144:ef7eb2e8f9f7 2032 hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
<> 144:ef7eb2e8f9f7 2033 keyaddr+=4;
<> 144:ef7eb2e8f9f7 2034 hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
<> 144:ef7eb2e8f9f7 2035 }
<> 144:ef7eb2e8f9f7 2036
<> 144:ef7eb2e8f9f7 2037 /**
<> 144:ef7eb2e8f9f7 2038 * @brief Writes the InitVector/InitCounter in IV registers.
<> 144:ef7eb2e8f9f7 2039 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2040 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 2041 * @param InitVector: Pointer to InitVector/InitCounter buffer
<> 144:ef7eb2e8f9f7 2042 * @note Init Vector must be written as little endian.
<> 144:ef7eb2e8f9f7 2043 * If Init Vector pointer points at address n,
<> 144:ef7eb2e8f9f7 2044 * n[15:0] contains Vector[96:127],
<> 144:ef7eb2e8f9f7 2045 * (n+4)[15:0] contains Vector[64:95],
<> 144:ef7eb2e8f9f7 2046 * (n+8)[15:0] contains Vector[32:63] and
<> 144:ef7eb2e8f9f7 2047 * (n+12)[15:0] contains Vector[0:31]
<> 144:ef7eb2e8f9f7 2048 * @retval None
<> 144:ef7eb2e8f9f7 2049 */
<> 144:ef7eb2e8f9f7 2050 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
<> 144:ef7eb2e8f9f7 2051 {
<> 144:ef7eb2e8f9f7 2052 uint32_t ivaddr = (uint32_t)InitVector;
<> 144:ef7eb2e8f9f7 2053
<> 144:ef7eb2e8f9f7 2054 hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
<> 144:ef7eb2e8f9f7 2055 ivaddr+=4;
<> 144:ef7eb2e8f9f7 2056 hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
<> 144:ef7eb2e8f9f7 2057 ivaddr+=4;
<> 144:ef7eb2e8f9f7 2058 hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
<> 144:ef7eb2e8f9f7 2059 ivaddr+=4;
<> 144:ef7eb2e8f9f7 2060 hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
<> 144:ef7eb2e8f9f7 2061 }
<> 144:ef7eb2e8f9f7 2062
<> 144:ef7eb2e8f9f7 2063 /**
<> 144:ef7eb2e8f9f7 2064 * @brief Process Data: Writes Input data in polling mode and reads the output data
<> 144:ef7eb2e8f9f7 2065 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2066 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 2067 * @param Input: Pointer to the Input buffer
<> 144:ef7eb2e8f9f7 2068 * @param Ilength: Length of the Input buffer, must be a multiple of 16.
<> 144:ef7eb2e8f9f7 2069 * @param Output: Pointer to the returned buffer
<> 144:ef7eb2e8f9f7 2070 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 2071 * @retval None
<> 144:ef7eb2e8f9f7 2072 */
<> 144:ef7eb2e8f9f7 2073 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 2074 {
<> 144:ef7eb2e8f9f7 2075 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 2076
<> 144:ef7eb2e8f9f7 2077 uint32_t index = 0;
<> 144:ef7eb2e8f9f7 2078 uint32_t inputaddr = (uint32_t)Input;
<> 144:ef7eb2e8f9f7 2079 uint32_t outputaddr = (uint32_t)Output;
<> 144:ef7eb2e8f9f7 2080
<> 144:ef7eb2e8f9f7 2081 for(index=0; (index < Ilength); index += 16)
<> 144:ef7eb2e8f9f7 2082 {
<> 144:ef7eb2e8f9f7 2083 /* Write the Input block in the Data Input register */
<> 144:ef7eb2e8f9f7 2084 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 2085 inputaddr+=4;
<> 144:ef7eb2e8f9f7 2086 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 2087 inputaddr+=4;
<> 144:ef7eb2e8f9f7 2088 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 2089 inputaddr+=4;
<> 144:ef7eb2e8f9f7 2090 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
<> 144:ef7eb2e8f9f7 2091 inputaddr+=4;
<> 144:ef7eb2e8f9f7 2092
<> 144:ef7eb2e8f9f7 2093 /* Get timeout */
<> 144:ef7eb2e8f9f7 2094 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2095
<> 144:ef7eb2e8f9f7 2096 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
<> 144:ef7eb2e8f9f7 2097 {
<> 144:ef7eb2e8f9f7 2098 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 2099 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 2100 {
<> 144:ef7eb2e8f9f7 2101 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 2102 {
<> 144:ef7eb2e8f9f7 2103 /* Change state */
<> 144:ef7eb2e8f9f7 2104 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 2105
<> 144:ef7eb2e8f9f7 2106 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2107 __HAL_UNLOCK(hcryp);
<> 144:ef7eb2e8f9f7 2108
<> 144:ef7eb2e8f9f7 2109 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2110 }
<> 144:ef7eb2e8f9f7 2111 }
<> 144:ef7eb2e8f9f7 2112 }
<> 144:ef7eb2e8f9f7 2113 /* Clear CCF Flag */
<> 144:ef7eb2e8f9f7 2114 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
<> 144:ef7eb2e8f9f7 2115
<> 144:ef7eb2e8f9f7 2116 /* Read the Output block from the Data Output Register */
<> 144:ef7eb2e8f9f7 2117 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
<> 144:ef7eb2e8f9f7 2118 outputaddr+=4;
<> 144:ef7eb2e8f9f7 2119 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
<> 144:ef7eb2e8f9f7 2120 outputaddr+=4;
<> 144:ef7eb2e8f9f7 2121 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
<> 144:ef7eb2e8f9f7 2122 outputaddr+=4;
<> 144:ef7eb2e8f9f7 2123 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
<> 144:ef7eb2e8f9f7 2124 outputaddr+=4;
<> 144:ef7eb2e8f9f7 2125 }
<> 144:ef7eb2e8f9f7 2126 /* Return function status */
<> 144:ef7eb2e8f9f7 2127 return HAL_OK;
<> 144:ef7eb2e8f9f7 2128 }
<> 144:ef7eb2e8f9f7 2129
<> 144:ef7eb2e8f9f7 2130 /**
<> 144:ef7eb2e8f9f7 2131 * @brief Set the DMA configuration and start the DMA transfer
<> 144:ef7eb2e8f9f7 2132 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2133 * the configuration information for CRYP module
<> 144:ef7eb2e8f9f7 2134 * @param inputaddr: address of the Input buffer
<> 144:ef7eb2e8f9f7 2135 * @param Size: Size of the Input buffer, must be a multiple of 16.
<> 144:ef7eb2e8f9f7 2136 * @param outputaddr: address of the Output buffer
<> 144:ef7eb2e8f9f7 2137 * @retval None
<> 144:ef7eb2e8f9f7 2138 */
<> 144:ef7eb2e8f9f7 2139 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
<> 144:ef7eb2e8f9f7 2140 {
<> 144:ef7eb2e8f9f7 2141 /* Set the CRYP DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 2142 hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
<> 144:ef7eb2e8f9f7 2143 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2144 hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
<> 144:ef7eb2e8f9f7 2145
<> 144:ef7eb2e8f9f7 2146 /* Set the CRYP DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 2147 hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
<> 144:ef7eb2e8f9f7 2148 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2149 hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
<> 144:ef7eb2e8f9f7 2150
<> 144:ef7eb2e8f9f7 2151 /* Enable the DMA In DMA Stream */
<> 144:ef7eb2e8f9f7 2152 HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);
<> 144:ef7eb2e8f9f7 2153
<> 144:ef7eb2e8f9f7 2154 /* Enable the DMA Out DMA Stream */
<> 144:ef7eb2e8f9f7 2155 HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);
<> 144:ef7eb2e8f9f7 2156
<> 144:ef7eb2e8f9f7 2157 /* Enable In and Out DMA requests */
<> 144:ef7eb2e8f9f7 2158 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
<> 144:ef7eb2e8f9f7 2159
<> 144:ef7eb2e8f9f7 2160 /* Enable CRYP */
<> 144:ef7eb2e8f9f7 2161 __HAL_CRYP_ENABLE(hcryp);
<> 144:ef7eb2e8f9f7 2162 }
<> 144:ef7eb2e8f9f7 2163
<> 144:ef7eb2e8f9f7 2164 /**
<> 144:ef7eb2e8f9f7 2165 * @}
<> 144:ef7eb2e8f9f7 2166 */
<> 144:ef7eb2e8f9f7 2167
<> 144:ef7eb2e8f9f7 2168 /**
<> 144:ef7eb2e8f9f7 2169 * @}
<> 144:ef7eb2e8f9f7 2170 */
<> 144:ef7eb2e8f9f7 2171
<> 144:ef7eb2e8f9f7 2172 /**
<> 144:ef7eb2e8f9f7 2173 * @}
<> 144:ef7eb2e8f9f7 2174 */
<> 144:ef7eb2e8f9f7 2175
<> 144:ef7eb2e8f9f7 2176 #endif /* HAL_CRYP_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2177 #endif /* STM32L021xx || STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
<> 144:ef7eb2e8f9f7 2178 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 2179