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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/stm32l073xx.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7
Parent:: 113:b3775bf36a83

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l073xx.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.0
<>	144:ef7eb2e8f9f7	6	* @date 8-January-2016
<>	144:ef7eb2e8f9f7	7	* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
<>	144:ef7eb2e8f9f7	8	* This file contains all the peripheral register's definitions, bits
<>	144:ef7eb2e8f9f7	9	* definitions and memory mapping for stm32l073xx devices.
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* This file contains:
<>	144:ef7eb2e8f9f7	12	* - Data structures and the address mapping for all peripherals
<>	144:ef7eb2e8f9f7	13	* - Peripheral's registers declarations and bits definition
<>	144:ef7eb2e8f9f7	14	* - Macros to access peripheral's registers hardware
<>	144:ef7eb2e8f9f7	15	*
<>	144:ef7eb2e8f9f7	16	******************************************************************************
<>	144:ef7eb2e8f9f7	17	* @attention
<>	144:ef7eb2e8f9f7	18	*
<>	144:ef7eb2e8f9f7	19	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	20	*
<>	144:ef7eb2e8f9f7	21	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	22	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	23	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	24	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	25	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	26	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	27	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	29	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	30	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	31	*
<>	144:ef7eb2e8f9f7	32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	42	*
<>	144:ef7eb2e8f9f7	43	******************************************************************************
<>	144:ef7eb2e8f9f7	44	*/
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/** @addtogroup CMSIS
<>	144:ef7eb2e8f9f7	47	* @{
<>	144:ef7eb2e8f9f7	48	*/
<>	144:ef7eb2e8f9f7	49
<>	144:ef7eb2e8f9f7	50	/** @addtogroup stm32l073xx
<>	144:ef7eb2e8f9f7	51	* @{
<>	144:ef7eb2e8f9f7	52	*/
<>	144:ef7eb2e8f9f7	53
<>	144:ef7eb2e8f9f7	54	#ifndef __STM32L073xx_H
<>	144:ef7eb2e8f9f7	55	#define __STM32L073xx_H
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	58	extern "C" {
<>	144:ef7eb2e8f9f7	59	#endif
<>	144:ef7eb2e8f9f7	60
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/** @addtogroup Configuration_section_for_CMSIS
<>	144:ef7eb2e8f9f7	63	* @{
<>	144:ef7eb2e8f9f7	64	*/
<>	144:ef7eb2e8f9f7	65	/**
<>	144:ef7eb2e8f9f7	66	* @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
<>	144:ef7eb2e8f9f7	67	*/
<>	144:ef7eb2e8f9f7	68	#define __CM0PLUS_REV 0 /!< Core Revision r0p0 /
<>	144:ef7eb2e8f9f7	69	#define __MPU_PRESENT 1 /!< STM32L0xx provides an MPU /
<>	144:ef7eb2e8f9f7	70	#define __VTOR_PRESENT 1 /!< Vector Table Register supported /
<>	144:ef7eb2e8f9f7	71	#define __NVIC_PRIO_BITS 2 /!< STM32L0xx uses 2 Bits for the Priority Levels /
<>	144:ef7eb2e8f9f7	72	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
<>	144:ef7eb2e8f9f7	73
<>	144:ef7eb2e8f9f7	74	/**
<>	144:ef7eb2e8f9f7	75	* @}
<>	144:ef7eb2e8f9f7	76	*/
<>	144:ef7eb2e8f9f7	77
<>	144:ef7eb2e8f9f7	78	/** @addtogroup Peripheral_interrupt_number_definition
<>	144:ef7eb2e8f9f7	79	* @{
<>	144:ef7eb2e8f9f7	80	*/
<>	144:ef7eb2e8f9f7	81
<>	144:ef7eb2e8f9f7	82	/**
<>	144:ef7eb2e8f9f7	83	* @brief stm32l073xx Interrupt Number Definition, according to the selected device
<>	144:ef7eb2e8f9f7	84	* in @ref Library_configuration_section
<>	144:ef7eb2e8f9f7	85	*/
<>	144:ef7eb2e8f9f7	86
<>	144:ef7eb2e8f9f7	87	/!< Interrupt Number Definition /
<>	144:ef7eb2e8f9f7	88	typedef enum
<>	144:ef7eb2e8f9f7	89	{
<>	144:ef7eb2e8f9f7	90	/**** Cortex-M0 Processor Exceptions Numbers ****************************************************/
<>	144:ef7eb2e8f9f7	91	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
<>	144:ef7eb2e8f9f7	92	HardFault_IRQn = -13, /!< 3 Cortex-M0+ Hard Fault Interrupt /
<>	144:ef7eb2e8f9f7	93	SVC_IRQn = -5, /!< 11 Cortex-M0+ SV Call Interrupt /
<>	144:ef7eb2e8f9f7	94	PendSV_IRQn = -2, /!< 14 Cortex-M0+ Pend SV Interrupt /
<>	144:ef7eb2e8f9f7	95	SysTick_IRQn = -1, /!< 15 Cortex-M0+ System Tick Interrupt /
<>	144:ef7eb2e8f9f7	96
<>	144:ef7eb2e8f9f7	97	/**** STM32L-0 specific Interrupt Numbers *******************************************************/
<>	144:ef7eb2e8f9f7	98	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
<>	144:ef7eb2e8f9f7	99	PVD_IRQn = 1, /!< PVD through EXTI Line detect Interrupt /
<>	144:ef7eb2e8f9f7	100	RTC_IRQn = 2, /!< RTC through EXTI Line Interrupt /
<>	144:ef7eb2e8f9f7	101	FLASH_IRQn = 3, /!< FLASH Interrupt /
<>	144:ef7eb2e8f9f7	102	RCC_CRS_IRQn = 4, /!< RCC and CRS Interrupts /
<>	144:ef7eb2e8f9f7	103	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
<>	144:ef7eb2e8f9f7	104	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
<>	144:ef7eb2e8f9f7	105	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
<>	144:ef7eb2e8f9f7	106	TSC_IRQn = 8, /!< TSC Interrupt /
<>	144:ef7eb2e8f9f7	107	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
<>	144:ef7eb2e8f9f7	108	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
<>	144:ef7eb2e8f9f7	109	DMA1_Channel4_5_6_7_IRQn = 11, /!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts /
<>	144:ef7eb2e8f9f7	110	ADC1_COMP_IRQn = 12, /!< ADC1, COMP1 and COMP2 Interrupts /
<>	144:ef7eb2e8f9f7	111	LPTIM1_IRQn = 13, /!< LPTIM1 Interrupt /
<>	144:ef7eb2e8f9f7	112	USART4_5_IRQn = 14, /!< USART4 and USART5 Interrupt /
<>	144:ef7eb2e8f9f7	113	TIM2_IRQn = 15, /!< TIM2 Interrupt /
<>	144:ef7eb2e8f9f7	114	TIM3_IRQn = 16, /!< TIM3 Interrupt /
<>	144:ef7eb2e8f9f7	115	TIM6_DAC_IRQn = 17, /!< TIM6 and DAC Interrupts /
<>	144:ef7eb2e8f9f7	116	TIM7_IRQn = 18, /!< TIM7 Interrupt /
<>	144:ef7eb2e8f9f7	117	TIM21_IRQn = 20, /!< TIM21 Interrupt /
<>	144:ef7eb2e8f9f7	118	I2C3_IRQn = 21, /!< I2C3 Interrupt /
<>	144:ef7eb2e8f9f7	119	TIM22_IRQn = 22, /!< TIM22 Interrupt /
<>	144:ef7eb2e8f9f7	120	I2C1_IRQn = 23, /!< I2C1 Interrupt /
<>	144:ef7eb2e8f9f7	121	I2C2_IRQn = 24, /!< I2C2 Interrupt /
<>	144:ef7eb2e8f9f7	122	SPI1_IRQn = 25, /!< SPI1 Interrupt /
<>	144:ef7eb2e8f9f7	123	SPI2_IRQn = 26, /!< SPI2 Interrupt /
<>	144:ef7eb2e8f9f7	124	USART1_IRQn = 27, /!< USART1 Interrupt /
<>	144:ef7eb2e8f9f7	125	USART2_IRQn = 28, /!< USART2 Interrupt /
<>	144:ef7eb2e8f9f7	126	RNG_LPUART1_IRQn = 29, /!< RNG and LPUART1 Interrupts /
<>	144:ef7eb2e8f9f7	127	LCD_IRQn = 30, /!< LCD Interrupt /
<>	144:ef7eb2e8f9f7	128	USB_IRQn = 31, /!< USB global Interrupt /
<>	144:ef7eb2e8f9f7	129	} IRQn_Type;
<>	144:ef7eb2e8f9f7	130
<>	144:ef7eb2e8f9f7	131	/**
<>	144:ef7eb2e8f9f7	132	* @}
<>	144:ef7eb2e8f9f7	133	*/
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	#include "core_cm0plus.h"
<>	144:ef7eb2e8f9f7	136	#include "system_stm32l0xx.h"
<>	144:ef7eb2e8f9f7	137	#include <stdint.h>
<>	144:ef7eb2e8f9f7	138
<>	144:ef7eb2e8f9f7	139	/** @addtogroup Peripheral_registers_structures
<>	144:ef7eb2e8f9f7	140	* @{
<>	144:ef7eb2e8f9f7	141	*/
<>	144:ef7eb2e8f9f7	142
<>	144:ef7eb2e8f9f7	143	/**
<>	144:ef7eb2e8f9f7	144	* @brief Analog to Digital Converter
<>	144:ef7eb2e8f9f7	145	*/
<>	144:ef7eb2e8f9f7	146
<>	144:ef7eb2e8f9f7	147	typedef struct
<>	144:ef7eb2e8f9f7	148	{
<>	144:ef7eb2e8f9f7	149	__IO uint32_t ISR; /!< ADC Interrupt and Status register, Address offset:0x00 /
<>	144:ef7eb2e8f9f7	150	__IO uint32_t IER; /!< ADC Interrupt Enable register, Address offset:0x04 /
<>	144:ef7eb2e8f9f7	151	__IO uint32_t CR; /!< ADC Control register, Address offset:0x08 /
<>	144:ef7eb2e8f9f7	152	__IO uint32_t CFGR1; /!< ADC Configuration register 1, Address offset:0x0C /
<>	144:ef7eb2e8f9f7	153	__IO uint32_t CFGR2; /!< ADC Configuration register 2, Address offset:0x10 /
<>	144:ef7eb2e8f9f7	154	__IO uint32_t SMPR; /!< ADC Sampling time register, Address offset:0x14 /
<>	144:ef7eb2e8f9f7	155	uint32_t RESERVED1; /!< Reserved, 0x18 /
<>	144:ef7eb2e8f9f7	156	uint32_t RESERVED2; /!< Reserved, 0x1C /
<>	144:ef7eb2e8f9f7	157	__IO uint32_t TR; /!< ADC watchdog threshold register, Address offset:0x20 /
<>	144:ef7eb2e8f9f7	158	uint32_t RESERVED3; /!< Reserved, 0x24 /
<>	144:ef7eb2e8f9f7	159	__IO uint32_t CHSELR; /!< ADC channel selection register, Address offset:0x28 /
<>	144:ef7eb2e8f9f7	160	uint32_t RESERVED4[5]; /!< Reserved, 0x2C /
<>	144:ef7eb2e8f9f7	161	__IO uint32_t DR; /!< ADC data register, Address offset:0x40 /
<>	144:ef7eb2e8f9f7	162	uint32_t RESERVED5[28]; /!< Reserved, 0x44 - 0xB0 /
<>	144:ef7eb2e8f9f7	163	__IO uint32_t CALFACT; /!< ADC data register, Address offset:0xB4 /
<>	144:ef7eb2e8f9f7	164	} ADC_TypeDef;
<>	144:ef7eb2e8f9f7	165
<>	144:ef7eb2e8f9f7	166	typedef struct
<>	144:ef7eb2e8f9f7	167	{
<>	144:ef7eb2e8f9f7	168	__IO uint32_t CCR;
<>	144:ef7eb2e8f9f7	169	} ADC_Common_TypeDef;
<>	144:ef7eb2e8f9f7	170
<>	144:ef7eb2e8f9f7	171
<>	144:ef7eb2e8f9f7	172	/**
<>	144:ef7eb2e8f9f7	173	* @brief Comparator
<>	144:ef7eb2e8f9f7	174	*/
<>	144:ef7eb2e8f9f7	175
<>	144:ef7eb2e8f9f7	176	typedef struct
<>	144:ef7eb2e8f9f7	177	{
<>	144:ef7eb2e8f9f7	178	__IO uint32_t CSR; /!< COMP comparator control and status register, Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	179	} COMP_TypeDef;
<>	144:ef7eb2e8f9f7	180
<>	144:ef7eb2e8f9f7	181	typedef struct
<>	144:ef7eb2e8f9f7	182	{
<>	144:ef7eb2e8f9f7	183	__IO uint32_t CSR; /!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	184	} COMP_Common_TypeDef;
<>	144:ef7eb2e8f9f7	185
<>	144:ef7eb2e8f9f7	186
<>	144:ef7eb2e8f9f7	187	/**
<>	144:ef7eb2e8f9f7	188	* @brief CRC calculation unit
<>	144:ef7eb2e8f9f7	189	*/
<>	144:ef7eb2e8f9f7	190
<>	144:ef7eb2e8f9f7	191	typedef struct
<>	144:ef7eb2e8f9f7	192	{
<>	144:ef7eb2e8f9f7	193	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	194	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	195	uint8_t RESERVED0; /!< Reserved, 0x05 /
<>	144:ef7eb2e8f9f7	196	uint16_t RESERVED1; /!< Reserved, 0x06 /
<>	144:ef7eb2e8f9f7	197	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	198	uint32_t RESERVED2; /!< Reserved, 0x0C /
<>	144:ef7eb2e8f9f7	199	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	200	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	201	} CRC_TypeDef;
<>	144:ef7eb2e8f9f7	202
<>	144:ef7eb2e8f9f7	203	/**
<>	144:ef7eb2e8f9f7	204	* @brief Clock Recovery System
<>	144:ef7eb2e8f9f7	205	*/
<>	144:ef7eb2e8f9f7	206
<>	144:ef7eb2e8f9f7	207	typedef struct
<>	144:ef7eb2e8f9f7	208	{
<>	144:ef7eb2e8f9f7	209	__IO uint32_t CR; /!< CRS ccontrol register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	210	__IO uint32_t CFGR; /!< CRS configuration register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	211	__IO uint32_t ISR; /!< CRS interrupt and status register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	212	__IO uint32_t ICR; /!< CRS interrupt flag clear register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	213	} CRS_TypeDef;
<>	144:ef7eb2e8f9f7	214
<>	144:ef7eb2e8f9f7	215	/**
<>	144:ef7eb2e8f9f7	216	* @brief Digital to Analog Converter
<>	144:ef7eb2e8f9f7	217	*/
<>	144:ef7eb2e8f9f7	218
<>	144:ef7eb2e8f9f7	219	typedef struct
<>	144:ef7eb2e8f9f7	220	{
<>	144:ef7eb2e8f9f7	221	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	222	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	223	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	224	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	225	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	226	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	227	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	228	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
<>	144:ef7eb2e8f9f7	229	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
<>	144:ef7eb2e8f9f7	230	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
<>	144:ef7eb2e8f9f7	231	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
<>	144:ef7eb2e8f9f7	232	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
<>	144:ef7eb2e8f9f7	233	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
<>	144:ef7eb2e8f9f7	234	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
<>	144:ef7eb2e8f9f7	235	} DAC_TypeDef;
<>	144:ef7eb2e8f9f7	236
<>	144:ef7eb2e8f9f7	237	/**
<>	144:ef7eb2e8f9f7	238	* @brief Debug MCU
<>	144:ef7eb2e8f9f7	239	*/
<>	144:ef7eb2e8f9f7	240
<>	144:ef7eb2e8f9f7	241	typedef struct
<>	144:ef7eb2e8f9f7	242	{
<>	144:ef7eb2e8f9f7	243	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	244	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	245	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	246	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	247	}DBGMCU_TypeDef;
<>	144:ef7eb2e8f9f7	248
<>	144:ef7eb2e8f9f7	249	/**
<>	144:ef7eb2e8f9f7	250	* @brief DMA Controller
<>	144:ef7eb2e8f9f7	251	*/
<>	144:ef7eb2e8f9f7	252
<>	144:ef7eb2e8f9f7	253	typedef struct
<>	144:ef7eb2e8f9f7	254	{
<>	144:ef7eb2e8f9f7	255	__IO uint32_t CCR; /!< DMA channel x configuration register /
<>	144:ef7eb2e8f9f7	256	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
<>	144:ef7eb2e8f9f7	257	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
<>	144:ef7eb2e8f9f7	258	__IO uint32_t CMAR; /!< DMA channel x memory address register /
<>	144:ef7eb2e8f9f7	259	} DMA_Channel_TypeDef;
<>	144:ef7eb2e8f9f7	260
<>	144:ef7eb2e8f9f7	261	typedef struct
<>	144:ef7eb2e8f9f7	262	{
<>	144:ef7eb2e8f9f7	263	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	264	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	265	} DMA_TypeDef;
<>	144:ef7eb2e8f9f7	266
<>	144:ef7eb2e8f9f7	267	typedef struct
<>	144:ef7eb2e8f9f7	268	{
<>	144:ef7eb2e8f9f7	269	__IO uint32_t CSELR; /!< DMA channel selection register, Address offset: 0xA8 /
<>	144:ef7eb2e8f9f7	270	} DMA_Request_TypeDef;
<>	144:ef7eb2e8f9f7	271
<>	144:ef7eb2e8f9f7	272	/**
<>	144:ef7eb2e8f9f7	273	* @brief External Interrupt/Event Controller
<>	144:ef7eb2e8f9f7	274	*/
<>	144:ef7eb2e8f9f7	275
<>	144:ef7eb2e8f9f7	276	typedef struct
<>	144:ef7eb2e8f9f7	277	{
<>	144:ef7eb2e8f9f7	278	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	279	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	280	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	281	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	282	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	283	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	284	}EXTI_TypeDef;
<>	144:ef7eb2e8f9f7	285
<>	144:ef7eb2e8f9f7	286	/**
<>	144:ef7eb2e8f9f7	287	* @brief FLASH Registers
<>	144:ef7eb2e8f9f7	288	*/
<>	144:ef7eb2e8f9f7	289	typedef struct
<>	144:ef7eb2e8f9f7	290	{
<>	144:ef7eb2e8f9f7	291	__IO uint32_t ACR; /!< Access control register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	292	__IO uint32_t PECR; /!< Program/erase control register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	293	__IO uint32_t PDKEYR; /!< Power down key register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	294	__IO uint32_t PEKEYR; /!< Program/erase key register, Address offset: 0x0c /
<>	144:ef7eb2e8f9f7	295	__IO uint32_t PRGKEYR; /!< Program memory key register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	296	__IO uint32_t OPTKEYR; /!< Option byte key register, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	297	__IO uint32_t SR; /!< Status register, Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	298	__IO uint32_t OPTR; /!< Option byte register, Address offset: 0x1c /
<>	144:ef7eb2e8f9f7	299	__IO uint32_t WRPR; /!< Write protection register, Address offset: 0x20 /
<>	144:ef7eb2e8f9f7	300	__IO uint32_t RESERVED1[23]; /!< Reserved1, Address offset: 0x24 /
<>	144:ef7eb2e8f9f7	301	__IO uint32_t WRPR2; /!< Write protection register 2, Address offset: 0x80 /
<>	144:ef7eb2e8f9f7	302	} FLASH_TypeDef;
<>	144:ef7eb2e8f9f7	303
<>	144:ef7eb2e8f9f7	304
<>	144:ef7eb2e8f9f7	305	/**
<>	144:ef7eb2e8f9f7	306	* @brief Option Bytes Registers
<>	144:ef7eb2e8f9f7	307	*/
<>	144:ef7eb2e8f9f7	308	typedef struct
<>	144:ef7eb2e8f9f7	309	{
<>	144:ef7eb2e8f9f7	310	__IO uint32_t RDP; /!< Read protection register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	311	__IO uint32_t USER; /!< user register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	312	__IO uint32_t WRP01; /!< write protection Bytes 0 and 1 Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	313	__IO uint32_t WRP23; /!< write protection Bytes 2 and 3 Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	314	__IO uint32_t WRP45; /!< write protection Bytes 4 and 5 Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	315	} OB_TypeDef;
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	/**
<>	144:ef7eb2e8f9f7	319	* @brief General Purpose IO
<>	144:ef7eb2e8f9f7	320	*/
<>	144:ef7eb2e8f9f7	321
<>	144:ef7eb2e8f9f7	322	typedef struct
<>	144:ef7eb2e8f9f7	323	{
<>	144:ef7eb2e8f9f7	324	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	325	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	326	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	327	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	328	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	329	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	330	__IO uint32_t BSRR; /!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	331	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
<>	144:ef7eb2e8f9f7	332	__IO uint32_t AFR[2]; /!< GPIO alternate function register, Address offset: 0x20-0x24 /
<>	144:ef7eb2e8f9f7	333	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
<>	144:ef7eb2e8f9f7	334	}GPIO_TypeDef;
<>	144:ef7eb2e8f9f7	335
<>	144:ef7eb2e8f9f7	336	/**
<>	144:ef7eb2e8f9f7	337	* @brief LPTIMIMER
<>	144:ef7eb2e8f9f7	338	*/
<>	144:ef7eb2e8f9f7	339	typedef struct
<>	144:ef7eb2e8f9f7	340	{
<>	144:ef7eb2e8f9f7	341	__IO uint32_t ISR; /!< LPTIM Interrupt and Status register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	342	__IO uint32_t ICR; /!< LPTIM Interrupt Clear register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	343	__IO uint32_t IER; /!< LPTIM Interrupt Enable register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	344	__IO uint32_t CFGR; /!< LPTIM Configuration register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	345	__IO uint32_t CR; /!< LPTIM Control register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	346	__IO uint32_t CMP; /!< LPTIM Compare register, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	347	__IO uint32_t ARR; /!< LPTIM Autoreload register, Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	348	__IO uint32_t CNT; /!< LPTIM Counter register, Address offset: 0x1C /
<>	144:ef7eb2e8f9f7	349	} LPTIM_TypeDef;
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	/**
<>	144:ef7eb2e8f9f7	352	* @brief SysTem Configuration
<>	144:ef7eb2e8f9f7	353	*/
<>	144:ef7eb2e8f9f7	354
<>	144:ef7eb2e8f9f7	355	typedef struct
<>	144:ef7eb2e8f9f7	356	{
<>	144:ef7eb2e8f9f7	357	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	358	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	359	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 /
<>	144:ef7eb2e8f9f7	360	uint32_t RESERVED[2]; /!< Reserved, 0x18-0x1C /
<>	144:ef7eb2e8f9f7	361	__IO uint32_t CFGR3; /!< SYSCFG configuration register 3, Address offset: 0x20 /
<>	144:ef7eb2e8f9f7	362	} SYSCFG_TypeDef;
<>	144:ef7eb2e8f9f7	363
<>	144:ef7eb2e8f9f7	364
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	/**
<>	144:ef7eb2e8f9f7	367	* @brief Inter-integrated Circuit Interface
<>	144:ef7eb2e8f9f7	368	*/
<>	144:ef7eb2e8f9f7	369
<>	144:ef7eb2e8f9f7	370	typedef struct
<>	144:ef7eb2e8f9f7	371	{
<>	144:ef7eb2e8f9f7	372	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	373	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	374	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	375	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	376	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	377	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	378	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	379	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
<>	144:ef7eb2e8f9f7	380	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
<>	144:ef7eb2e8f9f7	381	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
<>	144:ef7eb2e8f9f7	382	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
<>	144:ef7eb2e8f9f7	383	}I2C_TypeDef;
<>	144:ef7eb2e8f9f7	384
<>	144:ef7eb2e8f9f7	385
<>	144:ef7eb2e8f9f7	386	/**
<>	144:ef7eb2e8f9f7	387	* @brief Independent WATCHDOG
<>	144:ef7eb2e8f9f7	388	*/
<>	144:ef7eb2e8f9f7	389	typedef struct
<>	144:ef7eb2e8f9f7	390	{
<>	144:ef7eb2e8f9f7	391	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	392	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	393	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	394	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	395	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	396	} IWDG_TypeDef;
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	/**
<>	144:ef7eb2e8f9f7	399	* @brief LCD
<>	144:ef7eb2e8f9f7	400	*/
<>	144:ef7eb2e8f9f7	401	typedef struct
<>	144:ef7eb2e8f9f7	402	{
<>	144:ef7eb2e8f9f7	403	__IO uint32_t CR; /!< LCD control register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	404	__IO uint32_t FCR; /!< LCD frame control register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	405	__IO uint32_t SR; /!< LCD status register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	406	__IO uint32_t CLR; /!< LCD clear register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	407	uint32_t RESERVED; /!< Reserved, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	408	__IO uint32_t RAM[16]; /!< LCD display memory, Address offset: 0x14-0x50 /
<>	144:ef7eb2e8f9f7	409	} LCD_TypeDef;
<>	144:ef7eb2e8f9f7	410
<>	144:ef7eb2e8f9f7	411	/**
<>	144:ef7eb2e8f9f7	412	* @brief MIFARE Firewall
<>	144:ef7eb2e8f9f7	413	*/
<>	144:ef7eb2e8f9f7	414	typedef struct
<>	144:ef7eb2e8f9f7	415	{
<>	144:ef7eb2e8f9f7	416	__IO uint32_t CSSA; /!< Code Segment Start Address register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	417	__IO uint32_t CSL; /!< Code Segment Length register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	418	__IO uint32_t NVDSSA; /!< NON volatile data Segment Start Address register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	419	__IO uint32_t NVDSL; /!< NON volatile data Segment Length register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	420	__IO uint32_t VDSSA ; /!< Volatile data Segment Start Address register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	421	__IO uint32_t VDSL ; /!< Volatile data Segment Length register, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	422	__IO uint32_t LSSA ; /!< Library Segment Start Address register, Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	423	__IO uint32_t LSL ; /!< Library Segment Length register, Address offset: 0x1C /
<>	144:ef7eb2e8f9f7	424	__IO uint32_t CR ; /!< Configuration register, Address offset: 0x20 /
<>	144:ef7eb2e8f9f7	425
<>	144:ef7eb2e8f9f7	426	} FIREWALL_TypeDef;
<>	144:ef7eb2e8f9f7	427
<>	144:ef7eb2e8f9f7	428	/**
<>	144:ef7eb2e8f9f7	429	* @brief Power Control
<>	144:ef7eb2e8f9f7	430	*/
<>	144:ef7eb2e8f9f7	431	typedef struct
<>	144:ef7eb2e8f9f7	432	{
<>	144:ef7eb2e8f9f7	433	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	434	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	435	} PWR_TypeDef;
<>	144:ef7eb2e8f9f7	436
<>	144:ef7eb2e8f9f7	437	/**
<>	144:ef7eb2e8f9f7	438	* @brief Reset and Clock Control
<>	144:ef7eb2e8f9f7	439	*/
<>	144:ef7eb2e8f9f7	440	typedef struct
<>	144:ef7eb2e8f9f7	441	{
<>	144:ef7eb2e8f9f7	442	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	443	__IO uint32_t ICSCR; /!< RCC Internal clock sources calibration register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	444	__IO uint32_t CRRCR; /!< RCC Clock recovery RC register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	445	__IO uint32_t CFGR; /!< RCC Clock configuration register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	446	__IO uint32_t CIER; /!< RCC Clock interrupt enable register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	447	__IO uint32_t CIFR; /!< RCC Clock interrupt flag register, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	448	__IO uint32_t CICR; /!< RCC Clock interrupt clear register, Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	449	__IO uint32_t IOPRSTR; /!< RCC IO port reset register, Address offset: 0x1C /
<>	144:ef7eb2e8f9f7	450	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x20 /
<>	144:ef7eb2e8f9f7	451	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
<>	144:ef7eb2e8f9f7	452	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x28 /
<>	144:ef7eb2e8f9f7	453	__IO uint32_t IOPENR; /!< RCC Clock IO port enable register, Address offset: 0x2C /
<>	144:ef7eb2e8f9f7	454	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock enable register, Address offset: 0x30 /
<>	144:ef7eb2e8f9f7	455	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral enable register, Address offset: 0x34 /
<>	144:ef7eb2e8f9f7	456	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral enable register, Address offset: 0x38 /
<>	144:ef7eb2e8f9f7	457	__IO uint32_t IOPSMENR; /!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C /
<>	144:ef7eb2e8f9f7	458	__IO uint32_t AHBSMENR; /!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 /
<>	144:ef7eb2e8f9f7	459	__IO uint32_t APB2SMENR; /!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 /
<>	144:ef7eb2e8f9f7	460	__IO uint32_t APB1SMENR; /!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 /
<>	144:ef7eb2e8f9f7	461	__IO uint32_t CCIPR; /!< RCC clock configuration register, Address offset: 0x4C /
<>	144:ef7eb2e8f9f7	462	__IO uint32_t CSR; /!< RCC Control/status register, Address offset: 0x50 /
<>	144:ef7eb2e8f9f7	463	} RCC_TypeDef;
<>	144:ef7eb2e8f9f7	464
<>	144:ef7eb2e8f9f7	465	/**
<>	144:ef7eb2e8f9f7	466	* @brief Random numbers generator
<>	144:ef7eb2e8f9f7	467	*/
<>	144:ef7eb2e8f9f7	468	typedef struct
<>	144:ef7eb2e8f9f7	469	{
<>	144:ef7eb2e8f9f7	470	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	471	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	472	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	473	} RNG_TypeDef;
<>	144:ef7eb2e8f9f7	474
<>	144:ef7eb2e8f9f7	475	/**
<>	144:ef7eb2e8f9f7	476	* @brief Real-Time Clock
<>	144:ef7eb2e8f9f7	477	*/
<>	144:ef7eb2e8f9f7	478	typedef struct
<>	144:ef7eb2e8f9f7	479	{
<>	144:ef7eb2e8f9f7	480	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	481	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	482	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	483	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	484	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	485	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	486	uint32_t RESERVED; /!< Reserved, Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	487	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
<>	144:ef7eb2e8f9f7	488	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
<>	144:ef7eb2e8f9f7	489	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
<>	144:ef7eb2e8f9f7	490	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
<>	144:ef7eb2e8f9f7	491	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
<>	144:ef7eb2e8f9f7	492	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
<>	144:ef7eb2e8f9f7	493	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
<>	144:ef7eb2e8f9f7	494	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
<>	144:ef7eb2e8f9f7	495	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
<>	144:ef7eb2e8f9f7	496	__IO uint32_t TAMPCR; /!< RTC tamper configuration register, Address offset: 0x40 /
<>	144:ef7eb2e8f9f7	497	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
<>	144:ef7eb2e8f9f7	498	__IO uint32_t ALRMBSSR; /!< RTC alarm B sub second register, Address offset: 0x48 /
<>	144:ef7eb2e8f9f7	499	__IO uint32_t OR; /!< RTC option register, Address offset 0x4C /
<>	144:ef7eb2e8f9f7	500	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
<>	144:ef7eb2e8f9f7	501	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
<>	144:ef7eb2e8f9f7	502	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
<>	144:ef7eb2e8f9f7	503	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
<>	144:ef7eb2e8f9f7	504	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
<>	144:ef7eb2e8f9f7	505	} RTC_TypeDef;
<>	144:ef7eb2e8f9f7	506
<>	144:ef7eb2e8f9f7	507
<>	144:ef7eb2e8f9f7	508	/**
<>	144:ef7eb2e8f9f7	509	* @brief Serial Peripheral Interface
<>	144:ef7eb2e8f9f7	510	*/
<>	144:ef7eb2e8f9f7	511	typedef struct
<>	144:ef7eb2e8f9f7	512	{
<>	144:ef7eb2e8f9f7	513	__IO uint32_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	514	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	515	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	516	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	517	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	518	__IO uint32_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	519	__IO uint32_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	520	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
<>	144:ef7eb2e8f9f7	521	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
<>	144:ef7eb2e8f9f7	522	} SPI_TypeDef;
<>	144:ef7eb2e8f9f7	523
<>	144:ef7eb2e8f9f7	524	/**
<>	144:ef7eb2e8f9f7	525	* @brief TIM
<>	144:ef7eb2e8f9f7	526	*/
<>	144:ef7eb2e8f9f7	527	typedef struct
<>	144:ef7eb2e8f9f7	528	{
<>	144:ef7eb2e8f9f7	529	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	530	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	531	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	532	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	533	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	534	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	535	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	536	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
<>	144:ef7eb2e8f9f7	537	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
<>	144:ef7eb2e8f9f7	538	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
<>	144:ef7eb2e8f9f7	539	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
<>	144:ef7eb2e8f9f7	540	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
<>	144:ef7eb2e8f9f7	541	uint32_t RESERVED12;/!< Reserved Address offset: 0x30 /
<>	144:ef7eb2e8f9f7	542	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
<>	144:ef7eb2e8f9f7	543	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
<>	144:ef7eb2e8f9f7	544	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
<>	144:ef7eb2e8f9f7	545	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
<>	144:ef7eb2e8f9f7	546	uint32_t RESERVED17;/!< Reserved, Address offset: 0x44 /
<>	144:ef7eb2e8f9f7	547	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
<>	144:ef7eb2e8f9f7	548	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
<>	144:ef7eb2e8f9f7	549	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
<>	144:ef7eb2e8f9f7	550	} TIM_TypeDef;
<>	144:ef7eb2e8f9f7	551
<>	144:ef7eb2e8f9f7	552	/**
<>	144:ef7eb2e8f9f7	553	* @brief Touch Sensing Controller (TSC)
<>	144:ef7eb2e8f9f7	554	*/
<>	144:ef7eb2e8f9f7	555	typedef struct
<>	144:ef7eb2e8f9f7	556	{
<>	144:ef7eb2e8f9f7	557	__IO uint32_t CR; /!< TSC control register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	558	__IO uint32_t IER; /!< TSC interrupt enable register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	559	__IO uint32_t ICR; /!< TSC interrupt clear register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	560	__IO uint32_t ISR; /!< TSC interrupt status register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	561	__IO uint32_t IOHCR; /!< TSC I/O hysteresis control register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	562	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	563	__IO uint32_t IOASCR; /!< TSC I/O analog switch control register, Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	564	uint32_t RESERVED2; /!< Reserved, Address offset: 0x1C /
<>	144:ef7eb2e8f9f7	565	__IO uint32_t IOSCR; /!< TSC I/O sampling control register, Address offset: 0x20 /
<>	144:ef7eb2e8f9f7	566	uint32_t RESERVED3; /!< Reserved, Address offset: 0x24 /
<>	144:ef7eb2e8f9f7	567	__IO uint32_t IOCCR; /!< TSC I/O channel control register, Address offset: 0x28 /
<>	144:ef7eb2e8f9f7	568	uint32_t RESERVED4; /!< Reserved, Address offset: 0x2C /
<>	144:ef7eb2e8f9f7	569	__IO uint32_t IOGCSR; /!< TSC I/O group control status register, Address offset: 0x30 /
<>	144:ef7eb2e8f9f7	570	__IO uint32_t IOGXCR[8]; /!< TSC I/O group x counter register, Address offset: 0x34-50 /
<>	144:ef7eb2e8f9f7	571	} TSC_TypeDef;
<>	144:ef7eb2e8f9f7	572
<>	144:ef7eb2e8f9f7	573	/**
<>	144:ef7eb2e8f9f7	574	* @brief Universal Synchronous Asynchronous Receiver Transmitter
<>	144:ef7eb2e8f9f7	575	*/
<>	144:ef7eb2e8f9f7	576	typedef struct
<>	144:ef7eb2e8f9f7	577	{
<>	144:ef7eb2e8f9f7	578	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	579	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	580	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	581	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	582	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	583	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	584	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	585	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
<>	144:ef7eb2e8f9f7	586	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
<>	144:ef7eb2e8f9f7	587	__IO uint32_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
<>	144:ef7eb2e8f9f7	588	__IO uint32_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
<>	144:ef7eb2e8f9f7	589	} USART_TypeDef;
<>	144:ef7eb2e8f9f7	590
<>	144:ef7eb2e8f9f7	591	/**
<>	144:ef7eb2e8f9f7	592	* @brief Window WATCHDOG
<>	144:ef7eb2e8f9f7	593	*/
<>	144:ef7eb2e8f9f7	594	typedef struct
<>	144:ef7eb2e8f9f7	595	{
<>	144:ef7eb2e8f9f7	596	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	597	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	598	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	599	} WWDG_TypeDef;
<>	144:ef7eb2e8f9f7	600
<>	144:ef7eb2e8f9f7	601	/**
<>	144:ef7eb2e8f9f7	602	* @brief Universal Serial Bus Full Speed Device
<>	144:ef7eb2e8f9f7	603	*/
<>	144:ef7eb2e8f9f7	604	typedef struct
<>	144:ef7eb2e8f9f7	605	{
<>	144:ef7eb2e8f9f7	606	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
<>	144:ef7eb2e8f9f7	607	__IO uint16_t RESERVED0; /!< Reserved /
<>	144:ef7eb2e8f9f7	608	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
<>	144:ef7eb2e8f9f7	609	__IO uint16_t RESERVED1; /!< Reserved /
<>	144:ef7eb2e8f9f7	610	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
<>	144:ef7eb2e8f9f7	611	__IO uint16_t RESERVED2; /!< Reserved /
<>	144:ef7eb2e8f9f7	612	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
<>	144:ef7eb2e8f9f7	613	__IO uint16_t RESERVED3; /!< Reserved /
<>	144:ef7eb2e8f9f7	614	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
<>	144:ef7eb2e8f9f7	615	__IO uint16_t RESERVED4; /!< Reserved /
<>	144:ef7eb2e8f9f7	616	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
<>	144:ef7eb2e8f9f7	617	__IO uint16_t RESERVED5; /!< Reserved /
<>	144:ef7eb2e8f9f7	618	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
<>	144:ef7eb2e8f9f7	619	__IO uint16_t RESERVED6; /!< Reserved /
<>	144:ef7eb2e8f9f7	620	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
<>	144:ef7eb2e8f9f7	621	__IO uint16_t RESERVED7[17]; /!< Reserved /
<>	144:ef7eb2e8f9f7	622	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
<>	144:ef7eb2e8f9f7	623	__IO uint16_t RESERVED8; /!< Reserved /
<>	144:ef7eb2e8f9f7	624	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
<>	144:ef7eb2e8f9f7	625	__IO uint16_t RESERVED9; /!< Reserved /
<>	144:ef7eb2e8f9f7	626	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
<>	144:ef7eb2e8f9f7	627	__IO uint16_t RESERVEDA; /!< Reserved /
<>	144:ef7eb2e8f9f7	628	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
<>	144:ef7eb2e8f9f7	629	__IO uint16_t RESERVEDB; /!< Reserved /
<>	144:ef7eb2e8f9f7	630	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
<>	144:ef7eb2e8f9f7	631	__IO uint16_t RESERVEDC; /!< Reserved /
<>	144:ef7eb2e8f9f7	632	__IO uint16_t LPMCSR; /!< LPM Control and Status register, Address offset: 0x54 /
<>	144:ef7eb2e8f9f7	633	__IO uint16_t RESERVEDD; /!< Reserved /
<>	144:ef7eb2e8f9f7	634	__IO uint16_t BCDR; /!< Battery Charging detector register, Address offset: 0x58 /
<>	144:ef7eb2e8f9f7	635	__IO uint16_t RESERVEDE; /!< Reserved /
<>	144:ef7eb2e8f9f7	636	} USB_TypeDef;
<>	144:ef7eb2e8f9f7	637
<>	144:ef7eb2e8f9f7	638	/**
<>	144:ef7eb2e8f9f7	639	* @}
<>	144:ef7eb2e8f9f7	640	*/
<>	144:ef7eb2e8f9f7	641
<>	144:ef7eb2e8f9f7	642	/** @addtogroup Peripheral_memory_map
<>	144:ef7eb2e8f9f7	643	* @{
<>	144:ef7eb2e8f9f7	644	*/
<>	144:ef7eb2e8f9f7	645	#define FLASH_BASE ((uint32_t)0x08000000U) /!< FLASH base address in the alias region /
<>	144:ef7eb2e8f9f7	646	#define FLASH_BANK2_BASE ((uint32_t)0x08018000U) /!< FLASH BANK2 base address in the alias region /
<>	144:ef7eb2e8f9f7	647	#define FLASH_BANK1_END ((uint32_t)0x08017FFFU) /!< Program end FLASH BANK1 address /
<>	144:ef7eb2e8f9f7	648	#define FLASH_BANK2_END ((uint32_t)0x0802FFFFU) /!< Program end FLASH BANK2 address /
<>	144:ef7eb2e8f9f7	649	#define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /!< DATA_EEPROM base address in the alias region /
<>	144:ef7eb2e8f9f7	650	#define DATA_EEPROM_BANK2_BASE ((uint32_t)0x08080C00U) /!< DATA EEPROM BANK2 base address in the alias region /
<>	144:ef7eb2e8f9f7	651	#define DATA_EEPROM_BANK1_END ((uint32_t)0x08080BFFU) /!< Program end DATA EEPROM BANK1 address /
<>	144:ef7eb2e8f9f7	652	#define DATA_EEPROM_BANK2_END ((uint32_t)0x080817FFU) /!< Program end DATA EEPROM BANK2 address /
<>	144:ef7eb2e8f9f7	653	#define SRAM_BASE ((uint32_t)0x20000000U) /!< SRAM base address in the alias region /
<>	144:ef7eb2e8f9f7	654	#define PERIPH_BASE ((uint32_t)0x40000000U) /!< Peripheral base address in the alias region /
<>	144:ef7eb2e8f9f7	655
<>	144:ef7eb2e8f9f7	656	/!< Peripheral memory map /
<>	144:ef7eb2e8f9f7	657	#define APBPERIPH_BASE PERIPH_BASE
<>	144:ef7eb2e8f9f7	658	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
<>	144:ef7eb2e8f9f7	659	#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000)
<>	144:ef7eb2e8f9f7	660
<>	144:ef7eb2e8f9f7	661	#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
<>	144:ef7eb2e8f9f7	662	#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
<>	144:ef7eb2e8f9f7	663	#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
<>	144:ef7eb2e8f9f7	664	#define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
<>	144:ef7eb2e8f9f7	665	#define LCD_BASE (APBPERIPH_BASE + 0x00002400)
<>	144:ef7eb2e8f9f7	666	#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
<>	144:ef7eb2e8f9f7	667	#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
<>	144:ef7eb2e8f9f7	668	#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
<>	144:ef7eb2e8f9f7	669	#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
<>	144:ef7eb2e8f9f7	670	#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
<>	144:ef7eb2e8f9f7	671	#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800)
<>	144:ef7eb2e8f9f7	672	#define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
<>	144:ef7eb2e8f9f7	673	#define USART5_BASE (APBPERIPH_BASE + 0x00005000)
<>	144:ef7eb2e8f9f7	674	#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
<>	144:ef7eb2e8f9f7	675	#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
<>	144:ef7eb2e8f9f7	676	#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
<>	144:ef7eb2e8f9f7	677	#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
<>	144:ef7eb2e8f9f7	678	#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
<>	144:ef7eb2e8f9f7	679	#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00)
<>	144:ef7eb2e8f9f7	680	#define I2C3_BASE (APBPERIPH_BASE + 0x00007800)
<>	144:ef7eb2e8f9f7	681
<>	144:ef7eb2e8f9f7	682	#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
<>	144:ef7eb2e8f9f7	683	#define COMP1_BASE (APBPERIPH_BASE + 0x00010018)
<>	144:ef7eb2e8f9f7	684	#define COMP2_BASE (APBPERIPH_BASE + 0x0001001C)
<>	144:ef7eb2e8f9f7	685	#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
<>	144:ef7eb2e8f9f7	686	#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
<>	144:ef7eb2e8f9f7	687	#define TIM21_BASE (APBPERIPH_BASE + 0x00010800)
<>	144:ef7eb2e8f9f7	688	#define TIM22_BASE (APBPERIPH_BASE + 0x00011400)
<>	144:ef7eb2e8f9f7	689	#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00)
<>	144:ef7eb2e8f9f7	690	#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
<>	144:ef7eb2e8f9f7	691	#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
<>	144:ef7eb2e8f9f7	692	#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
<>	144:ef7eb2e8f9f7	693	#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
<>	144:ef7eb2e8f9f7	694	#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
<>	144:ef7eb2e8f9f7	695
<>	144:ef7eb2e8f9f7	696	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
<>	144:ef7eb2e8f9f7	697	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
<>	144:ef7eb2e8f9f7	698	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
<>	144:ef7eb2e8f9f7	699	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
<>	144:ef7eb2e8f9f7	700	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
<>	144:ef7eb2e8f9f7	701	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
<>	144:ef7eb2e8f9f7	702	#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
<>	144:ef7eb2e8f9f7	703	#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
<>	144:ef7eb2e8f9f7	704	#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8)
<>	144:ef7eb2e8f9f7	705
<>	144:ef7eb2e8f9f7	706
<>	144:ef7eb2e8f9f7	707	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
<>	144:ef7eb2e8f9f7	708	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /!< FLASH registers base address /
<>	144:ef7eb2e8f9f7	709	#define OB_BASE ((uint32_t)0x1FF80000U) /!< FLASH Option Bytes base address /
<>	144:ef7eb2e8f9f7	710	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
<>	144:ef7eb2e8f9f7	711	#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
<>	144:ef7eb2e8f9f7	712	#define RNG_BASE (AHBPERIPH_BASE + 0x00005000)
<>	144:ef7eb2e8f9f7	713
<>	144:ef7eb2e8f9f7	714	#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000)
<>	144:ef7eb2e8f9f7	715	#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400)
<>	144:ef7eb2e8f9f7	716	#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800)
<>	144:ef7eb2e8f9f7	717	#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00)
<>	144:ef7eb2e8f9f7	718	#define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000)
<>	144:ef7eb2e8f9f7	719	#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00)
<>	144:ef7eb2e8f9f7	720
<>	144:ef7eb2e8f9f7	721	/**
<>	144:ef7eb2e8f9f7	722	* @}
<>	144:ef7eb2e8f9f7	723	*/
<>	144:ef7eb2e8f9f7	724
<>	144:ef7eb2e8f9f7	725	/** @addtogroup Peripheral_declaration
<>	144:ef7eb2e8f9f7	726	* @{
<>	144:ef7eb2e8f9f7	727	*/
<>	144:ef7eb2e8f9f7	728
<>	144:ef7eb2e8f9f7	729	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
<>	144:ef7eb2e8f9f7	730	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
<>	144:ef7eb2e8f9f7	731	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
<>	144:ef7eb2e8f9f7	732	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
<>	144:ef7eb2e8f9f7	733	#define RTC ((RTC_TypeDef *) RTC_BASE)
<>	144:ef7eb2e8f9f7	734	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
<>	144:ef7eb2e8f9f7	735	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
<>	144:ef7eb2e8f9f7	736	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
<>	144:ef7eb2e8f9f7	737	#define USART2 ((USART_TypeDef *) USART2_BASE)
<>	144:ef7eb2e8f9f7	738	#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
<>	144:ef7eb2e8f9f7	739	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<>	144:ef7eb2e8f9f7	740	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
<>	144:ef7eb2e8f9f7	741	#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
<>	144:ef7eb2e8f9f7	742	#define CRS ((CRS_TypeDef *) CRS_BASE)
<>	144:ef7eb2e8f9f7	743	#define PWR ((PWR_TypeDef *) PWR_BASE)
<>	144:ef7eb2e8f9f7	744	#define DAC ((DAC_TypeDef *) DAC_BASE)
<>	144:ef7eb2e8f9f7	745	#define DAC1 ((DAC_TypeDef *) DAC_BASE)
<>	144:ef7eb2e8f9f7	746	#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
<>	144:ef7eb2e8f9f7	747	#define LCD ((LCD_TypeDef *) LCD_BASE)
<>	144:ef7eb2e8f9f7	748	#define USART4 ((USART_TypeDef *) USART4_BASE)
<>	144:ef7eb2e8f9f7	749	#define USART5 ((USART_TypeDef *) USART5_BASE)
<>	144:ef7eb2e8f9f7	750
<>	144:ef7eb2e8f9f7	751	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
<>	144:ef7eb2e8f9f7	752	#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
<>	144:ef7eb2e8f9f7	753	#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
<>	144:ef7eb2e8f9f7	754	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
<>	144:ef7eb2e8f9f7	755	#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
<>	144:ef7eb2e8f9f7	756	#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
<>	144:ef7eb2e8f9f7	757	#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
<>	144:ef7eb2e8f9f7	758	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
<>	144:ef7eb2e8f9f7	759	#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
<>	144:ef7eb2e8f9f7	760	/* Legacy defines */
<>	144:ef7eb2e8f9f7	761	#define ADC ADC1_COMMON
<>	144:ef7eb2e8f9f7	762	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
<>	144:ef7eb2e8f9f7	763	#define USART1 ((USART_TypeDef *) USART1_BASE)
<>	144:ef7eb2e8f9f7	764	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
<>	144:ef7eb2e8f9f7	767	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
<>	144:ef7eb2e8f9f7	768	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
<>	144:ef7eb2e8f9f7	769	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
<>	144:ef7eb2e8f9f7	770	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
<>	144:ef7eb2e8f9f7	771	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
<>	144:ef7eb2e8f9f7	772	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
<>	144:ef7eb2e8f9f7	773	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
<>	144:ef7eb2e8f9f7	774	#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
<>	144:ef7eb2e8f9f7	775
<>	144:ef7eb2e8f9f7	776
<>	144:ef7eb2e8f9f7	777	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
<>	144:ef7eb2e8f9f7	778	#define OB ((OB_TypeDef *) OB_BASE)
<>	144:ef7eb2e8f9f7	779	#define RCC ((RCC_TypeDef *) RCC_BASE)
<>	144:ef7eb2e8f9f7	780	#define CRC ((CRC_TypeDef *) CRC_BASE)
<>	144:ef7eb2e8f9f7	781	#define TSC ((TSC_TypeDef *) TSC_BASE)
<>	144:ef7eb2e8f9f7	782	#define RNG ((RNG_TypeDef *) RNG_BASE)
<>	144:ef7eb2e8f9f7	783
<>	144:ef7eb2e8f9f7	784	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
<>	144:ef7eb2e8f9f7	785	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
<>	144:ef7eb2e8f9f7	786	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
<>	144:ef7eb2e8f9f7	787	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
<>	144:ef7eb2e8f9f7	788	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
<>	144:ef7eb2e8f9f7	789	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
<>	144:ef7eb2e8f9f7	790
<>	144:ef7eb2e8f9f7	791	#define USB ((USB_TypeDef *) USB_BASE)
<>	144:ef7eb2e8f9f7	792
<>	144:ef7eb2e8f9f7	793	/**
<>	144:ef7eb2e8f9f7	794	* @}
<>	144:ef7eb2e8f9f7	795	*/
<>	144:ef7eb2e8f9f7	796
<>	144:ef7eb2e8f9f7	797	/** @addtogroup Exported_constants
<>	144:ef7eb2e8f9f7	798	* @{
<>	144:ef7eb2e8f9f7	799	*/
<>	144:ef7eb2e8f9f7	800
<>	144:ef7eb2e8f9f7	801	/** @addtogroup Peripheral_Registers_Bits_Definition
<>	144:ef7eb2e8f9f7	802	* @{
<>	144:ef7eb2e8f9f7	803	*/
<>	144:ef7eb2e8f9f7	804
<>	144:ef7eb2e8f9f7	805	/******************************************************************************/
<>	144:ef7eb2e8f9f7	806	/* Peripheral Registers Bits Definition */
<>	144:ef7eb2e8f9f7	807	/******************************************************************************/
<>	144:ef7eb2e8f9f7	808	/******************************************************************************/
<>	144:ef7eb2e8f9f7	809	/* */
<>	144:ef7eb2e8f9f7	810	/* Analog to Digital Converter (ADC) */
<>	144:ef7eb2e8f9f7	811	/* */
<>	144:ef7eb2e8f9f7	812	/******************************************************************************/
<>	144:ef7eb2e8f9f7	813	/****************** Bits definition for ADC_ISR register ****************/
<>	144:ef7eb2e8f9f7	814	#define ADC_ISR_EOCAL ((uint32_t)0x00000800U) /!< End of calibration flag /
<>	144:ef7eb2e8f9f7	815	#define ADC_ISR_AWD ((uint32_t)0x00000080U) /!< Analog watchdog flag /
<>	144:ef7eb2e8f9f7	816	#define ADC_ISR_OVR ((uint32_t)0x00000010U) /!< Overrun flag /
<>	144:ef7eb2e8f9f7	817	#define ADC_ISR_EOSEQ ((uint32_t)0x00000008U) /!< End of Sequence flag /
<>	144:ef7eb2e8f9f7	818	#define ADC_ISR_EOC ((uint32_t)0x00000004U) /!< End of Conversion /
<>	144:ef7eb2e8f9f7	819	#define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /!< End of sampling flag /
<>	144:ef7eb2e8f9f7	820	#define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /!< ADC Ready /
<>	144:ef7eb2e8f9f7	821
<>	144:ef7eb2e8f9f7	822	/* Old EOSEQ bit definition, maintained for legacy purpose */
<>	144:ef7eb2e8f9f7	823	#define ADC_ISR_EOS ADC_ISR_EOSEQ
<>	144:ef7eb2e8f9f7	824
<>	144:ef7eb2e8f9f7	825	/****************** Bits definition for ADC_IER register ****************/
<>	144:ef7eb2e8f9f7	826	#define ADC_IER_EOCALIE ((uint32_t)0x00000800U) /!< Enf Of Calibration interrupt enable /
<>	144:ef7eb2e8f9f7	827	#define ADC_IER_AWDIE ((uint32_t)0x00000080U) /!< Analog Watchdog interrupt enable /
<>	144:ef7eb2e8f9f7	828	#define ADC_IER_OVRIE ((uint32_t)0x00000010U) /!< Overrun interrupt enable /
<>	144:ef7eb2e8f9f7	829	#define ADC_IER_EOSEQIE ((uint32_t)0x00000008U) /!< End of Sequence of conversion interrupt enable /
<>	144:ef7eb2e8f9f7	830	#define ADC_IER_EOCIE ((uint32_t)0x00000004U) /!< End of Conversion interrupt enable /
<>	144:ef7eb2e8f9f7	831	#define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /!< End of sampling interrupt enable /
<>	144:ef7eb2e8f9f7	832	#define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /!< ADC Ready interrupt enable /
<>	144:ef7eb2e8f9f7	833
<>	144:ef7eb2e8f9f7	834	/* Old EOSEQIE bit definition, maintained for legacy purpose */
<>	144:ef7eb2e8f9f7	835	#define ADC_IER_EOSIE ADC_IER_EOSEQIE
<>	144:ef7eb2e8f9f7	836
<>	144:ef7eb2e8f9f7	837	/****************** Bits definition for ADC_CR register *****************/
<>	144:ef7eb2e8f9f7	838	#define ADC_CR_ADCAL ((uint32_t)0x80000000U) /!< ADC calibration /
<>	144:ef7eb2e8f9f7	839	#define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /!< ADC Voltage Regulator Enable /
<>	144:ef7eb2e8f9f7	840	#define ADC_CR_ADSTP ((uint32_t)0x00000010U) /!< ADC stop of conversion command /
<>	144:ef7eb2e8f9f7	841	#define ADC_CR_ADSTART ((uint32_t)0x00000004U) /!< ADC start of conversion /
<>	144:ef7eb2e8f9f7	842	#define ADC_CR_ADDIS ((uint32_t)0x00000002U) /!< ADC disable command /
<>	144:ef7eb2e8f9f7	843	#define ADC_CR_ADEN ((uint32_t)0x00000001U) /!< ADC enable control / /#### TBV /
<>	144:ef7eb2e8f9f7	844
<>	144:ef7eb2e8f9f7	845	/***************** Bits definition for ADC_CFGR1 register ***************/
<>	144:ef7eb2e8f9f7	846	#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000U) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
<>	144:ef7eb2e8f9f7	847	#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	848	#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	849	#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	850	#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000U) /!< Bit 3 /
<>	144:ef7eb2e8f9f7	851	#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000U) /!< Bit 4 /
<>	144:ef7eb2e8f9f7	852	#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000U) /!< Analog watchdog enable on regular channels /
<>	144:ef7eb2e8f9f7	853	#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000U) /!< Enable the watchdog on a single channel or on all channels /
<>	144:ef7eb2e8f9f7	854	#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /!< Discontinuous mode on regular channels /
<>	144:ef7eb2e8f9f7	855	#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /!< ADC auto power off /
<>	144:ef7eb2e8f9f7	856	#define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /!< ADC wait conversion mode /
<>	144:ef7eb2e8f9f7	857	#define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /!< Continuous Conversion /
<>	144:ef7eb2e8f9f7	858	#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /!< Overrun mode /
<>	144:ef7eb2e8f9f7	859	#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
<>	144:ef7eb2e8f9f7	860	#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	861	#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	862	#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
<>	144:ef7eb2e8f9f7	863	#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	864	#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	865	#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	866	#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /!< Data Alignment /
<>	144:ef7eb2e8f9f7	867	#define ADC_CFGR1_RES ((uint32_t)0x00000018U) /!< RES[1:0] bits (Resolution) /
<>	144:ef7eb2e8f9f7	868	#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	869	#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	870	#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /!< Sequence scan direction /
<>	144:ef7eb2e8f9f7	871	#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /!< Direct memory access configuration /
<>	144:ef7eb2e8f9f7	872	#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /!< Direct memory access enable /
<>	144:ef7eb2e8f9f7	873
<>	144:ef7eb2e8f9f7	874	/* Old WAIT bit definition, maintained for legacy purpose */
<>	144:ef7eb2e8f9f7	875	#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
<>	144:ef7eb2e8f9f7	876
<>	144:ef7eb2e8f9f7	877	/***************** Bits definition for ADC_CFGR2 register ***************/
<>	144:ef7eb2e8f9f7	878	#define ADC_CFGR2_TOVS ((uint32_t)0x80000200U) /!< Triggered Oversampling /
<>	144:ef7eb2e8f9f7	879	#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /!< OVSS [3:0] bits (Oversampling shift) /
<>	144:ef7eb2e8f9f7	880	#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	881	#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	882	#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	883	#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /!< Bit 3 /
<>	144:ef7eb2e8f9f7	884	#define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /!< OVSR [2:0] bits (Oversampling ratio) /
<>	144:ef7eb2e8f9f7	885	#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	886	#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	887	#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	888	#define ADC_CFGR2_OVSE ((uint32_t)0x00000001U) /!< Oversampler Enable /
<>	144:ef7eb2e8f9f7	889	#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /!< CKMODE [1:0] bits (ADC clock mode) /
<>	144:ef7eb2e8f9f7	890	#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	891	#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	892
<>	144:ef7eb2e8f9f7	893
<>	144:ef7eb2e8f9f7	894	/**************** Bit definition for ADC_SMPR register ******************/
<>	144:ef7eb2e8f9f7	895	#define ADC_SMPR_SMP ((uint32_t)0x00000007U) /!< SMPR[2:0] bits (Sampling time selection) /
<>	144:ef7eb2e8f9f7	896	#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	897	#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	898	#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	899
<>	144:ef7eb2e8f9f7	900	/* Legacy defines */
<>	144:ef7eb2e8f9f7	901	#define ADC_SMPR_SMPR ADC_SMPR_SMP
<>	144:ef7eb2e8f9f7	902	#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
<>	144:ef7eb2e8f9f7	903	#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
<>	144:ef7eb2e8f9f7	904	#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
<>	144:ef7eb2e8f9f7	905
<>	144:ef7eb2e8f9f7	906	/***************** Bit definition for ADC_TR register ******************/
<>	144:ef7eb2e8f9f7	907	#define ADC_TR_HT ((uint32_t)0x0FFF0000U) /!< Analog watchdog high threshold /
<>	144:ef7eb2e8f9f7	908	#define ADC_TR_LT ((uint32_t)0x00000FFFU) /!< Analog watchdog low threshold /
<>	144:ef7eb2e8f9f7	909
<>	144:ef7eb2e8f9f7	910	/**************** Bit definition for ADC_CHSELR register ****************/
<>	144:ef7eb2e8f9f7	911	#define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /!< ADC group regular sequencer channels /
<>	144:ef7eb2e8f9f7	912	#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /!< Channel 18 selection /
<>	144:ef7eb2e8f9f7	913	#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /!< Channel 17 selection /
<>	144:ef7eb2e8f9f7	914	#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000U) /!< Channel 16 selection /
<>	144:ef7eb2e8f9f7	915	#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /!< Channel 15 selection /
<>	144:ef7eb2e8f9f7	916	#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /!< Channel 14 selection /
<>	144:ef7eb2e8f9f7	917	#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /!< Channel 13 selection /
<>	144:ef7eb2e8f9f7	918	#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /!< Channel 12 selection /
<>	144:ef7eb2e8f9f7	919	#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /!< Channel 11 selection /
<>	144:ef7eb2e8f9f7	920	#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /!< Channel 10 selection /
<>	144:ef7eb2e8f9f7	921	#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /!< Channel 9 selection /
<>	144:ef7eb2e8f9f7	922	#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /!< Channel 8 selection /
<>	144:ef7eb2e8f9f7	923	#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /!< Channel 7 selection /
<>	144:ef7eb2e8f9f7	924	#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /!< Channel 6 selection /
<>	144:ef7eb2e8f9f7	925	#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /!< Channel 5 selection /
<>	144:ef7eb2e8f9f7	926	#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /!< Channel 4 selection /
<>	144:ef7eb2e8f9f7	927	#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /!< Channel 3 selection /
<>	144:ef7eb2e8f9f7	928	#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /!< Channel 2 selection /
<>	144:ef7eb2e8f9f7	929	#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /!< Channel 1 selection /
<>	144:ef7eb2e8f9f7	930	#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /!< Channel 0 selection /
<>	144:ef7eb2e8f9f7	931
<>	144:ef7eb2e8f9f7	932	/****************** Bit definition for ADC_DR register ******************/
<>	144:ef7eb2e8f9f7	933	#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /!< Regular data /
<>	144:ef7eb2e8f9f7	934
<>	144:ef7eb2e8f9f7	935	/****************** Bit definition for ADC_CALFACT register ******************/
<>	144:ef7eb2e8f9f7	936	#define ADC_CALFACT_CALFACT ((uint32_t)0x0000007FU) /!< Calibration factor /
<>	144:ef7eb2e8f9f7	937
<>	144:ef7eb2e8f9f7	938	/***************** Bit definition for ADC_CCR register ******************/
<>	144:ef7eb2e8f9f7	939	#define ADC_CCR_LFMEN ((uint32_t)0x02000000U) /!< Low Frequency Mode enable /
<>	144:ef7eb2e8f9f7	940	#define ADC_CCR_VLCDEN ((uint32_t)0x01000000U) /!< Voltage LCD enable /
<>	144:ef7eb2e8f9f7	941	#define ADC_CCR_TSEN ((uint32_t)0x00800000U) /!< Temperature sensore enable /
<>	144:ef7eb2e8f9f7	942	#define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /!< Vrefint enable /
<>	144:ef7eb2e8f9f7	943	#define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /!< PRESC [3:0] bits (ADC prescaler) /
<>	144:ef7eb2e8f9f7	944	#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	945	#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	946	#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	947	#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /!< Bit 3 /
<>	144:ef7eb2e8f9f7	948
<>	144:ef7eb2e8f9f7	949	/******************************************************************************/
<>	144:ef7eb2e8f9f7	950	/* */
<>	144:ef7eb2e8f9f7	951	/* Analog Comparators (COMP) */
<>	144:ef7eb2e8f9f7	952	/* */
<>	144:ef7eb2e8f9f7	953	/******************************************************************************/
<>	144:ef7eb2e8f9f7	954	/*********** Bit definition for COMP_CSR register (COMP1 and COMP2) ************/
<>	144:ef7eb2e8f9f7	955	/* COMP1 bits definition */
<>	144:ef7eb2e8f9f7	956	#define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /!< COMP1 enable /
<>	144:ef7eb2e8f9f7	957	#define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030U) /!< COMP1 inverting input select /
<>	144:ef7eb2e8f9f7	958	#define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010U) /!< COMP1 inverting input select bit 0 /
<>	144:ef7eb2e8f9f7	959	#define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020U) /!< COMP1 inverting input select bit 1 /
<>	144:ef7eb2e8f9f7	960	#define COMP_CSR_COMP1WM ((uint32_t)0x00000100U) /!< Comparators window mode enable /
<>	144:ef7eb2e8f9f7	961	#define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000U) /!< COMP1 LPTIM1 IN1 connection /
<>	144:ef7eb2e8f9f7	962	#define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000U) /!< COMP1 output polarity /
<>	144:ef7eb2e8f9f7	963	#define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000U) /!< COMP1 output level /
<>	144:ef7eb2e8f9f7	964	#define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000U) /!< COMP1 lock /
<>	144:ef7eb2e8f9f7	965	/* COMP2 bits definition */
<>	144:ef7eb2e8f9f7	966	#define COMP_CSR_COMP2EN ((uint32_t)0x00000001U) /!< COMP2 enable /
<>	144:ef7eb2e8f9f7	967	#define COMP_CSR_COMP2SPEED ((uint32_t)0x00000008U) /!< COMP2 power mode /
<>	144:ef7eb2e8f9f7	968	#define COMP_CSR_COMP2INNSEL ((uint32_t)0x00000070U) /!< COMP2 inverting input select /
<>	144:ef7eb2e8f9f7	969	#define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00000010U) /!< COMP2 inverting input select bit 0 /
<>	144:ef7eb2e8f9f7	970	#define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00000020U) /!< COMP2 inverting input select bit 1 /
<>	144:ef7eb2e8f9f7	971	#define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00000040U) /!< COMP2 inverting input select bit 2 /
<>	144:ef7eb2e8f9f7	972	#define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700U) /!< COMPx non inverting input select /
<>	144:ef7eb2e8f9f7	973	#define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100U) /!< COMPx non inverting input select /
<>	144:ef7eb2e8f9f7	974	#define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200U) /!< COMPx non inverting input select /
<>	144:ef7eb2e8f9f7	975	#define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400U) /!< COMPx non inverting input select /
<>	144:ef7eb2e8f9f7	976	#define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000U) /!< COMP2 LPTIM1 IN2 connection /
<>	144:ef7eb2e8f9f7	977	#define COMP_CSR_COMP2LPTIM1IN1 ((uint32_t)0x00002000U) /!< COMP2 LPTIM1 IN1 connection /
<>	144:ef7eb2e8f9f7	978	#define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000U) /!< COMP2 output polarity /
<>	144:ef7eb2e8f9f7	979	#define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000U) /!< COMP2 output level /
<>	144:ef7eb2e8f9f7	980	#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /!< COMP2 lock /
<>	144:ef7eb2e8f9f7	981
<>	144:ef7eb2e8f9f7	982	/******************** Bit definition for COMP_CSR register common **************/
<>	144:ef7eb2e8f9f7	983	#define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /!< COMPx enable /
<>	144:ef7eb2e8f9f7	984	#define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000U) /!< COMPx output polarity /
<>	144:ef7eb2e8f9f7	985	#define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000U) /!< COMPx output level /
<>	144:ef7eb2e8f9f7	986	#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000U) /!< COMPx lock /
<>	144:ef7eb2e8f9f7	987
<>	144:ef7eb2e8f9f7	988	/* Reference defines */
<>	144:ef7eb2e8f9f7	989	#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) /
<>	144:ef7eb2e8f9f7	990
<>	144:ef7eb2e8f9f7	991	/******************************************************************************/
<>	144:ef7eb2e8f9f7	992	/* */
<>	144:ef7eb2e8f9f7	993	/* CRC calculation unit (CRC) */
<>	144:ef7eb2e8f9f7	994	/* */
<>	144:ef7eb2e8f9f7	995	/******************************************************************************/
<>	144:ef7eb2e8f9f7	996	/***************** Bit definition for CRC_DR register *******************/
<>	144:ef7eb2e8f9f7	997	#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /!< Data register bits /
<>	144:ef7eb2e8f9f7	998
<>	144:ef7eb2e8f9f7	999	/***************** Bit definition for CRC_IDR register ******************/
<>	144:ef7eb2e8f9f7	1000	#define CRC_IDR_IDR ((uint8_t)0xFFU) /!< General-purpose 8-bit data register bits /
<>	144:ef7eb2e8f9f7	1001
<>	144:ef7eb2e8f9f7	1002	/****************** Bit definition for CRC_CR register ******************/
<>	144:ef7eb2e8f9f7	1003	#define CRC_CR_RESET ((uint32_t)0x00000001U) /!< RESET the CRC computation unit bit /
<>	144:ef7eb2e8f9f7	1004	#define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /!< Polynomial size bits /
<>	144:ef7eb2e8f9f7	1005	#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /!< Polynomial size bit 0 /
<>	144:ef7eb2e8f9f7	1006	#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /!< Polynomial size bit 1 /
<>	144:ef7eb2e8f9f7	1007	#define CRC_CR_REV_IN ((uint32_t)0x00000060U) /!< REV_IN Reverse Input Data bits /
<>	144:ef7eb2e8f9f7	1008	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	1009	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	1010	#define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /!< REV_OUT Reverse Output Data bits /
<>	144:ef7eb2e8f9f7	1011
<>	144:ef7eb2e8f9f7	1012	/***************** Bit definition for CRC_INIT register *****************/
<>	144:ef7eb2e8f9f7	1013	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /!< Initial CRC value bits /
<>	144:ef7eb2e8f9f7	1014
<>	144:ef7eb2e8f9f7	1015	/***************** Bit definition for CRC_POL register ******************/
<>	144:ef7eb2e8f9f7	1016	#define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /!< Coefficients of the polynomial /
<>	144:ef7eb2e8f9f7	1017
<>	144:ef7eb2e8f9f7	1018	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1019	/* */
<>	144:ef7eb2e8f9f7	1020	/* CRS Clock Recovery System */
<>	144:ef7eb2e8f9f7	1021	/* */
<>	144:ef7eb2e8f9f7	1022	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1023
<>	144:ef7eb2e8f9f7	1024	/***************** Bit definition for CRS_CR register *******************/
<>	144:ef7eb2e8f9f7	1025	#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001U) /* SYNC event OK interrupt enable */
<>	144:ef7eb2e8f9f7	1026	#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002U) /* SYNC warning interrupt enable */
<>	144:ef7eb2e8f9f7	1027	#define CRS_CR_ERRIE ((uint32_t)0x00000004U) /* SYNC error interrupt enable */
<>	144:ef7eb2e8f9f7	1028	#define CRS_CR_ESYNCIE ((uint32_t)0x00000008U) /* Expected SYNC(ESYNCF) interrupt Enable*/
<>	144:ef7eb2e8f9f7	1029	#define CRS_CR_CEN ((uint32_t)0x00000020U) /* Frequency error counter enable */
<>	144:ef7eb2e8f9f7	1030	#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040U) /* Automatic trimming enable */
<>	144:ef7eb2e8f9f7	1031	#define CRS_CR_SWSYNC ((uint32_t)0x00000080U) /* A Software SYNC event is generated */
<>	144:ef7eb2e8f9f7	1032	#define CRS_CR_TRIM ((uint32_t)0x00003F00U) /* HSI48 oscillator smooth trimming */
<>	144:ef7eb2e8f9f7	1033
<>	144:ef7eb2e8f9f7	1034	/***************** Bit definition for CRS_CFGR register *******************/
<>	144:ef7eb2e8f9f7	1035	#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFFU) /* Counter reload value */
<>	144:ef7eb2e8f9f7	1036	#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000U) /* Frequency error limit */
<>	144:ef7eb2e8f9f7	1037
<>	144:ef7eb2e8f9f7	1038	#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000U) /* SYNC divider */
<>	144:ef7eb2e8f9f7	1039	#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000U) /* Bit 0 */
<>	144:ef7eb2e8f9f7	1040	#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000U) /* Bit 1 */
<>	144:ef7eb2e8f9f7	1041	#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000U) /* Bit 2 */
<>	144:ef7eb2e8f9f7	1042
<>	144:ef7eb2e8f9f7	1043	#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000U) /* SYNC signal source selection */
<>	144:ef7eb2e8f9f7	1044	#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000U) /* Bit 0 */
<>	144:ef7eb2e8f9f7	1045	#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000U) /* Bit 1 */
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000U) /* SYNC polarity selection */
<>	144:ef7eb2e8f9f7	1048
<>	144:ef7eb2e8f9f7	1049	/***************** Bit definition for CRS_ISR register *******************/
<>	144:ef7eb2e8f9f7	1050	#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001U) /* SYNC event OK flag */
<>	144:ef7eb2e8f9f7	1051	#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002U) /* SYNC warning */
<>	144:ef7eb2e8f9f7	1052	#define CRS_ISR_ERRF ((uint32_t)0x00000004U) /* SYNC error flag */
<>	144:ef7eb2e8f9f7	1053	#define CRS_ISR_ESYNCF ((uint32_t)0x00000008U) /* Expected SYNC flag */
<>	144:ef7eb2e8f9f7	1054	#define CRS_ISR_SYNCERR ((uint32_t)0x00000100U) /* SYNC error */
<>	144:ef7eb2e8f9f7	1055	#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200U) /* SYNC missed */
<>	144:ef7eb2e8f9f7	1056	#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400U) /* Trimming overflow or underflow */
<>	144:ef7eb2e8f9f7	1057	#define CRS_ISR_FEDIR ((uint32_t)0x00008000U) /* Frequency error direction */
<>	144:ef7eb2e8f9f7	1058	#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000U) /* Frequency error capture */
<>	144:ef7eb2e8f9f7	1059
<>	144:ef7eb2e8f9f7	1060	/***************** Bit definition for CRS_ICR register *******************/
<>	144:ef7eb2e8f9f7	1061	#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001U) /* SYNC event OK clear flag */
<>	144:ef7eb2e8f9f7	1062	#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002U) /* SYNC warning clear flag */
<>	144:ef7eb2e8f9f7	1063	#define CRS_ICR_ERRC ((uint32_t)0x00000004U) /* Error clear flag */
<>	144:ef7eb2e8f9f7	1064	#define CRS_ICR_ESYNCC ((uint32_t)0x00000008U) /* Expected SYNC clear flag */
<>	144:ef7eb2e8f9f7	1065
<>	144:ef7eb2e8f9f7	1066	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1067	/* */
<>	144:ef7eb2e8f9f7	1068	/* Digital to Analog Converter (DAC) */
<>	144:ef7eb2e8f9f7	1069	/* */
<>	144:ef7eb2e8f9f7	1070	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1071
<>	144:ef7eb2e8f9f7	1072	/*
<>	144:ef7eb2e8f9f7	1073	* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
<>	144:ef7eb2e8f9f7	1074	*/
<>	144:ef7eb2e8f9f7	1075	#define DAC_CHANNEL2_SUPPORT /!< DAC feature available only on specific devices: availability of DAC channel 2 /
<>	144:ef7eb2e8f9f7	1076
<>	144:ef7eb2e8f9f7	1077	/****************** Bit definition for DAC_CR register ******************/
<>	144:ef7eb2e8f9f7	1078	#define DAC_CR_EN1 ((uint32_t)0x00000001U) /!< DAC channel1 enable /
<>	144:ef7eb2e8f9f7	1079	#define DAC_CR_BOFF1 ((uint32_t)0x00000002U) /!< DAC channel1 output buffer disable /
<>	144:ef7eb2e8f9f7	1080	#define DAC_CR_TEN1 ((uint32_t)0x00000004U) /!< DAC channel1 Trigger enable /
<>	144:ef7eb2e8f9f7	1081
<>	144:ef7eb2e8f9f7	1082	#define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
<>	144:ef7eb2e8f9f7	1083	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	1084	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	1085	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	1086
<>	144:ef7eb2e8f9f7	1087	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
<>	144:ef7eb2e8f9f7	1088	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	1089	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	1090
<>	144:ef7eb2e8f9f7	1091	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
<>	144:ef7eb2e8f9f7	1092	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	1093	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	1094	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	1095	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /!< Bit 3 /
<>	144:ef7eb2e8f9f7	1096
<>	144:ef7eb2e8f9f7	1097	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /!< DAC channel1 DMA enable /
<>	144:ef7eb2e8f9f7	1098	#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /!< DAC channel1 DMA Underrun interrupt enable /
<>	144:ef7eb2e8f9f7	1099
<>	144:ef7eb2e8f9f7	1100	#define DAC_CR_EN2 ((uint32_t)0x00010000U) /!< DAC channel2 enable /
<>	144:ef7eb2e8f9f7	1101	#define DAC_CR_BOFF2 ((uint32_t)0x00020000U) /!< DAC channel2 output buffer disable /
<>	144:ef7eb2e8f9f7	1102	#define DAC_CR_TEN2 ((uint32_t)0x00040000U) /!< DAC channel2 Trigger enable /
<>	144:ef7eb2e8f9f7	1103
<>	144:ef7eb2e8f9f7	1104	#define DAC_CR_TSEL2 ((uint32_t)0x00380000U) /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
<>	144:ef7eb2e8f9f7	1105	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	1106	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	1107	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	1108
<>	144:ef7eb2e8f9f7	1109	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000U) /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
<>	144:ef7eb2e8f9f7	1110	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	1111	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	1112
<>	144:ef7eb2e8f9f7	1113	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000U) /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
<>	144:ef7eb2e8f9f7	1114	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	1115	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	1116	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	1117	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000U) /!< Bit 3 /
<>	144:ef7eb2e8f9f7	1118
<>	144:ef7eb2e8f9f7	1119	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000U) /!< DAC channel2 DMA enabled /
<>	144:ef7eb2e8f9f7	1120	#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000U) /!< DAC channel12DMA Underrun interrupt enable /
<>	144:ef7eb2e8f9f7	1121
<>	144:ef7eb2e8f9f7	1122	/*************** Bit definition for DAC_SWTRIGR register ****************/
<>	144:ef7eb2e8f9f7	1123	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /!< DAC channel1 software trigger /
<>	144:ef7eb2e8f9f7	1124	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002U) /!< DAC channel2 software trigger /
<>	144:ef7eb2e8f9f7	1125
<>	144:ef7eb2e8f9f7	1126	/*************** Bit definition for DAC_DHR12R1 register ****************/
<>	144:ef7eb2e8f9f7	1127	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /!< DAC channel1 12-bit Right aligned data /
<>	144:ef7eb2e8f9f7	1128
<>	144:ef7eb2e8f9f7	1129	/*************** Bit definition for DAC_DHR12L1 register ****************/
<>	144:ef7eb2e8f9f7	1130	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /!< DAC channel1 12-bit Left aligned data /
<>	144:ef7eb2e8f9f7	1131
<>	144:ef7eb2e8f9f7	1132	/**************** Bit definition for DAC_DHR8R1 register ****************/
<>	144:ef7eb2e8f9f7	1133	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /!< DAC channel1 8-bit Right aligned data /
<>	144:ef7eb2e8f9f7	1134
<>	144:ef7eb2e8f9f7	1135	/*************** Bit definition for DAC_DHR12R2 register ****************/
<>	144:ef7eb2e8f9f7	1136	#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFFU) /!< DAC channel2 12-bit Right aligned data /
<>	144:ef7eb2e8f9f7	1137
<>	144:ef7eb2e8f9f7	1138	/*************** Bit definition for DAC_DHR12L2 register ****************/
<>	144:ef7eb2e8f9f7	1139	#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0U) /!< DAC channel2 12-bit Left aligned data /
<>	144:ef7eb2e8f9f7	1140
<>	144:ef7eb2e8f9f7	1141	/**************** Bit definition for DAC_DHR8R2 register ****************/
<>	144:ef7eb2e8f9f7	1142	#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FFU) /!< DAC channel2 8-bit Right aligned data /
<>	144:ef7eb2e8f9f7	1143
<>	144:ef7eb2e8f9f7	1144	/*************** Bit definition for DAC_DHR12RD register ****************/
<>	144:ef7eb2e8f9f7	1145	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFFU) /!< DAC channel1 12-bit Right aligned data /
<>	144:ef7eb2e8f9f7	1146	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000U) /!< DAC channel2 12-bit Right aligned data /
<>	144:ef7eb2e8f9f7	1147
<>	144:ef7eb2e8f9f7	1148	/*************** Bit definition for DAC_DHR12LD register ****************/
<>	144:ef7eb2e8f9f7	1149	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0U) /!< DAC channel1 12-bit Left aligned data /
<>	144:ef7eb2e8f9f7	1150	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000U) /!< DAC channel2 12-bit Left aligned data /
<>	144:ef7eb2e8f9f7	1151
<>	144:ef7eb2e8f9f7	1152	/**************** Bit definition for DAC_DHR8RD register ****************/
<>	144:ef7eb2e8f9f7	1153	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FFU) /!< DAC channel1 8-bit Right aligned data /
<>	144:ef7eb2e8f9f7	1154	#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00U) /!< DAC channel2 8-bit Right aligned data /
<>	144:ef7eb2e8f9f7	1155
<>	144:ef7eb2e8f9f7	1156	/***************** Bit definition for DAC_DOR1 register *****************/
<>	144:ef7eb2e8f9f7	1157	#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /!< DAC channel1 data output /
<>	144:ef7eb2e8f9f7	1158
<>	144:ef7eb2e8f9f7	1159	/***************** Bit definition for DAC_DOR2 register *****************/
<>	144:ef7eb2e8f9f7	1160	#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFFU) /!< DAC channel2 data output /
<>	144:ef7eb2e8f9f7	1161
<>	144:ef7eb2e8f9f7	1162	/****************** Bit definition for DAC_SR register ******************/
<>	144:ef7eb2e8f9f7	1163	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /!< DAC channel1 DMA underrun flag /
<>	144:ef7eb2e8f9f7	1164	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000U) /!< DAC channel2 DMA underrun flag /
<>	144:ef7eb2e8f9f7	1165
<>	144:ef7eb2e8f9f7	1166	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1167	/* */
<>	144:ef7eb2e8f9f7	1168	/* Debug MCU (DBGMCU) */
<>	144:ef7eb2e8f9f7	1169	/* */
<>	144:ef7eb2e8f9f7	1170	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1171
<>	144:ef7eb2e8f9f7	1172	/************** Bit definition for DBGMCU_IDCODE register ***************/
<>	144:ef7eb2e8f9f7	1173	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /!< Device Identifier /
<>	144:ef7eb2e8f9f7	1174
<>	144:ef7eb2e8f9f7	1175	#define DBGMCU_IDCODE_DIV_ID ((uint32_t)0x0000F000U) /!< Division Identifier /
<>	144:ef7eb2e8f9f7	1176	#define DBGMCU_IDCODE_MCD_DIV_ID ((uint32_t)0x00006000U) /!< MCD divsion ID is 6 /
<>	144:ef7eb2e8f9f7	1177	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /!< REV_ID[15:0] bits (Revision Identifier) /
<>	144:ef7eb2e8f9f7	1178	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	1179	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	1180	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	1181	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /!< Bit 3 /
<>	144:ef7eb2e8f9f7	1182	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /!< Bit 4 /
<>	144:ef7eb2e8f9f7	1183	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /!< Bit 5 /
<>	144:ef7eb2e8f9f7	1184	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /!< Bit 6 /
<>	144:ef7eb2e8f9f7	1185	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /!< Bit 7 /
<>	144:ef7eb2e8f9f7	1186	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /!< Bit 8 /
<>	144:ef7eb2e8f9f7	1187	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /!< Bit 9 /
<>	144:ef7eb2e8f9f7	1188	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /!< Bit 10 /
<>	144:ef7eb2e8f9f7	1189	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /!< Bit 11 /
<>	144:ef7eb2e8f9f7	1190	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /!< Bit 12 /
<>	144:ef7eb2e8f9f7	1191	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /!< Bit 13 /
<>	144:ef7eb2e8f9f7	1192	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /!< Bit 14 /
<>	144:ef7eb2e8f9f7	1193	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /!< Bit 15 /
<>	144:ef7eb2e8f9f7	1194
<>	144:ef7eb2e8f9f7	1195	/**************** Bit definition for DBGMCU_CR register *****************/
<>	144:ef7eb2e8f9f7	1196	#define DBGMCU_CR_DBG ((uint32_t)0x00000007U) /!< Debug mode mask /
<>	144:ef7eb2e8f9f7	1197	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /!< Debug Sleep Mode /
<>	144:ef7eb2e8f9f7	1198	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /!< Debug Stop Mode /
<>	144:ef7eb2e8f9f7	1199	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /!< Debug Standby mode /
<>	144:ef7eb2e8f9f7	1200
<>	144:ef7eb2e8f9f7	1201	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
<>	144:ef7eb2e8f9f7	1202	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /!< TIM2 counter stopped when core is halted /
<>	144:ef7eb2e8f9f7	1203	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	1204	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010U) /!< TIM6 counter stopped when core is halted /
<>	144:ef7eb2e8f9f7	1205	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	1206	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /!< RTC Calendar frozen when core is halted /
<>	144:ef7eb2e8f9f7	1207	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /!< Debug Window Watchdog stopped when Core is halted /
<>	144:ef7eb2e8f9f7	1208	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /!< Debug Independent Watchdog stopped when Core is halted /
<>	144:ef7eb2e8f9f7	1209	#define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000U) /!< I2C1 SMBUS timeout mode stopped when Core is halted /
<>	144:ef7eb2e8f9f7	1210	#define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000U) /!< I2C2 SMBUS timeout mode stopped when Core is halted /
<>	144:ef7eb2e8f9f7	1211	#define DBGMCU_APB1_FZ_DBG_I2C3_STOP ((uint32_t)0x00800000U) /!< I2C3 SMBUS timeout mode stopped when Core is halted /
<>	144:ef7eb2e8f9f7	1212	#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000U) /!< LPTIM1 counter stopped when core is halted /
<>	144:ef7eb2e8f9f7	1213	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
<>	144:ef7eb2e8f9f7	1214	#define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020U) /!< TIM22 counter stopped when core is halted /
<>	144:ef7eb2e8f9f7	1215	#define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004U) /!< TIM21 counter stopped when core is halted /
<>	144:ef7eb2e8f9f7	1216
<>	144:ef7eb2e8f9f7	1217	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1218	/* */
<>	144:ef7eb2e8f9f7	1219	/* DMA Controller (DMA) */
<>	144:ef7eb2e8f9f7	1220	/* */
<>	144:ef7eb2e8f9f7	1221	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1222
<>	144:ef7eb2e8f9f7	1223	/***************** Bit definition for DMA_ISR register ******************/
<>	144:ef7eb2e8f9f7	1224	#define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /!< Channel 1 Global interrupt flag /
<>	144:ef7eb2e8f9f7	1225	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /!< Channel 1 Transfer Complete flag /
<>	144:ef7eb2e8f9f7	1226	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /!< Channel 1 Half Transfer flag /
<>	144:ef7eb2e8f9f7	1227	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /!< Channel 1 Transfer Error flag /
<>	144:ef7eb2e8f9f7	1228	#define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /!< Channel 2 Global interrupt flag /
<>	144:ef7eb2e8f9f7	1229	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /!< Channel 2 Transfer Complete flag /
<>	144:ef7eb2e8f9f7	1230	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /!< Channel 2 Half Transfer flag /
<>	144:ef7eb2e8f9f7	1231	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /!< Channel 2 Transfer Error flag /
<>	144:ef7eb2e8f9f7	1232	#define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /!< Channel 3 Global interrupt flag /
<>	144:ef7eb2e8f9f7	1233	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /!< Channel 3 Transfer Complete flag /
<>	144:ef7eb2e8f9f7	1234	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /!< Channel 3 Half Transfer flag /
<>	144:ef7eb2e8f9f7	1235	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /!< Channel 3 Transfer Error flag /
<>	144:ef7eb2e8f9f7	1236	#define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /!< Channel 4 Global interrupt flag /
<>	144:ef7eb2e8f9f7	1237	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /!< Channel 4 Transfer Complete flag /
<>	144:ef7eb2e8f9f7	1238	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /!< Channel 4 Half Transfer flag /
<>	144:ef7eb2e8f9f7	1239	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /!< Channel 4 Transfer Error flag /
<>	144:ef7eb2e8f9f7	1240	#define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /!< Channel 5 Global interrupt flag /
<>	144:ef7eb2e8f9f7	1241	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /!< Channel 5 Transfer Complete flag /
<>	144:ef7eb2e8f9f7	1242	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /!< Channel 5 Half Transfer flag /
<>	144:ef7eb2e8f9f7	1243	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /!< Channel 5 Transfer Error flag /
<>	144:ef7eb2e8f9f7	1244	#define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /!< Channel 6 Global interrupt flag /
<>	144:ef7eb2e8f9f7	1245	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /!< Channel 6 Transfer Complete flag /
<>	144:ef7eb2e8f9f7	1246	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /!< Channel 6 Half Transfer flag /
<>	144:ef7eb2e8f9f7	1247	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /!< Channel 6 Transfer Error flag /
<>	144:ef7eb2e8f9f7	1248	#define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /!< Channel 7 Global interrupt flag /
<>	144:ef7eb2e8f9f7	1249	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /!< Channel 7 Transfer Complete flag /
<>	144:ef7eb2e8f9f7	1250	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /!< Channel 7 Half Transfer flag /
<>	144:ef7eb2e8f9f7	1251	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /!< Channel 7 Transfer Error flag /
<>	144:ef7eb2e8f9f7	1252
<>	144:ef7eb2e8f9f7	1253	/***************** Bit definition for DMA_IFCR register *****************/
<>	144:ef7eb2e8f9f7	1254	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /!< Channel 1 Global interrupt clear /
<>	144:ef7eb2e8f9f7	1255	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /!< Channel 1 Transfer Complete clear /
<>	144:ef7eb2e8f9f7	1256	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /!< Channel 1 Half Transfer clear /
<>	144:ef7eb2e8f9f7	1257	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /!< Channel 1 Transfer Error clear /
<>	144:ef7eb2e8f9f7	1258	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /!< Channel 2 Global interrupt clear /
<>	144:ef7eb2e8f9f7	1259	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /!< Channel 2 Transfer Complete clear /
<>	144:ef7eb2e8f9f7	1260	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /!< Channel 2 Half Transfer clear /
<>	144:ef7eb2e8f9f7	1261	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /!< Channel 2 Transfer Error clear /
<>	144:ef7eb2e8f9f7	1262	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /!< Channel 3 Global interrupt clear /
<>	144:ef7eb2e8f9f7	1263	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /!< Channel 3 Transfer Complete clear /
<>	144:ef7eb2e8f9f7	1264	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /!< Channel 3 Half Transfer clear /
<>	144:ef7eb2e8f9f7	1265	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /!< Channel 3 Transfer Error clear /
<>	144:ef7eb2e8f9f7	1266	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /!< Channel 4 Global interrupt clear /
<>	144:ef7eb2e8f9f7	1267	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /!< Channel 4 Transfer Complete clear /
<>	144:ef7eb2e8f9f7	1268	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /!< Channel 4 Half Transfer clear /
<>	144:ef7eb2e8f9f7	1269	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /!< Channel 4 Transfer Error clear /
<>	144:ef7eb2e8f9f7	1270	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /!< Channel 5 Global interrupt clear /
<>	144:ef7eb2e8f9f7	1271	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /!< Channel 5 Transfer Complete clear /
<>	144:ef7eb2e8f9f7	1272	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /!< Channel 5 Half Transfer clear /
<>	144:ef7eb2e8f9f7	1273	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /!< Channel 5 Transfer Error clear /
<>	144:ef7eb2e8f9f7	1274	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /!< Channel 6 Global interrupt clear /
<>	144:ef7eb2e8f9f7	1275	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /!< Channel 6 Transfer Complete clear /
<>	144:ef7eb2e8f9f7	1276	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /!< Channel 6 Half Transfer clear /
<>	144:ef7eb2e8f9f7	1277	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /!< Channel 6 Transfer Error clear /
<>	144:ef7eb2e8f9f7	1278	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /!< Channel 7 Global interrupt clear /
<>	144:ef7eb2e8f9f7	1279	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /!< Channel 7 Transfer Complete clear /
<>	144:ef7eb2e8f9f7	1280	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /!< Channel 7 Half Transfer clear /
<>	144:ef7eb2e8f9f7	1281	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /!< Channel 7 Transfer Error clear /
<>	144:ef7eb2e8f9f7	1282
<>	144:ef7eb2e8f9f7	1283	/***************** Bit definition for DMA_CCR register ******************/
<>	144:ef7eb2e8f9f7	1284	#define DMA_CCR_EN ((uint32_t)0x00000001U) /!< Channel enable /
<>	144:ef7eb2e8f9f7	1285	#define DMA_CCR_TCIE ((uint32_t)0x00000002U) /!< Transfer complete interrupt enable /
<>	144:ef7eb2e8f9f7	1286	#define DMA_CCR_HTIE ((uint32_t)0x00000004U) /!< Half Transfer interrupt enable /
<>	144:ef7eb2e8f9f7	1287	#define DMA_CCR_TEIE ((uint32_t)0x00000008U) /!< Transfer error interrupt enable /
<>	144:ef7eb2e8f9f7	1288	#define DMA_CCR_DIR ((uint32_t)0x00000010U) /!< Data transfer direction /
<>	144:ef7eb2e8f9f7	1289	#define DMA_CCR_CIRC ((uint32_t)0x00000020U) /!< Circular mode /
<>	144:ef7eb2e8f9f7	1290	#define DMA_CCR_PINC ((uint32_t)0x00000040U) /!< Peripheral increment mode /
<>	144:ef7eb2e8f9f7	1291	#define DMA_CCR_MINC ((uint32_t)0x00000080U) /!< Memory increment mode /
<>	144:ef7eb2e8f9f7	1292
<>	144:ef7eb2e8f9f7	1293	#define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /!< PSIZE[1:0] bits (Peripheral size) /
<>	144:ef7eb2e8f9f7	1294	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	1295	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	1296
<>	144:ef7eb2e8f9f7	1297	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /!< MSIZE[1:0] bits (Memory size) /
<>	144:ef7eb2e8f9f7	1298	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	1299	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	1300
<>	144:ef7eb2e8f9f7	1301	#define DMA_CCR_PL ((uint32_t)0x00003000U) /!< PL[1:0] bits(Channel Priority level)/
<>	144:ef7eb2e8f9f7	1302	#define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	1303	#define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	1304
<>	144:ef7eb2e8f9f7	1305	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /!< Memory to memory mode /
<>	144:ef7eb2e8f9f7	1306
<>	144:ef7eb2e8f9f7	1307	/**************** Bit definition for DMA_CNDTR register *****************/
<>	144:ef7eb2e8f9f7	1308	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /!< Number of data to Transfer /
<>	144:ef7eb2e8f9f7	1309
<>	144:ef7eb2e8f9f7	1310	/**************** Bit definition for DMA_CPAR register ******************/
<>	144:ef7eb2e8f9f7	1311	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /!< Peripheral Address /
<>	144:ef7eb2e8f9f7	1312
<>	144:ef7eb2e8f9f7	1313	/**************** Bit definition for DMA_CMAR register ******************/
<>	144:ef7eb2e8f9f7	1314	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /!< Memory Address /
<>	144:ef7eb2e8f9f7	1315
<>	144:ef7eb2e8f9f7	1316
<>	144:ef7eb2e8f9f7	1317	/***************** Bit definition for DMA_CSELR register *****************/
<>	144:ef7eb2e8f9f7	1318	#define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /!< Channel 1 Selection /
<>	144:ef7eb2e8f9f7	1319	#define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /!< Channel 2 Selection /
<>	144:ef7eb2e8f9f7	1320	#define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /!< Channel 3 Selection /
<>	144:ef7eb2e8f9f7	1321	#define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /!< Channel 4 Selection /
<>	144:ef7eb2e8f9f7	1322	#define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /!< Channel 5 Selection /
<>	144:ef7eb2e8f9f7	1323	#define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /!< Channel 6 Selection /
<>	144:ef7eb2e8f9f7	1324	#define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /!< Channel 7 Selection /
<>	144:ef7eb2e8f9f7	1325
<>	144:ef7eb2e8f9f7	1326
<>	144:ef7eb2e8f9f7	1327	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1328	/* */
<>	144:ef7eb2e8f9f7	1329	/* External Interrupt/Event Controller (EXTI) */
<>	144:ef7eb2e8f9f7	1330	/* */
<>	144:ef7eb2e8f9f7	1331	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1332
<>	144:ef7eb2e8f9f7	1333	/***************** Bit definition for EXTI_IMR register *****************/
<>	144:ef7eb2e8f9f7	1334	#define EXTI_IMR_IM0 ((uint32_t)0x00000001U) /!< Interrupt Mask on line 0 /
<>	144:ef7eb2e8f9f7	1335	#define EXTI_IMR_IM1 ((uint32_t)0x00000002U) /!< Interrupt Mask on line 1 /
<>	144:ef7eb2e8f9f7	1336	#define EXTI_IMR_IM2 ((uint32_t)0x00000004U) /!< Interrupt Mask on line 2 /
<>	144:ef7eb2e8f9f7	1337	#define EXTI_IMR_IM3 ((uint32_t)0x00000008U) /!< Interrupt Mask on line 3 /
<>	144:ef7eb2e8f9f7	1338	#define EXTI_IMR_IM4 ((uint32_t)0x00000010U) /!< Interrupt Mask on line 4 /
<>	144:ef7eb2e8f9f7	1339	#define EXTI_IMR_IM5 ((uint32_t)0x00000020U) /!< Interrupt Mask on line 5 /
<>	144:ef7eb2e8f9f7	1340	#define EXTI_IMR_IM6 ((uint32_t)0x00000040U) /!< Interrupt Mask on line 6 /
<>	144:ef7eb2e8f9f7	1341	#define EXTI_IMR_IM7 ((uint32_t)0x00000080U) /!< Interrupt Mask on line 7 /
<>	144:ef7eb2e8f9f7	1342	#define EXTI_IMR_IM8 ((uint32_t)0x00000100U) /!< Interrupt Mask on line 8 /
<>	144:ef7eb2e8f9f7	1343	#define EXTI_IMR_IM9 ((uint32_t)0x00000200U) /!< Interrupt Mask on line 9 /
<>	144:ef7eb2e8f9f7	1344	#define EXTI_IMR_IM10 ((uint32_t)0x00000400U) /!< Interrupt Mask on line 10 /
<>	144:ef7eb2e8f9f7	1345	#define EXTI_IMR_IM11 ((uint32_t)0x00000800U) /!< Interrupt Mask on line 11 /
<>	144:ef7eb2e8f9f7	1346	#define EXTI_IMR_IM12 ((uint32_t)0x00001000U) /!< Interrupt Mask on line 12 /
<>	144:ef7eb2e8f9f7	1347	#define EXTI_IMR_IM13 ((uint32_t)0x00002000U) /!< Interrupt Mask on line 13 /
<>	144:ef7eb2e8f9f7	1348	#define EXTI_IMR_IM14 ((uint32_t)0x00004000U) /!< Interrupt Mask on line 14 /
<>	144:ef7eb2e8f9f7	1349	#define EXTI_IMR_IM15 ((uint32_t)0x00008000U) /!< Interrupt Mask on line 15 /
<>	144:ef7eb2e8f9f7	1350	#define EXTI_IMR_IM16 ((uint32_t)0x00010000U) /!< Interrupt Mask on line 16 /
<>	144:ef7eb2e8f9f7	1351	#define EXTI_IMR_IM17 ((uint32_t)0x00020000U) /!< Interrupt Mask on line 17 /
<>	144:ef7eb2e8f9f7	1352	#define EXTI_IMR_IM18 ((uint32_t)0x00040000U) /!< Interrupt Mask on line 18 /
<>	144:ef7eb2e8f9f7	1353	#define EXTI_IMR_IM19 ((uint32_t)0x00080000U) /!< Interrupt Mask on line 19 /
<>	144:ef7eb2e8f9f7	1354	#define EXTI_IMR_IM20 ((uint32_t)0x00100000U) /!< Interrupt Mask on line 20 /
<>	144:ef7eb2e8f9f7	1355	#define EXTI_IMR_IM21 ((uint32_t)0x00200000U) /!< Interrupt Mask on line 21 /
<>	144:ef7eb2e8f9f7	1356	#define EXTI_IMR_IM22 ((uint32_t)0x00400000U) /!< Interrupt Mask on line 22 /
<>	144:ef7eb2e8f9f7	1357	#define EXTI_IMR_IM23 ((uint32_t)0x00800000U) /!< Interrupt Mask on line 23 /
<>	144:ef7eb2e8f9f7	1358	#define EXTI_IMR_IM24 ((uint32_t)0x01000000U) /!< Interrupt Mask on line 24 /
<>	144:ef7eb2e8f9f7	1359	#define EXTI_IMR_IM25 ((uint32_t)0x02000000U) /!< Interrupt Mask on line 25 /
<>	144:ef7eb2e8f9f7	1360	#define EXTI_IMR_IM26 ((uint32_t)0x04000000U) /!< Interrupt Mask on line 26 /
<>	144:ef7eb2e8f9f7	1361	#define EXTI_IMR_IM28 ((uint32_t)0x10000000U) /!< Interrupt Mask on line 28 /
<>	144:ef7eb2e8f9f7	1362	#define EXTI_IMR_IM29 ((uint32_t)0x20000000U) /!< Interrupt Mask on line 29 /
<>	144:ef7eb2e8f9f7	1363
<>	144:ef7eb2e8f9f7	1364	/**************** Bit definition for EXTI_EMR register ******************/
<>	144:ef7eb2e8f9f7	1365	#define EXTI_EMR_EM0 ((uint32_t)0x00000001U) /!< Event Mask on line 0 /
<>	144:ef7eb2e8f9f7	1366	#define EXTI_EMR_EM1 ((uint32_t)0x00000002U) /!< Event Mask on line 1 /
<>	144:ef7eb2e8f9f7	1367	#define EXTI_EMR_EM2 ((uint32_t)0x00000004U) /!< Event Mask on line 2 /
<>	144:ef7eb2e8f9f7	1368	#define EXTI_EMR_EM3 ((uint32_t)0x00000008U) /!< Event Mask on line 3 /
<>	144:ef7eb2e8f9f7	1369	#define EXTI_EMR_EM4 ((uint32_t)0x00000010U) /!< Event Mask on line 4 /
<>	144:ef7eb2e8f9f7	1370	#define EXTI_EMR_EM5 ((uint32_t)0x00000020U) /!< Event Mask on line 5 /
<>	144:ef7eb2e8f9f7	1371	#define EXTI_EMR_EM6 ((uint32_t)0x00000040U) /!< Event Mask on line 6 /
<>	144:ef7eb2e8f9f7	1372	#define EXTI_EMR_EM7 ((uint32_t)0x00000080U) /!< Event Mask on line 7 /
<>	144:ef7eb2e8f9f7	1373	#define EXTI_EMR_EM8 ((uint32_t)0x00000100U) /!< Event Mask on line 8 /
<>	144:ef7eb2e8f9f7	1374	#define EXTI_EMR_EM9 ((uint32_t)0x00000200U) /!< Event Mask on line 9 /
<>	144:ef7eb2e8f9f7	1375	#define EXTI_EMR_EM10 ((uint32_t)0x00000400U) /!< Event Mask on line 10 /
<>	144:ef7eb2e8f9f7	1376	#define EXTI_EMR_EM11 ((uint32_t)0x00000800U) /!< Event Mask on line 11 /
<>	144:ef7eb2e8f9f7	1377	#define EXTI_EMR_EM12 ((uint32_t)0x00001000U) /!< Event Mask on line 12 /
<>	144:ef7eb2e8f9f7	1378	#define EXTI_EMR_EM13 ((uint32_t)0x00002000U) /!< Event Mask on line 13 /
<>	144:ef7eb2e8f9f7	1379	#define EXTI_EMR_EM14 ((uint32_t)0x00004000U) /!< Event Mask on line 14 /
<>	144:ef7eb2e8f9f7	1380	#define EXTI_EMR_EM15 ((uint32_t)0x00008000U) /!< Event Mask on line 15 /
<>	144:ef7eb2e8f9f7	1381	#define EXTI_EMR_EM16 ((uint32_t)0x00010000U) /!< Event Mask on line 16 /
<>	144:ef7eb2e8f9f7	1382	#define EXTI_EMR_EM17 ((uint32_t)0x00020000U) /!< Event Mask on line 17 /
<>	144:ef7eb2e8f9f7	1383	#define EXTI_EMR_EM18 ((uint32_t)0x00040000U) /!< Event Mask on line 18 /
<>	144:ef7eb2e8f9f7	1384	#define EXTI_EMR_EM19 ((uint32_t)0x00080000U) /!< Event Mask on line 19 /
<>	144:ef7eb2e8f9f7	1385	#define EXTI_EMR_EM20 ((uint32_t)0x00100000U) /!< Event Mask on line 20 /
<>	144:ef7eb2e8f9f7	1386	#define EXTI_EMR_EM21 ((uint32_t)0x00200000U) /!< Event Mask on line 21 /
<>	144:ef7eb2e8f9f7	1387	#define EXTI_EMR_EM22 ((uint32_t)0x00400000U) /!< Event Mask on line 22 /
<>	144:ef7eb2e8f9f7	1388	#define EXTI_EMR_EM23 ((uint32_t)0x00800000U) /!< Event Mask on line 23 /
<>	144:ef7eb2e8f9f7	1389	#define EXTI_EMR_EM24 ((uint32_t)0x01000000U) /!< Event Mask on line 24 /
<>	144:ef7eb2e8f9f7	1390	#define EXTI_EMR_EM25 ((uint32_t)0x02000000U) /!< Event Mask on line 25 /
<>	144:ef7eb2e8f9f7	1391	#define EXTI_EMR_EM26 ((uint32_t)0x04000000U) /!< Event Mask on line 26 /
<>	144:ef7eb2e8f9f7	1392	#define EXTI_EMR_EM28 ((uint32_t)0x10000000U) /!< Event Mask on line 28 /
<>	144:ef7eb2e8f9f7	1393	#define EXTI_EMR_EM29 ((uint32_t)0x20000000U) /!< Event Mask on line 29 /
<>	144:ef7eb2e8f9f7	1394
<>	144:ef7eb2e8f9f7	1395	/***************** Bit definition for EXTI_RTSR register ****************/
<>	144:ef7eb2e8f9f7	1396	#define EXTI_RTSR_RT0 ((uint32_t)0x00000001U) /!< Rising trigger event configuration bit of line 0 /
<>	144:ef7eb2e8f9f7	1397	#define EXTI_RTSR_RT1 ((uint32_t)0x00000002U) /!< Rising trigger event configuration bit of line 1 /
<>	144:ef7eb2e8f9f7	1398	#define EXTI_RTSR_RT2 ((uint32_t)0x00000004U) /!< Rising trigger event configuration bit of line 2 /
<>	144:ef7eb2e8f9f7	1399	#define EXTI_RTSR_RT3 ((uint32_t)0x00000008U) /!< Rising trigger event configuration bit of line 3 /
<>	144:ef7eb2e8f9f7	1400	#define EXTI_RTSR_RT4 ((uint32_t)0x00000010U) /!< Rising trigger event configuration bit of line 4 /
<>	144:ef7eb2e8f9f7	1401	#define EXTI_RTSR_RT5 ((uint32_t)0x00000020U) /!< Rising trigger event configuration bit of line 5 /
<>	144:ef7eb2e8f9f7	1402	#define EXTI_RTSR_RT6 ((uint32_t)0x00000040U) /!< Rising trigger event configuration bit of line 6 /
<>	144:ef7eb2e8f9f7	1403	#define EXTI_RTSR_RT7 ((uint32_t)0x00000080U) /!< Rising trigger event configuration bit of line 7 /
<>	144:ef7eb2e8f9f7	1404	#define EXTI_RTSR_RT8 ((uint32_t)0x00000100U) /!< Rising trigger event configuration bit of line 8 /
<>	144:ef7eb2e8f9f7	1405	#define EXTI_RTSR_RT9 ((uint32_t)0x00000200U) /!< Rising trigger event configuration bit of line 9 /
<>	144:ef7eb2e8f9f7	1406	#define EXTI_RTSR_RT10 ((uint32_t)0x00000400U) /!< Rising trigger event configuration bit of line 10 /
<>	144:ef7eb2e8f9f7	1407	#define EXTI_RTSR_RT11 ((uint32_t)0x00000800U) /!< Rising trigger event configuration bit of line 11 /
<>	144:ef7eb2e8f9f7	1408	#define EXTI_RTSR_RT12 ((uint32_t)0x00001000U) /!< Rising trigger event configuration bit of line 12 /
<>	144:ef7eb2e8f9f7	1409	#define EXTI_RTSR_RT13 ((uint32_t)0x00002000U) /!< Rising trigger event configuration bit of line 13 /
<>	144:ef7eb2e8f9f7	1410	#define EXTI_RTSR_RT14 ((uint32_t)0x00004000U) /!< Rising trigger event configuration bit of line 14 /
<>	144:ef7eb2e8f9f7	1411	#define EXTI_RTSR_RT15 ((uint32_t)0x00008000U) /!< Rising trigger event configuration bit of line 15 /
<>	144:ef7eb2e8f9f7	1412	#define EXTI_RTSR_RT16 ((uint32_t)0x00010000U) /!< Rising trigger event configuration bit of line 16 /
<>	144:ef7eb2e8f9f7	1413	#define EXTI_RTSR_RT17 ((uint32_t)0x00020000U) /!< Rising trigger event configuration bit of line 17 /
<>	144:ef7eb2e8f9f7	1414	#define EXTI_RTSR_RT19 ((uint32_t)0x00080000U) /!< Rising trigger event configuration bit of line 19 /
<>	144:ef7eb2e8f9f7	1415	#define EXTI_RTSR_RT20 ((uint32_t)0x00100000U) /!< Rising trigger event configuration bit of line 20 /
<>	144:ef7eb2e8f9f7	1416	#define EXTI_RTSR_RT21 ((uint32_t)0x00200000U) /!< Rising trigger event configuration bit of line 21 /
<>	144:ef7eb2e8f9f7	1417	#define EXTI_RTSR_RT22 ((uint32_t)0x00400000U) /!< Rising trigger event configuration bit of line 22 /
<>	144:ef7eb2e8f9f7	1418
<>	144:ef7eb2e8f9f7	1419	/* Legacy defines */
<>	144:ef7eb2e8f9f7	1420	#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
<>	144:ef7eb2e8f9f7	1421	#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
<>	144:ef7eb2e8f9f7	1422	#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
<>	144:ef7eb2e8f9f7	1423	#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
<>	144:ef7eb2e8f9f7	1424	#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
<>	144:ef7eb2e8f9f7	1425	#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
<>	144:ef7eb2e8f9f7	1426	#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
<>	144:ef7eb2e8f9f7	1427	#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
<>	144:ef7eb2e8f9f7	1428	#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
<>	144:ef7eb2e8f9f7	1429	#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
<>	144:ef7eb2e8f9f7	1430	#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
<>	144:ef7eb2e8f9f7	1431	#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
<>	144:ef7eb2e8f9f7	1432	#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
<>	144:ef7eb2e8f9f7	1433	#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
<>	144:ef7eb2e8f9f7	1434	#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
<>	144:ef7eb2e8f9f7	1435	#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
<>	144:ef7eb2e8f9f7	1436	#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
<>	144:ef7eb2e8f9f7	1437	#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
<>	144:ef7eb2e8f9f7	1438	#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
<>	144:ef7eb2e8f9f7	1439	#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
<>	144:ef7eb2e8f9f7	1440	#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
<>	144:ef7eb2e8f9f7	1441	#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
<>	144:ef7eb2e8f9f7	1442
<>	144:ef7eb2e8f9f7	1443	/***************** Bit definition for EXTI_FTSR register *****************/
<>	144:ef7eb2e8f9f7	1444	#define EXTI_FTSR_FT0 ((uint32_t)0x00000001U) /!< Falling trigger event configuration bit of line 0 /
<>	144:ef7eb2e8f9f7	1445	#define EXTI_FTSR_FT1 ((uint32_t)0x00000002U) /!< Falling trigger event configuration bit of line 1 /
<>	144:ef7eb2e8f9f7	1446	#define EXTI_FTSR_FT2 ((uint32_t)0x00000004U) /!< Falling trigger event configuration bit of line 2 /
<>	144:ef7eb2e8f9f7	1447	#define EXTI_FTSR_FT3 ((uint32_t)0x00000008U) /!< Falling trigger event configuration bit of line 3 /
<>	144:ef7eb2e8f9f7	1448	#define EXTI_FTSR_FT4 ((uint32_t)0x00000010U) /!< Falling trigger event configuration bit of line 4 /
<>	144:ef7eb2e8f9f7	1449	#define EXTI_FTSR_FT5 ((uint32_t)0x00000020U) /!< Falling trigger event configuration bit of line 5 /
<>	144:ef7eb2e8f9f7	1450	#define EXTI_FTSR_FT6 ((uint32_t)0x00000040U) /!< Falling trigger event configuration bit of line 6 /
<>	144:ef7eb2e8f9f7	1451	#define EXTI_FTSR_FT7 ((uint32_t)0x00000080U) /!< Falling trigger event configuration bit of line 7 /
<>	144:ef7eb2e8f9f7	1452	#define EXTI_FTSR_FT8 ((uint32_t)0x00000100U) /!< Falling trigger event configuration bit of line 8 /
<>	144:ef7eb2e8f9f7	1453	#define EXTI_FTSR_FT9 ((uint32_t)0x00000200U) /!< Falling trigger event configuration bit of line 9 /
<>	144:ef7eb2e8f9f7	1454	#define EXTI_FTSR_FT10 ((uint32_t)0x00000400U) /!< Falling trigger event configuration bit of line 10 /
<>	144:ef7eb2e8f9f7	1455	#define EXTI_FTSR_FT11 ((uint32_t)0x00000800U) /!< Falling trigger event configuration bit of line 11 /
<>	144:ef7eb2e8f9f7	1456	#define EXTI_FTSR_FT12 ((uint32_t)0x00001000U) /!< Falling trigger event configuration bit of line 12 /
<>	144:ef7eb2e8f9f7	1457	#define EXTI_FTSR_FT13 ((uint32_t)0x00002000U) /!< Falling trigger event configuration bit of line 13 /
<>	144:ef7eb2e8f9f7	1458	#define EXTI_FTSR_FT14 ((uint32_t)0x00004000U) /!< Falling trigger event configuration bit of line 14 /
<>	144:ef7eb2e8f9f7	1459	#define EXTI_FTSR_FT15 ((uint32_t)0x00008000U) /!< Falling trigger event configuration bit of line 15 /
<>	144:ef7eb2e8f9f7	1460	#define EXTI_FTSR_FT16 ((uint32_t)0x00010000U) /!< Falling trigger event configuration bit of line 16 /
<>	144:ef7eb2e8f9f7	1461	#define EXTI_FTSR_FT17 ((uint32_t)0x00020000U) /!< Falling trigger event configuration bit of line 17 /
<>	144:ef7eb2e8f9f7	1462	#define EXTI_FTSR_FT19 ((uint32_t)0x00080000U) /!< Falling trigger event configuration bit of line 19 /
<>	144:ef7eb2e8f9f7	1463	#define EXTI_FTSR_FT20 ((uint32_t)0x00100000U) /!< Falling trigger event configuration bit of line 20 /
<>	144:ef7eb2e8f9f7	1464	#define EXTI_FTSR_FT21 ((uint32_t)0x00200000U) /!< Falling trigger event configuration bit of line 21 /
<>	144:ef7eb2e8f9f7	1465	#define EXTI_FTSR_FT22 ((uint32_t)0x00400000U) /!< Falling trigger event configuration bit of line 22 /
<>	144:ef7eb2e8f9f7	1466
<>	144:ef7eb2e8f9f7	1467	/* Legacy defines */
<>	144:ef7eb2e8f9f7	1468	#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
<>	144:ef7eb2e8f9f7	1469	#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
<>	144:ef7eb2e8f9f7	1470	#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
<>	144:ef7eb2e8f9f7	1471	#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
<>	144:ef7eb2e8f9f7	1472	#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
<>	144:ef7eb2e8f9f7	1473	#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
<>	144:ef7eb2e8f9f7	1474	#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
<>	144:ef7eb2e8f9f7	1475	#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
<>	144:ef7eb2e8f9f7	1476	#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
<>	144:ef7eb2e8f9f7	1477	#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
<>	144:ef7eb2e8f9f7	1478	#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
<>	144:ef7eb2e8f9f7	1479	#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
<>	144:ef7eb2e8f9f7	1480	#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
<>	144:ef7eb2e8f9f7	1481	#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
<>	144:ef7eb2e8f9f7	1482	#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
<>	144:ef7eb2e8f9f7	1483	#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
<>	144:ef7eb2e8f9f7	1484	#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
<>	144:ef7eb2e8f9f7	1485	#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
<>	144:ef7eb2e8f9f7	1486	#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
<>	144:ef7eb2e8f9f7	1487	#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
<>	144:ef7eb2e8f9f7	1488	#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
<>	144:ef7eb2e8f9f7	1489	#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
<>	144:ef7eb2e8f9f7	1490
<>	144:ef7eb2e8f9f7	1491	/***************** Bit definition for EXTI_SWIER register *****************/
<>	144:ef7eb2e8f9f7	1492	#define EXTI_SWIER_SWI0 ((uint32_t)0x00000001U) /!< Software Interrupt on line 0 /
<>	144:ef7eb2e8f9f7	1493	#define EXTI_SWIER_SWI1 ((uint32_t)0x00000002U) /!< Software Interrupt on line 1 /
<>	144:ef7eb2e8f9f7	1494	#define EXTI_SWIER_SWI2 ((uint32_t)0x00000004U) /!< Software Interrupt on line 2 /
<>	144:ef7eb2e8f9f7	1495	#define EXTI_SWIER_SWI3 ((uint32_t)0x00000008U) /!< Software Interrupt on line 3 /
<>	144:ef7eb2e8f9f7	1496	#define EXTI_SWIER_SWI4 ((uint32_t)0x00000010U) /!< Software Interrupt on line 4 /
<>	144:ef7eb2e8f9f7	1497	#define EXTI_SWIER_SWI5 ((uint32_t)0x00000020U) /!< Software Interrupt on line 5 /
<>	144:ef7eb2e8f9f7	1498	#define EXTI_SWIER_SWI6 ((uint32_t)0x00000040U) /!< Software Interrupt on line 6 /
<>	144:ef7eb2e8f9f7	1499	#define EXTI_SWIER_SWI7 ((uint32_t)0x00000080U) /!< Software Interrupt on line 7 /
<>	144:ef7eb2e8f9f7	1500	#define EXTI_SWIER_SWI8 ((uint32_t)0x00000100U) /!< Software Interrupt on line 8 /
<>	144:ef7eb2e8f9f7	1501	#define EXTI_SWIER_SWI9 ((uint32_t)0x00000200U) /!< Software Interrupt on line 9 /
<>	144:ef7eb2e8f9f7	1502	#define EXTI_SWIER_SWI10 ((uint32_t)0x00000400U) /!< Software Interrupt on line 10 /
<>	144:ef7eb2e8f9f7	1503	#define EXTI_SWIER_SWI11 ((uint32_t)0x00000800U) /!< Software Interrupt on line 11 /
<>	144:ef7eb2e8f9f7	1504	#define EXTI_SWIER_SWI12 ((uint32_t)0x00001000U) /!< Software Interrupt on line 12 /
<>	144:ef7eb2e8f9f7	1505	#define EXTI_SWIER_SWI13 ((uint32_t)0x00002000U) /!< Software Interrupt on line 13 /
<>	144:ef7eb2e8f9f7	1506	#define EXTI_SWIER_SWI14 ((uint32_t)0x00004000U) /!< Software Interrupt on line 14 /
<>	144:ef7eb2e8f9f7	1507	#define EXTI_SWIER_SWI15 ((uint32_t)0x00008000U) /!< Software Interrupt on line 15 /
<>	144:ef7eb2e8f9f7	1508	#define EXTI_SWIER_SWI16 ((uint32_t)0x00010000U) /!< Software Interrupt on line 16 /
<>	144:ef7eb2e8f9f7	1509	#define EXTI_SWIER_SWI17 ((uint32_t)0x00020000U) /!< Software Interrupt on line 17 /
<>	144:ef7eb2e8f9f7	1510	#define EXTI_SWIER_SWI19 ((uint32_t)0x00080000U) /!< Software Interrupt on line 19 /
<>	144:ef7eb2e8f9f7	1511	#define EXTI_SWIER_SWI20 ((uint32_t)0x00100000U) /!< Software Interrupt on line 20 /
<>	144:ef7eb2e8f9f7	1512	#define EXTI_SWIER_SWI21 ((uint32_t)0x00200000U) /!< Software Interrupt on line 21 /
<>	144:ef7eb2e8f9f7	1513	#define EXTI_SWIER_SWI22 ((uint32_t)0x00400000U) /!< Software Interrupt on line 22 /
<>	144:ef7eb2e8f9f7	1514
<>	144:ef7eb2e8f9f7	1515	/* Legacy defines */
<>	144:ef7eb2e8f9f7	1516	#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
<>	144:ef7eb2e8f9f7	1517	#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
<>	144:ef7eb2e8f9f7	1518	#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
<>	144:ef7eb2e8f9f7	1519	#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
<>	144:ef7eb2e8f9f7	1520	#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
<>	144:ef7eb2e8f9f7	1521	#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
<>	144:ef7eb2e8f9f7	1522	#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
<>	144:ef7eb2e8f9f7	1523	#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
<>	144:ef7eb2e8f9f7	1524	#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
<>	144:ef7eb2e8f9f7	1525	#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
<>	144:ef7eb2e8f9f7	1526	#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
<>	144:ef7eb2e8f9f7	1527	#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
<>	144:ef7eb2e8f9f7	1528	#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
<>	144:ef7eb2e8f9f7	1529	#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
<>	144:ef7eb2e8f9f7	1530	#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
<>	144:ef7eb2e8f9f7	1531	#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
<>	144:ef7eb2e8f9f7	1532	#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
<>	144:ef7eb2e8f9f7	1533	#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
<>	144:ef7eb2e8f9f7	1534	#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
<>	144:ef7eb2e8f9f7	1535	#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
<>	144:ef7eb2e8f9f7	1536	#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
<>	144:ef7eb2e8f9f7	1537	#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
<>	144:ef7eb2e8f9f7	1538
<>	144:ef7eb2e8f9f7	1539	/**************** Bit definition for EXTI_PR register *******************/
<>	144:ef7eb2e8f9f7	1540	#define EXTI_PR_PIF0 ((uint32_t)0x00000001U) /!< Pending bit 0 /
<>	144:ef7eb2e8f9f7	1541	#define EXTI_PR_PIF1 ((uint32_t)0x00000002U) /!< Pending bit 1 /
<>	144:ef7eb2e8f9f7	1542	#define EXTI_PR_PIF2 ((uint32_t)0x00000004U) /!< Pending bit 2 /
<>	144:ef7eb2e8f9f7	1543	#define EXTI_PR_PIF3 ((uint32_t)0x00000008U) /!< Pending bit 3 /
<>	144:ef7eb2e8f9f7	1544	#define EXTI_PR_PIF4 ((uint32_t)0x00000010U) /!< Pending bit 4 /
<>	144:ef7eb2e8f9f7	1545	#define EXTI_PR_PIF5 ((uint32_t)0x00000020U) /!< Pending bit 5 /
<>	144:ef7eb2e8f9f7	1546	#define EXTI_PR_PIF6 ((uint32_t)0x00000040U) /!< Pending bit 6 /
<>	144:ef7eb2e8f9f7	1547	#define EXTI_PR_PIF7 ((uint32_t)0x00000080U) /!< Pending bit 7 /
<>	144:ef7eb2e8f9f7	1548	#define EXTI_PR_PIF8 ((uint32_t)0x00000100U) /!< Pending bit 8 /
<>	144:ef7eb2e8f9f7	1549	#define EXTI_PR_PIF9 ((uint32_t)0x00000200U) /!< Pending bit 9 /
<>	144:ef7eb2e8f9f7	1550	#define EXTI_PR_PIF10 ((uint32_t)0x00000400U) /!< Pending bit 10 /
<>	144:ef7eb2e8f9f7	1551	#define EXTI_PR_PIF11 ((uint32_t)0x00000800U) /!< Pending bit 11 /
<>	144:ef7eb2e8f9f7	1552	#define EXTI_PR_PIF12 ((uint32_t)0x00001000U) /!< Pending bit 12 /
<>	144:ef7eb2e8f9f7	1553	#define EXTI_PR_PIF13 ((uint32_t)0x00002000U) /!< Pending bit 13 /
<>	144:ef7eb2e8f9f7	1554	#define EXTI_PR_PIF14 ((uint32_t)0x00004000U) /!< Pending bit 14 /
<>	144:ef7eb2e8f9f7	1555	#define EXTI_PR_PIF15 ((uint32_t)0x00008000U) /!< Pending bit 15 /
<>	144:ef7eb2e8f9f7	1556	#define EXTI_PR_PIF16 ((uint32_t)0x00010000U) /!< Pending bit 16 /
<>	144:ef7eb2e8f9f7	1557	#define EXTI_PR_PIF17 ((uint32_t)0x00020000U) /!< Pending bit 17 /
<>	144:ef7eb2e8f9f7	1558	#define EXTI_PR_PIF19 ((uint32_t)0x00080000U) /!< Pending bit 19 /
<>	144:ef7eb2e8f9f7	1559	#define EXTI_PR_PIF20 ((uint32_t)0x00100000U) /!< Pending bit 20 /
<>	144:ef7eb2e8f9f7	1560	#define EXTI_PR_PIF21 ((uint32_t)0x00200000U) /!< Pending bit 21 /
<>	144:ef7eb2e8f9f7	1561	#define EXTI_PR_PIF22 ((uint32_t)0x00400000U) /!< Pending bit 22 /
<>	144:ef7eb2e8f9f7	1562
<>	144:ef7eb2e8f9f7	1563	/* Legacy defines */
<>	144:ef7eb2e8f9f7	1564	#define EXTI_PR_PR0 EXTI_PR_PIF0
<>	144:ef7eb2e8f9f7	1565	#define EXTI_PR_PR1 EXTI_PR_PIF1
<>	144:ef7eb2e8f9f7	1566	#define EXTI_PR_PR2 EXTI_PR_PIF2
<>	144:ef7eb2e8f9f7	1567	#define EXTI_PR_PR3 EXTI_PR_PIF3
<>	144:ef7eb2e8f9f7	1568	#define EXTI_PR_PR4 EXTI_PR_PIF4
<>	144:ef7eb2e8f9f7	1569	#define EXTI_PR_PR5 EXTI_PR_PIF5
<>	144:ef7eb2e8f9f7	1570	#define EXTI_PR_PR6 EXTI_PR_PIF6
<>	144:ef7eb2e8f9f7	1571	#define EXTI_PR_PR7 EXTI_PR_PIF7
<>	144:ef7eb2e8f9f7	1572	#define EXTI_PR_PR8 EXTI_PR_PIF8
<>	144:ef7eb2e8f9f7	1573	#define EXTI_PR_PR9 EXTI_PR_PIF9
<>	144:ef7eb2e8f9f7	1574	#define EXTI_PR_PR10 EXTI_PR_PIF10
<>	144:ef7eb2e8f9f7	1575	#define EXTI_PR_PR11 EXTI_PR_PIF11
<>	144:ef7eb2e8f9f7	1576	#define EXTI_PR_PR12 EXTI_PR_PIF12
<>	144:ef7eb2e8f9f7	1577	#define EXTI_PR_PR13 EXTI_PR_PIF13
<>	144:ef7eb2e8f9f7	1578	#define EXTI_PR_PR14 EXTI_PR_PIF14
<>	144:ef7eb2e8f9f7	1579	#define EXTI_PR_PR15 EXTI_PR_PIF15
<>	144:ef7eb2e8f9f7	1580	#define EXTI_PR_PR16 EXTI_PR_PIF16
<>	144:ef7eb2e8f9f7	1581	#define EXTI_PR_PR17 EXTI_PR_PIF17
<>	144:ef7eb2e8f9f7	1582	#define EXTI_PR_PR19 EXTI_PR_PIF19
<>	144:ef7eb2e8f9f7	1583	#define EXTI_PR_PR20 EXTI_PR_PIF20
<>	144:ef7eb2e8f9f7	1584	#define EXTI_PR_PR21 EXTI_PR_PIF21
<>	144:ef7eb2e8f9f7	1585	#define EXTI_PR_PR22 EXTI_PR_PIF22
<>	144:ef7eb2e8f9f7	1586
<>	144:ef7eb2e8f9f7	1587	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1588	/* */
<>	144:ef7eb2e8f9f7	1589	/* FLASH and Option Bytes Registers */
<>	144:ef7eb2e8f9f7	1590	/* */
<>	144:ef7eb2e8f9f7	1591	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1592
<>	144:ef7eb2e8f9f7	1593	/***************** Bit definition for FLASH_ACR register ****************/
<>	144:ef7eb2e8f9f7	1594	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /!< LATENCY bit (Latency) /
<>	144:ef7eb2e8f9f7	1595	#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /!< Prefetch Buffer Enable /
<>	144:ef7eb2e8f9f7	1596	#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /!< Flash mode during sleep mode /
<>	144:ef7eb2e8f9f7	1597	#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /!< Flash mode during RUN mode /
<>	144:ef7eb2e8f9f7	1598	#define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020U) /!< Disable Buffer /
<>	144:ef7eb2e8f9f7	1599	#define FLASH_ACR_PRE_READ ((uint32_t)0x00000040U) /!< Pre-read data address /
<>	144:ef7eb2e8f9f7	1600
<>	144:ef7eb2e8f9f7	1601	/***************** Bit definition for FLASH_PECR register ****************/
<>	144:ef7eb2e8f9f7	1602	#define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /!< FLASH_PECR and Flash data Lock /
<>	144:ef7eb2e8f9f7	1603	#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /!< Program matrix Lock /
<>	144:ef7eb2e8f9f7	1604	#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /!< Option byte matrix Lock /
<>	144:ef7eb2e8f9f7	1605	#define FLASH_PECR_PROG ((uint32_t)0x00000008U) /!< Program matrix selection /
<>	144:ef7eb2e8f9f7	1606	#define FLASH_PECR_DATA ((uint32_t)0x00000010U) /!< Data matrix selection /
<>	144:ef7eb2e8f9f7	1607	#define FLASH_PECR_FIX ((uint32_t)0x00000100U) /!< Fixed Time Data write for Word/Half Word/Byte programming /
<>	144:ef7eb2e8f9f7	1608	#define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /!< Page erasing mode /
<>	144:ef7eb2e8f9f7	1609	#define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /!< Fast Page/Half Page programming mode /
<>	144:ef7eb2e8f9f7	1610	#define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000U) /!< Parallel Bank mode /
<>	144:ef7eb2e8f9f7	1611	#define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /!< End of programming interrupt /
<>	144:ef7eb2e8f9f7	1612	#define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /!< Error interrupt /
<>	144:ef7eb2e8f9f7	1613	#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /!< Launch the option byte loading /
<>	144:ef7eb2e8f9f7	1614	#define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000U) /!< Half array mode /
<>	144:ef7eb2e8f9f7	1615	#define FLASH_PECR_NZDISABLE ((uint32_t)0x00400000U) /!< Non-Zero check disable /
<>	144:ef7eb2e8f9f7	1616
<>	144:ef7eb2e8f9f7	1617	/**************** Bit definition for FLASH_PDKEYR register ****************/
<>	144:ef7eb2e8f9f7	1618	#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /!< FLASH_PEC and data matrix Key /
<>	144:ef7eb2e8f9f7	1619
<>	144:ef7eb2e8f9f7	1620	/**************** Bit definition for FLASH_PEKEYR register ****************/
<>	144:ef7eb2e8f9f7	1621	#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /!< FLASH_PEC and data matrix Key /
<>	144:ef7eb2e8f9f7	1622
<>	144:ef7eb2e8f9f7	1623	/**************** Bit definition for FLASH_PRGKEYR register ****************/
<>	144:ef7eb2e8f9f7	1624	#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /!< Program matrix Key /
<>	144:ef7eb2e8f9f7	1625
<>	144:ef7eb2e8f9f7	1626	/**************** Bit definition for FLASH_OPTKEYR register ****************/
<>	144:ef7eb2e8f9f7	1627	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /!< Option bytes matrix Key /
<>	144:ef7eb2e8f9f7	1628
<>	144:ef7eb2e8f9f7	1629	/**************** Bit definition for FLASH_SR register *****************/
<>	144:ef7eb2e8f9f7	1630	#define FLASH_SR_BSY ((uint32_t)0x00000001U) /!< Busy /
<>	144:ef7eb2e8f9f7	1631	#define FLASH_SR_EOP ((uint32_t)0x00000002U) /!< End Of Programming/
<>	144:ef7eb2e8f9f7	1632	#define FLASH_SR_HVOFF ((uint32_t)0x00000004U) /!< End of high voltage /
<>	144:ef7eb2e8f9f7	1633	#define FLASH_SR_READY ((uint32_t)0x00000008U) /!< Flash ready after low power mode /
<>	144:ef7eb2e8f9f7	1634
<>	144:ef7eb2e8f9f7	1635	#define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /!< Write protection error /
<>	144:ef7eb2e8f9f7	1636	#define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /!< Programming Alignment Error /
<>	144:ef7eb2e8f9f7	1637	#define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /!< Size error /
<>	144:ef7eb2e8f9f7	1638	#define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /!< Option Valid error /
<>	144:ef7eb2e8f9f7	1639	#define FLASH_SR_RDERR ((uint32_t)0x00002000U) /!< Read protected error /
<>	144:ef7eb2e8f9f7	1640	#define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000U) /!< Not Zero error /
<>	144:ef7eb2e8f9f7	1641	#define FLASH_SR_FWWERR ((uint32_t)0x00020000U) /!< Write/Errase operation aborted /
<>	144:ef7eb2e8f9f7	1642
<>	144:ef7eb2e8f9f7	1643	/* Legacy defines */
<>	144:ef7eb2e8f9f7	1644	#define FLASH_SR_FWWER FLASH_SR_FWWERR
<>	144:ef7eb2e8f9f7	1645	#define FLASH_SR_ENHV FLASH_SR_HVOFF
<>	144:ef7eb2e8f9f7	1646	#define FLASH_SR_ENDHV FLASH_SR_HVOFF
<>	144:ef7eb2e8f9f7	1647
<>	144:ef7eb2e8f9f7	1648	/**************** Bit definition for FLASH_OPTR register *****************/
<>	144:ef7eb2e8f9f7	1649	#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FFU) /!< Read Protection /
<>	144:ef7eb2e8f9f7	1650	#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100U) /!< Selection of protection mode of WPR bits /
<>	144:ef7eb2e8f9f7	1651	#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000U) /!< BOR_LEV[3:0] Brown Out Reset Threshold Level/
<>	144:ef7eb2e8f9f7	1652	#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000U) /!< IWDG_SW /
<>	144:ef7eb2e8f9f7	1653	#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000U) /!< nRST_STOP /
<>	144:ef7eb2e8f9f7	1654	#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000U) /!< nRST_STDBY /
<>	144:ef7eb2e8f9f7	1655	#define FLASH_OPTR_BFB2 ((uint32_t)0x00800000U) /!< BFB2 /
<>	144:ef7eb2e8f9f7	1656	#define FLASH_OPTR_USER ((uint32_t)0x00700000U) /!< User Option Bytes /
<>	144:ef7eb2e8f9f7	1657	#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000U) /!< BOOT1 /
<>	144:ef7eb2e8f9f7	1658
<>	144:ef7eb2e8f9f7	1659	/**************** Bit definition for FLASH_WRPR register ****************/
<>	144:ef7eb2e8f9f7	1660	#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /!< Write Protection bits /
<>	144:ef7eb2e8f9f7	1661
<>	144:ef7eb2e8f9f7	1662	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1663	/* */
<>	144:ef7eb2e8f9f7	1664	/* General Purpose IOs (GPIO) */
<>	144:ef7eb2e8f9f7	1665	/* */
<>	144:ef7eb2e8f9f7	1666	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1667	/***************** Bit definition for GPIO_MODER register ***************/
<>	144:ef7eb2e8f9f7	1668	#define GPIO_MODER_MODE0 ((uint32_t)0x00000003U)
<>	144:ef7eb2e8f9f7	1669	#define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	1670	#define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	1671	#define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU)
<>	144:ef7eb2e8f9f7	1672	#define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	1673	#define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	1674	#define GPIO_MODER_MODE2 ((uint32_t)0x00000030U)
<>	144:ef7eb2e8f9f7	1675	#define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U)
<>	144:ef7eb2e8f9f7	1676	#define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	1677	#define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U)
<>	144:ef7eb2e8f9f7	1678	#define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U)
<>	144:ef7eb2e8f9f7	1679	#define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U)
<>	144:ef7eb2e8f9f7	1680	#define GPIO_MODER_MODE4 ((uint32_t)0x00000300U)
<>	144:ef7eb2e8f9f7	1681	#define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	1682	#define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	1683	#define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U)
<>	144:ef7eb2e8f9f7	1684	#define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U)
<>	144:ef7eb2e8f9f7	1685	#define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U)
<>	144:ef7eb2e8f9f7	1686	#define GPIO_MODER_MODE6 ((uint32_t)0x00003000U)
<>	144:ef7eb2e8f9f7	1687	#define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U)
<>	144:ef7eb2e8f9f7	1688	#define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U)
<>	144:ef7eb2e8f9f7	1689	#define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U)
<>	144:ef7eb2e8f9f7	1690	#define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U)
<>	144:ef7eb2e8f9f7	1691	#define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U)
<>	144:ef7eb2e8f9f7	1692	#define GPIO_MODER_MODE8 ((uint32_t)0x00030000U)
<>	144:ef7eb2e8f9f7	1693	#define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U)
<>	144:ef7eb2e8f9f7	1694	#define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U)
<>	144:ef7eb2e8f9f7	1695	#define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U)
<>	144:ef7eb2e8f9f7	1696	#define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U)
<>	144:ef7eb2e8f9f7	1697	#define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U)
<>	144:ef7eb2e8f9f7	1698	#define GPIO_MODER_MODE10 ((uint32_t)0x00300000U)
<>	144:ef7eb2e8f9f7	1699	#define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U)
<>	144:ef7eb2e8f9f7	1700	#define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U)
<>	144:ef7eb2e8f9f7	1701	#define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U)
<>	144:ef7eb2e8f9f7	1702	#define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U)
<>	144:ef7eb2e8f9f7	1703	#define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U)
<>	144:ef7eb2e8f9f7	1704	#define GPIO_MODER_MODE12 ((uint32_t)0x03000000U)
<>	144:ef7eb2e8f9f7	1705	#define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U)
<>	144:ef7eb2e8f9f7	1706	#define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U)
<>	144:ef7eb2e8f9f7	1707	#define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U)
<>	144:ef7eb2e8f9f7	1708	#define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U)
<>	144:ef7eb2e8f9f7	1709	#define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U)
<>	144:ef7eb2e8f9f7	1710	#define GPIO_MODER_MODE14 ((uint32_t)0x30000000U)
<>	144:ef7eb2e8f9f7	1711	#define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U)
<>	144:ef7eb2e8f9f7	1712	#define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U)
<>	144:ef7eb2e8f9f7	1713	#define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U)
<>	144:ef7eb2e8f9f7	1714	#define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U)
<>	144:ef7eb2e8f9f7	1715	#define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U)
<>	144:ef7eb2e8f9f7	1716
<>	144:ef7eb2e8f9f7	1717	/**************** Bit definition for GPIO_OTYPER register ***************/
<>	144:ef7eb2e8f9f7	1718	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	1719	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	1720	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	1721	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	1722	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U)
<>	144:ef7eb2e8f9f7	1723	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	1724	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U)
<>	144:ef7eb2e8f9f7	1725	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U)
<>	144:ef7eb2e8f9f7	1726	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	1727	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	1728	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U)
<>	144:ef7eb2e8f9f7	1729	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U)
<>	144:ef7eb2e8f9f7	1730	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U)
<>	144:ef7eb2e8f9f7	1731	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U)
<>	144:ef7eb2e8f9f7	1732	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U)
<>	144:ef7eb2e8f9f7	1733	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U)
<>	144:ef7eb2e8f9f7	1734
<>	144:ef7eb2e8f9f7	1735	/************** Bit definition for GPIO_OSPEEDR register ****************/
<>	144:ef7eb2e8f9f7	1736	#define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003U)
<>	144:ef7eb2e8f9f7	1737	#define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	1738	#define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	1739	#define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000CU)
<>	144:ef7eb2e8f9f7	1740	#define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	1741	#define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	1742	#define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030U)
<>	144:ef7eb2e8f9f7	1743	#define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010U)
<>	144:ef7eb2e8f9f7	1744	#define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	1745	#define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0U)
<>	144:ef7eb2e8f9f7	1746	#define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040U)
<>	144:ef7eb2e8f9f7	1747	#define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080U)
<>	144:ef7eb2e8f9f7	1748	#define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300U)
<>	144:ef7eb2e8f9f7	1749	#define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	1750	#define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	1751	#define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00U)
<>	144:ef7eb2e8f9f7	1752	#define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400U)
<>	144:ef7eb2e8f9f7	1753	#define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800U)
<>	144:ef7eb2e8f9f7	1754	#define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000U)
<>	144:ef7eb2e8f9f7	1755	#define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000U)
<>	144:ef7eb2e8f9f7	1756	#define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000U)
<>	144:ef7eb2e8f9f7	1757	#define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000U)
<>	144:ef7eb2e8f9f7	1758	#define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000U)
<>	144:ef7eb2e8f9f7	1759	#define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000U)
<>	144:ef7eb2e8f9f7	1760	#define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000U)
<>	144:ef7eb2e8f9f7	1761	#define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000U)
<>	144:ef7eb2e8f9f7	1762	#define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000U)
<>	144:ef7eb2e8f9f7	1763	#define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000U)
<>	144:ef7eb2e8f9f7	1764	#define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000U)
<>	144:ef7eb2e8f9f7	1765	#define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000U)
<>	144:ef7eb2e8f9f7	1766	#define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000U)
<>	144:ef7eb2e8f9f7	1767	#define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000U)
<>	144:ef7eb2e8f9f7	1768	#define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000U)
<>	144:ef7eb2e8f9f7	1769	#define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000U)
<>	144:ef7eb2e8f9f7	1770	#define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000U)
<>	144:ef7eb2e8f9f7	1771	#define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000U)
<>	144:ef7eb2e8f9f7	1772	#define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000U)
<>	144:ef7eb2e8f9f7	1773	#define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000U)
<>	144:ef7eb2e8f9f7	1774	#define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000U)
<>	144:ef7eb2e8f9f7	1775	#define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000U)
<>	144:ef7eb2e8f9f7	1776	#define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000U)
<>	144:ef7eb2e8f9f7	1777	#define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000U)
<>	144:ef7eb2e8f9f7	1778	#define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000U)
<>	144:ef7eb2e8f9f7	1779	#define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000U)
<>	144:ef7eb2e8f9f7	1780	#define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000U)
<>	144:ef7eb2e8f9f7	1781	#define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000U)
<>	144:ef7eb2e8f9f7	1782	#define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000U)
<>	144:ef7eb2e8f9f7	1783	#define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000U)
<>	144:ef7eb2e8f9f7	1784
<>	144:ef7eb2e8f9f7	1785	/***************** Bit definition for GPIO_PUPDR register ****************/
<>	144:ef7eb2e8f9f7	1786	#define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U)
<>	144:ef7eb2e8f9f7	1787	#define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	1788	#define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	1789	#define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU)
<>	144:ef7eb2e8f9f7	1790	#define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	1791	#define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	1792	#define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U)
<>	144:ef7eb2e8f9f7	1793	#define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U)
<>	144:ef7eb2e8f9f7	1794	#define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	1795	#define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U)
<>	144:ef7eb2e8f9f7	1796	#define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U)
<>	144:ef7eb2e8f9f7	1797	#define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U)
<>	144:ef7eb2e8f9f7	1798	#define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U)
<>	144:ef7eb2e8f9f7	1799	#define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	1800	#define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	1801	#define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U)
<>	144:ef7eb2e8f9f7	1802	#define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U)
<>	144:ef7eb2e8f9f7	1803	#define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U)
<>	144:ef7eb2e8f9f7	1804	#define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U)
<>	144:ef7eb2e8f9f7	1805	#define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U)
<>	144:ef7eb2e8f9f7	1806	#define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U)
<>	144:ef7eb2e8f9f7	1807	#define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U)
<>	144:ef7eb2e8f9f7	1808	#define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U)
<>	144:ef7eb2e8f9f7	1809	#define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U)
<>	144:ef7eb2e8f9f7	1810	#define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U)
<>	144:ef7eb2e8f9f7	1811	#define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U)
<>	144:ef7eb2e8f9f7	1812	#define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U)
<>	144:ef7eb2e8f9f7	1813	#define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U)
<>	144:ef7eb2e8f9f7	1814	#define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U)
<>	144:ef7eb2e8f9f7	1815	#define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U)
<>	144:ef7eb2e8f9f7	1816	#define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U)
<>	144:ef7eb2e8f9f7	1817	#define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U)
<>	144:ef7eb2e8f9f7	1818	#define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U)
<>	144:ef7eb2e8f9f7	1819	#define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U)
<>	144:ef7eb2e8f9f7	1820	#define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U)
<>	144:ef7eb2e8f9f7	1821	#define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U)
<>	144:ef7eb2e8f9f7	1822	#define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U)
<>	144:ef7eb2e8f9f7	1823	#define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U)
<>	144:ef7eb2e8f9f7	1824	#define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U)
<>	144:ef7eb2e8f9f7	1825	#define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U)
<>	144:ef7eb2e8f9f7	1826	#define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U)
<>	144:ef7eb2e8f9f7	1827	#define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U)
<>	144:ef7eb2e8f9f7	1828	#define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U)
<>	144:ef7eb2e8f9f7	1829	#define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U)
<>	144:ef7eb2e8f9f7	1830	#define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U)
<>	144:ef7eb2e8f9f7	1831	#define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U)
<>	144:ef7eb2e8f9f7	1832	#define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U)
<>	144:ef7eb2e8f9f7	1833	#define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U)
<>	144:ef7eb2e8f9f7	1834
<>	144:ef7eb2e8f9f7	1835	/***************** Bit definition for GPIO_IDR register *****************/
<>	144:ef7eb2e8f9f7	1836	#define GPIO_IDR_ID0 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	1837	#define GPIO_IDR_ID1 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	1838	#define GPIO_IDR_ID2 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	1839	#define GPIO_IDR_ID3 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	1840	#define GPIO_IDR_ID4 ((uint32_t)0x00000010U)
<>	144:ef7eb2e8f9f7	1841	#define GPIO_IDR_ID5 ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	1842	#define GPIO_IDR_ID6 ((uint32_t)0x00000040U)
<>	144:ef7eb2e8f9f7	1843	#define GPIO_IDR_ID7 ((uint32_t)0x00000080U)
<>	144:ef7eb2e8f9f7	1844	#define GPIO_IDR_ID8 ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	1845	#define GPIO_IDR_ID9 ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	1846	#define GPIO_IDR_ID10 ((uint32_t)0x00000400U)
<>	144:ef7eb2e8f9f7	1847	#define GPIO_IDR_ID11 ((uint32_t)0x00000800U)
<>	144:ef7eb2e8f9f7	1848	#define GPIO_IDR_ID12 ((uint32_t)0x00001000U)
<>	144:ef7eb2e8f9f7	1849	#define GPIO_IDR_ID13 ((uint32_t)0x00002000U)
<>	144:ef7eb2e8f9f7	1850	#define GPIO_IDR_ID14 ((uint32_t)0x00004000U)
<>	144:ef7eb2e8f9f7	1851	#define GPIO_IDR_ID15 ((uint32_t)0x00008000U)
<>	144:ef7eb2e8f9f7	1852
<>	144:ef7eb2e8f9f7	1853	/**************** Bit definition for GPIO_ODR register ******************/
<>	144:ef7eb2e8f9f7	1854	#define GPIO_ODR_OD0 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	1855	#define GPIO_ODR_OD1 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	1856	#define GPIO_ODR_OD2 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	1857	#define GPIO_ODR_OD3 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	1858	#define GPIO_ODR_OD4 ((uint32_t)0x00000010U)
<>	144:ef7eb2e8f9f7	1859	#define GPIO_ODR_OD5 ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	1860	#define GPIO_ODR_OD6 ((uint32_t)0x00000040U)
<>	144:ef7eb2e8f9f7	1861	#define GPIO_ODR_OD7 ((uint32_t)0x00000080U)
<>	144:ef7eb2e8f9f7	1862	#define GPIO_ODR_OD8 ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	1863	#define GPIO_ODR_OD9 ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	1864	#define GPIO_ODR_OD10 ((uint32_t)0x00000400U)
<>	144:ef7eb2e8f9f7	1865	#define GPIO_ODR_OD11 ((uint32_t)0x00000800U)
<>	144:ef7eb2e8f9f7	1866	#define GPIO_ODR_OD12 ((uint32_t)0x00001000U)
<>	144:ef7eb2e8f9f7	1867	#define GPIO_ODR_OD13 ((uint32_t)0x00002000U)
<>	144:ef7eb2e8f9f7	1868	#define GPIO_ODR_OD14 ((uint32_t)0x00004000U)
<>	144:ef7eb2e8f9f7	1869	#define GPIO_ODR_OD15 ((uint32_t)0x00008000U)
<>	144:ef7eb2e8f9f7	1870
<>	144:ef7eb2e8f9f7	1871	/**************** Bit definition for GPIO_BSRR register ******************/
<>	144:ef7eb2e8f9f7	1872	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	1873	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	1874	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	1875	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	1876	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U)
<>	144:ef7eb2e8f9f7	1877	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	1878	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U)
<>	144:ef7eb2e8f9f7	1879	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U)
<>	144:ef7eb2e8f9f7	1880	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	1881	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	1882	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U)
<>	144:ef7eb2e8f9f7	1883	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U)
<>	144:ef7eb2e8f9f7	1884	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U)
<>	144:ef7eb2e8f9f7	1885	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U)
<>	144:ef7eb2e8f9f7	1886	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U)
<>	144:ef7eb2e8f9f7	1887	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U)
<>	144:ef7eb2e8f9f7	1888	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U)
<>	144:ef7eb2e8f9f7	1889	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U)
<>	144:ef7eb2e8f9f7	1890	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U)
<>	144:ef7eb2e8f9f7	1891	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U)
<>	144:ef7eb2e8f9f7	1892	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U)
<>	144:ef7eb2e8f9f7	1893	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U)
<>	144:ef7eb2e8f9f7	1894	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U)
<>	144:ef7eb2e8f9f7	1895	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U)
<>	144:ef7eb2e8f9f7	1896	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U)
<>	144:ef7eb2e8f9f7	1897	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U)
<>	144:ef7eb2e8f9f7	1898	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U)
<>	144:ef7eb2e8f9f7	1899	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U)
<>	144:ef7eb2e8f9f7	1900	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U)
<>	144:ef7eb2e8f9f7	1901	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U)
<>	144:ef7eb2e8f9f7	1902	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U)
<>	144:ef7eb2e8f9f7	1903	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U)
<>	144:ef7eb2e8f9f7	1904
<>	144:ef7eb2e8f9f7	1905	/**************** Bit definition for GPIO_LCKR register ******************/
<>	144:ef7eb2e8f9f7	1906	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	1907	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	1908	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	1909	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	1910	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U)
<>	144:ef7eb2e8f9f7	1911	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	1912	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U)
<>	144:ef7eb2e8f9f7	1913	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U)
<>	144:ef7eb2e8f9f7	1914	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	1915	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	1916	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U)
<>	144:ef7eb2e8f9f7	1917	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U)
<>	144:ef7eb2e8f9f7	1918	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U)
<>	144:ef7eb2e8f9f7	1919	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U)
<>	144:ef7eb2e8f9f7	1920	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U)
<>	144:ef7eb2e8f9f7	1921	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U)
<>	144:ef7eb2e8f9f7	1922	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000U)
<>	144:ef7eb2e8f9f7	1923
<>	144:ef7eb2e8f9f7	1924	/**************** Bit definition for GPIO_AFRL register ******************/
<>	144:ef7eb2e8f9f7	1925	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU)
<>	144:ef7eb2e8f9f7	1926	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U)
<>	144:ef7eb2e8f9f7	1927	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U)
<>	144:ef7eb2e8f9f7	1928	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U)
<>	144:ef7eb2e8f9f7	1929	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U)
<>	144:ef7eb2e8f9f7	1930	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U)
<>	144:ef7eb2e8f9f7	1931	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U)
<>	144:ef7eb2e8f9f7	1932	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U)
<>	144:ef7eb2e8f9f7	1933
<>	144:ef7eb2e8f9f7	1934	/**************** Bit definition for GPIO_AFRH register ******************/
<>	144:ef7eb2e8f9f7	1935	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU)
<>	144:ef7eb2e8f9f7	1936	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U)
<>	144:ef7eb2e8f9f7	1937	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U)
<>	144:ef7eb2e8f9f7	1938	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U)
<>	144:ef7eb2e8f9f7	1939	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U)
<>	144:ef7eb2e8f9f7	1940	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U)
<>	144:ef7eb2e8f9f7	1941	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U)
<>	144:ef7eb2e8f9f7	1942	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U)
<>	144:ef7eb2e8f9f7	1943
<>	144:ef7eb2e8f9f7	1944	/**************** Bit definition for GPIO_BRR register *******************/
<>	144:ef7eb2e8f9f7	1945	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	1946	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	1947	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	1948	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	1949	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010U)
<>	144:ef7eb2e8f9f7	1950	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	1951	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040U)
<>	144:ef7eb2e8f9f7	1952	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080U)
<>	144:ef7eb2e8f9f7	1953	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	1954	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	1955	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400U)
<>	144:ef7eb2e8f9f7	1956	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800U)
<>	144:ef7eb2e8f9f7	1957	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000U)
<>	144:ef7eb2e8f9f7	1958	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000U)
<>	144:ef7eb2e8f9f7	1959	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000U)
<>	144:ef7eb2e8f9f7	1960	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000U)
<>	144:ef7eb2e8f9f7	1961
<>	144:ef7eb2e8f9f7	1962	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1963	/* */
<>	144:ef7eb2e8f9f7	1964	/* Inter-integrated Circuit Interface (I2C) */
<>	144:ef7eb2e8f9f7	1965	/* */
<>	144:ef7eb2e8f9f7	1966	/******************************************************************************/
<>	144:ef7eb2e8f9f7	1967
<>	144:ef7eb2e8f9f7	1968	/***************** Bit definition for I2C_CR1 register *****************/
<>	144:ef7eb2e8f9f7	1969	#define I2C_CR1_PE ((uint32_t)0x00000001U) /!< Peripheral enable /
<>	144:ef7eb2e8f9f7	1970	#define I2C_CR1_TXIE ((uint32_t)0x00000002U) /!< TX interrupt enable /
<>	144:ef7eb2e8f9f7	1971	#define I2C_CR1_RXIE ((uint32_t)0x00000004U) /!< RX interrupt enable /
<>	144:ef7eb2e8f9f7	1972	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /!< Address match interrupt enable /
<>	144:ef7eb2e8f9f7	1973	#define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /!< NACK received interrupt enable /
<>	144:ef7eb2e8f9f7	1974	#define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /!< STOP detection interrupt enable /
<>	144:ef7eb2e8f9f7	1975	#define I2C_CR1_TCIE ((uint32_t)0x00000040U) /!< Transfer complete interrupt enable /
<>	144:ef7eb2e8f9f7	1976	#define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /!< Errors interrupt enable /
<>	144:ef7eb2e8f9f7	1977	#define I2C_CR1_DNF ((uint32_t)0x00000F00U) /!< Digital noise filter /
<>	144:ef7eb2e8f9f7	1978	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /!< Analog noise filter OFF /
<>	144:ef7eb2e8f9f7	1979	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /!< DMA transmission requests enable /
<>	144:ef7eb2e8f9f7	1980	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /!< DMA reception requests enable /
<>	144:ef7eb2e8f9f7	1981	#define I2C_CR1_SBC ((uint32_t)0x00010000U) /!< Slave byte control /
<>	144:ef7eb2e8f9f7	1982	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /!< Clock stretching disable /
<>	144:ef7eb2e8f9f7	1983	#define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /!< Wakeup from STOP enable /
<>	144:ef7eb2e8f9f7	1984	#define I2C_CR1_GCEN ((uint32_t)0x00080000U) /!< General call enable /
<>	144:ef7eb2e8f9f7	1985	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /!< SMBus host address enable /
<>	144:ef7eb2e8f9f7	1986	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /!< SMBus device default address enable /
<>	144:ef7eb2e8f9f7	1987	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /!< SMBus alert enable /
<>	144:ef7eb2e8f9f7	1988	#define I2C_CR1_PECEN ((uint32_t)0x00800000U) /!< PEC enable /
<>	144:ef7eb2e8f9f7	1989
<>	144:ef7eb2e8f9f7	1990	/**************** Bit definition for I2C_CR2 register ******************/
<>	144:ef7eb2e8f9f7	1991	#define I2C_CR2_SADD ((uint32_t)0x000003FFU) /!< Slave address (master mode) /
<>	144:ef7eb2e8f9f7	1992	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /!< Transfer direction (master mode) /
<>	144:ef7eb2e8f9f7	1993	#define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /!< 10-bit addressing mode (master mode) /
<>	144:ef7eb2e8f9f7	1994	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /!< 10-bit address header only read direction (master mode) /
<>	144:ef7eb2e8f9f7	1995	#define I2C_CR2_START ((uint32_t)0x00002000U) /!< START generation /
<>	144:ef7eb2e8f9f7	1996	#define I2C_CR2_STOP ((uint32_t)0x00004000U) /!< STOP generation (master mode) /
<>	144:ef7eb2e8f9f7	1997	#define I2C_CR2_NACK ((uint32_t)0x00008000U) /!< NACK generation (slave mode) /
<>	144:ef7eb2e8f9f7	1998	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /!< Number of bytes /
<>	144:ef7eb2e8f9f7	1999	#define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /!< NBYTES reload mode /
<>	144:ef7eb2e8f9f7	2000	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /!< Automatic end mode (master mode) /
<>	144:ef7eb2e8f9f7	2001	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /!< Packet error checking byte /
<>	144:ef7eb2e8f9f7	2002
<>	144:ef7eb2e8f9f7	2003	/***************** Bit definition for I2C_OAR1 register ****************/
<>	144:ef7eb2e8f9f7	2004	#define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /!< Interface own address 1 /
<>	144:ef7eb2e8f9f7	2005	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /!< Own address 1 10-bit mode /
<>	144:ef7eb2e8f9f7	2006	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /!< Own address 1 enable /
<>	144:ef7eb2e8f9f7	2007
<>	144:ef7eb2e8f9f7	2008	/***************** Bit definition for I2C_OAR2 register ****************/
<>	144:ef7eb2e8f9f7	2009	#define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /!< Interface own address 2 /
<>	144:ef7eb2e8f9f7	2010	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /!< Own address 2 masks /
<>	144:ef7eb2e8f9f7	2011	#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /!< No mask /
<>	144:ef7eb2e8f9f7	2012	#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /!< OA2[1] is masked, Only OA2[7:2] are compared /
<>	144:ef7eb2e8f9f7	2013	#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /!< OA2[2:1] is masked, Only OA2[7:3] are compared /
<>	144:ef7eb2e8f9f7	2014	#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /!< OA2[3:1] is masked, Only OA2[7:4] are compared /
<>	144:ef7eb2e8f9f7	2015	#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /!< OA2[4:1] is masked, Only OA2[7:5] are compared /
<>	144:ef7eb2e8f9f7	2016	#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /!< OA2[5:1] is masked, Only OA2[7:6] are compared /
<>	144:ef7eb2e8f9f7	2017	#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /!< OA2[6:1] is masked, Only OA2[7] are compared /
<>	144:ef7eb2e8f9f7	2018	#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /!< OA2[7:1] is masked, No comparison is done /
<>	144:ef7eb2e8f9f7	2019	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /!< Own address 2 enable /
<>	144:ef7eb2e8f9f7	2020
<>	144:ef7eb2e8f9f7	2021	/***************** Bit definition for I2C_TIMINGR register *****************/
<>	144:ef7eb2e8f9f7	2022	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /!< SCL low period (master mode) /
<>	144:ef7eb2e8f9f7	2023	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /!< SCL high period (master mode) /
<>	144:ef7eb2e8f9f7	2024	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /!< Data hold time /
<>	144:ef7eb2e8f9f7	2025	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /!< Data setup time /
<>	144:ef7eb2e8f9f7	2026	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /!< Timings prescaler /
<>	144:ef7eb2e8f9f7	2027
<>	144:ef7eb2e8f9f7	2028	/***************** Bit definition for I2C_TIMEOUTR register *****************/
<>	144:ef7eb2e8f9f7	2029	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /!< Bus timeout A /
<>	144:ef7eb2e8f9f7	2030	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /!< Idle clock timeout detection /
<>	144:ef7eb2e8f9f7	2031	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /!< Clock timeout enable /
<>	144:ef7eb2e8f9f7	2032	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /!< Bus timeout B/
<>	144:ef7eb2e8f9f7	2033	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /!< Extended clock timeout enable /
<>	144:ef7eb2e8f9f7	2034
<>	144:ef7eb2e8f9f7	2035	/**************** Bit definition for I2C_ISR register *******************/
<>	144:ef7eb2e8f9f7	2036	#define I2C_ISR_TXE ((uint32_t)0x00000001U) /!< Transmit data register empty /
<>	144:ef7eb2e8f9f7	2037	#define I2C_ISR_TXIS ((uint32_t)0x00000002U) /!< Transmit interrupt status /
<>	144:ef7eb2e8f9f7	2038	#define I2C_ISR_RXNE ((uint32_t)0x00000004U) /!< Receive data register not empty /
<>	144:ef7eb2e8f9f7	2039	#define I2C_ISR_ADDR ((uint32_t)0x00000008U) /!< Address matched (slave mode)/
<>	144:ef7eb2e8f9f7	2040	#define I2C_ISR_NACKF ((uint32_t)0x00000010U) /!< NACK received flag /
<>	144:ef7eb2e8f9f7	2041	#define I2C_ISR_STOPF ((uint32_t)0x00000020U) /!< STOP detection flag /
<>	144:ef7eb2e8f9f7	2042	#define I2C_ISR_TC ((uint32_t)0x00000040U) /!< Transfer complete (master mode) /
<>	144:ef7eb2e8f9f7	2043	#define I2C_ISR_TCR ((uint32_t)0x00000080U) /!< Transfer complete reload /
<>	144:ef7eb2e8f9f7	2044	#define I2C_ISR_BERR ((uint32_t)0x00000100U) /!< Bus error /
<>	144:ef7eb2e8f9f7	2045	#define I2C_ISR_ARLO ((uint32_t)0x00000200U) /!< Arbitration lost /
<>	144:ef7eb2e8f9f7	2046	#define I2C_ISR_OVR ((uint32_t)0x00000400U) /!< Overrun/Underrun /
<>	144:ef7eb2e8f9f7	2047	#define I2C_ISR_PECERR ((uint32_t)0x00000800U) /!< PEC error in reception /
<>	144:ef7eb2e8f9f7	2048	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /!< Timeout or Tlow detection flag /
<>	144:ef7eb2e8f9f7	2049	#define I2C_ISR_ALERT ((uint32_t)0x00002000U) /!< SMBus alert /
<>	144:ef7eb2e8f9f7	2050	#define I2C_ISR_BUSY ((uint32_t)0x00008000U) /!< Bus busy /
<>	144:ef7eb2e8f9f7	2051	#define I2C_ISR_DIR ((uint32_t)0x00010000U) /!< Transfer direction (slave mode) /
<>	144:ef7eb2e8f9f7	2052	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /!< Address match code (slave mode) /
<>	144:ef7eb2e8f9f7	2053
<>	144:ef7eb2e8f9f7	2054	/**************** Bit definition for I2C_ICR register *******************/
<>	144:ef7eb2e8f9f7	2055	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /!< Address matched clear flag /
<>	144:ef7eb2e8f9f7	2056	#define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /!< NACK clear flag /
<>	144:ef7eb2e8f9f7	2057	#define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /!< STOP detection clear flag /
<>	144:ef7eb2e8f9f7	2058	#define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /!< Bus error clear flag /
<>	144:ef7eb2e8f9f7	2059	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /!< Arbitration lost clear flag /
<>	144:ef7eb2e8f9f7	2060	#define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /!< Overrun/Underrun clear flag /
<>	144:ef7eb2e8f9f7	2061	#define I2C_ICR_PECCF ((uint32_t)0x00000800U) /!< PAC error clear flag /
<>	144:ef7eb2e8f9f7	2062	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /!< Timeout clear flag /
<>	144:ef7eb2e8f9f7	2063	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /!< Alert clear flag /
<>	144:ef7eb2e8f9f7	2064
<>	144:ef7eb2e8f9f7	2065	/**************** Bit definition for I2C_PECR register *******************/
<>	144:ef7eb2e8f9f7	2066	#define I2C_PECR_PEC ((uint32_t)0x000000FFU) /!< PEC register /
<>	144:ef7eb2e8f9f7	2067
<>	144:ef7eb2e8f9f7	2068	/**************** Bit definition for I2C_RXDR register *******************/
<>	144:ef7eb2e8f9f7	2069	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /!< 8-bit receive data /
<>	144:ef7eb2e8f9f7	2070
<>	144:ef7eb2e8f9f7	2071	/**************** Bit definition for I2C_TXDR register *******************/
<>	144:ef7eb2e8f9f7	2072	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /!< 8-bit transmit data /
<>	144:ef7eb2e8f9f7	2073
<>	144:ef7eb2e8f9f7	2074	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2075	/* */
<>	144:ef7eb2e8f9f7	2076	/* Independent WATCHDOG (IWDG) */
<>	144:ef7eb2e8f9f7	2077	/* */
<>	144:ef7eb2e8f9f7	2078	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2079	/***************** Bit definition for IWDG_KR register ******************/
<>	144:ef7eb2e8f9f7	2080	#define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /!< Key value (write only, read 0000h) /
<>	144:ef7eb2e8f9f7	2081
<>	144:ef7eb2e8f9f7	2082	/***************** Bit definition for IWDG_PR register ******************/
<>	144:ef7eb2e8f9f7	2083	#define IWDG_PR_PR ((uint32_t)0x00000007U) /!< PR[2:0] (Prescaler divider) /
<>	144:ef7eb2e8f9f7	2084	#define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2085	#define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2086	#define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	2087
<>	144:ef7eb2e8f9f7	2088	/***************** Bit definition for IWDG_RLR register *****************/
<>	144:ef7eb2e8f9f7	2089	#define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /!< Watchdog counter reload value /
<>	144:ef7eb2e8f9f7	2090
<>	144:ef7eb2e8f9f7	2091	/***************** Bit definition for IWDG_SR register ******************/
<>	144:ef7eb2e8f9f7	2092	#define IWDG_SR_PVU ((uint32_t)0x00000001U) /!< Watchdog prescaler value update /
<>	144:ef7eb2e8f9f7	2093	#define IWDG_SR_RVU ((uint32_t)0x00000002U) /!< Watchdog counter reload value update /
<>	144:ef7eb2e8f9f7	2094	#define IWDG_SR_WVU ((uint32_t)0x00000004U) /!< Watchdog counter window value update /
<>	144:ef7eb2e8f9f7	2095
<>	144:ef7eb2e8f9f7	2096	/***************** Bit definition for IWDG_KR register ******************/
<>	144:ef7eb2e8f9f7	2097	#define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /!< Watchdog counter window value /
<>	144:ef7eb2e8f9f7	2098
<>	144:ef7eb2e8f9f7	2099	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2100	/* */
<>	144:ef7eb2e8f9f7	2101	/* LCD Controller (LCD) */
<>	144:ef7eb2e8f9f7	2102	/* */
<>	144:ef7eb2e8f9f7	2103	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2104
<>	144:ef7eb2e8f9f7	2105	/***************** Bit definition for LCD_CR register *******************/
<>	144:ef7eb2e8f9f7	2106	#define LCD_CR_LCDEN ((uint32_t)0x00000001U) /!< LCD Enable Bit /
<>	144:ef7eb2e8f9f7	2107	#define LCD_CR_VSEL ((uint32_t)0x00000002U) /!< Voltage source selector Bit /
<>	144:ef7eb2e8f9f7	2108
<>	144:ef7eb2e8f9f7	2109	#define LCD_CR_DUTY ((uint32_t)0x0000001CU) /!< DUTY[2:0] bits (Duty selector) /
<>	144:ef7eb2e8f9f7	2110	#define LCD_CR_DUTY_0 ((uint32_t)0x00000004U) /!< Duty selector Bit 0 /
<>	144:ef7eb2e8f9f7	2111	#define LCD_CR_DUTY_1 ((uint32_t)0x00000008U) /!< Duty selector Bit 1 /
<>	144:ef7eb2e8f9f7	2112	#define LCD_CR_DUTY_2 ((uint32_t)0x00000010U) /!< Duty selector Bit 2 /
<>	144:ef7eb2e8f9f7	2113
<>	144:ef7eb2e8f9f7	2114	#define LCD_CR_BIAS ((uint32_t)0x00000060U) /!< BIAS[1:0] bits (Bias selector) /
<>	144:ef7eb2e8f9f7	2115	#define LCD_CR_BIAS_0 ((uint32_t)0x00000020U) /!< Bias selector Bit 0 /
<>	144:ef7eb2e8f9f7	2116	#define LCD_CR_BIAS_1 ((uint32_t)0x00000040U) /!< Bias selector Bit 1 /
<>	144:ef7eb2e8f9f7	2117
<>	144:ef7eb2e8f9f7	2118	#define LCD_CR_MUX_SEG ((uint32_t)0x00000080U) /!< Mux Segment Enable Bit /
<>	144:ef7eb2e8f9f7	2119
<>	144:ef7eb2e8f9f7	2120	/***************** Bit definition for LCD_FCR register ******************/
<>	144:ef7eb2e8f9f7	2121	#define LCD_FCR_HD ((uint32_t)0x00000001U) /!< High Drive Enable Bit /
<>	144:ef7eb2e8f9f7	2122	#define LCD_FCR_SOFIE ((uint32_t)0x00000002U) /!< Start of Frame Interrupt Enable Bit /
<>	144:ef7eb2e8f9f7	2123	#define LCD_FCR_UDDIE ((uint32_t)0x00000008U) /!< Update Display Done Interrupt Enable Bit /
<>	144:ef7eb2e8f9f7	2124
<>	144:ef7eb2e8f9f7	2125	#define LCD_FCR_PON ((uint32_t)0x00000070U) /!< PON[2:0] bits (Puls ON Duration) /
<>	144:ef7eb2e8f9f7	2126	#define LCD_FCR_PON_0 ((uint32_t)0x00000010U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2127	#define LCD_FCR_PON_1 ((uint32_t)0x00000020U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2128	#define LCD_FCR_PON_2 ((uint32_t)0x00000040U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	2129
<>	144:ef7eb2e8f9f7	2130	#define LCD_FCR_DEAD ((uint32_t)0x00000380U) /!< DEAD[2:0] bits (DEAD Time) /
<>	144:ef7eb2e8f9f7	2131	#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2132	#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2133	#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	2134
<>	144:ef7eb2e8f9f7	2135	#define LCD_FCR_CC ((uint32_t)0x00001C00U) /!< CC[2:0] bits (Contrast Control) /
<>	144:ef7eb2e8f9f7	2136	#define LCD_FCR_CC_0 ((uint32_t)0x00000400U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2137	#define LCD_FCR_CC_1 ((uint32_t)0x00000800U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2138	#define LCD_FCR_CC_2 ((uint32_t)0x00001000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	2139
<>	144:ef7eb2e8f9f7	2140	#define LCD_FCR_BLINKF ((uint32_t)0x0000E000U) /!< BLINKF[2:0] bits (Blink Frequency) /
<>	144:ef7eb2e8f9f7	2141	#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2142	#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2143	#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	2144
<>	144:ef7eb2e8f9f7	2145	#define LCD_FCR_BLINK ((uint32_t)0x00030000U) /!< BLINK[1:0] bits (Blink Enable) /
<>	144:ef7eb2e8f9f7	2146	#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2147	#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2148
<>	144:ef7eb2e8f9f7	2149	#define LCD_FCR_DIV ((uint32_t)0x003C0000U) /!< DIV[3:0] bits (Divider) /
<>	144:ef7eb2e8f9f7	2150	#define LCD_FCR_PS ((uint32_t)0x03C00000U) /!< PS[3:0] bits (Prescaler) /
<>	144:ef7eb2e8f9f7	2151
<>	144:ef7eb2e8f9f7	2152	/***************** Bit definition for LCD_SR register *******************/
<>	144:ef7eb2e8f9f7	2153	#define LCD_SR_ENS ((uint32_t)0x00000001U) /!< LCD Enabled Bit /
<>	144:ef7eb2e8f9f7	2154	#define LCD_SR_SOF ((uint32_t)0x00000002U) /!< Start Of Frame Flag Bit /
<>	144:ef7eb2e8f9f7	2155	#define LCD_SR_UDR ((uint32_t)0x00000004U) /!< Update Display Request Bit /
<>	144:ef7eb2e8f9f7	2156	#define LCD_SR_UDD ((uint32_t)0x00000008U) /!< Update Display Done Flag Bit /
<>	144:ef7eb2e8f9f7	2157	#define LCD_SR_RDY ((uint32_t)0x00000010U) /!< Ready Flag Bit /
<>	144:ef7eb2e8f9f7	2158	#define LCD_SR_FCRSR ((uint32_t)0x00000020U) /!< LCD FCR Register Synchronization Flag Bit /
<>	144:ef7eb2e8f9f7	2159
<>	144:ef7eb2e8f9f7	2160	/***************** Bit definition for LCD_CLR register ******************/
<>	144:ef7eb2e8f9f7	2161	#define LCD_CLR_SOFC ((uint32_t)0x00000002U) /!< Start Of Frame Flag Clear Bit /
<>	144:ef7eb2e8f9f7	2162	#define LCD_CLR_UDDC ((uint32_t)0x00000008U) /!< Update Display Done Flag Clear Bit /
<>	144:ef7eb2e8f9f7	2163
<>	144:ef7eb2e8f9f7	2164	/***************** Bit definition for LCD_RAM register ******************/
<>	144:ef7eb2e8f9f7	2165	#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFFU) /!< Segment Data Bits /
<>	144:ef7eb2e8f9f7	2166
<>	144:ef7eb2e8f9f7	2167	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2168	/* */
<>	144:ef7eb2e8f9f7	2169	/* Low Power Timer (LPTTIM) */
<>	144:ef7eb2e8f9f7	2170	/* */
<>	144:ef7eb2e8f9f7	2171	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2172	/**************** Bit definition for LPTIM_ISR register *****************/
<>	144:ef7eb2e8f9f7	2173	#define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /!< Compare match /
<>	144:ef7eb2e8f9f7	2174	#define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /!< Autoreload match /
<>	144:ef7eb2e8f9f7	2175	#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /!< External trigger edge event /
<>	144:ef7eb2e8f9f7	2176	#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /!< Compare register update OK /
<>	144:ef7eb2e8f9f7	2177	#define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /!< Autoreload register update OK /
<>	144:ef7eb2e8f9f7	2178	#define LPTIM_ISR_UP ((uint32_t)0x00000020U) /!< Counter direction change down to up /
<>	144:ef7eb2e8f9f7	2179	#define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /!< Counter direction change up to down /
<>	144:ef7eb2e8f9f7	2180
<>	144:ef7eb2e8f9f7	2181	/**************** Bit definition for LPTIM_ICR register *****************/
<>	144:ef7eb2e8f9f7	2182	#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /!< Compare match Clear Flag /
<>	144:ef7eb2e8f9f7	2183	#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /!< Autoreload match Clear Flag /
<>	144:ef7eb2e8f9f7	2184	#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /!< External trigger edge event Clear Flag /
<>	144:ef7eb2e8f9f7	2185	#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /!< Compare register update OK Clear Flag /
<>	144:ef7eb2e8f9f7	2186	#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /!< Autoreload register update OK Clear Flag /
<>	144:ef7eb2e8f9f7	2187	#define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /!< Counter direction change down to up Clear Flag /
<>	144:ef7eb2e8f9f7	2188	#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /!< Counter direction change up to down Clear Flag /
<>	144:ef7eb2e8f9f7	2189
<>	144:ef7eb2e8f9f7	2190	/**************** Bit definition for LPTIM_IER register ******************/
<>	144:ef7eb2e8f9f7	2191	#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /!< Compare match Interrupt Enable /
<>	144:ef7eb2e8f9f7	2192	#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /!< Autoreload match Interrupt Enable /
<>	144:ef7eb2e8f9f7	2193	#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /!< External trigger edge event Interrupt Enable /
<>	144:ef7eb2e8f9f7	2194	#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /!< Compare register update OK Interrupt Enable /
<>	144:ef7eb2e8f9f7	2195	#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /!< Autoreload register update OK Interrupt Enable /
<>	144:ef7eb2e8f9f7	2196	#define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /!< Counter direction change down to up Interrupt Enable /
<>	144:ef7eb2e8f9f7	2197	#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /!< Counter direction change up to down Interrupt Enable /
<>	144:ef7eb2e8f9f7	2198
<>	144:ef7eb2e8f9f7	2199	/**************** Bit definition for LPTIM_CFGR register *****************/
<>	144:ef7eb2e8f9f7	2200	#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /!< Clock selector /
<>	144:ef7eb2e8f9f7	2201
<>	144:ef7eb2e8f9f7	2202	#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /!< CKPOL[1:0] bits (Clock polarity) /
<>	144:ef7eb2e8f9f7	2203	#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2204	#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2205
<>	144:ef7eb2e8f9f7	2206	#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /!< CKFLT[1:0] bits (Configurable digital filter for external clock) /
<>	144:ef7eb2e8f9f7	2207	#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2208	#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2209
<>	144:ef7eb2e8f9f7	2210	#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /!< TRGFLT[1:0] bits (Configurable digital filter for trigger) /
<>	144:ef7eb2e8f9f7	2211	#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2212	#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2213
<>	144:ef7eb2e8f9f7	2214	#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /!< PRESC[2:0] bits (Clock prescaler) /
<>	144:ef7eb2e8f9f7	2215	#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2216	#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2217	#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	2218
<>	144:ef7eb2e8f9f7	2219	#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /!< TRIGSEL[2:0]] bits (Trigger selector) /
<>	144:ef7eb2e8f9f7	2220	#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2221	#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2222	#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	2223
<>	144:ef7eb2e8f9f7	2224	#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /!< TRIGEN[1:0] bits (Trigger enable and polarity) /
<>	144:ef7eb2e8f9f7	2225	#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2226	#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2227
<>	144:ef7eb2e8f9f7	2228	#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /!< Timout enable /
<>	144:ef7eb2e8f9f7	2229	#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /!< Waveform shape /
<>	144:ef7eb2e8f9f7	2230	#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /!< Waveform shape polarity /
<>	144:ef7eb2e8f9f7	2231	#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /!< Reg update mode /
<>	144:ef7eb2e8f9f7	2232	#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /!< Counter mode enable /
<>	144:ef7eb2e8f9f7	2233	#define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /!< Encoder mode enable /
<>	144:ef7eb2e8f9f7	2234
<>	144:ef7eb2e8f9f7	2235	/**************** Bit definition for LPTIM_CR register ******************/
<>	144:ef7eb2e8f9f7	2236	#define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /!< LPTIMer enable /
<>	144:ef7eb2e8f9f7	2237	#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /!< Timer start in single mode /
<>	144:ef7eb2e8f9f7	2238	#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /!< Timer start in continuous mode /
<>	144:ef7eb2e8f9f7	2239
<>	144:ef7eb2e8f9f7	2240	/**************** Bit definition for LPTIM_CMP register *****************/
<>	144:ef7eb2e8f9f7	2241	#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /!< Compare register /
<>	144:ef7eb2e8f9f7	2242
<>	144:ef7eb2e8f9f7	2243	/**************** Bit definition for LPTIM_ARR register *****************/
<>	144:ef7eb2e8f9f7	2244	#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /!< Auto reload register /
<>	144:ef7eb2e8f9f7	2245
<>	144:ef7eb2e8f9f7	2246	/**************** Bit definition for LPTIM_CNT register *****************/
<>	144:ef7eb2e8f9f7	2247	#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /!< Counter register /
<>	144:ef7eb2e8f9f7	2248
<>	144:ef7eb2e8f9f7	2249	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2250	/* */
<>	144:ef7eb2e8f9f7	2251	/* MIFARE Firewall */
<>	144:ef7eb2e8f9f7	2252	/* */
<>	144:ef7eb2e8f9f7	2253	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2254
<>	144:ef7eb2e8f9f7	2255	/******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register /
<>	144:ef7eb2e8f9f7	2256	#define FW_CSSA_ADD ((uint32_t)0x00FFFF00U) /!< Code Segment Start Address /
<>	144:ef7eb2e8f9f7	2257	#define FW_CSL_LENG ((uint32_t)0x003FFF00U) /!< Code Segment Length /
<>	144:ef7eb2e8f9f7	2258	#define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00U) /!< Non Volatile Dat Segment Start Address /
<>	144:ef7eb2e8f9f7	2259	#define FW_NVDSL_LENG ((uint32_t)0x003FFF00U) /!< Non Volatile Data Segment Length /
<>	144:ef7eb2e8f9f7	2260	#define FW_VDSSA_ADD ((uint32_t)0x0000FFC0U) /!< Volatile Data Segment Start Address /
<>	144:ef7eb2e8f9f7	2261	#define FW_VDSL_LENG ((uint32_t)0x0000FFC0U) /!< Volatile Data Segment Length /
<>	144:ef7eb2e8f9f7	2262
<>	144:ef7eb2e8f9f7	2263	/************************Bit definition for CR register *******************/
<>	144:ef7eb2e8f9f7	2264	#define FW_CR_FPA ((uint32_t)0x00000001U) /!< Firewall Pre Arm/
<>	144:ef7eb2e8f9f7	2265	#define FW_CR_VDS ((uint32_t)0x00000002U) /!< Volatile Data Sharing/
<>	144:ef7eb2e8f9f7	2266	#define FW_CR_VDE ((uint32_t)0x00000004U) /!< Volatile Data Execution/
<>	144:ef7eb2e8f9f7	2267
<>	144:ef7eb2e8f9f7	2268	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2269	/* */
<>	144:ef7eb2e8f9f7	2270	/* Power Control (PWR) */
<>	144:ef7eb2e8f9f7	2271	/* */
<>	144:ef7eb2e8f9f7	2272	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2273
<>	144:ef7eb2e8f9f7	2274	/****************** Bit definition for PWR_CR register ******************/
<>	144:ef7eb2e8f9f7	2275	#define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /!< Low-power deepsleep/sleep/low power run /
<>	144:ef7eb2e8f9f7	2276	#define PWR_CR_PDDS ((uint32_t)0x00000002U) /!< Power Down Deepsleep /
<>	144:ef7eb2e8f9f7	2277	#define PWR_CR_CWUF ((uint32_t)0x00000004U) /!< Clear Wakeup Flag /
<>	144:ef7eb2e8f9f7	2278	#define PWR_CR_CSBF ((uint32_t)0x00000008U) /!< Clear Standby Flag /
<>	144:ef7eb2e8f9f7	2279	#define PWR_CR_PVDE ((uint32_t)0x00000010U) /!< Power Voltage Detector Enable /
<>	144:ef7eb2e8f9f7	2280
<>	144:ef7eb2e8f9f7	2281	#define PWR_CR_PLS ((uint32_t)0x000000E0U) /!< PLS[2:0] bits (PVD Level Selection) /
<>	144:ef7eb2e8f9f7	2282	#define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2283	#define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2284	#define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	2285
<>	144:ef7eb2e8f9f7	2286	/!< PVD level configuration /
<>	144:ef7eb2e8f9f7	2287	#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /!< PVD level 0 /
<>	144:ef7eb2e8f9f7	2288	#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /!< PVD level 1 /
<>	144:ef7eb2e8f9f7	2289	#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /!< PVD level 2 /
<>	144:ef7eb2e8f9f7	2290	#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /!< PVD level 3 /
<>	144:ef7eb2e8f9f7	2291	#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /!< PVD level 4 /
<>	144:ef7eb2e8f9f7	2292	#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /!< PVD level 5 /
<>	144:ef7eb2e8f9f7	2293	#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /!< PVD level 6 /
<>	144:ef7eb2e8f9f7	2294	#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /!< PVD level 7 /
<>	144:ef7eb2e8f9f7	2295
<>	144:ef7eb2e8f9f7	2296	#define PWR_CR_DBP ((uint32_t)0x00000100U) /!< Disable Backup Domain write protection /
<>	144:ef7eb2e8f9f7	2297	#define PWR_CR_ULP ((uint32_t)0x00000200U) /!< Ultra Low Power mode /
<>	144:ef7eb2e8f9f7	2298	#define PWR_CR_FWU ((uint32_t)0x00000400U) /!< Fast wakeup /
<>	144:ef7eb2e8f9f7	2299
<>	144:ef7eb2e8f9f7	2300	#define PWR_CR_VOS ((uint32_t)0x00001800U) /!< VOS[1:0] bits (Voltage scaling range selection) /
<>	144:ef7eb2e8f9f7	2301	#define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2302	#define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2303	#define PWR_CR_DSEEKOFF ((uint32_t)0x00002000U) /!< Deep Sleep mode with EEPROM kept Off /
<>	144:ef7eb2e8f9f7	2304	#define PWR_CR_LPRUN ((uint32_t)0x00004000U) /!< Low power run mode /
<>	144:ef7eb2e8f9f7	2305
<>	144:ef7eb2e8f9f7	2306	/***************** Bit definition for PWR_CSR register ******************/
<>	144:ef7eb2e8f9f7	2307	#define PWR_CSR_WUF ((uint32_t)0x00000001U) /!< Wakeup Flag /
<>	144:ef7eb2e8f9f7	2308	#define PWR_CSR_SBF ((uint32_t)0x00000002U) /!< Standby Flag /
<>	144:ef7eb2e8f9f7	2309	#define PWR_CSR_PVDO ((uint32_t)0x00000004U) /!< PVD Output /
<>	144:ef7eb2e8f9f7	2310	#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /!< Internal voltage reference (VREFINT) ready flag /
<>	144:ef7eb2e8f9f7	2311	#define PWR_CSR_VOSF ((uint32_t)0x00000010U) /!< Voltage Scaling select flag /
<>	144:ef7eb2e8f9f7	2312	#define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /!< Regulator LP flag /
<>	144:ef7eb2e8f9f7	2313
<>	144:ef7eb2e8f9f7	2314	#define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /!< Enable WKUP pin 1 /
<>	144:ef7eb2e8f9f7	2315	#define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /!< Enable WKUP pin 2 /
<>	144:ef7eb2e8f9f7	2316	#define PWR_CSR_EWUP3 ((uint32_t)0x00000400U) /!< Enable WKUP pin 3 /
<>	144:ef7eb2e8f9f7	2317
<>	144:ef7eb2e8f9f7	2318	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2319	/* */
<>	144:ef7eb2e8f9f7	2320	/* Reset and Clock Control */
<>	144:ef7eb2e8f9f7	2321	/* */
<>	144:ef7eb2e8f9f7	2322	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2323
<>	144:ef7eb2e8f9f7	2324	/****************** Bit definition for RCC_CR register ******************/
<>	144:ef7eb2e8f9f7	2325	#define RCC_CR_HSION ((uint32_t)0x00000001U) /!< Internal High Speed clock enable /
<>	144:ef7eb2e8f9f7	2326	#define RCC_CR_HSIKERON ((uint32_t)0x00000002U) /!< Internal High Speed clock enable for some IPs Kernel /
<>	144:ef7eb2e8f9f7	2327	#define RCC_CR_HSIRDY ((uint32_t)0x00000004U) /!< Internal High Speed clock ready flag /
<>	144:ef7eb2e8f9f7	2328	#define RCC_CR_HSIDIVEN ((uint32_t)0x00000008U) /!< Internal High Speed clock divider enable /
<>	144:ef7eb2e8f9f7	2329	#define RCC_CR_HSIDIVF ((uint32_t)0x00000010U) /!< Internal High Speed clock divider flag /
<>	144:ef7eb2e8f9f7	2330	#define RCC_CR_HSIOUTEN ((uint32_t)0x00000020U) /!< Internal High Speed clock out enable /
<>	144:ef7eb2e8f9f7	2331	#define RCC_CR_MSION ((uint32_t)0x00000100U) /!< Internal Multi Speed clock enable /
<>	144:ef7eb2e8f9f7	2332	#define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /!< Internal Multi Speed clock ready flag /
<>	144:ef7eb2e8f9f7	2333	#define RCC_CR_HSEON ((uint32_t)0x00010000U) /!< External High Speed clock enable /
<>	144:ef7eb2e8f9f7	2334	#define RCC_CR_HSERDY ((uint32_t)0x00020000U) /!< External High Speed clock ready flag /
<>	144:ef7eb2e8f9f7	2335	#define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /!< External High Speed clock Bypass /
<>	144:ef7eb2e8f9f7	2336	#define RCC_CR_CSSHSEON ((uint32_t)0x00080000U) /!< HSE Clock Security System enable /
<>	144:ef7eb2e8f9f7	2337	#define RCC_CR_RTCPRE ((uint32_t)0x00300000U) /!< RTC/LCD prescaler [1:0] bits /
<>	144:ef7eb2e8f9f7	2338	#define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000U) /!< RTC/LCD prescaler Bit 0 /
<>	144:ef7eb2e8f9f7	2339	#define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000U) /!< RTC/LCD prescaler Bit 1 /
<>	144:ef7eb2e8f9f7	2340	#define RCC_CR_PLLON ((uint32_t)0x01000000U) /!< PLL enable /
<>	144:ef7eb2e8f9f7	2341	#define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /!< PLL clock ready flag /
<>	144:ef7eb2e8f9f7	2342
<>	144:ef7eb2e8f9f7	2343	/* Reference defines */
<>	144:ef7eb2e8f9f7	2344	#define RCC_CR_CSSON RCC_CR_CSSHSEON
<>	144:ef7eb2e8f9f7	2345
<>	144:ef7eb2e8f9f7	2346	/****************** Bit definition for RCC_ICSCR register ***************/
<>	144:ef7eb2e8f9f7	2347	#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /!< Internal High Speed clock Calibration /
<>	144:ef7eb2e8f9f7	2348	#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /!< Internal High Speed clock trimming /
<>	144:ef7eb2e8f9f7	2349
<>	144:ef7eb2e8f9f7	2350	#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /!< Internal Multi Speed clock Range /
<>	144:ef7eb2e8f9f7	2351	#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /!< Internal Multi Speed clock Range 65.536 KHz /
<>	144:ef7eb2e8f9f7	2352	#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /!< Internal Multi Speed clock Range 131.072 KHz /
<>	144:ef7eb2e8f9f7	2353	#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /!< Internal Multi Speed clock Range 262.144 KHz /
<>	144:ef7eb2e8f9f7	2354	#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /!< Internal Multi Speed clock Range 524.288 KHz /
<>	144:ef7eb2e8f9f7	2355	#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /!< Internal Multi Speed clock Range 1.048 MHz /
<>	144:ef7eb2e8f9f7	2356	#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /!< Internal Multi Speed clock Range 2.097 MHz /
<>	144:ef7eb2e8f9f7	2357	#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /!< Internal Multi Speed clock Range 4.194 MHz /
<>	144:ef7eb2e8f9f7	2358	#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /!< Internal Multi Speed clock Calibration /
<>	144:ef7eb2e8f9f7	2359	#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /!< Internal Multi Speed clock trimming /
<>	144:ef7eb2e8f9f7	2360
<>	144:ef7eb2e8f9f7	2361	/****************** Bit definition for RCC_CRRCR register ***************/
<>	144:ef7eb2e8f9f7	2362	#define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001U) /!< HSI 48MHz clock enable /
<>	144:ef7eb2e8f9f7	2363	#define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002U) /!< HSI 48MHz clock ready flag /
<>	144:ef7eb2e8f9f7	2364	#define RCC_CRRCR_HSI48DIV6OUTEN ((uint32_t)0x00000004U) /!< HSI 48MHz DIV6 out enable /
<>	144:ef7eb2e8f9f7	2365	#define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00U) /!< HSI 48MHz clock Calibration /
<>	144:ef7eb2e8f9f7	2366
<>	144:ef7eb2e8f9f7	2367	/***************** Bit definition for RCC_CFGR register *****************/
<>	144:ef7eb2e8f9f7	2368	/!< SW configuration /
<>	144:ef7eb2e8f9f7	2369	#define RCC_CFGR_SW ((uint32_t)0x00000003U) /!< SW[1:0] bits (System clock Switch) /
<>	144:ef7eb2e8f9f7	2370	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2371	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2372
<>	144:ef7eb2e8f9f7	2373	#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /!< MSI selected as system clock /
<>	144:ef7eb2e8f9f7	2374	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /!< HSI selected as system clock /
<>	144:ef7eb2e8f9f7	2375	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /!< HSE selected as system clock /
<>	144:ef7eb2e8f9f7	2376	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /!< PLL selected as system clock /
<>	144:ef7eb2e8f9f7	2377
<>	144:ef7eb2e8f9f7	2378	/!< SWS configuration /
<>	144:ef7eb2e8f9f7	2379	#define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /!< SWS[1:0] bits (System Clock Switch Status) /
<>	144:ef7eb2e8f9f7	2380	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2381	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2382
<>	144:ef7eb2e8f9f7	2383	#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /!< MSI oscillator used as system clock /
<>	144:ef7eb2e8f9f7	2384	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /!< HSI oscillator used as system clock /
<>	144:ef7eb2e8f9f7	2385	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /!< HSE oscillator used as system clock /
<>	144:ef7eb2e8f9f7	2386	#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /!< PLL used as system clock /
<>	144:ef7eb2e8f9f7	2387
<>	144:ef7eb2e8f9f7	2388	/!< HPRE configuration /
<>	144:ef7eb2e8f9f7	2389	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /!< HPRE[3:0] bits (AHB prescaler) /
<>	144:ef7eb2e8f9f7	2390	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2391	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2392	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	2393	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /!< Bit 3 /
<>	144:ef7eb2e8f9f7	2394
<>	144:ef7eb2e8f9f7	2395	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /!< SYSCLK not divided /
<>	144:ef7eb2e8f9f7	2396	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /!< SYSCLK divided by 2 /
<>	144:ef7eb2e8f9f7	2397	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /!< SYSCLK divided by 4 /
<>	144:ef7eb2e8f9f7	2398	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /!< SYSCLK divided by 8 /
<>	144:ef7eb2e8f9f7	2399	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /!< SYSCLK divided by 16 /
<>	144:ef7eb2e8f9f7	2400	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /!< SYSCLK divided by 64 /
<>	144:ef7eb2e8f9f7	2401	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /!< SYSCLK divided by 128 /
<>	144:ef7eb2e8f9f7	2402	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /!< SYSCLK divided by 256 /
<>	144:ef7eb2e8f9f7	2403	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /!< SYSCLK divided by 512 /
<>	144:ef7eb2e8f9f7	2404
<>	144:ef7eb2e8f9f7	2405	/!< PPRE1 configuration /
<>	144:ef7eb2e8f9f7	2406	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /!< PRE1[2:0] bits (APB1 prescaler) /
<>	144:ef7eb2e8f9f7	2407	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2408	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2409	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	2410
<>	144:ef7eb2e8f9f7	2411	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /!< HCLK not divided /
<>	144:ef7eb2e8f9f7	2412	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /!< HCLK divided by 2 /
<>	144:ef7eb2e8f9f7	2413	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /!< HCLK divided by 4 /
<>	144:ef7eb2e8f9f7	2414	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /!< HCLK divided by 8 /
<>	144:ef7eb2e8f9f7	2415	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /!< HCLK divided by 16 /
<>	144:ef7eb2e8f9f7	2416
<>	144:ef7eb2e8f9f7	2417	/!< PPRE2 configuration /
<>	144:ef7eb2e8f9f7	2418	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /!< PRE2[2:0] bits (APB2 prescaler) /
<>	144:ef7eb2e8f9f7	2419	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2420	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2421	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	2422
<>	144:ef7eb2e8f9f7	2423	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /!< HCLK not divided /
<>	144:ef7eb2e8f9f7	2424	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /!< HCLK divided by 2 /
<>	144:ef7eb2e8f9f7	2425	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /!< HCLK divided by 4 /
<>	144:ef7eb2e8f9f7	2426	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /!< HCLK divided by 8 /
<>	144:ef7eb2e8f9f7	2427	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /!< HCLK divided by 16 /
<>	144:ef7eb2e8f9f7	2428
<>	144:ef7eb2e8f9f7	2429	#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /!< Wake Up from Stop Clock selection /
<>	144:ef7eb2e8f9f7	2430
<>	144:ef7eb2e8f9f7	2431	/!< PLL entry clock source/
<>	144:ef7eb2e8f9f7	2432	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /!< PLL entry clock source /
<>	144:ef7eb2e8f9f7	2433
<>	144:ef7eb2e8f9f7	2434	#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /!< HSI as PLL entry clock source /
<>	144:ef7eb2e8f9f7	2435	#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /!< HSE as PLL entry clock source /
<>	144:ef7eb2e8f9f7	2436
<>	144:ef7eb2e8f9f7	2437
<>	144:ef7eb2e8f9f7	2438	/!< PLLMUL configuration /
<>	144:ef7eb2e8f9f7	2439	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
<>	144:ef7eb2e8f9f7	2440	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2441	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2442	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	2443	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /!< Bit 3 /
<>	144:ef7eb2e8f9f7	2444
<>	144:ef7eb2e8f9f7	2445	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /!< PLL input clock 3 */
<>	144:ef7eb2e8f9f7	2446	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /!< PLL input clock 4 */
<>	144:ef7eb2e8f9f7	2447	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /!< PLL input clock 6 */
<>	144:ef7eb2e8f9f7	2448	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /!< PLL input clock 8 */
<>	144:ef7eb2e8f9f7	2449	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /!< PLL input clock 12 */
<>	144:ef7eb2e8f9f7	2450	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /!< PLL input clock 16 */
<>	144:ef7eb2e8f9f7	2451	#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /!< PLL input clock 24 */
<>	144:ef7eb2e8f9f7	2452	#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /!< PLL input clock 32 */
<>	144:ef7eb2e8f9f7	2453	#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /!< PLL input clock 48 */
<>	144:ef7eb2e8f9f7	2454
<>	144:ef7eb2e8f9f7	2455	/!< PLLDIV configuration /
<>	144:ef7eb2e8f9f7	2456	#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /!< PLLDIV[1:0] bits (PLL Output Division) /
<>	144:ef7eb2e8f9f7	2457	#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /!< Bit0 /
<>	144:ef7eb2e8f9f7	2458	#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /!< Bit1 /
<>	144:ef7eb2e8f9f7	2459
<>	144:ef7eb2e8f9f7	2460	#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /!< PLL clock output = CKVCO / 2 /
<>	144:ef7eb2e8f9f7	2461	#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /!< PLL clock output = CKVCO / 3 /
<>	144:ef7eb2e8f9f7	2462	#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /!< PLL clock output = CKVCO / 4 /
<>	144:ef7eb2e8f9f7	2463
<>	144:ef7eb2e8f9f7	2464	/!< MCO configuration /
<>	144:ef7eb2e8f9f7	2465	#define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000U) /!< MCO[3:0] bits (Microcontroller Clock Output) /
<>	144:ef7eb2e8f9f7	2466	#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2467	#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2468	#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	2469	#define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000U) /!< Bit 3 /
<>	144:ef7eb2e8f9f7	2470
<>	144:ef7eb2e8f9f7	2471	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000U) /!< No clock /
<>	144:ef7eb2e8f9f7	2472	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000U) /!< System clock selected as MCO source /
<>	144:ef7eb2e8f9f7	2473	#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000U) /!< Internal 16 MHz RC oscillator clock selected /
<>	144:ef7eb2e8f9f7	2474	#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000U) /!< Internal Medium Speed RC oscillator clock selected /
<>	144:ef7eb2e8f9f7	2475	#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000U) /!< External 1-25 MHz oscillator clock selected /
<>	144:ef7eb2e8f9f7	2476	#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000U) /!< PLL clock divided /
<>	144:ef7eb2e8f9f7	2477	#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000U) /!< LSI selected /
<>	144:ef7eb2e8f9f7	2478	#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000U) /!< LSE selected /
<>	144:ef7eb2e8f9f7	2479	#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000U) /!< HSI48 clock selected as MCO source /
<>	144:ef7eb2e8f9f7	2480
<>	144:ef7eb2e8f9f7	2481	#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /!< MCO prescaler /
<>	144:ef7eb2e8f9f7	2482	#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /!< MCO is divided by 2 /
<>	144:ef7eb2e8f9f7	2483	#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /!< MCO is divided by 4 /
<>	144:ef7eb2e8f9f7	2484	#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /!< MCO is divided by 8 /
<>	144:ef7eb2e8f9f7	2485
<>	144:ef7eb2e8f9f7	2486	#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /!< MCO is divided by 1 /
<>	144:ef7eb2e8f9f7	2487	#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /!< MCO is divided by 2 /
<>	144:ef7eb2e8f9f7	2488	#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /!< MCO is divided by 4 /
<>	144:ef7eb2e8f9f7	2489	#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /!< MCO is divided by 8 /
<>	144:ef7eb2e8f9f7	2490	#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /!< MCO is divided by 16 /
<>	144:ef7eb2e8f9f7	2491
<>	144:ef7eb2e8f9f7	2492	/* Legacy defines */
<>	144:ef7eb2e8f9f7	2493	#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /!< MCO prescaler /
<>	144:ef7eb2e8f9f7	2494	#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /!< MCO is divided by 1 /
<>	144:ef7eb2e8f9f7	2495	#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO is divided by 1 /
<>	144:ef7eb2e8f9f7	2496	#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO is divided by 1 /
<>	144:ef7eb2e8f9f7	2497	#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO is divided by 1 /
<>	144:ef7eb2e8f9f7	2498	#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO is divided by 1 /
<>	144:ef7eb2e8f9f7	2499
<>	144:ef7eb2e8f9f7	2500	/!<*************** Bit definition for RCC_CIER register ******************/
<>	144:ef7eb2e8f9f7	2501	#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U) /!< LSI Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	2502	#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U) /!< LSE Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	2503	#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004U) /!< HSI Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	2504	#define RCC_CIER_HSERDYIE ((uint32_t)0x00000008U) /!< HSE Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	2505	#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010U) /!< PLL Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	2506	#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020U) /!< MSI Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	2507	#define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040U) /!< HSI48 Ready Interrupt Enable /
<>	144:ef7eb2e8f9f7	2508	#define RCC_CIER_CSSLSE ((uint32_t)0x00000080U) /!< LSE CSS Interrupt Enable /
<>	144:ef7eb2e8f9f7	2509
<>	144:ef7eb2e8f9f7	2510	/* Reference defines */
<>	144:ef7eb2e8f9f7	2511	#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
<>	144:ef7eb2e8f9f7	2512
<>	144:ef7eb2e8f9f7	2513	/!<*************** Bit definition for RCC_CIFR register ******************/
<>	144:ef7eb2e8f9f7	2514	#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U) /!< LSI Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	2515	#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U) /!< LSE Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	2516	#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004U) /!< HSI Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	2517	#define RCC_CIFR_HSERDYF ((uint32_t)0x00000008U) /!< HSE Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	2518	#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010U) /!< PLL Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	2519	#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020U) /!< MSI Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	2520	#define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040U) /!< HSI48 Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	2521	#define RCC_CIFR_CSSLSEF ((uint32_t)0x00000080U) /!< LSE Clock Security System Interrupt flag /
<>	144:ef7eb2e8f9f7	2522	#define RCC_CIFR_CSSHSEF ((uint32_t)0x00000100U) /!< HSE Clock Security System Interrupt flag /
<>	144:ef7eb2e8f9f7	2523
<>	144:ef7eb2e8f9f7	2524	/* Reference defines */
<>	144:ef7eb2e8f9f7	2525	#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
<>	144:ef7eb2e8f9f7	2526	#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
<>	144:ef7eb2e8f9f7	2527
<>	144:ef7eb2e8f9f7	2528	/!<*************** Bit definition for RCC_CICR register ******************/
<>	144:ef7eb2e8f9f7	2529	#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U) /!< LSI Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	2530	#define RCC_CICR_LSERDYC ((uint32_t)0x00000002U) /!< LSE Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	2531	#define RCC_CICR_HSIRDYC ((uint32_t)0x00000004U) /!< HSI Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	2532	#define RCC_CICR_HSERDYC ((uint32_t)0x00000008U) /!< HSE Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	2533	#define RCC_CICR_PLLRDYC ((uint32_t)0x00000010U) /!< PLL Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	2534	#define RCC_CICR_MSIRDYC ((uint32_t)0x00000020U) /!< MSI Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	2535	#define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040U) /!< HSI48 Ready Interrupt Clear /
<>	144:ef7eb2e8f9f7	2536	#define RCC_CICR_CSSLSEC ((uint32_t)0x00000080U) /!< LSE Clock Security System Interrupt Clear /
<>	144:ef7eb2e8f9f7	2537	#define RCC_CICR_CSSHSEC ((uint32_t)0x00000100U) /!< HSE Clock Security System Interrupt Clear /
<>	144:ef7eb2e8f9f7	2538
<>	144:ef7eb2e8f9f7	2539	/* Reference defines */
<>	144:ef7eb2e8f9f7	2540	#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
<>	144:ef7eb2e8f9f7	2541	#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
<>	144:ef7eb2e8f9f7	2542	/*************** Bit definition for RCC_IOPRSTR register ****************/
<>	144:ef7eb2e8f9f7	2543	#define RCC_IOPRSTR_IOPARST ((uint32_t)0x00000001U) /!< GPIO port A reset /
<>	144:ef7eb2e8f9f7	2544	#define RCC_IOPRSTR_IOPBRST ((uint32_t)0x00000002U) /!< GPIO port B reset /
<>	144:ef7eb2e8f9f7	2545	#define RCC_IOPRSTR_IOPCRST ((uint32_t)0x00000004U) /!< GPIO port C reset /
<>	144:ef7eb2e8f9f7	2546	#define RCC_IOPRSTR_IOPDRST ((uint32_t)0x00000008U) /!< GPIO port D reset /
<>	144:ef7eb2e8f9f7	2547	#define RCC_IOPRSTR_IOPERST ((uint32_t)0x00000010U) /!< GPIO port E reset /
<>	144:ef7eb2e8f9f7	2548	#define RCC_IOPRSTR_IOPHRST ((uint32_t)0x00000080U) /!< GPIO port H reset /
<>	144:ef7eb2e8f9f7	2549
<>	144:ef7eb2e8f9f7	2550	/* Reference defines */
<>	144:ef7eb2e8f9f7	2551	#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /!< GPIO port A reset /
<>	144:ef7eb2e8f9f7	2552	#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /!< GPIO port B reset /
<>	144:ef7eb2e8f9f7	2553	#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /!< GPIO port C reset /
<>	144:ef7eb2e8f9f7	2554	#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /!< GPIO port D reset /
<>	144:ef7eb2e8f9f7	2555	#define RCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERST /!< GPIO port E reset /
<>	144:ef7eb2e8f9f7	2556	#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /!< GPIO port H reset /
<>	144:ef7eb2e8f9f7	2557
<>	144:ef7eb2e8f9f7	2558
<>	144:ef7eb2e8f9f7	2559	/**************** Bit definition for RCC_AHBRST register ****************/
<>	144:ef7eb2e8f9f7	2560	#define RCC_AHBRSTR_DMARST ((uint32_t)0x00000001U) /!< DMA1 reset /
<>	144:ef7eb2e8f9f7	2561	#define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100U) /!< Memory interface reset reset /
<>	144:ef7eb2e8f9f7	2562	#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /!< CRC reset /
<>	144:ef7eb2e8f9f7	2563	#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000U) /!< TSC reset /
<>	144:ef7eb2e8f9f7	2564	#define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000U) /!< RNG reset /
<>	144:ef7eb2e8f9f7	2565
<>	144:ef7eb2e8f9f7	2566	/* Reference defines */
<>	144:ef7eb2e8f9f7	2567	#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /!< DMA1 reset /
<>	144:ef7eb2e8f9f7	2568
<>	144:ef7eb2e8f9f7	2569	/*************** Bit definition for RCC_APB2RSTR register ***************/
<>	144:ef7eb2e8f9f7	2570	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /!< SYSCFG clock reset /
<>	144:ef7eb2e8f9f7	2571	#define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004U) /!< TIM21 clock reset /
<>	144:ef7eb2e8f9f7	2572	#define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020U) /!< TIM22 clock reset /
<>	144:ef7eb2e8f9f7	2573	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200U) /!< ADC1 clock reset /
<>	144:ef7eb2e8f9f7	2574	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /!< SPI1 clock reset /
<>	144:ef7eb2e8f9f7	2575	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U) /!< USART1 clock reset /
<>	144:ef7eb2e8f9f7	2576	#define RCC_APB2RSTR_DBGRST ((uint32_t)0x00400000U) /!< DBGMCU clock reset /
<>	144:ef7eb2e8f9f7	2577
<>	144:ef7eb2e8f9f7	2578	/* Reference defines */
<>	144:ef7eb2e8f9f7	2579	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /!< ADC1 clock reset /
<>	144:ef7eb2e8f9f7	2580	#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /!< DBGMCU clock reset /
<>	144:ef7eb2e8f9f7	2581
<>	144:ef7eb2e8f9f7	2582	/*************** Bit definition for RCC_APB1RSTR register ***************/
<>	144:ef7eb2e8f9f7	2583	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /!< Timer 2 clock reset /
<>	144:ef7eb2e8f9f7	2584	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002U) /!< Timer 3 clock reset /
<>	144:ef7eb2e8f9f7	2585	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010U) /!< Timer 6 clock reset /
<>	144:ef7eb2e8f9f7	2586	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020U) /!< Timer 7 clock reset /
<>	144:ef7eb2e8f9f7	2587	#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200U) /!< LCD clock reset /
<>	144:ef7eb2e8f9f7	2588	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /!< Window Watchdog clock reset /
<>	144:ef7eb2e8f9f7	2589	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000U) /!< SPI2 clock reset /
<>	144:ef7eb2e8f9f7	2590	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /!< USART 2 clock reset /
<>	144:ef7eb2e8f9f7	2591	#define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000U) /!< LPUART1 clock reset /
<>	144:ef7eb2e8f9f7	2592	#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000U) /!< USART4 clock reset /
<>	144:ef7eb2e8f9f7	2593	#define RCC_APB1RSTR_USART5RST ((uint32_t)0x00100000U) /!< USART5 clock reset /
<>	144:ef7eb2e8f9f7	2594	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /!< I2C 1 clock reset /
<>	144:ef7eb2e8f9f7	2595	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000U) /!< I2C 2 clock reset /
<>	144:ef7eb2e8f9f7	2596	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000U) /!< USB clock reset /
<>	144:ef7eb2e8f9f7	2597	#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000U) /!< CRS clock reset /
<>	144:ef7eb2e8f9f7	2598	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /!< PWR clock reset /
<>	144:ef7eb2e8f9f7	2599	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000U) /!< DAC clock reset /
<>	144:ef7eb2e8f9f7	2600	#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000U) /!< I2C 3 clock reset /
<>	144:ef7eb2e8f9f7	2601	#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000U) /!< LPTIM1 clock reset /
<>	144:ef7eb2e8f9f7	2602
<>	144:ef7eb2e8f9f7	2603	/*************** Bit definition for RCC_IOPENR register ****************/
<>	144:ef7eb2e8f9f7	2604	#define RCC_IOPENR_IOPAEN ((uint32_t)0x00000001U) /!< GPIO port A clock enable /
<>	144:ef7eb2e8f9f7	2605	#define RCC_IOPENR_IOPBEN ((uint32_t)0x00000002U) /!< GPIO port B clock enable /
<>	144:ef7eb2e8f9f7	2606	#define RCC_IOPENR_IOPCEN ((uint32_t)0x00000004U) /!< GPIO port C clock enable /
<>	144:ef7eb2e8f9f7	2607	#define RCC_IOPENR_IOPDEN ((uint32_t)0x00000008U) /!< GPIO port D clock enable /
<>	144:ef7eb2e8f9f7	2608	#define RCC_IOPENR_IOPEEN ((uint32_t)0x00000010U) /!< GPIO port E clock enable /
<>	144:ef7eb2e8f9f7	2609	#define RCC_IOPENR_IOPHEN ((uint32_t)0x00000080U) /!< GPIO port H clock enable /
<>	144:ef7eb2e8f9f7	2610
<>	144:ef7eb2e8f9f7	2611	/* Reference defines */
<>	144:ef7eb2e8f9f7	2612	#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /!< GPIO port A clock enable /
<>	144:ef7eb2e8f9f7	2613	#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /!< GPIO port B clock enable /
<>	144:ef7eb2e8f9f7	2614	#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /!< GPIO port C clock enable /
<>	144:ef7eb2e8f9f7	2615	#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /!< GPIO port D clock enable /
<>	144:ef7eb2e8f9f7	2616	#define RCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEEN /!< GPIO port E clock enable /
<>	144:ef7eb2e8f9f7	2617	#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /!< GPIO port H clock enable /
<>	144:ef7eb2e8f9f7	2618
<>	144:ef7eb2e8f9f7	2619	/*************** Bit definition for RCC_AHBENR register ****************/
<>	144:ef7eb2e8f9f7	2620	#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001U) /!< DMA1 clock enable /
<>	144:ef7eb2e8f9f7	2621	#define RCC_AHBENR_MIFEN ((uint32_t)0x00000100U) /!< NVM interface clock enable bit /
<>	144:ef7eb2e8f9f7	2622	#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /!< CRC clock enable /
<>	144:ef7eb2e8f9f7	2623	#define RCC_AHBENR_TSCEN ((uint32_t)0x00010000U) /!< TSC clock enable /
<>	144:ef7eb2e8f9f7	2624	#define RCC_AHBENR_RNGEN ((uint32_t)0x00100000U) /!< RNG clock enable /
<>	144:ef7eb2e8f9f7	2625
<>	144:ef7eb2e8f9f7	2626	/* Reference defines */
<>	144:ef7eb2e8f9f7	2627	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /!< DMA1 clock enable /
<>	144:ef7eb2e8f9f7	2628
<>	144:ef7eb2e8f9f7	2629	/*************** Bit definition for RCC_APB2ENR register ****************/
<>	144:ef7eb2e8f9f7	2630	#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /!< SYSCFG clock enable /
<>	144:ef7eb2e8f9f7	2631	#define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004U) /!< TIM21 clock enable /
<>	144:ef7eb2e8f9f7	2632	#define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020U) /!< TIM22 clock enable /
<>	144:ef7eb2e8f9f7	2633	#define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U) /!< MiFare Firewall clock enable /
<>	144:ef7eb2e8f9f7	2634	#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200U) /!< ADC1 clock enable /
<>	144:ef7eb2e8f9f7	2635	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /!< SPI1 clock enable /
<>	144:ef7eb2e8f9f7	2636	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U) /!< USART1 clock enable /
<>	144:ef7eb2e8f9f7	2637	#define RCC_APB2ENR_DBGEN ((uint32_t)0x00400000U) /!< DBGMCU clock enable /
<>	144:ef7eb2e8f9f7	2638
<>	144:ef7eb2e8f9f7	2639	/* Reference defines */
<>	144:ef7eb2e8f9f7	2640
<>	144:ef7eb2e8f9f7	2641	#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /!< MiFare Firewall clock enable /
<>	144:ef7eb2e8f9f7	2642	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /!< ADC1 clock enable /
<>	144:ef7eb2e8f9f7	2643	#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /!< DBGMCU clock enable /
<>	144:ef7eb2e8f9f7	2644
<>	144:ef7eb2e8f9f7	2645	/*************** Bit definition for RCC_APB1ENR register ****************/
<>	144:ef7eb2e8f9f7	2646	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /!< Timer 2 clock enable /
<>	144:ef7eb2e8f9f7	2647	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002U) /!< Timer 3 clock enable /
<>	144:ef7eb2e8f9f7	2648	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010U) /!< Timer 6 clock enable /
<>	144:ef7eb2e8f9f7	2649	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020U) /!< Timer 7 clock enable /
<>	144:ef7eb2e8f9f7	2650	#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200U) /!< LCD clock enable /
<>	144:ef7eb2e8f9f7	2651	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /!< Window Watchdog clock enable /
<>	144:ef7eb2e8f9f7	2652	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000U) /!< SPI2 clock enable /
<>	144:ef7eb2e8f9f7	2653	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /!< USART2 clock enable /
<>	144:ef7eb2e8f9f7	2654	#define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000U) /!< LPUART1 clock enable /
<>	144:ef7eb2e8f9f7	2655	#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000U) /!< USART4 clock enable /
<>	144:ef7eb2e8f9f7	2656	#define RCC_APB1ENR_USART5EN ((uint32_t)0x00100000U) /!< USART5 clock enable /
<>	144:ef7eb2e8f9f7	2657	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /!< I2C1 clock enable /
<>	144:ef7eb2e8f9f7	2658	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000U) /!< I2C2 clock enable /
<>	144:ef7eb2e8f9f7	2659	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000U) /!< USB clock enable /
<>	144:ef7eb2e8f9f7	2660	#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000U) /!< CRS clock enable /
<>	144:ef7eb2e8f9f7	2661	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /!< PWR clock enable /
<>	144:ef7eb2e8f9f7	2662	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000U) /!< DAC clock enable /
<>	144:ef7eb2e8f9f7	2663	#define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000U) /!< I2C3 clock enable /
<>	144:ef7eb2e8f9f7	2664	#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000U) /!< LPTIM1 clock enable /
<>	144:ef7eb2e8f9f7	2665
<>	144:ef7eb2e8f9f7	2666	/**************** Bit definition for RCC_IOPSMENR register **************/
<>	144:ef7eb2e8f9f7	2667	#define RCC_IOPSMENR_IOPASMEN ((uint32_t)0x00000001U) /!< GPIO port A clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2668	#define RCC_IOPSMENR_IOPBSMEN ((uint32_t)0x00000002U) /!< GPIO port B clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2669	#define RCC_IOPSMENR_IOPCSMEN ((uint32_t)0x00000004U) /!< GPIO port C clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2670	#define RCC_IOPSMENR_IOPDSMEN ((uint32_t)0x00000008U) /!< GPIO port D clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2671	#define RCC_IOPSMENR_IOPESMEN ((uint32_t)0x00000010U) /!< GPIO port E clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2672	#define RCC_IOPSMENR_IOPHSMEN ((uint32_t)0x00000080U) /!< GPIO port H clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2673
<>	144:ef7eb2e8f9f7	2674	/* Reference defines */
<>	144:ef7eb2e8f9f7	2675	#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /!< GPIO port A clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2676	#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /!< GPIO port B clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2677	#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /!< GPIO port C clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2678	#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /!< GPIO port D clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2679	#define RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN /!< GPIO port E clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2680	#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /!< GPIO port H clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2681
<>	144:ef7eb2e8f9f7	2682	/*************** Bit definition for RCC_AHBSMENR register ****************/
<>	144:ef7eb2e8f9f7	2683	#define RCC_AHBSMENR_DMASMEN ((uint32_t)0x00000001U) /!< DMA1 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2684	#define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100U) /!< NVM interface clock enable during sleep mode /
<>	144:ef7eb2e8f9f7	2685	#define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200U) /!< SRAM clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2686	#define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000U) /!< CRC clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2687	#define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000U) /!< TSC clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2688	#define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000U) /!< RNG clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2689
<>	144:ef7eb2e8f9f7	2690	/* Reference defines */
<>	144:ef7eb2e8f9f7	2691	#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /!< DMA1 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2692
<>	144:ef7eb2e8f9f7	2693	/*************** Bit definition for RCC_APB2SMENR register ****************/
<>	144:ef7eb2e8f9f7	2694	#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U) /!< SYSCFG clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2695	#define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004U) /!< TIM21 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2696	#define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020U) /!< TIM22 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2697	#define RCC_APB2SMENR_ADCSMEN ((uint32_t)0x00000200U) /!< ADC1 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2698	#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U) /!< SPI1 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2699	#define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000U) /!< USART1 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2700	#define RCC_APB2SMENR_DBGSMEN ((uint32_t)0x00400000U) /!< DBGMCU clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2701
<>	144:ef7eb2e8f9f7	2702	/* Reference defines */
<>	144:ef7eb2e8f9f7	2703	#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /!< ADC1 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2704	#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /!< DBGMCU clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2705
<>	144:ef7eb2e8f9f7	2706	/*************** Bit definition for RCC_APB1SMENR register ****************/
<>	144:ef7eb2e8f9f7	2707	#define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001U) /!< Timer 2 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2708	#define RCC_APB1SMENR_TIM3SMEN ((uint32_t)0x00000002U) /!< Timer 3 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2709	#define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010U) /!< Timer 6 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2710	#define RCC_APB1SMENR_TIM7SMEN ((uint32_t)0x00000020U) /!< Timer 7 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2711	#define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200U) /!< LCD clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2712	#define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800U) /!< Window Watchdog clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2713	#define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000U) /!< SPI2 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2714	#define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000U) /!< USART2 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2715	#define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000U) /!< LPUART1 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2716	#define RCC_APB1SMENR_USART4SMEN ((uint32_t)0x00080000U) /!< USART4 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2717	#define RCC_APB1SMENR_USART5SMEN ((uint32_t)0x00100000U) /!< USART5 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2718	#define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000U) /!< I2C1 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2719	#define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000U) /!< I2C2 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2720	#define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000U) /!< USB clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2721	#define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000U) /!< CRS clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2722	#define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000U) /!< PWR clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2723	#define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000U) /!< DAC clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2724	#define RCC_APB1SMENR_I2C3SMEN ((uint32_t)0x40000000U) /!< I2C3 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2725	#define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000U) /!< LPTIM1 clock enabled in sleep mode /
<>	144:ef7eb2e8f9f7	2726
<>	144:ef7eb2e8f9f7	2727	/***************** Bit definition for RCC_CCIPR register *****************/
<>	144:ef7eb2e8f9f7	2728	/!< USART1 Clock source selection /
<>	144:ef7eb2e8f9f7	2729	#define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003U) /!< USART1SEL[1:0] bits /
<>	144:ef7eb2e8f9f7	2730	#define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2731	#define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2732
<>	144:ef7eb2e8f9f7	2733	/!< USART2 Clock source selection /
<>	144:ef7eb2e8f9f7	2734	#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU) /!< USART2SEL[1:0] bits /
<>	144:ef7eb2e8f9f7	2735	#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2736	#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2737
<>	144:ef7eb2e8f9f7	2738	/!< LPUART1 Clock source selection /
<>	144:ef7eb2e8f9f7	2739	#define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /!< LPUART1SEL[1:0] bits /
<>	144:ef7eb2e8f9f7	2740	#define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2741	#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2742
<>	144:ef7eb2e8f9f7	2743	/!< I2C1 Clock source selection /
<>	144:ef7eb2e8f9f7	2744	#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U) /!< I2C1SEL [1:0] bits /
<>	144:ef7eb2e8f9f7	2745	#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2746	#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2747
<>	144:ef7eb2e8f9f7	2748	/!< I2C3 Clock source selection /
<>	144:ef7eb2e8f9f7	2749	#define RCC_CCIPR_I2C3SEL ((uint32_t)0x00030000U) /!< I2C3SEL [1:0] bits /
<>	144:ef7eb2e8f9f7	2750	#define RCC_CCIPR_I2C3SEL_0 ((uint32_t)0x00010000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2751	#define RCC_CCIPR_I2C3SEL_1 ((uint32_t)0x00020000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2752
<>	144:ef7eb2e8f9f7	2753	/!< LPTIM1 Clock source selection /
<>	144:ef7eb2e8f9f7	2754	#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U) /!< LPTIM1SEL [1:0] bits /
<>	144:ef7eb2e8f9f7	2755	#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2756	#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2757
<>	144:ef7eb2e8f9f7	2758	/!< HSI48 Clock source selection /
<>	144:ef7eb2e8f9f7	2759	#define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000U) /!< HSI48 RC clock source selection bit for USB and RNG/
<>	144:ef7eb2e8f9f7	2760
<>	144:ef7eb2e8f9f7	2761	/* Legacy defines */
<>	144:ef7eb2e8f9f7	2762	#define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
<>	144:ef7eb2e8f9f7	2763
<>	144:ef7eb2e8f9f7	2764	/***************** Bit definition for RCC_CSR register *****************/
<>	144:ef7eb2e8f9f7	2765	#define RCC_CSR_LSION ((uint32_t)0x00000001U) /!< Internal Low Speed oscillator enable /
<>	144:ef7eb2e8f9f7	2766	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /!< Internal Low Speed oscillator Ready /
<>	144:ef7eb2e8f9f7	2767
<>	144:ef7eb2e8f9f7	2768	#define RCC_CSR_LSEON ((uint32_t)0x00000100U) /!< External Low Speed oscillator enable /
<>	144:ef7eb2e8f9f7	2769	#define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /!< External Low Speed oscillator Ready /
<>	144:ef7eb2e8f9f7	2770	#define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /!< External Low Speed oscillator Bypass /
<>	144:ef7eb2e8f9f7	2771
<>	144:ef7eb2e8f9f7	2772	#define RCC_CSR_LSEDRV ((uint32_t)0x00001800U) /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
<>	144:ef7eb2e8f9f7	2773	#define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2774	#define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2775
<>	144:ef7eb2e8f9f7	2776	#define RCC_CSR_LSECSSON ((uint32_t)0x00002000U) /!< External Low Speed oscillator CSS Enable /
<>	144:ef7eb2e8f9f7	2777	#define RCC_CSR_LSECSSD ((uint32_t)0x00004000U) /!< External Low Speed oscillator CSS Detected /
<>	144:ef7eb2e8f9f7	2778
<>	144:ef7eb2e8f9f7	2779	/!< RTC congiguration /
<>	144:ef7eb2e8f9f7	2780	#define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /!< RTCSEL[1:0] bits (RTC clock source selection) /
<>	144:ef7eb2e8f9f7	2781	#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	2782	#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	2783
<>	144:ef7eb2e8f9f7	2784	#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /!< No clock /
<>	144:ef7eb2e8f9f7	2785	#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /!< LSE oscillator clock used as RTC clock /
<>	144:ef7eb2e8f9f7	2786	#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /!< LSI oscillator clock used as RTC clock /
<>	144:ef7eb2e8f9f7	2787	#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /!< HSE oscillator clock used as RTC clock /
<>	144:ef7eb2e8f9f7	2788
<>	144:ef7eb2e8f9f7	2789	#define RCC_CSR_RTCEN ((uint32_t)0x00040000U) /!< RTC clock enable /
<>	144:ef7eb2e8f9f7	2790	#define RCC_CSR_RTCRST ((uint32_t)0x00080000U) /!< RTC software reset /
<>	144:ef7eb2e8f9f7	2791
<>	144:ef7eb2e8f9f7	2792	#define RCC_CSR_RMVF ((uint32_t)0x00800000U) /!< Remove reset flag /
<>	144:ef7eb2e8f9f7	2793	#define RCC_CSR_FWRSTF ((uint32_t)0x01000000U) /!< Mifare Firewall reset flag /
<>	144:ef7eb2e8f9f7	2794	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /!< OBL reset flag /
<>	144:ef7eb2e8f9f7	2795	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /!< PIN reset flag /
<>	144:ef7eb2e8f9f7	2796	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /!< POR/PDR reset flag /
<>	144:ef7eb2e8f9f7	2797	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /!< Software Reset flag /
<>	144:ef7eb2e8f9f7	2798	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /!< Independent Watchdog reset flag /
<>	144:ef7eb2e8f9f7	2799	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /!< Window watchdog reset flag /
<>	144:ef7eb2e8f9f7	2800	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /!< Low-Power reset flag /
<>	144:ef7eb2e8f9f7	2801
<>	144:ef7eb2e8f9f7	2802	/* Reference defines */
<>	144:ef7eb2e8f9f7	2803	#define RCC_CSR_OBL RCC_CSR_OBLRSTF /!< OBL reset flag /
<>	144:ef7eb2e8f9f7	2804
<>	144:ef7eb2e8f9f7	2805
<>	144:ef7eb2e8f9f7	2806	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2807	/* */
<>	144:ef7eb2e8f9f7	2808	/* RNG */
<>	144:ef7eb2e8f9f7	2809	/* */
<>	144:ef7eb2e8f9f7	2810	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2811	/****************** Bits definition for RNG_CR register *****************/
<>	144:ef7eb2e8f9f7	2812	#define RNG_CR_RNGEN ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	2813	#define RNG_CR_IE ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	2814
<>	144:ef7eb2e8f9f7	2815	/****************** Bits definition for RNG_SR register *****************/
<>	144:ef7eb2e8f9f7	2816	#define RNG_SR_DRDY ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	2817	#define RNG_SR_CECS ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	2818	#define RNG_SR_SECS ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	2819	#define RNG_SR_CEIS ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	2820	#define RNG_SR_SEIS ((uint32_t)0x00000040U)
<>	144:ef7eb2e8f9f7	2821
<>	144:ef7eb2e8f9f7	2822	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2823	/* */
<>	144:ef7eb2e8f9f7	2824	/* Real-Time Clock (RTC) */
<>	144:ef7eb2e8f9f7	2825	/* */
<>	144:ef7eb2e8f9f7	2826	/******************************************************************************/
<>	144:ef7eb2e8f9f7	2827	/****************** Bits definition for RTC_TR register *****************/
<>	144:ef7eb2e8f9f7	2828	#define RTC_TR_PM ((uint32_t)0x00400000U) /!< /
<>	144:ef7eb2e8f9f7	2829	#define RTC_TR_HT ((uint32_t)0x00300000U) /!< /
<>	144:ef7eb2e8f9f7	2830	#define RTC_TR_HT_0 ((uint32_t)0x00100000U) /!< /
<>	144:ef7eb2e8f9f7	2831	#define RTC_TR_HT_1 ((uint32_t)0x00200000U) /!< /
<>	144:ef7eb2e8f9f7	2832	#define RTC_TR_HU ((uint32_t)0x000F0000U) /!< /
<>	144:ef7eb2e8f9f7	2833	#define RTC_TR_HU_0 ((uint32_t)0x00010000U) /!< /
<>	144:ef7eb2e8f9f7	2834	#define RTC_TR_HU_1 ((uint32_t)0x00020000U) /!< /
<>	144:ef7eb2e8f9f7	2835	#define RTC_TR_HU_2 ((uint32_t)0x00040000U) /!< /
<>	144:ef7eb2e8f9f7	2836	#define RTC_TR_HU_3 ((uint32_t)0x00080000U) /!< /
<>	144:ef7eb2e8f9f7	2837	#define RTC_TR_MNT ((uint32_t)0x00007000U) /!< /
<>	144:ef7eb2e8f9f7	2838	#define RTC_TR_MNT_0 ((uint32_t)0x00001000U) /!< /
<>	144:ef7eb2e8f9f7	2839	#define RTC_TR_MNT_1 ((uint32_t)0x00002000U) /!< /
<>	144:ef7eb2e8f9f7	2840	#define RTC_TR_MNT_2 ((uint32_t)0x00004000U) /!< /
<>	144:ef7eb2e8f9f7	2841	#define RTC_TR_MNU ((uint32_t)0x00000F00U) /!< /
<>	144:ef7eb2e8f9f7	2842	#define RTC_TR_MNU_0 ((uint32_t)0x00000100U) /!< /
<>	144:ef7eb2e8f9f7	2843	#define RTC_TR_MNU_1 ((uint32_t)0x00000200U) /!< /
<>	144:ef7eb2e8f9f7	2844	#define RTC_TR_MNU_2 ((uint32_t)0x00000400U) /!< /
<>	144:ef7eb2e8f9f7	2845	#define RTC_TR_MNU_3 ((uint32_t)0x00000800U) /!< /
<>	144:ef7eb2e8f9f7	2846	#define RTC_TR_ST ((uint32_t)0x00000070U) /!< /
<>	144:ef7eb2e8f9f7	2847	#define RTC_TR_ST_0 ((uint32_t)0x00000010U) /!< /
<>	144:ef7eb2e8f9f7	2848	#define RTC_TR_ST_1 ((uint32_t)0x00000020U) /!< /
<>	144:ef7eb2e8f9f7	2849	#define RTC_TR_ST_2 ((uint32_t)0x00000040U) /!< /
<>	144:ef7eb2e8f9f7	2850	#define RTC_TR_SU ((uint32_t)0x0000000FU) /!< /
<>	144:ef7eb2e8f9f7	2851	#define RTC_TR_SU_0 ((uint32_t)0x00000001U) /!< /
<>	144:ef7eb2e8f9f7	2852	#define RTC_TR_SU_1 ((uint32_t)0x00000002U) /!< /
<>	144:ef7eb2e8f9f7	2853	#define RTC_TR_SU_2 ((uint32_t)0x00000004U) /!< /
<>	144:ef7eb2e8f9f7	2854	#define RTC_TR_SU_3 ((uint32_t)0x00000008U) /!< /
<>	144:ef7eb2e8f9f7	2855
<>	144:ef7eb2e8f9f7	2856	/****************** Bits definition for RTC_DR register *****************/
<>	144:ef7eb2e8f9f7	2857	#define RTC_DR_YT ((uint32_t)0x00F00000U) /!< /
<>	144:ef7eb2e8f9f7	2858	#define RTC_DR_YT_0 ((uint32_t)0x00100000U) /!< /
<>	144:ef7eb2e8f9f7	2859	#define RTC_DR_YT_1 ((uint32_t)0x00200000U) /!< /
<>	144:ef7eb2e8f9f7	2860	#define RTC_DR_YT_2 ((uint32_t)0x00400000U) /!< /
<>	144:ef7eb2e8f9f7	2861	#define RTC_DR_YT_3 ((uint32_t)0x00800000U) /!< /
<>	144:ef7eb2e8f9f7	2862	#define RTC_DR_YU ((uint32_t)0x000F0000U) /!< /
<>	144:ef7eb2e8f9f7	2863	#define RTC_DR_YU_0 ((uint32_t)0x00010000U) /!< /
<>	144:ef7eb2e8f9f7	2864	#define RTC_DR_YU_1 ((uint32_t)0x00020000U) /!< /
<>	144:ef7eb2e8f9f7	2865	#define RTC_DR_YU_2 ((uint32_t)0x00040000U) /!< /
<>	144:ef7eb2e8f9f7	2866	#define RTC_DR_YU_3 ((uint32_t)0x00080000U) /!< /
<>	144:ef7eb2e8f9f7	2867	#define RTC_DR_WDU ((uint32_t)0x0000E000U) /!< /
<>	144:ef7eb2e8f9f7	2868	#define RTC_DR_WDU_0 ((uint32_t)0x00002000U) /!< /
<>	144:ef7eb2e8f9f7	2869	#define RTC_DR_WDU_1 ((uint32_t)0x00004000U) /!< /
<>	144:ef7eb2e8f9f7	2870	#define RTC_DR_WDU_2 ((uint32_t)0x00008000U) /!< /
<>	144:ef7eb2e8f9f7	2871	#define RTC_DR_MT ((uint32_t)0x00001000U) /!< /
<>	144:ef7eb2e8f9f7	2872	#define RTC_DR_MU ((uint32_t)0x00000F00U) /!< /
<>	144:ef7eb2e8f9f7	2873	#define RTC_DR_MU_0 ((uint32_t)0x00000100U) /!< /
<>	144:ef7eb2e8f9f7	2874	#define RTC_DR_MU_1 ((uint32_t)0x00000200U) /!< /
<>	144:ef7eb2e8f9f7	2875	#define RTC_DR_MU_2 ((uint32_t)0x00000400U) /!< /
<>	144:ef7eb2e8f9f7	2876	#define RTC_DR_MU_3 ((uint32_t)0x00000800U) /!< /
<>	144:ef7eb2e8f9f7	2877	#define RTC_DR_DT ((uint32_t)0x00000030U) /!< /
<>	144:ef7eb2e8f9f7	2878	#define RTC_DR_DT_0 ((uint32_t)0x00000010U) /!< /
<>	144:ef7eb2e8f9f7	2879	#define RTC_DR_DT_1 ((uint32_t)0x00000020U) /!< /
<>	144:ef7eb2e8f9f7	2880	#define RTC_DR_DU ((uint32_t)0x0000000FU) /!< /
<>	144:ef7eb2e8f9f7	2881	#define RTC_DR_DU_0 ((uint32_t)0x00000001U) /!< /
<>	144:ef7eb2e8f9f7	2882	#define RTC_DR_DU_1 ((uint32_t)0x00000002U) /!< /
<>	144:ef7eb2e8f9f7	2883	#define RTC_DR_DU_2 ((uint32_t)0x00000004U) /!< /
<>	144:ef7eb2e8f9f7	2884	#define RTC_DR_DU_3 ((uint32_t)0x00000008U) /!< /
<>	144:ef7eb2e8f9f7	2885
<>	144:ef7eb2e8f9f7	2886	/****************** Bits definition for RTC_CR register *****************/
<>	144:ef7eb2e8f9f7	2887	#define RTC_CR_COE ((uint32_t)0x00800000U) /!< /
<>	144:ef7eb2e8f9f7	2888	#define RTC_CR_OSEL ((uint32_t)0x00600000U) /!< /
<>	144:ef7eb2e8f9f7	2889	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000U) /!< /
<>	144:ef7eb2e8f9f7	2890	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000U) /!< /
<>	144:ef7eb2e8f9f7	2891	#define RTC_CR_POL ((uint32_t)0x00100000U) /!< /
<>	144:ef7eb2e8f9f7	2892	#define RTC_CR_COSEL ((uint32_t)0x00080000U) /!< /
<>	144:ef7eb2e8f9f7	2893	#define RTC_CR_BCK ((uint32_t)0x00040000U) /!< /
<>	144:ef7eb2e8f9f7	2894	#define RTC_CR_SUB1H ((uint32_t)0x00020000U) /!< /
<>	144:ef7eb2e8f9f7	2895	#define RTC_CR_ADD1H ((uint32_t)0x00010000U) /!< /
<>	144:ef7eb2e8f9f7	2896	#define RTC_CR_TSIE ((uint32_t)0x00008000U) /!< /
<>	144:ef7eb2e8f9f7	2897	#define RTC_CR_WUTIE ((uint32_t)0x00004000U) /!< /
<>	144:ef7eb2e8f9f7	2898	#define RTC_CR_ALRBIE ((uint32_t)0x00002000U) /!< /
<>	144:ef7eb2e8f9f7	2899	#define RTC_CR_ALRAIE ((uint32_t)0x00001000U) /!< /
<>	144:ef7eb2e8f9f7	2900	#define RTC_CR_TSE ((uint32_t)0x00000800U) /!< /
<>	144:ef7eb2e8f9f7	2901	#define RTC_CR_WUTE ((uint32_t)0x00000400U) /!< /
<>	144:ef7eb2e8f9f7	2902	#define RTC_CR_ALRBE ((uint32_t)0x00000200U) /!< /
<>	144:ef7eb2e8f9f7	2903	#define RTC_CR_ALRAE ((uint32_t)0x00000100U) /!< /
<>	144:ef7eb2e8f9f7	2904	#define RTC_CR_FMT ((uint32_t)0x00000040U) /!< /
<>	144:ef7eb2e8f9f7	2905	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020U) /!< /
<>	144:ef7eb2e8f9f7	2906	#define RTC_CR_REFCKON ((uint32_t)0x00000010U) /!< /
<>	144:ef7eb2e8f9f7	2907	#define RTC_CR_TSEDGE ((uint32_t)0x00000008U) /!< /
<>	144:ef7eb2e8f9f7	2908	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007U) /!< /
<>	144:ef7eb2e8f9f7	2909	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U) /!< /
<>	144:ef7eb2e8f9f7	2910	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U) /!< /
<>	144:ef7eb2e8f9f7	2911	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U) /!< /
<>	144:ef7eb2e8f9f7	2912
<>	144:ef7eb2e8f9f7	2913	/****************** Bits definition for RTC_ISR register ****************/
<>	144:ef7eb2e8f9f7	2914	#define RTC_ISR_RECALPF ((uint32_t)0x00010000U) /!< /
<>	144:ef7eb2e8f9f7	2915	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000U) /!< /
<>	144:ef7eb2e8f9f7	2916	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000U) /!< /
<>	144:ef7eb2e8f9f7	2917	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000U) /!< /
<>	144:ef7eb2e8f9f7	2918	#define RTC_ISR_TSOVF ((uint32_t)0x00001000U) /!< /
<>	144:ef7eb2e8f9f7	2919	#define RTC_ISR_TSF ((uint32_t)0x00000800U) /!< /
<>	144:ef7eb2e8f9f7	2920	#define RTC_ISR_WUTF ((uint32_t)0x00000400U) /!< /
<>	144:ef7eb2e8f9f7	2921	#define RTC_ISR_ALRBF ((uint32_t)0x00000200U) /!< /
<>	144:ef7eb2e8f9f7	2922	#define RTC_ISR_ALRAF ((uint32_t)0x00000100U) /!< /
<>	144:ef7eb2e8f9f7	2923	#define RTC_ISR_INIT ((uint32_t)0x00000080U) /!< /
<>	144:ef7eb2e8f9f7	2924	#define RTC_ISR_INITF ((uint32_t)0x00000040U) /!< /
<>	144:ef7eb2e8f9f7	2925	#define RTC_ISR_RSF ((uint32_t)0x00000020U) /!< /
<>	144:ef7eb2e8f9f7	2926	#define RTC_ISR_INITS ((uint32_t)0x00000010U) /!< /
<>	144:ef7eb2e8f9f7	2927	#define RTC_ISR_SHPF ((uint32_t)0x00000008U) /!< /
<>	144:ef7eb2e8f9f7	2928	#define RTC_ISR_WUTWF ((uint32_t)0x00000004U) /!< /
<>	144:ef7eb2e8f9f7	2929	#define RTC_ISR_ALRBWF ((uint32_t)0x00000002U) /!< /
<>	144:ef7eb2e8f9f7	2930	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001U) /!< /
<>	144:ef7eb2e8f9f7	2931
<>	144:ef7eb2e8f9f7	2932	/****************** Bits definition for RTC_PRER register ***************/
<>	144:ef7eb2e8f9f7	2933	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U) /!< /
<>	144:ef7eb2e8f9f7	2934	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU) /!< /
<>	144:ef7eb2e8f9f7	2935
<>	144:ef7eb2e8f9f7	2936	/****************** Bits definition for RTC_WUTR register ***************/
<>	144:ef7eb2e8f9f7	2937	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU)
<>	144:ef7eb2e8f9f7	2938
<>	144:ef7eb2e8f9f7	2939	/****************** Bits definition for RTC_ALRMAR register *************/
<>	144:ef7eb2e8f9f7	2940	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U) /!< /
<>	144:ef7eb2e8f9f7	2941	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U) /!< /
<>	144:ef7eb2e8f9f7	2942	#define RTC_ALRMAR_DT ((uint32_t)0x30000000U) /!< /
<>	144:ef7eb2e8f9f7	2943	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U) /!< /
<>	144:ef7eb2e8f9f7	2944	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U) /!< /
<>	144:ef7eb2e8f9f7	2945	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000U) /!< /
<>	144:ef7eb2e8f9f7	2946	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U) /!< /
<>	144:ef7eb2e8f9f7	2947	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U) /!< /
<>	144:ef7eb2e8f9f7	2948	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U) /!< /
<>	144:ef7eb2e8f9f7	2949	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U) /!< /
<>	144:ef7eb2e8f9f7	2950	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U) /!< /
<>	144:ef7eb2e8f9f7	2951	#define RTC_ALRMAR_PM ((uint32_t)0x00400000U) /!< /
<>	144:ef7eb2e8f9f7	2952	#define RTC_ALRMAR_HT ((uint32_t)0x00300000U) /!< /
<>	144:ef7eb2e8f9f7	2953	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U) /!< /
<>	144:ef7eb2e8f9f7	2954	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U) /!< /
<>	144:ef7eb2e8f9f7	2955	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000U) /!< /
<>	144:ef7eb2e8f9f7	2956	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U) /!< /
<>	144:ef7eb2e8f9f7	2957	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U) /!< /
<>	144:ef7eb2e8f9f7	2958	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U) /!< /
<>	144:ef7eb2e8f9f7	2959	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U) /!< /
<>	144:ef7eb2e8f9f7	2960	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U) /!< /
<>	144:ef7eb2e8f9f7	2961	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000U) /!< /
<>	144:ef7eb2e8f9f7	2962	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U) /!< /
<>	144:ef7eb2e8f9f7	2963	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U) /!< /
<>	144:ef7eb2e8f9f7	2964	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U) /!< /
<>	144:ef7eb2e8f9f7	2965	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U) /!< /
<>	144:ef7eb2e8f9f7	2966	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U) /!< /
<>	144:ef7eb2e8f9f7	2967	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U) /!< /
<>	144:ef7eb2e8f9f7	2968	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U) /!< /
<>	144:ef7eb2e8f9f7	2969	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U) /!< /
<>	144:ef7eb2e8f9f7	2970	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U) /!< /
<>	144:ef7eb2e8f9f7	2971	#define RTC_ALRMAR_ST ((uint32_t)0x00000070U) /!< /
<>	144:ef7eb2e8f9f7	2972	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U) /!< /
<>	144:ef7eb2e8f9f7	2973	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U) /!< /
<>	144:ef7eb2e8f9f7	2974	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U) /!< /
<>	144:ef7eb2e8f9f7	2975	#define RTC_ALRMAR_SU ((uint32_t)0x0000000FU) /!< /
<>	144:ef7eb2e8f9f7	2976	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U) /!< /
<>	144:ef7eb2e8f9f7	2977	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U) /!< /
<>	144:ef7eb2e8f9f7	2978	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U) /!< /
<>	144:ef7eb2e8f9f7	2979	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U) /!< /
<>	144:ef7eb2e8f9f7	2980
<>	144:ef7eb2e8f9f7	2981	/****************** Bits definition for RTC_ALRMBR register *************/
<>	144:ef7eb2e8f9f7	2982	#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U) /!< /
<>	144:ef7eb2e8f9f7	2983	#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U) /!< /
<>	144:ef7eb2e8f9f7	2984	#define RTC_ALRMBR_DT ((uint32_t)0x30000000U) /!< /
<>	144:ef7eb2e8f9f7	2985	#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U) /!< /
<>	144:ef7eb2e8f9f7	2986	#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U) /!< /
<>	144:ef7eb2e8f9f7	2987	#define RTC_ALRMBR_DU ((uint32_t)0x0F000000U) /!< /
<>	144:ef7eb2e8f9f7	2988	#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U) /!< /
<>	144:ef7eb2e8f9f7	2989	#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U) /!< /
<>	144:ef7eb2e8f9f7	2990	#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U) /!< /
<>	144:ef7eb2e8f9f7	2991	#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U) /!< /
<>	144:ef7eb2e8f9f7	2992	#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U) /!< /
<>	144:ef7eb2e8f9f7	2993	#define RTC_ALRMBR_PM ((uint32_t)0x00400000U) /!< /
<>	144:ef7eb2e8f9f7	2994	#define RTC_ALRMBR_HT ((uint32_t)0x00300000U) /!< /
<>	144:ef7eb2e8f9f7	2995	#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U) /!< /
<>	144:ef7eb2e8f9f7	2996	#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U) /!< /
<>	144:ef7eb2e8f9f7	2997	#define RTC_ALRMBR_HU ((uint32_t)0x000F0000U) /!< /
<>	144:ef7eb2e8f9f7	2998	#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U) /!< /
<>	144:ef7eb2e8f9f7	2999	#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U) /!< /
<>	144:ef7eb2e8f9f7	3000	#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U) /!< /
<>	144:ef7eb2e8f9f7	3001	#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U) /!< /
<>	144:ef7eb2e8f9f7	3002	#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U) /!< /
<>	144:ef7eb2e8f9f7	3003	#define RTC_ALRMBR_MNT ((uint32_t)0x00007000U) /!< /
<>	144:ef7eb2e8f9f7	3004	#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U) /!< /
<>	144:ef7eb2e8f9f7	3005	#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U) /!< /
<>	144:ef7eb2e8f9f7	3006	#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U) /!< /
<>	144:ef7eb2e8f9f7	3007	#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U) /!< /
<>	144:ef7eb2e8f9f7	3008	#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U) /!< /
<>	144:ef7eb2e8f9f7	3009	#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U) /!< /
<>	144:ef7eb2e8f9f7	3010	#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U) /!< /
<>	144:ef7eb2e8f9f7	3011	#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U) /!< /
<>	144:ef7eb2e8f9f7	3012	#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U) /!< /
<>	144:ef7eb2e8f9f7	3013	#define RTC_ALRMBR_ST ((uint32_t)0x00000070U) /!< /
<>	144:ef7eb2e8f9f7	3014	#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U) /!< /
<>	144:ef7eb2e8f9f7	3015	#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U) /!< /
<>	144:ef7eb2e8f9f7	3016	#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U) /!< /
<>	144:ef7eb2e8f9f7	3017	#define RTC_ALRMBR_SU ((uint32_t)0x0000000FU) /!< /
<>	144:ef7eb2e8f9f7	3018	#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U) /!< /
<>	144:ef7eb2e8f9f7	3019	#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U) /!< /
<>	144:ef7eb2e8f9f7	3020	#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U) /!< /
<>	144:ef7eb2e8f9f7	3021	#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U) /!< /
<>	144:ef7eb2e8f9f7	3022
<>	144:ef7eb2e8f9f7	3023	/****************** Bits definition for RTC_WPR register ****************/
<>	144:ef7eb2e8f9f7	3024	#define RTC_WPR_KEY ((uint32_t)0x000000FFU) /!< /
<>	144:ef7eb2e8f9f7	3025
<>	144:ef7eb2e8f9f7	3026	/****************** Bits definition for RTC_SSR register ****************/
<>	144:ef7eb2e8f9f7	3027	#define RTC_SSR_SS ((uint32_t)0x0000FFFFU) /!< /
<>	144:ef7eb2e8f9f7	3028
<>	144:ef7eb2e8f9f7	3029	/****************** Bits definition for RTC_SHIFTR register *************/
<>	144:ef7eb2e8f9f7	3030	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU) /!< /
<>	144:ef7eb2e8f9f7	3031	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U) /!< /
<>	144:ef7eb2e8f9f7	3032
<>	144:ef7eb2e8f9f7	3033	/****************** Bits definition for RTC_TSTR register ***************/
<>	144:ef7eb2e8f9f7	3034	#define RTC_TSTR_PM ((uint32_t)0x00400000U) /!< /
<>	144:ef7eb2e8f9f7	3035	#define RTC_TSTR_HT ((uint32_t)0x00300000U) /!< /
<>	144:ef7eb2e8f9f7	3036	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000U) /!< /
<>	144:ef7eb2e8f9f7	3037	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000U) /!< /
<>	144:ef7eb2e8f9f7	3038	#define RTC_TSTR_HU ((uint32_t)0x000F0000U) /!< /
<>	144:ef7eb2e8f9f7	3039	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000U) /!< /
<>	144:ef7eb2e8f9f7	3040	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000U) /!< /
<>	144:ef7eb2e8f9f7	3041	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000U) /!< /
<>	144:ef7eb2e8f9f7	3042	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000U) /!< /
<>	144:ef7eb2e8f9f7	3043	#define RTC_TSTR_MNT ((uint32_t)0x00007000U) /!< /
<>	144:ef7eb2e8f9f7	3044	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U) /!< /
<>	144:ef7eb2e8f9f7	3045	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U) /!< /
<>	144:ef7eb2e8f9f7	3046	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U) /!< /
<>	144:ef7eb2e8f9f7	3047	#define RTC_TSTR_MNU ((uint32_t)0x00000F00U) /!< /
<>	144:ef7eb2e8f9f7	3048	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U) /!< /
<>	144:ef7eb2e8f9f7	3049	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U) /!< /
<>	144:ef7eb2e8f9f7	3050	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U) /!< /
<>	144:ef7eb2e8f9f7	3051	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U) /!< /
<>	144:ef7eb2e8f9f7	3052	#define RTC_TSTR_ST ((uint32_t)0x00000070U) /!< /
<>	144:ef7eb2e8f9f7	3053	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010U) /!< /
<>	144:ef7eb2e8f9f7	3054	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020U) /!< /
<>	144:ef7eb2e8f9f7	3055	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040U) /!< /
<>	144:ef7eb2e8f9f7	3056	#define RTC_TSTR_SU ((uint32_t)0x0000000FU) /!< /
<>	144:ef7eb2e8f9f7	3057	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001U) /!< /
<>	144:ef7eb2e8f9f7	3058	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002U) /!< /
<>	144:ef7eb2e8f9f7	3059	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004U) /!< /
<>	144:ef7eb2e8f9f7	3060	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008U) /!< /
<>	144:ef7eb2e8f9f7	3061
<>	144:ef7eb2e8f9f7	3062	/****************** Bits definition for RTC_TSDR register ***************/
<>	144:ef7eb2e8f9f7	3063	#define RTC_TSDR_WDU ((uint32_t)0x0000E000U) /!< /
<>	144:ef7eb2e8f9f7	3064	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U) /!< /
<>	144:ef7eb2e8f9f7	3065	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U) /!< /
<>	144:ef7eb2e8f9f7	3066	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U) /!< /
<>	144:ef7eb2e8f9f7	3067	#define RTC_TSDR_MT ((uint32_t)0x00001000U) /!< /
<>	144:ef7eb2e8f9f7	3068	#define RTC_TSDR_MU ((uint32_t)0x00000F00U) /!< /
<>	144:ef7eb2e8f9f7	3069	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100U) /!< /
<>	144:ef7eb2e8f9f7	3070	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200U) /!< /
<>	144:ef7eb2e8f9f7	3071	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400U) /!< /
<>	144:ef7eb2e8f9f7	3072	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800U) /!< /
<>	144:ef7eb2e8f9f7	3073	#define RTC_TSDR_DT ((uint32_t)0x00000030U) /!< /
<>	144:ef7eb2e8f9f7	3074	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010U) /!< /
<>	144:ef7eb2e8f9f7	3075	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020U) /!< /
<>	144:ef7eb2e8f9f7	3076	#define RTC_TSDR_DU ((uint32_t)0x0000000FU) /!< /
<>	144:ef7eb2e8f9f7	3077	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001U) /!< /
<>	144:ef7eb2e8f9f7	3078	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002U) /!< /
<>	144:ef7eb2e8f9f7	3079	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004U) /!< /
<>	144:ef7eb2e8f9f7	3080	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008U) /!< /
<>	144:ef7eb2e8f9f7	3081
<>	144:ef7eb2e8f9f7	3082	/****************** Bits definition for RTC_TSSSR register **************/
<>	144:ef7eb2e8f9f7	3083	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU)
<>	144:ef7eb2e8f9f7	3084
<>	144:ef7eb2e8f9f7	3085	/****************** Bits definition for RTC_CALR register ***************/
<>	144:ef7eb2e8f9f7	3086	#define RTC_CALR_CALP ((uint32_t)0x00008000U) /!< /
<>	144:ef7eb2e8f9f7	3087	#define RTC_CALR_CALW8 ((uint32_t)0x00004000U) /!< /
<>	144:ef7eb2e8f9f7	3088	#define RTC_CALR_CALW16 ((uint32_t)0x00002000U) /!< /
<>	144:ef7eb2e8f9f7	3089	#define RTC_CALR_CALM ((uint32_t)0x000001FFU) /!< /
<>	144:ef7eb2e8f9f7	3090	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001U) /!< /
<>	144:ef7eb2e8f9f7	3091	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002U) /!< /
<>	144:ef7eb2e8f9f7	3092	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004U) /!< /
<>	144:ef7eb2e8f9f7	3093	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008U) /!< /
<>	144:ef7eb2e8f9f7	3094	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010U) /!< /
<>	144:ef7eb2e8f9f7	3095	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020U) /!< /
<>	144:ef7eb2e8f9f7	3096	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040U) /!< /
<>	144:ef7eb2e8f9f7	3097	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080U) /!< /
<>	144:ef7eb2e8f9f7	3098	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100U) /!< /
<>	144:ef7eb2e8f9f7	3099
<>	144:ef7eb2e8f9f7	3100	/* Legacy defines */
<>	144:ef7eb2e8f9f7	3101	#define RTC_CAL_CALP RTC_CALR_CALP
<>	144:ef7eb2e8f9f7	3102	#define RTC_CAL_CALW8 RTC_CALR_CALW8
<>	144:ef7eb2e8f9f7	3103	#define RTC_CAL_CALW16 RTC_CALR_CALW16
<>	144:ef7eb2e8f9f7	3104	#define RTC_CAL_CALM RTC_CALR_CALM
<>	144:ef7eb2e8f9f7	3105	#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
<>	144:ef7eb2e8f9f7	3106	#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
<>	144:ef7eb2e8f9f7	3107	#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
<>	144:ef7eb2e8f9f7	3108	#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
<>	144:ef7eb2e8f9f7	3109	#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
<>	144:ef7eb2e8f9f7	3110	#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
<>	144:ef7eb2e8f9f7	3111	#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
<>	144:ef7eb2e8f9f7	3112	#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
<>	144:ef7eb2e8f9f7	3113	#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
<>	144:ef7eb2e8f9f7	3114
<>	144:ef7eb2e8f9f7	3115	/****************** Bits definition for RTC_TAMPCR register **************/
<>	144:ef7eb2e8f9f7	3116	#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000U) /!< /
<>	144:ef7eb2e8f9f7	3117	#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000U) /!< /
<>	144:ef7eb2e8f9f7	3118	#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000U) /!< /
<>	144:ef7eb2e8f9f7	3119	#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U) /!< /
<>	144:ef7eb2e8f9f7	3120	#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U) /!< /
<>	144:ef7eb2e8f9f7	3121	#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U) /!< /
<>	144:ef7eb2e8f9f7	3122	#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U) /!< /
<>	144:ef7eb2e8f9f7	3123	#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U) /!< /
<>	144:ef7eb2e8f9f7	3124	#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U) /!< /
<>	144:ef7eb2e8f9f7	3125	#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U) /!< /
<>	144:ef7eb2e8f9f7	3126	#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U) /!< /
<>	144:ef7eb2e8f9f7	3127	#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U) /!< /
<>	144:ef7eb2e8f9f7	3128	#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U) /!< /
<>	144:ef7eb2e8f9f7	3129	#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U) /!< /
<>	144:ef7eb2e8f9f7	3130	#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U) /!< /
<>	144:ef7eb2e8f9f7	3131	#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U) /!< /
<>	144:ef7eb2e8f9f7	3132	#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U) /!< /
<>	144:ef7eb2e8f9f7	3133	#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U) /!< /
<>	144:ef7eb2e8f9f7	3134	#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U) /!< /
<>	144:ef7eb2e8f9f7	3135	#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U) /!< /
<>	144:ef7eb2e8f9f7	3136	#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U) /!< /
<>	144:ef7eb2e8f9f7	3137	#define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040U) /!< /
<>	144:ef7eb2e8f9f7	3138	#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020U) /!< /
<>	144:ef7eb2e8f9f7	3139	#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U) /!< /
<>	144:ef7eb2e8f9f7	3140	#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U) /!< /
<>	144:ef7eb2e8f9f7	3141	#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U) /!< /
<>	144:ef7eb2e8f9f7	3142	#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U) /!< /
<>	144:ef7eb2e8f9f7	3143	#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U) /!< /
<>	144:ef7eb2e8f9f7	3144
<>	144:ef7eb2e8f9f7	3145	/****************** Bits definition for RTC_ALRMASSR register ***********/
<>	144:ef7eb2e8f9f7	3146	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U)
<>	144:ef7eb2e8f9f7	3147	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U)
<>	144:ef7eb2e8f9f7	3148	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U)
<>	144:ef7eb2e8f9f7	3149	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U)
<>	144:ef7eb2e8f9f7	3150	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U)
<>	144:ef7eb2e8f9f7	3151	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU)
<>	144:ef7eb2e8f9f7	3152
<>	144:ef7eb2e8f9f7	3153	/****************** Bits definition for RTC_ALRMBSSR register ***********/
<>	144:ef7eb2e8f9f7	3154	#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U)
<>	144:ef7eb2e8f9f7	3155	#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U)
<>	144:ef7eb2e8f9f7	3156	#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U)
<>	144:ef7eb2e8f9f7	3157	#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U)
<>	144:ef7eb2e8f9f7	3158	#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U)
<>	144:ef7eb2e8f9f7	3159	#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU)
<>	144:ef7eb2e8f9f7	3160
<>	144:ef7eb2e8f9f7	3161	/****************** Bits definition for RTC_OR register **************/
<>	144:ef7eb2e8f9f7	3162	#define RTC_OR_OUT_RMP ((uint32_t)0x00000002U) /!< /
<>	144:ef7eb2e8f9f7	3163	#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U) /!< /
<>	144:ef7eb2e8f9f7	3164
<>	144:ef7eb2e8f9f7	3165	/* Legacy defines */
<>	144:ef7eb2e8f9f7	3166	#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
<>	144:ef7eb2e8f9f7	3167
<>	144:ef7eb2e8f9f7	3168	/****************** Bits definition for RTC_BKP0R register **************/
<>	144:ef7eb2e8f9f7	3169	#define RTC_BKP0R ((uint32_t)0xFFFFFFFFU) /!< /
<>	144:ef7eb2e8f9f7	3170
<>	144:ef7eb2e8f9f7	3171	/****************** Bits definition for RTC_BKP1R register **************/
<>	144:ef7eb2e8f9f7	3172	#define RTC_BKP1R ((uint32_t)0xFFFFFFFFU) /!< /
<>	144:ef7eb2e8f9f7	3173
<>	144:ef7eb2e8f9f7	3174	/****************** Bits definition for RTC_BKP2R register **************/
<>	144:ef7eb2e8f9f7	3175	#define RTC_BKP2R ((uint32_t)0xFFFFFFFFU) /!< /
<>	144:ef7eb2e8f9f7	3176
<>	144:ef7eb2e8f9f7	3177	/****************** Bits definition for RTC_BKP3R register **************/
<>	144:ef7eb2e8f9f7	3178	#define RTC_BKP3R ((uint32_t)0xFFFFFFFFU) /!< /
<>	144:ef7eb2e8f9f7	3179
<>	144:ef7eb2e8f9f7	3180	/****************** Bits definition for RTC_BKP4R register **************/
<>	144:ef7eb2e8f9f7	3181	#define RTC_BKP4R ((uint32_t)0xFFFFFFFFU) /!< /
<>	144:ef7eb2e8f9f7	3182
<>	144:ef7eb2e8f9f7	3183	/****************** Number of backup registers ****************************/
<>	144:ef7eb2e8f9f7	3184	#define RTC_BKP_NUMBER ((uint32_t)0x00000005U) /!< /
<>	144:ef7eb2e8f9f7	3185
<>	144:ef7eb2e8f9f7	3186	/******************************************************************************/
<>	144:ef7eb2e8f9f7	3187	/* */
<>	144:ef7eb2e8f9f7	3188	/* Serial Peripheral Interface (SPI) */
<>	144:ef7eb2e8f9f7	3189	/* */
<>	144:ef7eb2e8f9f7	3190	/******************************************************************************/
<>	144:ef7eb2e8f9f7	3191	/***************** Bit definition for SPI_CR1 register ******************/
<>	144:ef7eb2e8f9f7	3192	#define SPI_CR1_CPHA ((uint32_t)0x00000001U) /!< Clock Phase /
<>	144:ef7eb2e8f9f7	3193	#define SPI_CR1_CPOL ((uint32_t)0x00000002U) /!< Clock Polarity /
<>	144:ef7eb2e8f9f7	3194	#define SPI_CR1_MSTR ((uint32_t)0x00000004U) /!< Master Selection /
<>	144:ef7eb2e8f9f7	3195	#define SPI_CR1_BR ((uint32_t)0x00000038U) /!< BR[2:0] bits (Baud Rate Control) /
<>	144:ef7eb2e8f9f7	3196	#define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	3197	#define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	3198	#define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	3199	#define SPI_CR1_SPE ((uint32_t)0x00000040U) /!< SPI Enable /
<>	144:ef7eb2e8f9f7	3200	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /!< Frame Format /
<>	144:ef7eb2e8f9f7	3201	#define SPI_CR1_SSI ((uint32_t)0x00000100U) /!< Internal slave select /
<>	144:ef7eb2e8f9f7	3202	#define SPI_CR1_SSM ((uint32_t)0x00000200U) /!< Software slave management /
<>	144:ef7eb2e8f9f7	3203	#define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /!< Receive only /
<>	144:ef7eb2e8f9f7	3204	#define SPI_CR1_DFF ((uint32_t)0x00000800U) /!< Data Frame Format /
<>	144:ef7eb2e8f9f7	3205	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /!< Transmit CRC next /
<>	144:ef7eb2e8f9f7	3206	#define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /!< Hardware CRC calculation enable /
<>	144:ef7eb2e8f9f7	3207	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /!< Output enable in bidirectional mode /
<>	144:ef7eb2e8f9f7	3208	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /!< Bidirectional data mode enable /
<>	144:ef7eb2e8f9f7	3209
<>	144:ef7eb2e8f9f7	3210	/***************** Bit definition for SPI_CR2 register ******************/
<>	144:ef7eb2e8f9f7	3211	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /!< Rx Buffer DMA Enable /
<>	144:ef7eb2e8f9f7	3212	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /!< Tx Buffer DMA Enable /
<>	144:ef7eb2e8f9f7	3213	#define SPI_CR2_SSOE ((uint32_t)0x00000004U) /!< SS Output Enable /
<>	144:ef7eb2e8f9f7	3214	#define SPI_CR2_FRF ((uint32_t)0x00000010U) /!< Frame Format Enable /
<>	144:ef7eb2e8f9f7	3215	#define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /!< Error Interrupt Enable /
<>	144:ef7eb2e8f9f7	3216	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /!< RX buffer Not Empty Interrupt Enable /
<>	144:ef7eb2e8f9f7	3217	#define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /!< Tx buffer Empty Interrupt Enable /
<>	144:ef7eb2e8f9f7	3218
<>	144:ef7eb2e8f9f7	3219	/****************** Bit definition for SPI_SR register ******************/
<>	144:ef7eb2e8f9f7	3220	#define SPI_SR_RXNE ((uint32_t)0x00000001U) /!< Receive buffer Not Empty /
<>	144:ef7eb2e8f9f7	3221	#define SPI_SR_TXE ((uint32_t)0x00000002U) /!< Transmit buffer Empty /
<>	144:ef7eb2e8f9f7	3222	#define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /!< Channel side /
<>	144:ef7eb2e8f9f7	3223	#define SPI_SR_UDR ((uint32_t)0x00000008U) /!< Underrun flag /
<>	144:ef7eb2e8f9f7	3224	#define SPI_SR_CRCERR ((uint32_t)0x00000010U) /!< CRC Error flag /
<>	144:ef7eb2e8f9f7	3225	#define SPI_SR_MODF ((uint32_t)0x00000020U) /!< Mode fault /
<>	144:ef7eb2e8f9f7	3226	#define SPI_SR_OVR ((uint32_t)0x00000040U) /!< Overrun flag /
<>	144:ef7eb2e8f9f7	3227	#define SPI_SR_BSY ((uint32_t)0x00000080U) /!< Busy flag /
<>	144:ef7eb2e8f9f7	3228	#define SPI_SR_FRE ((uint32_t)0x00000100U) /!< TI frame format error /
<>	144:ef7eb2e8f9f7	3229
<>	144:ef7eb2e8f9f7	3230	/****************** Bit definition for SPI_DR register ******************/
<>	144:ef7eb2e8f9f7	3231	#define SPI_DR_DR ((uint32_t)0x0000FFFFU) /!< Data Register /
<>	144:ef7eb2e8f9f7	3232
<>	144:ef7eb2e8f9f7	3233	/***************** Bit definition for SPI_CRCPR register ****************/
<>	144:ef7eb2e8f9f7	3234	#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /!< CRC polynomial register /
<>	144:ef7eb2e8f9f7	3235
<>	144:ef7eb2e8f9f7	3236	/**************** Bit definition for SPI_RXCRCR register ****************/
<>	144:ef7eb2e8f9f7	3237	#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /!< Rx CRC Register /
<>	144:ef7eb2e8f9f7	3238
<>	144:ef7eb2e8f9f7	3239	/**************** Bit definition for SPI_TXCRCR register ****************/
<>	144:ef7eb2e8f9f7	3240	#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /!< Tx CRC Register /
<>	144:ef7eb2e8f9f7	3241
<>	144:ef7eb2e8f9f7	3242	/**************** Bit definition for SPI_I2SCFGR register ***************/
<>	144:ef7eb2e8f9f7	3243	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001U) /!<Channel length (number of bits per audio channel) /
<>	144:ef7eb2e8f9f7	3244	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006U) /!<DATLEN[1:0] bits (Data length to be transferred) /
<>	144:ef7eb2e8f9f7	3245	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3246	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3247	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008U) /!<steady state clock polarity /
<>	144:ef7eb2e8f9f7	3248	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030U) /!<I2SSTD[1:0] bits (I2S standard selection) /
<>	144:ef7eb2e8f9f7	3249	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3250	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3251	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080U) /!<PCM frame synchronization /
<>	144:ef7eb2e8f9f7	3252	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300U) /!<I2SCFG[1:0] bits (I2S configuration mode) /
<>	144:ef7eb2e8f9f7	3253	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3254	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3255	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400U) /!<I2S Enable /
<>	144:ef7eb2e8f9f7	3256	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800U) /!<I2S mode selection /
<>	144:ef7eb2e8f9f7	3257	#define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000U) /!<Asynchronous start enable /
<>	144:ef7eb2e8f9f7	3258	/**************** Bit definition for SPI_I2SPR register *****************/
<>	144:ef7eb2e8f9f7	3259	#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FFU) /!<I2S Linear prescaler /
<>	144:ef7eb2e8f9f7	3260	#define SPI_I2SPR_ODD ((uint32_t)0x00000100U) /!<Odd factor for the prescaler /
<>	144:ef7eb2e8f9f7	3261	#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200U) /!<Master Clock Output Enable /
<>	144:ef7eb2e8f9f7	3262
<>	144:ef7eb2e8f9f7	3263	/******************************************************************************/
<>	144:ef7eb2e8f9f7	3264	/* */
<>	144:ef7eb2e8f9f7	3265	/* System Configuration (SYSCFG) */
<>	144:ef7eb2e8f9f7	3266	/* */
<>	144:ef7eb2e8f9f7	3267	/******************************************************************************/
<>	144:ef7eb2e8f9f7	3268	/*************** Bit definition for SYSCFG_CFGR1 register **************/
<>	144:ef7eb2e8f9f7	3269	#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003U) /!< SYSCFG_Memory Remap Config /
<>	144:ef7eb2e8f9f7	3270	#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001U) /!< SYSCFG_Memory Remap Config Bit 0 /
<>	144:ef7eb2e8f9f7	3271	#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002U) /!< SYSCFG_Memory Remap Config Bit 1 /
<>	144:ef7eb2e8f9f7	3272	#define SYSCFG_CFGR1_UFB ((uint32_t)0x00000008U) /!< User bank swapping /
<>	144:ef7eb2e8f9f7	3273	#define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300U) /!< SYSCFG_Boot mode Config /
<>	144:ef7eb2e8f9f7	3274	#define SYSCFG_CFGR1_BOOT_MODE_0 ((uint32_t)0x00000100U) /!< SYSCFG_Boot mode Config Bit 0 /
<>	144:ef7eb2e8f9f7	3275	#define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200U) /!< SYSCFG_Boot mode Config Bit 1 /
<>	144:ef7eb2e8f9f7	3276
<>	144:ef7eb2e8f9f7	3277	/*************** Bit definition for SYSCFG_CFGR2 register **************/
<>	144:ef7eb2e8f9f7	3278	#define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001U) /!< Firewall disable bit /
<>	144:ef7eb2e8f9f7	3279	#define SYSCFG_CFGR2_CAPA ((uint32_t)0x0000003EU) /!< Connection of internal Vlcd rail to external capacitors /
<>	144:ef7eb2e8f9f7	3280	#define SYSCFG_CFGR2_CAPA_0 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	3281	#define SYSCFG_CFGR2_CAPA_1 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	3282	#define SYSCFG_CFGR2_CAPA_2 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	3283	#define SYSCFG_CFGR2_CAPA_3 ((uint32_t)0x00000010U)
<>	144:ef7eb2e8f9f7	3284	#define SYSCFG_CFGR2_CAPA_4 ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	3285	#define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100U) /!< I2C PB6 Fast mode plus /
<>	144:ef7eb2e8f9f7	3286	#define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200U) /!< I2C PB7 Fast mode plus /
<>	144:ef7eb2e8f9f7	3287	#define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400U) /!< I2C PB8 Fast mode plus /
<>	144:ef7eb2e8f9f7	3288	#define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800U) /!< I2C PB9 Fast mode plus /
<>	144:ef7eb2e8f9f7	3289	#define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000U) /!< I2C1 Fast mode plus /
<>	144:ef7eb2e8f9f7	3290	#define SYSCFG_CFGR2_I2C2_FMP ((uint32_t)0x00002000U) /!< I2C2 Fast mode plus /
<>	144:ef7eb2e8f9f7	3291	#define SYSCFG_CFGR2_I2C3_FMP ((uint32_t)0x00004000U) /!< I2C3 Fast mode plus /
<>	144:ef7eb2e8f9f7	3292
<>	144:ef7eb2e8f9f7	3293	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
<>	144:ef7eb2e8f9f7	3294	#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000FU) /!< EXTI 0 configuration /
<>	144:ef7eb2e8f9f7	3295	#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0U) /!< EXTI 1 configuration /
<>	144:ef7eb2e8f9f7	3296	#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00U) /!< EXTI 2 configuration /
<>	144:ef7eb2e8f9f7	3297	#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000U) /!< EXTI 3 configuration /
<>	144:ef7eb2e8f9f7	3298
<>	144:ef7eb2e8f9f7	3299	/**
<>	144:ef7eb2e8f9f7	3300	* @brief EXTI0 configuration
<>	144:ef7eb2e8f9f7	3301	*/
<>	144:ef7eb2e8f9f7	3302	#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /!< PA[0] pin /
<>	144:ef7eb2e8f9f7	3303	#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /!< PB[0] pin /
<>	144:ef7eb2e8f9f7	3304	#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /!< PC[0] pin /
<>	144:ef7eb2e8f9f7	3305	#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003U) /!< PD[0] pin /
<>	144:ef7eb2e8f9f7	3306	#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004U) /!< PE[0] pin /
<>	144:ef7eb2e8f9f7	3307	#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005U) /!< PH[0] pin /
<>	144:ef7eb2e8f9f7	3308
<>	144:ef7eb2e8f9f7	3309	/**
<>	144:ef7eb2e8f9f7	3310	* @brief EXTI1 configuration
<>	144:ef7eb2e8f9f7	3311	*/
<>	144:ef7eb2e8f9f7	3312	#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /!< PA[1] pin /
<>	144:ef7eb2e8f9f7	3313	#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /!< PB[1] pin /
<>	144:ef7eb2e8f9f7	3314	#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /!< PC[1] pin /
<>	144:ef7eb2e8f9f7	3315	#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030U) /!< PD[1] pin /
<>	144:ef7eb2e8f9f7	3316	#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040U) /!< PE[1] pin /
<>	144:ef7eb2e8f9f7	3317	#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050U) /!< PH[1] pin /
<>	144:ef7eb2e8f9f7	3318
<>	144:ef7eb2e8f9f7	3319	/**
<>	144:ef7eb2e8f9f7	3320	* @brief EXTI2 configuration
<>	144:ef7eb2e8f9f7	3321	*/
<>	144:ef7eb2e8f9f7	3322	#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /!< PA[2] pin /
<>	144:ef7eb2e8f9f7	3323	#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /!< PB[2] pin /
<>	144:ef7eb2e8f9f7	3324	#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /!< PC[2] pin /
<>	144:ef7eb2e8f9f7	3325	#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /!< PD[2] pin /
<>	144:ef7eb2e8f9f7	3326	#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400U) /!< PE[2] pin /
<>	144:ef7eb2e8f9f7	3327
<>	144:ef7eb2e8f9f7	3328	/**
<>	144:ef7eb2e8f9f7	3329	* @brief EXTI3 configuration
<>	144:ef7eb2e8f9f7	3330	*/
<>	144:ef7eb2e8f9f7	3331	#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /!< PA[3] pin /
<>	144:ef7eb2e8f9f7	3332	#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /!< PB[3] pin /
<>	144:ef7eb2e8f9f7	3333	#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /!< PC[3] pin /
<>	144:ef7eb2e8f9f7	3334	#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000U) /!< PD[3] pin /
<>	144:ef7eb2e8f9f7	3335	#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000U) /!< PE[3] pin /
<>	144:ef7eb2e8f9f7	3336
<>	144:ef7eb2e8f9f7	3337	/*************** Bit definition for SYSCFG_EXTICR2 register ***************/
<>	144:ef7eb2e8f9f7	3338	#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000FU) /!< EXTI 4 configuration /
<>	144:ef7eb2e8f9f7	3339	#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0U) /!< EXTI 5 configuration /
<>	144:ef7eb2e8f9f7	3340	#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00U) /!< EXTI 6 configuration /
<>	144:ef7eb2e8f9f7	3341	#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000U) /!< EXTI 7 configuration /
<>	144:ef7eb2e8f9f7	3342
<>	144:ef7eb2e8f9f7	3343	/**
<>	144:ef7eb2e8f9f7	3344	* @brief EXTI4 configuration
<>	144:ef7eb2e8f9f7	3345	*/
<>	144:ef7eb2e8f9f7	3346	#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /!< PA[4] pin /
<>	144:ef7eb2e8f9f7	3347	#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /!< PB[4] pin /
<>	144:ef7eb2e8f9f7	3348	#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /!< PC[4] pin /
<>	144:ef7eb2e8f9f7	3349	#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003U) /!< PD[4] pin /
<>	144:ef7eb2e8f9f7	3350	#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004U) /!< PE[4] pin /
<>	144:ef7eb2e8f9f7	3351
<>	144:ef7eb2e8f9f7	3352	/**
<>	144:ef7eb2e8f9f7	3353	* @brief EXTI5 configuration
<>	144:ef7eb2e8f9f7	3354	*/
<>	144:ef7eb2e8f9f7	3355	#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /!< PA[5] pin /
<>	144:ef7eb2e8f9f7	3356	#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /!< PB[5] pin /
<>	144:ef7eb2e8f9f7	3357	#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /!< PC[5] pin /
<>	144:ef7eb2e8f9f7	3358	#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030U) /!< PD[5] pin /
<>	144:ef7eb2e8f9f7	3359	#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040U) /!< PE[5] pin /
<>	144:ef7eb2e8f9f7	3360
<>	144:ef7eb2e8f9f7	3361	/**
<>	144:ef7eb2e8f9f7	3362	* @brief EXTI6 configuration
<>	144:ef7eb2e8f9f7	3363	*/
<>	144:ef7eb2e8f9f7	3364	#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /!< PA[6] pin /
<>	144:ef7eb2e8f9f7	3365	#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /!< PB[6] pin /
<>	144:ef7eb2e8f9f7	3366	#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /!< PC[6] pin /
<>	144:ef7eb2e8f9f7	3367	#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300U) /!< PD[6] pin /
<>	144:ef7eb2e8f9f7	3368	#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400U) /!< PE[6] pin /
<>	144:ef7eb2e8f9f7	3369
<>	144:ef7eb2e8f9f7	3370	/**
<>	144:ef7eb2e8f9f7	3371	* @brief EXTI7 configuration
<>	144:ef7eb2e8f9f7	3372	*/
<>	144:ef7eb2e8f9f7	3373	#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /!< PA[7] pin /
<>	144:ef7eb2e8f9f7	3374	#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /!< PB[7] pin /
<>	144:ef7eb2e8f9f7	3375	#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /!< PC[7] pin /
<>	144:ef7eb2e8f9f7	3376	#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000U) /!< PD[7] pin /
<>	144:ef7eb2e8f9f7	3377	#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000U) /!< PE[7] pin /
<>	144:ef7eb2e8f9f7	3378
<>	144:ef7eb2e8f9f7	3379	/*************** Bit definition for SYSCFG_EXTICR3 register ***************/
<>	144:ef7eb2e8f9f7	3380	#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000FU) /!< EXTI 8 configuration /
<>	144:ef7eb2e8f9f7	3381	#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0U) /!< EXTI 9 configuration /
<>	144:ef7eb2e8f9f7	3382	#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00U) /!< EXTI 10 configuration /
<>	144:ef7eb2e8f9f7	3383	#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000U) /!< EXTI 11 configuration /
<>	144:ef7eb2e8f9f7	3384
<>	144:ef7eb2e8f9f7	3385	/**
<>	144:ef7eb2e8f9f7	3386	* @brief EXTI8 configuration
<>	144:ef7eb2e8f9f7	3387	*/
<>	144:ef7eb2e8f9f7	3388	#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /!< PA[8] pin /
<>	144:ef7eb2e8f9f7	3389	#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /!< PB[8] pin /
<>	144:ef7eb2e8f9f7	3390	#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /!< PC[8] pin /
<>	144:ef7eb2e8f9f7	3391	#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003U) /!< PD[8] pin /
<>	144:ef7eb2e8f9f7	3392	#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004U) /!< PE[8] pin /
<>	144:ef7eb2e8f9f7	3393
<>	144:ef7eb2e8f9f7	3394	/**
<>	144:ef7eb2e8f9f7	3395	* @brief EXTI9 configuration
<>	144:ef7eb2e8f9f7	3396	*/
<>	144:ef7eb2e8f9f7	3397	#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /!< PA[9] pin /
<>	144:ef7eb2e8f9f7	3398	#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /!< PB[9] pin /
<>	144:ef7eb2e8f9f7	3399	#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /!< PC[9] pin /
<>	144:ef7eb2e8f9f7	3400	#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030U) /!< PD[9] pin /
<>	144:ef7eb2e8f9f7	3401	#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040U) /!< PE[9] pin /
<>	144:ef7eb2e8f9f7	3402	#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000050U) /!< PH[9] pin /
<>	144:ef7eb2e8f9f7	3403
<>	144:ef7eb2e8f9f7	3404	/**
<>	144:ef7eb2e8f9f7	3405	* @brief EXTI10 configuration
<>	144:ef7eb2e8f9f7	3406	*/
<>	144:ef7eb2e8f9f7	3407	#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /!< PA[10] pin /
<>	144:ef7eb2e8f9f7	3408	#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /!< PB[10] pin /
<>	144:ef7eb2e8f9f7	3409	#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /!< PC[10] pin /
<>	144:ef7eb2e8f9f7	3410	#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300U) /!< PD[10] pin /
<>	144:ef7eb2e8f9f7	3411	#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400U) /!< PE[10] pin /
<>	144:ef7eb2e8f9f7	3412	#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000500U) /!< PH[10] pin /
<>	144:ef7eb2e8f9f7	3413
<>	144:ef7eb2e8f9f7	3414	/**
<>	144:ef7eb2e8f9f7	3415	* @brief EXTI11 configuration
<>	144:ef7eb2e8f9f7	3416	*/
<>	144:ef7eb2e8f9f7	3417	#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /!< PA[11] pin /
<>	144:ef7eb2e8f9f7	3418	#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /!< PB[11] pin /
<>	144:ef7eb2e8f9f7	3419	#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /!< PC[11] pin /
<>	144:ef7eb2e8f9f7	3420	#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000U) /!< PD[11] pin /
<>	144:ef7eb2e8f9f7	3421	#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000U) /!< PE[11] pin /
<>	144:ef7eb2e8f9f7	3422
<>	144:ef7eb2e8f9f7	3423	/*************** Bit definition for SYSCFG_EXTICR4 register ***************/
<>	144:ef7eb2e8f9f7	3424	#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000FU) /!< EXTI 12 configuration /
<>	144:ef7eb2e8f9f7	3425	#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0U) /!< EXTI 13 configuration /
<>	144:ef7eb2e8f9f7	3426	#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00U) /!< EXTI 14 configuration /
<>	144:ef7eb2e8f9f7	3427	#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000U) /!< EXTI 15 configuration /
<>	144:ef7eb2e8f9f7	3428
<>	144:ef7eb2e8f9f7	3429	/**
<>	144:ef7eb2e8f9f7	3430	* @brief EXTI12 configuration
<>	144:ef7eb2e8f9f7	3431	*/
<>	144:ef7eb2e8f9f7	3432	#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /!< PA[12] pin /
<>	144:ef7eb2e8f9f7	3433	#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /!< PB[12] pin /
<>	144:ef7eb2e8f9f7	3434	#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /!< PC[12] pin /
<>	144:ef7eb2e8f9f7	3435	#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003U) /!< PD[12] pin /
<>	144:ef7eb2e8f9f7	3436	#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004U) /!< PE[12] pin /
<>	144:ef7eb2e8f9f7	3437
<>	144:ef7eb2e8f9f7	3438	/**
<>	144:ef7eb2e8f9f7	3439	* @brief EXTI13 configuration
<>	144:ef7eb2e8f9f7	3440	*/
<>	144:ef7eb2e8f9f7	3441	#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /!< PA[13] pin /
<>	144:ef7eb2e8f9f7	3442	#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /!< PB[13] pin /
<>	144:ef7eb2e8f9f7	3443	#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /!< PC[13] pin /
<>	144:ef7eb2e8f9f7	3444	#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030U) /!< PD[13] pin /
<>	144:ef7eb2e8f9f7	3445	#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040U) /!< PE[13] pin /
<>	144:ef7eb2e8f9f7	3446
<>	144:ef7eb2e8f9f7	3447	/**
<>	144:ef7eb2e8f9f7	3448	* @brief EXTI14 configuration
<>	144:ef7eb2e8f9f7	3449	*/
<>	144:ef7eb2e8f9f7	3450	#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /!< PA[14] pin /
<>	144:ef7eb2e8f9f7	3451	#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /!< PB[14] pin /
<>	144:ef7eb2e8f9f7	3452	#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /!< PC[14] pin /
<>	144:ef7eb2e8f9f7	3453	#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300U) /!< PD[14] pin /
<>	144:ef7eb2e8f9f7	3454	#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400U) /!< PE[14] pin /
<>	144:ef7eb2e8f9f7	3455
<>	144:ef7eb2e8f9f7	3456	/**
<>	144:ef7eb2e8f9f7	3457	* @brief EXTI15 configuration
<>	144:ef7eb2e8f9f7	3458	*/
<>	144:ef7eb2e8f9f7	3459	#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /!< PA[15] pin /
<>	144:ef7eb2e8f9f7	3460	#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /!< PB[15] pin /
<>	144:ef7eb2e8f9f7	3461	#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /!< PC[15] pin /
<>	144:ef7eb2e8f9f7	3462	#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000U) /!< PD[15] pin /
<>	144:ef7eb2e8f9f7	3463	#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000U) /!< PE[15] pin /
<>	144:ef7eb2e8f9f7	3464
<>	144:ef7eb2e8f9f7	3465
<>	144:ef7eb2e8f9f7	3466	/*************** Bit definition for SYSCFG_CFGR3 register **************/
<>	144:ef7eb2e8f9f7	3467	#define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001U) /!< Vref Enable bit/
<>	144:ef7eb2e8f9f7	3468	#define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030U) /!< Verf_ADC connection bit /
<>	144:ef7eb2e8f9f7	3469	#define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	3470	#define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	3471	#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100U) /!< VREFINT reference for ADC enable bit /
<>	144:ef7eb2e8f9f7	3472	#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200U) /!< Sensor reference for ADC enable bit /
<>	144:ef7eb2e8f9f7	3473	#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000U) /!< VREFINT reference for comparator 2 enable bit /
<>	144:ef7eb2e8f9f7	3474	#define SYSCFG_CFGR3_ENREF_HSI48 ((uint32_t)0x00002000U) /!< VREFINT reference or 48 MHz RC oscillator enable bit /
<>	144:ef7eb2e8f9f7	3475	#define SYSCFG_CFGR3_REF_HSI48_RDYF ((uint32_t)0x04000000U) /!< VREFINT for 48 MHz RC oscillator ready flag /
<>	144:ef7eb2e8f9f7	3476	#define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000U) /!< Sensor for ADC ready flag /
<>	144:ef7eb2e8f9f7	3477	#define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000U) /!< VREFINT for ADC ready flag /
<>	144:ef7eb2e8f9f7	3478	#define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000U) /!< VREFINT for comparator ready flag /
<>	144:ef7eb2e8f9f7	3479	#define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000U) /!< VREFINT ready flag /
<>	144:ef7eb2e8f9f7	3480	#define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000U) /!< CFGR3 lock bit /
<>	144:ef7eb2e8f9f7	3481
<>	144:ef7eb2e8f9f7	3482	/* Legacy defines */
<>	144:ef7eb2e8f9f7	3483
<>	144:ef7eb2e8f9f7	3484	#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
<>	144:ef7eb2e8f9f7	3485	#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
<>	144:ef7eb2e8f9f7	3486	#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
<>	144:ef7eb2e8f9f7	3487	#define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
<>	144:ef7eb2e8f9f7	3488	#define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_REF_HSI48_RDYF
<>	144:ef7eb2e8f9f7	3489	#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_ADC_RDYF
<>	144:ef7eb2e8f9f7	3490
<>	144:ef7eb2e8f9f7	3491	/******************************************************************************/
<>	144:ef7eb2e8f9f7	3492	/* */
<>	144:ef7eb2e8f9f7	3493	/* Timers (TIM) */
<>	144:ef7eb2e8f9f7	3494	/* */
<>	144:ef7eb2e8f9f7	3495	/******************************************************************************/
<>	144:ef7eb2e8f9f7	3496	/*
<>	144:ef7eb2e8f9f7	3497	* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
<>	144:ef7eb2e8f9f7	3498	*/
<>	144:ef7eb2e8f9f7	3499	#if defined (STM32L071xx) \|\| defined (STM32L072xx) \|\| defined (STM32L073xx) \
<>	144:ef7eb2e8f9f7	3500	\|\| defined (STM32L081xx) \|\| defined (STM32L082xx) \|\| defined (STM32L083xx)
<>	144:ef7eb2e8f9f7	3501	#define TIM_TIM2_REMAP_HSI_SUPPORT /!<Support remap HSI on TIM2 /
<>	144:ef7eb2e8f9f7	3502	#define TIM_TIM2_REMAP_HSI48_SUPPORT /!<Support remap HSI48 on TIM2 /
<>	144:ef7eb2e8f9f7	3503	#else
<>	144:ef7eb2e8f9f7	3504	#define TIM_TIM2_REMAP_HSI48_SUPPORT /!<Support remap HSI48 on TIM2 /
<>	144:ef7eb2e8f9f7	3505	#endif
<>	144:ef7eb2e8f9f7	3506
<>	144:ef7eb2e8f9f7	3507	/***************** Bit definition for TIM_CR1 register ******************/
<>	144:ef7eb2e8f9f7	3508	#define TIM_CR1_CEN ((uint32_t)0x00000001U) /!<Counter enable /
<>	144:ef7eb2e8f9f7	3509	#define TIM_CR1_UDIS ((uint32_t)0x00000002U) /!<Update disable /
<>	144:ef7eb2e8f9f7	3510	#define TIM_CR1_URS ((uint32_t)0x00000004U) /!<Update request source /
<>	144:ef7eb2e8f9f7	3511	#define TIM_CR1_OPM ((uint32_t)0x00000008U) /!<One pulse mode /
<>	144:ef7eb2e8f9f7	3512	#define TIM_CR1_DIR ((uint32_t)0x00000010U) /!<Direction /
<>	144:ef7eb2e8f9f7	3513
<>	144:ef7eb2e8f9f7	3514	#define TIM_CR1_CMS ((uint32_t)0x00000060U) /!<CMS[1:0] bits (Center-aligned mode selection) /
<>	144:ef7eb2e8f9f7	3515	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3516	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3517
<>	144:ef7eb2e8f9f7	3518	#define TIM_CR1_ARPE ((uint32_t)0x00000080U) /!<Auto-reload preload enable /
<>	144:ef7eb2e8f9f7	3519
<>	144:ef7eb2e8f9f7	3520	#define TIM_CR1_CKD ((uint32_t)0x00000300U) /!<CKD[1:0] bits (clock division) /
<>	144:ef7eb2e8f9f7	3521	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3522	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3523
<>	144:ef7eb2e8f9f7	3524	/***************** Bit definition for TIM_CR2 register ******************/
<>	144:ef7eb2e8f9f7	3525	#define TIM_CR2_CCDS ((uint32_t)0x00000008U) /!<Capture/Compare DMA Selection /
<>	144:ef7eb2e8f9f7	3526
<>	144:ef7eb2e8f9f7	3527	#define TIM_CR2_MMS ((uint32_t)0x00000070U) /!<MMS[2:0] bits (Master Mode Selection) /
<>	144:ef7eb2e8f9f7	3528	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3529	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3530	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3531
<>	144:ef7eb2e8f9f7	3532	#define TIM_CR2_TI1S ((uint32_t)0x00000080U) /!<TI1 Selection /
<>	144:ef7eb2e8f9f7	3533
<>	144:ef7eb2e8f9f7	3534	/***************** Bit definition for TIM_SMCR register *****************/
<>	144:ef7eb2e8f9f7	3535	#define TIM_SMCR_SMS ((uint32_t)0x00000007U) /!<SMS[2:0] bits (Slave mode selection) /
<>	144:ef7eb2e8f9f7	3536	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3537	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3538	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3539
<>	144:ef7eb2e8f9f7	3540	#define TIM_SMCR_OCCS ((uint32_t)0x00000008U) /!< OCREF clear selection /
<>	144:ef7eb2e8f9f7	3541
<>	144:ef7eb2e8f9f7	3542	#define TIM_SMCR_TS ((uint32_t)0x00000070U) /!<TS[2:0] bits (Trigger selection) /
<>	144:ef7eb2e8f9f7	3543	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3544	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3545	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3546
<>	144:ef7eb2e8f9f7	3547	#define TIM_SMCR_MSM ((uint32_t)0x00000080U) /!<Master/slave mode /
<>	144:ef7eb2e8f9f7	3548
<>	144:ef7eb2e8f9f7	3549	#define TIM_SMCR_ETF ((uint32_t)0x00000F00U) /!<ETF[3:0] bits (External trigger filter) /
<>	144:ef7eb2e8f9f7	3550	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3551	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3552	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3553	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800U) /!<Bit 3 /
<>	144:ef7eb2e8f9f7	3554
<>	144:ef7eb2e8f9f7	3555	#define TIM_SMCR_ETPS ((uint32_t)0x00003000U) /!<ETPS[1:0] bits (External trigger prescaler) /
<>	144:ef7eb2e8f9f7	3556	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3557	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3558
<>	144:ef7eb2e8f9f7	3559	#define TIM_SMCR_ECE ((uint32_t)0x00004000U) /!<External clock enable /
<>	144:ef7eb2e8f9f7	3560	#define TIM_SMCR_ETP ((uint32_t)0x00008000U) /!<External trigger polarity /
<>	144:ef7eb2e8f9f7	3561
<>	144:ef7eb2e8f9f7	3562	/***************** Bit definition for TIM_DIER register *****************/
<>	144:ef7eb2e8f9f7	3563	#define TIM_DIER_UIE ((uint32_t)0x00000001U) /!<Update interrupt enable /
<>	144:ef7eb2e8f9f7	3564	#define TIM_DIER_CC1IE ((uint32_t)0x00000002U) /!<Capture/Compare 1 interrupt enable /
<>	144:ef7eb2e8f9f7	3565	#define TIM_DIER_CC2IE ((uint32_t)0x00000004U) /!<Capture/Compare 2 interrupt enable /
<>	144:ef7eb2e8f9f7	3566	#define TIM_DIER_CC3IE ((uint32_t)0x00000008U) /!<Capture/Compare 3 interrupt enable /
<>	144:ef7eb2e8f9f7	3567	#define TIM_DIER_CC4IE ((uint32_t)0x00000010U) /!<Capture/Compare 4 interrupt enable /
<>	144:ef7eb2e8f9f7	3568	#define TIM_DIER_TIE ((uint32_t)0x00000040U) /!<Trigger interrupt enable /
<>	144:ef7eb2e8f9f7	3569	#define TIM_DIER_UDE ((uint32_t)0x00000100U) /!<Update DMA request enable /
<>	144:ef7eb2e8f9f7	3570	#define TIM_DIER_CC1DE ((uint32_t)0x00000200U) /!<Capture/Compare 1 DMA request enable /
<>	144:ef7eb2e8f9f7	3571	#define TIM_DIER_CC2DE ((uint32_t)0x00000400U) /!<Capture/Compare 2 DMA request enable /
<>	144:ef7eb2e8f9f7	3572	#define TIM_DIER_CC3DE ((uint32_t)0x00000800U) /!<Capture/Compare 3 DMA request enable /
<>	144:ef7eb2e8f9f7	3573	#define TIM_DIER_CC4DE ((uint32_t)0x00001000U) /!<Capture/Compare 4 DMA request enable /
<>	144:ef7eb2e8f9f7	3574	#define TIM_DIER_TDE ((uint32_t)0x00004000U) /!<Trigger DMA request enable /
<>	144:ef7eb2e8f9f7	3575
<>	144:ef7eb2e8f9f7	3576	/****************** Bit definition for TIM_SR register ******************/
<>	144:ef7eb2e8f9f7	3577	#define TIM_SR_UIF ((uint32_t)0x00000001U) /!<Update interrupt Flag /
<>	144:ef7eb2e8f9f7	3578	#define TIM_SR_CC1IF ((uint32_t)0x00000002U) /!<Capture/Compare 1 interrupt Flag /
<>	144:ef7eb2e8f9f7	3579	#define TIM_SR_CC2IF ((uint32_t)0x00000004U) /!<Capture/Compare 2 interrupt Flag /
<>	144:ef7eb2e8f9f7	3580	#define TIM_SR_CC3IF ((uint32_t)0x00000008U) /!<Capture/Compare 3 interrupt Flag /
<>	144:ef7eb2e8f9f7	3581	#define TIM_SR_CC4IF ((uint32_t)0x00000010U) /!<Capture/Compare 4 interrupt Flag /
<>	144:ef7eb2e8f9f7	3582	#define TIM_SR_TIF ((uint32_t)0x00000040U) /!<Trigger interrupt Flag /
<>	144:ef7eb2e8f9f7	3583	#define TIM_SR_CC1OF ((uint32_t)0x00000200U) /!<Capture/Compare 1 Overcapture Flag /
<>	144:ef7eb2e8f9f7	3584	#define TIM_SR_CC2OF ((uint32_t)0x00000400U) /!<Capture/Compare 2 Overcapture Flag /
<>	144:ef7eb2e8f9f7	3585	#define TIM_SR_CC3OF ((uint32_t)0x00000800U) /!<Capture/Compare 3 Overcapture Flag /
<>	144:ef7eb2e8f9f7	3586	#define TIM_SR_CC4OF ((uint32_t)0x00001000U) /!<Capture/Compare 4 Overcapture Flag /
<>	144:ef7eb2e8f9f7	3587
<>	144:ef7eb2e8f9f7	3588	/***************** Bit definition for TIM_EGR register ******************/
<>	144:ef7eb2e8f9f7	3589	#define TIM_EGR_UG ((uint32_t)0x00000001U) /!<Update Generation /
<>	144:ef7eb2e8f9f7	3590	#define TIM_EGR_CC1G ((uint32_t)0x00000002U) /!<Capture/Compare 1 Generation /
<>	144:ef7eb2e8f9f7	3591	#define TIM_EGR_CC2G ((uint32_t)0x00000004U) /!<Capture/Compare 2 Generation /
<>	144:ef7eb2e8f9f7	3592	#define TIM_EGR_CC3G ((uint32_t)0x00000008U) /!<Capture/Compare 3 Generation /
<>	144:ef7eb2e8f9f7	3593	#define TIM_EGR_CC4G ((uint32_t)0x00000010U) /!<Capture/Compare 4 Generation /
<>	144:ef7eb2e8f9f7	3594	#define TIM_EGR_TG ((uint32_t)0x00000040U) /!<Trigger Generation /
<>	144:ef7eb2e8f9f7	3595
<>	144:ef7eb2e8f9f7	3596	/**************** Bit definition for TIM_CCMR1 register *****************/
<>	144:ef7eb2e8f9f7	3597	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003U) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
<>	144:ef7eb2e8f9f7	3598	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3599	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3600
<>	144:ef7eb2e8f9f7	3601	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004U) /!<Output Compare 1 Fast enable /
<>	144:ef7eb2e8f9f7	3602	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008U) /!<Output Compare 1 Preload enable /
<>	144:ef7eb2e8f9f7	3603
<>	144:ef7eb2e8f9f7	3604	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070U) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
<>	144:ef7eb2e8f9f7	3605	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3606	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3607	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3608
<>	144:ef7eb2e8f9f7	3609	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080U) /!<Output Compare 1Clear Enable /
<>	144:ef7eb2e8f9f7	3610
<>	144:ef7eb2e8f9f7	3611	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300U) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
<>	144:ef7eb2e8f9f7	3612	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3613	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3614
<>	144:ef7eb2e8f9f7	3615	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400U) /!<Output Compare 2 Fast enable /
<>	144:ef7eb2e8f9f7	3616	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800U) /!<Output Compare 2 Preload enable /
<>	144:ef7eb2e8f9f7	3617
<>	144:ef7eb2e8f9f7	3618	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000U) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
<>	144:ef7eb2e8f9f7	3619	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3620	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3621	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3622
<>	144:ef7eb2e8f9f7	3623	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000U) /!<Output Compare 2 Clear Enable /
<>	144:ef7eb2e8f9f7	3624
<>	144:ef7eb2e8f9f7	3625	/----------------------------------------------------------------------------/
<>	144:ef7eb2e8f9f7	3626
<>	144:ef7eb2e8f9f7	3627	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000CU) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
<>	144:ef7eb2e8f9f7	3628	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3629	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3630
<>	144:ef7eb2e8f9f7	3631	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0U) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
<>	144:ef7eb2e8f9f7	3632	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3633	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3634	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3635	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080U) /!<Bit 3 /
<>	144:ef7eb2e8f9f7	3636
<>	144:ef7eb2e8f9f7	3637	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00U) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
<>	144:ef7eb2e8f9f7	3638	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3639	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3640
<>	144:ef7eb2e8f9f7	3641	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000U) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
<>	144:ef7eb2e8f9f7	3642	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3643	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3644	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3645	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000U) /!<Bit 3 /
<>	144:ef7eb2e8f9f7	3646
<>	144:ef7eb2e8f9f7	3647	/**************** Bit definition for TIM_CCMR2 register *****************/
<>	144:ef7eb2e8f9f7	3648	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003U) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
<>	144:ef7eb2e8f9f7	3649	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3650	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3651
<>	144:ef7eb2e8f9f7	3652	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004U) /!<Output Compare 3 Fast enable /
<>	144:ef7eb2e8f9f7	3653	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008U) /!<Output Compare 3 Preload enable /
<>	144:ef7eb2e8f9f7	3654
<>	144:ef7eb2e8f9f7	3655	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070U) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
<>	144:ef7eb2e8f9f7	3656	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3657	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3658	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3659
<>	144:ef7eb2e8f9f7	3660	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080U) /!<Output Compare 3 Clear Enable /
<>	144:ef7eb2e8f9f7	3661
<>	144:ef7eb2e8f9f7	3662	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300U) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
<>	144:ef7eb2e8f9f7	3663	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3664	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3665
<>	144:ef7eb2e8f9f7	3666	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400U) /!<Output Compare 4 Fast enable /
<>	144:ef7eb2e8f9f7	3667	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800U) /!<Output Compare 4 Preload enable /
<>	144:ef7eb2e8f9f7	3668
<>	144:ef7eb2e8f9f7	3669	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000U) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
<>	144:ef7eb2e8f9f7	3670	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3671	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3672	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3673
<>	144:ef7eb2e8f9f7	3674	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000U) /!<Output Compare 4 Clear Enable /
<>	144:ef7eb2e8f9f7	3675
<>	144:ef7eb2e8f9f7	3676	/----------------------------------------------------------------------------/
<>	144:ef7eb2e8f9f7	3677
<>	144:ef7eb2e8f9f7	3678	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000CU) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
<>	144:ef7eb2e8f9f7	3679	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3680	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3681
<>	144:ef7eb2e8f9f7	3682	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0U) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
<>	144:ef7eb2e8f9f7	3683	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3684	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3685	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3686	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080U) /!<Bit 3 /
<>	144:ef7eb2e8f9f7	3687
<>	144:ef7eb2e8f9f7	3688	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00U) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
<>	144:ef7eb2e8f9f7	3689	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3690	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3691
<>	144:ef7eb2e8f9f7	3692	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000U) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
<>	144:ef7eb2e8f9f7	3693	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3694	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3695	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3696	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000U) /!<Bit 3 /
<>	144:ef7eb2e8f9f7	3697
<>	144:ef7eb2e8f9f7	3698	/***************** Bit definition for TIM_CCER register *****************/
<>	144:ef7eb2e8f9f7	3699	#define TIM_CCER_CC1E ((uint32_t)0x00000001U) /!<Capture/Compare 1 output enable /
<>	144:ef7eb2e8f9f7	3700	#define TIM_CCER_CC1P ((uint32_t)0x00000002U) /!<Capture/Compare 1 output Polarity /
<>	144:ef7eb2e8f9f7	3701	#define TIM_CCER_CC1NP ((uint32_t)0x00000008U) /!<Capture/Compare 1 Complementary output Polarity /
<>	144:ef7eb2e8f9f7	3702	#define TIM_CCER_CC2E ((uint32_t)0x00000010U) /!<Capture/Compare 2 output enable /
<>	144:ef7eb2e8f9f7	3703	#define TIM_CCER_CC2P ((uint32_t)0x00000020U) /!<Capture/Compare 2 output Polarity /
<>	144:ef7eb2e8f9f7	3704	#define TIM_CCER_CC2NP ((uint32_t)0x00000080U) /!<Capture/Compare 2 Complementary output Polarity /
<>	144:ef7eb2e8f9f7	3705	#define TIM_CCER_CC3E ((uint32_t)0x00000100U) /!<Capture/Compare 3 output enable /
<>	144:ef7eb2e8f9f7	3706	#define TIM_CCER_CC3P ((uint32_t)0x00000200U) /!<Capture/Compare 3 output Polarity /
<>	144:ef7eb2e8f9f7	3707	#define TIM_CCER_CC3NP ((uint32_t)0x00000800U) /!<Capture/Compare 3 Complementary output Polarity /
<>	144:ef7eb2e8f9f7	3708	#define TIM_CCER_CC4E ((uint32_t)0x00001000U) /!<Capture/Compare 4 output enable /
<>	144:ef7eb2e8f9f7	3709	#define TIM_CCER_CC4P ((uint32_t)0x00002000U) /!<Capture/Compare 4 output Polarity /
<>	144:ef7eb2e8f9f7	3710	#define TIM_CCER_CC4NP ((uint32_t)0x00008000U) /!<Capture/Compare 4 Complementary output Polarity /
<>	144:ef7eb2e8f9f7	3711
<>	144:ef7eb2e8f9f7	3712	/***************** Bit definition for TIM_CNT register ******************/
<>	144:ef7eb2e8f9f7	3713	#define TIM_CNT_CNT ((uint32_t)0x0000FFFFU) /!<Counter Value /
<>	144:ef7eb2e8f9f7	3714
<>	144:ef7eb2e8f9f7	3715	/***************** Bit definition for TIM_PSC register ******************/
<>	144:ef7eb2e8f9f7	3716	#define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /!<Prescaler Value /
<>	144:ef7eb2e8f9f7	3717
<>	144:ef7eb2e8f9f7	3718	/***************** Bit definition for TIM_ARR register ******************/
<>	144:ef7eb2e8f9f7	3719	#define TIM_ARR_ARR ((uint32_t)0x0000FFFFU) /!<actual auto-reload Value /
<>	144:ef7eb2e8f9f7	3720
<>	144:ef7eb2e8f9f7	3721	/***************** Bit definition for TIM_CCR1 register *****************/
<>	144:ef7eb2e8f9f7	3722	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFFU) /!<Capture/Compare 1 Value /
<>	144:ef7eb2e8f9f7	3723
<>	144:ef7eb2e8f9f7	3724	/***************** Bit definition for TIM_CCR2 register *****************/
<>	144:ef7eb2e8f9f7	3725	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFFU) /!<Capture/Compare 2 Value /
<>	144:ef7eb2e8f9f7	3726
<>	144:ef7eb2e8f9f7	3727	/***************** Bit definition for TIM_CCR3 register *****************/
<>	144:ef7eb2e8f9f7	3728	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFFU) /!<Capture/Compare 3 Value /
<>	144:ef7eb2e8f9f7	3729
<>	144:ef7eb2e8f9f7	3730	/***************** Bit definition for TIM_CCR4 register *****************/
<>	144:ef7eb2e8f9f7	3731	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFFU) /!<Capture/Compare 4 Value /
<>	144:ef7eb2e8f9f7	3732
<>	144:ef7eb2e8f9f7	3733	/***************** Bit definition for TIM_DCR register ******************/
<>	144:ef7eb2e8f9f7	3734	#define TIM_DCR_DBA ((uint32_t)0x0000001FU) /!<DBA[4:0] bits (DMA Base Address) /
<>	144:ef7eb2e8f9f7	3735	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3736	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3737	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3738	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008U) /!<Bit 3 /
<>	144:ef7eb2e8f9f7	3739	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010U) /!<Bit 4 /
<>	144:ef7eb2e8f9f7	3740
<>	144:ef7eb2e8f9f7	3741	#define TIM_DCR_DBL ((uint32_t)0x00001F00U) /!<DBL[4:0] bits (DMA Burst Length) /
<>	144:ef7eb2e8f9f7	3742	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3743	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3744	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3745	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800U) /!<Bit 3 /
<>	144:ef7eb2e8f9f7	3746	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000U) /!<Bit 4 /
<>	144:ef7eb2e8f9f7	3747
<>	144:ef7eb2e8f9f7	3748	/***************** Bit definition for TIM_DMAR register *****************/
<>	144:ef7eb2e8f9f7	3749	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFFU) /!<DMA register for burst accesses /
<>	144:ef7eb2e8f9f7	3750
<>	144:ef7eb2e8f9f7	3751	/***************** Bit definition for TIM_OR register *******************/
<>	144:ef7eb2e8f9f7	3752	#define TIM2_OR_ETR_RMP ((uint32_t)0x00000007U) /!<ETR_RMP[1:0] bits (TIM2 ETR remap) /
<>	144:ef7eb2e8f9f7	3753	#define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3754	#define TIM2_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3755	#define TIM2_OR_ETR_RMP_2 ((uint32_t)0x00000004U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3756	#define TIM2_OR_TI4_RMP ((uint32_t)0x0000018) /!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) /
<>	144:ef7eb2e8f9f7	3757	#define TIM2_OR_TI4_RMP_0 ((uint32_t)0x00000008U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3758	#define TIM2_OR_TI4_RMP_1 ((uint32_t)0x00000010U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3759
<>	144:ef7eb2e8f9f7	3760	#define TIM21_OR_ETR_RMP ((uint32_t)0x00000003U) /!<ETR_RMP[1:0] bits (TIM21 ETR remap) /
<>	144:ef7eb2e8f9f7	3761	#define TIM21_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3762	#define TIM21_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3763	#define TIM21_OR_TI1_RMP ((uint32_t)0x0000001CU) /!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) /
<>	144:ef7eb2e8f9f7	3764	#define TIM21_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3765	#define TIM21_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3766	#define TIM21_OR_TI1_RMP_2 ((uint32_t)0x00000010U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3767	#define TIM21_OR_TI2_RMP ((uint32_t)0x00000020U) /!<TI2_RMP bit (TIM21 Input 2 remap) /
<>	144:ef7eb2e8f9f7	3768
<>	144:ef7eb2e8f9f7	3769	#define TIM22_OR_ETR_RMP ((uint32_t)0x00000003U) /!<ETR_RMP[1:0] bits (TIM22 ETR remap) /
<>	144:ef7eb2e8f9f7	3770	#define TIM22_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3771	#define TIM22_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3772	#define TIM22_OR_TI1_RMP ((uint32_t)0x0000000CU) /!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) /
<>	144:ef7eb2e8f9f7	3773	#define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3774	#define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3775
<>	144:ef7eb2e8f9f7	3776	#define TIM3_OR_ETR_RMP ((uint32_t)0x00000003U) /!<ETR_RMP[1:0] bits (TIM3 ETR remap) /
<>	144:ef7eb2e8f9f7	3777	#define TIM3_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3778	#define TIM3_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3779	#define TIM3_OR_TI1_RMP ((uint32_t)0x00000004U) /!<TI1_RMP[2] bit /
<>	144:ef7eb2e8f9f7	3780	#define TIM3_OR_TI2_RMP ((uint32_t)0x00000008U) /!<TI2_RMP[3] bit /
<>	144:ef7eb2e8f9f7	3781	#define TIM3_OR_TI4_RMP ((uint32_t)0x00000010U) /!<TI4_RMP[4] bit /
<>	144:ef7eb2e8f9f7	3782
<>	144:ef7eb2e8f9f7	3783
<>	144:ef7eb2e8f9f7	3784	/******************************************************************************/
<>	144:ef7eb2e8f9f7	3785	/* */
<>	144:ef7eb2e8f9f7	3786	/* Touch Sensing Controller (TSC) */
<>	144:ef7eb2e8f9f7	3787	/* */
<>	144:ef7eb2e8f9f7	3788	/******************************************************************************/
<>	144:ef7eb2e8f9f7	3789	/***************** Bit definition for TSC_CR register *******************/
<>	144:ef7eb2e8f9f7	3790	#define TSC_CR_TSCE ((uint32_t)0x00000001U) /!<Touch sensing controller enable /
<>	144:ef7eb2e8f9f7	3791	#define TSC_CR_START ((uint32_t)0x00000002U) /!<Start acquisition /
<>	144:ef7eb2e8f9f7	3792	#define TSC_CR_AM ((uint32_t)0x00000004U) /!<Acquisition mode /
<>	144:ef7eb2e8f9f7	3793	#define TSC_CR_SYNCPOL ((uint32_t)0x00000008U) /!<Synchronization pin polarity /
<>	144:ef7eb2e8f9f7	3794	#define TSC_CR_IODEF ((uint32_t)0x00000010U) /!<IO default mode /
<>	144:ef7eb2e8f9f7	3795
<>	144:ef7eb2e8f9f7	3796	#define TSC_CR_MCV ((uint32_t)0x000000E0U) /!<MCV[2:0] bits (Max Count Value) /
<>	144:ef7eb2e8f9f7	3797	#define TSC_CR_MCV_0 ((uint32_t)0x00000020U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3798	#define TSC_CR_MCV_1 ((uint32_t)0x00000040U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3799	#define TSC_CR_MCV_2 ((uint32_t)0x00000080U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3800
<>	144:ef7eb2e8f9f7	3801	#define TSC_CR_PGPSC ((uint32_t)0x00007000U) /!<PGPSC[2:0] bits (Pulse Generator Prescaler) /
<>	144:ef7eb2e8f9f7	3802	#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3803	#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3804	#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3805
<>	144:ef7eb2e8f9f7	3806	#define TSC_CR_SSPSC ((uint32_t)0x00008000U) /!<Spread Spectrum Prescaler /
<>	144:ef7eb2e8f9f7	3807	#define TSC_CR_SSE ((uint32_t)0x00010000U) /!<Spread Spectrum Enable /
<>	144:ef7eb2e8f9f7	3808
<>	144:ef7eb2e8f9f7	3809	#define TSC_CR_SSD ((uint32_t)0x00FE0000U) /!<SSD[6:0] bits (Spread Spectrum Deviation) /
<>	144:ef7eb2e8f9f7	3810	#define TSC_CR_SSD_0 ((uint32_t)0x00020000U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3811	#define TSC_CR_SSD_1 ((uint32_t)0x00040000U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3812	#define TSC_CR_SSD_2 ((uint32_t)0x00080000U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3813	#define TSC_CR_SSD_3 ((uint32_t)0x00100000U) /!<Bit 3 /
<>	144:ef7eb2e8f9f7	3814	#define TSC_CR_SSD_4 ((uint32_t)0x00200000U) /!<Bit 4 /
<>	144:ef7eb2e8f9f7	3815	#define TSC_CR_SSD_5 ((uint32_t)0x00400000U) /!<Bit 5 /
<>	144:ef7eb2e8f9f7	3816	#define TSC_CR_SSD_6 ((uint32_t)0x00800000U) /!<Bit 6 /
<>	144:ef7eb2e8f9f7	3817
<>	144:ef7eb2e8f9f7	3818	#define TSC_CR_CTPL ((uint32_t)0x0F000000U) /!<CTPL[3:0] bits (Charge Transfer pulse low) /
<>	144:ef7eb2e8f9f7	3819	#define TSC_CR_CTPL_0 ((uint32_t)0x01000000U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3820	#define TSC_CR_CTPL_1 ((uint32_t)0x02000000U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3821	#define TSC_CR_CTPL_2 ((uint32_t)0x04000000U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3822	#define TSC_CR_CTPL_3 ((uint32_t)0x08000000U) /!<Bit 3 /
<>	144:ef7eb2e8f9f7	3823
<>	144:ef7eb2e8f9f7	3824	#define TSC_CR_CTPH ((uint32_t)0xF0000000U) /!<CTPH[3:0] bits (Charge Transfer pulse high) /
<>	144:ef7eb2e8f9f7	3825	#define TSC_CR_CTPH_0 ((uint32_t)0x10000000U) /!<Bit 0 /
<>	144:ef7eb2e8f9f7	3826	#define TSC_CR_CTPH_1 ((uint32_t)0x20000000U) /!<Bit 1 /
<>	144:ef7eb2e8f9f7	3827	#define TSC_CR_CTPH_2 ((uint32_t)0x40000000U) /!<Bit 2 /
<>	144:ef7eb2e8f9f7	3828	#define TSC_CR_CTPH_3 ((uint32_t)0x80000000U) /!<Bit 3 /
<>	144:ef7eb2e8f9f7	3829
<>	144:ef7eb2e8f9f7	3830	/***************** Bit definition for TSC_IER register ******************/
<>	144:ef7eb2e8f9f7	3831	#define TSC_IER_EOAIE ((uint32_t)0x00000001U) /!<End of acquisition interrupt enable /
<>	144:ef7eb2e8f9f7	3832	#define TSC_IER_MCEIE ((uint32_t)0x00000002U) /!<Max count error interrupt enable /
<>	144:ef7eb2e8f9f7	3833
<>	144:ef7eb2e8f9f7	3834	/***************** Bit definition for TSC_ICR register ******************/
<>	144:ef7eb2e8f9f7	3835	#define TSC_ICR_EOAIC ((uint32_t)0x00000001U) /!<End of acquisition interrupt clear /
<>	144:ef7eb2e8f9f7	3836	#define TSC_ICR_MCEIC ((uint32_t)0x00000002U) /!<Max count error interrupt clear /
<>	144:ef7eb2e8f9f7	3837
<>	144:ef7eb2e8f9f7	3838	/***************** Bit definition for TSC_ISR register ******************/
<>	144:ef7eb2e8f9f7	3839	#define TSC_ISR_EOAF ((uint32_t)0x00000001U) /!<End of acquisition flag /
<>	144:ef7eb2e8f9f7	3840	#define TSC_ISR_MCEF ((uint32_t)0x00000002U) /!<Max count error flag /
<>	144:ef7eb2e8f9f7	3841
<>	144:ef7eb2e8f9f7	3842	/***************** Bit definition for TSC_IOHCR register ****************/
<>	144:ef7eb2e8f9f7	3843	#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001U) /!<GROUP1_IO1 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3844	#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002U) /!<GROUP1_IO2 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3845	#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004U) /!<GROUP1_IO3 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3846	#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008U) /!<GROUP1_IO4 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3847	#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010U) /!<GROUP2_IO1 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3848	#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020U) /!<GROUP2_IO2 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3849	#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040U) /!<GROUP2_IO3 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3850	#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080U) /!<GROUP2_IO4 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3851	#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100U) /!<GROUP3_IO1 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3852	#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200U) /!<GROUP3_IO2 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3853	#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400U) /!<GROUP3_IO3 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3854	#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800U) /!<GROUP3_IO4 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3855	#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000U) /!<GROUP4_IO1 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3856	#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000U) /!<GROUP4_IO2 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3857	#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000U) /!<GROUP4_IO3 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3858	#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000U) /!<GROUP4_IO4 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3859	#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000U) /!<GROUP5_IO1 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3860	#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000U) /!<GROUP5_IO2 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3861	#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000U) /!<GROUP5_IO3 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3862	#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000U) /!<GROUP5_IO4 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3863	#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000U) /!<GROUP6_IO1 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3864	#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000U) /!<GROUP6_IO2 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3865	#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000U) /!<GROUP6_IO3 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3866	#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000U) /!<GROUP6_IO4 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3867	#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000U) /!<GROUP7_IO1 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3868	#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000U) /!<GROUP7_IO2 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3869	#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000U) /!<GROUP7_IO3 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3870	#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000U) /!<GROUP7_IO4 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3871	#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000U) /!<GROUP8_IO1 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3872	#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000U) /!<GROUP8_IO2 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3873	#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000U) /!<GROUP8_IO3 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3874	#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000U) /!<GROUP8_IO4 schmitt trigger hysteresis mode /
<>	144:ef7eb2e8f9f7	3875
<>	144:ef7eb2e8f9f7	3876	/***************** Bit definition for TSC_IOASCR register ***************/
<>	144:ef7eb2e8f9f7	3877	#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001U) /!<GROUP1_IO1 analog switch enable /
<>	144:ef7eb2e8f9f7	3878	#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002U) /!<GROUP1_IO2 analog switch enable /
<>	144:ef7eb2e8f9f7	3879	#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004U) /!<GROUP1_IO3 analog switch enable /
<>	144:ef7eb2e8f9f7	3880	#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008U) /!<GROUP1_IO4 analog switch enable /
<>	144:ef7eb2e8f9f7	3881	#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010U) /!<GROUP2_IO1 analog switch enable /
<>	144:ef7eb2e8f9f7	3882	#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020U) /!<GROUP2_IO2 analog switch enable /
<>	144:ef7eb2e8f9f7	3883	#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040U) /!<GROUP2_IO3 analog switch enable /
<>	144:ef7eb2e8f9f7	3884	#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080U) /!<GROUP2_IO4 analog switch enable /
<>	144:ef7eb2e8f9f7	3885	#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100U) /!<GROUP3_IO1 analog switch enable /
<>	144:ef7eb2e8f9f7	3886	#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200U) /!<GROUP3_IO2 analog switch enable /
<>	144:ef7eb2e8f9f7	3887	#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400U) /!<GROUP3_IO3 analog switch enable /
<>	144:ef7eb2e8f9f7	3888	#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800U) /!<GROUP3_IO4 analog switch enable /
<>	144:ef7eb2e8f9f7	3889	#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000U) /!<GROUP4_IO1 analog switch enable /
<>	144:ef7eb2e8f9f7	3890	#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000U) /!<GROUP4_IO2 analog switch enable /
<>	144:ef7eb2e8f9f7	3891	#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000U) /!<GROUP4_IO3 analog switch enable /
<>	144:ef7eb2e8f9f7	3892	#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000U) /!<GROUP4_IO4 analog switch enable /
<>	144:ef7eb2e8f9f7	3893	#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000U) /!<GROUP5_IO1 analog switch enable /
<>	144:ef7eb2e8f9f7	3894	#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000U) /!<GROUP5_IO2 analog switch enable /
<>	144:ef7eb2e8f9f7	3895	#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000U) /!<GROUP5_IO3 analog switch enable /
<>	144:ef7eb2e8f9f7	3896	#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000U) /!<GROUP5_IO4 analog switch enable /
<>	144:ef7eb2e8f9f7	3897	#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000U) /!<GROUP6_IO1 analog switch enable /
<>	144:ef7eb2e8f9f7	3898	#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000U) /!<GROUP6_IO2 analog switch enable /
<>	144:ef7eb2e8f9f7	3899	#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000U) /!<GROUP6_IO3 analog switch enable /
<>	144:ef7eb2e8f9f7	3900	#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000U) /!<GROUP6_IO4 analog switch enable /
<>	144:ef7eb2e8f9f7	3901	#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000U) /!<GROUP7_IO1 analog switch enable /
<>	144:ef7eb2e8f9f7	3902	#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000U) /!<GROUP7_IO2 analog switch enable /
<>	144:ef7eb2e8f9f7	3903	#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000U) /!<GROUP7_IO3 analog switch enable /
<>	144:ef7eb2e8f9f7	3904	#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000U) /!<GROUP7_IO4 analog switch enable /
<>	144:ef7eb2e8f9f7	3905	#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000U) /!<GROUP8_IO1 analog switch enable /
<>	144:ef7eb2e8f9f7	3906	#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000U) /!<GROUP8_IO2 analog switch enable /
<>	144:ef7eb2e8f9f7	3907	#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000U) /!<GROUP8_IO3 analog switch enable /
<>	144:ef7eb2e8f9f7	3908	#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000U) /!<GROUP8_IO4 analog switch enable /
<>	144:ef7eb2e8f9f7	3909
<>	144:ef7eb2e8f9f7	3910	/***************** Bit definition for TSC_IOSCR register ****************/
<>	144:ef7eb2e8f9f7	3911	#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001U) /!<GROUP1_IO1 sampling mode /
<>	144:ef7eb2e8f9f7	3912	#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002U) /!<GROUP1_IO2 sampling mode /
<>	144:ef7eb2e8f9f7	3913	#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004U) /!<GROUP1_IO3 sampling mode /
<>	144:ef7eb2e8f9f7	3914	#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008U) /!<GROUP1_IO4 sampling mode /
<>	144:ef7eb2e8f9f7	3915	#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010U) /!<GROUP2_IO1 sampling mode /
<>	144:ef7eb2e8f9f7	3916	#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020U) /!<GROUP2_IO2 sampling mode /
<>	144:ef7eb2e8f9f7	3917	#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040U) /!<GROUP2_IO3 sampling mode /
<>	144:ef7eb2e8f9f7	3918	#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080U) /!<GROUP2_IO4 sampling mode /
<>	144:ef7eb2e8f9f7	3919	#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100U) /!<GROUP3_IO1 sampling mode /
<>	144:ef7eb2e8f9f7	3920	#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200U) /!<GROUP3_IO2 sampling mode /
<>	144:ef7eb2e8f9f7	3921	#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400U) /!<GROUP3_IO3 sampling mode /
<>	144:ef7eb2e8f9f7	3922	#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800U) /!<GROUP3_IO4 sampling mode /
<>	144:ef7eb2e8f9f7	3923	#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000U) /!<GROUP4_IO1 sampling mode /
<>	144:ef7eb2e8f9f7	3924	#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000U) /!<GROUP4_IO2 sampling mode /
<>	144:ef7eb2e8f9f7	3925	#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000U) /!<GROUP4_IO3 sampling mode /
<>	144:ef7eb2e8f9f7	3926	#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000U) /!<GROUP4_IO4 sampling mode /
<>	144:ef7eb2e8f9f7	3927	#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000U) /!<GROUP5_IO1 sampling mode /
<>	144:ef7eb2e8f9f7	3928	#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000U) /!<GROUP5_IO2 sampling mode /
<>	144:ef7eb2e8f9f7	3929	#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000U) /!<GROUP5_IO3 sampling mode /
<>	144:ef7eb2e8f9f7	3930	#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000U) /!<GROUP5_IO4 sampling mode /
<>	144:ef7eb2e8f9f7	3931	#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000U) /!<GROUP6_IO1 sampling mode /
<>	144:ef7eb2e8f9f7	3932	#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000U) /!<GROUP6_IO2 sampling mode /
<>	144:ef7eb2e8f9f7	3933	#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000U) /!<GROUP6_IO3 sampling mode /
<>	144:ef7eb2e8f9f7	3934	#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000U) /!<GROUP6_IO4 sampling mode /
<>	144:ef7eb2e8f9f7	3935	#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000U) /!<GROUP7_IO1 sampling mode /
<>	144:ef7eb2e8f9f7	3936	#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000U) /!<GROUP7_IO2 sampling mode /
<>	144:ef7eb2e8f9f7	3937	#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000U) /!<GROUP7_IO3 sampling mode /
<>	144:ef7eb2e8f9f7	3938	#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000U) /!<GROUP7_IO4 sampling mode /
<>	144:ef7eb2e8f9f7	3939	#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000U) /!<GROUP8_IO1 sampling mode /
<>	144:ef7eb2e8f9f7	3940	#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000U) /!<GROUP8_IO2 sampling mode /
<>	144:ef7eb2e8f9f7	3941	#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000U) /!<GROUP8_IO3 sampling mode /
<>	144:ef7eb2e8f9f7	3942	#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000U) /!<GROUP8_IO4 sampling mode /
<>	144:ef7eb2e8f9f7	3943
<>	144:ef7eb2e8f9f7	3944	/***************** Bit definition for TSC_IOCCR register ****************/
<>	144:ef7eb2e8f9f7	3945	#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001U) /!<GROUP1_IO1 channel mode /
<>	144:ef7eb2e8f9f7	3946	#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002U) /!<GROUP1_IO2 channel mode /
<>	144:ef7eb2e8f9f7	3947	#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004U) /!<GROUP1_IO3 channel mode /
<>	144:ef7eb2e8f9f7	3948	#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008U) /!<GROUP1_IO4 channel mode /
<>	144:ef7eb2e8f9f7	3949	#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010U) /!<GROUP2_IO1 channel mode /
<>	144:ef7eb2e8f9f7	3950	#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020U) /!<GROUP2_IO2 channel mode /
<>	144:ef7eb2e8f9f7	3951	#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040U) /!<GROUP2_IO3 channel mode /
<>	144:ef7eb2e8f9f7	3952	#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080U) /!<GROUP2_IO4 channel mode /
<>	144:ef7eb2e8f9f7	3953	#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100U) /!<GROUP3_IO1 channel mode /
<>	144:ef7eb2e8f9f7	3954	#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200U) /!<GROUP3_IO2 channel mode /
<>	144:ef7eb2e8f9f7	3955	#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400U) /!<GROUP3_IO3 channel mode /
<>	144:ef7eb2e8f9f7	3956	#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800U) /!<GROUP3_IO4 channel mode /
<>	144:ef7eb2e8f9f7	3957	#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000U) /!<GROUP4_IO1 channel mode /
<>	144:ef7eb2e8f9f7	3958	#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000U) /!<GROUP4_IO2 channel mode /
<>	144:ef7eb2e8f9f7	3959	#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000U) /!<GROUP4_IO3 channel mode /
<>	144:ef7eb2e8f9f7	3960	#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000U) /!<GROUP4_IO4 channel mode /
<>	144:ef7eb2e8f9f7	3961	#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000U) /!<GROUP5_IO1 channel mode /
<>	144:ef7eb2e8f9f7	3962	#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000U) /!<GROUP5_IO2 channel mode /
<>	144:ef7eb2e8f9f7	3963	#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000U) /!<GROUP5_IO3 channel mode /
<>	144:ef7eb2e8f9f7	3964	#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000U) /!<GROUP5_IO4 channel mode /
<>	144:ef7eb2e8f9f7	3965	#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000U) /!<GROUP6_IO1 channel mode /
<>	144:ef7eb2e8f9f7	3966	#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000U) /!<GROUP6_IO2 channel mode /
<>	144:ef7eb2e8f9f7	3967	#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000U) /!<GROUP6_IO3 channel mode /
<>	144:ef7eb2e8f9f7	3968	#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000U) /!<GROUP6_IO4 channel mode /
<>	144:ef7eb2e8f9f7	3969	#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000U) /!<GROUP7_IO1 channel mode /
<>	144:ef7eb2e8f9f7	3970	#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000U) /!<GROUP7_IO2 channel mode /
<>	144:ef7eb2e8f9f7	3971	#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000U) /!<GROUP7_IO3 channel mode /
<>	144:ef7eb2e8f9f7	3972	#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000U) /!<GROUP7_IO4 channel mode /
<>	144:ef7eb2e8f9f7	3973	#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000U) /!<GROUP8_IO1 channel mode /
<>	144:ef7eb2e8f9f7	3974	#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000U) /!<GROUP8_IO2 channel mode /
<>	144:ef7eb2e8f9f7	3975	#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000U) /!<GROUP8_IO3 channel mode /
<>	144:ef7eb2e8f9f7	3976	#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000U) /!<GROUP8_IO4 channel mode /
<>	144:ef7eb2e8f9f7	3977
<>	144:ef7eb2e8f9f7	3978	/***************** Bit definition for TSC_IOGCSR register ***************/
<>	144:ef7eb2e8f9f7	3979	#define TSC_IOGCSR_G1E ((uint32_t)0x00000001U) /!<Analog IO GROUP1 enable /
<>	144:ef7eb2e8f9f7	3980	#define TSC_IOGCSR_G2E ((uint32_t)0x00000002U) /!<Analog IO GROUP2 enable /
<>	144:ef7eb2e8f9f7	3981	#define TSC_IOGCSR_G3E ((uint32_t)0x00000004U) /!<Analog IO GROUP3 enable /
<>	144:ef7eb2e8f9f7	3982	#define TSC_IOGCSR_G4E ((uint32_t)0x00000008U) /!<Analog IO GROUP4 enable /
<>	144:ef7eb2e8f9f7	3983	#define TSC_IOGCSR_G5E ((uint32_t)0x00000010U) /!<Analog IO GROUP5 enable /
<>	144:ef7eb2e8f9f7	3984	#define TSC_IOGCSR_G6E ((uint32_t)0x00000020U) /!<Analog IO GROUP6 enable /
<>	144:ef7eb2e8f9f7	3985	#define TSC_IOGCSR_G7E ((uint32_t)0x00000040U) /!<Analog IO GROUP7 enable /
<>	144:ef7eb2e8f9f7	3986	#define TSC_IOGCSR_G8E ((uint32_t)0x00000080U) /!<Analog IO GROUP8 enable /
<>	144:ef7eb2e8f9f7	3987	#define TSC_IOGCSR_G1S ((uint32_t)0x00010000U) /!<Analog IO GROUP1 status /
<>	144:ef7eb2e8f9f7	3988	#define TSC_IOGCSR_G2S ((uint32_t)0x00020000U) /!<Analog IO GROUP2 status /
<>	144:ef7eb2e8f9f7	3989	#define TSC_IOGCSR_G3S ((uint32_t)0x00040000U) /!<Analog IO GROUP3 status /
<>	144:ef7eb2e8f9f7	3990	#define TSC_IOGCSR_G4S ((uint32_t)0x00080000U) /!<Analog IO GROUP4 status /
<>	144:ef7eb2e8f9f7	3991	#define TSC_IOGCSR_G5S ((uint32_t)0x00100000U) /!<Analog IO GROUP5 status /
<>	144:ef7eb2e8f9f7	3992	#define TSC_IOGCSR_G6S ((uint32_t)0x00200000U) /!<Analog IO GROUP6 status /
<>	144:ef7eb2e8f9f7	3993	#define TSC_IOGCSR_G7S ((uint32_t)0x00400000U) /!<Analog IO GROUP7 status /
<>	144:ef7eb2e8f9f7	3994	#define TSC_IOGCSR_G8S ((uint32_t)0x00800000U) /!<Analog IO GROUP8 status /
<>	144:ef7eb2e8f9f7	3995
<>	144:ef7eb2e8f9f7	3996	/***************** Bit definition for TSC_IOGXCR register ***************/
<>	144:ef7eb2e8f9f7	3997	#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFFU) /!<CNT[13:0] bits (Counter value) /
<>	144:ef7eb2e8f9f7	3998
<>	144:ef7eb2e8f9f7	3999	/******************************************************************************/
<>	144:ef7eb2e8f9f7	4000	/* */
<>	144:ef7eb2e8f9f7	4001	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
<>	144:ef7eb2e8f9f7	4002	/* */
<>	144:ef7eb2e8f9f7	4003	/******************************************************************************/
<>	144:ef7eb2e8f9f7	4004
<>	144:ef7eb2e8f9f7	4005	/*
<>	144:ef7eb2e8f9f7	4006	* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
<>	144:ef7eb2e8f9f7	4007	*/
<>	144:ef7eb2e8f9f7	4008	/* Note: No specific macro feature on this device */
<>	144:ef7eb2e8f9f7	4009
<>	144:ef7eb2e8f9f7	4010	/**************** Bit definition for USART_CR1 register *****************/
<>	144:ef7eb2e8f9f7	4011	#define USART_CR1_UE ((uint32_t)0x00000001U) /!< USART Enable /
<>	144:ef7eb2e8f9f7	4012	#define USART_CR1_UESM ((uint32_t)0x00000002U) /!< USART Enable in STOP Mode /
<>	144:ef7eb2e8f9f7	4013	#define USART_CR1_RE ((uint32_t)0x00000004U) /!< Receiver Enable /
<>	144:ef7eb2e8f9f7	4014	#define USART_CR1_TE ((uint32_t)0x00000008U) /!< Transmitter Enable /
<>	144:ef7eb2e8f9f7	4015	#define USART_CR1_IDLEIE ((uint32_t)0x00000010U) /!< IDLE Interrupt Enable /
<>	144:ef7eb2e8f9f7	4016	#define USART_CR1_RXNEIE ((uint32_t)0x00000020U) /!< RXNE Interrupt Enable /
<>	144:ef7eb2e8f9f7	4017	#define USART_CR1_TCIE ((uint32_t)0x00000040U) /!< Transmission Complete Interrupt Enable /
<>	144:ef7eb2e8f9f7	4018	#define USART_CR1_TXEIE ((uint32_t)0x00000080U) /!< TXE Interrupt Enable /
<>	144:ef7eb2e8f9f7	4019	#define USART_CR1_PEIE ((uint32_t)0x00000100U) /!< PE Interrupt Enable /
<>	144:ef7eb2e8f9f7	4020	#define USART_CR1_PS ((uint32_t)0x00000200U) /!< Parity Selection /
<>	144:ef7eb2e8f9f7	4021	#define USART_CR1_PCE ((uint32_t)0x00000400U) /!< Parity Control Enable /
<>	144:ef7eb2e8f9f7	4022	#define USART_CR1_WAKE ((uint32_t)0x00000800U) /!< Receiver Wakeup method /
<>	144:ef7eb2e8f9f7	4023	#define USART_CR1_M ((uint32_t)0x10001000U) /!< Word length /
<>	144:ef7eb2e8f9f7	4024	#define USART_CR1_M0 ((uint32_t)0x00001000U) /!< Word length - Bit 0 /
<>	144:ef7eb2e8f9f7	4025	#define USART_CR1_MME ((uint32_t)0x00002000U) /!< Mute Mode Enable /
<>	144:ef7eb2e8f9f7	4026	#define USART_CR1_CMIE ((uint32_t)0x00004000U) /!< Character match interrupt enable /
<>	144:ef7eb2e8f9f7	4027	#define USART_CR1_OVER8 ((uint32_t)0x00008000U) /!< Oversampling by 8-bit or 16-bit mode /
<>	144:ef7eb2e8f9f7	4028	#define USART_CR1_DEDT ((uint32_t)0x001F0000U) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
<>	144:ef7eb2e8f9f7	4029	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	4030	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	4031	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	4032	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000U) /!< Bit 3 /
<>	144:ef7eb2e8f9f7	4033	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000U) /!< Bit 4 /
<>	144:ef7eb2e8f9f7	4034	#define USART_CR1_DEAT ((uint32_t)0x03E00000U) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
<>	144:ef7eb2e8f9f7	4035	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	4036	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	4037	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	4038	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000U) /!< Bit 3 /
<>	144:ef7eb2e8f9f7	4039	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000U) /!< Bit 4 /
<>	144:ef7eb2e8f9f7	4040	#define USART_CR1_RTOIE ((uint32_t)0x04000000U) /!< Receive Time Out interrupt enable /
<>	144:ef7eb2e8f9f7	4041	#define USART_CR1_EOBIE ((uint32_t)0x08000000U) /!< End of Block interrupt enable /
<>	144:ef7eb2e8f9f7	4042	#define USART_CR1_M1 ((uint32_t)0x10000000U) /!< Word length - Bit 1 /
<>	144:ef7eb2e8f9f7	4043	/**************** Bit definition for USART_CR2 register *****************/
<>	144:ef7eb2e8f9f7	4044	#define USART_CR2_ADDM7 ((uint32_t)0x00000010U) /!< 7-bit or 4-bit Address Detection /
<>	144:ef7eb2e8f9f7	4045	#define USART_CR2_LBDL ((uint32_t)0x00000020U) /!< LIN Break Detection Length /
<>	144:ef7eb2e8f9f7	4046	#define USART_CR2_LBDIE ((uint32_t)0x00000040U) /!< LIN Break Detection Interrupt Enable /
<>	144:ef7eb2e8f9f7	4047	#define USART_CR2_LBCL ((uint32_t)0x00000100U) /!< Last Bit Clock pulse /
<>	144:ef7eb2e8f9f7	4048	#define USART_CR2_CPHA ((uint32_t)0x00000200U) /!< Clock Phase /
<>	144:ef7eb2e8f9f7	4049	#define USART_CR2_CPOL ((uint32_t)0x00000400U) /!< Clock Polarity /
<>	144:ef7eb2e8f9f7	4050	#define USART_CR2_CLKEN ((uint32_t)0x00000800U) /!< Clock Enable /
<>	144:ef7eb2e8f9f7	4051	#define USART_CR2_STOP ((uint32_t)0x00003000U) /!< STOP[1:0] bits (STOP bits) /
<>	144:ef7eb2e8f9f7	4052	#define USART_CR2_STOP_0 ((uint32_t)0x00001000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	4053	#define USART_CR2_STOP_1 ((uint32_t)0x00002000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	4054	#define USART_CR2_LINEN ((uint32_t)0x00004000U) /!< LIN mode enable /
<>	144:ef7eb2e8f9f7	4055	#define USART_CR2_SWAP ((uint32_t)0x00008000U) /!< SWAP TX/RX pins /
<>	144:ef7eb2e8f9f7	4056	#define USART_CR2_RXINV ((uint32_t)0x00010000U) /!< RX pin active level inversion /
<>	144:ef7eb2e8f9f7	4057	#define USART_CR2_TXINV ((uint32_t)0x00020000U) /!< TX pin active level inversion /
<>	144:ef7eb2e8f9f7	4058	#define USART_CR2_DATAINV ((uint32_t)0x00040000U) /!< Binary data inversion /
<>	144:ef7eb2e8f9f7	4059	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000U) /!< Most Significant Bit First /
<>	144:ef7eb2e8f9f7	4060	#define USART_CR2_ABREN ((uint32_t)0x00100000U) /!< Auto Baud-Rate Enable/
<>	144:ef7eb2e8f9f7	4061	#define USART_CR2_ABRMODE ((uint32_t)0x00600000U) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
<>	144:ef7eb2e8f9f7	4062	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	4063	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	4064	#define USART_CR2_RTOEN ((uint32_t)0x00800000U) /!< Receiver Time-Out enable /
<>	144:ef7eb2e8f9f7	4065	#define USART_CR2_ADD ((uint32_t)0xFF000000U) /!< Address of the USART node /
<>	144:ef7eb2e8f9f7	4066
<>	144:ef7eb2e8f9f7	4067	/**************** Bit definition for USART_CR3 register *****************/
<>	144:ef7eb2e8f9f7	4068	#define USART_CR3_EIE ((uint32_t)0x00000001U) /!< Error Interrupt Enable /
<>	144:ef7eb2e8f9f7	4069	#define USART_CR3_IREN ((uint32_t)0x00000002U) /!< IrDA mode Enable /
<>	144:ef7eb2e8f9f7	4070	#define USART_CR3_IRLP ((uint32_t)0x00000004U) /!< IrDA Low-Power /
<>	144:ef7eb2e8f9f7	4071	#define USART_CR3_HDSEL ((uint32_t)0x00000008U) /!< Half-Duplex Selection /
<>	144:ef7eb2e8f9f7	4072	#define USART_CR3_NACK ((uint32_t)0x00000010U) /!< SmartCard NACK enable /
<>	144:ef7eb2e8f9f7	4073	#define USART_CR3_SCEN ((uint32_t)0x00000020U) /!< SmartCard mode enable /
<>	144:ef7eb2e8f9f7	4074	#define USART_CR3_DMAR ((uint32_t)0x00000040U) /!< DMA Enable Receiver /
<>	144:ef7eb2e8f9f7	4075	#define USART_CR3_DMAT ((uint32_t)0x00000080U) /!< DMA Enable Transmitter /
<>	144:ef7eb2e8f9f7	4076	#define USART_CR3_RTSE ((uint32_t)0x00000100U) /!< RTS Enable /
<>	144:ef7eb2e8f9f7	4077	#define USART_CR3_CTSE ((uint32_t)0x00000200U) /!< CTS Enable /
<>	144:ef7eb2e8f9f7	4078	#define USART_CR3_CTSIE ((uint32_t)0x00000400U) /!< CTS Interrupt Enable /
<>	144:ef7eb2e8f9f7	4079	#define USART_CR3_ONEBIT ((uint32_t)0x00000800U) /!< One sample bit method enable /
<>	144:ef7eb2e8f9f7	4080	#define USART_CR3_OVRDIS ((uint32_t)0x00001000U) /!< Overrun Disable /
<>	144:ef7eb2e8f9f7	4081	#define USART_CR3_DDRE ((uint32_t)0x00002000U) /!< DMA Disable on Reception Error /
<>	144:ef7eb2e8f9f7	4082	#define USART_CR3_DEM ((uint32_t)0x00004000U) /!< Driver Enable Mode /
<>	144:ef7eb2e8f9f7	4083	#define USART_CR3_DEP ((uint32_t)0x00008000U) /!< Driver Enable Polarity Selection /
<>	144:ef7eb2e8f9f7	4084	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000U) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
<>	144:ef7eb2e8f9f7	4085	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	4086	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	4087	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	4088	#define USART_CR3_WUS ((uint32_t)0x00300000U) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
<>	144:ef7eb2e8f9f7	4089	#define USART_CR3_WUS_0 ((uint32_t)0x00100000U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	4090	#define USART_CR3_WUS_1 ((uint32_t)0x00200000U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	4091	#define USART_CR3_WUFIE ((uint32_t)0x00400000U) /!< Wake Up Interrupt Enable /
<>	144:ef7eb2e8f9f7	4092	#define USART_CR3_UCESM ((uint32_t)0x00800000U) /!< Clock Enable in Stop mode /
<>	144:ef7eb2e8f9f7	4093
<>	144:ef7eb2e8f9f7	4094	/**************** Bit definition for USART_BRR register *****************/
<>	144:ef7eb2e8f9f7	4095	#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000FU) /!< Fraction of USARTDIV /
<>	144:ef7eb2e8f9f7	4096	#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0U) /!< Mantissa of USARTDIV /
<>	144:ef7eb2e8f9f7	4097
<>	144:ef7eb2e8f9f7	4098	/**************** Bit definition for USART_GTPR register ****************/
<>	144:ef7eb2e8f9f7	4099	#define USART_GTPR_PSC ((uint32_t)0x000000FFU) /!< PSC[7:0] bits (Prescaler value) /
<>	144:ef7eb2e8f9f7	4100	#define USART_GTPR_GT ((uint32_t)0x0000FF00U) /!< GT[7:0] bits (Guard time value) /
<>	144:ef7eb2e8f9f7	4101
<>	144:ef7eb2e8f9f7	4102
<>	144:ef7eb2e8f9f7	4103	/***************** Bit definition for USART_RTOR register ***************/
<>	144:ef7eb2e8f9f7	4104	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFFU) /!< Receiver Time Out Value /
<>	144:ef7eb2e8f9f7	4105	#define USART_RTOR_BLEN ((uint32_t)0xFF000000U) /!< Block Length /
<>	144:ef7eb2e8f9f7	4106
<>	144:ef7eb2e8f9f7	4107	/***************** Bit definition for USART_RQR register ****************/
<>	144:ef7eb2e8f9f7	4108	#define USART_RQR_ABRRQ ((uint32_t)0x00000001U) /!< Auto-Baud Rate Request /
<>	144:ef7eb2e8f9f7	4109	#define USART_RQR_SBKRQ ((uint32_t)0x00000002U) /!< Send Break Request /
<>	144:ef7eb2e8f9f7	4110	#define USART_RQR_MMRQ ((uint32_t)0x00000004U) /!< Mute Mode Request /
<>	144:ef7eb2e8f9f7	4111	#define USART_RQR_RXFRQ ((uint32_t)0x00000008U) /!< Receive Data flush Request /
<>	144:ef7eb2e8f9f7	4112	#define USART_RQR_TXFRQ ((uint32_t)0x00000010U) /!< Transmit data flush Request /
<>	144:ef7eb2e8f9f7	4113
<>	144:ef7eb2e8f9f7	4114	/***************** Bit definition for USART_ISR register ****************/
<>	144:ef7eb2e8f9f7	4115	#define USART_ISR_PE ((uint32_t)0x00000001U) /!< Parity Error /
<>	144:ef7eb2e8f9f7	4116	#define USART_ISR_FE ((uint32_t)0x00000002U) /!< Framing Error /
<>	144:ef7eb2e8f9f7	4117	#define USART_ISR_NE ((uint32_t)0x00000004U) /!< Noise detected Flag /
<>	144:ef7eb2e8f9f7	4118	#define USART_ISR_ORE ((uint32_t)0x00000008U) /!< OverRun Error /
<>	144:ef7eb2e8f9f7	4119	#define USART_ISR_IDLE ((uint32_t)0x00000010U) /!< IDLE line detected /
<>	144:ef7eb2e8f9f7	4120	#define USART_ISR_RXNE ((uint32_t)0x00000020U) /!< Read Data Register Not Empty /
<>	144:ef7eb2e8f9f7	4121	#define USART_ISR_TC ((uint32_t)0x00000040U) /!< Transmission Complete /
<>	144:ef7eb2e8f9f7	4122	#define USART_ISR_TXE ((uint32_t)0x00000080U) /!< Transmit Data Register Empty /
<>	144:ef7eb2e8f9f7	4123	#define USART_ISR_LBDF ((uint32_t)0x00000100U) /!< LIN Break Detection Flag /
<>	144:ef7eb2e8f9f7	4124	#define USART_ISR_CTSIF ((uint32_t)0x00000200U) /!< CTS interrupt flag /
<>	144:ef7eb2e8f9f7	4125	#define USART_ISR_CTS ((uint32_t)0x00000400U) /!< CTS flag /
<>	144:ef7eb2e8f9f7	4126	#define USART_ISR_RTOF ((uint32_t)0x00000800U) /!< Receiver Time Out /
<>	144:ef7eb2e8f9f7	4127	#define USART_ISR_EOBF ((uint32_t)0x00001000U) /!< End Of Block Flag /
<>	144:ef7eb2e8f9f7	4128	#define USART_ISR_ABRE ((uint32_t)0x00004000U) /!< Auto-Baud Rate Error /
<>	144:ef7eb2e8f9f7	4129	#define USART_ISR_ABRF ((uint32_t)0x00008000U) /!< Auto-Baud Rate Flag /
<>	144:ef7eb2e8f9f7	4130	#define USART_ISR_BUSY ((uint32_t)0x00010000U) /!< Busy Flag /
<>	144:ef7eb2e8f9f7	4131	#define USART_ISR_CMF ((uint32_t)0x00020000U) /!< Character Match Flag /
<>	144:ef7eb2e8f9f7	4132	#define USART_ISR_SBKF ((uint32_t)0x00040000U) /!< Send Break Flag /
<>	144:ef7eb2e8f9f7	4133	#define USART_ISR_RWU ((uint32_t)0x00080000U) /!< Receive Wake Up from mute mode Flag /
<>	144:ef7eb2e8f9f7	4134	#define USART_ISR_WUF ((uint32_t)0x00100000U) /!< Wake Up from stop mode Flag /
<>	144:ef7eb2e8f9f7	4135	#define USART_ISR_TEACK ((uint32_t)0x00200000U) /!< Transmit Enable Acknowledge Flag /
<>	144:ef7eb2e8f9f7	4136	#define USART_ISR_REACK ((uint32_t)0x00400000U) /!< Receive Enable Acknowledge Flag /
<>	144:ef7eb2e8f9f7	4137
<>	144:ef7eb2e8f9f7	4138	/***************** Bit definition for USART_ICR register ****************/
<>	144:ef7eb2e8f9f7	4139	#define USART_ICR_PECF ((uint32_t)0x00000001U) /!< Parity Error Clear Flag /
<>	144:ef7eb2e8f9f7	4140	#define USART_ICR_FECF ((uint32_t)0x00000002U) /!< Framing Error Clear Flag /
<>	144:ef7eb2e8f9f7	4141	#define USART_ICR_NCF ((uint32_t)0x00000004U) /!< Noise detected Clear Flag /
<>	144:ef7eb2e8f9f7	4142	#define USART_ICR_ORECF ((uint32_t)0x00000008U) /!< OverRun Error Clear Flag /
<>	144:ef7eb2e8f9f7	4143	#define USART_ICR_IDLECF ((uint32_t)0x00000010U) /!< IDLE line detected Clear Flag /
<>	144:ef7eb2e8f9f7	4144	#define USART_ICR_TCCF ((uint32_t)0x00000040U) /!< Transmission Complete Clear Flag /
<>	144:ef7eb2e8f9f7	4145	#define USART_ICR_LBDCF ((uint32_t)0x00000100U) /!< LIN Break Detection Clear Flag /
<>	144:ef7eb2e8f9f7	4146	#define USART_ICR_CTSCF ((uint32_t)0x00000200U) /!< CTS Interrupt Clear Flag /
<>	144:ef7eb2e8f9f7	4147	#define USART_ICR_RTOCF ((uint32_t)0x00000800U) /!< Receiver Time Out Clear Flag /
<>	144:ef7eb2e8f9f7	4148	#define USART_ICR_EOBCF ((uint32_t)0x00001000U) /!< End Of Block Clear Flag /
<>	144:ef7eb2e8f9f7	4149	#define USART_ICR_CMCF ((uint32_t)0x00020000U) /!< Character Match Clear Flag /
<>	144:ef7eb2e8f9f7	4150	#define USART_ICR_WUCF ((uint32_t)0x00100000U) /!< Wake Up from stop mode Clear Flag /
<>	144:ef7eb2e8f9f7	4151
<>	144:ef7eb2e8f9f7	4152	/***************** Bit definition for USART_RDR register ****************/
<>	144:ef7eb2e8f9f7	4153	#define USART_RDR_RDR ((uint32_t)0x000001FFU) /!< RDR[8:0] bits (Receive Data value) /
<>	144:ef7eb2e8f9f7	4154
<>	144:ef7eb2e8f9f7	4155	/***************** Bit definition for USART_TDR register ****************/
<>	144:ef7eb2e8f9f7	4156	#define USART_TDR_TDR ((uint32_t)0x000001FFU) /!< TDR[8:0] bits (Transmit Data value) /
<>	144:ef7eb2e8f9f7	4157
<>	144:ef7eb2e8f9f7	4158	/******************************************************************************/
<>	144:ef7eb2e8f9f7	4159	/* */
<>	144:ef7eb2e8f9f7	4160	/* USB Device General registers */
<>	144:ef7eb2e8f9f7	4161	/* */
<>	144:ef7eb2e8f9f7	4162	/******************************************************************************/
<>	144:ef7eb2e8f9f7	4163	#define USB_BASE ((uint32_t)0x40005C00U) /!< USB_IP Peripheral Registers base address /
<>	144:ef7eb2e8f9f7	4164	#define USB_PMAADDR ((uint32_t)0x40006000U) /!< USB_IP Packet Memory Area base address /
<>	144:ef7eb2e8f9f7	4165
<>	144:ef7eb2e8f9f7	4166	#define USB_CNTR (USB_BASE + 0x40) /!< Control register /
<>	144:ef7eb2e8f9f7	4167	#define USB_ISTR (USB_BASE + 0x44) /!< Interrupt status register /
<>	144:ef7eb2e8f9f7	4168	#define USB_FNR (USB_BASE + 0x48) /!< Frame number register /
<>	144:ef7eb2e8f9f7	4169	#define USB_DADDR (USB_BASE + 0x4C) /!< Device address register /
<>	144:ef7eb2e8f9f7	4170	#define USB_BTABLE (USB_BASE + 0x50) /!< Buffer Table address register /
<>	144:ef7eb2e8f9f7	4171	#define USB_LPMCSR (USB_BASE + 0x54) /!< LPM Control and Status register /
<>	144:ef7eb2e8f9f7	4172	#define USB_BCDR (USB_BASE + 0x58) /!< Battery Charging detector register/
<>	144:ef7eb2e8f9f7	4173
<>	144:ef7eb2e8f9f7	4174	/************************** ISTR interrupt events ***********************/
<>	144:ef7eb2e8f9f7	4175	#define USB_ISTR_CTR ((uint16_t)0x8000U) /!< Correct TRansfer (clear-only bit) /
<>	144:ef7eb2e8f9f7	4176	#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /!< DMA OVeR/underrun (clear-only bit) /
<>	144:ef7eb2e8f9f7	4177	#define USB_ISTR_ERR ((uint16_t)0x2000U) /!< ERRor (clear-only bit) /
<>	144:ef7eb2e8f9f7	4178	#define USB_ISTR_WKUP ((uint16_t)0x1000U) /!< WaKe UP (clear-only bit) /
<>	144:ef7eb2e8f9f7	4179	#define USB_ISTR_SUSP ((uint16_t)0x0800U) /!< SUSPend (clear-only bit) /
<>	144:ef7eb2e8f9f7	4180	#define USB_ISTR_RESET ((uint16_t)0x0400U) /!< RESET (clear-only bit) /
<>	144:ef7eb2e8f9f7	4181	#define USB_ISTR_SOF ((uint16_t)0x0200U) /!< Start Of Frame (clear-only bit) /
<>	144:ef7eb2e8f9f7	4182	#define USB_ISTR_ESOF ((uint16_t)0x0100U) /!< Expected Start Of Frame (clear-only bit) /
<>	144:ef7eb2e8f9f7	4183	#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /!< LPM L1 state request /
<>	144:ef7eb2e8f9f7	4184	#define USB_ISTR_DIR ((uint16_t)0x0010U) /!< DIRection of transaction (read-only bit) /
<>	144:ef7eb2e8f9f7	4185	#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /!< EndPoint IDentifier (read-only bit) /
<>	144:ef7eb2e8f9f7	4186
<>	144:ef7eb2e8f9f7	4187	#define USB_CLR_CTR (~USB_ISTR_CTR) /!< clear Correct TRansfer bit /
<>	144:ef7eb2e8f9f7	4188	#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /!< clear DMA OVeR/underrun bit/
<>	144:ef7eb2e8f9f7	4189	#define USB_CLR_ERR (~USB_ISTR_ERR) /!< clear ERRor bit /
<>	144:ef7eb2e8f9f7	4190	#define USB_CLR_WKUP (~USB_ISTR_WKUP) /!< clear WaKe UP bit /
<>	144:ef7eb2e8f9f7	4191	#define USB_CLR_SUSP (~USB_ISTR_SUSP) /!< clear SUSPend bit /
<>	144:ef7eb2e8f9f7	4192	#define USB_CLR_RESET (~USB_ISTR_RESET) /!< clear RESET bit /
<>	144:ef7eb2e8f9f7	4193	#define USB_CLR_SOF (~USB_ISTR_SOF) /!< clear Start Of Frame bit /
<>	144:ef7eb2e8f9f7	4194	#define USB_CLR_ESOF (~USB_ISTR_ESOF) /!< clear Expected Start Of Frame bit /
<>	144:ef7eb2e8f9f7	4195	#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /!< clear LPM L1 bit /
<>	144:ef7eb2e8f9f7	4196	/*********************** CNTR control register bits definitions *********/
<>	144:ef7eb2e8f9f7	4197	#define USB_CNTR_CTRM ((uint16_t)0x8000U) /!< Correct TRansfer Mask /
<>	144:ef7eb2e8f9f7	4198	#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /!< DMA OVeR/underrun Mask /
<>	144:ef7eb2e8f9f7	4199	#define USB_CNTR_ERRM ((uint16_t)0x2000U) /!< ERRor Mask /
<>	144:ef7eb2e8f9f7	4200	#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /!< WaKe UP Mask /
<>	144:ef7eb2e8f9f7	4201	#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /!< SUSPend Mask /
<>	144:ef7eb2e8f9f7	4202	#define USB_CNTR_RESETM ((uint16_t)0x0400U) /!< RESET Mask /
<>	144:ef7eb2e8f9f7	4203	#define USB_CNTR_SOFM ((uint16_t)0x0200U) /!< Start Of Frame Mask /
<>	144:ef7eb2e8f9f7	4204	#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /!< Expected Start Of Frame Mask /
<>	144:ef7eb2e8f9f7	4205	#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /!< LPM L1 state request interrupt mask /
<>	144:ef7eb2e8f9f7	4206	#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /!< LPM L1 Resume request /
<>	144:ef7eb2e8f9f7	4207	#define USB_CNTR_RESUME ((uint16_t)0x0010U) /!< RESUME request /
<>	144:ef7eb2e8f9f7	4208	#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /!< Force SUSPend /
<>	144:ef7eb2e8f9f7	4209	#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /!< Low-power MODE /
<>	144:ef7eb2e8f9f7	4210	#define USB_CNTR_PDWN ((uint16_t)0x0002U) /!< Power DoWN /
<>	144:ef7eb2e8f9f7	4211	#define USB_CNTR_FRES ((uint16_t)0x0001U) /!< Force USB RESet /
<>	144:ef7eb2e8f9f7	4212	/*********************** BCDR control register bits definitions *********/
<>	144:ef7eb2e8f9f7	4213	#define USB_BCDR_DPPU ((uint16_t)0x8000U) /!< DP Pull-up Enable /
<>	144:ef7eb2e8f9f7	4214	#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /!< PS2 port or proprietary charger detected /
<>	144:ef7eb2e8f9f7	4215	#define USB_BCDR_SDET ((uint16_t)0x0040U) /!< Secondary detection (SD) status /
<>	144:ef7eb2e8f9f7	4216	#define USB_BCDR_PDET ((uint16_t)0x0020U) /!< Primary detection (PD) status /
<>	144:ef7eb2e8f9f7	4217	#define USB_BCDR_DCDET ((uint16_t)0x0010U) /!< Data contact detection (DCD) status /
<>	144:ef7eb2e8f9f7	4218	#define USB_BCDR_SDEN ((uint16_t)0x0008U) /!< Secondary detection (SD) mode enable /
<>	144:ef7eb2e8f9f7	4219	#define USB_BCDR_PDEN ((uint16_t)0x0004U) /!< Primary detection (PD) mode enable /
<>	144:ef7eb2e8f9f7	4220	#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /!< Data contact detection (DCD) mode enable /
<>	144:ef7eb2e8f9f7	4221	#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /!< Battery charging detector (BCD) enable /
<>	144:ef7eb2e8f9f7	4222	/************************* LPM register bits definitions ****************/
<>	144:ef7eb2e8f9f7	4223	#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /!< BESL value received with last ACKed LPM Token /
<>	144:ef7eb2e8f9f7	4224	#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /!< bRemoteWake value received with last ACKed LPM Token /
<>	144:ef7eb2e8f9f7	4225	#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /!< LPM Token acknowledge enable/
<>	144:ef7eb2e8f9f7	4226	#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /!< LPM support enable /
<>	144:ef7eb2e8f9f7	4227	/****************** FNR Frame Number Register bit definitions **********/
<>	144:ef7eb2e8f9f7	4228	#define USB_FNR_RXDP ((uint16_t)0x8000U) /!< status of D+ data line /
<>	144:ef7eb2e8f9f7	4229	#define USB_FNR_RXDM ((uint16_t)0x4000U) /!< status of D- data line /
<>	144:ef7eb2e8f9f7	4230	#define USB_FNR_LCK ((uint16_t)0x2000U) /!< LoCKed /
<>	144:ef7eb2e8f9f7	4231	#define USB_FNR_LSOF ((uint16_t)0x1800U) /!< Lost SOF /
<>	144:ef7eb2e8f9f7	4232	#define USB_FNR_FN ((uint16_t)0x07FFU) /!< Frame Number /
<>	144:ef7eb2e8f9f7	4233	/****************** DADDR Device ADDRess bit definitions **************/
<>	144:ef7eb2e8f9f7	4234	#define USB_DADDR_EF ((uint8_t)0x80U) /!< USB device address Enable Function /
<>	144:ef7eb2e8f9f7	4235	#define USB_DADDR_ADD ((uint8_t)0x7FU) /!< USB device address /
<>	144:ef7eb2e8f9f7	4236	/**************************** Endpoint register ***********************/
<>	144:ef7eb2e8f9f7	4237	#define USB_EP0R USB_BASE /!< endpoint 0 register address /
<>	144:ef7eb2e8f9f7	4238	#define USB_EP1R (USB_BASE + 0x04) /!< endpoint 1 register address /
<>	144:ef7eb2e8f9f7	4239	#define USB_EP2R (USB_BASE + 0x08) /!< endpoint 2 register address /
<>	144:ef7eb2e8f9f7	4240	#define USB_EP3R (USB_BASE + 0x0C) /!< endpoint 3 register address /
<>	144:ef7eb2e8f9f7	4241	#define USB_EP4R (USB_BASE + 0x10) /!< endpoint 4 register address /
<>	144:ef7eb2e8f9f7	4242	#define USB_EP5R (USB_BASE + 0x14) /!< endpoint 5 register address /
<>	144:ef7eb2e8f9f7	4243	#define USB_EP6R (USB_BASE + 0x18) /!< endpoint 6 register address /
<>	144:ef7eb2e8f9f7	4244	#define USB_EP7R (USB_BASE + 0x1C) /!< endpoint 7 register address /
<>	144:ef7eb2e8f9f7	4245	/* bit positions */
<>	144:ef7eb2e8f9f7	4246	#define USB_EP_CTR_RX ((uint16_t)0x8000U) /!< EndPoint Correct TRansfer RX /
<>	144:ef7eb2e8f9f7	4247	#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /!< EndPoint Data TOGGLE RX /
<>	144:ef7eb2e8f9f7	4248	#define USB_EPRX_STAT ((uint16_t)0x3000U) /!< EndPoint RX STATus bit field /
<>	144:ef7eb2e8f9f7	4249	#define USB_EP_SETUP ((uint16_t)0x0800U) /!< EndPoint SETUP /
<>	144:ef7eb2e8f9f7	4250	#define USB_EP_T_FIELD ((uint16_t)0x0600U) /!< EndPoint TYPE /
<>	144:ef7eb2e8f9f7	4251	#define USB_EP_KIND ((uint16_t)0x0100U) /!< EndPoint KIND /
<>	144:ef7eb2e8f9f7	4252	#define USB_EP_CTR_TX ((uint16_t)0x0080U) /!< EndPoint Correct TRansfer TX /
<>	144:ef7eb2e8f9f7	4253	#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /!< EndPoint Data TOGGLE TX /
<>	144:ef7eb2e8f9f7	4254	#define USB_EPTX_STAT ((uint16_t)0x0030U) /!< EndPoint TX STATus bit field /
<>	144:ef7eb2e8f9f7	4255	#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /!< EndPoint ADDRess FIELD /
<>	144:ef7eb2e8f9f7	4256
<>	144:ef7eb2e8f9f7	4257	/* EndPoint REGister MASK (no toggle fields) */
<>	144:ef7eb2e8f9f7	4258	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
<>	144:ef7eb2e8f9f7	4259	/!< EP_TYPE[1:0] EndPoint TYPE /
<>	144:ef7eb2e8f9f7	4260	#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /!< EndPoint TYPE Mask /
<>	144:ef7eb2e8f9f7	4261	#define USB_EP_BULK ((uint16_t)0x0000U) /!< EndPoint BULK /
<>	144:ef7eb2e8f9f7	4262	#define USB_EP_CONTROL ((uint16_t)0x0200U) /!< EndPoint CONTROL /
<>	144:ef7eb2e8f9f7	4263	#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /!< EndPoint ISOCHRONOUS /
<>	144:ef7eb2e8f9f7	4264	#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /!< EndPoint INTERRUPT /
<>	144:ef7eb2e8f9f7	4265	#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
<>	144:ef7eb2e8f9f7	4266
<>	144:ef7eb2e8f9f7	4267	#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
<>	144:ef7eb2e8f9f7	4268	/!< STAT_TX[1:0] STATus for TX transfer /
<>	144:ef7eb2e8f9f7	4269	#define USB_EP_TX_DIS ((uint16_t)0x0000U) /!< EndPoint TX DISabled /
<>	144:ef7eb2e8f9f7	4270	#define USB_EP_TX_STALL ((uint16_t)0x0010U) /!< EndPoint TX STALLed /
<>	144:ef7eb2e8f9f7	4271	#define USB_EP_TX_NAK ((uint16_t)0x0020U) /!< EndPoint TX NAKed /
<>	144:ef7eb2e8f9f7	4272	#define USB_EP_TX_VALID ((uint16_t)0x0030U) /!< EndPoint TX VALID /
<>	144:ef7eb2e8f9f7	4273	#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /!< EndPoint TX Data TOGgle bit1 /
<>	144:ef7eb2e8f9f7	4274	#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /!< EndPoint TX Data TOGgle bit2 /
<>	144:ef7eb2e8f9f7	4275	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
<>	144:ef7eb2e8f9f7	4276	/!< STAT_RX[1:0] STATus for RX transfer /
<>	144:ef7eb2e8f9f7	4277	#define USB_EP_RX_DIS ((uint16_t)0x0000U) /!< EndPoint RX DISabled /
<>	144:ef7eb2e8f9f7	4278	#define USB_EP_RX_STALL ((uint16_t)0x1000U) /!< EndPoint RX STALLed /
<>	144:ef7eb2e8f9f7	4279	#define USB_EP_RX_NAK ((uint16_t)0x2000U) /!< EndPoint RX NAKed /
<>	144:ef7eb2e8f9f7	4280	#define USB_EP_RX_VALID ((uint16_t)0x3000U) /!< EndPoint RX VALID /
<>	144:ef7eb2e8f9f7	4281	#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /!< EndPoint RX Data TOGgle bit1 /
<>	144:ef7eb2e8f9f7	4282	#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /!< EndPoint RX Data TOGgle bit1 /
<>	144:ef7eb2e8f9f7	4283	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
<>	144:ef7eb2e8f9f7	4284
<>	144:ef7eb2e8f9f7	4285	/******************************************************************************/
<>	144:ef7eb2e8f9f7	4286	/* */
<>	144:ef7eb2e8f9f7	4287	/* Window WATCHDOG (WWDG) */
<>	144:ef7eb2e8f9f7	4288	/* */
<>	144:ef7eb2e8f9f7	4289	/******************************************************************************/
<>	144:ef7eb2e8f9f7	4290
<>	144:ef7eb2e8f9f7	4291	/***************** Bit definition for WWDG_CR register ******************/
<>	144:ef7eb2e8f9f7	4292	#define WWDG_CR_T ((uint32_t)0x0000007FU) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
<>	144:ef7eb2e8f9f7	4293	#define WWDG_CR_T_0 ((uint32_t)0x00000001U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	4294	#define WWDG_CR_T_1 ((uint32_t)0x00000002U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	4295	#define WWDG_CR_T_2 ((uint32_t)0x00000004U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	4296	#define WWDG_CR_T_3 ((uint32_t)0x00000008U) /!< Bit 3 /
<>	144:ef7eb2e8f9f7	4297	#define WWDG_CR_T_4 ((uint32_t)0x00000010U) /!< Bit 4 /
<>	144:ef7eb2e8f9f7	4298	#define WWDG_CR_T_5 ((uint32_t)0x00000020U) /!< Bit 5 /
<>	144:ef7eb2e8f9f7	4299	#define WWDG_CR_T_6 ((uint32_t)0x00000040U) /!< Bit 6 /
<>	144:ef7eb2e8f9f7	4300
<>	144:ef7eb2e8f9f7	4301	/* Legacy defines */
<>	144:ef7eb2e8f9f7	4302	#define WWDG_CR_T0 WWDG_CR_T_0
<>	144:ef7eb2e8f9f7	4303	#define WWDG_CR_T1 WWDG_CR_T_1
<>	144:ef7eb2e8f9f7	4304	#define WWDG_CR_T2 WWDG_CR_T_2
<>	144:ef7eb2e8f9f7	4305	#define WWDG_CR_T3 WWDG_CR_T_3
<>	144:ef7eb2e8f9f7	4306	#define WWDG_CR_T4 WWDG_CR_T_4
<>	144:ef7eb2e8f9f7	4307	#define WWDG_CR_T5 WWDG_CR_T_5
<>	144:ef7eb2e8f9f7	4308	#define WWDG_CR_T6 WWDG_CR_T_6
<>	144:ef7eb2e8f9f7	4309
<>	144:ef7eb2e8f9f7	4310	#define WWDG_CR_WDGA ((uint32_t)0x00000080U) /!< Activation bit /
<>	144:ef7eb2e8f9f7	4311
<>	144:ef7eb2e8f9f7	4312	/***************** Bit definition for WWDG_CFR register *****************/
<>	144:ef7eb2e8f9f7	4313	#define WWDG_CFR_W ((uint32_t)0x0000007FU) /!< W[6:0] bits (7-bit window value) /
<>	144:ef7eb2e8f9f7	4314	#define WWDG_CFR_W_0 ((uint32_t)0x00000001U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	4315	#define WWDG_CFR_W_1 ((uint32_t)0x00000002U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	4316	#define WWDG_CFR_W_2 ((uint32_t)0x00000004U) /!< Bit 2 /
<>	144:ef7eb2e8f9f7	4317	#define WWDG_CFR_W_3 ((uint32_t)0x00000008U) /!< Bit 3 /
<>	144:ef7eb2e8f9f7	4318	#define WWDG_CFR_W_4 ((uint32_t)0x00000010U) /!< Bit 4 /
<>	144:ef7eb2e8f9f7	4319	#define WWDG_CFR_W_5 ((uint32_t)0x00000020U) /!< Bit 5 /
<>	144:ef7eb2e8f9f7	4320	#define WWDG_CFR_W_6 ((uint32_t)0x00000040U) /!< Bit 6 /
<>	144:ef7eb2e8f9f7	4321
<>	144:ef7eb2e8f9f7	4322	/* Legacy defines */
<>	144:ef7eb2e8f9f7	4323	#define WWDG_CFR_W0 WWDG_CFR_W_0
<>	144:ef7eb2e8f9f7	4324	#define WWDG_CFR_W1 WWDG_CFR_W_1
<>	144:ef7eb2e8f9f7	4325	#define WWDG_CFR_W2 WWDG_CFR_W_2
<>	144:ef7eb2e8f9f7	4326	#define WWDG_CFR_W3 WWDG_CFR_W_3
<>	144:ef7eb2e8f9f7	4327	#define WWDG_CFR_W4 WWDG_CFR_W_4
<>	144:ef7eb2e8f9f7	4328	#define WWDG_CFR_W5 WWDG_CFR_W_5
<>	144:ef7eb2e8f9f7	4329	#define WWDG_CFR_W6 WWDG_CFR_W_6
<>	144:ef7eb2e8f9f7	4330
<>	144:ef7eb2e8f9f7	4331	#define WWDG_CFR_WDGTB ((uint32_t)0x00000180U) /!< WDGTB[1:0] bits (Timer Base) /
<>	144:ef7eb2e8f9f7	4332	#define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080U) /!< Bit 0 /
<>	144:ef7eb2e8f9f7	4333	#define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100U) /!< Bit 1 /
<>	144:ef7eb2e8f9f7	4334
<>	144:ef7eb2e8f9f7	4335	/* Legacy defines */
<>	144:ef7eb2e8f9f7	4336	#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
<>	144:ef7eb2e8f9f7	4337	#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
<>	144:ef7eb2e8f9f7	4338
<>	144:ef7eb2e8f9f7	4339	#define WWDG_CFR_EWI ((uint32_t)0x00000200U) /!< Early Wakeup Interrupt /
<>	144:ef7eb2e8f9f7	4340
<>	144:ef7eb2e8f9f7	4341	/***************** Bit definition for WWDG_SR register ******************/
<>	144:ef7eb2e8f9f7	4342	#define WWDG_SR_EWIF ((uint32_t)0x00000001U) /!< Early Wakeup Interrupt Flag /
<>	144:ef7eb2e8f9f7	4343
<>	144:ef7eb2e8f9f7	4344	/**
<>	144:ef7eb2e8f9f7	4345	* @}
<>	144:ef7eb2e8f9f7	4346	*/
<>	144:ef7eb2e8f9f7	4347
<>	144:ef7eb2e8f9f7	4348	/**
<>	144:ef7eb2e8f9f7	4349	* @}
<>	144:ef7eb2e8f9f7	4350	*/
<>	144:ef7eb2e8f9f7	4351
<>	144:ef7eb2e8f9f7	4352	/** @addtogroup Exported_macros
<>	144:ef7eb2e8f9f7	4353	* @{
<>	144:ef7eb2e8f9f7	4354	*/
<>	144:ef7eb2e8f9f7	4355
<>	144:ef7eb2e8f9f7	4356	/***************************** ADC Instances ******************************/
<>	144:ef7eb2e8f9f7	4357	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
<>	144:ef7eb2e8f9f7	4358
<>	144:ef7eb2e8f9f7	4359	/***************************** COMP Instances *****************************/
<>	144:ef7eb2e8f9f7	4360	#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) \|\| \
<>	144:ef7eb2e8f9f7	4361	((INSTANCE) == COMP2))
<>	144:ef7eb2e8f9f7	4362
<>	144:ef7eb2e8f9f7	4363	#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
<>	144:ef7eb2e8f9f7	4364
<>	144:ef7eb2e8f9f7	4365	/***************************** CRC Instances ******************************/
<>	144:ef7eb2e8f9f7	4366	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
<>	144:ef7eb2e8f9f7	4367
<>	144:ef7eb2e8f9f7	4368	/***************************** DAC Instances *******************************/
<>	144:ef7eb2e8f9f7	4369	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
<>	144:ef7eb2e8f9f7	4370
<>	144:ef7eb2e8f9f7	4371	/***************************** DMA Instances *******************************/
<>	144:ef7eb2e8f9f7	4372	#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) \|\| \
<>	144:ef7eb2e8f9f7	4373	((INSTANCE) == DMA1_Stream1) \|\| \
<>	144:ef7eb2e8f9f7	4374	((INSTANCE) == DMA1_Stream2) \|\| \
<>	144:ef7eb2e8f9f7	4375	((INSTANCE) == DMA1_Stream3) \|\| \
<>	144:ef7eb2e8f9f7	4376	((INSTANCE) == DMA1_Stream4) \|\| \
<>	144:ef7eb2e8f9f7	4377	((INSTANCE) == DMA1_Stream5) \|\| \
<>	144:ef7eb2e8f9f7	4378	((INSTANCE) == DMA1_Stream6) \|\| \
<>	144:ef7eb2e8f9f7	4379	((INSTANCE) == DMA1_Stream7))
<>	144:ef7eb2e8f9f7	4380
<>	144:ef7eb2e8f9f7	4381	/***************************** GPIO Instances *****************************/
<>	144:ef7eb2e8f9f7	4382	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
<>	144:ef7eb2e8f9f7	4383	((INSTANCE) == GPIOB) \|\| \
<>	144:ef7eb2e8f9f7	4384	((INSTANCE) == GPIOC) \|\| \
<>	144:ef7eb2e8f9f7	4385	((INSTANCE) == GPIOD) \|\| \
<>	144:ef7eb2e8f9f7	4386	((INSTANCE) == GPIOE) \|\| \
<>	144:ef7eb2e8f9f7	4387	((INSTANCE) == GPIOH))
<>	144:ef7eb2e8f9f7	4388
<>	144:ef7eb2e8f9f7	4389	#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
<>	144:ef7eb2e8f9f7	4390	((INSTANCE) == GPIOB) \|\| \
<>	144:ef7eb2e8f9f7	4391	((INSTANCE) == GPIOC) \|\| \
<>	144:ef7eb2e8f9f7	4392	((INSTANCE) == GPIOD) \|\| \
<>	144:ef7eb2e8f9f7	4393	((INSTANCE) == GPIOE) \|\| \
<>	144:ef7eb2e8f9f7	4394	((INSTANCE) == GPIOH))
<>	144:ef7eb2e8f9f7	4395
<>	144:ef7eb2e8f9f7	4396	/****************************** I2C Instances *****************************/
<>	144:ef7eb2e8f9f7	4397	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
<>	144:ef7eb2e8f9f7	4398	((INSTANCE) == I2C2) \|\| \
<>	144:ef7eb2e8f9f7	4399	((INSTANCE) == I2C3))
<>	144:ef7eb2e8f9f7	4400
<>	144:ef7eb2e8f9f7	4401	/****************************** I2S Instances *****************************/
<>	144:ef7eb2e8f9f7	4402	#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
<>	144:ef7eb2e8f9f7	4403
<>	144:ef7eb2e8f9f7	4404	/***************************** RNG Instances ******************************/
<>	144:ef7eb2e8f9f7	4405	#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
<>	144:ef7eb2e8f9f7	4406
<>	144:ef7eb2e8f9f7	4407	/**************************** RTC Instances *******************************/
<>	144:ef7eb2e8f9f7	4408	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
<>	144:ef7eb2e8f9f7	4409
<>	144:ef7eb2e8f9f7	4410	/****************************** SMBUS Instances ***************************/
<>	144:ef7eb2e8f9f7	4411	#define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
<>	144:ef7eb2e8f9f7	4412	((INSTANCE) == I2C3))
<>	144:ef7eb2e8f9f7	4413
<>	144:ef7eb2e8f9f7	4414	/****************************** SPI Instances *****************************/
<>	144:ef7eb2e8f9f7	4415	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
<>	144:ef7eb2e8f9f7	4416	((INSTANCE) == SPI2))
<>	144:ef7eb2e8f9f7	4417
<>	144:ef7eb2e8f9f7	4418	/**************** LPTIM Instances : All supported instances ***************/
<>	144:ef7eb2e8f9f7	4419	#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
<>	144:ef7eb2e8f9f7	4420
<>	144:ef7eb2e8f9f7	4421	/**************** TIM Instances : All supported instances *****************/
<>	144:ef7eb2e8f9f7	4422	#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4423	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4424	((INSTANCE) == TIM6) \|\| \
<>	144:ef7eb2e8f9f7	4425	((INSTANCE) == TIM7) \|\| \
<>	144:ef7eb2e8f9f7	4426	((INSTANCE) == TIM21) \|\| \
<>	144:ef7eb2e8f9f7	4427	((INSTANCE) == TIM22))
<>	144:ef7eb2e8f9f7	4428
<>	144:ef7eb2e8f9f7	4429	/**************** TIM Instances : supporting counting mode selection ******/
<>	144:ef7eb2e8f9f7	4430	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4431	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4432	((INSTANCE) == TIM21) \|\| \
<>	144:ef7eb2e8f9f7	4433	((INSTANCE) == TIM22))
<>	144:ef7eb2e8f9f7	4434
<>	144:ef7eb2e8f9f7	4435	/**************** TIM Instances : supporting clock division ***************/
<>	144:ef7eb2e8f9f7	4436	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4437	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4438	((INSTANCE) == TIM21) \|\| \
<>	144:ef7eb2e8f9f7	4439	((INSTANCE) == TIM22))
<>	144:ef7eb2e8f9f7	4440
<>	144:ef7eb2e8f9f7	4441	/**** TIM Instances : supporting external clock mode 1 for ETRF input *****/
<>	144:ef7eb2e8f9f7	4442	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4443	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4444	((INSTANCE) == TIM21))
<>	144:ef7eb2e8f9f7	4445
<>	144:ef7eb2e8f9f7	4446	/**** TIM Instances : supporting external clock mode 2 for ETRF input *****/
<>	144:ef7eb2e8f9f7	4447	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4448	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4449	((INSTANCE) == TIM21) \|\| \
<>	144:ef7eb2e8f9f7	4450	((INSTANCE) == TIM22))
<>	144:ef7eb2e8f9f7	4451
<>	144:ef7eb2e8f9f7	4452	/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
<>	144:ef7eb2e8f9f7	4453	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4454	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4455	((INSTANCE) == TIM21))
<>	144:ef7eb2e8f9f7	4456
<>	144:ef7eb2e8f9f7	4457	/**************** TIM Instances : supporting internal trigger inputs(ITRX) *****/
<>	144:ef7eb2e8f9f7	4458	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4459	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4460	((INSTANCE) == TIM21) \|\| \
<>	144:ef7eb2e8f9f7	4461	((INSTANCE) == TIM22))
<>	144:ef7eb2e8f9f7	4462
<>	144:ef7eb2e8f9f7	4463	/*********** TIM Instances : at least 1 capture/compare channel ***********/
<>	144:ef7eb2e8f9f7	4464	#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4465	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4466	((INSTANCE) == TIM21) \|\| \
<>	144:ef7eb2e8f9f7	4467	((INSTANCE) == TIM22))
<>	144:ef7eb2e8f9f7	4468
<>	144:ef7eb2e8f9f7	4469	/********** TIM Instances : at least 2 capture/compare channels ***********/
<>	144:ef7eb2e8f9f7	4470	#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4471	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4472	((INSTANCE) == TIM21) \|\| \
<>	144:ef7eb2e8f9f7	4473	((INSTANCE) == TIM22))
<>	144:ef7eb2e8f9f7	4474
<>	144:ef7eb2e8f9f7	4475	/********** TIM Instances : at least 3 capture/compare channels ***********/
<>	144:ef7eb2e8f9f7	4476	#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4477	((INSTANCE) == TIM3))
<>	144:ef7eb2e8f9f7	4478
<>	144:ef7eb2e8f9f7	4479	/********** TIM Instances : at least 4 capture/compare channels ***********/
<>	144:ef7eb2e8f9f7	4480	#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4481	((INSTANCE) == TIM3))
<>	144:ef7eb2e8f9f7	4482
<>	144:ef7eb2e8f9f7	4483	/****************** TIM Instances : Advanced-control timers ***************/
<>	144:ef7eb2e8f9f7	4484
<>	144:ef7eb2e8f9f7	4485	/***************** TIM Instances : Timer input XOR function ***************/
<>	144:ef7eb2e8f9f7	4486	#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4487	((INSTANCE) == TIM3))
<>	144:ef7eb2e8f9f7	4488
<>	144:ef7eb2e8f9f7	4489	/**************** TIM Instances : DMA requests generation (UDE) ***********/
<>	144:ef7eb2e8f9f7	4490	#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4491	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4492	((INSTANCE) == TIM6) \|\| \
<>	144:ef7eb2e8f9f7	4493	((INSTANCE) == TIM7))
<>	144:ef7eb2e8f9f7	4494
<>	144:ef7eb2e8f9f7	4495	/********** TIM Instances : DMA requests generation (CCxDE) ***************/
<>	144:ef7eb2e8f9f7	4496	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4497	((INSTANCE) == TIM3))
<>	144:ef7eb2e8f9f7	4498
<>	144:ef7eb2e8f9f7	4499	/********** TIM Instances : DMA requests generation (COMDE) ***************/
<>	144:ef7eb2e8f9f7	4500	#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4501	(INSTANCE) == TIM3))
<>	144:ef7eb2e8f9f7	4502
<>	144:ef7eb2e8f9f7	4503	/****************** TIM Instances : DMA burst feature *********************/
<>	144:ef7eb2e8f9f7	4504	#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4505	((INSTANCE) == TIM3))
<>	144:ef7eb2e8f9f7	4506
<>	144:ef7eb2e8f9f7	4507	/**** TIM Instances : master mode available (TIMx_CR2.MMS available )******/
<>	144:ef7eb2e8f9f7	4508	#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4509	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4510	((INSTANCE) == TIM6) \|\| \
<>	144:ef7eb2e8f9f7	4511	((INSTANCE) == TIM7) \|\| \
<>	144:ef7eb2e8f9f7	4512	((INSTANCE) == TIM21) \|\| \
<>	144:ef7eb2e8f9f7	4513	((INSTANCE) == TIM22))
<>	144:ef7eb2e8f9f7	4514
<>	144:ef7eb2e8f9f7	4515	/********* TIM Instances : Slave mode available (TIMx_SMCR available )*****/
<>	144:ef7eb2e8f9f7	4516	#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4517	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4518	((INSTANCE) == TIM21) \|\| \
<>	144:ef7eb2e8f9f7	4519	((INSTANCE) == TIM22))
<>	144:ef7eb2e8f9f7	4520
<>	144:ef7eb2e8f9f7	4521	/******************** TIM Instances : 32 bit Counter **********************/
<>	144:ef7eb2e8f9f7	4522
<>	144:ef7eb2e8f9f7	4523	/*************** TIM Instances : external trigger input availabe **********/
<>	144:ef7eb2e8f9f7	4524	#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4525	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4526	((INSTANCE) == TIM21) \|\| \
<>	144:ef7eb2e8f9f7	4527	((INSTANCE) == TIM22))
<>	144:ef7eb2e8f9f7	4528
<>	144:ef7eb2e8f9f7	4529	/**************** TIM Instances : remapping capability ********************/
<>	144:ef7eb2e8f9f7	4530	#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4531	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4532	((INSTANCE) == TIM21) \|\| \
<>	144:ef7eb2e8f9f7	4533	((INSTANCE) == TIM22))
<>	144:ef7eb2e8f9f7	4534
<>	144:ef7eb2e8f9f7	4535	/**************** TIM Instances : supporting encoder interface ************/
<>	144:ef7eb2e8f9f7	4536	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4537	((INSTANCE) == TIM3) \|\| \
<>	144:ef7eb2e8f9f7	4538	((INSTANCE) == TIM21) \|\| \
<>	144:ef7eb2e8f9f7	4539	((INSTANCE) == TIM22))
<>	144:ef7eb2e8f9f7	4540
<>	144:ef7eb2e8f9f7	4541	/***************** TIM Instances : output(s) OCXEC register ***************/
<>	144:ef7eb2e8f9f7	4542	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4543	((INSTANCE) == TIM3))
<>	144:ef7eb2e8f9f7	4544
<>	144:ef7eb2e8f9f7	4545	/***************** TIM Instances : output(s) available ********************/
<>	144:ef7eb2e8f9f7	4546	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
<>	144:ef7eb2e8f9f7	4547	(((((INSTANCE) == TIM2) \|\| \
<>	144:ef7eb2e8f9f7	4548	((INSTANCE) == TIM3)) \
<>	144:ef7eb2e8f9f7	4549	&& \
<>	144:ef7eb2e8f9f7	4550	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	4551	((CHANNEL) == TIM_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	4552	((CHANNEL) == TIM_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	4553	((CHANNEL) == TIM_CHANNEL_4))) \
<>	144:ef7eb2e8f9f7	4554	\|\| \
<>	144:ef7eb2e8f9f7	4555	(((INSTANCE) == TIM21) && \
<>	144:ef7eb2e8f9f7	4556	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	4557	((CHANNEL) == TIM_CHANNEL_2))) \
<>	144:ef7eb2e8f9f7	4558	\|\| \
<>	144:ef7eb2e8f9f7	4559	(((INSTANCE) == TIM22) && \
<>	144:ef7eb2e8f9f7	4560	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	4561	((CHANNEL) == TIM_CHANNEL_2))))
<>	144:ef7eb2e8f9f7	4562
<>	144:ef7eb2e8f9f7	4563	/****************** UART Instances : Asynchronous mode ********************/
<>	144:ef7eb2e8f9f7	4564	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
<>	144:ef7eb2e8f9f7	4565	((INSTANCE) == USART2) \|\| \
<>	144:ef7eb2e8f9f7	4566	((INSTANCE) == USART4) \|\| \
<>	144:ef7eb2e8f9f7	4567	((INSTANCE) == USART5) \|\| \
<>	144:ef7eb2e8f9f7	4568	((INSTANCE) == LPUART1))
<>	144:ef7eb2e8f9f7	4569
<>	144:ef7eb2e8f9f7	4570	/****************** USART Instances : Synchronous mode ********************/
<>	144:ef7eb2e8f9f7	4571	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
<>	144:ef7eb2e8f9f7	4572	((INSTANCE) == USART2) \|\| \
<>	144:ef7eb2e8f9f7	4573	((INSTANCE) == USART4) \|\| \
<>	144:ef7eb2e8f9f7	4574	((INSTANCE) == USART5))
<>	144:ef7eb2e8f9f7	4575
<>	144:ef7eb2e8f9f7	4576	/**************** USART Instances : Auto Baud Rate detection **************/
<>	144:ef7eb2e8f9f7	4577
<>	144:ef7eb2e8f9f7	4578	#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
<>	144:ef7eb2e8f9f7	4579	((INSTANCE) == USART2))
<>	144:ef7eb2e8f9f7	4580
<>	144:ef7eb2e8f9f7	4581	/****************** UART Instances : Half-Duplex mode ********************/
<>	144:ef7eb2e8f9f7	4582	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
<>	144:ef7eb2e8f9f7	4583	((INSTANCE) == USART2) \|\| \
<>	144:ef7eb2e8f9f7	4584	((INSTANCE) == USART4) \|\| \
<>	144:ef7eb2e8f9f7	4585	((INSTANCE) == USART5) \|\| \
<>	144:ef7eb2e8f9f7	4586	((INSTANCE) == LPUART1))
<>	144:ef7eb2e8f9f7	4587
<>	144:ef7eb2e8f9f7	4588	/****************** UART Instances : LIN mode ********************/
<>	144:ef7eb2e8f9f7	4589	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
<>	144:ef7eb2e8f9f7	4590	((INSTANCE) == USART2))
<>	144:ef7eb2e8f9f7	4591
<>	144:ef7eb2e8f9f7	4592	/****************** UART Instances : Wake-up from Stop mode ********************/
<>	144:ef7eb2e8f9f7	4593	#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
<>	144:ef7eb2e8f9f7	4594	((INSTANCE) == USART2) \|\| \
<>	144:ef7eb2e8f9f7	4595	((INSTANCE) == LPUART1))
<>	144:ef7eb2e8f9f7	4596	/**************** UART Instances : Hardware Flow control ******************/
<>	144:ef7eb2e8f9f7	4597	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
<>	144:ef7eb2e8f9f7	4598	((INSTANCE) == USART2) \|\| \
<>	144:ef7eb2e8f9f7	4599	((INSTANCE) == USART4) \|\| \
<>	144:ef7eb2e8f9f7	4600	((INSTANCE) == USART5) \|\| \
<>	144:ef7eb2e8f9f7	4601	((INSTANCE) == LPUART1))
<>	144:ef7eb2e8f9f7	4602
<>	144:ef7eb2e8f9f7	4603	/******************* UART Instances : Smard card mode *********************/
<>	144:ef7eb2e8f9f7	4604	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
<>	144:ef7eb2e8f9f7	4605	((INSTANCE) == USART2))
<>	144:ef7eb2e8f9f7	4606
<>	144:ef7eb2e8f9f7	4607	/********************* UART Instances : IRDA mode *************************/
<>	144:ef7eb2e8f9f7	4608	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
<>	144:ef7eb2e8f9f7	4609	((INSTANCE) == USART2))
<>	144:ef7eb2e8f9f7	4610
<>	144:ef7eb2e8f9f7	4611	/**************************** IWDG Instances ******************************/
<>	144:ef7eb2e8f9f7	4612	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
<>	144:ef7eb2e8f9f7	4613
<>	144:ef7eb2e8f9f7	4614	/**************************** USB Instances ******************************/
<>	144:ef7eb2e8f9f7	4615	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
<>	144:ef7eb2e8f9f7	4616
<>	144:ef7eb2e8f9f7	4617	/**************************** WWDG Instances ******************************/
<>	144:ef7eb2e8f9f7	4618	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
<>	144:ef7eb2e8f9f7	4619
<>	144:ef7eb2e8f9f7	4620	/**************************** LCD Instances ******************************/
<>	144:ef7eb2e8f9f7	4621	#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
<>	144:ef7eb2e8f9f7	4622
<>	144:ef7eb2e8f9f7	4623	/**
<>	144:ef7eb2e8f9f7	4624	* @}
<>	144:ef7eb2e8f9f7	4625	*/
<>	144:ef7eb2e8f9f7	4626
<>	144:ef7eb2e8f9f7	4627	/******************************************************************************/
<>	144:ef7eb2e8f9f7	4628	/* For a painless codes migration between the STM32L0xx device product */
<>	144:ef7eb2e8f9f7	4629	/* lines, the aliases defined below are put in place to overcome the */
<>	144:ef7eb2e8f9f7	4630	/* differences in the interrupt handlers and IRQn definitions. */
<>	144:ef7eb2e8f9f7	4631	/* No need to update developed interrupt code when moving across */
<>	144:ef7eb2e8f9f7	4632	/* product lines within the same STM32L0 Family */
<>	144:ef7eb2e8f9f7	4633	/******************************************************************************/
<>	144:ef7eb2e8f9f7	4634
<>	144:ef7eb2e8f9f7	4635	/* Aliases for __IRQn */
<>	144:ef7eb2e8f9f7	4636
<>	144:ef7eb2e8f9f7	4637	#define LPUART1_IRQn RNG_LPUART1_IRQn
<>	144:ef7eb2e8f9f7	4638	#define AES_LPUART1_IRQn RNG_LPUART1_IRQn
<>	144:ef7eb2e8f9f7	4639	#define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
<>	144:ef7eb2e8f9f7	4640	#define TIM6_IRQn TIM6_DAC_IRQn
<>	144:ef7eb2e8f9f7	4641	#define RCC_IRQn RCC_CRS_IRQn
<>	144:ef7eb2e8f9f7	4642
<>	144:ef7eb2e8f9f7	4643	/* Aliases for __IRQHandler */
<>	144:ef7eb2e8f9f7	4644	#define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
<>	144:ef7eb2e8f9f7	4645	#define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
<>	144:ef7eb2e8f9f7	4646	#define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
<>	144:ef7eb2e8f9f7	4647	#define TIM6_IRQHandler TIM6_DAC_IRQHandler
<>	144:ef7eb2e8f9f7	4648	#define RCC_IRQHandler RCC_CRS_IRQHandler
<>	144:ef7eb2e8f9f7	4649
<>	144:ef7eb2e8f9f7	4650	/**
<>	144:ef7eb2e8f9f7	4651	* @}
<>	144:ef7eb2e8f9f7	4652	*/
<>	144:ef7eb2e8f9f7	4653
<>	144:ef7eb2e8f9f7	4654	/**
<>	144:ef7eb2e8f9f7	4655	* @}
<>	144:ef7eb2e8f9f7	4656	*/
<>	144:ef7eb2e8f9f7	4657
<>	144:ef7eb2e8f9f7	4658	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	4659	}
<>	144:ef7eb2e8f9f7	4660	#endif /* __cplusplus */
<>	144:ef7eb2e8f9f7	4661
<>	144:ef7eb2e8f9f7	4662	#endif /* __STM32L073xx_H */
<>	144:ef7eb2e8f9f7	4663
<>	144:ef7eb2e8f9f7	4664
<>	144:ef7eb2e8f9f7	4665
<>	144:ef7eb2e8f9f7	4666	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/