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mbed library sources. Supersedes mbed-src.

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targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_irda.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_irda.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief IRDA HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the IrDA SIR ENDEC block (IrDA):
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization methods
<> 144:ef7eb2e8f9f7 11 * + IO operation methods
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control methods
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 The IRDA HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 (#) Declare a IRDA_HandleTypeDef handle structure.
<> 144:ef7eb2e8f9f7 22 (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
<> 144:ef7eb2e8f9f7 23 (##) Enable the USARTx interface clock.
<> 144:ef7eb2e8f9f7 24 (##) IRDA pins configuration:
<> 144:ef7eb2e8f9f7 25 (+++) Enable the clock for the IRDA GPIOs.
<> 144:ef7eb2e8f9f7 26 (+++) Configure these IRDA pins as alternate function pull-up.
<> 144:ef7eb2e8f9f7 27 (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 28 and HAL_IRDA_Receive_IT() APIs):
<> 144:ef7eb2e8f9f7 29 (+++) Configure the USARTx interrupt priority.
<> 144:ef7eb2e8f9f7 30 (+++) Enable the NVIC USART IRQ handle.
<> 144:ef7eb2e8f9f7 31 (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 32 and HAL_IRDA_Receive_DMA() APIs):
<> 144:ef7eb2e8f9f7 33 (+++) Declare a DMA handle structure for the Tx/Rx stream.
<> 144:ef7eb2e8f9f7 34 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 35 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 36 (+++) Configure the DMA Tx/Rx Stream.
<> 144:ef7eb2e8f9f7 37 (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 38 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
<> 144:ef7eb2e8f9f7 41 and Mode(Receiver/Transmitter) in the hirda Init structure.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
<> 144:ef7eb2e8f9f7 44 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 45 by calling the customized HAL_IRDA_MspInit() API.
<> 144:ef7eb2e8f9f7 46 -@@- The specific IRDA interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 47 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 48 __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 (#) Three operation modes are available within this driver :
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 53 =================================
<> 144:ef7eb2e8f9f7 54 [..]
<> 144:ef7eb2e8f9f7 55 (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
<> 144:ef7eb2e8f9f7 56 (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 59 ===================================
<> 144:ef7eb2e8f9f7 60 [..]
<> 144:ef7eb2e8f9f7 61 (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 62 (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 63 add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
<> 144:ef7eb2e8f9f7 64 (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 65 (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 66 add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
<> 144:ef7eb2e8f9f7 67 (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 68 add his own code by customization of function pointer HAL_IRDA_ErrorCallback
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 71 =============================
<> 144:ef7eb2e8f9f7 72 [..]
<> 144:ef7eb2e8f9f7 73 (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 74 (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 75 add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
<> 144:ef7eb2e8f9f7 76 (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
<> 144:ef7eb2e8f9f7 77 (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 78 add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
<> 144:ef7eb2e8f9f7 79 (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 80 add his own code by customization of function pointer HAL_IRDA_ErrorCallback
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 *** IRDA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 83 ===================================
<> 144:ef7eb2e8f9f7 84 [..]
<> 144:ef7eb2e8f9f7 85 Below the list of most used macros in IRDA HAL driver.
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
<> 144:ef7eb2e8f9f7 88 (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
<> 144:ef7eb2e8f9f7 89 (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
<> 144:ef7eb2e8f9f7 90 (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
<> 144:ef7eb2e8f9f7 91 (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
<> 144:ef7eb2e8f9f7 92 (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 (@) You can refer to the IRDA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 @endverbatim
<> 144:ef7eb2e8f9f7 97 ******************************************************************************
<> 144:ef7eb2e8f9f7 98 * @attention
<> 144:ef7eb2e8f9f7 99 *
<> 144:ef7eb2e8f9f7 100 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 101 *
<> 144:ef7eb2e8f9f7 102 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 103 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 104 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 105 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 106 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 107 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 108 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 109 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 110 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 111 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 112 *
<> 144:ef7eb2e8f9f7 113 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 114 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 115 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 116 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 117 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 118 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 119 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 120 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 121 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 122 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 123 *
<> 144:ef7eb2e8f9f7 124 ******************************************************************************
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 128 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @defgroup IRDA IRDA
<> 144:ef7eb2e8f9f7 135 * @brief HAL IRDA module driver
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 #ifdef HAL_IRDA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 142 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /** @addtogroup IRDA_Private_Constants
<> 144:ef7eb2e8f9f7 144 * @{
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146 /**
<> 144:ef7eb2e8f9f7 147 * @}
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 150 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 151 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 152 /** @addtogroup IRDA_Private_Functions
<> 144:ef7eb2e8f9f7 153 * @{
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155 static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 156 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 157 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 158 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 159 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 160 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 161 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 162 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 163 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 164 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 165 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart,uint32_t Timeout);
<> 144:ef7eb2e8f9f7 166 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 167 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @}
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 172 /** @defgroup IRDA_Exported_Functions IrDA Exported Functions
<> 144:ef7eb2e8f9f7 173 * @{
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 177 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 178 *
<> 144:ef7eb2e8f9f7 179 @verbatim
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 ===============================================================================
<> 144:ef7eb2e8f9f7 182 ##### Initialization and Configuration functions #####
<> 144:ef7eb2e8f9f7 183 ===============================================================================
<> 144:ef7eb2e8f9f7 184 [..]
<> 144:ef7eb2e8f9f7 185 This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
<> 144:ef7eb2e8f9f7 186 in IrDA mode.
<> 144:ef7eb2e8f9f7 187 (+) For the asynchronous mode only these parameters can be configured:
<> 144:ef7eb2e8f9f7 188 (++) BaudRate
<> 144:ef7eb2e8f9f7 189 (++) WordLength
<> 144:ef7eb2e8f9f7 190 (++) Parity: If the parity is enabled, then the MSB bit of the data written
<> 144:ef7eb2e8f9f7 191 in the data register is transmitted but is changed by the parity bit.
<> 144:ef7eb2e8f9f7 192 Depending on the frame length defined by the M bit (8-bits or 9-bits),
<> 144:ef7eb2e8f9f7 193 please refer to Reference manual for possible IRDA frame formats.
<> 144:ef7eb2e8f9f7 194 (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
<> 144:ef7eb2e8f9f7 195 not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
<> 144:ef7eb2e8f9f7 196 specification specifies a minimum of 10 ms delay between transmission and
<> 144:ef7eb2e8f9f7 197 reception (IrDA is a half duplex protocol).
<> 144:ef7eb2e8f9f7 198 (++) Mode: Receiver/transmitter modes
<> 144:ef7eb2e8f9f7 199 (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
<> 144:ef7eb2e8f9f7 200 [..]
<> 144:ef7eb2e8f9f7 201 The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
<> 144:ef7eb2e8f9f7 202 are available in reference manual).
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 @endverbatim
<> 144:ef7eb2e8f9f7 205 * @{
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @brief Initializes the IRDA mode according to the specified
<> 144:ef7eb2e8f9f7 210 * parameters in the IRDA_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 211 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 212 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 213 * @retval HAL status
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 216 {
<> 144:ef7eb2e8f9f7 217 /* Check the IRDA handle allocation */
<> 144:ef7eb2e8f9f7 218 if(hirda == NULL)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Check the IRDA instance parameters */
<> 144:ef7eb2e8f9f7 224 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 225 /* Check the IRDA mode parameter in the IRDA handle */
<> 144:ef7eb2e8f9f7 226 assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 if(hirda->gState == HAL_IRDA_STATE_RESET)
<> 144:ef7eb2e8f9f7 229 {
<> 144:ef7eb2e8f9f7 230 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 231 hirda->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 232 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
<> 144:ef7eb2e8f9f7 233 HAL_IRDA_MspInit(hirda);
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 hirda->gState = HAL_IRDA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Disable the IRDA peripheral */
<> 144:ef7eb2e8f9f7 239 __HAL_IRDA_DISABLE(hirda);
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /* Set the IRDA communication parameters */
<> 144:ef7eb2e8f9f7 242 IRDA_SetConfig(hirda);
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* In IrDA mode, the following bits must be kept cleared:
<> 144:ef7eb2e8f9f7 245 - LINEN, STOP and CLKEN bits in the USART_CR2 register,
<> 144:ef7eb2e8f9f7 246 - SCEN and HDSEL bits in the USART_CR3 register.*/
<> 144:ef7eb2e8f9f7 247 CLEAR_BIT(hirda->Instance->CR3, USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN);
<> 144:ef7eb2e8f9f7 248 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_SCEN | USART_CR3_HDSEL);
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /* Enable the IRDA peripheral */
<> 144:ef7eb2e8f9f7 251 __HAL_IRDA_ENABLE(hirda);
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Set the prescaler */
<> 144:ef7eb2e8f9f7 254 MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Configure the IrDA mode */
<> 144:ef7eb2e8f9f7 257 MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode);
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
<> 144:ef7eb2e8f9f7 260 SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Initialize the IRDA state*/
<> 144:ef7eb2e8f9f7 263 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 264 hirda->gState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 265 hirda->RxState= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 return HAL_OK;
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /**
<> 144:ef7eb2e8f9f7 271 * @brief DeInitializes the IRDA peripheral
<> 144:ef7eb2e8f9f7 272 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 273 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 274 * @retval HAL status
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 /* Check the IRDA handle allocation */
<> 144:ef7eb2e8f9f7 279 if(hirda == NULL)
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /* Check the parameters */
<> 144:ef7eb2e8f9f7 285 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 hirda->gState = HAL_IRDA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 290 __HAL_IRDA_DISABLE(hirda);
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 293 HAL_IRDA_MspDeInit(hirda);
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 hirda->gState = HAL_IRDA_STATE_RESET;
<> 144:ef7eb2e8f9f7 298 hirda->RxState = HAL_IRDA_STATE_RESET;
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Release Lock */
<> 144:ef7eb2e8f9f7 301 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 return HAL_OK;
<> 144:ef7eb2e8f9f7 304 }
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /**
<> 144:ef7eb2e8f9f7 307 * @brief IRDA MSP Init.
<> 144:ef7eb2e8f9f7 308 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 309 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 310 * @retval None
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 315 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 316 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 317 the HAL_IRDA_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /**
<> 144:ef7eb2e8f9f7 322 * @brief IRDA MSP DeInit.
<> 144:ef7eb2e8f9f7 323 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 324 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 325 * @retval None
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 328 {
<> 144:ef7eb2e8f9f7 329 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 330 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 331 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 332 the HAL_IRDA_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /**
<> 144:ef7eb2e8f9f7 337 * @}
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 341 * @brief IRDA Transmit/Receive functions
<> 144:ef7eb2e8f9f7 342 *
<> 144:ef7eb2e8f9f7 343 @verbatim
<> 144:ef7eb2e8f9f7 344 ===============================================================================
<> 144:ef7eb2e8f9f7 345 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 346 ===============================================================================
<> 144:ef7eb2e8f9f7 347 This subsection provides a set of functions allowing to manage the IRDA data transfers.
<> 144:ef7eb2e8f9f7 348 [..]
<> 144:ef7eb2e8f9f7 349 IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
<> 144:ef7eb2e8f9f7 350 on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
<> 144:ef7eb2e8f9f7 351 is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
<> 144:ef7eb2e8f9f7 352 While receiving data, transmission should be avoided as the data to be transmitted
<> 144:ef7eb2e8f9f7 353 could be corrupted.
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 356 (++) Blocking mode: The communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 357 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 358 after finishing transfer.
<> 144:ef7eb2e8f9f7 359 (++) No-Blocking mode: The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 360 or DMA, These APIs return the HAL status.
<> 144:ef7eb2e8f9f7 361 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 362 dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 363 using DMA mode.
<> 144:ef7eb2e8f9f7 364 The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 365 will be executed respectively at the end of the transmit or Receive process
<> 144:ef7eb2e8f9f7 366 The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 (#) Blocking mode API's are :
<> 144:ef7eb2e8f9f7 369 (++) HAL_IRDA_Transmit()
<> 144:ef7eb2e8f9f7 370 (++) HAL_IRDA_Receive()
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 (#) Non Blocking mode APIs with Interrupt are :
<> 144:ef7eb2e8f9f7 373 (++) HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 374 (++) HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 375 (++) HAL_IRDA_IRQHandler()
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 (#) Non Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 378 (++) HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 379 (++) HAL_IRDA_Receive_DMA()
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<> 144:ef7eb2e8f9f7 382 (++) HAL_IRDA_TxCpltCallback()
<> 144:ef7eb2e8f9f7 383 (++) HAL_IRDA_RxCpltCallback()
<> 144:ef7eb2e8f9f7 384 (++) HAL_IRDA_ErrorCallback()
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 @endverbatim
<> 144:ef7eb2e8f9f7 387 * @{
<> 144:ef7eb2e8f9f7 388 */
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /**
<> 144:ef7eb2e8f9f7 391 * @brief Sends an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 392 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 393 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 394 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 395 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 396 * @param Timeout: Specify timeout value
<> 144:ef7eb2e8f9f7 397 * @retval HAL status
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 402 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 405 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 406 {
<> 144:ef7eb2e8f9f7 407 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 408 {
<> 144:ef7eb2e8f9f7 409 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 410 }
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Process Locked */
<> 144:ef7eb2e8f9f7 413 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 416 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Init tickstart for timeout managment*/
<> 144:ef7eb2e8f9f7 419 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 422 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 423 while(hirda->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 hirda->TxXferCount--;
<> 144:ef7eb2e8f9f7 426 if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
<> 144:ef7eb2e8f9f7 427 {
<> 144:ef7eb2e8f9f7 428 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 429 {
<> 144:ef7eb2e8f9f7 430 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432 tmp = (uint16_t*) pData;
<> 144:ef7eb2e8f9f7 433 hirda->Instance->DR = (*tmp & (uint16_t)0x01FFU);
<> 144:ef7eb2e8f9f7 434 if(hirda->Init.Parity == IRDA_PARITY_NONE)
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 pData +=2U;
<> 144:ef7eb2e8f9f7 437 }
<> 144:ef7eb2e8f9f7 438 else
<> 144:ef7eb2e8f9f7 439 {
<> 144:ef7eb2e8f9f7 440 pData +=1U;
<> 144:ef7eb2e8f9f7 441 }
<> 144:ef7eb2e8f9f7 442 }
<> 144:ef7eb2e8f9f7 443 else
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 446 {
<> 144:ef7eb2e8f9f7 447 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 448 }
<> 144:ef7eb2e8f9f7 449 hirda->Instance->DR = (*pData++ & (uint8_t)0xFFU);
<> 144:ef7eb2e8f9f7 450 }
<> 144:ef7eb2e8f9f7 451 }
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* At end of Tx process, restore hirda->gState to Ready */
<> 144:ef7eb2e8f9f7 459 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 462 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 return HAL_OK;
<> 144:ef7eb2e8f9f7 465 }
<> 144:ef7eb2e8f9f7 466 else
<> 144:ef7eb2e8f9f7 467 {
<> 144:ef7eb2e8f9f7 468 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 469 }
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /**
<> 144:ef7eb2e8f9f7 473 * @brief Receive an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 474 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 475 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 476 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 477 * @param Size: Amount of data to be received
<> 144:ef7eb2e8f9f7 478 * @param Timeout: Specify timeout value
<> 144:ef7eb2e8f9f7 479 * @retval HAL status
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 482 {
<> 144:ef7eb2e8f9f7 483 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 484 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 487 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 488 {
<> 144:ef7eb2e8f9f7 489 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 492 }
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Process Locked */
<> 144:ef7eb2e8f9f7 495 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 498 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /* Init tickstart for timeout managment*/
<> 144:ef7eb2e8f9f7 501 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 504 hirda->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 505 /* Check the remain data to be received */
<> 144:ef7eb2e8f9f7 506 while(hirda->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 507 {
<> 144:ef7eb2e8f9f7 508 hirda->RxXferCount--;
<> 144:ef7eb2e8f9f7 509 if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
<> 144:ef7eb2e8f9f7 510 {
<> 144:ef7eb2e8f9f7 511 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 512 {
<> 144:ef7eb2e8f9f7 513 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 514 }
<> 144:ef7eb2e8f9f7 515 tmp = (uint16_t*) pData ;
<> 144:ef7eb2e8f9f7 516 if(hirda->Init.Parity == IRDA_PARITY_NONE)
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FFU);
<> 144:ef7eb2e8f9f7 519 pData +=2U;
<> 144:ef7eb2e8f9f7 520 }
<> 144:ef7eb2e8f9f7 521 else
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FFU);
<> 144:ef7eb2e8f9f7 524 pData +=1U;
<> 144:ef7eb2e8f9f7 525 }
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527 else
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 530 {
<> 144:ef7eb2e8f9f7 531 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 532 }
<> 144:ef7eb2e8f9f7 533 if(hirda->Init.Parity == IRDA_PARITY_NONE)
<> 144:ef7eb2e8f9f7 534 {
<> 144:ef7eb2e8f9f7 535 *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FFU);
<> 144:ef7eb2e8f9f7 536 }
<> 144:ef7eb2e8f9f7 537 else
<> 144:ef7eb2e8f9f7 538 {
<> 144:ef7eb2e8f9f7 539 *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007FU);
<> 144:ef7eb2e8f9f7 540 }
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /* At end of Rx process, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 545 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 548 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 return HAL_OK;
<> 144:ef7eb2e8f9f7 551 }
<> 144:ef7eb2e8f9f7 552 else
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /**
<> 144:ef7eb2e8f9f7 559 * @brief Send an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 560 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 561 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 562 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 563 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 564 * @retval HAL status
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 567 {
<> 144:ef7eb2e8f9f7 568 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 569 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575 /* Process Locked */
<> 144:ef7eb2e8f9f7 576 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 hirda->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 579 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 580 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 581 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 582 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 585 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /* Enable the IRDA Transmit Data Register Empty Interrupt */
<> 144:ef7eb2e8f9f7 588 SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 return HAL_OK;
<> 144:ef7eb2e8f9f7 591 }
<> 144:ef7eb2e8f9f7 592 else
<> 144:ef7eb2e8f9f7 593 {
<> 144:ef7eb2e8f9f7 594 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /**
<> 144:ef7eb2e8f9f7 599 * @brief Receives an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 600 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 601 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 602 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 603 * @param Size: Amount of data to be received
<> 144:ef7eb2e8f9f7 604 * @retval HAL status
<> 144:ef7eb2e8f9f7 605 */
<> 144:ef7eb2e8f9f7 606 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 607 {
<> 144:ef7eb2e8f9f7 608 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 609 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 610 {
<> 144:ef7eb2e8f9f7 611 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 612 {
<> 144:ef7eb2e8f9f7 613 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 614 }
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /* Process Locked */
<> 144:ef7eb2e8f9f7 617 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 hirda->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 620 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 621 hirda->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 622 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 623 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 626 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
<> 144:ef7eb2e8f9f7 629 SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 632 SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 return HAL_OK;
<> 144:ef7eb2e8f9f7 635 }
<> 144:ef7eb2e8f9f7 636 else
<> 144:ef7eb2e8f9f7 637 {
<> 144:ef7eb2e8f9f7 638 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640 }
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /**
<> 144:ef7eb2e8f9f7 643 * @brief Sends an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 644 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 645 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 646 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 647 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 648 * @retval HAL status
<> 144:ef7eb2e8f9f7 649 */
<> 144:ef7eb2e8f9f7 650 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 655 if(hirda->gState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* Process Locked */
<> 144:ef7eb2e8f9f7 663 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 hirda->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 666 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 667 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 668 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 669 hirda->gState = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Set the IRDA DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 672 hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /* Set the IRDA DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 675 hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 678 hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /* Set the DMA abort callback */
<> 144:ef7eb2e8f9f7 681 hirda->hdmatx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /* Enable the IRDA transmit DMA Stream */
<> 144:ef7eb2e8f9f7 684 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 685 HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* Clear the TC flag in the SR register by writing 0 to it */
<> 144:ef7eb2e8f9f7 688 __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 691 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /* Enable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 694 in the USART CR3 register */
<> 144:ef7eb2e8f9f7 695 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 return HAL_OK;
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699 else
<> 144:ef7eb2e8f9f7 700 {
<> 144:ef7eb2e8f9f7 701 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /**
<> 144:ef7eb2e8f9f7 706 * @brief Receives an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 707 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 708 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 709 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 710 * @param Size: Amount of data to be received
<> 144:ef7eb2e8f9f7 711 * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
<> 144:ef7eb2e8f9f7 712 * @retval HAL status
<> 144:ef7eb2e8f9f7 713 */
<> 144:ef7eb2e8f9f7 714 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 715 {
<> 144:ef7eb2e8f9f7 716 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 719 if(hirda->RxState == HAL_IRDA_STATE_READY)
<> 144:ef7eb2e8f9f7 720 {
<> 144:ef7eb2e8f9f7 721 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 724 }
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /* Process Locked */
<> 144:ef7eb2e8f9f7 727 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 hirda->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 730 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 731 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 732 hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Set the IRDA DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 735 hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /* Set the IRDA DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 738 hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 741 hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Set the DMA abort callback */
<> 144:ef7eb2e8f9f7 744 hirda->hdmarx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 747 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 748 HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 751 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /* Enable the IRDA Parity Error Interrupt */
<> 144:ef7eb2e8f9f7 754 SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 757 SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /* Enable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 760 in the USART CR3 register */
<> 144:ef7eb2e8f9f7 761 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 return HAL_OK;
<> 144:ef7eb2e8f9f7 764 }
<> 144:ef7eb2e8f9f7 765 else
<> 144:ef7eb2e8f9f7 766 {
<> 144:ef7eb2e8f9f7 767 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 768 }
<> 144:ef7eb2e8f9f7 769 }
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /**
<> 144:ef7eb2e8f9f7 772 * @brief Pauses the DMA Transfer.
<> 144:ef7eb2e8f9f7 773 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 774 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 775 * @retval HAL status
<> 144:ef7eb2e8f9f7 776 */
<> 144:ef7eb2e8f9f7 777 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 778 {
<> 144:ef7eb2e8f9f7 779 uint32_t dmarequest = 0x00U;
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /* Process Locked */
<> 144:ef7eb2e8f9f7 782 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 785 if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
<> 144:ef7eb2e8f9f7 786 {
<> 144:ef7eb2e8f9f7 787 /* Disable the IRDA DMA Tx request */
<> 144:ef7eb2e8f9f7 788 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 792 if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
<> 144:ef7eb2e8f9f7 793 {
<> 144:ef7eb2e8f9f7 794 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 144:ef7eb2e8f9f7 795 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 796 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 /* Disable the IRDA DMA Rx request */
<> 144:ef7eb2e8f9f7 799 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 800 }
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 803 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 return HAL_OK;
<> 144:ef7eb2e8f9f7 806 }
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /**
<> 144:ef7eb2e8f9f7 809 * @brief Resumes the DMA Transfer.
<> 144:ef7eb2e8f9f7 810 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 811 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 812 * @retval HAL status
<> 144:ef7eb2e8f9f7 813 */
<> 144:ef7eb2e8f9f7 814 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 815 {
<> 144:ef7eb2e8f9f7 816 /* Process Locked */
<> 144:ef7eb2e8f9f7 817 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 820 {
<> 144:ef7eb2e8f9f7 821 /* Enable the IRDA DMA Tx request */
<> 144:ef7eb2e8f9f7 822 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824 if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 /* Clear the Overrun flag before resuming the Rx transfer */
<> 144:ef7eb2e8f9f7 827 __HAL_IRDA_CLEAR_OREFLAG(hirda);
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 144:ef7eb2e8f9f7 830 SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 831 SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 /* Enable the IRDA DMA Rx request */
<> 144:ef7eb2e8f9f7 834 SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 835 }
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 838 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 return HAL_OK;
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /**
<> 144:ef7eb2e8f9f7 844 * @brief Stops the DMA Transfer.
<> 144:ef7eb2e8f9f7 845 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 846 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 847 * @retval HAL status
<> 144:ef7eb2e8f9f7 848 */
<> 144:ef7eb2e8f9f7 849 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 uint32_t dmarequest = 0x00U;
<> 144:ef7eb2e8f9f7 852 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 853 to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
<> 144:ef7eb2e8f9f7 854 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<> 144:ef7eb2e8f9f7 855 and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
<> 144:ef7eb2e8f9f7 856 */
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Stop IRDA DMA Tx request if ongoing */
<> 144:ef7eb2e8f9f7 859 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 860 if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
<> 144:ef7eb2e8f9f7 861 {
<> 144:ef7eb2e8f9f7 862 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /* Abort the IRDA DMA Tx channel */
<> 144:ef7eb2e8f9f7 865 if(hirda->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 866 {
<> 144:ef7eb2e8f9f7 867 HAL_DMA_Abort(hirda->hdmatx);
<> 144:ef7eb2e8f9f7 868 }
<> 144:ef7eb2e8f9f7 869 IRDA_EndTxTransfer(hirda);
<> 144:ef7eb2e8f9f7 870 }
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /* Stop IRDA DMA Rx request if ongoing */
<> 144:ef7eb2e8f9f7 873 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 874 if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
<> 144:ef7eb2e8f9f7 875 {
<> 144:ef7eb2e8f9f7 876 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /* Abort the IRDA DMA Rx channel */
<> 144:ef7eb2e8f9f7 879 if(hirda->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 880 {
<> 144:ef7eb2e8f9f7 881 HAL_DMA_Abort(hirda->hdmarx);
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883 IRDA_EndRxTransfer(hirda);
<> 144:ef7eb2e8f9f7 884 }
<> 144:ef7eb2e8f9f7 885 return HAL_OK;
<> 144:ef7eb2e8f9f7 886 }
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /**
<> 144:ef7eb2e8f9f7 889 * @brief This function handles IRDA interrupt request.
<> 144:ef7eb2e8f9f7 890 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 891 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 892 * @retval None
<> 144:ef7eb2e8f9f7 893 */
<> 144:ef7eb2e8f9f7 894 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 895 {
<> 144:ef7eb2e8f9f7 896 uint32_t isrflags = READ_REG(hirda->Instance->SR);
<> 144:ef7eb2e8f9f7 897 uint32_t cr1its = READ_REG(hirda->Instance->CR1);
<> 144:ef7eb2e8f9f7 898 uint32_t cr3its = READ_REG(hirda->Instance->CR3);
<> 144:ef7eb2e8f9f7 899 uint32_t errorflags = 0x00U;
<> 144:ef7eb2e8f9f7 900 uint32_t dmarequest = 0x00U;
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 /* If no error occurs */
<> 144:ef7eb2e8f9f7 903 errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
<> 144:ef7eb2e8f9f7 904 if(errorflags == RESET)
<> 144:ef7eb2e8f9f7 905 {
<> 144:ef7eb2e8f9f7 906 /* IRDA in mode Receiver -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 907 if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 144:ef7eb2e8f9f7 908 {
<> 144:ef7eb2e8f9f7 909 IRDA_Receive_IT(hirda);
<> 144:ef7eb2e8f9f7 910 return;
<> 144:ef7eb2e8f9f7 911 }
<> 144:ef7eb2e8f9f7 912 }
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 /* If some errors occur */
<> 144:ef7eb2e8f9f7 915 if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
<> 144:ef7eb2e8f9f7 916 {
<> 144:ef7eb2e8f9f7 917 /* IRDA parity error interrupt occurred -------------------------------*/
<> 144:ef7eb2e8f9f7 918 if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
<> 144:ef7eb2e8f9f7 919 {
<> 144:ef7eb2e8f9f7 920 hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
<> 144:ef7eb2e8f9f7 921 }
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 /* IRDA noise error interrupt occurred --------------------------------*/
<> 144:ef7eb2e8f9f7 924 if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 144:ef7eb2e8f9f7 925 {
<> 144:ef7eb2e8f9f7 926 hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* IRDA frame error interrupt occurred --------------------------------*/
<> 144:ef7eb2e8f9f7 930 if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 144:ef7eb2e8f9f7 931 {
<> 144:ef7eb2e8f9f7 932 hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
<> 144:ef7eb2e8f9f7 933 }
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /* IRDA Over-Run interrupt occurred -----------------------------------*/
<> 144:ef7eb2e8f9f7 936 if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 144:ef7eb2e8f9f7 937 {
<> 144:ef7eb2e8f9f7 938 hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
<> 144:ef7eb2e8f9f7 939 }
<> 144:ef7eb2e8f9f7 940 /* Call IRDA Error Call back function if need be -----------------------*/
<> 144:ef7eb2e8f9f7 941 if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
<> 144:ef7eb2e8f9f7 942 {
<> 144:ef7eb2e8f9f7 943 /* IRDA in mode Receiver ---------------------------------------------*/
<> 144:ef7eb2e8f9f7 944 if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 144:ef7eb2e8f9f7 945 {
<> 144:ef7eb2e8f9f7 946 IRDA_Receive_IT(hirda);
<> 144:ef7eb2e8f9f7 947 }
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 950 /* If Overrun error occurs, or if any error occurs in DMA mode reception,
<> 144:ef7eb2e8f9f7 951 consider error as blocking */
<> 144:ef7eb2e8f9f7 952 if(((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || dmarequest)
<> 144:ef7eb2e8f9f7 953 {
<> 144:ef7eb2e8f9f7 954 /* Blocking error : transfer is aborted
<> 144:ef7eb2e8f9f7 955 Set the IRDA state ready to be able to start again the process,
<> 144:ef7eb2e8f9f7 956 Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
<> 144:ef7eb2e8f9f7 957 IRDA_EndRxTransfer(hirda);
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /* Disable the IRDA DMA Rx request if enabled */
<> 144:ef7eb2e8f9f7 960 if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
<> 144:ef7eb2e8f9f7 961 {
<> 144:ef7eb2e8f9f7 962 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /* Abort the IRDA DMA Rx channel */
<> 144:ef7eb2e8f9f7 965 if(hirda->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 966 {
<> 144:ef7eb2e8f9f7 967 /* Set the IRDA DMA Abort callback :
<> 144:ef7eb2e8f9f7 968 will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
<> 144:ef7eb2e8f9f7 969 hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
<> 144:ef7eb2e8f9f7 972 {
<> 144:ef7eb2e8f9f7 973 /* Call Directly XferAbortCallback function in case of error */
<> 144:ef7eb2e8f9f7 974 hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
<> 144:ef7eb2e8f9f7 975 }
<> 144:ef7eb2e8f9f7 976 }
<> 144:ef7eb2e8f9f7 977 else
<> 144:ef7eb2e8f9f7 978 {
<> 144:ef7eb2e8f9f7 979 /* Call user error callback */
<> 144:ef7eb2e8f9f7 980 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 981 }
<> 144:ef7eb2e8f9f7 982 }
<> 144:ef7eb2e8f9f7 983 else
<> 144:ef7eb2e8f9f7 984 {
<> 144:ef7eb2e8f9f7 985 /* Call user error callback */
<> 144:ef7eb2e8f9f7 986 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 987 }
<> 144:ef7eb2e8f9f7 988 }
<> 144:ef7eb2e8f9f7 989 else
<> 144:ef7eb2e8f9f7 990 {
<> 144:ef7eb2e8f9f7 991 /* Non Blocking error : transfer could go on.
<> 144:ef7eb2e8f9f7 992 Error is notified to user through user error callback */
<> 144:ef7eb2e8f9f7 993 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 994 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997 return;
<> 144:ef7eb2e8f9f7 998 } /* End if some error occurs */
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 /* IRDA in mode Transmitter ------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1001 if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
<> 144:ef7eb2e8f9f7 1002 {
<> 144:ef7eb2e8f9f7 1003 IRDA_Transmit_IT(hirda);
<> 144:ef7eb2e8f9f7 1004 return;
<> 144:ef7eb2e8f9f7 1005 }
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* IRDA in mode Transmitter end --------------------------------------------*/
<> 144:ef7eb2e8f9f7 1008 if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
<> 144:ef7eb2e8f9f7 1009 {
<> 144:ef7eb2e8f9f7 1010 IRDA_EndTransmit_IT(hirda);
<> 144:ef7eb2e8f9f7 1011 return;
<> 144:ef7eb2e8f9f7 1012 }
<> 144:ef7eb2e8f9f7 1013 }
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 /**
<> 144:ef7eb2e8f9f7 1016 * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
<> 144:ef7eb2e8f9f7 1017 * @param hirda: IRDA handle.
<> 144:ef7eb2e8f9f7 1018 * @retval None
<> 144:ef7eb2e8f9f7 1019 */
<> 144:ef7eb2e8f9f7 1020 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1021 {
<> 144:ef7eb2e8f9f7 1022 /* Disable TXEIE and TCIE interrupts */
<> 144:ef7eb2e8f9f7 1023 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /* At end of Tx process, restore hirda->gState to Ready */
<> 144:ef7eb2e8f9f7 1026 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1027 }
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /**
<> 144:ef7eb2e8f9f7 1030 * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
<> 144:ef7eb2e8f9f7 1031 * @param hirda: IRDA handle.
<> 144:ef7eb2e8f9f7 1032 * @retval None
<> 144:ef7eb2e8f9f7 1033 */
<> 144:ef7eb2e8f9f7 1034 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1035 {
<> 144:ef7eb2e8f9f7 1036 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 144:ef7eb2e8f9f7 1037 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 144:ef7eb2e8f9f7 1038 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1039
<> 144:ef7eb2e8f9f7 1040 /* At end of Rx process, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 1041 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1042 }
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 /**
<> 144:ef7eb2e8f9f7 1045 * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
<> 144:ef7eb2e8f9f7 1046 * (To be called at end of DMA Abort procedure following error occurrence).
<> 144:ef7eb2e8f9f7 1047 * @param hdma DMA handle.
<> 144:ef7eb2e8f9f7 1048 * @retval None
<> 144:ef7eb2e8f9f7 1049 */
<> 144:ef7eb2e8f9f7 1050 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1051 {
<> 144:ef7eb2e8f9f7 1052 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1053 hirda->RxXferCount = 0x00U;
<> 144:ef7eb2e8f9f7 1054 hirda->TxXferCount = 0x00U;
<> 144:ef7eb2e8f9f7 1055
<> 144:ef7eb2e8f9f7 1056 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 1057 }
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 /**
<> 144:ef7eb2e8f9f7 1060 * @brief Tx Transfer complete callbacks.
<> 144:ef7eb2e8f9f7 1061 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1062 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1063 * @retval None
<> 144:ef7eb2e8f9f7 1064 */
<> 144:ef7eb2e8f9f7 1065 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1066 {
<> 144:ef7eb2e8f9f7 1067 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1068 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1069 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1070 the HAL_IRDA_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1071 */
<> 144:ef7eb2e8f9f7 1072 }
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 /**
<> 144:ef7eb2e8f9f7 1075 * @brief Tx Half Transfer completed callbacks.
<> 144:ef7eb2e8f9f7 1076 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1077 * the configuration information for the specified USART module.
<> 144:ef7eb2e8f9f7 1078 * @retval None
<> 144:ef7eb2e8f9f7 1079 */
<> 144:ef7eb2e8f9f7 1080 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1081 {
<> 144:ef7eb2e8f9f7 1082 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1083 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1084 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1085 the HAL_IRDA_TxHalfCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1086 */
<> 144:ef7eb2e8f9f7 1087 }
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089 /**
<> 144:ef7eb2e8f9f7 1090 * @brief Rx Transfer complete callbacks.
<> 144:ef7eb2e8f9f7 1091 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1092 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1093 * @retval None
<> 144:ef7eb2e8f9f7 1094 */
<> 144:ef7eb2e8f9f7 1095 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1096 {
<> 144:ef7eb2e8f9f7 1097 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1098 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1099 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1100 the HAL_IRDA_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1101 */
<> 144:ef7eb2e8f9f7 1102 }
<> 144:ef7eb2e8f9f7 1103
<> 144:ef7eb2e8f9f7 1104 /**
<> 144:ef7eb2e8f9f7 1105 * @brief Rx Half Transfer complete callbacks.
<> 144:ef7eb2e8f9f7 1106 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1107 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1108 * @retval None
<> 144:ef7eb2e8f9f7 1109 */
<> 144:ef7eb2e8f9f7 1110 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1111 {
<> 144:ef7eb2e8f9f7 1112 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1113 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1114 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1115 the HAL_IRDA_RxHalfCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1116 */
<> 144:ef7eb2e8f9f7 1117 }
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 /**
<> 144:ef7eb2e8f9f7 1120 * @brief IRDA error callbacks.
<> 144:ef7eb2e8f9f7 1121 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1122 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1123 * @retval None
<> 144:ef7eb2e8f9f7 1124 */
<> 144:ef7eb2e8f9f7 1125 __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1126 {
<> 144:ef7eb2e8f9f7 1127 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1128 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1129 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1130 the HAL_IRDA_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1131 */
<> 144:ef7eb2e8f9f7 1132 }
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 /**
<> 144:ef7eb2e8f9f7 1135 * @}
<> 144:ef7eb2e8f9f7 1136 */
<> 144:ef7eb2e8f9f7 1137
<> 144:ef7eb2e8f9f7 1138 /** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1139 * @brief IRDA State and Errors functions
<> 144:ef7eb2e8f9f7 1140 *
<> 144:ef7eb2e8f9f7 1141 @verbatim
<> 144:ef7eb2e8f9f7 1142 ==============================================================================
<> 144:ef7eb2e8f9f7 1143 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1144 ==============================================================================
<> 144:ef7eb2e8f9f7 1145 [..]
<> 144:ef7eb2e8f9f7 1146 This subsection provides a set of functions allowing to return the State of IrDA
<> 144:ef7eb2e8f9f7 1147 communication process and also return Peripheral Errors occurred during communication process
<> 144:ef7eb2e8f9f7 1148 (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
<> 144:ef7eb2e8f9f7 1149 (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.
<> 144:ef7eb2e8f9f7 1150
<> 144:ef7eb2e8f9f7 1151 @endverbatim
<> 144:ef7eb2e8f9f7 1152 * @{
<> 144:ef7eb2e8f9f7 1153 */
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /**
<> 144:ef7eb2e8f9f7 1156 * @brief Returns the IRDA state.
<> 144:ef7eb2e8f9f7 1157 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1158 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1159 * @retval HAL state
<> 144:ef7eb2e8f9f7 1160 */
<> 144:ef7eb2e8f9f7 1161 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1162 {
<> 144:ef7eb2e8f9f7 1163 uint32_t temp1 = 0x00U, temp2 = 0x00U;
<> 144:ef7eb2e8f9f7 1164 temp1 = hirda->gState;
<> 144:ef7eb2e8f9f7 1165 temp2 = hirda->RxState;
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
<> 144:ef7eb2e8f9f7 1168 }
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 /**
<> 144:ef7eb2e8f9f7 1171 * @brief Return the IARDA error code
<> 144:ef7eb2e8f9f7 1172 * @param hirda : pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1173 * the configuration information for the specified IRDA.
<> 144:ef7eb2e8f9f7 1174 * @retval IRDA Error Code
<> 144:ef7eb2e8f9f7 1175 */
<> 144:ef7eb2e8f9f7 1176 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1177 {
<> 144:ef7eb2e8f9f7 1178 return hirda->ErrorCode;
<> 144:ef7eb2e8f9f7 1179 }
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 /**
<> 144:ef7eb2e8f9f7 1182 * @}
<> 144:ef7eb2e8f9f7 1183 */
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 /**
<> 144:ef7eb2e8f9f7 1186 * @brief DMA IRDA transmit process complete callback.
<> 144:ef7eb2e8f9f7 1187 * @param hdma : DMA handle
<> 144:ef7eb2e8f9f7 1188 * @retval None
<> 144:ef7eb2e8f9f7 1189 */
<> 144:ef7eb2e8f9f7 1190 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1191 {
<> 144:ef7eb2e8f9f7 1192 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1193 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 1194 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 1195 {
<> 144:ef7eb2e8f9f7 1196 hirda->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 /* Disable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 1199 in the IRDA CR3 register */
<> 144:ef7eb2e8f9f7 1200 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202 /* Enable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1203 SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 1204 }
<> 144:ef7eb2e8f9f7 1205 /* DMA Circular mode */
<> 144:ef7eb2e8f9f7 1206 else
<> 144:ef7eb2e8f9f7 1207 {
<> 144:ef7eb2e8f9f7 1208 HAL_IRDA_TxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1209 }
<> 144:ef7eb2e8f9f7 1210 }
<> 144:ef7eb2e8f9f7 1211
<> 144:ef7eb2e8f9f7 1212 /**
<> 144:ef7eb2e8f9f7 1213 * @brief DMA IRDA receive process half complete callback
<> 144:ef7eb2e8f9f7 1214 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1215 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1216 * @retval None
<> 144:ef7eb2e8f9f7 1217 */
<> 144:ef7eb2e8f9f7 1218 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1219 {
<> 144:ef7eb2e8f9f7 1220 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 HAL_IRDA_TxHalfCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1223 }
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /**
<> 144:ef7eb2e8f9f7 1226 * @brief DMA IRDA receive process complete callback.
<> 144:ef7eb2e8f9f7 1227 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 1228 * @retval None
<> 144:ef7eb2e8f9f7 1229 */
<> 144:ef7eb2e8f9f7 1230 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1231 {
<> 144:ef7eb2e8f9f7 1232 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1233 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 1234 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 1235 {
<> 144:ef7eb2e8f9f7 1236 hirda->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1237
<> 144:ef7eb2e8f9f7 1238 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 144:ef7eb2e8f9f7 1239 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 1240 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1241
<> 144:ef7eb2e8f9f7 1242 /* Disable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 1243 in the IRDA CR3 register */
<> 144:ef7eb2e8f9f7 1244 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 /* At end of Rx process, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 1247 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1248 }
<> 144:ef7eb2e8f9f7 1249
<> 144:ef7eb2e8f9f7 1250 HAL_IRDA_RxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1251 }
<> 144:ef7eb2e8f9f7 1252
<> 144:ef7eb2e8f9f7 1253 /**
<> 144:ef7eb2e8f9f7 1254 * @brief DMA IRDA receive process half complete callback
<> 144:ef7eb2e8f9f7 1255 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1256 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1257 * @retval None
<> 144:ef7eb2e8f9f7 1258 */
<> 144:ef7eb2e8f9f7 1259 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1260 {
<> 144:ef7eb2e8f9f7 1261 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1262 HAL_IRDA_RxHalfCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1263 }
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 /**
<> 144:ef7eb2e8f9f7 1266 * @brief DMA IRDA communication error callback.
<> 144:ef7eb2e8f9f7 1267 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 1268 * @retval None
<> 144:ef7eb2e8f9f7 1269 */
<> 144:ef7eb2e8f9f7 1270 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1271 {
<> 144:ef7eb2e8f9f7 1272 uint32_t dmarequest = 0x00U;
<> 144:ef7eb2e8f9f7 1273 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /* Stop IRDA DMA Tx request if ongoing */
<> 144:ef7eb2e8f9f7 1276 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1277 if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
<> 144:ef7eb2e8f9f7 1278 {
<> 144:ef7eb2e8f9f7 1279 hirda->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1280 IRDA_EndTxTransfer(hirda);
<> 144:ef7eb2e8f9f7 1281 }
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 /* Stop IRDA DMA Rx request if ongoing */
<> 144:ef7eb2e8f9f7 1284 dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1285 if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
<> 144:ef7eb2e8f9f7 1286 {
<> 144:ef7eb2e8f9f7 1287 hirda->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1288 IRDA_EndRxTransfer(hirda);
<> 144:ef7eb2e8f9f7 1289 }
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1292
<> 144:ef7eb2e8f9f7 1293 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 1294 }
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 /**
<> 144:ef7eb2e8f9f7 1297 * @brief This function handles IRDA Communication Timeout.
<> 144:ef7eb2e8f9f7 1298 * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1299 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1300 * @param Flag specifies the IRDA flag to check.
<> 144:ef7eb2e8f9f7 1301 * @param Status The new Flag status (SET or RESET).
<> 144:ef7eb2e8f9f7 1302 * @param Tickstart Tick start value
<> 144:ef7eb2e8f9f7 1303 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 1304 * @retval HAL status
<> 144:ef7eb2e8f9f7 1305 */
<> 144:ef7eb2e8f9f7 1306 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1307 {
<> 144:ef7eb2e8f9f7 1308 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 1309 while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
<> 144:ef7eb2e8f9f7 1310 {
<> 144:ef7eb2e8f9f7 1311 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1312 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1313 {
<> 144:ef7eb2e8f9f7 1314 if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1315 {
<> 144:ef7eb2e8f9f7 1316 /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 1317 CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
<> 144:ef7eb2e8f9f7 1318 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1319
<> 144:ef7eb2e8f9f7 1320 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1321 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1322
<> 144:ef7eb2e8f9f7 1323 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1324 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1327 }
<> 144:ef7eb2e8f9f7 1328 }
<> 144:ef7eb2e8f9f7 1329 }
<> 144:ef7eb2e8f9f7 1330 return HAL_OK;
<> 144:ef7eb2e8f9f7 1331 }
<> 144:ef7eb2e8f9f7 1332
<> 144:ef7eb2e8f9f7 1333 /**
<> 144:ef7eb2e8f9f7 1334 * @brief Send an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 1335 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1336 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1337 * @retval HAL status
<> 144:ef7eb2e8f9f7 1338 */
<> 144:ef7eb2e8f9f7 1339 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1340 {
<> 144:ef7eb2e8f9f7 1341 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /* Check that a Tx process is ongoing */
<> 144:ef7eb2e8f9f7 1344 if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1345 {
<> 144:ef7eb2e8f9f7 1346 if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
<> 144:ef7eb2e8f9f7 1347 {
<> 144:ef7eb2e8f9f7 1348 tmp = (uint16_t*) hirda->pTxBuffPtr;
<> 144:ef7eb2e8f9f7 1349 hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
<> 144:ef7eb2e8f9f7 1350 if(hirda->Init.Parity == IRDA_PARITY_NONE)
<> 144:ef7eb2e8f9f7 1351 {
<> 144:ef7eb2e8f9f7 1352 hirda->pTxBuffPtr += 2U;
<> 144:ef7eb2e8f9f7 1353 }
<> 144:ef7eb2e8f9f7 1354 else
<> 144:ef7eb2e8f9f7 1355 {
<> 144:ef7eb2e8f9f7 1356 hirda->pTxBuffPtr += 1U;
<> 144:ef7eb2e8f9f7 1357 }
<> 144:ef7eb2e8f9f7 1358 }
<> 144:ef7eb2e8f9f7 1359 else
<> 144:ef7eb2e8f9f7 1360 {
<> 144:ef7eb2e8f9f7 1361 hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FFU);
<> 144:ef7eb2e8f9f7 1362 }
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 if(--hirda->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 1365 {
<> 144:ef7eb2e8f9f7 1366 /* Disable the IRDA Transmit Data Register Empty Interrupt */
<> 144:ef7eb2e8f9f7 1367 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 /* Enable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1370 SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 1371 }
<> 144:ef7eb2e8f9f7 1372
<> 144:ef7eb2e8f9f7 1373 return HAL_OK;
<> 144:ef7eb2e8f9f7 1374 }
<> 144:ef7eb2e8f9f7 1375 else
<> 144:ef7eb2e8f9f7 1376 {
<> 144:ef7eb2e8f9f7 1377 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1378 }
<> 144:ef7eb2e8f9f7 1379 }
<> 144:ef7eb2e8f9f7 1380
<> 144:ef7eb2e8f9f7 1381 /**
<> 144:ef7eb2e8f9f7 1382 * @brief Wraps up transmission in non blocking mode.
<> 144:ef7eb2e8f9f7 1383 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1384 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1385 * @retval HAL status
<> 144:ef7eb2e8f9f7 1386 */
<> 144:ef7eb2e8f9f7 1387 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1388 {
<> 144:ef7eb2e8f9f7 1389 /* Disable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1390 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 1391
<> 144:ef7eb2e8f9f7 1392 /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 1393 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1394
<> 144:ef7eb2e8f9f7 1395 /* Tx process is ended, restore hirda->gState to Ready */
<> 144:ef7eb2e8f9f7 1396 hirda->gState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 HAL_IRDA_TxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 return HAL_OK;
<> 144:ef7eb2e8f9f7 1401 }
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 /**
<> 144:ef7eb2e8f9f7 1404 * @brief Receives an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 1405 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1406 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1407 * @retval HAL status
<> 144:ef7eb2e8f9f7 1408 */
<> 144:ef7eb2e8f9f7 1409 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1410 {
<> 144:ef7eb2e8f9f7 1411 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 1412 uint16_t uhdata;
<> 144:ef7eb2e8f9f7 1413
<> 144:ef7eb2e8f9f7 1414 /* Check that a Rx process is ongoing */
<> 144:ef7eb2e8f9f7 1415 if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1416 {
<> 144:ef7eb2e8f9f7 1417 uhdata = (uint16_t) READ_REG(hirda->Instance->DR);
<> 144:ef7eb2e8f9f7 1418 if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
<> 144:ef7eb2e8f9f7 1419 {
<> 144:ef7eb2e8f9f7 1420 tmp = (uint16_t*) hirda->pRxBuffPtr;
<> 144:ef7eb2e8f9f7 1421 if(hirda->Init.Parity == IRDA_PARITY_NONE)
<> 144:ef7eb2e8f9f7 1422 {
<> 144:ef7eb2e8f9f7 1423 *tmp = (uint16_t)(uhdata & (uint16_t)0x01FFU);
<> 144:ef7eb2e8f9f7 1424 hirda->pRxBuffPtr += 2U;
<> 144:ef7eb2e8f9f7 1425 }
<> 144:ef7eb2e8f9f7 1426 else
<> 144:ef7eb2e8f9f7 1427 {
<> 144:ef7eb2e8f9f7 1428 *tmp = (uint16_t)(uhdata & (uint16_t)0x00FFU);
<> 144:ef7eb2e8f9f7 1429 hirda->pRxBuffPtr += 1U;
<> 144:ef7eb2e8f9f7 1430 }
<> 144:ef7eb2e8f9f7 1431 }
<> 144:ef7eb2e8f9f7 1432 else
<> 144:ef7eb2e8f9f7 1433 {
<> 144:ef7eb2e8f9f7 1434 if(hirda->Init.Parity == IRDA_PARITY_NONE)
<> 144:ef7eb2e8f9f7 1435 {
<> 144:ef7eb2e8f9f7 1436 *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FFU);
<> 144:ef7eb2e8f9f7 1437 }
<> 144:ef7eb2e8f9f7 1438 else
<> 144:ef7eb2e8f9f7 1439 {
<> 144:ef7eb2e8f9f7 1440 *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x007FU);
<> 144:ef7eb2e8f9f7 1441 }
<> 144:ef7eb2e8f9f7 1442 }
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 if(--hirda->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 1445 {
<> 144:ef7eb2e8f9f7 1446 /* Disable the IRDA Data Register not empty Interrupt */
<> 144:ef7eb2e8f9f7 1447 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 /* Disable the IRDA Parity Error Interrupt */
<> 144:ef7eb2e8f9f7 1450 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 1453 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1454
<> 144:ef7eb2e8f9f7 1455 /* Rx process is completed, restore hirda->RxState to Ready */
<> 144:ef7eb2e8f9f7 1456 hirda->RxState = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1457
<> 144:ef7eb2e8f9f7 1458 HAL_IRDA_RxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1459
<> 144:ef7eb2e8f9f7 1460 return HAL_OK;
<> 144:ef7eb2e8f9f7 1461 }
<> 144:ef7eb2e8f9f7 1462 return HAL_OK;
<> 144:ef7eb2e8f9f7 1463 }
<> 144:ef7eb2e8f9f7 1464 else
<> 144:ef7eb2e8f9f7 1465 {
<> 144:ef7eb2e8f9f7 1466 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1467 }
<> 144:ef7eb2e8f9f7 1468 }
<> 144:ef7eb2e8f9f7 1469
<> 144:ef7eb2e8f9f7 1470 /**
<> 144:ef7eb2e8f9f7 1471 * @brief Configures the IRDA peripheral.
<> 144:ef7eb2e8f9f7 1472 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1473 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1474 * @retval None
<> 144:ef7eb2e8f9f7 1475 */
<> 144:ef7eb2e8f9f7 1476 static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1477 {
<> 144:ef7eb2e8f9f7 1478 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1479 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 1480 assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
<> 144:ef7eb2e8f9f7 1481 assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
<> 144:ef7eb2e8f9f7 1482 assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
<> 144:ef7eb2e8f9f7 1483 assert_param(IS_IRDA_MODE(hirda->Init.Mode));
<> 144:ef7eb2e8f9f7 1484
<> 144:ef7eb2e8f9f7 1485 /*-------------------------- IRDA CR2 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 1486 /* Clear STOP[13:12] bits */
<> 144:ef7eb2e8f9f7 1487 CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP);
<> 144:ef7eb2e8f9f7 1488
<> 144:ef7eb2e8f9f7 1489 /*-------------------------- USART CR1 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1490 /* Clear M, PCE, PS, TE and RE bits */
<> 144:ef7eb2e8f9f7 1491 CLEAR_BIT(hirda->Instance->CR1, USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE);
<> 144:ef7eb2e8f9f7 1492
<> 144:ef7eb2e8f9f7 1493 /* Configure the USART Word Length, Parity and mode:
<> 144:ef7eb2e8f9f7 1494 Set the M bits according to hirda->Init.WordLength value
<> 144:ef7eb2e8f9f7 1495 Set PCE and PS bits according to hirda->Init.Parity value
<> 144:ef7eb2e8f9f7 1496 Set TE and RE bits according to hirda->Init.Mode value */
<> 144:ef7eb2e8f9f7 1497 /* Write to USART CR1 */
<> 144:ef7eb2e8f9f7 1498 SET_BIT(hirda->Instance->CR1, (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode);
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 /*-------------------------- USART CR3 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1501 /* Clear CTSE and RTSE bits */
<> 144:ef7eb2e8f9f7 1502 CLEAR_BIT(hirda->Instance->CR3, USART_CR3_RTSE | USART_CR3_CTSE);
<> 144:ef7eb2e8f9f7 1503
<> 144:ef7eb2e8f9f7 1504 /*-------------------------- USART BRR Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1505 if((hirda->Instance == USART1) || (hirda->Instance == USART6))
<> 144:ef7eb2e8f9f7 1506 {
<> 144:ef7eb2e8f9f7 1507 SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
<> 144:ef7eb2e8f9f7 1508 }
<> 144:ef7eb2e8f9f7 1509 else
<> 144:ef7eb2e8f9f7 1510 {
<> 144:ef7eb2e8f9f7 1511 SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate));
<> 144:ef7eb2e8f9f7 1512 }
<> 144:ef7eb2e8f9f7 1513 }
<> 144:ef7eb2e8f9f7 1514
<> 144:ef7eb2e8f9f7 1515 /**
<> 144:ef7eb2e8f9f7 1516 * @}
<> 144:ef7eb2e8f9f7 1517 */
<> 144:ef7eb2e8f9f7 1518
<> 144:ef7eb2e8f9f7 1519 #endif /* HAL_IRDA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1520 /**
<> 144:ef7eb2e8f9f7 1521 * @}
<> 144:ef7eb2e8f9f7 1522 */
<> 144:ef7eb2e8f9f7 1523
<> 144:ef7eb2e8f9f7 1524 /**
<> 144:ef7eb2e8f9f7 1525 * @}
<> 144:ef7eb2e8f9f7 1526 */
<> 144:ef7eb2e8f9f7 1527
<> 144:ef7eb2e8f9f7 1528 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/