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targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_dma.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f2xx_hal_dma.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.1.3
<>	144:ef7eb2e8f9f7	6	* @date 29-June-2016
<>	144:ef7eb2e8f9f7	7	* @brief DMA HAL module driver.
<>	144:ef7eb2e8f9f7	8	*
<>	144:ef7eb2e8f9f7	9	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	10	* functionalities of the Direct Memory Access (DMA) peripheral:
<>	144:ef7eb2e8f9f7	11	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	12	* + IO operation functions
<>	144:ef7eb2e8f9f7	13	* + Peripheral State and errors functions
<>	144:ef7eb2e8f9f7	14	@verbatim
<>	144:ef7eb2e8f9f7	15	==============================================================================
<>	144:ef7eb2e8f9f7	16	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	17	==============================================================================
<>	144:ef7eb2e8f9f7	18	[..]
<>	144:ef7eb2e8f9f7	19	(#) Enable and configure the peripheral to be connected to the DMA Stream
<>	144:ef7eb2e8f9f7	20	(except for internal SRAM/FLASH memories: no initialization is
<>	144:ef7eb2e8f9f7	21	necessary) please refer to Reference manual for connection between peripherals
<>	144:ef7eb2e8f9f7	22	and DMA requests.
<>	144:ef7eb2e8f9f7	23
<>	144:ef7eb2e8f9f7	24	(#) For a given Stream, program the required configuration through the following parameters:
<>	144:ef7eb2e8f9f7	25	Transfer Direction, Source and Destination data formats,
<>	144:ef7eb2e8f9f7	26	Circular, Normal or peripheral flow control mode, Stream Priority level,
<>	144:ef7eb2e8f9f7	27	Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
<>	144:ef7eb2e8f9f7	28	Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
<>	144:ef7eb2e8f9f7	29
<>	144:ef7eb2e8f9f7	30	-@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
<>	144:ef7eb2e8f9f7	31	__HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
<>	144:ef7eb2e8f9f7	32
<>	144:ef7eb2e8f9f7	33	* Polling mode IO operation *
<>	144:ef7eb2e8f9f7	34	=================================
<>	144:ef7eb2e8f9f7	35	[..]
<>	144:ef7eb2e8f9f7	36	(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
<>	144:ef7eb2e8f9f7	37	address and destination address and the Length of data to be transferred.
<>	144:ef7eb2e8f9f7	38	(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
<>	144:ef7eb2e8f9f7	39	case a fixed Timeout can be configured by User depending from his application.
<>	144:ef7eb2e8f9f7	40	(+) Use HAL_DMA_Abort() function to abort the current transfer.
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	* Interrupt mode IO operation *
<>	144:ef7eb2e8f9f7	43	===================================
<>	144:ef7eb2e8f9f7	44	[..]
<>	144:ef7eb2e8f9f7	45	(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
<>	144:ef7eb2e8f9f7	46	(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
<>	144:ef7eb2e8f9f7	47	(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
<>	144:ef7eb2e8f9f7	48	Source address and destination address and the Length of data to be transferred. In this
<>	144:ef7eb2e8f9f7	49	case the DMA interrupt is configured
<>	144:ef7eb2e8f9f7	50	(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
<>	144:ef7eb2e8f9f7	51	(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
<>	144:ef7eb2e8f9f7	52	add his own function by customization of function pointer XferCpltCallback and
<>	144:ef7eb2e8f9f7	53	XferErrorCallback (i.e a member of DMA handle structure).
<>	144:ef7eb2e8f9f7	54	[..]
<>	144:ef7eb2e8f9f7	55	(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<>	144:ef7eb2e8f9f7	56	detection.
<>	144:ef7eb2e8f9f7	57
<>	144:ef7eb2e8f9f7	58	(#) Use HAL_DMA_Abort_IT() function to abort the current transfer
<>	144:ef7eb2e8f9f7	59
<>	144:ef7eb2e8f9f7	60	-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	-@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
<>	144:ef7eb2e8f9f7	63	possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
<>	144:ef7eb2e8f9f7	64	Half-Word data size for the peripheral to access its data register and set Word data size
<>	144:ef7eb2e8f9f7	65	for the Memory to gain in access time. Each two half words will be packed and written in
<>	144:ef7eb2e8f9f7	66	a single access to a Word in the Memory).
<>	144:ef7eb2e8f9f7	67
<>	144:ef7eb2e8f9f7	68	-@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
<>	144:ef7eb2e8f9f7	69	and Destination. In this case the Peripheral Data Size will be applied to both Source
<>	144:ef7eb2e8f9f7	70	and Destination.
<>	144:ef7eb2e8f9f7	71
<>	144:ef7eb2e8f9f7	72	* DMA HAL driver macros list *
<>	144:ef7eb2e8f9f7	73	=============================================
<>	144:ef7eb2e8f9f7	74	[..]
<>	144:ef7eb2e8f9f7	75	Below the list of most used macros in DMA HAL driver.
<>	144:ef7eb2e8f9f7	76
<>	144:ef7eb2e8f9f7	77	(+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
<>	144:ef7eb2e8f9f7	78	(+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
<>	144:ef7eb2e8f9f7	79	(+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
<>	144:ef7eb2e8f9f7	80	(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
<>	144:ef7eb2e8f9f7	81	(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
<>	144:ef7eb2e8f9f7	82	(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
<>	144:ef7eb2e8f9f7	83
<>	144:ef7eb2e8f9f7	84	[..]
<>	144:ef7eb2e8f9f7	85	(@) You can refer to the DMA HAL driver header file for more useful macros
<>	144:ef7eb2e8f9f7	86
<>	144:ef7eb2e8f9f7	87	@endverbatim
<>	144:ef7eb2e8f9f7	88	******************************************************************************
<>	144:ef7eb2e8f9f7	89	* @attention
<>	144:ef7eb2e8f9f7	90	*
<>	144:ef7eb2e8f9f7	91	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	92	*
<>	144:ef7eb2e8f9f7	93	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	94	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	95	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	96	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	97	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	98	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	99	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	100	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	101	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	102	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	103	*
<>	144:ef7eb2e8f9f7	104	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	105	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	106	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	107	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	108	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	109	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	110	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	111	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	112	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	113	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	114	*
<>	144:ef7eb2e8f9f7	115	******************************************************************************
<>	144:ef7eb2e8f9f7	116	*/
<>	144:ef7eb2e8f9f7	117
<>	144:ef7eb2e8f9f7	118	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	119	#include "stm32f2xx_hal.h"
<>	144:ef7eb2e8f9f7	120
<>	144:ef7eb2e8f9f7	121	/** @addtogroup STM32F2xx_HAL_Driver
<>	144:ef7eb2e8f9f7	122	* @{
<>	144:ef7eb2e8f9f7	123	*/
<>	144:ef7eb2e8f9f7	124
<>	144:ef7eb2e8f9f7	125	/** @defgroup DMA DMA
<>	144:ef7eb2e8f9f7	126	* @brief DMA HAL module driver
<>	144:ef7eb2e8f9f7	127	* @{
<>	144:ef7eb2e8f9f7	128	*/
<>	144:ef7eb2e8f9f7	129
<>	144:ef7eb2e8f9f7	130	#ifdef HAL_DMA_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	131
<>	144:ef7eb2e8f9f7	132	/* Private types -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	133	typedef struct
<>	144:ef7eb2e8f9f7	134	{
<>	144:ef7eb2e8f9f7	135	__IO uint32_t ISR; /!< DMA interrupt status register /
<>	144:ef7eb2e8f9f7	136	__IO uint32_t Reserved0;
<>	144:ef7eb2e8f9f7	137	__IO uint32_t IFCR; /!< DMA interrupt flag clear register /
<>	144:ef7eb2e8f9f7	138	} DMA_Base_Registers;
<>	144:ef7eb2e8f9f7	139
<>	144:ef7eb2e8f9f7	140	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	141	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	142	/** @addtogroup DMA_Private_Constants
<>	144:ef7eb2e8f9f7	143	* @{
<>	144:ef7eb2e8f9f7	144	*/
<>	144:ef7eb2e8f9f7	145	#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */
<>	144:ef7eb2e8f9f7	146	/**
<>	144:ef7eb2e8f9f7	147	* @}
<>	144:ef7eb2e8f9f7	148	*/
<>	144:ef7eb2e8f9f7	149	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	150	/* Private functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	151	/** @addtogroup DMA_Private_Functions
<>	144:ef7eb2e8f9f7	152	* @{
<>	144:ef7eb2e8f9f7	153	*/
<>	144:ef7eb2e8f9f7	154	static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<>	144:ef7eb2e8f9f7	155	static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	156	static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	157
<>	144:ef7eb2e8f9f7	158	/**
<>	144:ef7eb2e8f9f7	159	* @}
<>	144:ef7eb2e8f9f7	160	*/
<>	144:ef7eb2e8f9f7	161
<>	144:ef7eb2e8f9f7	162	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	163	/** @addtogroup DMA_Exported_Functions
<>	144:ef7eb2e8f9f7	164	* @{
<>	144:ef7eb2e8f9f7	165	*/
<>	144:ef7eb2e8f9f7	166
<>	144:ef7eb2e8f9f7	167	/** @addtogroup DMA_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	168	*
<>	144:ef7eb2e8f9f7	169	@verbatim
<>	144:ef7eb2e8f9f7	170	===============================================================================
<>	144:ef7eb2e8f9f7	171	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	172	===============================================================================
<>	144:ef7eb2e8f9f7	173	[..]
<>	144:ef7eb2e8f9f7	174	This section provides functions allowing to initialize the DMA Stream source
<>	144:ef7eb2e8f9f7	175	and destination addresses, incrementation and data sizes, transfer direction,
<>	144:ef7eb2e8f9f7	176	circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
<>	144:ef7eb2e8f9f7	177	[..]
<>	144:ef7eb2e8f9f7	178	The HAL_DMA_Init() function follows the DMA configuration procedures as described in
<>	144:ef7eb2e8f9f7	179	reference manual.
<>	144:ef7eb2e8f9f7	180
<>	144:ef7eb2e8f9f7	181	@endverbatim
<>	144:ef7eb2e8f9f7	182	* @{
<>	144:ef7eb2e8f9f7	183	*/
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185	/**
<>	144:ef7eb2e8f9f7	186	* @brief Initializes the DMA according to the specified
<>	144:ef7eb2e8f9f7	187	* parameters in the DMA_InitTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	188	* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	189	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	190	* @retval HAL status
<>	144:ef7eb2e8f9f7	191	*/
<>	144:ef7eb2e8f9f7	192	HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	193	{
<>	144:ef7eb2e8f9f7	194	uint32_t tmp = 0U;
<>	144:ef7eb2e8f9f7	195	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	196	DMA_Base_Registers *regs;
<>	144:ef7eb2e8f9f7	197
<>	144:ef7eb2e8f9f7	198	/* Check the DMA peripheral state */
<>	144:ef7eb2e8f9f7	199	if(hdma == NULL)
<>	144:ef7eb2e8f9f7	200	{
<>	144:ef7eb2e8f9f7	201	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	202	}
<>	144:ef7eb2e8f9f7	203
<>	144:ef7eb2e8f9f7	204	/* Check the parameters */
<>	144:ef7eb2e8f9f7	205	assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
<>	144:ef7eb2e8f9f7	206	assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
<>	144:ef7eb2e8f9f7	207	assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<>	144:ef7eb2e8f9f7	208	assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<>	144:ef7eb2e8f9f7	209	assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<>	144:ef7eb2e8f9f7	210	assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<>	144:ef7eb2e8f9f7	211	assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<>	144:ef7eb2e8f9f7	212	assert_param(IS_DMA_MODE(hdma->Init.Mode));
<>	144:ef7eb2e8f9f7	213	assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
<>	144:ef7eb2e8f9f7	214	assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
<>	144:ef7eb2e8f9f7	215	/* Check the memory burst, peripheral burst and FIFO threshold parameters only
<>	144:ef7eb2e8f9f7	216	when FIFO mode is enabled */
<>	144:ef7eb2e8f9f7	217	if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
<>	144:ef7eb2e8f9f7	218	{
<>	144:ef7eb2e8f9f7	219	assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
<>	144:ef7eb2e8f9f7	220	assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
<>	144:ef7eb2e8f9f7	221	assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
<>	144:ef7eb2e8f9f7	222	}
<>	144:ef7eb2e8f9f7	223
<>	144:ef7eb2e8f9f7	224	/* Allocate lock resource */
<>	144:ef7eb2e8f9f7	225	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	226
<>	144:ef7eb2e8f9f7	227	/* Change DMA peripheral state */
<>	144:ef7eb2e8f9f7	228	hdma->State = HAL_DMA_STATE_BUSY;
<>	144:ef7eb2e8f9f7	229
<>	144:ef7eb2e8f9f7	230	/* Disable the peripheral */
<>	144:ef7eb2e8f9f7	231	__HAL_DMA_DISABLE(hdma);
<>	144:ef7eb2e8f9f7	232
<>	144:ef7eb2e8f9f7	233	/* Check if the DMA Stream is effectively disabled */
<>	144:ef7eb2e8f9f7	234	while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
<>	144:ef7eb2e8f9f7	235	{
<>	144:ef7eb2e8f9f7	236	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	237	if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
<>	144:ef7eb2e8f9f7	238	{
<>	144:ef7eb2e8f9f7	239	/* Update error code */
<>	144:ef7eb2e8f9f7	240	hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	241
<>	144:ef7eb2e8f9f7	242	/* Change the DMA state */
<>	144:ef7eb2e8f9f7	243	hdma->State = HAL_DMA_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	246	}
<>	144:ef7eb2e8f9f7	247	}
<>	144:ef7eb2e8f9f7	248
<>	144:ef7eb2e8f9f7	249	/* Get the CR register value */
<>	144:ef7eb2e8f9f7	250	tmp = hdma->Instance->CR;
<>	144:ef7eb2e8f9f7	251
<>	144:ef7eb2e8f9f7	252	/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
<>	144:ef7eb2e8f9f7	253	tmp &= ((uint32_t)~(DMA_SxCR_CHSEL \| DMA_SxCR_MBURST \| DMA_SxCR_PBURST \| \
<>	144:ef7eb2e8f9f7	254	DMA_SxCR_PL \| DMA_SxCR_MSIZE \| DMA_SxCR_PSIZE \| \
<>	144:ef7eb2e8f9f7	255	DMA_SxCR_MINC \| DMA_SxCR_PINC \| DMA_SxCR_CIRC \| \
<>	144:ef7eb2e8f9f7	256	DMA_SxCR_DIR \| DMA_SxCR_CT \| DMA_SxCR_DBM));
<>	144:ef7eb2e8f9f7	257
<>	144:ef7eb2e8f9f7	258	/* Prepare the DMA Stream configuration */
<>	144:ef7eb2e8f9f7	259	tmp \|= hdma->Init.Channel \| hdma->Init.Direction \|
<>	144:ef7eb2e8f9f7	260	hdma->Init.PeriphInc \| hdma->Init.MemInc \|
<>	144:ef7eb2e8f9f7	261	hdma->Init.PeriphDataAlignment \| hdma->Init.MemDataAlignment \|
<>	144:ef7eb2e8f9f7	262	hdma->Init.Mode \| hdma->Init.Priority;
<>	144:ef7eb2e8f9f7	263
<>	144:ef7eb2e8f9f7	264	/* the Memory burst and peripheral burst are not used when the FIFO is disabled */
<>	144:ef7eb2e8f9f7	265	if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
<>	144:ef7eb2e8f9f7	266	{
<>	144:ef7eb2e8f9f7	267	/* Get memory burst and peripheral burst */
<>	144:ef7eb2e8f9f7	268	tmp \|= hdma->Init.MemBurst \| hdma->Init.PeriphBurst;
<>	144:ef7eb2e8f9f7	269	}
<>	144:ef7eb2e8f9f7	270
<>	144:ef7eb2e8f9f7	271	/* Write to DMA Stream CR register */
<>	144:ef7eb2e8f9f7	272	hdma->Instance->CR = tmp;
<>	144:ef7eb2e8f9f7	273
<>	144:ef7eb2e8f9f7	274	/* Get the FCR register value */
<>	144:ef7eb2e8f9f7	275	tmp = hdma->Instance->FCR;
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	/* Clear Direct mode and FIFO threshold bits */
<>	144:ef7eb2e8f9f7	278	tmp &= (uint32_t)~(DMA_SxFCR_DMDIS \| DMA_SxFCR_FTH);
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	/* Prepare the DMA Stream FIFO configuration */
<>	144:ef7eb2e8f9f7	281	tmp \|= hdma->Init.FIFOMode;
<>	144:ef7eb2e8f9f7	282
<>	144:ef7eb2e8f9f7	283	/* the FIFO threshold is not used when the FIFO mode is disabled */
<>	144:ef7eb2e8f9f7	284	if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
<>	144:ef7eb2e8f9f7	285	{
<>	144:ef7eb2e8f9f7	286	/* Get the FIFO threshold */
<>	144:ef7eb2e8f9f7	287	tmp \|= hdma->Init.FIFOThreshold;
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	if(DMA_CheckFifoParam(hdma) != HAL_OK)
<>	144:ef7eb2e8f9f7	290	{
<>	144:ef7eb2e8f9f7	291	/* Update error code */
<>	144:ef7eb2e8f9f7	292	hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
<>	144:ef7eb2e8f9f7	293
<>	144:ef7eb2e8f9f7	294	/* Change the DMA state */
<>	144:ef7eb2e8f9f7	295	hdma->State = HAL_DMA_STATE_READY;
<>	144:ef7eb2e8f9f7	296
<>	144:ef7eb2e8f9f7	297	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	298	}
<>	144:ef7eb2e8f9f7	299	}
<>	144:ef7eb2e8f9f7	300
<>	144:ef7eb2e8f9f7	301	/* Write to DMA Stream FCR */
<>	144:ef7eb2e8f9f7	302	hdma->Instance->FCR = tmp;
<>	144:ef7eb2e8f9f7	303
<>	144:ef7eb2e8f9f7	304	/* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
<>	144:ef7eb2e8f9f7	305	DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
<>	144:ef7eb2e8f9f7	306	regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	/* Clear all interrupt flags */
<>	144:ef7eb2e8f9f7	309	regs->IFCR = 0x3FU << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	310
<>	144:ef7eb2e8f9f7	311	/* Initialize the error code */
<>	144:ef7eb2e8f9f7	312	hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/* Initialize the DMA state */
<>	144:ef7eb2e8f9f7	315	hdma->State = HAL_DMA_STATE_READY;
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317	return HAL_OK;
<>	144:ef7eb2e8f9f7	318	}
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	/**
<>	144:ef7eb2e8f9f7	321	* @brief DeInitializes the DMA peripheral
<>	144:ef7eb2e8f9f7	322	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	323	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	324	* @retval HAL status
<>	144:ef7eb2e8f9f7	325	*/
<>	144:ef7eb2e8f9f7	326	HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	327	{
<>	144:ef7eb2e8f9f7	328	DMA_Base_Registers *regs;
<>	144:ef7eb2e8f9f7	329
<>	144:ef7eb2e8f9f7	330	/* Check the DMA peripheral state */
<>	144:ef7eb2e8f9f7	331	if(hdma == NULL)
<>	144:ef7eb2e8f9f7	332	{
<>	144:ef7eb2e8f9f7	333	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	334	}
<>	144:ef7eb2e8f9f7	335
<>	144:ef7eb2e8f9f7	336	/* Check the DMA peripheral state */
<>	144:ef7eb2e8f9f7	337	if(hdma->State == HAL_DMA_STATE_BUSY)
<>	144:ef7eb2e8f9f7	338	{
<>	144:ef7eb2e8f9f7	339	/* Return error status */
<>	144:ef7eb2e8f9f7	340	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	341	}
<>	144:ef7eb2e8f9f7	342
<>	144:ef7eb2e8f9f7	343	/* Disable the selected DMA Streamx */
<>	144:ef7eb2e8f9f7	344	__HAL_DMA_DISABLE(hdma);
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	/* Reset DMA Streamx control register */
<>	144:ef7eb2e8f9f7	347	hdma->Instance->CR = 0U;
<>	144:ef7eb2e8f9f7	348
<>	144:ef7eb2e8f9f7	349	/* Reset DMA Streamx number of data to transfer register */
<>	144:ef7eb2e8f9f7	350	hdma->Instance->NDTR = 0U;
<>	144:ef7eb2e8f9f7	351
<>	144:ef7eb2e8f9f7	352	/* Reset DMA Streamx peripheral address register */
<>	144:ef7eb2e8f9f7	353	hdma->Instance->PAR = 0U;
<>	144:ef7eb2e8f9f7	354
<>	144:ef7eb2e8f9f7	355	/* Reset DMA Streamx memory 0 address register */
<>	144:ef7eb2e8f9f7	356	hdma->Instance->M0AR = 0U;
<>	144:ef7eb2e8f9f7	357
<>	144:ef7eb2e8f9f7	358	/* Reset DMA Streamx memory 1 address register */
<>	144:ef7eb2e8f9f7	359	hdma->Instance->M1AR = 0U;
<>	144:ef7eb2e8f9f7	360
<>	144:ef7eb2e8f9f7	361	/* Reset DMA Streamx FIFO control register */
<>	144:ef7eb2e8f9f7	362	hdma->Instance->FCR = (uint32_t)0x00000021U;
<>	144:ef7eb2e8f9f7	363
<>	144:ef7eb2e8f9f7	364	/* Get DMA steam Base Address */
<>	144:ef7eb2e8f9f7	365	regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
<>	144:ef7eb2e8f9f7	366
<>	144:ef7eb2e8f9f7	367	/* Clear all interrupt flags at correct offset within the register */
<>	144:ef7eb2e8f9f7	368	regs->IFCR = 0x3FU << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	369
<>	144:ef7eb2e8f9f7	370	/* Initialize the error code */
<>	144:ef7eb2e8f9f7	371	hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<>	144:ef7eb2e8f9f7	372
<>	144:ef7eb2e8f9f7	373	/* Initialize the DMA state */
<>	144:ef7eb2e8f9f7	374	hdma->State = HAL_DMA_STATE_RESET;
<>	144:ef7eb2e8f9f7	375
<>	144:ef7eb2e8f9f7	376	/* Release Lock */
<>	144:ef7eb2e8f9f7	377	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	378
<>	144:ef7eb2e8f9f7	379	return HAL_OK;
<>	144:ef7eb2e8f9f7	380	}
<>	144:ef7eb2e8f9f7	381
<>	144:ef7eb2e8f9f7	382	/**
<>	144:ef7eb2e8f9f7	383	* @}
<>	144:ef7eb2e8f9f7	384	*/
<>	144:ef7eb2e8f9f7	385
<>	144:ef7eb2e8f9f7	386	/** @addtogroup DMA_Exported_Functions_Group2
<>	144:ef7eb2e8f9f7	387	*
<>	144:ef7eb2e8f9f7	388	@verbatim
<>	144:ef7eb2e8f9f7	389	===============================================================================
<>	144:ef7eb2e8f9f7	390	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	391	===============================================================================
<>	144:ef7eb2e8f9f7	392	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	393	(+) Configure the source, destination address and data length and Start DMA transfer
<>	144:ef7eb2e8f9f7	394	(+) Configure the source, destination address and data length and
<>	144:ef7eb2e8f9f7	395	Start DMA transfer with interrupt
<>	144:ef7eb2e8f9f7	396	(+) Abort DMA transfer
<>	144:ef7eb2e8f9f7	397	(+) Poll for transfer complete
<>	144:ef7eb2e8f9f7	398	(+) Handle DMA interrupt request
<>	144:ef7eb2e8f9f7	399
<>	144:ef7eb2e8f9f7	400	@endverbatim
<>	144:ef7eb2e8f9f7	401	* @{
<>	144:ef7eb2e8f9f7	402	*/
<>	144:ef7eb2e8f9f7	403
<>	144:ef7eb2e8f9f7	404	/**
<>	144:ef7eb2e8f9f7	405	* @brief Starts the DMA Transfer.
<>	144:ef7eb2e8f9f7	406	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	407	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	408	* @param SrcAddress: The source memory Buffer address
<>	144:ef7eb2e8f9f7	409	* @param DstAddress: The destination memory Buffer address
<>	144:ef7eb2e8f9f7	410	* @param DataLength: The length of data to be transferred from source to destination
<>	144:ef7eb2e8f9f7	411	* @retval HAL status
<>	144:ef7eb2e8f9f7	412	*/
<>	144:ef7eb2e8f9f7	413	HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<>	144:ef7eb2e8f9f7	414	{
<>	144:ef7eb2e8f9f7	415	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	416
<>	144:ef7eb2e8f9f7	417	/* Check the parameters */
<>	144:ef7eb2e8f9f7	418	assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<>	144:ef7eb2e8f9f7	419
<>	144:ef7eb2e8f9f7	420	/* Process locked */
<>	144:ef7eb2e8f9f7	421	__HAL_LOCK(hdma);
<>	144:ef7eb2e8f9f7	422
<>	144:ef7eb2e8f9f7	423	if(HAL_DMA_STATE_READY == hdma->State)
<>	144:ef7eb2e8f9f7	424	{
<>	144:ef7eb2e8f9f7	425	/* Change DMA peripheral state */
<>	144:ef7eb2e8f9f7	426	hdma->State = HAL_DMA_STATE_BUSY;
<>	144:ef7eb2e8f9f7	427
<>	144:ef7eb2e8f9f7	428	/* Initialize the error code */
<>	144:ef7eb2e8f9f7	429	hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<>	144:ef7eb2e8f9f7	430
<>	144:ef7eb2e8f9f7	431	/* Configure the source, destination address and the data length */
<>	144:ef7eb2e8f9f7	432	DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<>	144:ef7eb2e8f9f7	433
<>	144:ef7eb2e8f9f7	434	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	435	__HAL_DMA_ENABLE(hdma);
<>	144:ef7eb2e8f9f7	436	}
<>	144:ef7eb2e8f9f7	437	else
<>	144:ef7eb2e8f9f7	438	{
<>	144:ef7eb2e8f9f7	439	/* Process unlocked */
<>	144:ef7eb2e8f9f7	440	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	441
<>	144:ef7eb2e8f9f7	442	/* Return error status */
<>	144:ef7eb2e8f9f7	443	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	444	}
<>	144:ef7eb2e8f9f7	445	return status;
<>	144:ef7eb2e8f9f7	446	}
<>	144:ef7eb2e8f9f7	447
<>	144:ef7eb2e8f9f7	448	/**
<>	144:ef7eb2e8f9f7	449	* @brief Starts the DMA Transfer with interrupt enabled.
<>	144:ef7eb2e8f9f7	450	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	451	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	452	* @param SrcAddress: The source memory Buffer address
<>	144:ef7eb2e8f9f7	453	* @param DstAddress: The destination memory Buffer address
<>	144:ef7eb2e8f9f7	454	* @param DataLength: The length of data to be transferred from source to destination
<>	144:ef7eb2e8f9f7	455	* @retval HAL status
<>	144:ef7eb2e8f9f7	456	*/
<>	144:ef7eb2e8f9f7	457	HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<>	144:ef7eb2e8f9f7	458	{
<>	144:ef7eb2e8f9f7	459	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	460
<>	144:ef7eb2e8f9f7	461	/* calculate DMA base and stream number */
<>	144:ef7eb2e8f9f7	462	DMA_Base_Registers regs = (DMA_Base_Registers )hdma->StreamBaseAddress;
<>	144:ef7eb2e8f9f7	463
<>	144:ef7eb2e8f9f7	464	/* Check the parameters */
<>	144:ef7eb2e8f9f7	465	assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<>	144:ef7eb2e8f9f7	466
<>	144:ef7eb2e8f9f7	467	/* Process locked */
<>	144:ef7eb2e8f9f7	468	__HAL_LOCK(hdma);
<>	144:ef7eb2e8f9f7	469
<>	144:ef7eb2e8f9f7	470	if(HAL_DMA_STATE_READY == hdma->State)
<>	144:ef7eb2e8f9f7	471	{
<>	144:ef7eb2e8f9f7	472	/* Change DMA peripheral state */
<>	144:ef7eb2e8f9f7	473	hdma->State = HAL_DMA_STATE_BUSY;
<>	144:ef7eb2e8f9f7	474
<>	144:ef7eb2e8f9f7	475	/* Initialize the error code */
<>	144:ef7eb2e8f9f7	476	hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<>	144:ef7eb2e8f9f7	477
<>	144:ef7eb2e8f9f7	478	/* Configure the source, destination address and the data length */
<>	144:ef7eb2e8f9f7	479	DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<>	144:ef7eb2e8f9f7	480
<>	144:ef7eb2e8f9f7	481	/* Clear all interrupt flags at correct offset within the register */
<>	144:ef7eb2e8f9f7	482	regs->IFCR = 0x3FU << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	483
<>	144:ef7eb2e8f9f7	484	/* Enable Common interrupts*/
<>	144:ef7eb2e8f9f7	485	hdma->Instance->CR \|= DMA_IT_TC \| DMA_IT_TE \| DMA_IT_DME;
<>	144:ef7eb2e8f9f7	486	hdma->Instance->FCR \|= DMA_IT_FE;
<>	144:ef7eb2e8f9f7	487
<>	144:ef7eb2e8f9f7	488	if(hdma->XferHalfCpltCallback != NULL)
<>	144:ef7eb2e8f9f7	489	{
<>	144:ef7eb2e8f9f7	490	hdma->Instance->CR \|= DMA_IT_HT;
<>	144:ef7eb2e8f9f7	491	}
<>	144:ef7eb2e8f9f7	492
<>	144:ef7eb2e8f9f7	493	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	494	__HAL_DMA_ENABLE(hdma);
<>	144:ef7eb2e8f9f7	495	}
<>	144:ef7eb2e8f9f7	496	else
<>	144:ef7eb2e8f9f7	497	{
<>	144:ef7eb2e8f9f7	498	/* Process unlocked */
<>	144:ef7eb2e8f9f7	499	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	500
<>	144:ef7eb2e8f9f7	501	/* Return error status */
<>	144:ef7eb2e8f9f7	502	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	503	}
<>	144:ef7eb2e8f9f7	504
<>	144:ef7eb2e8f9f7	505	return status;
<>	144:ef7eb2e8f9f7	506	}
<>	144:ef7eb2e8f9f7	507
<>	144:ef7eb2e8f9f7	508	/**
<>	144:ef7eb2e8f9f7	509	* @brief Aborts the DMA Transfer.
<>	144:ef7eb2e8f9f7	510	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	511	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	512	*
<>	144:ef7eb2e8f9f7	513	* @note After disabling a DMA Stream, a check for wait until the DMA Stream is
<>	144:ef7eb2e8f9f7	514	* effectively disabled is added. If a Stream is disabled
<>	144:ef7eb2e8f9f7	515	* while a data transfer is ongoing, the current data will be transferred
<>	144:ef7eb2e8f9f7	516	* and the Stream will be effectively disabled only after the transfer of
<>	144:ef7eb2e8f9f7	517	* this single data is finished.
<>	144:ef7eb2e8f9f7	518	* @retval HAL status
<>	144:ef7eb2e8f9f7	519	*/
<>	144:ef7eb2e8f9f7	520	HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	521	{
<>	144:ef7eb2e8f9f7	522	/* calculate DMA base and stream number */
<>	144:ef7eb2e8f9f7	523	DMA_Base_Registers regs = (DMA_Base_Registers )hdma->StreamBaseAddress;
<>	144:ef7eb2e8f9f7	524
<>	144:ef7eb2e8f9f7	525	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	526
<>	144:ef7eb2e8f9f7	527	if(hdma->State != HAL_DMA_STATE_BUSY)
<>	144:ef7eb2e8f9f7	528	{
<>	144:ef7eb2e8f9f7	529	hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<>	144:ef7eb2e8f9f7	530
<>	144:ef7eb2e8f9f7	531	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	532	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	533
<>	144:ef7eb2e8f9f7	534	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	535	}
<>	144:ef7eb2e8f9f7	536	else
<>	144:ef7eb2e8f9f7	537	{
<>	144:ef7eb2e8f9f7	538	/* Disable all the transfer interrupts */
<>	144:ef7eb2e8f9f7	539	hdma->Instance->CR &= ~(DMA_IT_TC \| DMA_IT_TE \| DMA_IT_DME);
<>	144:ef7eb2e8f9f7	540	hdma->Instance->FCR &= ~(DMA_IT_FE);
<>	144:ef7eb2e8f9f7	541
<>	144:ef7eb2e8f9f7	542	if((hdma->XferHalfCpltCallback != NULL) \|\| (hdma->XferM1HalfCpltCallback != NULL))
<>	144:ef7eb2e8f9f7	543	{
<>	144:ef7eb2e8f9f7	544	hdma->Instance->CR &= ~(DMA_IT_HT);
<>	144:ef7eb2e8f9f7	545	}
<>	144:ef7eb2e8f9f7	546
<>	144:ef7eb2e8f9f7	547	/* Disable the stream */
<>	144:ef7eb2e8f9f7	548	__HAL_DMA_DISABLE(hdma);
<>	144:ef7eb2e8f9f7	549
<>	144:ef7eb2e8f9f7	550	/* Check if the DMA Stream is effectively disabled */
<>	144:ef7eb2e8f9f7	551	while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
<>	144:ef7eb2e8f9f7	552	{
<>	144:ef7eb2e8f9f7	553	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	554	if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
<>	144:ef7eb2e8f9f7	555	{
<>	144:ef7eb2e8f9f7	556	/* Update error code */
<>	144:ef7eb2e8f9f7	557	hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	558
<>	144:ef7eb2e8f9f7	559	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	560	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	561
<>	144:ef7eb2e8f9f7	562	/* Change the DMA state */
<>	144:ef7eb2e8f9f7	563	hdma->State = HAL_DMA_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	564
<>	144:ef7eb2e8f9f7	565	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	566	}
<>	144:ef7eb2e8f9f7	567	}
<>	144:ef7eb2e8f9f7	568
<>	144:ef7eb2e8f9f7	569	/* Clear all interrupt flags at correct offset within the register */
<>	144:ef7eb2e8f9f7	570	regs->IFCR = 0x3FU << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	571
<>	144:ef7eb2e8f9f7	572	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	573	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	574
<>	144:ef7eb2e8f9f7	575	/* Change the DMA state*/
<>	144:ef7eb2e8f9f7	576	hdma->State = HAL_DMA_STATE_READY;
<>	144:ef7eb2e8f9f7	577	}
<>	144:ef7eb2e8f9f7	578	return HAL_OK;
<>	144:ef7eb2e8f9f7	579	}
<>	144:ef7eb2e8f9f7	580
<>	144:ef7eb2e8f9f7	581	/**
<>	144:ef7eb2e8f9f7	582	* @brief Aborts the DMA Transfer in Interrupt mode.
<>	144:ef7eb2e8f9f7	583	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	584	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	585	* @retval HAL status
<>	144:ef7eb2e8f9f7	586	*/
<>	144:ef7eb2e8f9f7	587	HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	588	{
<>	144:ef7eb2e8f9f7	589	if(hdma->State != HAL_DMA_STATE_BUSY)
<>	144:ef7eb2e8f9f7	590	{
<>	144:ef7eb2e8f9f7	591	hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<>	144:ef7eb2e8f9f7	592	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	593	}
<>	144:ef7eb2e8f9f7	594	else
<>	144:ef7eb2e8f9f7	595	{
<>	144:ef7eb2e8f9f7	596	/* Set Abort State */
<>	144:ef7eb2e8f9f7	597	hdma->State = HAL_DMA_STATE_ABORT;
<>	144:ef7eb2e8f9f7	598
<>	144:ef7eb2e8f9f7	599	/* Disable the stream */
<>	144:ef7eb2e8f9f7	600	__HAL_DMA_DISABLE(hdma);
<>	144:ef7eb2e8f9f7	601	}
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	return HAL_OK;
<>	144:ef7eb2e8f9f7	604	}
<>	144:ef7eb2e8f9f7	605
<>	144:ef7eb2e8f9f7	606	/**
<>	144:ef7eb2e8f9f7	607	* @brief Polling for transfer complete.
<>	144:ef7eb2e8f9f7	608	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	609	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	610	* @param CompleteLevel: Specifies the DMA level complete.
<>	144:ef7eb2e8f9f7	611	* @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
<>	144:ef7eb2e8f9f7	612	* This model could be used for debug purpose.
<>	144:ef7eb2e8f9f7	613	* @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
<>	144:ef7eb2e8f9f7	614	* @param Timeout: Timeout duration.
<>	144:ef7eb2e8f9f7	615	* @retval HAL status
<>	144:ef7eb2e8f9f7	616	*/
<>	144:ef7eb2e8f9f7	617	HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	618	{
<>	144:ef7eb2e8f9f7	619	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	620	uint32_t mask_cpltlevel;
<>	144:ef7eb2e8f9f7	621	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	622	uint32_t tmpisr;
<>	144:ef7eb2e8f9f7	623
<>	144:ef7eb2e8f9f7	624	/* calculate DMA base and stream number */
<>	144:ef7eb2e8f9f7	625	DMA_Base_Registers *regs;
<>	144:ef7eb2e8f9f7	626
<>	144:ef7eb2e8f9f7	627	if(HAL_DMA_STATE_BUSY != hdma->State)
<>	144:ef7eb2e8f9f7	628	{
<>	144:ef7eb2e8f9f7	629	/* No transfer ongoing */
<>	144:ef7eb2e8f9f7	630	hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<>	144:ef7eb2e8f9f7	631	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	632	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	633	}
<>	144:ef7eb2e8f9f7	634
<>	144:ef7eb2e8f9f7	635	/* Polling mode not supported in circular mode and double buffering mode */
<>	144:ef7eb2e8f9f7	636	if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
<>	144:ef7eb2e8f9f7	637	{
<>	144:ef7eb2e8f9f7	638	hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
<>	144:ef7eb2e8f9f7	639	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	640	}
<>	144:ef7eb2e8f9f7	641
<>	144:ef7eb2e8f9f7	642	/* Get the level transfer complete flag */
<>	144:ef7eb2e8f9f7	643	if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<>	144:ef7eb2e8f9f7	644	{
<>	144:ef7eb2e8f9f7	645	/* Transfer Complete flag */
<>	144:ef7eb2e8f9f7	646	mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	647	}
<>	144:ef7eb2e8f9f7	648	else
<>	144:ef7eb2e8f9f7	649	{
<>	144:ef7eb2e8f9f7	650	/* Half Transfer Complete flag */
<>	144:ef7eb2e8f9f7	651	mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	652	}
<>	144:ef7eb2e8f9f7	653
<>	144:ef7eb2e8f9f7	654	regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
<>	144:ef7eb2e8f9f7	655	tmpisr = regs->ISR;
<>	144:ef7eb2e8f9f7	656
<>	144:ef7eb2e8f9f7	657	while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
<>	144:ef7eb2e8f9f7	658	{
<>	144:ef7eb2e8f9f7	659	/* Check for the Timeout (Not applicable in circular mode)*/
<>	144:ef7eb2e8f9f7	660	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	661	{
<>	144:ef7eb2e8f9f7	662	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	663	{
<>	144:ef7eb2e8f9f7	664	/* Update error code */
<>	144:ef7eb2e8f9f7	665	hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	666
<>	144:ef7eb2e8f9f7	667	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	668	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	669
<>	144:ef7eb2e8f9f7	670	/* Change the DMA state */
<>	144:ef7eb2e8f9f7	671	hdma->State = HAL_DMA_STATE_READY;
<>	144:ef7eb2e8f9f7	672
<>	144:ef7eb2e8f9f7	673	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	674	}
<>	144:ef7eb2e8f9f7	675	}
<>	144:ef7eb2e8f9f7	676
<>	144:ef7eb2e8f9f7	677	/* Get the ISR register value */
<>	144:ef7eb2e8f9f7	678	tmpisr = regs->ISR;
<>	144:ef7eb2e8f9f7	679
<>	144:ef7eb2e8f9f7	680	if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
<>	144:ef7eb2e8f9f7	681	{
<>	144:ef7eb2e8f9f7	682	/* Update error code */
<>	144:ef7eb2e8f9f7	683	hdma->ErrorCode \|= HAL_DMA_ERROR_TE;
<>	144:ef7eb2e8f9f7	684
<>	144:ef7eb2e8f9f7	685	/* Clear the transfer error flag */
<>	144:ef7eb2e8f9f7	686	regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	687	}
<>	144:ef7eb2e8f9f7	688
<>	144:ef7eb2e8f9f7	689	if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
<>	144:ef7eb2e8f9f7	690	{
<>	144:ef7eb2e8f9f7	691	/* Update error code */
<>	144:ef7eb2e8f9f7	692	hdma->ErrorCode \|= HAL_DMA_ERROR_FE;
<>	144:ef7eb2e8f9f7	693
<>	144:ef7eb2e8f9f7	694	/* Clear the FIFO error flag */
<>	144:ef7eb2e8f9f7	695	regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	696	}
<>	144:ef7eb2e8f9f7	697
<>	144:ef7eb2e8f9f7	698	if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
<>	144:ef7eb2e8f9f7	699	{
<>	144:ef7eb2e8f9f7	700	/* Update error code */
<>	144:ef7eb2e8f9f7	701	hdma->ErrorCode \|= HAL_DMA_ERROR_DME;
<>	144:ef7eb2e8f9f7	702
<>	144:ef7eb2e8f9f7	703	/* Clear the Direct Mode error flag */
<>	144:ef7eb2e8f9f7	704	regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	705	}
<>	144:ef7eb2e8f9f7	706	}
<>	144:ef7eb2e8f9f7	707
<>	144:ef7eb2e8f9f7	708	if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
<>	144:ef7eb2e8f9f7	709	{
<>	144:ef7eb2e8f9f7	710	if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
<>	144:ef7eb2e8f9f7	711	{
<>	144:ef7eb2e8f9f7	712	HAL_DMA_Abort(hdma);
<>	144:ef7eb2e8f9f7	713
<>	144:ef7eb2e8f9f7	714	/* Clear the half transfer and transfer complete flags */
<>	144:ef7eb2e8f9f7	715	regs->IFCR = (DMA_FLAG_HTIF0_4 \| DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	716
<>	144:ef7eb2e8f9f7	717	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	718	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	719
<>	144:ef7eb2e8f9f7	720	/* Change the DMA state */
<>	144:ef7eb2e8f9f7	721	hdma->State= HAL_DMA_STATE_READY;
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	724	}
<>	144:ef7eb2e8f9f7	725	}
<>	144:ef7eb2e8f9f7	726
<>	144:ef7eb2e8f9f7	727	/* Get the level transfer complete flag */
<>	144:ef7eb2e8f9f7	728	if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<>	144:ef7eb2e8f9f7	729	{
<>	144:ef7eb2e8f9f7	730	/* Clear the half transfer and transfer complete flags */
<>	144:ef7eb2e8f9f7	731	regs->IFCR = (DMA_FLAG_HTIF0_4 \| DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	732
<>	144:ef7eb2e8f9f7	733	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	734	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	735
<>	144:ef7eb2e8f9f7	736	hdma->State = HAL_DMA_STATE_READY;
<>	144:ef7eb2e8f9f7	737	}
<>	144:ef7eb2e8f9f7	738	else
<>	144:ef7eb2e8f9f7	739	{
<>	144:ef7eb2e8f9f7	740	/* Clear the half transfer and transfer complete flags */
<>	144:ef7eb2e8f9f7	741	regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	742	}
<>	144:ef7eb2e8f9f7	743
<>	144:ef7eb2e8f9f7	744	return status;
<>	144:ef7eb2e8f9f7	745	}
<>	144:ef7eb2e8f9f7	746
<>	144:ef7eb2e8f9f7	747	/**
<>	144:ef7eb2e8f9f7	748	* @brief Handles DMA interrupt request.
<>	144:ef7eb2e8f9f7	749	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	750	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	751	* @retval None
<>	144:ef7eb2e8f9f7	752	*/
<>	144:ef7eb2e8f9f7	753	void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	754	{
<>	144:ef7eb2e8f9f7	755	uint32_t tmpisr;
<>	144:ef7eb2e8f9f7	756	__IO uint32_t count = 0;
<>	144:ef7eb2e8f9f7	757	uint32_t timeout = SystemCoreClock / 9600;
<>	144:ef7eb2e8f9f7	758
<>	144:ef7eb2e8f9f7	759	/* calculate DMA base and stream number */
<>	144:ef7eb2e8f9f7	760	DMA_Base_Registers regs = (DMA_Base_Registers )hdma->StreamBaseAddress;
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	tmpisr = regs->ISR;
<>	144:ef7eb2e8f9f7	763
<>	144:ef7eb2e8f9f7	764	/* Transfer Error Interrupt management ***************************************/
<>	144:ef7eb2e8f9f7	765	if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
<>	144:ef7eb2e8f9f7	766	{
<>	144:ef7eb2e8f9f7	767	if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
<>	144:ef7eb2e8f9f7	768	{
<>	144:ef7eb2e8f9f7	769	/* Disable the transfer error interrupt */
<>	144:ef7eb2e8f9f7	770	hdma->Instance->CR &= ~(DMA_IT_TE);
<>	144:ef7eb2e8f9f7	771
<>	144:ef7eb2e8f9f7	772	/* Clear the transfer error flag */
<>	144:ef7eb2e8f9f7	773	regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	774
<>	144:ef7eb2e8f9f7	775	/* Update error code */
<>	144:ef7eb2e8f9f7	776	hdma->ErrorCode \|= HAL_DMA_ERROR_TE;
<>	144:ef7eb2e8f9f7	777	}
<>	144:ef7eb2e8f9f7	778	}
<>	144:ef7eb2e8f9f7	779	/* FIFO Error Interrupt management ******************************************/
<>	144:ef7eb2e8f9f7	780	if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
<>	144:ef7eb2e8f9f7	781	{
<>	144:ef7eb2e8f9f7	782	if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
<>	144:ef7eb2e8f9f7	783	{
<>	144:ef7eb2e8f9f7	784	/* Clear the FIFO error flag */
<>	144:ef7eb2e8f9f7	785	regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	786
<>	144:ef7eb2e8f9f7	787	/* Update error code */
<>	144:ef7eb2e8f9f7	788	hdma->ErrorCode \|= HAL_DMA_ERROR_FE;
<>	144:ef7eb2e8f9f7	789	}
<>	144:ef7eb2e8f9f7	790	}
<>	144:ef7eb2e8f9f7	791	/* Direct Mode Error Interrupt management ***********************************/
<>	144:ef7eb2e8f9f7	792	if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
<>	144:ef7eb2e8f9f7	793	{
<>	144:ef7eb2e8f9f7	794	if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
<>	144:ef7eb2e8f9f7	795	{
<>	144:ef7eb2e8f9f7	796	/* Clear the direct mode error flag */
<>	144:ef7eb2e8f9f7	797	regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	798
<>	144:ef7eb2e8f9f7	799	/* Update error code */
<>	144:ef7eb2e8f9f7	800	hdma->ErrorCode \|= HAL_DMA_ERROR_DME;
<>	144:ef7eb2e8f9f7	801	}
<>	144:ef7eb2e8f9f7	802	}
<>	144:ef7eb2e8f9f7	803	/* Half Transfer Complete Interrupt management ******************************/
<>	144:ef7eb2e8f9f7	804	if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
<>	144:ef7eb2e8f9f7	805	{
<>	144:ef7eb2e8f9f7	806	if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
<>	144:ef7eb2e8f9f7	807	{
<>	144:ef7eb2e8f9f7	808	/* Clear the half transfer complete flag */
<>	144:ef7eb2e8f9f7	809	regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	810
<>	144:ef7eb2e8f9f7	811	/* Multi_Buffering mode enabled */
<>	144:ef7eb2e8f9f7	812	if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
<>	144:ef7eb2e8f9f7	813	{
<>	144:ef7eb2e8f9f7	814	/* Current memory buffer used is Memory 0 */
<>	144:ef7eb2e8f9f7	815	if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
<>	144:ef7eb2e8f9f7	816	{
<>	144:ef7eb2e8f9f7	817	if(hdma->XferHalfCpltCallback != NULL)
<>	144:ef7eb2e8f9f7	818	{
<>	144:ef7eb2e8f9f7	819	/* Half transfer callback */
<>	144:ef7eb2e8f9f7	820	hdma->XferHalfCpltCallback(hdma);
<>	144:ef7eb2e8f9f7	821	}
<>	144:ef7eb2e8f9f7	822	}
<>	144:ef7eb2e8f9f7	823	/* Current memory buffer used is Memory 1 */
<>	144:ef7eb2e8f9f7	824	else
<>	144:ef7eb2e8f9f7	825	{
<>	144:ef7eb2e8f9f7	826	if(hdma->XferM1HalfCpltCallback != NULL)
<>	144:ef7eb2e8f9f7	827	{
<>	144:ef7eb2e8f9f7	828	/* Half transfer callback */
<>	144:ef7eb2e8f9f7	829	hdma->XferM1HalfCpltCallback(hdma);
<>	144:ef7eb2e8f9f7	830	}
<>	144:ef7eb2e8f9f7	831	}
<>	144:ef7eb2e8f9f7	832	}
<>	144:ef7eb2e8f9f7	833	else
<>	144:ef7eb2e8f9f7	834	{
<>	144:ef7eb2e8f9f7	835	/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
<>	144:ef7eb2e8f9f7	836	if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
<>	144:ef7eb2e8f9f7	837	{
<>	144:ef7eb2e8f9f7	838	/* Disable the half transfer interrupt */
<>	144:ef7eb2e8f9f7	839	hdma->Instance->CR &= ~(DMA_IT_HT);
<>	144:ef7eb2e8f9f7	840	}
<>	144:ef7eb2e8f9f7	841
<>	144:ef7eb2e8f9f7	842	if(hdma->XferHalfCpltCallback != NULL)
<>	144:ef7eb2e8f9f7	843	{
<>	144:ef7eb2e8f9f7	844	/* Half transfer callback */
<>	144:ef7eb2e8f9f7	845	hdma->XferHalfCpltCallback(hdma);
<>	144:ef7eb2e8f9f7	846	}
<>	144:ef7eb2e8f9f7	847	}
<>	144:ef7eb2e8f9f7	848	}
<>	144:ef7eb2e8f9f7	849	}
<>	144:ef7eb2e8f9f7	850	/* Transfer Complete Interrupt management ***********************************/
<>	144:ef7eb2e8f9f7	851	if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
<>	144:ef7eb2e8f9f7	852	{
<>	144:ef7eb2e8f9f7	853	if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
<>	144:ef7eb2e8f9f7	854	{
<>	144:ef7eb2e8f9f7	855	/* Clear the transfer complete flag */
<>	144:ef7eb2e8f9f7	856	regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	857
<>	144:ef7eb2e8f9f7	858	if(HAL_DMA_STATE_ABORT == hdma->State)
<>	144:ef7eb2e8f9f7	859	{
<>	144:ef7eb2e8f9f7	860	/* Disable all the transfer interrupts */
<>	144:ef7eb2e8f9f7	861	hdma->Instance->CR &= ~(DMA_IT_TC \| DMA_IT_TE \| DMA_IT_DME);
<>	144:ef7eb2e8f9f7	862	hdma->Instance->FCR &= ~(DMA_IT_FE);
<>	144:ef7eb2e8f9f7	863
<>	144:ef7eb2e8f9f7	864	if((hdma->XferHalfCpltCallback != NULL) \|\| (hdma->XferM1HalfCpltCallback != NULL))
<>	144:ef7eb2e8f9f7	865	{
<>	144:ef7eb2e8f9f7	866	hdma->Instance->CR &= ~(DMA_IT_HT);
<>	144:ef7eb2e8f9f7	867	}
<>	144:ef7eb2e8f9f7	868
<>	144:ef7eb2e8f9f7	869	/* Clear all interrupt flags at correct offset within the register */
<>	144:ef7eb2e8f9f7	870	regs->IFCR = 0x3FU << hdma->StreamIndex;
<>	144:ef7eb2e8f9f7	871
<>	144:ef7eb2e8f9f7	872	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	873	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	874
<>	144:ef7eb2e8f9f7	875	/* Change the DMA state */
<>	144:ef7eb2e8f9f7	876	hdma->State = HAL_DMA_STATE_READY;
<>	144:ef7eb2e8f9f7	877
<>	144:ef7eb2e8f9f7	878	if(hdma->XferAbortCallback != NULL)
<>	144:ef7eb2e8f9f7	879	{
<>	144:ef7eb2e8f9f7	880	hdma->XferAbortCallback(hdma);
<>	144:ef7eb2e8f9f7	881	}
<>	144:ef7eb2e8f9f7	882	return;
<>	144:ef7eb2e8f9f7	883	}
<>	144:ef7eb2e8f9f7	884
<>	144:ef7eb2e8f9f7	885	if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
<>	144:ef7eb2e8f9f7	886	{
<>	144:ef7eb2e8f9f7	887	/* Current memory buffer used is Memory 0 */
<>	144:ef7eb2e8f9f7	888	if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
<>	144:ef7eb2e8f9f7	889	{
<>	144:ef7eb2e8f9f7	890	if(hdma->XferM1CpltCallback != NULL)
<>	144:ef7eb2e8f9f7	891	{
<>	144:ef7eb2e8f9f7	892	/* Transfer complete Callback for memory1 */
<>	144:ef7eb2e8f9f7	893	hdma->XferM1CpltCallback(hdma);
<>	144:ef7eb2e8f9f7	894	}
<>	144:ef7eb2e8f9f7	895	}
<>	144:ef7eb2e8f9f7	896	/* Current memory buffer used is Memory 1 */
<>	144:ef7eb2e8f9f7	897	else
<>	144:ef7eb2e8f9f7	898	{
<>	144:ef7eb2e8f9f7	899	if(hdma->XferCpltCallback != NULL)
<>	144:ef7eb2e8f9f7	900	{
<>	144:ef7eb2e8f9f7	901	/* Transfer complete Callback for memory0 */
<>	144:ef7eb2e8f9f7	902	hdma->XferCpltCallback(hdma);
<>	144:ef7eb2e8f9f7	903	}
<>	144:ef7eb2e8f9f7	904	}
<>	144:ef7eb2e8f9f7	905	}
<>	144:ef7eb2e8f9f7	906	/* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
<>	144:ef7eb2e8f9f7	907	else
<>	144:ef7eb2e8f9f7	908	{
<>	144:ef7eb2e8f9f7	909	if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
<>	144:ef7eb2e8f9f7	910	{
<>	144:ef7eb2e8f9f7	911	/* Disable the transfer complete interrupt */
<>	144:ef7eb2e8f9f7	912	hdma->Instance->CR &= ~(DMA_IT_TC);
<>	144:ef7eb2e8f9f7	913
<>	144:ef7eb2e8f9f7	914	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	915	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	916
<>	144:ef7eb2e8f9f7	917	/* Change the DMA state */
<>	144:ef7eb2e8f9f7	918	hdma->State = HAL_DMA_STATE_READY;
<>	144:ef7eb2e8f9f7	919	}
<>	144:ef7eb2e8f9f7	920
<>	144:ef7eb2e8f9f7	921	if(hdma->XferCpltCallback != NULL)
<>	144:ef7eb2e8f9f7	922	{
<>	144:ef7eb2e8f9f7	923	/* Transfer complete callback */
<>	144:ef7eb2e8f9f7	924	hdma->XferCpltCallback(hdma);
<>	144:ef7eb2e8f9f7	925	}
<>	144:ef7eb2e8f9f7	926	}
<>	144:ef7eb2e8f9f7	927	}
<>	144:ef7eb2e8f9f7	928	}
<>	144:ef7eb2e8f9f7	929
<>	144:ef7eb2e8f9f7	930	/* manage error case */
<>	144:ef7eb2e8f9f7	931	if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
<>	144:ef7eb2e8f9f7	932	{
<>	144:ef7eb2e8f9f7	933	if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
<>	144:ef7eb2e8f9f7	934	{
<>	144:ef7eb2e8f9f7	935	hdma->State = HAL_DMA_STATE_ABORT;
<>	144:ef7eb2e8f9f7	936
<>	144:ef7eb2e8f9f7	937	/* Disable the stream */
<>	144:ef7eb2e8f9f7	938	__HAL_DMA_DISABLE(hdma);
<>	144:ef7eb2e8f9f7	939
<>	144:ef7eb2e8f9f7	940	do
<>	144:ef7eb2e8f9f7	941	{
<>	144:ef7eb2e8f9f7	942	if (++count > timeout)
<>	144:ef7eb2e8f9f7	943	{
<>	144:ef7eb2e8f9f7	944	break;
<>	144:ef7eb2e8f9f7	945	}
<>	144:ef7eb2e8f9f7	946	}
<>	144:ef7eb2e8f9f7	947	while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
<>	144:ef7eb2e8f9f7	948
<>	144:ef7eb2e8f9f7	949	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	950	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	951
<>	144:ef7eb2e8f9f7	952	/* Change the DMA state */
<>	144:ef7eb2e8f9f7	953	hdma->State = HAL_DMA_STATE_READY;
<>	144:ef7eb2e8f9f7	954	}
<>	144:ef7eb2e8f9f7	955
<>	144:ef7eb2e8f9f7	956	if(hdma->XferErrorCallback != NULL)
<>	144:ef7eb2e8f9f7	957	{
<>	144:ef7eb2e8f9f7	958	/* Transfer error callback */
<>	144:ef7eb2e8f9f7	959	hdma->XferErrorCallback(hdma);
<>	144:ef7eb2e8f9f7	960	}
<>	144:ef7eb2e8f9f7	961	}
<>	144:ef7eb2e8f9f7	962	}
<>	144:ef7eb2e8f9f7	963
<>	144:ef7eb2e8f9f7	964	/**
<>	144:ef7eb2e8f9f7	965	* @brief Register callbacks
<>	144:ef7eb2e8f9f7	966	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	967	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	968	* @param CallbackID: User Callback identifer
<>	144:ef7eb2e8f9f7	969	* a DMA_HandleTypeDef structure as parameter.
<>	144:ef7eb2e8f9f7	970	* @param pCallback: pointer to private callbacsk function which has pointer to
<>	144:ef7eb2e8f9f7	971	* a DMA_HandleTypeDef structure as parameter.
<>	144:ef7eb2e8f9f7	972	* @retval HAL status
<>	144:ef7eb2e8f9f7	973	*/
<>	144:ef7eb2e8f9f7	974	HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void ( pCallback)(DMA_HandleTypeDef *_hdma))
<>	144:ef7eb2e8f9f7	975	{
<>	144:ef7eb2e8f9f7	976
<>	144:ef7eb2e8f9f7	977	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	978
<>	144:ef7eb2e8f9f7	979	/* Process locked */
<>	144:ef7eb2e8f9f7	980	__HAL_LOCK(hdma);
<>	144:ef7eb2e8f9f7	981
<>	144:ef7eb2e8f9f7	982	if(HAL_DMA_STATE_READY == hdma->State)
<>	144:ef7eb2e8f9f7	983	{
<>	144:ef7eb2e8f9f7	984	switch (CallbackID)
<>	144:ef7eb2e8f9f7	985	{
<>	144:ef7eb2e8f9f7	986	case HAL_DMA_XFER_CPLT_CB_ID:
<>	144:ef7eb2e8f9f7	987	hdma->XferCpltCallback = pCallback;
<>	144:ef7eb2e8f9f7	988	break;
<>	144:ef7eb2e8f9f7	989
<>	144:ef7eb2e8f9f7	990	case HAL_DMA_XFER_HALFCPLT_CB_ID:
<>	144:ef7eb2e8f9f7	991	hdma->XferHalfCpltCallback = pCallback;
<>	144:ef7eb2e8f9f7	992	break;
<>	144:ef7eb2e8f9f7	993
<>	144:ef7eb2e8f9f7	994	case HAL_DMA_XFER_M1CPLT_CB_ID:
<>	144:ef7eb2e8f9f7	995	hdma->XferM1CpltCallback = pCallback;
<>	144:ef7eb2e8f9f7	996	break;
<>	144:ef7eb2e8f9f7	997
<>	144:ef7eb2e8f9f7	998	case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
<>	144:ef7eb2e8f9f7	999	hdma->XferM1HalfCpltCallback = pCallback;
<>	144:ef7eb2e8f9f7	1000	break;
<>	144:ef7eb2e8f9f7	1001
<>	144:ef7eb2e8f9f7	1002	case HAL_DMA_XFER_ERROR_CB_ID:
<>	144:ef7eb2e8f9f7	1003	hdma->XferErrorCallback = pCallback;
<>	144:ef7eb2e8f9f7	1004	break;
<>	144:ef7eb2e8f9f7	1005
<>	144:ef7eb2e8f9f7	1006	case HAL_DMA_XFER_ABORT_CB_ID:
<>	144:ef7eb2e8f9f7	1007	hdma->XferAbortCallback = pCallback;
<>	144:ef7eb2e8f9f7	1008	break;
<>	144:ef7eb2e8f9f7	1009
<>	144:ef7eb2e8f9f7	1010	default:
<>	144:ef7eb2e8f9f7	1011	break;
<>	144:ef7eb2e8f9f7	1012	}
<>	144:ef7eb2e8f9f7	1013	}
<>	144:ef7eb2e8f9f7	1014	else
<>	144:ef7eb2e8f9f7	1015	{
<>	144:ef7eb2e8f9f7	1016	/* Return error status */
<>	144:ef7eb2e8f9f7	1017	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1018	}
<>	144:ef7eb2e8f9f7	1019
<>	144:ef7eb2e8f9f7	1020	/* Release Lock */
<>	144:ef7eb2e8f9f7	1021	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	1022
<>	144:ef7eb2e8f9f7	1023	return status;
<>	144:ef7eb2e8f9f7	1024	}
<>	144:ef7eb2e8f9f7	1025
<>	144:ef7eb2e8f9f7	1026	/**
<>	144:ef7eb2e8f9f7	1027	* @brief UnRegister callbacks
<>	144:ef7eb2e8f9f7	1028	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1029	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	1030	* @param CallbackID: User Callback identifer
<>	144:ef7eb2e8f9f7	1031	* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<>	144:ef7eb2e8f9f7	1032	* @retval HAL status
<>	144:ef7eb2e8f9f7	1033	*/
<>	144:ef7eb2e8f9f7	1034	HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
<>	144:ef7eb2e8f9f7	1035	{
<>	144:ef7eb2e8f9f7	1036	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1037
<>	144:ef7eb2e8f9f7	1038	/* Process locked */
<>	144:ef7eb2e8f9f7	1039	__HAL_LOCK(hdma);
<>	144:ef7eb2e8f9f7	1040
<>	144:ef7eb2e8f9f7	1041	if(HAL_DMA_STATE_READY == hdma->State)
<>	144:ef7eb2e8f9f7	1042	{
<>	144:ef7eb2e8f9f7	1043	switch (CallbackID)
<>	144:ef7eb2e8f9f7	1044	{
<>	144:ef7eb2e8f9f7	1045	case HAL_DMA_XFER_CPLT_CB_ID:
<>	144:ef7eb2e8f9f7	1046	hdma->XferCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1047	break;
<>	144:ef7eb2e8f9f7	1048
<>	144:ef7eb2e8f9f7	1049	case HAL_DMA_XFER_HALFCPLT_CB_ID:
<>	144:ef7eb2e8f9f7	1050	hdma->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1051	break;
<>	144:ef7eb2e8f9f7	1052
<>	144:ef7eb2e8f9f7	1053	case HAL_DMA_XFER_M1CPLT_CB_ID:
<>	144:ef7eb2e8f9f7	1054	hdma->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1055	break;
<>	144:ef7eb2e8f9f7	1056
<>	144:ef7eb2e8f9f7	1057	case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
<>	144:ef7eb2e8f9f7	1058	hdma->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1059	break;
<>	144:ef7eb2e8f9f7	1060
<>	144:ef7eb2e8f9f7	1061	case HAL_DMA_XFER_ERROR_CB_ID:
<>	144:ef7eb2e8f9f7	1062	hdma->XferErrorCallback = NULL;
<>	144:ef7eb2e8f9f7	1063	break;
<>	144:ef7eb2e8f9f7	1064
<>	144:ef7eb2e8f9f7	1065	case HAL_DMA_XFER_ABORT_CB_ID:
<>	144:ef7eb2e8f9f7	1066	hdma->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1067	break;
<>	144:ef7eb2e8f9f7	1068
<>	144:ef7eb2e8f9f7	1069	case HAL_DMA_XFER_ALL_CB_ID:
<>	144:ef7eb2e8f9f7	1070	hdma->XferCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1071	hdma->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1072	hdma->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1073	hdma->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1074	hdma->XferErrorCallback = NULL;
<>	144:ef7eb2e8f9f7	1075	hdma->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1076	break;
<>	144:ef7eb2e8f9f7	1077
<>	144:ef7eb2e8f9f7	1078	default:
<>	144:ef7eb2e8f9f7	1079	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1080	break;
<>	144:ef7eb2e8f9f7	1081	}
<>	144:ef7eb2e8f9f7	1082	}
<>	144:ef7eb2e8f9f7	1083	else
<>	144:ef7eb2e8f9f7	1084	{
<>	144:ef7eb2e8f9f7	1085	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1086	}
<>	144:ef7eb2e8f9f7	1087
<>	144:ef7eb2e8f9f7	1088	/* Release Lock */
<>	144:ef7eb2e8f9f7	1089	__HAL_UNLOCK(hdma);
<>	144:ef7eb2e8f9f7	1090
<>	144:ef7eb2e8f9f7	1091	return status;
<>	144:ef7eb2e8f9f7	1092	}
<>	144:ef7eb2e8f9f7	1093
<>	144:ef7eb2e8f9f7	1094	/**
<>	144:ef7eb2e8f9f7	1095	* @}
<>	144:ef7eb2e8f9f7	1096	*/
<>	144:ef7eb2e8f9f7	1097
<>	144:ef7eb2e8f9f7	1098	/** @addtogroup DMA_Exported_Functions_Group3
<>	144:ef7eb2e8f9f7	1099	*
<>	144:ef7eb2e8f9f7	1100	@verbatim
<>	144:ef7eb2e8f9f7	1101	===============================================================================
<>	144:ef7eb2e8f9f7	1102	##### State and Errors functions #####
<>	144:ef7eb2e8f9f7	1103	===============================================================================
<>	144:ef7eb2e8f9f7	1104	[..]
<>	144:ef7eb2e8f9f7	1105	This subsection provides functions allowing to
<>	144:ef7eb2e8f9f7	1106	(+) Check the DMA state
<>	144:ef7eb2e8f9f7	1107	(+) Get error code
<>	144:ef7eb2e8f9f7	1108
<>	144:ef7eb2e8f9f7	1109	@endverbatim
<>	144:ef7eb2e8f9f7	1110	* @{
<>	144:ef7eb2e8f9f7	1111	*/
<>	144:ef7eb2e8f9f7	1112
<>	144:ef7eb2e8f9f7	1113	/**
<>	144:ef7eb2e8f9f7	1114	* @brief Returns the DMA state.
<>	144:ef7eb2e8f9f7	1115	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1116	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	1117	* @retval HAL state
<>	144:ef7eb2e8f9f7	1118	*/
<>	144:ef7eb2e8f9f7	1119	HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1120	{
<>	144:ef7eb2e8f9f7	1121	return hdma->State;
<>	144:ef7eb2e8f9f7	1122	}
<>	144:ef7eb2e8f9f7	1123
<>	144:ef7eb2e8f9f7	1124	/**
<>	144:ef7eb2e8f9f7	1125	* @brief Return the DMA error code
<>	144:ef7eb2e8f9f7	1126	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1127	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	1128	* @retval DMA Error Code
<>	144:ef7eb2e8f9f7	1129	*/
<>	144:ef7eb2e8f9f7	1130	uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1131	{
<>	144:ef7eb2e8f9f7	1132	return hdma->ErrorCode;
<>	144:ef7eb2e8f9f7	1133	}
<>	144:ef7eb2e8f9f7	1134
<>	144:ef7eb2e8f9f7	1135	/**
<>	144:ef7eb2e8f9f7	1136	* @}
<>	144:ef7eb2e8f9f7	1137	*/
<>	144:ef7eb2e8f9f7	1138
<>	144:ef7eb2e8f9f7	1139	/**
<>	144:ef7eb2e8f9f7	1140	* @}
<>	144:ef7eb2e8f9f7	1141	*/
<>	144:ef7eb2e8f9f7	1142
<>	144:ef7eb2e8f9f7	1143	/** @addtogroup DMA_Private_Functions
<>	144:ef7eb2e8f9f7	1144	* @{
<>	144:ef7eb2e8f9f7	1145	*/
<>	144:ef7eb2e8f9f7	1146
<>	144:ef7eb2e8f9f7	1147	/**
<>	144:ef7eb2e8f9f7	1148	* @brief Sets the DMA Transfer parameter.
<>	144:ef7eb2e8f9f7	1149	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1150	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	1151	* @param SrcAddress: The source memory Buffer address
<>	144:ef7eb2e8f9f7	1152	* @param DstAddress: The destination memory Buffer address
<>	144:ef7eb2e8f9f7	1153	* @param DataLength: The length of data to be transferred from source to destination
<>	144:ef7eb2e8f9f7	1154	* @retval HAL status
<>	144:ef7eb2e8f9f7	1155	*/
<>	144:ef7eb2e8f9f7	1156	static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<>	144:ef7eb2e8f9f7	1157	{
<>	144:ef7eb2e8f9f7	1158	/* Clear DBM bit */
<>	144:ef7eb2e8f9f7	1159	hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
<>	144:ef7eb2e8f9f7	1160
<>	144:ef7eb2e8f9f7	1161	/* Configure DMA Stream data length */
<>	144:ef7eb2e8f9f7	1162	hdma->Instance->NDTR = DataLength;
<>	144:ef7eb2e8f9f7	1163
<>	144:ef7eb2e8f9f7	1164	/* Peripheral to Memory */
<>	144:ef7eb2e8f9f7	1165	if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<>	144:ef7eb2e8f9f7	1166	{
<>	144:ef7eb2e8f9f7	1167	/* Configure DMA Stream destination address */
<>	144:ef7eb2e8f9f7	1168	hdma->Instance->PAR = DstAddress;
<>	144:ef7eb2e8f9f7	1169
<>	144:ef7eb2e8f9f7	1170	/* Configure DMA Stream source address */
<>	144:ef7eb2e8f9f7	1171	hdma->Instance->M0AR = SrcAddress;
<>	144:ef7eb2e8f9f7	1172	}
<>	144:ef7eb2e8f9f7	1173	/* Memory to Peripheral */
<>	144:ef7eb2e8f9f7	1174	else
<>	144:ef7eb2e8f9f7	1175	{
<>	144:ef7eb2e8f9f7	1176	/* Configure DMA Stream source address */
<>	144:ef7eb2e8f9f7	1177	hdma->Instance->PAR = SrcAddress;
<>	144:ef7eb2e8f9f7	1178
<>	144:ef7eb2e8f9f7	1179	/* Configure DMA Stream destination address */
<>	144:ef7eb2e8f9f7	1180	hdma->Instance->M0AR = DstAddress;
<>	144:ef7eb2e8f9f7	1181	}
<>	144:ef7eb2e8f9f7	1182	}
<>	144:ef7eb2e8f9f7	1183
<>	144:ef7eb2e8f9f7	1184	/**
<>	144:ef7eb2e8f9f7	1185	* @brief Returns the DMA Stream base address depending on stream number
<>	144:ef7eb2e8f9f7	1186	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1187	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	1188	* @retval Stream base address
<>	144:ef7eb2e8f9f7	1189	*/
<>	144:ef7eb2e8f9f7	1190	static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1191	{
<>	144:ef7eb2e8f9f7	1192	uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
<>	144:ef7eb2e8f9f7	1193
<>	144:ef7eb2e8f9f7	1194	/* lookup table for necessary bitshift of flags within status registers */
<>	144:ef7eb2e8f9f7	1195	static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
<>	144:ef7eb2e8f9f7	1196	hdma->StreamIndex = flagBitshiftOffset[stream_number];
<>	144:ef7eb2e8f9f7	1197
<>	144:ef7eb2e8f9f7	1198	if (stream_number > 3U)
<>	144:ef7eb2e8f9f7	1199	{
<>	144:ef7eb2e8f9f7	1200	/* return pointer to HISR and HIFCR */
<>	144:ef7eb2e8f9f7	1201	hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
<>	144:ef7eb2e8f9f7	1202	}
<>	144:ef7eb2e8f9f7	1203	else
<>	144:ef7eb2e8f9f7	1204	{
<>	144:ef7eb2e8f9f7	1205	/* return pointer to LISR and LIFCR */
<>	144:ef7eb2e8f9f7	1206	hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
<>	144:ef7eb2e8f9f7	1207	}
<>	144:ef7eb2e8f9f7	1208
<>	144:ef7eb2e8f9f7	1209	return hdma->StreamBaseAddress;
<>	144:ef7eb2e8f9f7	1210	}
<>	144:ef7eb2e8f9f7	1211
<>	144:ef7eb2e8f9f7	1212	/**
<>	144:ef7eb2e8f9f7	1213	* @brief Checks compatibility between FIFO threshold level and size of the memory burst
<>	144:ef7eb2e8f9f7	1214	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1215	* the configuration information for the specified DMA Stream.
<>	144:ef7eb2e8f9f7	1216	* @retval HAL status
<>	144:ef7eb2e8f9f7	1217	*/
<>	144:ef7eb2e8f9f7	1218	static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1219	{
<>	144:ef7eb2e8f9f7	1220	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1221	uint32_t tmp = hdma->Init.FIFOThreshold;
<>	144:ef7eb2e8f9f7	1222
<>	144:ef7eb2e8f9f7	1223	/* Memory Data size equal to Byte */
<>	144:ef7eb2e8f9f7	1224	if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
<>	144:ef7eb2e8f9f7	1225	{
<>	144:ef7eb2e8f9f7	1226	switch (tmp)
<>	144:ef7eb2e8f9f7	1227	{
<>	144:ef7eb2e8f9f7	1228	case DMA_FIFO_THRESHOLD_1QUARTERFULL:
<>	144:ef7eb2e8f9f7	1229	if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
<>	144:ef7eb2e8f9f7	1230	{
<>	144:ef7eb2e8f9f7	1231	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1232	}
<>	144:ef7eb2e8f9f7	1233	break;
<>	144:ef7eb2e8f9f7	1234	case DMA_FIFO_THRESHOLD_HALFFULL:
<>	144:ef7eb2e8f9f7	1235	if(hdma->Init.MemBurst == DMA_MBURST_INC16)
<>	144:ef7eb2e8f9f7	1236	{
<>	144:ef7eb2e8f9f7	1237	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1238	}
<>	144:ef7eb2e8f9f7	1239	break;
<>	144:ef7eb2e8f9f7	1240	case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
<>	144:ef7eb2e8f9f7	1241	if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
<>	144:ef7eb2e8f9f7	1242	{
<>	144:ef7eb2e8f9f7	1243	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1244	}
<>	144:ef7eb2e8f9f7	1245	break;
<>	144:ef7eb2e8f9f7	1246	case DMA_FIFO_THRESHOLD_FULL:
<>	144:ef7eb2e8f9f7	1247	break;
<>	144:ef7eb2e8f9f7	1248	default:
<>	144:ef7eb2e8f9f7	1249	break;
<>	144:ef7eb2e8f9f7	1250	}
<>	144:ef7eb2e8f9f7	1251	}
<>	144:ef7eb2e8f9f7	1252
<>	144:ef7eb2e8f9f7	1253	/* Memory Data size equal to Half-Word */
<>	144:ef7eb2e8f9f7	1254	else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<>	144:ef7eb2e8f9f7	1255	{
<>	144:ef7eb2e8f9f7	1256	switch (tmp)
<>	144:ef7eb2e8f9f7	1257	{
<>	144:ef7eb2e8f9f7	1258	case DMA_FIFO_THRESHOLD_1QUARTERFULL:
<>	144:ef7eb2e8f9f7	1259	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1260	break;
<>	144:ef7eb2e8f9f7	1261	case DMA_FIFO_THRESHOLD_HALFFULL:
<>	144:ef7eb2e8f9f7	1262	if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
<>	144:ef7eb2e8f9f7	1263	{
<>	144:ef7eb2e8f9f7	1264	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1265	}
<>	144:ef7eb2e8f9f7	1266	break;
<>	144:ef7eb2e8f9f7	1267	case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
<>	144:ef7eb2e8f9f7	1268	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1269	break;
<>	144:ef7eb2e8f9f7	1270	case DMA_FIFO_THRESHOLD_FULL:
<>	144:ef7eb2e8f9f7	1271	if (hdma->Init.MemBurst == DMA_MBURST_INC16)
<>	144:ef7eb2e8f9f7	1272	{
<>	144:ef7eb2e8f9f7	1273	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1274	}
<>	144:ef7eb2e8f9f7	1275	break;
<>	144:ef7eb2e8f9f7	1276	default:
<>	144:ef7eb2e8f9f7	1277	break;
<>	144:ef7eb2e8f9f7	1278	}
<>	144:ef7eb2e8f9f7	1279	}
<>	144:ef7eb2e8f9f7	1280
<>	144:ef7eb2e8f9f7	1281	/* Memory Data size equal to Word */
<>	144:ef7eb2e8f9f7	1282	else
<>	144:ef7eb2e8f9f7	1283	{
<>	144:ef7eb2e8f9f7	1284	switch (tmp)
<>	144:ef7eb2e8f9f7	1285	{
<>	144:ef7eb2e8f9f7	1286	case DMA_FIFO_THRESHOLD_1QUARTERFULL:
<>	144:ef7eb2e8f9f7	1287	case DMA_FIFO_THRESHOLD_HALFFULL:
<>	144:ef7eb2e8f9f7	1288	case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
<>	144:ef7eb2e8f9f7	1289	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1290	break;
<>	144:ef7eb2e8f9f7	1291	case DMA_FIFO_THRESHOLD_FULL:
<>	144:ef7eb2e8f9f7	1292	if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
<>	144:ef7eb2e8f9f7	1293	{
<>	144:ef7eb2e8f9f7	1294	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1295	}
<>	144:ef7eb2e8f9f7	1296	break;
<>	144:ef7eb2e8f9f7	1297	default:
<>	144:ef7eb2e8f9f7	1298	break;
<>	144:ef7eb2e8f9f7	1299	}
<>	144:ef7eb2e8f9f7	1300	}
<>	144:ef7eb2e8f9f7	1301
<>	144:ef7eb2e8f9f7	1302	return status;
<>	144:ef7eb2e8f9f7	1303	}
<>	144:ef7eb2e8f9f7	1304
<>	144:ef7eb2e8f9f7	1305	/**
<>	144:ef7eb2e8f9f7	1306	* @}
<>	144:ef7eb2e8f9f7	1307	*/
<>	144:ef7eb2e8f9f7	1308
<>	144:ef7eb2e8f9f7	1309	#endif /* HAL_DMA_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	1310	/**
<>	144:ef7eb2e8f9f7	1311	* @}
<>	144:ef7eb2e8f9f7	1312	*/
<>	144:ef7eb2e8f9f7	1313
<>	144:ef7eb2e8f9f7	1314	/**
<>	144:ef7eb2e8f9f7	1315	* @}
<>	144:ef7eb2e8f9f7	1316	*/
<>	144:ef7eb2e8f9f7	1317
<>	144:ef7eb2e8f9f7	1318	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/