mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/TOOLCHAIN_ARM_STD/startup_stm32f207xx.s@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ******************* (C) COPYRIGHT 2016 STMicroelectronics ********************
<> 144:ef7eb2e8f9f7 2 ;* File Name : startup_stm32f207xx.s
<> 144:ef7eb2e8f9f7 3 ;* Author : MCD Application Team
<> 144:ef7eb2e8f9f7 4 ;* Version : V2.1.1
<> 144:ef7eb2e8f9f7 5 ;* Date : 20-November-2015
<> 144:ef7eb2e8f9f7 6 ;* Description : STM32F207xx devices vector table for MDK-ARM_STD toolchain.
<> 144:ef7eb2e8f9f7 7 ;* This module performs:
<> 144:ef7eb2e8f9f7 8 ;* - Set the initial SP
<> 144:ef7eb2e8f9f7 9 ;* - Set the initial PC == Reset_Handler
<> 144:ef7eb2e8f9f7 10 ;* - Set the vector table entries with the exceptions ISR address
<> 144:ef7eb2e8f9f7 11 ;* - Branches to __main in the C library (which eventually
<> 144:ef7eb2e8f9f7 12 ;* calls main()).
<> 144:ef7eb2e8f9f7 13 ;* After Reset the CortexM3 processor is in Thread mode,
<> 144:ef7eb2e8f9f7 14 ;* priority is Privileged, and the Stack is set to Main.
<> 144:ef7eb2e8f9f7 15 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 16 ;
<> 144:ef7eb2e8f9f7 17 ;* Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 18 ;* are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 19 ;* 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 20 ;* this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 21 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 22 ;* this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 23 ;* and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 24 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 25 ;* may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 26 ;* without specific prior written permission.
<> 144:ef7eb2e8f9f7 27 ;*
<> 144:ef7eb2e8f9f7 28 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 29 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 30 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 31 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 32 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 33 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 34 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 35 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 36 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 37 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 38 ;
<> 144:ef7eb2e8f9f7 39 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 ; Amount of memory (in bytes) allocated for Stack
<> 144:ef7eb2e8f9f7 42 ; Tailor this value to your application needs
<> 144:ef7eb2e8f9f7 43 ; <h> Stack Configuration
<> 144:ef7eb2e8f9f7 44 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 45 ; </h>
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 Stack_Size EQU 0x00000400
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 50 Stack_Mem SPACE Stack_Size
<> 144:ef7eb2e8f9f7 51 __initial_sp EQU 0x20020000
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 ; <h> Heap Configuration
<> 144:ef7eb2e8f9f7 55 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 56 ; </h>
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 Heap_Size EQU 0x00000200
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 61 __heap_base
<> 144:ef7eb2e8f9f7 62 Heap_Mem SPACE Heap_Size
<> 144:ef7eb2e8f9f7 63 __heap_limit
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 PRESERVE8
<> 144:ef7eb2e8f9f7 66 THUMB
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 70 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 71 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 72 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 73 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 76 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 77 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 78 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 79 DCD MemManage_Handler ; MPU Fault Handler
<> 144:ef7eb2e8f9f7 80 DCD BusFault_Handler ; Bus Fault Handler
<> 144:ef7eb2e8f9f7 81 DCD UsageFault_Handler ; Usage Fault Handler
<> 144:ef7eb2e8f9f7 82 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 83 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 84 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 85 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 86 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 87 DCD DebugMon_Handler ; Debug Monitor Handler
<> 144:ef7eb2e8f9f7 88 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 89 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 90 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 ; External Interrupts
<> 144:ef7eb2e8f9f7 93 DCD WWDG_IRQHandler ; Window WatchDog
<> 144:ef7eb2e8f9f7 94 DCD PVD_IRQHandler ; PVD through EXTI Line detection
<> 144:ef7eb2e8f9f7 95 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
<> 144:ef7eb2e8f9f7 96 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
<> 144:ef7eb2e8f9f7 97 DCD FLASH_IRQHandler ; FLASH
<> 144:ef7eb2e8f9f7 98 DCD RCC_IRQHandler ; RCC
<> 144:ef7eb2e8f9f7 99 DCD EXTI0_IRQHandler ; EXTI Line0
<> 144:ef7eb2e8f9f7 100 DCD EXTI1_IRQHandler ; EXTI Line1
<> 144:ef7eb2e8f9f7 101 DCD EXTI2_IRQHandler ; EXTI Line2
<> 144:ef7eb2e8f9f7 102 DCD EXTI3_IRQHandler ; EXTI Line3
<> 144:ef7eb2e8f9f7 103 DCD EXTI4_IRQHandler ; EXTI Line4
<> 144:ef7eb2e8f9f7 104 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
<> 144:ef7eb2e8f9f7 105 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
<> 144:ef7eb2e8f9f7 106 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
<> 144:ef7eb2e8f9f7 107 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
<> 144:ef7eb2e8f9f7 108 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
<> 144:ef7eb2e8f9f7 109 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
<> 144:ef7eb2e8f9f7 110 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
<> 144:ef7eb2e8f9f7 111 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
<> 144:ef7eb2e8f9f7 112 DCD CAN1_TX_IRQHandler ; CAN1 TX
<> 144:ef7eb2e8f9f7 113 DCD CAN1_RX0_IRQHandler ; CAN1 RX0
<> 144:ef7eb2e8f9f7 114 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
<> 144:ef7eb2e8f9f7 115 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
<> 144:ef7eb2e8f9f7 116 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
<> 144:ef7eb2e8f9f7 117 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
<> 144:ef7eb2e8f9f7 118 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
<> 144:ef7eb2e8f9f7 119 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
<> 144:ef7eb2e8f9f7 120 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
<> 144:ef7eb2e8f9f7 121 DCD TIM2_IRQHandler ; TIM2
<> 144:ef7eb2e8f9f7 122 DCD TIM3_IRQHandler ; TIM3
<> 144:ef7eb2e8f9f7 123 DCD TIM4_IRQHandler ; TIM4
<> 144:ef7eb2e8f9f7 124 DCD I2C1_EV_IRQHandler ; I2C1 Event
<> 144:ef7eb2e8f9f7 125 DCD I2C1_ER_IRQHandler ; I2C1 Error
<> 144:ef7eb2e8f9f7 126 DCD I2C2_EV_IRQHandler ; I2C2 Event
<> 144:ef7eb2e8f9f7 127 DCD I2C2_ER_IRQHandler ; I2C2 Error
<> 144:ef7eb2e8f9f7 128 DCD SPI1_IRQHandler ; SPI1
<> 144:ef7eb2e8f9f7 129 DCD SPI2_IRQHandler ; SPI2
<> 144:ef7eb2e8f9f7 130 DCD USART1_IRQHandler ; USART1
<> 144:ef7eb2e8f9f7 131 DCD USART2_IRQHandler ; USART2
<> 144:ef7eb2e8f9f7 132 DCD USART3_IRQHandler ; USART3
<> 144:ef7eb2e8f9f7 133 DCD EXTI15_10_IRQHandler ; External Line[15:10]s
<> 144:ef7eb2e8f9f7 134 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
<> 144:ef7eb2e8f9f7 135 DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
<> 144:ef7eb2e8f9f7 136 DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
<> 144:ef7eb2e8f9f7 137 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
<> 144:ef7eb2e8f9f7 138 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
<> 144:ef7eb2e8f9f7 139 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
<> 144:ef7eb2e8f9f7 140 DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
<> 144:ef7eb2e8f9f7 141 DCD FSMC_IRQHandler ; FSMC
<> 144:ef7eb2e8f9f7 142 DCD SDIO_IRQHandler ; SDIO
<> 144:ef7eb2e8f9f7 143 DCD TIM5_IRQHandler ; TIM5
<> 144:ef7eb2e8f9f7 144 DCD SPI3_IRQHandler ; SPI3
<> 144:ef7eb2e8f9f7 145 DCD UART4_IRQHandler ; UART4
<> 144:ef7eb2e8f9f7 146 DCD UART5_IRQHandler ; UART5
<> 144:ef7eb2e8f9f7 147 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
<> 144:ef7eb2e8f9f7 148 DCD TIM7_IRQHandler ; TIM7
<> 144:ef7eb2e8f9f7 149 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
<> 144:ef7eb2e8f9f7 150 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
<> 144:ef7eb2e8f9f7 151 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
<> 144:ef7eb2e8f9f7 152 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
<> 144:ef7eb2e8f9f7 153 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
<> 144:ef7eb2e8f9f7 154 DCD ETH_IRQHandler ; Ethernet
<> 144:ef7eb2e8f9f7 155 DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
<> 144:ef7eb2e8f9f7 156 DCD CAN2_TX_IRQHandler ; CAN2 TX
<> 144:ef7eb2e8f9f7 157 DCD CAN2_RX0_IRQHandler ; CAN2 RX0
<> 144:ef7eb2e8f9f7 158 DCD CAN2_RX1_IRQHandler ; CAN2 RX1
<> 144:ef7eb2e8f9f7 159 DCD CAN2_SCE_IRQHandler ; CAN2 SCE
<> 144:ef7eb2e8f9f7 160 DCD OTG_FS_IRQHandler ; USB OTG FS
<> 144:ef7eb2e8f9f7 161 DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
<> 144:ef7eb2e8f9f7 162 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
<> 144:ef7eb2e8f9f7 163 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
<> 144:ef7eb2e8f9f7 164 DCD USART6_IRQHandler ; USART6
<> 144:ef7eb2e8f9f7 165 DCD I2C3_EV_IRQHandler ; I2C3 event
<> 144:ef7eb2e8f9f7 166 DCD I2C3_ER_IRQHandler ; I2C3 error
<> 144:ef7eb2e8f9f7 167 DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
<> 144:ef7eb2e8f9f7 168 DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
<> 144:ef7eb2e8f9f7 169 DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
<> 144:ef7eb2e8f9f7 170 DCD OTG_HS_IRQHandler ; USB OTG HS
<> 144:ef7eb2e8f9f7 171 DCD DCMI_IRQHandler ; DCMI
<> 144:ef7eb2e8f9f7 172 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 173 DCD HASH_RNG_IRQHandler ; Hash and Rng
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 __Vectors_End
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 ; Reset handler
<> 144:ef7eb2e8f9f7 183 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 184 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 185 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 186 IMPORT __main
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 189 BLX R0
<> 144:ef7eb2e8f9f7 190 LDR R0, =__main
<> 144:ef7eb2e8f9f7 191 BX R0
<> 144:ef7eb2e8f9f7 192 ENDP
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 197 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 198 B .
<> 144:ef7eb2e8f9f7 199 ENDP
<> 144:ef7eb2e8f9f7 200 HardFault_Handler\
<> 144:ef7eb2e8f9f7 201 PROC
<> 144:ef7eb2e8f9f7 202 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 203 B .
<> 144:ef7eb2e8f9f7 204 ENDP
<> 144:ef7eb2e8f9f7 205 MemManage_Handler\
<> 144:ef7eb2e8f9f7 206 PROC
<> 144:ef7eb2e8f9f7 207 EXPORT MemManage_Handler [WEAK]
<> 144:ef7eb2e8f9f7 208 B .
<> 144:ef7eb2e8f9f7 209 ENDP
<> 144:ef7eb2e8f9f7 210 BusFault_Handler\
<> 144:ef7eb2e8f9f7 211 PROC
<> 144:ef7eb2e8f9f7 212 EXPORT BusFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 213 B .
<> 144:ef7eb2e8f9f7 214 ENDP
<> 144:ef7eb2e8f9f7 215 UsageFault_Handler\
<> 144:ef7eb2e8f9f7 216 PROC
<> 144:ef7eb2e8f9f7 217 EXPORT UsageFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 218 B .
<> 144:ef7eb2e8f9f7 219 ENDP
<> 144:ef7eb2e8f9f7 220 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 221 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 222 B .
<> 144:ef7eb2e8f9f7 223 ENDP
<> 144:ef7eb2e8f9f7 224 DebugMon_Handler\
<> 144:ef7eb2e8f9f7 225 PROC
<> 144:ef7eb2e8f9f7 226 EXPORT DebugMon_Handler [WEAK]
<> 144:ef7eb2e8f9f7 227 B .
<> 144:ef7eb2e8f9f7 228 ENDP
<> 144:ef7eb2e8f9f7 229 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 230 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 231 B .
<> 144:ef7eb2e8f9f7 232 ENDP
<> 144:ef7eb2e8f9f7 233 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 234 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 235 B .
<> 144:ef7eb2e8f9f7 236 ENDP
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 Default_Handler PROC
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 EXPORT WWDG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 241 EXPORT PVD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 242 EXPORT TAMP_STAMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 243 EXPORT RTC_WKUP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 244 EXPORT FLASH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 245 EXPORT RCC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 246 EXPORT EXTI0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 247 EXPORT EXTI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 248 EXPORT EXTI2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 249 EXPORT EXTI3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 250 EXPORT EXTI4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 251 EXPORT DMA1_Stream0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 252 EXPORT DMA1_Stream1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 253 EXPORT DMA1_Stream2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 254 EXPORT DMA1_Stream3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 255 EXPORT DMA1_Stream4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 256 EXPORT DMA1_Stream5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 257 EXPORT DMA1_Stream6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 258 EXPORT ADC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 259 EXPORT CAN1_TX_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 260 EXPORT CAN1_RX0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 261 EXPORT CAN1_RX1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 262 EXPORT CAN1_SCE_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 263 EXPORT EXTI9_5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 264 EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 265 EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 266 EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 267 EXPORT TIM1_CC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 268 EXPORT TIM2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 269 EXPORT TIM3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 270 EXPORT TIM4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 271 EXPORT I2C1_EV_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 272 EXPORT I2C1_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 273 EXPORT I2C2_EV_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 274 EXPORT I2C2_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 275 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 276 EXPORT SPI2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 277 EXPORT USART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 278 EXPORT USART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 279 EXPORT USART3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 280 EXPORT EXTI15_10_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 281 EXPORT RTC_Alarm_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 282 EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 283 EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 284 EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 285 EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 286 EXPORT TIM8_CC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 287 EXPORT DMA1_Stream7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 288 EXPORT FSMC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 289 EXPORT SDIO_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 290 EXPORT TIM5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 291 EXPORT SPI3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 292 EXPORT UART4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 293 EXPORT UART5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 294 EXPORT TIM6_DAC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 295 EXPORT TIM7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 296 EXPORT DMA2_Stream0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 297 EXPORT DMA2_Stream1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 298 EXPORT DMA2_Stream2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 299 EXPORT DMA2_Stream3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 300 EXPORT DMA2_Stream4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 301 EXPORT ETH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 302 EXPORT ETH_WKUP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 303 EXPORT CAN2_TX_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 304 EXPORT CAN2_RX0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 305 EXPORT CAN2_RX1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 306 EXPORT CAN2_SCE_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 307 EXPORT OTG_FS_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 308 EXPORT DMA2_Stream5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 309 EXPORT DMA2_Stream6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 310 EXPORT DMA2_Stream7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 311 EXPORT USART6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 312 EXPORT I2C3_EV_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 313 EXPORT I2C3_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 314 EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 315 EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 316 EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 317 EXPORT OTG_HS_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 318 EXPORT DCMI_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 319 EXPORT HASH_RNG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 322 PVD_IRQHandler
<> 144:ef7eb2e8f9f7 323 TAMP_STAMP_IRQHandler
<> 144:ef7eb2e8f9f7 324 RTC_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 325 FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 326 RCC_IRQHandler
<> 144:ef7eb2e8f9f7 327 EXTI0_IRQHandler
<> 144:ef7eb2e8f9f7 328 EXTI1_IRQHandler
<> 144:ef7eb2e8f9f7 329 EXTI2_IRQHandler
<> 144:ef7eb2e8f9f7 330 EXTI3_IRQHandler
<> 144:ef7eb2e8f9f7 331 EXTI4_IRQHandler
<> 144:ef7eb2e8f9f7 332 DMA1_Stream0_IRQHandler
<> 144:ef7eb2e8f9f7 333 DMA1_Stream1_IRQHandler
<> 144:ef7eb2e8f9f7 334 DMA1_Stream2_IRQHandler
<> 144:ef7eb2e8f9f7 335 DMA1_Stream3_IRQHandler
<> 144:ef7eb2e8f9f7 336 DMA1_Stream4_IRQHandler
<> 144:ef7eb2e8f9f7 337 DMA1_Stream5_IRQHandler
<> 144:ef7eb2e8f9f7 338 DMA1_Stream6_IRQHandler
<> 144:ef7eb2e8f9f7 339 ADC_IRQHandler
<> 144:ef7eb2e8f9f7 340 CAN1_TX_IRQHandler
<> 144:ef7eb2e8f9f7 341 CAN1_RX0_IRQHandler
<> 144:ef7eb2e8f9f7 342 CAN1_RX1_IRQHandler
<> 144:ef7eb2e8f9f7 343 CAN1_SCE_IRQHandler
<> 144:ef7eb2e8f9f7 344 EXTI9_5_IRQHandler
<> 144:ef7eb2e8f9f7 345 TIM1_BRK_TIM9_IRQHandler
<> 144:ef7eb2e8f9f7 346 TIM1_UP_TIM10_IRQHandler
<> 144:ef7eb2e8f9f7 347 TIM1_TRG_COM_TIM11_IRQHandler
<> 144:ef7eb2e8f9f7 348 TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 349 TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 350 TIM3_IRQHandler
<> 144:ef7eb2e8f9f7 351 TIM4_IRQHandler
<> 144:ef7eb2e8f9f7 352 I2C1_EV_IRQHandler
<> 144:ef7eb2e8f9f7 353 I2C1_ER_IRQHandler
<> 144:ef7eb2e8f9f7 354 I2C2_EV_IRQHandler
<> 144:ef7eb2e8f9f7 355 I2C2_ER_IRQHandler
<> 144:ef7eb2e8f9f7 356 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 357 SPI2_IRQHandler
<> 144:ef7eb2e8f9f7 358 USART1_IRQHandler
<> 144:ef7eb2e8f9f7 359 USART2_IRQHandler
<> 144:ef7eb2e8f9f7 360 USART3_IRQHandler
<> 144:ef7eb2e8f9f7 361 EXTI15_10_IRQHandler
<> 144:ef7eb2e8f9f7 362 RTC_Alarm_IRQHandler
<> 144:ef7eb2e8f9f7 363 OTG_FS_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 364 TIM8_BRK_TIM12_IRQHandler
<> 144:ef7eb2e8f9f7 365 TIM8_UP_TIM13_IRQHandler
<> 144:ef7eb2e8f9f7 366 TIM8_TRG_COM_TIM14_IRQHandler
<> 144:ef7eb2e8f9f7 367 TIM8_CC_IRQHandler
<> 144:ef7eb2e8f9f7 368 DMA1_Stream7_IRQHandler
<> 144:ef7eb2e8f9f7 369 FSMC_IRQHandler
<> 144:ef7eb2e8f9f7 370 SDIO_IRQHandler
<> 144:ef7eb2e8f9f7 371 TIM5_IRQHandler
<> 144:ef7eb2e8f9f7 372 SPI3_IRQHandler
<> 144:ef7eb2e8f9f7 373 UART4_IRQHandler
<> 144:ef7eb2e8f9f7 374 UART5_IRQHandler
<> 144:ef7eb2e8f9f7 375 TIM6_DAC_IRQHandler
<> 144:ef7eb2e8f9f7 376 TIM7_IRQHandler
<> 144:ef7eb2e8f9f7 377 DMA2_Stream0_IRQHandler
<> 144:ef7eb2e8f9f7 378 DMA2_Stream1_IRQHandler
<> 144:ef7eb2e8f9f7 379 DMA2_Stream2_IRQHandler
<> 144:ef7eb2e8f9f7 380 DMA2_Stream3_IRQHandler
<> 144:ef7eb2e8f9f7 381 DMA2_Stream4_IRQHandler
<> 144:ef7eb2e8f9f7 382 ETH_IRQHandler
<> 144:ef7eb2e8f9f7 383 ETH_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 384 CAN2_TX_IRQHandler
<> 144:ef7eb2e8f9f7 385 CAN2_RX0_IRQHandler
<> 144:ef7eb2e8f9f7 386 CAN2_RX1_IRQHandler
<> 144:ef7eb2e8f9f7 387 CAN2_SCE_IRQHandler
<> 144:ef7eb2e8f9f7 388 OTG_FS_IRQHandler
<> 144:ef7eb2e8f9f7 389 DMA2_Stream5_IRQHandler
<> 144:ef7eb2e8f9f7 390 DMA2_Stream6_IRQHandler
<> 144:ef7eb2e8f9f7 391 DMA2_Stream7_IRQHandler
<> 144:ef7eb2e8f9f7 392 USART6_IRQHandler
<> 144:ef7eb2e8f9f7 393 I2C3_EV_IRQHandler
<> 144:ef7eb2e8f9f7 394 I2C3_ER_IRQHandler
<> 144:ef7eb2e8f9f7 395 OTG_HS_EP1_OUT_IRQHandler
<> 144:ef7eb2e8f9f7 396 OTG_HS_EP1_IN_IRQHandler
<> 144:ef7eb2e8f9f7 397 OTG_HS_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 398 OTG_HS_IRQHandler
<> 144:ef7eb2e8f9f7 399 DCMI_IRQHandler
<> 144:ef7eb2e8f9f7 400 HASH_RNG_IRQHandler
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 B .
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 ENDP
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 ALIGN
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 409 ; User Stack and Heap initialization
<> 144:ef7eb2e8f9f7 410 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 411 IF :DEF:__MICROLIB
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 414 EXPORT __heap_base
<> 144:ef7eb2e8f9f7 415 EXPORT __heap_limit
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 ELSE
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 IMPORT __use_two_region_memory
<> 144:ef7eb2e8f9f7 420 EXPORT __user_initial_stackheap
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 __user_initial_stackheap
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 LDR R0, = Heap_Mem
<> 144:ef7eb2e8f9f7 425 LDR R1, =(Stack_Mem + Stack_Size)
<> 144:ef7eb2e8f9f7 426 LDR R2, = (Heap_Mem + Heap_Size)
<> 144:ef7eb2e8f9f7 427 LDR R3, = Stack_Mem
<> 144:ef7eb2e8f9f7 428 BX LR
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 ALIGN
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 ENDIF
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 END
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****