mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
124:6a4a5b7d7324 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_adc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the Analog to Digital Convertor (ADC)
<> 144:ef7eb2e8f9f7 9 * peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * ++ Initialization and Configuration of ADC
<> 144:ef7eb2e8f9f7 12 * + Operation functions
<> 144:ef7eb2e8f9f7 13 * ++ Start, stop, get result of conversions of regular
<> 144:ef7eb2e8f9f7 14 * group, using 3 possible modes: polling, interruption or DMA.
<> 144:ef7eb2e8f9f7 15 * + Control functions
<> 144:ef7eb2e8f9f7 16 * ++ Channels configuration on regular group
<> 144:ef7eb2e8f9f7 17 * ++ Channels configuration on injected group
<> 144:ef7eb2e8f9f7 18 * ++ Analog Watchdog configuration
<> 144:ef7eb2e8f9f7 19 * + State functions
<> 144:ef7eb2e8f9f7 20 * ++ ADC state machine management
<> 144:ef7eb2e8f9f7 21 * ++ Interrupts and flags management
<> 144:ef7eb2e8f9f7 22 * Other functions (extended functions) are available in file
<> 144:ef7eb2e8f9f7 23 * "stm32f1xx_hal_adc_ex.c".
<> 144:ef7eb2e8f9f7 24 *
<> 144:ef7eb2e8f9f7 25 @verbatim
<> 144:ef7eb2e8f9f7 26 ==============================================================================
<> 144:ef7eb2e8f9f7 27 ##### ADC peripheral features #####
<> 144:ef7eb2e8f9f7 28 ==============================================================================
<> 144:ef7eb2e8f9f7 29 [..]
<> 144:ef7eb2e8f9f7 30 (+) 12-bit resolution
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 (+) Interrupt generation at the end of regular conversion, end of injected
<> 144:ef7eb2e8f9f7 33 conversion, and in case of analog watchdog or overrun events.
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 (+) Single and continuous conversion modes.
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 (+) Scan mode for conversion of several channels sequentially.
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 (+) Data alignment with in-built data coherency.
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (+) Programmable sampling time (channel wise)
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 (+) ADC conversion of regular group and injected group.
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 (+) External trigger (timer or EXTI)
<> 144:ef7eb2e8f9f7 46 for both regular and injected groups.
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 (+) DMA request generation for transfer of conversions data of regular group.
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 (+) Multimode Dual mode (available on devices with 2 ADCs or more).
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 (+) Configurable DMA data storage in Multimode Dual mode (available on devices
<> 144:ef7eb2e8f9f7 53 with 2 DCs or more).
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 (+) Configurable delay between conversions in Dual interleaved mode (available
<> 144:ef7eb2e8f9f7 56 on devices with 2 DCs or more).
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 (+) ADC calibration
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
<> 144:ef7eb2e8f9f7 61 slower speed.
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
<> 144:ef7eb2e8f9f7 64 Vdda or to an external voltage reference).
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 68 ==============================================================================
<> 144:ef7eb2e8f9f7 69 [..]
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 *** Configuration of top level parameters related to ADC ***
<> 144:ef7eb2e8f9f7 72 ============================================================
<> 144:ef7eb2e8f9f7 73 [..]
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 (#) Enable the ADC interface
<> 144:ef7eb2e8f9f7 76 (++) As prerequisite, ADC clock must be configured at RCC top level.
<> 144:ef7eb2e8f9f7 77 Caution: On STM32F1, ADC clock frequency max is 14MHz (refer
<> 144:ef7eb2e8f9f7 78 to device datasheet).
<> 144:ef7eb2e8f9f7 79 Therefore, ADC clock prescaler must be configured in
<> 144:ef7eb2e8f9f7 80 function of ADC clock source frequency to remain below
<> 144:ef7eb2e8f9f7 81 this maximum frequency.
<> 144:ef7eb2e8f9f7 82 (++) One clock setting is mandatory:
<> 144:ef7eb2e8f9f7 83 ADC clock (core clock, also possibly conversion clock).
<> 144:ef7eb2e8f9f7 84 (+++) Example:
<> 144:ef7eb2e8f9f7 85 Into HAL_ADC_MspInit() (recommended code location) or with
<> 144:ef7eb2e8f9f7 86 other device clock parameters configuration:
<> 144:ef7eb2e8f9f7 87 (+++) RCC_PeriphCLKInitTypeDef PeriphClkInit;
<> 144:ef7eb2e8f9f7 88 (+++) __ADC1_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 89 (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
<> 144:ef7eb2e8f9f7 90 (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
<> 144:ef7eb2e8f9f7 91 (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 (#) ADC pins configuration
<> 144:ef7eb2e8f9f7 94 (++) Enable the clock for the ADC GPIOs
<> 144:ef7eb2e8f9f7 95 using macro __HAL_RCC_GPIOx_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 96 (++) Configure these ADC pins in analog mode
<> 144:ef7eb2e8f9f7 97 using function HAL_GPIO_Init()
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 (#) Optionally, in case of usage of ADC with interruptions:
<> 144:ef7eb2e8f9f7 100 (++) Configure the NVIC for ADC
<> 144:ef7eb2e8f9f7 101 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
<> 144:ef7eb2e8f9f7 102 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
<> 144:ef7eb2e8f9f7 103 into the function of corresponding ADC interruption vector
<> 144:ef7eb2e8f9f7 104 ADCx_IRQHandler().
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 (#) Optionally, in case of usage of DMA:
<> 144:ef7eb2e8f9f7 107 (++) Configure the DMA (DMA channel, mode normal or circular, ...)
<> 144:ef7eb2e8f9f7 108 using function HAL_DMA_Init().
<> 144:ef7eb2e8f9f7 109 (++) Configure the NVIC for DMA
<> 144:ef7eb2e8f9f7 110 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
<> 144:ef7eb2e8f9f7 111 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
<> 144:ef7eb2e8f9f7 112 into the function of corresponding DMA interruption vector
<> 144:ef7eb2e8f9f7 113 DMAx_Channelx_IRQHandler().
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 *** Configuration of ADC, groups regular/injected, channels parameters ***
<> 144:ef7eb2e8f9f7 116 ==========================================================================
<> 144:ef7eb2e8f9f7 117 [..]
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 (#) Configure the ADC parameters (resolution, data alignment, ...)
<> 144:ef7eb2e8f9f7 120 and regular group parameters (conversion trigger, sequencer, ...)
<> 144:ef7eb2e8f9f7 121 using function HAL_ADC_Init().
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 (#) Configure the channels for regular group parameters (channel number,
<> 144:ef7eb2e8f9f7 124 channel rank into sequencer, ..., into regular group)
<> 144:ef7eb2e8f9f7 125 using function HAL_ADC_ConfigChannel().
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 (#) Optionally, configure the injected group parameters (conversion trigger,
<> 144:ef7eb2e8f9f7 128 sequencer, ..., of injected group)
<> 144:ef7eb2e8f9f7 129 and the channels for injected group parameters (channel number,
<> 144:ef7eb2e8f9f7 130 channel rank into sequencer, ..., into injected group)
<> 144:ef7eb2e8f9f7 131 using function HAL_ADCEx_InjectedConfigChannel().
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 (#) Optionally, configure the analog watchdog parameters (channels
<> 144:ef7eb2e8f9f7 134 monitored, thresholds, ...)
<> 144:ef7eb2e8f9f7 135 using function HAL_ADC_AnalogWDGConfig().
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 (#) Optionally, for devices with several ADC instances: configure the
<> 144:ef7eb2e8f9f7 138 multimode parameters
<> 144:ef7eb2e8f9f7 139 using function HAL_ADCEx_MultiModeConfigChannel().
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 *** Execution of ADC conversions ***
<> 144:ef7eb2e8f9f7 142 ====================================
<> 144:ef7eb2e8f9f7 143 [..]
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 (#) Optionally, perform an automatic ADC calibration to improve the
<> 144:ef7eb2e8f9f7 146 conversion accuracy
<> 144:ef7eb2e8f9f7 147 using function HAL_ADCEx_Calibration_Start().
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 (#) ADC driver can be used among three modes: polling, interruption,
<> 144:ef7eb2e8f9f7 150 transfer by DMA.
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 (++) ADC conversion by polling:
<> 144:ef7eb2e8f9f7 153 (+++) Activate the ADC peripheral and start conversions
<> 144:ef7eb2e8f9f7 154 using function HAL_ADC_Start()
<> 144:ef7eb2e8f9f7 155 (+++) Wait for ADC conversion completion
<> 144:ef7eb2e8f9f7 156 using function HAL_ADC_PollForConversion()
<> 144:ef7eb2e8f9f7 157 (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
<> 144:ef7eb2e8f9f7 158 (+++) Retrieve conversion results
<> 144:ef7eb2e8f9f7 159 using function HAL_ADC_GetValue()
<> 144:ef7eb2e8f9f7 160 (or for injected group: HAL_ADCEx_InjectedGetValue() )
<> 144:ef7eb2e8f9f7 161 (+++) Stop conversion and disable the ADC peripheral
<> 144:ef7eb2e8f9f7 162 using function HAL_ADC_Stop()
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 (++) ADC conversion by interruption:
<> 144:ef7eb2e8f9f7 165 (+++) Activate the ADC peripheral and start conversions
<> 144:ef7eb2e8f9f7 166 using function HAL_ADC_Start_IT()
<> 144:ef7eb2e8f9f7 167 (+++) Wait for ADC conversion completion by call of function
<> 144:ef7eb2e8f9f7 168 HAL_ADC_ConvCpltCallback()
<> 144:ef7eb2e8f9f7 169 (this function must be implemented in user program)
<> 144:ef7eb2e8f9f7 170 (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
<> 144:ef7eb2e8f9f7 171 (+++) Retrieve conversion results
<> 144:ef7eb2e8f9f7 172 using function HAL_ADC_GetValue()
<> 144:ef7eb2e8f9f7 173 (or for injected group: HAL_ADCEx_InjectedGetValue() )
<> 144:ef7eb2e8f9f7 174 (+++) Stop conversion and disable the ADC peripheral
<> 144:ef7eb2e8f9f7 175 using function HAL_ADC_Stop_IT()
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 (++) ADC conversion with transfer by DMA:
<> 144:ef7eb2e8f9f7 178 (+++) Activate the ADC peripheral and start conversions
<> 144:ef7eb2e8f9f7 179 using function HAL_ADC_Start_DMA()
<> 144:ef7eb2e8f9f7 180 (+++) Wait for ADC conversion completion by call of function
<> 144:ef7eb2e8f9f7 181 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
<> 144:ef7eb2e8f9f7 182 (these functions must be implemented in user program)
<> 144:ef7eb2e8f9f7 183 (+++) Conversion results are automatically transferred by DMA into
<> 144:ef7eb2e8f9f7 184 destination variable address.
<> 144:ef7eb2e8f9f7 185 (+++) Stop conversion and disable the ADC peripheral
<> 144:ef7eb2e8f9f7 186 using function HAL_ADC_Stop_DMA()
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 (++) For devices with several ADCs: ADC multimode conversion
<> 144:ef7eb2e8f9f7 189 with transfer by DMA:
<> 144:ef7eb2e8f9f7 190 (+++) Activate the ADC peripheral (slave) and start conversions
<> 144:ef7eb2e8f9f7 191 using function HAL_ADC_Start()
<> 144:ef7eb2e8f9f7 192 (+++) Activate the ADC peripheral (master) and start conversions
<> 144:ef7eb2e8f9f7 193 using function HAL_ADCEx_MultiModeStart_DMA()
<> 144:ef7eb2e8f9f7 194 (+++) Wait for ADC conversion completion by call of function
<> 144:ef7eb2e8f9f7 195 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
<> 144:ef7eb2e8f9f7 196 (these functions must be implemented in user program)
<> 144:ef7eb2e8f9f7 197 (+++) Conversion results are automatically transferred by DMA into
<> 144:ef7eb2e8f9f7 198 destination variable address.
<> 144:ef7eb2e8f9f7 199 (+++) Stop conversion and disable the ADC peripheral (master)
<> 144:ef7eb2e8f9f7 200 using function HAL_ADCEx_MultiModeStop_DMA()
<> 144:ef7eb2e8f9f7 201 (+++) Stop conversion and disable the ADC peripheral (slave)
<> 144:ef7eb2e8f9f7 202 using function HAL_ADC_Stop_IT()
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 [..]
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 (@) Callback functions must be implemented in user program:
<> 144:ef7eb2e8f9f7 207 (+@) HAL_ADC_ErrorCallback()
<> 144:ef7eb2e8f9f7 208 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
<> 144:ef7eb2e8f9f7 209 (+@) HAL_ADC_ConvCpltCallback()
<> 144:ef7eb2e8f9f7 210 (+@) HAL_ADC_ConvHalfCpltCallback
<> 144:ef7eb2e8f9f7 211 (+@) HAL_ADCEx_InjectedConvCpltCallback()
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 *** Deinitialization of ADC ***
<> 144:ef7eb2e8f9f7 214 ============================================================
<> 144:ef7eb2e8f9f7 215 [..]
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 (#) Disable the ADC interface
<> 144:ef7eb2e8f9f7 218 (++) ADC clock can be hard reset and disabled at RCC top level.
<> 144:ef7eb2e8f9f7 219 (++) Hard reset of ADC peripherals
<> 144:ef7eb2e8f9f7 220 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
<> 144:ef7eb2e8f9f7 221 (++) ADC clock disable
<> 144:ef7eb2e8f9f7 222 using the equivalent macro/functions as configuration step.
<> 144:ef7eb2e8f9f7 223 (+++) Example:
<> 144:ef7eb2e8f9f7 224 Into HAL_ADC_MspDeInit() (recommended code location) or with
<> 144:ef7eb2e8f9f7 225 other device clock parameters configuration:
<> 144:ef7eb2e8f9f7 226 (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
<> 144:ef7eb2e8f9f7 227 (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF
<> 144:ef7eb2e8f9f7 228 (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 (#) ADC pins configuration
<> 144:ef7eb2e8f9f7 231 (++) Disable the clock for the ADC GPIOs
<> 144:ef7eb2e8f9f7 232 using macro __HAL_RCC_GPIOx_CLK_DISABLE()
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 (#) Optionally, in case of usage of ADC with interruptions:
<> 144:ef7eb2e8f9f7 235 (++) Disable the NVIC for ADC
<> 144:ef7eb2e8f9f7 236 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 (#) Optionally, in case of usage of DMA:
<> 144:ef7eb2e8f9f7 239 (++) Deinitialize the DMA
<> 144:ef7eb2e8f9f7 240 using function HAL_DMA_Init().
<> 144:ef7eb2e8f9f7 241 (++) Disable the NVIC for DMA
<> 144:ef7eb2e8f9f7 242 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 [..]
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 @endverbatim
<> 144:ef7eb2e8f9f7 247 ******************************************************************************
<> 144:ef7eb2e8f9f7 248 * @attention
<> 144:ef7eb2e8f9f7 249 *
<> 144:ef7eb2e8f9f7 250 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 251 *
<> 144:ef7eb2e8f9f7 252 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 253 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 254 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 255 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 256 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 257 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 258 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 259 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 260 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 261 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 262 *
<> 144:ef7eb2e8f9f7 263 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 264 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 265 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 266 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 267 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 268 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 269 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 270 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 271 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 272 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 273 *
<> 144:ef7eb2e8f9f7 274 ******************************************************************************
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 278 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 281 * @{
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /** @defgroup ADC ADC
<> 144:ef7eb2e8f9f7 285 * @brief ADC HAL module driver
<> 144:ef7eb2e8f9f7 286 * @{
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 #ifdef HAL_ADC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 292 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 293 /** @defgroup ADC_Private_Constants ADC Private Constants
<> 144:ef7eb2e8f9f7 294 * @{
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* Timeout values for ADC enable and disable settling time. */
<> 144:ef7eb2e8f9f7 298 /* Values defined to be higher than worst cases: low clocks freq, */
<> 144:ef7eb2e8f9f7 299 /* maximum prescaler. */
<> 144:ef7eb2e8f9f7 300 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
<> 144:ef7eb2e8f9f7 301 /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
<> 144:ef7eb2e8f9f7 302 /* Unit: ms */
<> 144:ef7eb2e8f9f7 303 #define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
<> 144:ef7eb2e8f9f7 304 #define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Delay for ADC stabilization time. */
<> 144:ef7eb2e8f9f7 307 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
<> 144:ef7eb2e8f9f7 308 /* Unit: us */
<> 144:ef7eb2e8f9f7 309 #define ADC_STAB_DELAY_US ((uint32_t) 1)
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /* Delay for temperature sensor stabilization time. */
<> 144:ef7eb2e8f9f7 312 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
<> 144:ef7eb2e8f9f7 313 /* Unit: us */
<> 144:ef7eb2e8f9f7 314 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /**
<> 144:ef7eb2e8f9f7 317 * @}
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 321 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 322 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 323 /** @defgroup ADC_Private_Functions ADC Private Functions
<> 144:ef7eb2e8f9f7 324 * @{
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326 /**
<> 144:ef7eb2e8f9f7 327 * @}
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /** @defgroup ADC_Exported_Functions ADC Exported Functions
<> 144:ef7eb2e8f9f7 333 * @{
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 337 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 338 *
<> 144:ef7eb2e8f9f7 339 @verbatim
<> 144:ef7eb2e8f9f7 340 ===============================================================================
<> 144:ef7eb2e8f9f7 341 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 342 ===============================================================================
<> 144:ef7eb2e8f9f7 343 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 344 (+) Initialize and configure the ADC.
<> 144:ef7eb2e8f9f7 345 (+) De-initialize the ADC.
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 @endverbatim
<> 144:ef7eb2e8f9f7 348 * @{
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @brief Initializes the ADC peripheral and regular group according to
<> 144:ef7eb2e8f9f7 353 * parameters specified in structure "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 354 * @note As prerequisite, ADC clock must be configured at RCC top level
<> 144:ef7eb2e8f9f7 355 * (clock source APB2).
<> 144:ef7eb2e8f9f7 356 * See commented example code below that can be copied and uncommented
<> 144:ef7eb2e8f9f7 357 * into HAL_ADC_MspInit().
<> 144:ef7eb2e8f9f7 358 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 359 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
<> 144:ef7eb2e8f9f7 360 * coming from ADC state reset. Following calls to this function can
<> 144:ef7eb2e8f9f7 361 * be used to reconfigure some parameters of ADC_InitTypeDef
<> 144:ef7eb2e8f9f7 362 * structure on the fly, without modifying MSP configuration. If ADC
<> 144:ef7eb2e8f9f7 363 * MSP has to be modified again, HAL_ADC_DeInit() must be called
<> 144:ef7eb2e8f9f7 364 * before HAL_ADC_Init().
<> 144:ef7eb2e8f9f7 365 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 366 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 367 * "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 368 * @note This function configures the ADC within 2 scopes: scope of entire
<> 144:ef7eb2e8f9f7 369 * ADC and scope of regular group. For parameters details, see comments
<> 144:ef7eb2e8f9f7 370 * of structure "ADC_InitTypeDef".
<> 144:ef7eb2e8f9f7 371 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 372 * @retval HAL status
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 375 {
<> 144:ef7eb2e8f9f7 376 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 377 uint32_t tmp_cr1 = 0;
<> 144:ef7eb2e8f9f7 378 uint32_t tmp_cr2 = 0;
<> 144:ef7eb2e8f9f7 379 uint32_t tmp_sqr1 = 0;
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /* Check ADC handle */
<> 144:ef7eb2e8f9f7 382 if(hadc == NULL)
<> 144:ef7eb2e8f9f7 383 {
<> 144:ef7eb2e8f9f7 384 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 385 }
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /* Check the parameters */
<> 144:ef7eb2e8f9f7 388 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 389 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
<> 144:ef7eb2e8f9f7 390 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
<> 144:ef7eb2e8f9f7 391 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 144:ef7eb2e8f9f7 392 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
<> 144:ef7eb2e8f9f7 395 {
<> 144:ef7eb2e8f9f7 396 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
<> 144:ef7eb2e8f9f7 397 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
<> 144:ef7eb2e8f9f7 398 if(hadc->Init.DiscontinuousConvMode != DISABLE)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
<> 144:ef7eb2e8f9f7 405 /* at RCC top level. */
<> 144:ef7eb2e8f9f7 406 /* Refer to header of this file for more details on clock enabling */
<> 144:ef7eb2e8f9f7 407 /* procedure. */
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Actions performed only if ADC is coming from state reset: */
<> 144:ef7eb2e8f9f7 410 /* - Initialization of ADC MSP */
<> 144:ef7eb2e8f9f7 411 if (hadc->State == HAL_ADC_STATE_RESET)
<> 144:ef7eb2e8f9f7 412 {
<> 144:ef7eb2e8f9f7 413 /* Initialize ADC error code */
<> 144:ef7eb2e8f9f7 414 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 417 hadc->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 420 HAL_ADC_MspInit(hadc);
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 424 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 425 /* Note: In case of ADC already enabled, precaution to not launch an */
<> 144:ef7eb2e8f9f7 426 /* unwanted conversion while modifying register CR2 by writing 1 to */
<> 144:ef7eb2e8f9f7 427 /* bit ADON. */
<> 144:ef7eb2e8f9f7 428 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /* Configuration of ADC parameters if previous preliminary actions are */
<> 144:ef7eb2e8f9f7 432 /* correctly completed. */
<> 144:ef7eb2e8f9f7 433 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
<> 144:ef7eb2e8f9f7 434 (tmp_hal_status == HAL_OK) )
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 /* Set ADC state */
<> 144:ef7eb2e8f9f7 437 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 438 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 439 HAL_ADC_STATE_BUSY_INTERNAL);
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* Set ADC parameters */
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Configuration of ADC: */
<> 144:ef7eb2e8f9f7 444 /* - data alignment */
<> 144:ef7eb2e8f9f7 445 /* - external trigger to start conversion */
<> 144:ef7eb2e8f9f7 446 /* - external trigger polarity (always set to 1, because needed for all */
<> 144:ef7eb2e8f9f7 447 /* triggers: external trigger of SW start) */
<> 144:ef7eb2e8f9f7 448 /* - continuous conversion mode */
<> 144:ef7eb2e8f9f7 449 /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
<> 144:ef7eb2e8f9f7 450 /* HAL_ADC_Start_xxx functions because if set in this function, */
<> 144:ef7eb2e8f9f7 451 /* a conversion on injected group would start a conversion also on */
<> 144:ef7eb2e8f9f7 452 /* regular group after ADC enabling. */
<> 144:ef7eb2e8f9f7 453 tmp_cr2 |= (hadc->Init.DataAlign |
<> 144:ef7eb2e8f9f7 454 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
<> 144:ef7eb2e8f9f7 455 ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /* Configuration of ADC: */
<> 144:ef7eb2e8f9f7 458 /* - scan mode */
<> 144:ef7eb2e8f9f7 459 /* - discontinuous mode disable/enable */
<> 144:ef7eb2e8f9f7 460 /* - discontinuous mode number of conversions */
<> 144:ef7eb2e8f9f7 461 tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Enable discontinuous mode only if continuous mode is disabled */
<> 144:ef7eb2e8f9f7 464 /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
<> 144:ef7eb2e8f9f7 465 /* discontinuous is set anyway, but will have no effect on ADC HW. */
<> 144:ef7eb2e8f9f7 466 if (hadc->Init.DiscontinuousConvMode == ENABLE)
<> 144:ef7eb2e8f9f7 467 {
<> 144:ef7eb2e8f9f7 468 if (hadc->Init.ContinuousConvMode == DISABLE)
<> 144:ef7eb2e8f9f7 469 {
<> 144:ef7eb2e8f9f7 470 /* Enable the selected ADC regular discontinuous mode */
<> 144:ef7eb2e8f9f7 471 /* Set the number of channels to be converted in discontinuous mode */
<> 144:ef7eb2e8f9f7 472 SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
<> 144:ef7eb2e8f9f7 473 ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475 else
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 /* ADC regular group settings continuous and sequencer discontinuous*/
<> 144:ef7eb2e8f9f7 478 /* cannot be enabled simultaneously. */
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 481 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 484 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Update ADC configuration register CR1 with previous settings */
<> 144:ef7eb2e8f9f7 489 MODIFY_REG(hadc->Instance->CR1,
<> 144:ef7eb2e8f9f7 490 ADC_CR1_SCAN |
<> 144:ef7eb2e8f9f7 491 ADC_CR1_DISCEN |
<> 144:ef7eb2e8f9f7 492 ADC_CR1_DISCNUM ,
<> 144:ef7eb2e8f9f7 493 tmp_cr1 );
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Update ADC configuration register CR2 with previous settings */
<> 144:ef7eb2e8f9f7 496 MODIFY_REG(hadc->Instance->CR2,
<> 144:ef7eb2e8f9f7 497 ADC_CR2_ALIGN |
<> 144:ef7eb2e8f9f7 498 ADC_CR2_EXTSEL |
<> 144:ef7eb2e8f9f7 499 ADC_CR2_EXTTRIG |
<> 144:ef7eb2e8f9f7 500 ADC_CR2_CONT ,
<> 144:ef7eb2e8f9f7 501 tmp_cr2 );
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Configuration of regular group sequencer: */
<> 144:ef7eb2e8f9f7 504 /* - if scan mode is disabled, regular channels sequence length is set to */
<> 144:ef7eb2e8f9f7 505 /* 0x00: 1 channel converted (channel on regular rank 1) */
<> 144:ef7eb2e8f9f7 506 /* Parameter "NbrOfConversion" is discarded. */
<> 144:ef7eb2e8f9f7 507 /* Note: Scan mode is present by hardware on this device and, if */
<> 144:ef7eb2e8f9f7 508 /* disabled, discards automatically nb of conversions. Anyway, nb of */
<> 144:ef7eb2e8f9f7 509 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
<> 144:ef7eb2e8f9f7 510 /* - if scan mode is enabled, regular channels sequence length is set to */
<> 144:ef7eb2e8f9f7 511 /* parameter "NbrOfConversion" */
<> 144:ef7eb2e8f9f7 512 if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
<> 144:ef7eb2e8f9f7 513 {
<> 144:ef7eb2e8f9f7 514 tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 MODIFY_REG(hadc->Instance->SQR1,
<> 144:ef7eb2e8f9f7 518 ADC_SQR1_L ,
<> 144:ef7eb2e8f9f7 519 tmp_sqr1 );
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /* Check back that ADC registers have effectively been configured to */
<> 144:ef7eb2e8f9f7 522 /* ensure of no potential problem of ADC core IP clocking. */
<> 144:ef7eb2e8f9f7 523 /* Check through register CR2 (excluding bits set in other functions: */
<> 144:ef7eb2e8f9f7 524 /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
<> 144:ef7eb2e8f9f7 525 /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
<> 144:ef7eb2e8f9f7 526 /* measurement path bit (TSVREFE). */
<> 144:ef7eb2e8f9f7 527 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
<> 144:ef7eb2e8f9f7 528 ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
<> 144:ef7eb2e8f9f7 529 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
<> 144:ef7eb2e8f9f7 530 ADC_CR2_TSVREFE ))
<> 144:ef7eb2e8f9f7 531 == tmp_cr2)
<> 144:ef7eb2e8f9f7 532 {
<> 144:ef7eb2e8f9f7 533 /* Set ADC error code to none */
<> 144:ef7eb2e8f9f7 534 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Set the ADC state */
<> 144:ef7eb2e8f9f7 537 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 538 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 539 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 540 }
<> 144:ef7eb2e8f9f7 541 else
<> 144:ef7eb2e8f9f7 542 {
<> 144:ef7eb2e8f9f7 543 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 544 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 545 HAL_ADC_STATE_BUSY_INTERNAL,
<> 144:ef7eb2e8f9f7 546 HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 549 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 552 }
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 }
<> 144:ef7eb2e8f9f7 555 else
<> 144:ef7eb2e8f9f7 556 {
<> 144:ef7eb2e8f9f7 557 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 558 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /* Return function status */
<> 144:ef7eb2e8f9f7 564 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 565 }
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /**
<> 144:ef7eb2e8f9f7 568 * @brief Deinitialize the ADC peripheral registers to their default reset
<> 144:ef7eb2e8f9f7 569 * values, with deinitialization of the ADC MSP.
<> 144:ef7eb2e8f9f7 570 * If needed, the example code can be copied and uncommented into
<> 144:ef7eb2e8f9f7 571 * function HAL_ADC_MspDeInit().
<> 144:ef7eb2e8f9f7 572 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 573 * @retval HAL status
<> 144:ef7eb2e8f9f7 574 */
<> 144:ef7eb2e8f9f7 575 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /* Check ADC handle */
<> 144:ef7eb2e8f9f7 580 if(hadc == NULL)
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 583 }
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /* Check the parameters */
<> 144:ef7eb2e8f9f7 586 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /* Set ADC state */
<> 144:ef7eb2e8f9f7 589 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 592 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 593 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Configuration of ADC parameters if previous preliminary actions are */
<> 144:ef7eb2e8f9f7 597 /* correctly completed. */
<> 144:ef7eb2e8f9f7 598 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 599 {
<> 144:ef7eb2e8f9f7 600 /* ========== Reset ADC registers ========== */
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /* Reset register SR */
<> 144:ef7eb2e8f9f7 606 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
<> 144:ef7eb2e8f9f7 607 ADC_FLAG_JSTRT | ADC_FLAG_STRT));
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Reset register CR1 */
<> 144:ef7eb2e8f9f7 610 CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
<> 144:ef7eb2e8f9f7 611 ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO |
<> 144:ef7eb2e8f9f7 612 ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
<> 144:ef7eb2e8f9f7 613 ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH ));
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /* Reset register CR2 */
<> 144:ef7eb2e8f9f7 616 CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
<> 144:ef7eb2e8f9f7 617 ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG |
<> 144:ef7eb2e8f9f7 618 ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA |
<> 144:ef7eb2e8f9f7 619 ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT |
<> 144:ef7eb2e8f9f7 620 ADC_CR2_ADON ));
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Reset register SMPR1 */
<> 144:ef7eb2e8f9f7 623 CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 |
<> 144:ef7eb2e8f9f7 624 ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 |
<> 144:ef7eb2e8f9f7 625 ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 ));
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /* Reset register SMPR2 */
<> 144:ef7eb2e8f9f7 628 CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 |
<> 144:ef7eb2e8f9f7 629 ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 |
<> 144:ef7eb2e8f9f7 630 ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 |
<> 144:ef7eb2e8f9f7 631 ADC_SMPR2_SMP0 ));
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* Reset register JOFR1 */
<> 144:ef7eb2e8f9f7 634 CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
<> 144:ef7eb2e8f9f7 635 /* Reset register JOFR2 */
<> 144:ef7eb2e8f9f7 636 CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
<> 144:ef7eb2e8f9f7 637 /* Reset register JOFR3 */
<> 144:ef7eb2e8f9f7 638 CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
<> 144:ef7eb2e8f9f7 639 /* Reset register JOFR4 */
<> 144:ef7eb2e8f9f7 640 CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /* Reset register HTR */
<> 144:ef7eb2e8f9f7 643 CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
<> 144:ef7eb2e8f9f7 644 /* Reset register LTR */
<> 144:ef7eb2e8f9f7 645 CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* Reset register SQR1 */
<> 144:ef7eb2e8f9f7 648 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
<> 144:ef7eb2e8f9f7 649 ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
<> 144:ef7eb2e8f9f7 650 ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /* Reset register SQR1 */
<> 144:ef7eb2e8f9f7 653 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
<> 144:ef7eb2e8f9f7 654 ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
<> 144:ef7eb2e8f9f7 655 ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /* Reset register SQR2 */
<> 144:ef7eb2e8f9f7 658 CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
<> 144:ef7eb2e8f9f7 659 ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 );
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* Reset register SQR3 */
<> 144:ef7eb2e8f9f7 662 CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
<> 144:ef7eb2e8f9f7 663 ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 );
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Reset register JSQR */
<> 144:ef7eb2e8f9f7 666 CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
<> 144:ef7eb2e8f9f7 667 ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
<> 144:ef7eb2e8f9f7 668 ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* Reset register JSQR */
<> 144:ef7eb2e8f9f7 671 CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
<> 144:ef7eb2e8f9f7 672 ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
<> 144:ef7eb2e8f9f7 673 ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* Reset register DR */
<> 144:ef7eb2e8f9f7 676 /* bits in access mode read only, no direct reset applicable*/
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
<> 144:ef7eb2e8f9f7 679 /* bits in access mode read only, no direct reset applicable*/
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /* ========== Hard reset ADC peripheral ========== */
<> 144:ef7eb2e8f9f7 682 /* Performs a global reset of the entire ADC peripheral: ADC state is */
<> 144:ef7eb2e8f9f7 683 /* forced to a similar state after device power-on. */
<> 144:ef7eb2e8f9f7 684 /* If needed, copy-paste and uncomment the following reset code into */
<> 144:ef7eb2e8f9f7 685 /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
<> 144:ef7eb2e8f9f7 686 /* */
<> 144:ef7eb2e8f9f7 687 /* __HAL_RCC_ADC1_FORCE_RESET() */
<> 144:ef7eb2e8f9f7 688 /* __HAL_RCC_ADC1_RELEASE_RESET() */
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 691 HAL_ADC_MspDeInit(hadc);
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /* Set ADC error code to none */
<> 144:ef7eb2e8f9f7 694 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /* Set ADC state */
<> 144:ef7eb2e8f9f7 697 hadc->State = HAL_ADC_STATE_RESET;
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /* Process unlocked */
<> 144:ef7eb2e8f9f7 702 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /* Return function status */
<> 144:ef7eb2e8f9f7 705 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /**
<> 144:ef7eb2e8f9f7 709 * @brief Initializes the ADC MSP.
<> 144:ef7eb2e8f9f7 710 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 711 * @retval None
<> 144:ef7eb2e8f9f7 712 */
<> 144:ef7eb2e8f9f7 713 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 716 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 717 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 718 function HAL_ADC_MspInit must be implemented in the user file.
<> 144:ef7eb2e8f9f7 719 */
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 /**
<> 144:ef7eb2e8f9f7 723 * @brief DeInitializes the ADC MSP.
<> 144:ef7eb2e8f9f7 724 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 725 * @retval None
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 728 {
<> 144:ef7eb2e8f9f7 729 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 730 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 731 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 732 function HAL_ADC_MspDeInit must be implemented in the user file.
<> 144:ef7eb2e8f9f7 733 */
<> 144:ef7eb2e8f9f7 734 }
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /**
<> 144:ef7eb2e8f9f7 737 * @}
<> 144:ef7eb2e8f9f7 738 */
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /** @defgroup ADC_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 741 * @brief Input and Output operation functions
<> 144:ef7eb2e8f9f7 742 *
<> 144:ef7eb2e8f9f7 743 @verbatim
<> 144:ef7eb2e8f9f7 744 ===============================================================================
<> 144:ef7eb2e8f9f7 745 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 746 ===============================================================================
<> 144:ef7eb2e8f9f7 747 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 748 (+) Start conversion of regular group.
<> 144:ef7eb2e8f9f7 749 (+) Stop conversion of regular group.
<> 144:ef7eb2e8f9f7 750 (+) Poll for conversion complete on regular group.
<> 144:ef7eb2e8f9f7 751 (+) Poll for conversion event.
<> 144:ef7eb2e8f9f7 752 (+) Get result of regular channel conversion.
<> 144:ef7eb2e8f9f7 753 (+) Start conversion of regular group and enable interruptions.
<> 144:ef7eb2e8f9f7 754 (+) Stop conversion of regular group and disable interruptions.
<> 144:ef7eb2e8f9f7 755 (+) Handle ADC interrupt request
<> 144:ef7eb2e8f9f7 756 (+) Start conversion of regular group and enable DMA transfer.
<> 144:ef7eb2e8f9f7 757 (+) Stop conversion of regular group and disable ADC DMA transfer.
<> 144:ef7eb2e8f9f7 758 @endverbatim
<> 144:ef7eb2e8f9f7 759 * @{
<> 144:ef7eb2e8f9f7 760 */
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /**
<> 144:ef7eb2e8f9f7 763 * @brief Enables ADC, starts conversion of regular group.
<> 144:ef7eb2e8f9f7 764 * Interruptions enabled in this function: None.
<> 144:ef7eb2e8f9f7 765 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 766 * @retval HAL status
<> 144:ef7eb2e8f9f7 767 */
<> 144:ef7eb2e8f9f7 768 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 769 {
<> 144:ef7eb2e8f9f7 770 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /* Check the parameters */
<> 144:ef7eb2e8f9f7 773 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /* Process locked */
<> 144:ef7eb2e8f9f7 776 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 779 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 782 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 783 {
<> 144:ef7eb2e8f9f7 784 /* Set ADC state */
<> 144:ef7eb2e8f9f7 785 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 786 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 787 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 788 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
<> 144:ef7eb2e8f9f7 789 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /* Set group injected state (from auto-injection) and multimode state */
<> 144:ef7eb2e8f9f7 792 /* for all cases of multimode: independent mode, multimode ADC master */
<> 144:ef7eb2e8f9f7 793 /* or multimode ADC slave (for devices with several ADCs): */
<> 144:ef7eb2e8f9f7 794 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 795 {
<> 144:ef7eb2e8f9f7 796 /* Set ADC state (ADC independent or master) */
<> 144:ef7eb2e8f9f7 797 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /* If conversions on group regular are also triggering group injected, */
<> 144:ef7eb2e8f9f7 800 /* update ADC state. */
<> 144:ef7eb2e8f9f7 801 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 804 }
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806 else
<> 144:ef7eb2e8f9f7 807 {
<> 144:ef7eb2e8f9f7 808 /* Set ADC state (ADC slave) */
<> 144:ef7eb2e8f9f7 809 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /* If conversions on group regular are also triggering group injected, */
<> 144:ef7eb2e8f9f7 812 /* update ADC state. */
<> 144:ef7eb2e8f9f7 813 if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
<> 144:ef7eb2e8f9f7 814 {
<> 144:ef7eb2e8f9f7 815 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817 }
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 /* State machine update: Check if an injected conversion is ongoing */
<> 144:ef7eb2e8f9f7 820 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 821 {
<> 144:ef7eb2e8f9f7 822 /* Reset ADC error code fields related to conversions on group regular */
<> 144:ef7eb2e8f9f7 823 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
<> 144:ef7eb2e8f9f7 824 }
<> 144:ef7eb2e8f9f7 825 else
<> 144:ef7eb2e8f9f7 826 {
<> 144:ef7eb2e8f9f7 827 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 828 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 829 }
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /* Process unlocked */
<> 144:ef7eb2e8f9f7 832 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 833 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 834 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Clear regular group conversion flag */
<> 144:ef7eb2e8f9f7 837 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 838 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 841 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 842 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 843 /* trigger event. */
<> 144:ef7eb2e8f9f7 844 /* Case of multimode enabled: */
<> 144:ef7eb2e8f9f7 845 /* - if ADC is slave, ADC is enabled only (conversion is not started). */
<> 144:ef7eb2e8f9f7 846 /* - if ADC is master, ADC is enabled and conversion is started. */
<> 144:ef7eb2e8f9f7 847 /* If ADC is master, ADC is enabled and conversion is started. */
<> 144:ef7eb2e8f9f7 848 /* Note: Alternate trigger for single conversion could be to force an */
<> 144:ef7eb2e8f9f7 849 /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
<> 144:ef7eb2e8f9f7 850 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 851 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
<> 144:ef7eb2e8f9f7 852 {
<> 144:ef7eb2e8f9f7 853 /* Start ADC conversion on regular group with SW start */
<> 144:ef7eb2e8f9f7 854 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
<> 144:ef7eb2e8f9f7 855 }
<> 144:ef7eb2e8f9f7 856 else
<> 144:ef7eb2e8f9f7 857 {
<> 144:ef7eb2e8f9f7 858 /* Start ADC conversion on regular group with external trigger */
<> 144:ef7eb2e8f9f7 859 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
<> 144:ef7eb2e8f9f7 860 }
<> 144:ef7eb2e8f9f7 861 }
<> 144:ef7eb2e8f9f7 862 else
<> 144:ef7eb2e8f9f7 863 {
<> 144:ef7eb2e8f9f7 864 /* Process unlocked */
<> 144:ef7eb2e8f9f7 865 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 866 }
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /* Return function status */
<> 144:ef7eb2e8f9f7 869 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 870 }
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /**
<> 144:ef7eb2e8f9f7 873 * @brief Stop ADC conversion of regular group (and injected channels in
<> 144:ef7eb2e8f9f7 874 * case of auto_injection mode), disable ADC peripheral.
<> 144:ef7eb2e8f9f7 875 * @note: ADC peripheral disable is forcing stop of potential
<> 144:ef7eb2e8f9f7 876 * conversion on injected group. If injected group is under use, it
<> 144:ef7eb2e8f9f7 877 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
<> 144:ef7eb2e8f9f7 878 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 879 * @retval HAL status.
<> 144:ef7eb2e8f9f7 880 */
<> 144:ef7eb2e8f9f7 881 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 882 {
<> 144:ef7eb2e8f9f7 883 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /* Check the parameters */
<> 144:ef7eb2e8f9f7 886 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /* Process locked */
<> 144:ef7eb2e8f9f7 889 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 892 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 893 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 896 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 897 {
<> 144:ef7eb2e8f9f7 898 /* Set ADC state */
<> 144:ef7eb2e8f9f7 899 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 900 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 901 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 902 }
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /* Process unlocked */
<> 144:ef7eb2e8f9f7 905 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /* Return function status */
<> 144:ef7eb2e8f9f7 908 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 909 }
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 /**
<> 144:ef7eb2e8f9f7 912 * @brief Wait for regular group conversion to be completed.
<> 144:ef7eb2e8f9f7 913 * @note This function cannot be used in a particular setup: ADC configured
<> 144:ef7eb2e8f9f7 914 * in DMA mode.
<> 144:ef7eb2e8f9f7 915 * In this case, DMA resets the flag EOC and polling cannot be
<> 144:ef7eb2e8f9f7 916 * performed on each conversion.
<> 144:ef7eb2e8f9f7 917 * @note On STM32F1 devices, limitation in case of sequencer enabled
<> 144:ef7eb2e8f9f7 918 * (several ranks selected): polling cannot be done on each
<> 144:ef7eb2e8f9f7 919 * conversion inside the sequence. In this case, polling is replaced by
<> 144:ef7eb2e8f9f7 920 * wait for maximum conversion time.
<> 144:ef7eb2e8f9f7 921 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 922 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 923 * @retval HAL status
<> 144:ef7eb2e8f9f7 924 */
<> 144:ef7eb2e8f9f7 925 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 926 {
<> 144:ef7eb2e8f9f7 927 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* Variables for polling in case of scan mode enabled and polling for each */
<> 144:ef7eb2e8f9f7 930 /* conversion. */
<> 144:ef7eb2e8f9f7 931 __IO uint32_t Conversion_Timeout_CPU_cycles = 0;
<> 144:ef7eb2e8f9f7 932 uint32_t Conversion_Timeout_CPU_cycles_max = 0;
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 /* Check the parameters */
<> 144:ef7eb2e8f9f7 935 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /* Get tick count */
<> 144:ef7eb2e8f9f7 938 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940 /* Verification that ADC configuration is compliant with polling for */
<> 144:ef7eb2e8f9f7 941 /* each conversion: */
<> 144:ef7eb2e8f9f7 942 /* Particular case is ADC configured in DMA mode */
<> 144:ef7eb2e8f9f7 943 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
<> 144:ef7eb2e8f9f7 944 {
<> 144:ef7eb2e8f9f7 945 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 946 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /* Process unlocked */
<> 144:ef7eb2e8f9f7 949 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 952 }
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /* Polling for end of conversion: differentiation if single/sequence */
<> 144:ef7eb2e8f9f7 955 /* conversion. */
<> 144:ef7eb2e8f9f7 956 /* - If single conversion for regular group (Scan mode disabled or enabled */
<> 144:ef7eb2e8f9f7 957 /* with NbrOfConversion =1), flag EOC is used to determine the */
<> 144:ef7eb2e8f9f7 958 /* conversion completion. */
<> 144:ef7eb2e8f9f7 959 /* - If sequence conversion for regular group (scan mode enabled and */
<> 144:ef7eb2e8f9f7 960 /* NbrOfConversion >=2), flag EOC is set only at the end of the */
<> 144:ef7eb2e8f9f7 961 /* sequence. */
<> 144:ef7eb2e8f9f7 962 /* To poll for each conversion, the maximum conversion time is computed */
<> 144:ef7eb2e8f9f7 963 /* from ADC conversion time (selected sampling time + conversion time of */
<> 144:ef7eb2e8f9f7 964 /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
<> 144:ef7eb2e8f9f7 965 /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
<> 144:ef7eb2e8f9f7 966 /* As flag EOC is not set after each conversion, no timeout status can */
<> 144:ef7eb2e8f9f7 967 /* be set. */
<> 144:ef7eb2e8f9f7 968 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
<> 144:ef7eb2e8f9f7 969 HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) )
<> 144:ef7eb2e8f9f7 970 {
<> 144:ef7eb2e8f9f7 971 /* Wait until End of Conversion flag is raised */
<> 144:ef7eb2e8f9f7 972 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
<> 144:ef7eb2e8f9f7 973 {
<> 144:ef7eb2e8f9f7 974 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 975 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 976 {
<> 144:ef7eb2e8f9f7 977 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 978 {
<> 144:ef7eb2e8f9f7 979 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 980 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 /* Process unlocked */
<> 144:ef7eb2e8f9f7 983 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 986 }
<> 144:ef7eb2e8f9f7 987 }
<> 144:ef7eb2e8f9f7 988 }
<> 144:ef7eb2e8f9f7 989 }
<> 144:ef7eb2e8f9f7 990 else
<> 144:ef7eb2e8f9f7 991 {
<> 144:ef7eb2e8f9f7 992 /* Replace polling by wait for maximum conversion time */
<> 144:ef7eb2e8f9f7 993 /* - Computation of CPU clock cycles corresponding to ADC clock cycles */
<> 144:ef7eb2e8f9f7 994 /* and ADC maximum conversion cycles on all channels. */
<> 144:ef7eb2e8f9f7 995 /* - Wait for the expected ADC clock cycles delay */
<> 144:ef7eb2e8f9f7 996 Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
<> 144:ef7eb2e8f9f7 997 / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
<> 144:ef7eb2e8f9f7 998 * ADC_CONVCYCLES_MAX_RANGE(hadc) );
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
<> 144:ef7eb2e8f9f7 1001 {
<> 144:ef7eb2e8f9f7 1002 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 1003 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1004 {
<> 144:ef7eb2e8f9f7 1005 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1006 {
<> 144:ef7eb2e8f9f7 1007 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 1008 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1011 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1014 }
<> 144:ef7eb2e8f9f7 1015 }
<> 144:ef7eb2e8f9f7 1016 Conversion_Timeout_CPU_cycles ++;
<> 144:ef7eb2e8f9f7 1017 }
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* Clear regular group conversion flag */
<> 144:ef7eb2e8f9f7 1021 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 1024 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 1027 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 1028 /* Note: On STM32F1 devices, in case of sequencer enabled */
<> 144:ef7eb2e8f9f7 1029 /* (several ranks selected), end of conversion flag is raised */
<> 144:ef7eb2e8f9f7 1030 /* at the end of the sequence. */
<> 144:ef7eb2e8f9f7 1031 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 1032 (hadc->Init.ContinuousConvMode == DISABLE) )
<> 144:ef7eb2e8f9f7 1033 {
<> 144:ef7eb2e8f9f7 1034 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1035 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 1038 {
<> 144:ef7eb2e8f9f7 1039 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1040 }
<> 144:ef7eb2e8f9f7 1041 }
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /* Return ADC state */
<> 144:ef7eb2e8f9f7 1044 return HAL_OK;
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /**
<> 144:ef7eb2e8f9f7 1048 * @brief Poll for conversion event.
<> 144:ef7eb2e8f9f7 1049 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1050 * @param EventType: the ADC event type.
<> 144:ef7eb2e8f9f7 1051 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1052 * @arg ADC_AWD_EVENT: ADC Analog watchdog event.
<> 144:ef7eb2e8f9f7 1053 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 1054 * @retval HAL status
<> 144:ef7eb2e8f9f7 1055 */
<> 144:ef7eb2e8f9f7 1056 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1057 {
<> 144:ef7eb2e8f9f7 1058 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1061 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1062 assert_param(IS_ADC_EVENT_TYPE(EventType));
<> 144:ef7eb2e8f9f7 1063
<> 144:ef7eb2e8f9f7 1064 /* Get tick count */
<> 144:ef7eb2e8f9f7 1065 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /* Check selected event flag */
<> 144:ef7eb2e8f9f7 1068 while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
<> 144:ef7eb2e8f9f7 1069 {
<> 144:ef7eb2e8f9f7 1070 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 1071 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1072 {
<> 144:ef7eb2e8f9f7 1073 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1074 {
<> 144:ef7eb2e8f9f7 1075 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 1076 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1079 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1082 }
<> 144:ef7eb2e8f9f7 1083 }
<> 144:ef7eb2e8f9f7 1084 }
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 /* Analog watchdog (level out of window) event */
<> 144:ef7eb2e8f9f7 1087 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1088 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /* Clear ADC analog watchdog flag */
<> 144:ef7eb2e8f9f7 1091 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /* Return ADC state */
<> 144:ef7eb2e8f9f7 1094 return HAL_OK;
<> 144:ef7eb2e8f9f7 1095 }
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /**
<> 144:ef7eb2e8f9f7 1098 * @brief Enables ADC, starts conversion of regular group with interruption.
<> 144:ef7eb2e8f9f7 1099 * Interruptions enabled in this function:
<> 144:ef7eb2e8f9f7 1100 * - EOC (end of conversion of regular group)
<> 144:ef7eb2e8f9f7 1101 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 1102 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1103 * @retval HAL status
<> 144:ef7eb2e8f9f7 1104 */
<> 144:ef7eb2e8f9f7 1105 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1106 {
<> 144:ef7eb2e8f9f7 1107 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1110 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 /* Process locked */
<> 144:ef7eb2e8f9f7 1113 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1116 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 1119 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1120 {
<> 144:ef7eb2e8f9f7 1121 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1122 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 1123 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 1124 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1125 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
<> 144:ef7eb2e8f9f7 1126 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 /* Set group injected state (from auto-injection) and multimode state */
<> 144:ef7eb2e8f9f7 1129 /* for all cases of multimode: independent mode, multimode ADC master */
<> 144:ef7eb2e8f9f7 1130 /* or multimode ADC slave (for devices with several ADCs): */
<> 144:ef7eb2e8f9f7 1131 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 1132 {
<> 144:ef7eb2e8f9f7 1133 /* Set ADC state (ADC independent or master) */
<> 144:ef7eb2e8f9f7 1134 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 1135
<> 144:ef7eb2e8f9f7 1136 /* If conversions on group regular are also triggering group injected, */
<> 144:ef7eb2e8f9f7 1137 /* update ADC state. */
<> 144:ef7eb2e8f9f7 1138 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
<> 144:ef7eb2e8f9f7 1139 {
<> 144:ef7eb2e8f9f7 1140 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 1141 }
<> 144:ef7eb2e8f9f7 1142 }
<> 144:ef7eb2e8f9f7 1143 else
<> 144:ef7eb2e8f9f7 1144 {
<> 144:ef7eb2e8f9f7 1145 /* Set ADC state (ADC slave) */
<> 144:ef7eb2e8f9f7 1146 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148 /* If conversions on group regular are also triggering group injected, */
<> 144:ef7eb2e8f9f7 1149 /* update ADC state. */
<> 144:ef7eb2e8f9f7 1150 if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
<> 144:ef7eb2e8f9f7 1151 {
<> 144:ef7eb2e8f9f7 1152 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 1153 }
<> 144:ef7eb2e8f9f7 1154 }
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /* State machine update: Check if an injected conversion is ongoing */
<> 144:ef7eb2e8f9f7 1157 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 1158 {
<> 144:ef7eb2e8f9f7 1159 /* Reset ADC error code fields related to conversions on group regular */
<> 144:ef7eb2e8f9f7 1160 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
<> 144:ef7eb2e8f9f7 1161 }
<> 144:ef7eb2e8f9f7 1162 else
<> 144:ef7eb2e8f9f7 1163 {
<> 144:ef7eb2e8f9f7 1164 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 1165 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 1166 }
<> 144:ef7eb2e8f9f7 1167
<> 144:ef7eb2e8f9f7 1168 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1169 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 1170 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 1171 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 1174 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 1175 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 /* Enable end of conversion interrupt for regular group */
<> 144:ef7eb2e8f9f7 1178 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
<> 144:ef7eb2e8f9f7 1179
<> 144:ef7eb2e8f9f7 1180 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 1181 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 1182 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 1183 /* trigger event. */
<> 144:ef7eb2e8f9f7 1184 /* Case of multimode enabled: */
<> 144:ef7eb2e8f9f7 1185 /* - if ADC is slave, ADC is enabled only (conversion is not started). */
<> 144:ef7eb2e8f9f7 1186 /* - if ADC is master, ADC is enabled and conversion is started. */
<> 144:ef7eb2e8f9f7 1187 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 1188 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
<> 144:ef7eb2e8f9f7 1189 {
<> 144:ef7eb2e8f9f7 1190 /* Start ADC conversion on regular group with SW start */
<> 144:ef7eb2e8f9f7 1191 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
<> 144:ef7eb2e8f9f7 1192 }
<> 144:ef7eb2e8f9f7 1193 else
<> 144:ef7eb2e8f9f7 1194 {
<> 144:ef7eb2e8f9f7 1195 /* Start ADC conversion on regular group with external trigger */
<> 144:ef7eb2e8f9f7 1196 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
<> 144:ef7eb2e8f9f7 1197 }
<> 144:ef7eb2e8f9f7 1198 }
<> 144:ef7eb2e8f9f7 1199 else
<> 144:ef7eb2e8f9f7 1200 {
<> 144:ef7eb2e8f9f7 1201 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1202 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1203 }
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 /* Return function status */
<> 144:ef7eb2e8f9f7 1206 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1207 }
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /**
<> 144:ef7eb2e8f9f7 1210 * @brief Stop ADC conversion of regular group (and injected group in
<> 144:ef7eb2e8f9f7 1211 * case of auto_injection mode), disable interrution of
<> 144:ef7eb2e8f9f7 1212 * end-of-conversion, disable ADC peripheral.
<> 144:ef7eb2e8f9f7 1213 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1214 * @retval None
<> 144:ef7eb2e8f9f7 1215 */
<> 144:ef7eb2e8f9f7 1216 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1217 {
<> 144:ef7eb2e8f9f7 1218 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1219
<> 144:ef7eb2e8f9f7 1220 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1221 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /* Process locked */
<> 144:ef7eb2e8f9f7 1224 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1225
<> 144:ef7eb2e8f9f7 1226 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 1227 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 1228 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 1231 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1232 {
<> 144:ef7eb2e8f9f7 1233 /* Disable ADC end of conversion interrupt for regular group */
<> 144:ef7eb2e8f9f7 1234 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
<> 144:ef7eb2e8f9f7 1235
<> 144:ef7eb2e8f9f7 1236 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1237 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1238 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 1239 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1240 }
<> 144:ef7eb2e8f9f7 1241
<> 144:ef7eb2e8f9f7 1242 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1243 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 /* Return function status */
<> 144:ef7eb2e8f9f7 1246 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1247 }
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 /**
<> 144:ef7eb2e8f9f7 1250 * @brief Enables ADC, starts conversion of regular group and transfers result
<> 144:ef7eb2e8f9f7 1251 * through DMA.
<> 144:ef7eb2e8f9f7 1252 * Interruptions enabled in this function:
<> 144:ef7eb2e8f9f7 1253 * - DMA transfer complete
<> 144:ef7eb2e8f9f7 1254 * - DMA half transfer
<> 144:ef7eb2e8f9f7 1255 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 1256 * @note For devices with several ADCs: This function is for single-ADC mode
<> 144:ef7eb2e8f9f7 1257 * only. For multimode, use the dedicated MultimodeStart function.
<> 144:ef7eb2e8f9f7 1258 * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
<> 144:ef7eb2e8f9f7 1259 * on devices) have DMA capability.
<> 144:ef7eb2e8f9f7 1260 * ADC2 converted data can be transferred in dual ADC mode using DMA
<> 144:ef7eb2e8f9f7 1261 * of ADC1 (ADC master in multimode).
<> 144:ef7eb2e8f9f7 1262 * In case of using ADC1 with DMA on a device featuring 2 ADC
<> 144:ef7eb2e8f9f7 1263 * instances: ADC1 conversion register DR contains ADC1 conversion
<> 144:ef7eb2e8f9f7 1264 * result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last
<> 144:ef7eb2e8f9f7 1265 * conversion result (ADC1 register DR bits 16 to 27). Therefore, to
<> 144:ef7eb2e8f9f7 1266 * have DMA transferring the conversion results of ADC1 only, DMA must
<> 144:ef7eb2e8f9f7 1267 * be configured to transfer size: half word.
<> 144:ef7eb2e8f9f7 1268 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1269 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 1270 * @param Length: The length of data to be transferred from ADC peripheral to memory.
<> 144:ef7eb2e8f9f7 1271 * @retval None
<> 144:ef7eb2e8f9f7 1272 */
<> 144:ef7eb2e8f9f7 1273 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
<> 144:ef7eb2e8f9f7 1274 {
<> 144:ef7eb2e8f9f7 1275 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1276
<> 144:ef7eb2e8f9f7 1277 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1278 assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 /* Verification if multimode is disabled (for devices with several ADC) */
<> 144:ef7eb2e8f9f7 1281 /* If multimode is enabled, dedicated function multimode conversion */
<> 144:ef7eb2e8f9f7 1282 /* start DMA must be used. */
<> 144:ef7eb2e8f9f7 1283 if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1284 {
<> 144:ef7eb2e8f9f7 1285 /* Process locked */
<> 144:ef7eb2e8f9f7 1286 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1289 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 1292 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1293 {
<> 144:ef7eb2e8f9f7 1294 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1295 /* - Clear state bitfield related to regular group conversion results */
<> 144:ef7eb2e8f9f7 1296 /* - Set state bitfield related to regular operation */
<> 144:ef7eb2e8f9f7 1297 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1298 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
<> 144:ef7eb2e8f9f7 1299 HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 /* Set group injected state (from auto-injection) and multimode state */
<> 144:ef7eb2e8f9f7 1302 /* for all cases of multimode: independent mode, multimode ADC master */
<> 144:ef7eb2e8f9f7 1303 /* or multimode ADC slave (for devices with several ADCs): */
<> 144:ef7eb2e8f9f7 1304 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
<> 144:ef7eb2e8f9f7 1305 {
<> 144:ef7eb2e8f9f7 1306 /* Set ADC state (ADC independent or master) */
<> 144:ef7eb2e8f9f7 1307 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 /* If conversions on group regular are also triggering group injected, */
<> 144:ef7eb2e8f9f7 1310 /* update ADC state. */
<> 144:ef7eb2e8f9f7 1311 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
<> 144:ef7eb2e8f9f7 1312 {
<> 144:ef7eb2e8f9f7 1313 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 1314 }
<> 144:ef7eb2e8f9f7 1315 }
<> 144:ef7eb2e8f9f7 1316 else
<> 144:ef7eb2e8f9f7 1317 {
<> 144:ef7eb2e8f9f7 1318 /* Set ADC state (ADC slave) */
<> 144:ef7eb2e8f9f7 1319 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
<> 144:ef7eb2e8f9f7 1320
<> 144:ef7eb2e8f9f7 1321 /* If conversions on group regular are also triggering group injected, */
<> 144:ef7eb2e8f9f7 1322 /* update ADC state. */
<> 144:ef7eb2e8f9f7 1323 if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
<> 144:ef7eb2e8f9f7 1324 {
<> 144:ef7eb2e8f9f7 1325 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 1326 }
<> 144:ef7eb2e8f9f7 1327 }
<> 144:ef7eb2e8f9f7 1328
<> 144:ef7eb2e8f9f7 1329 /* State machine update: Check if an injected conversion is ongoing */
<> 144:ef7eb2e8f9f7 1330 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 1331 {
<> 144:ef7eb2e8f9f7 1332 /* Reset ADC error code fields related to conversions on group regular */
<> 144:ef7eb2e8f9f7 1333 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
<> 144:ef7eb2e8f9f7 1334 }
<> 144:ef7eb2e8f9f7 1335 else
<> 144:ef7eb2e8f9f7 1336 {
<> 144:ef7eb2e8f9f7 1337 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 1338 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 1339 }
<> 144:ef7eb2e8f9f7 1340
<> 144:ef7eb2e8f9f7 1341 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1342 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 1343 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 1344 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1345
<> 144:ef7eb2e8f9f7 1346 /* Set the DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1347 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
<> 144:ef7eb2e8f9f7 1348
<> 144:ef7eb2e8f9f7 1349 /* Set the DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 1350 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1353 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
<> 144:ef7eb2e8f9f7 1354
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
<> 144:ef7eb2e8f9f7 1357 /* start (in case of SW start): */
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 /* Clear regular group conversion flag and overrun flag */
<> 144:ef7eb2e8f9f7 1360 /* (To ensure of no unknown state from potential previous ADC */
<> 144:ef7eb2e8f9f7 1361 /* operations) */
<> 144:ef7eb2e8f9f7 1362 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 /* Enable ADC DMA mode */
<> 144:ef7eb2e8f9f7 1365 SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 /* Start the DMA channel */
<> 144:ef7eb2e8f9f7 1368 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 /* Enable conversion of regular group. */
<> 144:ef7eb2e8f9f7 1371 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 1372 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 1373 /* trigger event. */
<> 144:ef7eb2e8f9f7 1374 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
<> 144:ef7eb2e8f9f7 1375 {
<> 144:ef7eb2e8f9f7 1376 /* Start ADC conversion on regular group with SW start */
<> 144:ef7eb2e8f9f7 1377 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
<> 144:ef7eb2e8f9f7 1378 }
<> 144:ef7eb2e8f9f7 1379 else
<> 144:ef7eb2e8f9f7 1380 {
<> 144:ef7eb2e8f9f7 1381 /* Start ADC conversion on regular group with external trigger */
<> 144:ef7eb2e8f9f7 1382 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
<> 144:ef7eb2e8f9f7 1383 }
<> 144:ef7eb2e8f9f7 1384 }
<> 144:ef7eb2e8f9f7 1385 else
<> 144:ef7eb2e8f9f7 1386 {
<> 144:ef7eb2e8f9f7 1387 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1388 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1389 }
<> 144:ef7eb2e8f9f7 1390 }
<> 144:ef7eb2e8f9f7 1391 else
<> 144:ef7eb2e8f9f7 1392 {
<> 144:ef7eb2e8f9f7 1393 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1394 }
<> 144:ef7eb2e8f9f7 1395
<> 144:ef7eb2e8f9f7 1396 /* Return function status */
<> 144:ef7eb2e8f9f7 1397 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1398 }
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 /**
<> 144:ef7eb2e8f9f7 1401 * @brief Stop ADC conversion of regular group (and injected group in
<> 144:ef7eb2e8f9f7 1402 * case of auto_injection mode), disable ADC DMA transfer, disable
<> 144:ef7eb2e8f9f7 1403 * ADC peripheral.
<> 144:ef7eb2e8f9f7 1404 * @note: ADC peripheral disable is forcing stop of potential
<> 144:ef7eb2e8f9f7 1405 * conversion on injected group. If injected group is under use, it
<> 144:ef7eb2e8f9f7 1406 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
<> 144:ef7eb2e8f9f7 1407 * @note For devices with several ADCs: This function is for single-ADC mode
<> 144:ef7eb2e8f9f7 1408 * only. For multimode, use the dedicated MultimodeStop function.
<> 144:ef7eb2e8f9f7 1409 * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
<> 144:ef7eb2e8f9f7 1410 * on devices) have DMA capability.
<> 144:ef7eb2e8f9f7 1411 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1412 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1413 */
<> 144:ef7eb2e8f9f7 1414 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1415 {
<> 144:ef7eb2e8f9f7 1416 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1417
<> 144:ef7eb2e8f9f7 1418 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1419 assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /* Process locked */
<> 144:ef7eb2e8f9f7 1422 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1423
<> 144:ef7eb2e8f9f7 1424 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 1425 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 1426 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 1427
<> 144:ef7eb2e8f9f7 1428 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 1429 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1430 {
<> 144:ef7eb2e8f9f7 1431 /* Disable ADC DMA mode */
<> 144:ef7eb2e8f9f7 1432 CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
<> 144:ef7eb2e8f9f7 1433
<> 144:ef7eb2e8f9f7 1434 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
<> 144:ef7eb2e8f9f7 1435 /* DMA transfer is on going) */
<> 144:ef7eb2e8f9f7 1436 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
<> 144:ef7eb2e8f9f7 1437
<> 144:ef7eb2e8f9f7 1438 /* Check if DMA channel effectively disabled */
<> 144:ef7eb2e8f9f7 1439 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 1440 {
<> 144:ef7eb2e8f9f7 1441 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1442 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 1443 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 1444 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1445 }
<> 144:ef7eb2e8f9f7 1446 else
<> 144:ef7eb2e8f9f7 1447 {
<> 144:ef7eb2e8f9f7 1448 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1449 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 1450 }
<> 144:ef7eb2e8f9f7 1451 }
<> 144:ef7eb2e8f9f7 1452
<> 144:ef7eb2e8f9f7 1453 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1454 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1455
<> 144:ef7eb2e8f9f7 1456 /* Return function status */
<> 144:ef7eb2e8f9f7 1457 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1458 }
<> 144:ef7eb2e8f9f7 1459
<> 144:ef7eb2e8f9f7 1460 /**
<> 144:ef7eb2e8f9f7 1461 * @brief Get ADC regular group conversion result.
<> 144:ef7eb2e8f9f7 1462 * @note Reading register DR automatically clears ADC flag EOC
<> 144:ef7eb2e8f9f7 1463 * (ADC group regular end of unitary conversion).
<> 144:ef7eb2e8f9f7 1464 * @note This function does not clear ADC flag EOS
<> 144:ef7eb2e8f9f7 1465 * (ADC group regular end of sequence conversion).
<> 144:ef7eb2e8f9f7 1466 * Occurrence of flag EOS rising:
<> 144:ef7eb2e8f9f7 1467 * - If sequencer is composed of 1 rank, flag EOS is equivalent
<> 144:ef7eb2e8f9f7 1468 * to flag EOC.
<> 144:ef7eb2e8f9f7 1469 * - If sequencer is composed of several ranks, during the scan
<> 144:ef7eb2e8f9f7 1470 * sequence flag EOC only is raised, at the end of the scan sequence
<> 144:ef7eb2e8f9f7 1471 * both flags EOC and EOS are raised.
<> 144:ef7eb2e8f9f7 1472 * To clear this flag, either use function:
<> 144:ef7eb2e8f9f7 1473 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
<> 144:ef7eb2e8f9f7 1474 * model polling: @ref HAL_ADC_PollForConversion()
<> 144:ef7eb2e8f9f7 1475 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
<> 144:ef7eb2e8f9f7 1476 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1477 * @retval ADC group regular conversion data
<> 144:ef7eb2e8f9f7 1478 */
<> 144:ef7eb2e8f9f7 1479 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1480 {
<> 144:ef7eb2e8f9f7 1481 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1482 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1483
<> 144:ef7eb2e8f9f7 1484 /* Note: EOC flag is not cleared here by software because automatically */
<> 144:ef7eb2e8f9f7 1485 /* cleared by hardware when reading register DR. */
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 /* Return ADC converted value */
<> 144:ef7eb2e8f9f7 1488 return hadc->Instance->DR;
<> 144:ef7eb2e8f9f7 1489 }
<> 144:ef7eb2e8f9f7 1490
<> 144:ef7eb2e8f9f7 1491 /**
<> 144:ef7eb2e8f9f7 1492 * @brief Handles ADC interrupt request
<> 144:ef7eb2e8f9f7 1493 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1494 * @retval None
<> 144:ef7eb2e8f9f7 1495 */
<> 144:ef7eb2e8f9f7 1496 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1497 {
<> 144:ef7eb2e8f9f7 1498 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1499 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1500 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 144:ef7eb2e8f9f7 1501 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
<> 144:ef7eb2e8f9f7 1502
<> 144:ef7eb2e8f9f7 1503
<> 144:ef7eb2e8f9f7 1504 /* ========== Check End of Conversion flag for regular group ========== */
<> 144:ef7eb2e8f9f7 1505 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
<> 144:ef7eb2e8f9f7 1506 {
<> 144:ef7eb2e8f9f7 1507 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
<> 144:ef7eb2e8f9f7 1508 {
<> 144:ef7eb2e8f9f7 1509 /* Update state machine on conversion status if not in error state */
<> 144:ef7eb2e8f9f7 1510 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<> 144:ef7eb2e8f9f7 1511 {
<> 144:ef7eb2e8f9f7 1512 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1513 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 1514 }
<> 144:ef7eb2e8f9f7 1515
<> 144:ef7eb2e8f9f7 1516 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 1517 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 1518 /* Note: On STM32F1 devices, in case of sequencer enabled */
<> 144:ef7eb2e8f9f7 1519 /* (several ranks selected), end of conversion flag is raised */
<> 144:ef7eb2e8f9f7 1520 /* at the end of the sequence. */
<> 144:ef7eb2e8f9f7 1521 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 1522 (hadc->Init.ContinuousConvMode == DISABLE) )
<> 144:ef7eb2e8f9f7 1523 {
<> 144:ef7eb2e8f9f7 1524 /* Disable ADC end of conversion interrupt on group regular */
<> 144:ef7eb2e8f9f7 1525 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
<> 144:ef7eb2e8f9f7 1526
<> 144:ef7eb2e8f9f7 1527 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1528 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 1531 {
<> 144:ef7eb2e8f9f7 1532 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1533 }
<> 144:ef7eb2e8f9f7 1534 }
<> 144:ef7eb2e8f9f7 1535
<> 144:ef7eb2e8f9f7 1536 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 1537 HAL_ADC_ConvCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 1538
<> 144:ef7eb2e8f9f7 1539 /* Clear regular group conversion flag */
<> 144:ef7eb2e8f9f7 1540 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
<> 144:ef7eb2e8f9f7 1541 }
<> 144:ef7eb2e8f9f7 1542 }
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 /* ========== Check End of Conversion flag for injected group ========== */
<> 144:ef7eb2e8f9f7 1545 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
<> 144:ef7eb2e8f9f7 1546 {
<> 144:ef7eb2e8f9f7 1547 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
<> 144:ef7eb2e8f9f7 1548 {
<> 144:ef7eb2e8f9f7 1549 /* Update state machine on conversion status if not in error state */
<> 144:ef7eb2e8f9f7 1550 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<> 144:ef7eb2e8f9f7 1551 {
<> 144:ef7eb2e8f9f7 1552 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1553 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
<> 144:ef7eb2e8f9f7 1554 }
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 /* Determine whether any further conversion upcoming on group injected */
<> 144:ef7eb2e8f9f7 1557 /* by external trigger, scan sequence on going or by automatic injected */
<> 144:ef7eb2e8f9f7 1558 /* conversion from group regular (same conditions as group regular */
<> 144:ef7eb2e8f9f7 1559 /* interruption disabling above). */
<> 144:ef7eb2e8f9f7 1560 /* Note: On STM32F1 devices, in case of sequencer enabled */
<> 144:ef7eb2e8f9f7 1561 /* (several ranks selected), end of conversion flag is raised */
<> 144:ef7eb2e8f9f7 1562 /* at the end of the sequence. */
<> 144:ef7eb2e8f9f7 1563 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
<> 144:ef7eb2e8f9f7 1564 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
<> 144:ef7eb2e8f9f7 1565 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 1566 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
<> 144:ef7eb2e8f9f7 1567 {
<> 144:ef7eb2e8f9f7 1568 /* Disable ADC end of conversion interrupt on group injected */
<> 144:ef7eb2e8f9f7 1569 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
<> 144:ef7eb2e8f9f7 1570
<> 144:ef7eb2e8f9f7 1571 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1572 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 1573
<> 144:ef7eb2e8f9f7 1574 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 1575 {
<> 144:ef7eb2e8f9f7 1576 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 1577 }
<> 144:ef7eb2e8f9f7 1578 }
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 1581 HAL_ADCEx_InjectedConvCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 1582
<> 144:ef7eb2e8f9f7 1583 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 1584 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
<> 144:ef7eb2e8f9f7 1585 }
<> 144:ef7eb2e8f9f7 1586 }
<> 144:ef7eb2e8f9f7 1587
<> 144:ef7eb2e8f9f7 1588 /* ========== Check Analog watchdog flags ========== */
<> 144:ef7eb2e8f9f7 1589 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
<> 144:ef7eb2e8f9f7 1590 {
<> 144:ef7eb2e8f9f7 1591 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
<> 144:ef7eb2e8f9f7 1592 {
<> 144:ef7eb2e8f9f7 1593 /* Set ADC state */
<> 144:ef7eb2e8f9f7 1594 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<> 144:ef7eb2e8f9f7 1595
<> 144:ef7eb2e8f9f7 1596 /* Level out of window callback */
<> 144:ef7eb2e8f9f7 1597 HAL_ADC_LevelOutOfWindowCallback(hadc);
<> 144:ef7eb2e8f9f7 1598
<> 144:ef7eb2e8f9f7 1599 /* Clear the ADC analog watchdog flag */
<> 144:ef7eb2e8f9f7 1600 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
<> 144:ef7eb2e8f9f7 1601 }
<> 144:ef7eb2e8f9f7 1602 }
<> 144:ef7eb2e8f9f7 1603
<> 144:ef7eb2e8f9f7 1604 }
<> 144:ef7eb2e8f9f7 1605
<> 144:ef7eb2e8f9f7 1606 /**
<> 144:ef7eb2e8f9f7 1607 * @brief Conversion complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 1608 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1609 * @retval None
<> 144:ef7eb2e8f9f7 1610 */
<> 144:ef7eb2e8f9f7 1611 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1612 {
<> 144:ef7eb2e8f9f7 1613 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1614 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1615 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1616 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1617 */
<> 144:ef7eb2e8f9f7 1618 }
<> 144:ef7eb2e8f9f7 1619
<> 144:ef7eb2e8f9f7 1620 /**
<> 144:ef7eb2e8f9f7 1621 * @brief Conversion DMA half-transfer callback in non blocking mode
<> 144:ef7eb2e8f9f7 1622 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1623 * @retval None
<> 144:ef7eb2e8f9f7 1624 */
<> 144:ef7eb2e8f9f7 1625 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1626 {
<> 144:ef7eb2e8f9f7 1627 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1628 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1629 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1630 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1631 */
<> 144:ef7eb2e8f9f7 1632 }
<> 144:ef7eb2e8f9f7 1633
<> 144:ef7eb2e8f9f7 1634 /**
<> 144:ef7eb2e8f9f7 1635 * @brief Analog watchdog callback in non blocking mode.
<> 144:ef7eb2e8f9f7 1636 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1637 * @retval None
<> 144:ef7eb2e8f9f7 1638 */
<> 144:ef7eb2e8f9f7 1639 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1640 {
<> 144:ef7eb2e8f9f7 1641 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1642 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1643 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1644 function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1645 */
<> 144:ef7eb2e8f9f7 1646 }
<> 144:ef7eb2e8f9f7 1647
<> 144:ef7eb2e8f9f7 1648 /**
<> 144:ef7eb2e8f9f7 1649 * @brief ADC error callback in non blocking mode
<> 144:ef7eb2e8f9f7 1650 * (ADC conversion with interruption or transfer by DMA)
<> 144:ef7eb2e8f9f7 1651 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1652 * @retval None
<> 144:ef7eb2e8f9f7 1653 */
<> 144:ef7eb2e8f9f7 1654 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
<> 144:ef7eb2e8f9f7 1655 {
<> 144:ef7eb2e8f9f7 1656 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1657 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 1658 /* NOTE : This function should not be modified. When the callback is needed,
<> 144:ef7eb2e8f9f7 1659 function HAL_ADC_ErrorCallback must be implemented in the user file.
<> 144:ef7eb2e8f9f7 1660 */
<> 144:ef7eb2e8f9f7 1661 }
<> 144:ef7eb2e8f9f7 1662
<> 144:ef7eb2e8f9f7 1663
<> 144:ef7eb2e8f9f7 1664 /**
<> 144:ef7eb2e8f9f7 1665 * @}
<> 144:ef7eb2e8f9f7 1666 */
<> 144:ef7eb2e8f9f7 1667
<> 144:ef7eb2e8f9f7 1668 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1669 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1670 *
<> 144:ef7eb2e8f9f7 1671 @verbatim
<> 144:ef7eb2e8f9f7 1672 ===============================================================================
<> 144:ef7eb2e8f9f7 1673 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1674 ===============================================================================
<> 144:ef7eb2e8f9f7 1675 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1676 (+) Configure channels on regular group
<> 144:ef7eb2e8f9f7 1677 (+) Configure the analog watchdog
<> 144:ef7eb2e8f9f7 1678
<> 144:ef7eb2e8f9f7 1679 @endverbatim
<> 144:ef7eb2e8f9f7 1680 * @{
<> 144:ef7eb2e8f9f7 1681 */
<> 144:ef7eb2e8f9f7 1682
<> 144:ef7eb2e8f9f7 1683 /**
<> 144:ef7eb2e8f9f7 1684 * @brief Configures the the selected channel to be linked to the regular
<> 144:ef7eb2e8f9f7 1685 * group.
<> 144:ef7eb2e8f9f7 1686 * @note In case of usage of internal measurement channels:
<> 144:ef7eb2e8f9f7 1687 * Vbat/VrefInt/TempSensor.
<> 144:ef7eb2e8f9f7 1688 * These internal paths can be be disabled using function
<> 144:ef7eb2e8f9f7 1689 * HAL_ADC_DeInit().
<> 144:ef7eb2e8f9f7 1690 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 1691 * This function initializes channel into regular group, following
<> 144:ef7eb2e8f9f7 1692 * calls to this function can be used to reconfigure some parameters
<> 144:ef7eb2e8f9f7 1693 * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
<> 144:ef7eb2e8f9f7 1694 * the ADC.
<> 144:ef7eb2e8f9f7 1695 * The setting of these parameters is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 1696 * For parameters constraints, see comments of structure
<> 144:ef7eb2e8f9f7 1697 * "ADC_ChannelConfTypeDef".
<> 144:ef7eb2e8f9f7 1698 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1699 * @param sConfig: Structure of ADC channel for regular group.
<> 144:ef7eb2e8f9f7 1700 * @retval HAL status
<> 144:ef7eb2e8f9f7 1701 */
<> 144:ef7eb2e8f9f7 1702 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 1703 {
<> 144:ef7eb2e8f9f7 1704 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 1705 __IO uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 1706
<> 144:ef7eb2e8f9f7 1707 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1708 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1709 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
<> 144:ef7eb2e8f9f7 1710 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
<> 144:ef7eb2e8f9f7 1711 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
<> 144:ef7eb2e8f9f7 1712
<> 144:ef7eb2e8f9f7 1713 /* Process locked */
<> 144:ef7eb2e8f9f7 1714 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1715
<> 144:ef7eb2e8f9f7 1716
<> 144:ef7eb2e8f9f7 1717 /* Regular sequence configuration */
<> 144:ef7eb2e8f9f7 1718 /* For Rank 1 to 6 */
<> 144:ef7eb2e8f9f7 1719 if (sConfig->Rank < 7)
<> 144:ef7eb2e8f9f7 1720 {
<> 144:ef7eb2e8f9f7 1721 MODIFY_REG(hadc->Instance->SQR3 ,
<> 144:ef7eb2e8f9f7 1722 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
<> 144:ef7eb2e8f9f7 1723 ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
<> 144:ef7eb2e8f9f7 1724 }
<> 144:ef7eb2e8f9f7 1725 /* For Rank 7 to 12 */
<> 144:ef7eb2e8f9f7 1726 else if (sConfig->Rank < 13)
<> 144:ef7eb2e8f9f7 1727 {
<> 144:ef7eb2e8f9f7 1728 MODIFY_REG(hadc->Instance->SQR2 ,
<> 144:ef7eb2e8f9f7 1729 ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
<> 144:ef7eb2e8f9f7 1730 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
<> 144:ef7eb2e8f9f7 1731 }
<> 144:ef7eb2e8f9f7 1732 /* For Rank 13 to 16 */
<> 144:ef7eb2e8f9f7 1733 else
<> 144:ef7eb2e8f9f7 1734 {
<> 144:ef7eb2e8f9f7 1735 MODIFY_REG(hadc->Instance->SQR1 ,
<> 144:ef7eb2e8f9f7 1736 ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) ,
<> 144:ef7eb2e8f9f7 1737 ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
<> 144:ef7eb2e8f9f7 1738 }
<> 144:ef7eb2e8f9f7 1739
<> 144:ef7eb2e8f9f7 1740
<> 144:ef7eb2e8f9f7 1741 /* Channel sampling time configuration */
<> 144:ef7eb2e8f9f7 1742 /* For channels 10 to 17 */
<> 144:ef7eb2e8f9f7 1743 if (sConfig->Channel >= ADC_CHANNEL_10)
<> 144:ef7eb2e8f9f7 1744 {
<> 144:ef7eb2e8f9f7 1745 MODIFY_REG(hadc->Instance->SMPR1 ,
<> 144:ef7eb2e8f9f7 1746 ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
<> 144:ef7eb2e8f9f7 1747 ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
<> 144:ef7eb2e8f9f7 1748 }
<> 144:ef7eb2e8f9f7 1749 else /* For channels 0 to 9 */
<> 144:ef7eb2e8f9f7 1750 {
<> 144:ef7eb2e8f9f7 1751 MODIFY_REG(hadc->Instance->SMPR2 ,
<> 144:ef7eb2e8f9f7 1752 ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) ,
<> 144:ef7eb2e8f9f7 1753 ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
<> 144:ef7eb2e8f9f7 1754 }
<> 144:ef7eb2e8f9f7 1755
<> 144:ef7eb2e8f9f7 1756 /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
<> 144:ef7eb2e8f9f7 1757 /* and VREFINT measurement path. */
<> 144:ef7eb2e8f9f7 1758 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
<> 144:ef7eb2e8f9f7 1759 (sConfig->Channel == ADC_CHANNEL_VREFINT) )
<> 144:ef7eb2e8f9f7 1760 {
<> 144:ef7eb2e8f9f7 1761 /* For STM32F1 devices with several ADC: Only ADC1 can access internal */
<> 144:ef7eb2e8f9f7 1762 /* measurement channels (VrefInt/TempSensor). If these channels are */
<> 144:ef7eb2e8f9f7 1763 /* intended to be set on other ADC instances, an error is reported. */
<> 144:ef7eb2e8f9f7 1764 if (hadc->Instance == ADC1)
<> 144:ef7eb2e8f9f7 1765 {
<> 144:ef7eb2e8f9f7 1766 if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
<> 144:ef7eb2e8f9f7 1767 {
<> 144:ef7eb2e8f9f7 1768 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
<> 144:ef7eb2e8f9f7 1769
<> 144:ef7eb2e8f9f7 1770 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
<> 144:ef7eb2e8f9f7 1771 {
<> 144:ef7eb2e8f9f7 1772 /* Delay for temperature sensor stabilization time */
<> 144:ef7eb2e8f9f7 1773 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 1774 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 1775 while(wait_loop_index != 0)
<> 144:ef7eb2e8f9f7 1776 {
<> 144:ef7eb2e8f9f7 1777 wait_loop_index--;
<> 144:ef7eb2e8f9f7 1778 }
<> 144:ef7eb2e8f9f7 1779 }
<> 144:ef7eb2e8f9f7 1780 }
<> 144:ef7eb2e8f9f7 1781 }
<> 144:ef7eb2e8f9f7 1782 else
<> 144:ef7eb2e8f9f7 1783 {
<> 144:ef7eb2e8f9f7 1784 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1785 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 1786
<> 144:ef7eb2e8f9f7 1787 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1788 }
<> 144:ef7eb2e8f9f7 1789 }
<> 144:ef7eb2e8f9f7 1790
<> 144:ef7eb2e8f9f7 1791 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1792 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1793
<> 144:ef7eb2e8f9f7 1794 /* Return function status */
<> 144:ef7eb2e8f9f7 1795 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 1796 }
<> 144:ef7eb2e8f9f7 1797
<> 144:ef7eb2e8f9f7 1798 /**
<> 144:ef7eb2e8f9f7 1799 * @brief Configures the analog watchdog.
<> 144:ef7eb2e8f9f7 1800 * @note Analog watchdog thresholds can be modified while ADC conversion
<> 144:ef7eb2e8f9f7 1801 * is on going.
<> 144:ef7eb2e8f9f7 1802 * In this case, some constraints must be taken into account:
<> 144:ef7eb2e8f9f7 1803 * the programmed threshold values are effective from the next
<> 144:ef7eb2e8f9f7 1804 * ADC EOC (end of unitary conversion).
<> 144:ef7eb2e8f9f7 1805 * Considering that registers write delay may happen due to
<> 144:ef7eb2e8f9f7 1806 * bus activity, this might cause an uncertainty on the
<> 144:ef7eb2e8f9f7 1807 * effective timing of the new programmed threshold values.
<> 144:ef7eb2e8f9f7 1808 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1809 * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
<> 144:ef7eb2e8f9f7 1810 * @retval HAL status
<> 144:ef7eb2e8f9f7 1811 */
<> 144:ef7eb2e8f9f7 1812 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
<> 144:ef7eb2e8f9f7 1813 {
<> 144:ef7eb2e8f9f7 1814 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1815 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 1816 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
<> 144:ef7eb2e8f9f7 1817 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
<> 144:ef7eb2e8f9f7 1818 assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
<> 144:ef7eb2e8f9f7 1819 assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
<> 144:ef7eb2e8f9f7 1820
<> 144:ef7eb2e8f9f7 1821 if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
<> 144:ef7eb2e8f9f7 1822 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
<> 144:ef7eb2e8f9f7 1823 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
<> 144:ef7eb2e8f9f7 1824 {
<> 144:ef7eb2e8f9f7 1825 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
<> 144:ef7eb2e8f9f7 1826 }
<> 144:ef7eb2e8f9f7 1827
<> 144:ef7eb2e8f9f7 1828 /* Process locked */
<> 144:ef7eb2e8f9f7 1829 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 1830
<> 144:ef7eb2e8f9f7 1831 /* Analog watchdog configuration */
<> 144:ef7eb2e8f9f7 1832
<> 144:ef7eb2e8f9f7 1833 /* Configure ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 1834 if(AnalogWDGConfig->ITMode == ENABLE)
<> 144:ef7eb2e8f9f7 1835 {
<> 144:ef7eb2e8f9f7 1836 /* Enable the ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 1837 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
<> 144:ef7eb2e8f9f7 1838 }
<> 144:ef7eb2e8f9f7 1839 else
<> 144:ef7eb2e8f9f7 1840 {
<> 144:ef7eb2e8f9f7 1841 /* Disable the ADC Analog watchdog interrupt */
<> 144:ef7eb2e8f9f7 1842 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
<> 144:ef7eb2e8f9f7 1843 }
<> 144:ef7eb2e8f9f7 1844
<> 144:ef7eb2e8f9f7 1845 /* Configuration of analog watchdog: */
<> 144:ef7eb2e8f9f7 1846 /* - Set the analog watchdog enable mode: regular and/or injected groups, */
<> 144:ef7eb2e8f9f7 1847 /* one or all channels. */
<> 144:ef7eb2e8f9f7 1848 /* - Set the Analog watchdog channel (is not used if watchdog */
<> 144:ef7eb2e8f9f7 1849 /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
<> 144:ef7eb2e8f9f7 1850 MODIFY_REG(hadc->Instance->CR1 ,
<> 144:ef7eb2e8f9f7 1851 ADC_CR1_AWDSGL |
<> 144:ef7eb2e8f9f7 1852 ADC_CR1_JAWDEN |
<> 144:ef7eb2e8f9f7 1853 ADC_CR1_AWDEN |
<> 144:ef7eb2e8f9f7 1854 ADC_CR1_AWDCH ,
<> 144:ef7eb2e8f9f7 1855 AnalogWDGConfig->WatchdogMode |
<> 144:ef7eb2e8f9f7 1856 AnalogWDGConfig->Channel );
<> 144:ef7eb2e8f9f7 1857
<> 144:ef7eb2e8f9f7 1858 /* Set the high threshold */
<> 144:ef7eb2e8f9f7 1859 WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 /* Set the low threshold */
<> 144:ef7eb2e8f9f7 1862 WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
<> 144:ef7eb2e8f9f7 1863
<> 144:ef7eb2e8f9f7 1864 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1865 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1866
<> 144:ef7eb2e8f9f7 1867 /* Return function status */
<> 144:ef7eb2e8f9f7 1868 return HAL_OK;
<> 144:ef7eb2e8f9f7 1869 }
<> 144:ef7eb2e8f9f7 1870
<> 144:ef7eb2e8f9f7 1871
<> 144:ef7eb2e8f9f7 1872 /**
<> 144:ef7eb2e8f9f7 1873 * @}
<> 144:ef7eb2e8f9f7 1874 */
<> 144:ef7eb2e8f9f7 1875
<> 144:ef7eb2e8f9f7 1876
<> 144:ef7eb2e8f9f7 1877 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
<> 144:ef7eb2e8f9f7 1878 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1879 *
<> 144:ef7eb2e8f9f7 1880 @verbatim
<> 144:ef7eb2e8f9f7 1881 ===============================================================================
<> 144:ef7eb2e8f9f7 1882 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1883 ===============================================================================
<> 144:ef7eb2e8f9f7 1884 [..]
<> 144:ef7eb2e8f9f7 1885 This subsection provides functions to get in run-time the status of the
<> 144:ef7eb2e8f9f7 1886 peripheral.
<> 144:ef7eb2e8f9f7 1887 (+) Check the ADC state
<> 144:ef7eb2e8f9f7 1888 (+) Check the ADC error code
<> 144:ef7eb2e8f9f7 1889
<> 144:ef7eb2e8f9f7 1890 @endverbatim
<> 144:ef7eb2e8f9f7 1891 * @{
<> 144:ef7eb2e8f9f7 1892 */
<> 144:ef7eb2e8f9f7 1893
<> 144:ef7eb2e8f9f7 1894 /**
<> 144:ef7eb2e8f9f7 1895 * @brief return the ADC state
<> 144:ef7eb2e8f9f7 1896 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1897 * @retval HAL state
<> 144:ef7eb2e8f9f7 1898 */
<> 144:ef7eb2e8f9f7 1899 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1900 {
<> 144:ef7eb2e8f9f7 1901 /* Return ADC state */
<> 144:ef7eb2e8f9f7 1902 return hadc->State;
<> 144:ef7eb2e8f9f7 1903 }
<> 144:ef7eb2e8f9f7 1904
<> 144:ef7eb2e8f9f7 1905 /**
<> 144:ef7eb2e8f9f7 1906 * @brief Return the ADC error code
<> 144:ef7eb2e8f9f7 1907 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1908 * @retval ADC Error Code
<> 144:ef7eb2e8f9f7 1909 */
<> 144:ef7eb2e8f9f7 1910 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
<> 144:ef7eb2e8f9f7 1911 {
<> 144:ef7eb2e8f9f7 1912 return hadc->ErrorCode;
<> 144:ef7eb2e8f9f7 1913 }
<> 144:ef7eb2e8f9f7 1914
<> 144:ef7eb2e8f9f7 1915 /**
<> 144:ef7eb2e8f9f7 1916 * @}
<> 144:ef7eb2e8f9f7 1917 */
<> 144:ef7eb2e8f9f7 1918
<> 144:ef7eb2e8f9f7 1919 /**
<> 144:ef7eb2e8f9f7 1920 * @}
<> 144:ef7eb2e8f9f7 1921 */
<> 144:ef7eb2e8f9f7 1922
<> 144:ef7eb2e8f9f7 1923 /** @defgroup ADC_Private_Functions ADC Private Functions
<> 144:ef7eb2e8f9f7 1924 * @{
<> 144:ef7eb2e8f9f7 1925 */
<> 144:ef7eb2e8f9f7 1926
<> 144:ef7eb2e8f9f7 1927 /**
<> 144:ef7eb2e8f9f7 1928 * @brief Enable the selected ADC.
<> 144:ef7eb2e8f9f7 1929 * @note Prerequisite condition to use this function: ADC must be disabled
<> 144:ef7eb2e8f9f7 1930 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
<> 144:ef7eb2e8f9f7 1931 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1932 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1933 */
<> 144:ef7eb2e8f9f7 1934 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1935 {
<> 144:ef7eb2e8f9f7 1936 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1937 __IO uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 1938
<> 144:ef7eb2e8f9f7 1939 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
<> 144:ef7eb2e8f9f7 1940 /* enabling phase not yet completed: flag ADC ready not yet set). */
<> 144:ef7eb2e8f9f7 1941 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
<> 144:ef7eb2e8f9f7 1942 /* causes: ADC clock not running, ...). */
<> 144:ef7eb2e8f9f7 1943 if (ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1944 {
<> 144:ef7eb2e8f9f7 1945 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1946 __HAL_ADC_ENABLE(hadc);
<> 144:ef7eb2e8f9f7 1947
<> 144:ef7eb2e8f9f7 1948 /* Delay for ADC stabilization time */
<> 144:ef7eb2e8f9f7 1949 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 1950 wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 1951 while(wait_loop_index != 0)
<> 144:ef7eb2e8f9f7 1952 {
<> 144:ef7eb2e8f9f7 1953 wait_loop_index--;
<> 144:ef7eb2e8f9f7 1954 }
<> 144:ef7eb2e8f9f7 1955
<> 144:ef7eb2e8f9f7 1956 /* Get tick count */
<> 144:ef7eb2e8f9f7 1957 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1958
<> 144:ef7eb2e8f9f7 1959 /* Wait for ADC effectively enabled */
<> 144:ef7eb2e8f9f7 1960 while(ADC_IS_ENABLE(hadc) == RESET)
<> 144:ef7eb2e8f9f7 1961 {
<> 144:ef7eb2e8f9f7 1962 if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
<> 144:ef7eb2e8f9f7 1963 {
<> 144:ef7eb2e8f9f7 1964 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 1965 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1966
<> 144:ef7eb2e8f9f7 1967 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 1968 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 1969
<> 144:ef7eb2e8f9f7 1970 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1971 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 1972
<> 144:ef7eb2e8f9f7 1973 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1974 }
<> 144:ef7eb2e8f9f7 1975 }
<> 144:ef7eb2e8f9f7 1976 }
<> 144:ef7eb2e8f9f7 1977
<> 144:ef7eb2e8f9f7 1978 /* Return HAL status */
<> 144:ef7eb2e8f9f7 1979 return HAL_OK;
<> 144:ef7eb2e8f9f7 1980 }
<> 144:ef7eb2e8f9f7 1981
<> 144:ef7eb2e8f9f7 1982 /**
<> 144:ef7eb2e8f9f7 1983 * @brief Stop ADC conversion and disable the selected ADC
<> 144:ef7eb2e8f9f7 1984 * @note Prerequisite condition to use this function: ADC conversions must be
<> 144:ef7eb2e8f9f7 1985 * stopped to disable the ADC.
<> 144:ef7eb2e8f9f7 1986 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 1987 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1988 */
<> 144:ef7eb2e8f9f7 1989 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 1990 {
<> 144:ef7eb2e8f9f7 1991 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1992
<> 144:ef7eb2e8f9f7 1993 /* Verification if ADC is not already disabled */
<> 144:ef7eb2e8f9f7 1994 if (ADC_IS_ENABLE(hadc) != RESET)
<> 144:ef7eb2e8f9f7 1995 {
<> 144:ef7eb2e8f9f7 1996 /* Disable the ADC peripheral */
<> 144:ef7eb2e8f9f7 1997 __HAL_ADC_DISABLE(hadc);
<> 144:ef7eb2e8f9f7 1998
<> 144:ef7eb2e8f9f7 1999 /* Get tick count */
<> 144:ef7eb2e8f9f7 2000 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2001
<> 144:ef7eb2e8f9f7 2002 /* Wait for ADC effectively disabled */
<> 144:ef7eb2e8f9f7 2003 while(ADC_IS_ENABLE(hadc) != RESET)
<> 144:ef7eb2e8f9f7 2004 {
<> 144:ef7eb2e8f9f7 2005 if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
<> 144:ef7eb2e8f9f7 2006 {
<> 144:ef7eb2e8f9f7 2007 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 2008 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 2009
<> 144:ef7eb2e8f9f7 2010 /* Set ADC error code to ADC IP internal error */
<> 144:ef7eb2e8f9f7 2011 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 144:ef7eb2e8f9f7 2012
<> 144:ef7eb2e8f9f7 2013 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2014 }
<> 144:ef7eb2e8f9f7 2015 }
<> 144:ef7eb2e8f9f7 2016 }
<> 144:ef7eb2e8f9f7 2017
<> 144:ef7eb2e8f9f7 2018 /* Return HAL status */
<> 144:ef7eb2e8f9f7 2019 return HAL_OK;
<> 144:ef7eb2e8f9f7 2020 }
<> 144:ef7eb2e8f9f7 2021
<> 144:ef7eb2e8f9f7 2022 /**
<> 144:ef7eb2e8f9f7 2023 * @brief DMA transfer complete callback.
<> 144:ef7eb2e8f9f7 2024 * @param hdma: pointer to DMA handle.
<> 144:ef7eb2e8f9f7 2025 * @retval None
<> 144:ef7eb2e8f9f7 2026 */
<> 144:ef7eb2e8f9f7 2027 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2028 {
<> 144:ef7eb2e8f9f7 2029 /* Retrieve ADC handle corresponding to current DMA handle */
<> 144:ef7eb2e8f9f7 2030 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2031
<> 144:ef7eb2e8f9f7 2032 /* Update state machine on conversion status if not in error state */
<> 144:ef7eb2e8f9f7 2033 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
<> 144:ef7eb2e8f9f7 2034 {
<> 144:ef7eb2e8f9f7 2035 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 2036 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 144:ef7eb2e8f9f7 2037
<> 144:ef7eb2e8f9f7 2038 /* Determine whether any further conversion upcoming on group regular */
<> 144:ef7eb2e8f9f7 2039 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 2040 /* Note: On STM32F1 devices, in case of sequencer enabled */
<> 144:ef7eb2e8f9f7 2041 /* (several ranks selected), end of conversion flag is raised */
<> 144:ef7eb2e8f9f7 2042 /* at the end of the sequence. */
<> 144:ef7eb2e8f9f7 2043 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 2044 (hadc->Init.ContinuousConvMode == DISABLE) )
<> 144:ef7eb2e8f9f7 2045 {
<> 144:ef7eb2e8f9f7 2046 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2047 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 144:ef7eb2e8f9f7 2048
<> 144:ef7eb2e8f9f7 2049 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 144:ef7eb2e8f9f7 2050 {
<> 144:ef7eb2e8f9f7 2051 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 2052 }
<> 144:ef7eb2e8f9f7 2053 }
<> 144:ef7eb2e8f9f7 2054
<> 144:ef7eb2e8f9f7 2055 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 2056 HAL_ADC_ConvCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 2057 }
<> 144:ef7eb2e8f9f7 2058 else
<> 144:ef7eb2e8f9f7 2059 {
<> 144:ef7eb2e8f9f7 2060 /* Call DMA error callback */
<> 144:ef7eb2e8f9f7 2061 hadc->DMA_Handle->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 2062 }
<> 144:ef7eb2e8f9f7 2063 }
<> 144:ef7eb2e8f9f7 2064
<> 144:ef7eb2e8f9f7 2065 /**
<> 144:ef7eb2e8f9f7 2066 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 2067 * @param hdma: pointer to DMA handle.
<> 144:ef7eb2e8f9f7 2068 * @retval None
<> 144:ef7eb2e8f9f7 2069 */
<> 144:ef7eb2e8f9f7 2070 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2071 {
<> 144:ef7eb2e8f9f7 2072 /* Retrieve ADC handle corresponding to current DMA handle */
<> 144:ef7eb2e8f9f7 2073 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2074
<> 144:ef7eb2e8f9f7 2075 /* Half conversion callback */
<> 144:ef7eb2e8f9f7 2076 HAL_ADC_ConvHalfCpltCallback(hadc);
<> 144:ef7eb2e8f9f7 2077 }
<> 144:ef7eb2e8f9f7 2078
<> 144:ef7eb2e8f9f7 2079 /**
<> 144:ef7eb2e8f9f7 2080 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 2081 * @param hdma: pointer to DMA handle.
<> 144:ef7eb2e8f9f7 2082 * @retval None
<> 144:ef7eb2e8f9f7 2083 */
<> 144:ef7eb2e8f9f7 2084 void ADC_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2085 {
<> 144:ef7eb2e8f9f7 2086 /* Retrieve ADC handle corresponding to current DMA handle */
<> 144:ef7eb2e8f9f7 2087 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 2088
<> 144:ef7eb2e8f9f7 2089 /* Set ADC state */
<> 144:ef7eb2e8f9f7 2090 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2091
<> 144:ef7eb2e8f9f7 2092 /* Set ADC error code to DMA error */
<> 144:ef7eb2e8f9f7 2093 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2094
<> 144:ef7eb2e8f9f7 2095 /* Error callback */
<> 144:ef7eb2e8f9f7 2096 HAL_ADC_ErrorCallback(hadc);
<> 144:ef7eb2e8f9f7 2097 }
<> 144:ef7eb2e8f9f7 2098
<> 144:ef7eb2e8f9f7 2099 /**
<> 144:ef7eb2e8f9f7 2100 * @}
<> 144:ef7eb2e8f9f7 2101 */
<> 144:ef7eb2e8f9f7 2102
<> 144:ef7eb2e8f9f7 2103 #endif /* HAL_ADC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2104 /**
<> 144:ef7eb2e8f9f7 2105 * @}
<> 144:ef7eb2e8f9f7 2106 */
<> 144:ef7eb2e8f9f7 2107
<> 144:ef7eb2e8f9f7 2108 /**
<> 144:ef7eb2e8f9f7 2109 * @}
<> 144:ef7eb2e8f9f7 2110 */
<> 144:ef7eb2e8f9f7 2111
<> 144:ef7eb2e8f9f7 2112 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/