mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_tsc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.4.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file contains all the functions prototypes for the TSC firmware
<> 144:ef7eb2e8f9f7 8 * library.
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @attention
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 15 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 16 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 17 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 19 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 20 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 22 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 23 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 24 *
<> 144:ef7eb2e8f9f7 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 *
<> 144:ef7eb2e8f9f7 36 ******************************************************************************
<> 144:ef7eb2e8f9f7 37 */
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 40 #ifndef __STM32F0xx_TSC_H
<> 144:ef7eb2e8f9f7 41 #define __STM32F0xx_TSC_H
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 44 extern "C" {
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 #if defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || \
<> 144:ef7eb2e8f9f7 48 defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
<> 144:ef7eb2e8f9f7 49 defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 52 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /** @addtogroup TSC
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /** @defgroup TSC_Exported_Types TSC Exported Types
<> 144:ef7eb2e8f9f7 65 * @{
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 /**
<> 144:ef7eb2e8f9f7 68 * @brief TSC state structure definition
<> 144:ef7eb2e8f9f7 69 */
<> 144:ef7eb2e8f9f7 70 typedef enum
<> 144:ef7eb2e8f9f7 71 {
<> 144:ef7eb2e8f9f7 72 HAL_TSC_STATE_RESET = 0x00, /*!< TSC registers have their reset value */
<> 144:ef7eb2e8f9f7 73 HAL_TSC_STATE_READY = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */
<> 144:ef7eb2e8f9f7 74 HAL_TSC_STATE_BUSY = 0x02, /*!< TSC initialization or acquisition is on-going */
<> 144:ef7eb2e8f9f7 75 HAL_TSC_STATE_ERROR = 0x03 /*!< Acquisition is completed with max count error */
<> 144:ef7eb2e8f9f7 76 } HAL_TSC_StateTypeDef;
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /**
<> 144:ef7eb2e8f9f7 79 * @brief TSC group status structure definition
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81 typedef enum
<> 144:ef7eb2e8f9f7 82 {
<> 144:ef7eb2e8f9f7 83 TSC_GROUP_ONGOING = 0x00, /*!< Acquisition on group is on-going or not started */
<> 144:ef7eb2e8f9f7 84 TSC_GROUP_COMPLETED = 0x01 /*!< Acquisition on group is completed with success (no max count error) */
<> 144:ef7eb2e8f9f7 85 } TSC_GroupStatusTypeDef;
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /**
<> 144:ef7eb2e8f9f7 88 * @brief TSC init structure definition
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90 typedef struct
<> 144:ef7eb2e8f9f7 91 {
<> 144:ef7eb2e8f9f7 92 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length */
<> 144:ef7eb2e8f9f7 93 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length */
<> 144:ef7eb2e8f9f7 94 uint32_t SpreadSpectrum; /*!< Spread spectrum activation */
<> 144:ef7eb2e8f9f7 95 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation */
<> 144:ef7eb2e8f9f7 96 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler */
<> 144:ef7eb2e8f9f7 97 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler */
<> 144:ef7eb2e8f9f7 98 uint32_t MaxCountValue; /*!< Max count value */
<> 144:ef7eb2e8f9f7 99 uint32_t IODefaultMode; /*!< IO default mode */
<> 144:ef7eb2e8f9f7 100 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity */
<> 144:ef7eb2e8f9f7 101 uint32_t AcquisitionMode; /*!< Acquisition mode */
<> 144:ef7eb2e8f9f7 102 uint32_t MaxCountInterrupt; /*!< Max count interrupt activation */
<> 144:ef7eb2e8f9f7 103 uint32_t ChannelIOs; /*!< Channel IOs mask */
<> 144:ef7eb2e8f9f7 104 uint32_t ShieldIOs; /*!< Shield IOs mask */
<> 144:ef7eb2e8f9f7 105 uint32_t SamplingIOs; /*!< Sampling IOs mask */
<> 144:ef7eb2e8f9f7 106 } TSC_InitTypeDef;
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /**
<> 144:ef7eb2e8f9f7 109 * @brief TSC IOs configuration structure definition
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111 typedef struct
<> 144:ef7eb2e8f9f7 112 {
<> 144:ef7eb2e8f9f7 113 uint32_t ChannelIOs; /*!< Channel IOs mask */
<> 144:ef7eb2e8f9f7 114 uint32_t ShieldIOs; /*!< Shield IOs mask */
<> 144:ef7eb2e8f9f7 115 uint32_t SamplingIOs; /*!< Sampling IOs mask */
<> 144:ef7eb2e8f9f7 116 } TSC_IOConfigTypeDef;
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /**
<> 144:ef7eb2e8f9f7 119 * @brief TSC handle Structure definition
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121 typedef struct
<> 144:ef7eb2e8f9f7 122 {
<> 144:ef7eb2e8f9f7 123 TSC_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 124 TSC_InitTypeDef Init; /*!< Initialization parameters */
<> 144:ef7eb2e8f9f7 125 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
<> 144:ef7eb2e8f9f7 126 HAL_LockTypeDef Lock; /*!< Lock feature */
<> 144:ef7eb2e8f9f7 127 } TSC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /**
<> 144:ef7eb2e8f9f7 130 * @}
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup TSC_Exported_Constants TSC Exported Constants
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /** @defgroup TSC_CTPH_Cycles TSC Charge Transfer Pulse High
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142 #define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28))
<> 144:ef7eb2e8f9f7 143 #define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28))
<> 144:ef7eb2e8f9f7 144 #define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28))
<> 144:ef7eb2e8f9f7 145 #define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28))
<> 144:ef7eb2e8f9f7 146 #define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28))
<> 144:ef7eb2e8f9f7 147 #define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28))
<> 144:ef7eb2e8f9f7 148 #define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28))
<> 144:ef7eb2e8f9f7 149 #define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28))
<> 144:ef7eb2e8f9f7 150 #define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28))
<> 144:ef7eb2e8f9f7 151 #define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28))
<> 144:ef7eb2e8f9f7 152 #define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28))
<> 144:ef7eb2e8f9f7 153 #define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28))
<> 144:ef7eb2e8f9f7 154 #define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28))
<> 144:ef7eb2e8f9f7 155 #define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28))
<> 144:ef7eb2e8f9f7 156 #define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28))
<> 144:ef7eb2e8f9f7 157 #define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28))
<> 144:ef7eb2e8f9f7 158 #define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
<> 144:ef7eb2e8f9f7 159 ((VAL) == TSC_CTPH_2CYCLES) || \
<> 144:ef7eb2e8f9f7 160 ((VAL) == TSC_CTPH_3CYCLES) || \
<> 144:ef7eb2e8f9f7 161 ((VAL) == TSC_CTPH_4CYCLES) || \
<> 144:ef7eb2e8f9f7 162 ((VAL) == TSC_CTPH_5CYCLES) || \
<> 144:ef7eb2e8f9f7 163 ((VAL) == TSC_CTPH_6CYCLES) || \
<> 144:ef7eb2e8f9f7 164 ((VAL) == TSC_CTPH_7CYCLES) || \
<> 144:ef7eb2e8f9f7 165 ((VAL) == TSC_CTPH_8CYCLES) || \
<> 144:ef7eb2e8f9f7 166 ((VAL) == TSC_CTPH_9CYCLES) || \
<> 144:ef7eb2e8f9f7 167 ((VAL) == TSC_CTPH_10CYCLES) || \
<> 144:ef7eb2e8f9f7 168 ((VAL) == TSC_CTPH_11CYCLES) || \
<> 144:ef7eb2e8f9f7 169 ((VAL) == TSC_CTPH_12CYCLES) || \
<> 144:ef7eb2e8f9f7 170 ((VAL) == TSC_CTPH_13CYCLES) || \
<> 144:ef7eb2e8f9f7 171 ((VAL) == TSC_CTPH_14CYCLES) || \
<> 144:ef7eb2e8f9f7 172 ((VAL) == TSC_CTPH_15CYCLES) || \
<> 144:ef7eb2e8f9f7 173 ((VAL) == TSC_CTPH_16CYCLES))
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @}
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /** @defgroup TSC_CTPL_Cycles TSC Charge Transfer Pulse Low
<> 144:ef7eb2e8f9f7 179 * @{
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181 #define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24))
<> 144:ef7eb2e8f9f7 182 #define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24))
<> 144:ef7eb2e8f9f7 183 #define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24))
<> 144:ef7eb2e8f9f7 184 #define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24))
<> 144:ef7eb2e8f9f7 185 #define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24))
<> 144:ef7eb2e8f9f7 186 #define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24))
<> 144:ef7eb2e8f9f7 187 #define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24))
<> 144:ef7eb2e8f9f7 188 #define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24))
<> 144:ef7eb2e8f9f7 189 #define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24))
<> 144:ef7eb2e8f9f7 190 #define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24))
<> 144:ef7eb2e8f9f7 191 #define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24))
<> 144:ef7eb2e8f9f7 192 #define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24))
<> 144:ef7eb2e8f9f7 193 #define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24))
<> 144:ef7eb2e8f9f7 194 #define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24))
<> 144:ef7eb2e8f9f7 195 #define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24))
<> 144:ef7eb2e8f9f7 196 #define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24))
<> 144:ef7eb2e8f9f7 197 #define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
<> 144:ef7eb2e8f9f7 198 ((VAL) == TSC_CTPL_2CYCLES) || \
<> 144:ef7eb2e8f9f7 199 ((VAL) == TSC_CTPL_3CYCLES) || \
<> 144:ef7eb2e8f9f7 200 ((VAL) == TSC_CTPL_4CYCLES) || \
<> 144:ef7eb2e8f9f7 201 ((VAL) == TSC_CTPL_5CYCLES) || \
<> 144:ef7eb2e8f9f7 202 ((VAL) == TSC_CTPL_6CYCLES) || \
<> 144:ef7eb2e8f9f7 203 ((VAL) == TSC_CTPL_7CYCLES) || \
<> 144:ef7eb2e8f9f7 204 ((VAL) == TSC_CTPL_8CYCLES) || \
<> 144:ef7eb2e8f9f7 205 ((VAL) == TSC_CTPL_9CYCLES) || \
<> 144:ef7eb2e8f9f7 206 ((VAL) == TSC_CTPL_10CYCLES) || \
<> 144:ef7eb2e8f9f7 207 ((VAL) == TSC_CTPL_11CYCLES) || \
<> 144:ef7eb2e8f9f7 208 ((VAL) == TSC_CTPL_12CYCLES) || \
<> 144:ef7eb2e8f9f7 209 ((VAL) == TSC_CTPL_13CYCLES) || \
<> 144:ef7eb2e8f9f7 210 ((VAL) == TSC_CTPL_14CYCLES) || \
<> 144:ef7eb2e8f9f7 211 ((VAL) == TSC_CTPL_15CYCLES) || \
<> 144:ef7eb2e8f9f7 212 ((VAL) == TSC_CTPL_16CYCLES))
<> 144:ef7eb2e8f9f7 213 /**
<> 144:ef7eb2e8f9f7 214 * @}
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /** @defgroup TSC_SS_Prescaler_definition TSC Spread spectrum prescaler definition
<> 144:ef7eb2e8f9f7 218 * @{
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220 #define TSC_SS_PRESC_DIV1 ((uint32_t)0)
<> 144:ef7eb2e8f9f7 221 #define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)
<> 144:ef7eb2e8f9f7 222 #define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @}
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /** @defgroup TSC_PG_Prescaler_definition TSC Pulse Generator prescaler definition
<> 144:ef7eb2e8f9f7 229 * @{
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231 #define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12))
<> 144:ef7eb2e8f9f7 232 #define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12))
<> 144:ef7eb2e8f9f7 233 #define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12))
<> 144:ef7eb2e8f9f7 234 #define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12))
<> 144:ef7eb2e8f9f7 235 #define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12))
<> 144:ef7eb2e8f9f7 236 #define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12))
<> 144:ef7eb2e8f9f7 237 #define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12))
<> 144:ef7eb2e8f9f7 238 #define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))
<> 144:ef7eb2e8f9f7 239 #define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
<> 144:ef7eb2e8f9f7 240 ((VAL) == TSC_PG_PRESC_DIV2) || \
<> 144:ef7eb2e8f9f7 241 ((VAL) == TSC_PG_PRESC_DIV4) || \
<> 144:ef7eb2e8f9f7 242 ((VAL) == TSC_PG_PRESC_DIV8) || \
<> 144:ef7eb2e8f9f7 243 ((VAL) == TSC_PG_PRESC_DIV16) || \
<> 144:ef7eb2e8f9f7 244 ((VAL) == TSC_PG_PRESC_DIV32) || \
<> 144:ef7eb2e8f9f7 245 ((VAL) == TSC_PG_PRESC_DIV64) || \
<> 144:ef7eb2e8f9f7 246 ((VAL) == TSC_PG_PRESC_DIV128))
<> 144:ef7eb2e8f9f7 247 /**
<> 144:ef7eb2e8f9f7 248 * @}
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /** @defgroup TSC_MCV_definition TSC Max Count Value definition
<> 144:ef7eb2e8f9f7 252 * @{
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254 #define TSC_MCV_255 ((uint32_t)(0 << 5))
<> 144:ef7eb2e8f9f7 255 #define TSC_MCV_511 ((uint32_t)(1 << 5))
<> 144:ef7eb2e8f9f7 256 #define TSC_MCV_1023 ((uint32_t)(2 << 5))
<> 144:ef7eb2e8f9f7 257 #define TSC_MCV_2047 ((uint32_t)(3 << 5))
<> 144:ef7eb2e8f9f7 258 #define TSC_MCV_4095 ((uint32_t)(4 << 5))
<> 144:ef7eb2e8f9f7 259 #define TSC_MCV_8191 ((uint32_t)(5 << 5))
<> 144:ef7eb2e8f9f7 260 #define TSC_MCV_16383 ((uint32_t)(6 << 5))
<> 144:ef7eb2e8f9f7 261 #define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
<> 144:ef7eb2e8f9f7 262 ((VAL) == TSC_MCV_511) || \
<> 144:ef7eb2e8f9f7 263 ((VAL) == TSC_MCV_1023) || \
<> 144:ef7eb2e8f9f7 264 ((VAL) == TSC_MCV_2047) || \
<> 144:ef7eb2e8f9f7 265 ((VAL) == TSC_MCV_4095) || \
<> 144:ef7eb2e8f9f7 266 ((VAL) == TSC_MCV_8191) || \
<> 144:ef7eb2e8f9f7 267 ((VAL) == TSC_MCV_16383))
<> 144:ef7eb2e8f9f7 268 /**
<> 144:ef7eb2e8f9f7 269 * @}
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /** @defgroup TSC_IO_default_mode_definition TSC I/O default mode definition
<> 144:ef7eb2e8f9f7 273 * @{
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275 #define TSC_IODEF_OUT_PP_LOW ((uint32_t)0)
<> 144:ef7eb2e8f9f7 276 #define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)
<> 144:ef7eb2e8f9f7 277 #define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @}
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /** @defgroup TSC_Synchronization_pin_polarity TSC Synchronization pin polarity
<> 144:ef7eb2e8f9f7 283 * @{
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 #define TSC_SYNC_POLARITY_FALLING ((uint32_t)0)
<> 144:ef7eb2e8f9f7 286 #define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
<> 144:ef7eb2e8f9f7 287 #define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
<> 144:ef7eb2e8f9f7 288 /**
<> 144:ef7eb2e8f9f7 289 * @}
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /** @defgroup TSC_Acquisition_mode TSC Acquisition mode
<> 144:ef7eb2e8f9f7 293 * @{
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 #define TSC_ACQ_MODE_NORMAL ((uint32_t)0)
<> 144:ef7eb2e8f9f7 296 #define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
<> 144:ef7eb2e8f9f7 297 #define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
<> 144:ef7eb2e8f9f7 298 /**
<> 144:ef7eb2e8f9f7 299 * @}
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /** @defgroup TSC_IO_mode_definition TSC I/O mode definition
<> 144:ef7eb2e8f9f7 303 * @{
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305 #define TSC_IOMODE_UNUSED ((uint32_t)0)
<> 144:ef7eb2e8f9f7 306 #define TSC_IOMODE_CHANNEL ((uint32_t)1)
<> 144:ef7eb2e8f9f7 307 #define TSC_IOMODE_SHIELD ((uint32_t)2)
<> 144:ef7eb2e8f9f7 308 #define TSC_IOMODE_SAMPLING ((uint32_t)3)
<> 144:ef7eb2e8f9f7 309 #define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
<> 144:ef7eb2e8f9f7 310 ((VAL) == TSC_IOMODE_CHANNEL) || \
<> 144:ef7eb2e8f9f7 311 ((VAL) == TSC_IOMODE_SHIELD) || \
<> 144:ef7eb2e8f9f7 312 ((VAL) == TSC_IOMODE_SAMPLING))
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @}
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /** @defgroup TSC_interrupts_definition TSC interrupts definition
<> 144:ef7eb2e8f9f7 318 * @{
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320 #define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
<> 144:ef7eb2e8f9f7 321 #define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
<> 144:ef7eb2e8f9f7 322 #define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @}
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /** @defgroup TSC_flags_definition TSC Flags Definition
<> 144:ef7eb2e8f9f7 328 * @{
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330 #define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
<> 144:ef7eb2e8f9f7 331 #define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
<> 144:ef7eb2e8f9f7 332 /**
<> 144:ef7eb2e8f9f7 333 * @}
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /** @defgroup TSC_groups_definition TSC groups definition
<> 144:ef7eb2e8f9f7 337 * @{
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 #define TSC_NB_OF_GROUPS (8)
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 #define TSC_GROUP1 ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 342 #define TSC_GROUP2 ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 343 #define TSC_GROUP3 ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 344 #define TSC_GROUP4 ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 345 #define TSC_GROUP5 ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 346 #define TSC_GROUP6 ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 347 #define TSC_GROUP7 ((uint32_t)0x00000040)
<> 144:ef7eb2e8f9f7 348 #define TSC_GROUP8 ((uint32_t)0x00000080)
<> 144:ef7eb2e8f9f7 349 #define TSC_ALL_GROUPS ((uint32_t)0x000000FF)
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 #define TSC_GROUP1_IDX ((uint32_t)0)
<> 144:ef7eb2e8f9f7 352 #define TSC_GROUP2_IDX ((uint32_t)1)
<> 144:ef7eb2e8f9f7 353 #define TSC_GROUP3_IDX ((uint32_t)2)
<> 144:ef7eb2e8f9f7 354 #define TSC_GROUP4_IDX ((uint32_t)3)
<> 144:ef7eb2e8f9f7 355 #define TSC_GROUP5_IDX ((uint32_t)4)
<> 144:ef7eb2e8f9f7 356 #define TSC_GROUP6_IDX ((uint32_t)5)
<> 144:ef7eb2e8f9f7 357 #define TSC_GROUP7_IDX ((uint32_t)6)
<> 144:ef7eb2e8f9f7 358 #define TSC_GROUP8_IDX ((uint32_t)7)
<> 144:ef7eb2e8f9f7 359 #define IS_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 #define TSC_GROUP1_IO1 ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 362 #define TSC_GROUP1_IO2 ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 363 #define TSC_GROUP1_IO3 ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 364 #define TSC_GROUP1_IO4 ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 365 #define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F)
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 #define TSC_GROUP2_IO1 ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 368 #define TSC_GROUP2_IO2 ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 369 #define TSC_GROUP2_IO3 ((uint32_t)0x00000040)
<> 144:ef7eb2e8f9f7 370 #define TSC_GROUP2_IO4 ((uint32_t)0x00000080)
<> 144:ef7eb2e8f9f7 371 #define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0)
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 #define TSC_GROUP3_IO1 ((uint32_t)0x00000100)
<> 144:ef7eb2e8f9f7 374 #define TSC_GROUP3_IO2 ((uint32_t)0x00000200)
<> 144:ef7eb2e8f9f7 375 #define TSC_GROUP3_IO3 ((uint32_t)0x00000400)
<> 144:ef7eb2e8f9f7 376 #define TSC_GROUP3_IO4 ((uint32_t)0x00000800)
<> 144:ef7eb2e8f9f7 377 #define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00)
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 #define TSC_GROUP4_IO1 ((uint32_t)0x00001000)
<> 144:ef7eb2e8f9f7 380 #define TSC_GROUP4_IO2 ((uint32_t)0x00002000)
<> 144:ef7eb2e8f9f7 381 #define TSC_GROUP4_IO3 ((uint32_t)0x00004000)
<> 144:ef7eb2e8f9f7 382 #define TSC_GROUP4_IO4 ((uint32_t)0x00008000)
<> 144:ef7eb2e8f9f7 383 #define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000)
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 #define TSC_GROUP5_IO1 ((uint32_t)0x00010000)
<> 144:ef7eb2e8f9f7 386 #define TSC_GROUP5_IO2 ((uint32_t)0x00020000)
<> 144:ef7eb2e8f9f7 387 #define TSC_GROUP5_IO3 ((uint32_t)0x00040000)
<> 144:ef7eb2e8f9f7 388 #define TSC_GROUP5_IO4 ((uint32_t)0x00080000)
<> 144:ef7eb2e8f9f7 389 #define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000)
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 #define TSC_GROUP6_IO1 ((uint32_t)0x00100000)
<> 144:ef7eb2e8f9f7 392 #define TSC_GROUP6_IO2 ((uint32_t)0x00200000)
<> 144:ef7eb2e8f9f7 393 #define TSC_GROUP6_IO3 ((uint32_t)0x00400000)
<> 144:ef7eb2e8f9f7 394 #define TSC_GROUP6_IO4 ((uint32_t)0x00800000)
<> 144:ef7eb2e8f9f7 395 #define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000)
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 #define TSC_GROUP7_IO1 ((uint32_t)0x01000000)
<> 144:ef7eb2e8f9f7 398 #define TSC_GROUP7_IO2 ((uint32_t)0x02000000)
<> 144:ef7eb2e8f9f7 399 #define TSC_GROUP7_IO3 ((uint32_t)0x04000000)
<> 144:ef7eb2e8f9f7 400 #define TSC_GROUP7_IO4 ((uint32_t)0x08000000)
<> 144:ef7eb2e8f9f7 401 #define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000)
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 #define TSC_GROUP8_IO1 ((uint32_t)0x10000000)
<> 144:ef7eb2e8f9f7 404 #define TSC_GROUP8_IO2 ((uint32_t)0x20000000)
<> 144:ef7eb2e8f9f7 405 #define TSC_GROUP8_IO3 ((uint32_t)0x40000000)
<> 144:ef7eb2e8f9f7 406 #define TSC_GROUP8_IO4 ((uint32_t)0x80000000U)
<> 144:ef7eb2e8f9f7 407 #define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000U)
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 #define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 410 /**
<> 144:ef7eb2e8f9f7 411 * @}
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /**
<> 144:ef7eb2e8f9f7 415 * @}
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Private macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 419 /** @defgroup TSC_Private_Macros TSC Private Macros
<> 144:ef7eb2e8f9f7 420 * @{
<> 144:ef7eb2e8f9f7 421 */
<> 144:ef7eb2e8f9f7 422 /** @defgroup TSC_Spread_Spectrum TSC Spread Spectrum
<> 144:ef7eb2e8f9f7 423 * @{
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425 #define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 #define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))
<> 144:ef7eb2e8f9f7 428 /**
<> 144:ef7eb2e8f9f7 429 * @}
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /**
<> 144:ef7eb2e8f9f7 433 * @}
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 437 /** @defgroup TSC_Exported_Macros TSC Exported Macros
<> 144:ef7eb2e8f9f7 438 * @{
<> 144:ef7eb2e8f9f7 439 */
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /** @brief Reset TSC handle state
<> 144:ef7eb2e8f9f7 442 * @param __HANDLE__: TSC handle.
<> 144:ef7eb2e8f9f7 443 * @retval None
<> 144:ef7eb2e8f9f7 444 */
<> 144:ef7eb2e8f9f7 445 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /**
<> 144:ef7eb2e8f9f7 448 * @brief Enable the TSC peripheral.
<> 144:ef7eb2e8f9f7 449 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 450 * @retval None
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /**
<> 144:ef7eb2e8f9f7 455 * @brief Disable the TSC peripheral.
<> 144:ef7eb2e8f9f7 456 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 457 * @retval None
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /**
<> 144:ef7eb2e8f9f7 462 * @brief Start acquisition
<> 144:ef7eb2e8f9f7 463 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 464 * @retval None
<> 144:ef7eb2e8f9f7 465 */
<> 144:ef7eb2e8f9f7 466 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /**
<> 144:ef7eb2e8f9f7 469 * @brief Stop acquisition
<> 144:ef7eb2e8f9f7 470 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 471 * @retval None
<> 144:ef7eb2e8f9f7 472 */
<> 144:ef7eb2e8f9f7 473 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /**
<> 144:ef7eb2e8f9f7 476 * @brief Set IO default mode to output push-pull low
<> 144:ef7eb2e8f9f7 477 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 478 * @retval None
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /**
<> 144:ef7eb2e8f9f7 483 * @brief Set IO default mode to input floating
<> 144:ef7eb2e8f9f7 484 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 485 * @retval None
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /**
<> 144:ef7eb2e8f9f7 490 * @brief Set synchronization polarity to falling edge
<> 144:ef7eb2e8f9f7 491 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 492 * @retval None
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /**
<> 144:ef7eb2e8f9f7 497 * @brief Set synchronization polarity to rising edge and high level
<> 144:ef7eb2e8f9f7 498 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 499 * @retval None
<> 144:ef7eb2e8f9f7 500 */
<> 144:ef7eb2e8f9f7 501 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /**
<> 144:ef7eb2e8f9f7 504 * @brief Enable TSC interrupt.
<> 144:ef7eb2e8f9f7 505 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 506 * @param __INTERRUPT__: TSC interrupt
<> 144:ef7eb2e8f9f7 507 * @retval None
<> 144:ef7eb2e8f9f7 508 */
<> 144:ef7eb2e8f9f7 509 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /**
<> 144:ef7eb2e8f9f7 512 * @brief Disable TSC interrupt.
<> 144:ef7eb2e8f9f7 513 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 514 * @param __INTERRUPT__: TSC interrupt
<> 144:ef7eb2e8f9f7 515 * @retval None
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /** @brief Check if the specified TSC interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 520 * @param __HANDLE__: TSC Handle
<> 144:ef7eb2e8f9f7 521 * @param __INTERRUPT__: TSC interrupt
<> 144:ef7eb2e8f9f7 522 * @retval SET or RESET
<> 144:ef7eb2e8f9f7 523 */
<> 144:ef7eb2e8f9f7 524 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /**
<> 144:ef7eb2e8f9f7 527 * @brief Get the selected TSC's flag status.
<> 144:ef7eb2e8f9f7 528 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 529 * @param __FLAG__: TSC flag
<> 144:ef7eb2e8f9f7 530 * @retval SET or RESET
<> 144:ef7eb2e8f9f7 531 */
<> 144:ef7eb2e8f9f7 532 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /**
<> 144:ef7eb2e8f9f7 535 * @brief Clear the TSC's pending flag.
<> 144:ef7eb2e8f9f7 536 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 537 * @param __FLAG__: TSC flag
<> 144:ef7eb2e8f9f7 538 * @retval None
<> 144:ef7eb2e8f9f7 539 */
<> 144:ef7eb2e8f9f7 540 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /**
<> 144:ef7eb2e8f9f7 543 * @brief Enable schmitt trigger hysteresis on a group of IOs
<> 144:ef7eb2e8f9f7 544 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 545 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 546 * @retval None
<> 144:ef7eb2e8f9f7 547 */
<> 144:ef7eb2e8f9f7 548 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /**
<> 144:ef7eb2e8f9f7 551 * @brief Disable schmitt trigger hysteresis on a group of IOs
<> 144:ef7eb2e8f9f7 552 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 553 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 554 * @retval None
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /**
<> 144:ef7eb2e8f9f7 559 * @brief Open analog switch on a group of IOs
<> 144:ef7eb2e8f9f7 560 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 561 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 562 * @retval None
<> 144:ef7eb2e8f9f7 563 */
<> 144:ef7eb2e8f9f7 564 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /**
<> 144:ef7eb2e8f9f7 567 * @brief Close analog switch on a group of IOs
<> 144:ef7eb2e8f9f7 568 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 569 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 570 * @retval None
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /**
<> 144:ef7eb2e8f9f7 575 * @brief Enable a group of IOs in channel mode
<> 144:ef7eb2e8f9f7 576 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 577 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 578 * @retval None
<> 144:ef7eb2e8f9f7 579 */
<> 144:ef7eb2e8f9f7 580 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /**
<> 144:ef7eb2e8f9f7 583 * @brief Disable a group of channel IOs
<> 144:ef7eb2e8f9f7 584 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 585 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 586 * @retval None
<> 144:ef7eb2e8f9f7 587 */
<> 144:ef7eb2e8f9f7 588 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 /**
<> 144:ef7eb2e8f9f7 591 * @brief Enable a group of IOs in sampling mode
<> 144:ef7eb2e8f9f7 592 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 593 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 594 * @retval None
<> 144:ef7eb2e8f9f7 595 */
<> 144:ef7eb2e8f9f7 596 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /**
<> 144:ef7eb2e8f9f7 599 * @brief Disable a group of sampling IOs
<> 144:ef7eb2e8f9f7 600 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 601 * @param __GX_IOY_MASK__: IOs mask
<> 144:ef7eb2e8f9f7 602 * @retval None
<> 144:ef7eb2e8f9f7 603 */
<> 144:ef7eb2e8f9f7 604 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /**
<> 144:ef7eb2e8f9f7 607 * @brief Enable acquisition groups
<> 144:ef7eb2e8f9f7 608 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 609 * @param __GX_MASK__: Groups mask
<> 144:ef7eb2e8f9f7 610 * @retval None
<> 144:ef7eb2e8f9f7 611 */
<> 144:ef7eb2e8f9f7 612 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /**
<> 144:ef7eb2e8f9f7 615 * @brief Disable acquisition groups
<> 144:ef7eb2e8f9f7 616 * @param __HANDLE__: TSC handle
<> 144:ef7eb2e8f9f7 617 * @param __GX_MASK__: Groups mask
<> 144:ef7eb2e8f9f7 618 * @retval None
<> 144:ef7eb2e8f9f7 619 */
<> 144:ef7eb2e8f9f7 620 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /** @brief Gets acquisition group status
<> 144:ef7eb2e8f9f7 623 * @param __HANDLE__: TSC Handle
<> 144:ef7eb2e8f9f7 624 * @param __GX_INDEX__: Group index
<> 144:ef7eb2e8f9f7 625 * @retval SET or RESET
<> 144:ef7eb2e8f9f7 626 */
<> 144:ef7eb2e8f9f7 627 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
<> 144:ef7eb2e8f9f7 628 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /**
<> 144:ef7eb2e8f9f7 631 * @}
<> 144:ef7eb2e8f9f7 632 */
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 635 /** @addtogroup TSC_Exported_Functions TSC Exported Functions
<> 144:ef7eb2e8f9f7 636 * @{
<> 144:ef7eb2e8f9f7 637 */
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /** @addtogroup TSC_Exported_Functions_Group1 Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 640 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 641 * @{
<> 144:ef7eb2e8f9f7 642 */
<> 144:ef7eb2e8f9f7 643 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 644 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 645 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
<> 144:ef7eb2e8f9f7 646 void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 647 void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 648 /**
<> 144:ef7eb2e8f9f7 649 * @}
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /** @addtogroup TSC_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 653 * @brief IO operation functions * @{
<> 144:ef7eb2e8f9f7 654 */
<> 144:ef7eb2e8f9f7 655 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 656 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 657 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 658 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 659 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 660 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
<> 144:ef7eb2e8f9f7 661 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
<> 144:ef7eb2e8f9f7 662 /**
<> 144:ef7eb2e8f9f7 663 * @}
<> 144:ef7eb2e8f9f7 664 */
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 667 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 668 * @{
<> 144:ef7eb2e8f9f7 669 */
<> 144:ef7eb2e8f9f7 670 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 671 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
<> 144:ef7eb2e8f9f7 672 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
<> 144:ef7eb2e8f9f7 673 /**
<> 144:ef7eb2e8f9f7 674 * @}
<> 144:ef7eb2e8f9f7 675 */
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /** @addtogroup TSC_Exported_Functions_Group4 State functions
<> 144:ef7eb2e8f9f7 678 * @brief State functions
<> 144:ef7eb2e8f9f7 679 * @{
<> 144:ef7eb2e8f9f7 680 */
<> 144:ef7eb2e8f9f7 681 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 682 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 683 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 684 void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 685 /**
<> 144:ef7eb2e8f9f7 686 * @}
<> 144:ef7eb2e8f9f7 687 */
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /** @addtogroup TSC_Exported_Functions_Group5 Callback functions
<> 144:ef7eb2e8f9f7 690 * @brief Callback functions
<> 144:ef7eb2e8f9f7 691 * @{
<> 144:ef7eb2e8f9f7 692 */
<> 144:ef7eb2e8f9f7 693 /* Callback functions *********************************************************/
<> 144:ef7eb2e8f9f7 694 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 695 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 696 /**
<> 144:ef7eb2e8f9f7 697 * @}
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /**
<> 144:ef7eb2e8f9f7 701 * @}
<> 144:ef7eb2e8f9f7 702 */
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /**
<> 144:ef7eb2e8f9f7 705 * @}
<> 144:ef7eb2e8f9f7 706 */
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /**
<> 144:ef7eb2e8f9f7 709 * @}
<> 144:ef7eb2e8f9f7 710 */
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 #endif /* defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || */
<> 144:ef7eb2e8f9f7 713 /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || */
<> 144:ef7eb2e8f9f7 714 /* defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx) */
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719 #endif
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 #endif /*__STM32F0xx_TSC_H */
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 724