mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_pwr_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.4.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of PWR HAL Extension module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F0xx_HAL_PWR_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F0xx_HAL_PWR_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup PWREx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup PWREx_Exported_Types PWREx Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 64 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 65 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /**
<> 144:ef7eb2e8f9f7 68 * @brief PWR PVD configuration structure definition
<> 144:ef7eb2e8f9f7 69 */
<> 144:ef7eb2e8f9f7 70 typedef struct
<> 144:ef7eb2e8f9f7 71 {
<> 144:ef7eb2e8f9f7 72 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
<> 144:ef7eb2e8f9f7 73 This parameter can be a value of @ref PWREx_PVD_detection_level */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
<> 144:ef7eb2e8f9f7 76 This parameter can be a value of @ref PWREx_PVD_Mode */
<> 144:ef7eb2e8f9f7 77 }PWR_PVDTypeDef;
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 80 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 81 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 82 /**
<> 144:ef7eb2e8f9f7 83 * @}
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
<> 144:ef7eb2e8f9f7 88 * @{
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins
<> 144:ef7eb2e8f9f7 93 * @{
<> 144:ef7eb2e8f9f7 94 */
<> 144:ef7eb2e8f9f7 95 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 96 defined (STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 97 #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
<> 144:ef7eb2e8f9f7 98 #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
<> 144:ef7eb2e8f9f7 99 #define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3)
<> 144:ef7eb2e8f9f7 100 #define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
<> 144:ef7eb2e8f9f7 101 #define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
<> 144:ef7eb2e8f9f7 102 #define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
<> 144:ef7eb2e8f9f7 103 #define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
<> 144:ef7eb2e8f9f7 104 #define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8)
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
<> 144:ef7eb2e8f9f7 107 ((PIN) == PWR_WAKEUP_PIN2) || \
<> 144:ef7eb2e8f9f7 108 ((PIN) == PWR_WAKEUP_PIN3) || \
<> 144:ef7eb2e8f9f7 109 ((PIN) == PWR_WAKEUP_PIN4) || \
<> 144:ef7eb2e8f9f7 110 ((PIN) == PWR_WAKEUP_PIN5) || \
<> 144:ef7eb2e8f9f7 111 ((PIN) == PWR_WAKEUP_PIN6) || \
<> 144:ef7eb2e8f9f7 112 ((PIN) == PWR_WAKEUP_PIN7) || \
<> 144:ef7eb2e8f9f7 113 ((PIN) == PWR_WAKEUP_PIN8))
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 #elif defined(STM32F030xC) || defined (STM32F070xB)
<> 144:ef7eb2e8f9f7 116 #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
<> 144:ef7eb2e8f9f7 117 #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
<> 144:ef7eb2e8f9f7 118 #define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
<> 144:ef7eb2e8f9f7 119 #define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
<> 144:ef7eb2e8f9f7 120 #define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
<> 144:ef7eb2e8f9f7 121 #define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
<> 144:ef7eb2e8f9f7 124 ((PIN) == PWR_WAKEUP_PIN2) || \
<> 144:ef7eb2e8f9f7 125 ((PIN) == PWR_WAKEUP_PIN4) || \
<> 144:ef7eb2e8f9f7 126 ((PIN) == PWR_WAKEUP_PIN5) || \
<> 144:ef7eb2e8f9f7 127 ((PIN) == PWR_WAKEUP_PIN6) || \
<> 144:ef7eb2e8f9f7 128 ((PIN) == PWR_WAKEUP_PIN7))
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 #elif defined(STM32F042x6) || defined (STM32F048xx)
<> 144:ef7eb2e8f9f7 131 #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
<> 144:ef7eb2e8f9f7 132 #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
<> 144:ef7eb2e8f9f7 133 #define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
<> 144:ef7eb2e8f9f7 134 #define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
<> 144:ef7eb2e8f9f7 135 #define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
<> 144:ef7eb2e8f9f7 138 ((PIN) == PWR_WAKEUP_PIN2) || \
<> 144:ef7eb2e8f9f7 139 ((PIN) == PWR_WAKEUP_PIN4) || \
<> 144:ef7eb2e8f9f7 140 ((PIN) == PWR_WAKEUP_PIN6) || \
<> 144:ef7eb2e8f9f7 141 ((PIN) == PWR_WAKEUP_PIN7))
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 #else
<> 144:ef7eb2e8f9f7 144 #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
<> 144:ef7eb2e8f9f7 145 #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
<> 144:ef7eb2e8f9f7 149 ((PIN) == PWR_WAKEUP_PIN2))
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 #endif
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @}
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /** @defgroup PWREx_EXTI_Line PWREx EXTI Line
<> 144:ef7eb2e8f9f7 158 * @{
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 161 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 162 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 167 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 168 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #if defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 171 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 172 defined (STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 #define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 #endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
<> 144:ef7eb2e8f9f7 177 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 178 defined (STM32F091xC) || defined (STM32F098xx) ||*/
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @}
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 184 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 185 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 186 /** @defgroup PWREx_PVD_detection_level PWREx PVD detection level
<> 144:ef7eb2e8f9f7 187 * @{
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
<> 144:ef7eb2e8f9f7 190 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
<> 144:ef7eb2e8f9f7 191 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
<> 144:ef7eb2e8f9f7 192 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
<> 144:ef7eb2e8f9f7 193 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
<> 144:ef7eb2e8f9f7 194 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
<> 144:ef7eb2e8f9f7 195 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
<> 144:ef7eb2e8f9f7 196 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
<> 144:ef7eb2e8f9f7 197 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
<> 144:ef7eb2e8f9f7 198 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
<> 144:ef7eb2e8f9f7 199 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
<> 144:ef7eb2e8f9f7 200 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
<> 144:ef7eb2e8f9f7 201 /**
<> 144:ef7eb2e8f9f7 202 * @}
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /** @defgroup PWREx_PVD_Mode PWREx PVD Mode
<> 144:ef7eb2e8f9f7 206 * @{
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
<> 144:ef7eb2e8f9f7 209 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
<> 144:ef7eb2e8f9f7 210 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 211 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 212 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
<> 144:ef7eb2e8f9f7 213 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 214 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
<> 144:ef7eb2e8f9f7 217 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
<> 144:ef7eb2e8f9f7 218 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
<> 144:ef7eb2e8f9f7 219 ((MODE) == PWR_PVD_MODE_NORMAL))
<> 144:ef7eb2e8f9f7 220 /**
<> 144:ef7eb2e8f9f7 221 * @}
<> 144:ef7eb2e8f9f7 222 */
<> 144:ef7eb2e8f9f7 223 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 224 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 225 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /** @defgroup PWREx_Flag PWREx Flag
<> 144:ef7eb2e8f9f7 228 * @{
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 231 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 232 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 #define PWR_FLAG_WU PWR_CSR_WUF
<> 144:ef7eb2e8f9f7 235 #define PWR_FLAG_SB PWR_CSR_SBF
<> 144:ef7eb2e8f9f7 236 #define PWR_FLAG_PVDO PWR_CSR_PVDO
<> 144:ef7eb2e8f9f7 237 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
<> 144:ef7eb2e8f9f7 238 #elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC)
<> 144:ef7eb2e8f9f7 239 #define PWR_FLAG_WU PWR_CSR_WUF
<> 144:ef7eb2e8f9f7 240 #define PWR_FLAG_SB PWR_CSR_SBF
<> 144:ef7eb2e8f9f7 241 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
<> 144:ef7eb2e8f9f7 242 #else
<> 144:ef7eb2e8f9f7 243 #define PWR_FLAG_WU PWR_CSR_WUF
<> 144:ef7eb2e8f9f7 244 #define PWR_FLAG_SB PWR_CSR_SBF
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 247 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 248 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @}
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @}
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 258 /** @defgroup PWREx_Exported_Macros PWREx Exported Macros
<> 144:ef7eb2e8f9f7 259 * @{
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 262 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 263 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @brief Enable interrupt on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 266 * @retval None.
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /**
<> 144:ef7eb2e8f9f7 271 * @brief Disable interrupt on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 272 * @retval None.
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @brief Enable event on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 278 * @retval None.
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /**
<> 144:ef7eb2e8f9f7 283 * @brief Disable event on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 284 * @retval None.
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /**
<> 144:ef7eb2e8f9f7 289 * @brief Disable the PVD Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 290 * @retval None.
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /**
<> 144:ef7eb2e8f9f7 295 * @brief Disable the PVD Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 296 * @retval None.
<> 144:ef7eb2e8f9f7 297 */
<> 144:ef7eb2e8f9f7 298 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 302 * @retval None
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /**
<> 144:ef7eb2e8f9f7 308 * @brief PVD EXTI line configuration: set falling edge trigger.
<> 144:ef7eb2e8f9f7 309 * @retval None.
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @brief PVD EXTI line configuration: set rising edge trigger.
<> 144:ef7eb2e8f9f7 315 * @retval None.
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /**
<> 144:ef7eb2e8f9f7 320 * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 321 * @retval None
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
<> 144:ef7eb2e8f9f7 327 * @retval EXTI PVD Line Status.
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /**
<> 144:ef7eb2e8f9f7 332 * @brief Clear the PVD EXTI flag.
<> 144:ef7eb2e8f9f7 333 * @retval None.
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 339 * @retval None.
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 344 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 345 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 #if defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 349 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 350 defined (STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @brief Enable interrupt on Vddio2 Monitor Exti Line 31.
<> 144:ef7eb2e8f9f7 353 * @retval None.
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355 #define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_VDDIO2))
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /**
<> 144:ef7eb2e8f9f7 358 * @brief Disable interrupt on Vddio2 Monitor Exti Line 31.
<> 144:ef7eb2e8f9f7 359 * @retval None.
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 #define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_VDDIO2))
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /**
<> 144:ef7eb2e8f9f7 364 * @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger.
<> 144:ef7eb2e8f9f7 365 * @retval None.
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367 #define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 368 do{ \
<> 144:ef7eb2e8f9f7 369 EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \
<> 144:ef7eb2e8f9f7 370 EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2); \
<> 144:ef7eb2e8f9f7 371 } while(0)
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger.
<> 144:ef7eb2e8f9f7 375 * @retval None.
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377 #define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2)
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /**
<> 144:ef7eb2e8f9f7 380 * @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not.
<> 144:ef7eb2e8f9f7 381 * @retval EXTI VDDIO2 Monitor Line Status.
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383 #define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_VDDIO2))
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /**
<> 144:ef7eb2e8f9f7 386 * @brief Clear the VDDIO2 Monitor EXTI flag.
<> 144:ef7eb2e8f9f7 387 * @retval None.
<> 144:ef7eb2e8f9f7 388 */
<> 144:ef7eb2e8f9f7 389 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_VDDIO2))
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /**
<> 144:ef7eb2e8f9f7 392 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 393 * @retval None.
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395 #define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2))
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 #endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
<> 144:ef7eb2e8f9f7 399 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 400 defined (STM32F091xC) || defined (STM32F098xx) */
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /**
<> 144:ef7eb2e8f9f7 403 * @}
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
<> 144:ef7eb2e8f9f7 409 * @{
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /** @addtogroup PWREx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 413 * @{
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 /* I/O operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 416 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 417 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 418 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 419 void HAL_PWR_PVD_IRQHandler(void);
<> 144:ef7eb2e8f9f7 420 void HAL_PWR_PVDCallback(void);
<> 144:ef7eb2e8f9f7 421 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 422 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 423 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 #if defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 426 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 427 defined (STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 428 void HAL_PWREx_Vddio2Monitor_IRQHandler(void);
<> 144:ef7eb2e8f9f7 429 void HAL_PWREx_Vddio2MonitorCallback(void);
<> 144:ef7eb2e8f9f7 430 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 431 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 432 defined (STM32F091xC) || defined (STM32F098xx) */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /* Peripheral Control functions **********************************************/
<> 144:ef7eb2e8f9f7 435 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 436 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 437 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 438 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
<> 144:ef7eb2e8f9f7 439 void HAL_PWR_EnablePVD(void);
<> 144:ef7eb2e8f9f7 440 void HAL_PWR_DisablePVD(void);
<> 144:ef7eb2e8f9f7 441 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 442 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 443 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 #if defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 446 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 447 defined (STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 448 void HAL_PWREx_EnableVddio2Monitor(void);
<> 144:ef7eb2e8f9f7 449 void HAL_PWREx_DisableVddio2Monitor(void);
<> 144:ef7eb2e8f9f7 450 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 451 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 452 defined (STM32F091xC) || defined (STM32F098xx) */
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /**
<> 144:ef7eb2e8f9f7 455 * @}
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /**
<> 144:ef7eb2e8f9f7 459 * @}
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @}
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * @}
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 471 }
<> 144:ef7eb2e8f9f7 472 #endif
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 #endif /* __STM32F0xx_HAL_PWR_EX_H */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 477